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1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 *
27 * Contributors:
28 * Niu Bing <bing.niu@intel.com>
29 * Zhi Wang <zhi.a.wang@intel.com>
30 *
31 */
32
33#ifndef _GVT_H_
34#define _GVT_H_
35
36#include "debug.h"
37#include "hypercall.h"
38#include "mmio.h"
39#include "reg.h"
40#include "interrupt.h"
41#include "gtt.h"
42#include "display.h"
43#include "edid.h"
44#include "execlist.h"
45#include "scheduler.h"
46#include "sched_policy.h"
47#include "mmio_context.h"
48#include "cmd_parser.h"
49#include "fb_decoder.h"
50#include "dmabuf.h"
51#include "page_track.h"
52
53#define GVT_MAX_VGPU 8
54
55struct intel_gvt_host {
56 struct device *dev;
57 bool initialized;
58 int hypervisor_type;
59 struct intel_gvt_mpt *mpt;
60};
61
62extern struct intel_gvt_host intel_gvt_host;
63
64/* Describe per-platform limitations. */
65struct intel_gvt_device_info {
66 u32 max_support_vgpus;
67 u32 cfg_space_size;
68 u32 mmio_size;
69 u32 mmio_bar;
70 unsigned long msi_cap_offset;
71 u32 gtt_start_offset;
72 u32 gtt_entry_size;
73 u32 gtt_entry_size_shift;
74 int gmadr_bytes_in_cmd;
75 u32 max_surface_size;
76};
77
78/* GM resources owned by a vGPU */
79struct intel_vgpu_gm {
80 u64 aperture_sz;
81 u64 hidden_sz;
82 struct drm_mm_node low_gm_node;
83 struct drm_mm_node high_gm_node;
84};
85
86#define INTEL_GVT_MAX_NUM_FENCES 32
87
88/* Fences owned by a vGPU */
89struct intel_vgpu_fence {
90 struct i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];
91 u32 base;
92 u32 size;
93};
94
95struct intel_vgpu_mmio {
96 void *vreg;
97};
98
99#define INTEL_GVT_MAX_BAR_NUM 4
100
101struct intel_vgpu_pci_bar {
102 u64 size;
103 bool tracked;
104};
105
106struct intel_vgpu_cfg_space {
107 unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE];
108 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
109 u32 pmcsr_off;
110};
111
112#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
113
114struct intel_vgpu_irq {
115 bool irq_warn_once[INTEL_GVT_EVENT_MAX];
116 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],
117 INTEL_GVT_EVENT_MAX);
118};
119
120struct intel_vgpu_opregion {
121 bool mapped;
122 void *va;
123 u32 gfn[INTEL_GVT_OPREGION_PAGES];
124};
125
126#define vgpu_opregion(vgpu) (&(vgpu->opregion))
127
128struct intel_vgpu_display {
129 struct intel_vgpu_i2c_edid i2c_edid;
130 struct intel_vgpu_port ports[I915_MAX_PORTS];
131 struct intel_vgpu_sbi sbi;
132};
133
134struct vgpu_sched_ctl {
135 int weight;
136};
137
138enum {
139 INTEL_VGPU_EXECLIST_SUBMISSION = 1,
140 INTEL_VGPU_GUC_SUBMISSION,
141};
142
143struct intel_vgpu_submission_ops {
144 const char *name;
145 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
146 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
147 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
148};
149
150struct intel_vgpu_submission {
151 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
152 struct list_head workload_q_head[I915_NUM_ENGINES];
153 struct intel_context *shadow[I915_NUM_ENGINES];
154 struct kmem_cache *workloads;
155 atomic_t running_workload_num;
156 union {
157 u64 i915_context_pml4;
158 u64 i915_context_pdps[GEN8_3LVL_PDPES];
159 };
160 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
161 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
162 void *ring_scan_buffer[I915_NUM_ENGINES];
163 int ring_scan_buffer_size[I915_NUM_ENGINES];
164 const struct intel_vgpu_submission_ops *ops;
165 int virtual_submission_interface;
166 bool active;
167 struct {
168 u32 lrca;
169 bool valid;
170 u64 ring_context_gpa;
171 } last_ctx[I915_NUM_ENGINES];
172};
173
174struct intel_vgpu {
175 struct intel_gvt *gvt;
176 struct mutex vgpu_lock;
177 int id;
178 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */
179 bool active;
180 bool pv_notified;
181 bool failsafe;
182 unsigned int resetting_eng;
183
184 /* Both sched_data and sched_ctl can be seen a part of the global gvt
185 * scheduler structure. So below 2 vgpu data are protected
186 * by sched_lock, not vgpu_lock.
187 */
188 void *sched_data;
189 struct vgpu_sched_ctl sched_ctl;
190
191 struct intel_vgpu_fence fence;
192 struct intel_vgpu_gm gm;
193 struct intel_vgpu_cfg_space cfg_space;
194 struct intel_vgpu_mmio mmio;
195 struct intel_vgpu_irq irq;
196 struct intel_vgpu_gtt gtt;
197 struct intel_vgpu_opregion opregion;
198 struct intel_vgpu_display display;
199 struct intel_vgpu_submission submission;
200 struct radix_tree_root page_track_tree;
201 u32 hws_pga[I915_NUM_ENGINES];
202 /* Set on PCI_D3, reset on DMLR, not reflecting the actual PM state */
203 bool d3_entered;
204
205 struct dentry *debugfs;
206
207 /* Hypervisor-specific device state. */
208 void *vdev;
209
210 struct list_head dmabuf_obj_list_head;
211 struct mutex dmabuf_lock;
212 struct idr object_idr;
213
214 u32 scan_nonprivbb;
215};
216
217static inline void *intel_vgpu_vdev(struct intel_vgpu *vgpu)
218{
219 return vgpu->vdev;
220}
221
222/* validating GM healthy status*/
223#define vgpu_is_vm_unhealthy(ret_val) \
224 (((ret_val) == -EBADRQC) || ((ret_val) == -EFAULT))
225
226struct intel_gvt_gm {
227 unsigned long vgpu_allocated_low_gm_size;
228 unsigned long vgpu_allocated_high_gm_size;
229};
230
231struct intel_gvt_fence {
232 unsigned long vgpu_allocated_fence_num;
233};
234
235/* Special MMIO blocks. */
236struct gvt_mmio_block {
237 unsigned int device;
238 i915_reg_t offset;
239 unsigned int size;
240 gvt_mmio_func read;
241 gvt_mmio_func write;
242};
243
244#define INTEL_GVT_MMIO_HASH_BITS 11
245
246struct intel_gvt_mmio {
247 u8 *mmio_attribute;
248/* Register contains RO bits */
249#define F_RO (1 << 0)
250/* Register contains graphics address */
251#define F_GMADR (1 << 1)
252/* Mode mask registers with high 16 bits as the mask bits */
253#define F_MODE_MASK (1 << 2)
254/* This reg can be accessed by GPU commands */
255#define F_CMD_ACCESS (1 << 3)
256/* This reg has been accessed by a VM */
257#define F_ACCESSED (1 << 4)
258/* This reg has been accessed through GPU commands */
259#define F_CMD_ACCESSED (1 << 5)
260/* This reg could be accessed by unaligned address */
261#define F_UNALIGN (1 << 6)
262/* This reg is saved/restored in context */
263#define F_IN_CTX (1 << 7)
264
265 struct gvt_mmio_block *mmio_block;
266 unsigned int num_mmio_block;
267
268 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
269 unsigned long num_tracked_mmio;
270};
271
272struct intel_gvt_firmware {
273 void *cfg_space;
274 void *mmio;
275 bool firmware_loaded;
276};
277
278#define NR_MAX_INTEL_VGPU_TYPES 20
279struct intel_vgpu_type {
280 char name[16];
281 unsigned int avail_instance;
282 unsigned int low_gm_size;
283 unsigned int high_gm_size;
284 unsigned int fence;
285 unsigned int weight;
286 enum intel_vgpu_edid resolution;
287};
288
289struct intel_gvt {
290 /* GVT scope lock, protect GVT itself, and all resource currently
291 * not yet protected by special locks(vgpu and scheduler lock).
292 */
293 struct mutex lock;
294 /* scheduler scope lock, protect gvt and vgpu schedule related data */
295 struct mutex sched_lock;
296
297 struct intel_gt *gt;
298 struct idr vgpu_idr; /* vGPU IDR pool */
299
300 struct intel_gvt_device_info device_info;
301 struct intel_gvt_gm gm;
302 struct intel_gvt_fence fence;
303 struct intel_gvt_mmio mmio;
304 struct intel_gvt_firmware firmware;
305 struct intel_gvt_irq irq;
306 struct intel_gvt_gtt gtt;
307 struct intel_gvt_workload_scheduler scheduler;
308 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES];
309 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS);
310 struct intel_vgpu_type *types;
311 unsigned int num_types;
312 struct intel_vgpu *idle_vgpu;
313
314 struct task_struct *service_thread;
315 wait_queue_head_t service_thread_wq;
316
317 /* service_request is always used in bit operation, we should always
318 * use it with atomic bit ops so that no need to use gvt big lock.
319 */
320 unsigned long service_request;
321
322 struct {
323 struct engine_mmio *mmio;
324 int ctx_mmio_count[I915_NUM_ENGINES];
325 u32 *tlb_mmio_offset_list;
326 u32 tlb_mmio_offset_list_cnt;
327 u32 *mocs_mmio_offset_list;
328 u32 mocs_mmio_offset_list_cnt;
329 } engine_mmio_list;
330
331 struct dentry *debugfs_root;
332};
333
334static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915)
335{
336 return i915->gvt;
337}
338
339enum {
340 INTEL_GVT_REQUEST_EMULATE_VBLANK = 0,
341
342 /* Scheduling trigger by timer */
343 INTEL_GVT_REQUEST_SCHED = 1,
344
345 /* Scheduling trigger by event */
346 INTEL_GVT_REQUEST_EVENT_SCHED = 2,
347};
348
349static inline void intel_gvt_request_service(struct intel_gvt *gvt,
350 int service)
351{
352 set_bit(service, (void *)&gvt->service_request);
353 wake_up(&gvt->service_thread_wq);
354}
355
356void intel_gvt_free_firmware(struct intel_gvt *gvt);
357int intel_gvt_load_firmware(struct intel_gvt *gvt);
358
359/* Aperture/GM space definitions for GVT device */
360#define MB_TO_BYTES(mb) ((mb) << 20ULL)
361#define BYTES_TO_MB(b) ((b) >> 20ULL)
362
363#define HOST_LOW_GM_SIZE MB_TO_BYTES(128)
364#define HOST_HIGH_GM_SIZE MB_TO_BYTES(384)
365#define HOST_FENCE 4
366
367#define gvt_to_ggtt(gvt) ((gvt)->gt->ggtt)
368
369/* Aperture/GM space definitions for GVT device */
370#define gvt_aperture_sz(gvt) gvt_to_ggtt(gvt)->mappable_end
371#define gvt_aperture_pa_base(gvt) gvt_to_ggtt(gvt)->gmadr.start
372
373#define gvt_ggtt_gm_sz(gvt) gvt_to_ggtt(gvt)->vm.total
374#define gvt_ggtt_sz(gvt) (gvt_to_ggtt(gvt)->vm.total >> PAGE_SHIFT << 3)
375#define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))
376
377#define gvt_aperture_gmadr_base(gvt) (0)
378#define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \
379 + gvt_aperture_sz(gvt) - 1)
380
381#define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \
382 + gvt_aperture_sz(gvt))
383#define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \
384 + gvt_hidden_sz(gvt) - 1)
385
386#define gvt_fence_sz(gvt) (gvt_to_ggtt(gvt)->num_fences)
387
388/* Aperture/GM space definitions for vGPU */
389#define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start)
390#define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start)
391#define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz)
392#define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz)
393
394#define vgpu_aperture_pa_base(vgpu) \
395 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))
396
397#define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz)
398
399#define vgpu_aperture_pa_end(vgpu) \
400 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
401
402#define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu))
403#define vgpu_aperture_gmadr_end(vgpu) \
404 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
405
406#define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu))
407#define vgpu_hidden_gmadr_end(vgpu) \
408 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
409
410#define vgpu_fence_base(vgpu) (vgpu->fence.base)
411#define vgpu_fence_sz(vgpu) (vgpu->fence.size)
412
413struct intel_vgpu_creation_params {
414 __u64 handle;
415 __u64 low_gm_sz; /* in MB */
416 __u64 high_gm_sz; /* in MB */
417 __u64 fence_sz;
418 __u64 resolution;
419 __s32 primary;
420 __u64 vgpu_id;
421
422 __u32 weight;
423};
424
425int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
426 struct intel_vgpu_creation_params *param);
427void intel_vgpu_reset_resource(struct intel_vgpu *vgpu);
428void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
429void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
430 u32 fence, u64 value);
431
432/* Macros for easily accessing vGPU virtual/shadow register.
433 Explicitly seperate use for typed MMIO reg or real offset.*/
434#define vgpu_vreg_t(vgpu, reg) \
435 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
436#define vgpu_vreg(vgpu, offset) \
437 (*(u32 *)(vgpu->mmio.vreg + (offset)))
438#define vgpu_vreg64_t(vgpu, reg) \
439 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
440#define vgpu_vreg64(vgpu, offset) \
441 (*(u64 *)(vgpu->mmio.vreg + (offset)))
442
443#define for_each_active_vgpu(gvt, vgpu, id) \
444 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
445 for_each_if(vgpu->active)
446
447static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,
448 u32 offset, u32 val, bool low)
449{
450 u32 *pval;
451
452 /* BAR offset should be 32 bits algiend */
453 offset = rounddown(offset, 4);
454 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
455
456 if (low) {
457 /*
458 * only update bit 31 - bit 4,
459 * leave the bit 3 - bit 0 unchanged.
460 */
461 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
462 } else {
463 *pval = val;
464 }
465}
466
467int intel_gvt_init_vgpu_types(struct intel_gvt *gvt);
468void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt);
469
470struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt);
471void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu);
472struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
473 struct intel_vgpu_type *type);
474void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu);
475void intel_gvt_release_vgpu(struct intel_vgpu *vgpu);
476void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
477 intel_engine_mask_t engine_mask);
478void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu);
479void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu);
480void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu);
481
482/* validating GM functions */
483#define vgpu_gmadr_is_aperture(vgpu, gmadr) \
484 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \
485 (gmadr <= vgpu_aperture_gmadr_end(vgpu)))
486
487#define vgpu_gmadr_is_hidden(vgpu, gmadr) \
488 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \
489 (gmadr <= vgpu_hidden_gmadr_end(vgpu)))
490
491#define vgpu_gmadr_is_valid(vgpu, gmadr) \
492 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \
493 (vgpu_gmadr_is_hidden(vgpu, gmadr))))
494
495#define gvt_gmadr_is_aperture(gvt, gmadr) \
496 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \
497 (gmadr <= gvt_aperture_gmadr_end(gvt)))
498
499#define gvt_gmadr_is_hidden(gvt, gmadr) \
500 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \
501 (gmadr <= gvt_hidden_gmadr_end(gvt)))
502
503#define gvt_gmadr_is_valid(gvt, gmadr) \
504 (gvt_gmadr_is_aperture(gvt, gmadr) || \
505 gvt_gmadr_is_hidden(gvt, gmadr))
506
507bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);
508int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr);
509int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr);
510int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
511 unsigned long *h_index);
512int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
513 unsigned long *g_index);
514
515void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
516 bool primary);
517void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu);
518
519int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
520 void *p_data, unsigned int bytes);
521
522int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
523 void *p_data, unsigned int bytes);
524
525void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected);
526
527static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar)
528{
529 /* We are 64bit bar. */
530 return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &
531 PCI_BASE_ADDRESS_MEM_MASK;
532}
533
534void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu);
535int intel_vgpu_init_opregion(struct intel_vgpu *vgpu);
536int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa);
537
538int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci);
539void populate_pvinfo_page(struct intel_vgpu *vgpu);
540
541int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload);
542void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason);
543
544struct intel_gvt_ops {
545 int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *,
546 unsigned int);
547 int (*emulate_cfg_write)(struct intel_vgpu *, unsigned int, void *,
548 unsigned int);
549 int (*emulate_mmio_read)(struct intel_vgpu *, u64, void *,
550 unsigned int);
551 int (*emulate_mmio_write)(struct intel_vgpu *, u64, void *,
552 unsigned int);
553 struct intel_vgpu *(*vgpu_create)(struct intel_gvt *,
554 struct intel_vgpu_type *);
555 void (*vgpu_destroy)(struct intel_vgpu *vgpu);
556 void (*vgpu_release)(struct intel_vgpu *vgpu);
557 void (*vgpu_reset)(struct intel_vgpu *);
558 void (*vgpu_activate)(struct intel_vgpu *);
559 void (*vgpu_deactivate)(struct intel_vgpu *);
560 struct intel_vgpu_type *(*gvt_find_vgpu_type)(struct intel_gvt *gvt,
561 const char *name);
562 bool (*get_gvt_attrs)(struct attribute_group ***intel_vgpu_type_groups);
563 int (*vgpu_query_plane)(struct intel_vgpu *vgpu, void *);
564 int (*vgpu_get_dmabuf)(struct intel_vgpu *vgpu, unsigned int);
565 int (*write_protect_handler)(struct intel_vgpu *, u64, void *,
566 unsigned int);
567 void (*emulate_hotplug)(struct intel_vgpu *vgpu, bool connected);
568};
569
570
571enum {
572 GVT_FAILSAFE_UNSUPPORTED_GUEST,
573 GVT_FAILSAFE_INSUFFICIENT_RESOURCE,
574 GVT_FAILSAFE_GUEST_ERR,
575};
576
577static inline void mmio_hw_access_pre(struct intel_gt *gt)
578{
579 intel_runtime_pm_get(gt->uncore->rpm);
580}
581
582static inline void mmio_hw_access_post(struct intel_gt *gt)
583{
584 intel_runtime_pm_put_unchecked(gt->uncore->rpm);
585}
586
587/**
588 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed
589 * @gvt: a GVT device
590 * @offset: register offset
591 *
592 */
593static inline void intel_gvt_mmio_set_accessed(
594 struct intel_gvt *gvt, unsigned int offset)
595{
596 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED;
597}
598
599/**
600 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command
601 * @gvt: a GVT device
602 * @offset: register offset
603 *
604 */
605static inline bool intel_gvt_mmio_is_cmd_access(
606 struct intel_gvt *gvt, unsigned int offset)
607{
608 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS;
609}
610
611/**
612 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned
613 * @gvt: a GVT device
614 * @offset: register offset
615 *
616 */
617static inline bool intel_gvt_mmio_is_unalign(
618 struct intel_gvt *gvt, unsigned int offset)
619{
620 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN;
621}
622
623/**
624 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command
625 * @gvt: a GVT device
626 * @offset: register offset
627 *
628 */
629static inline void intel_gvt_mmio_set_cmd_accessed(
630 struct intel_gvt *gvt, unsigned int offset)
631{
632 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESSED;
633}
634
635/**
636 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask
637 * @gvt: a GVT device
638 * @offset: register offset
639 *
640 * Returns:
641 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't.
642 *
643 */
644static inline bool intel_gvt_mmio_has_mode_mask(
645 struct intel_gvt *gvt, unsigned int offset)
646{
647 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK;
648}
649
650/**
651 * intel_gvt_mmio_is_in_ctx - check if a MMIO has in-ctx mask
652 * @gvt: a GVT device
653 * @offset: register offset
654 *
655 * Returns:
656 * True if a MMIO has a in-context mask, false if it isn't.
657 *
658 */
659static inline bool intel_gvt_mmio_is_in_ctx(
660 struct intel_gvt *gvt, unsigned int offset)
661{
662 return gvt->mmio.mmio_attribute[offset >> 2] & F_IN_CTX;
663}
664
665/**
666 * intel_gvt_mmio_set_in_ctx - mask a MMIO in logical context
667 * @gvt: a GVT device
668 * @offset: register offset
669 *
670 */
671static inline void intel_gvt_mmio_set_in_ctx(
672 struct intel_gvt *gvt, unsigned int offset)
673{
674 gvt->mmio.mmio_attribute[offset >> 2] |= F_IN_CTX;
675}
676
677void intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu);
678void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu);
679void intel_gvt_debugfs_init(struct intel_gvt *gvt);
680void intel_gvt_debugfs_clean(struct intel_gvt *gvt);
681
682
683#include "trace.h"
684#include "mpt.h"
685
686#endif