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1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 *
27 * Contributors:
28 * Niu Bing <bing.niu@intel.com>
29 * Zhi Wang <zhi.a.wang@intel.com>
30 *
31 */
32
33#ifndef _GVT_H_
34#define _GVT_H_
35
36#include "debug.h"
37#include "hypercall.h"
38#include "mmio.h"
39#include "reg.h"
40#include "interrupt.h"
41#include "gtt.h"
42#include "display.h"
43#include "edid.h"
44#include "execlist.h"
45#include "scheduler.h"
46#include "sched_policy.h"
47#include "render.h"
48#include "cmd_parser.h"
49
50#define GVT_MAX_VGPU 8
51
52enum {
53 INTEL_GVT_HYPERVISOR_XEN = 0,
54 INTEL_GVT_HYPERVISOR_KVM,
55};
56
57struct intel_gvt_host {
58 bool initialized;
59 int hypervisor_type;
60 struct intel_gvt_mpt *mpt;
61};
62
63extern struct intel_gvt_host intel_gvt_host;
64
65/* Describe per-platform limitations. */
66struct intel_gvt_device_info {
67 u32 max_support_vgpus;
68 u32 cfg_space_size;
69 u32 mmio_size;
70 u32 mmio_bar;
71 unsigned long msi_cap_offset;
72 u32 gtt_start_offset;
73 u32 gtt_entry_size;
74 u32 gtt_entry_size_shift;
75 int gmadr_bytes_in_cmd;
76 u32 max_surface_size;
77};
78
79/* GM resources owned by a vGPU */
80struct intel_vgpu_gm {
81 u64 aperture_sz;
82 u64 hidden_sz;
83 struct drm_mm_node low_gm_node;
84 struct drm_mm_node high_gm_node;
85};
86
87#define INTEL_GVT_MAX_NUM_FENCES 32
88
89/* Fences owned by a vGPU */
90struct intel_vgpu_fence {
91 struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];
92 u32 base;
93 u32 size;
94};
95
96struct intel_vgpu_mmio {
97 void *vreg;
98 void *sreg;
99 bool disable_warn_untrack;
100};
101
102#define INTEL_GVT_MAX_CFG_SPACE_SZ 256
103#define INTEL_GVT_MAX_BAR_NUM 4
104
105struct intel_vgpu_pci_bar {
106 u64 size;
107 bool tracked;
108};
109
110struct intel_vgpu_cfg_space {
111 unsigned char virtual_cfg_space[INTEL_GVT_MAX_CFG_SPACE_SZ];
112 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
113};
114
115#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
116
117#define INTEL_GVT_MAX_PIPE 4
118
119struct intel_vgpu_irq {
120 bool irq_warn_once[INTEL_GVT_EVENT_MAX];
121 DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE],
122 INTEL_GVT_EVENT_MAX);
123};
124
125struct intel_vgpu_opregion {
126 void *va;
127 u32 gfn[INTEL_GVT_OPREGION_PAGES];
128 struct page *pages[INTEL_GVT_OPREGION_PAGES];
129};
130
131#define vgpu_opregion(vgpu) (&(vgpu->opregion))
132
133#define INTEL_GVT_MAX_PORT 5
134
135struct intel_vgpu_display {
136 struct intel_vgpu_i2c_edid i2c_edid;
137 struct intel_vgpu_port ports[INTEL_GVT_MAX_PORT];
138 struct intel_vgpu_sbi sbi;
139};
140
141struct intel_vgpu {
142 struct intel_gvt *gvt;
143 int id;
144 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */
145 bool active;
146 bool resetting;
147 void *sched_data;
148
149 struct intel_vgpu_fence fence;
150 struct intel_vgpu_gm gm;
151 struct intel_vgpu_cfg_space cfg_space;
152 struct intel_vgpu_mmio mmio;
153 struct intel_vgpu_irq irq;
154 struct intel_vgpu_gtt gtt;
155 struct intel_vgpu_opregion opregion;
156 struct intel_vgpu_display display;
157 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
158 struct list_head workload_q_head[I915_NUM_ENGINES];
159 struct kmem_cache *workloads;
160 atomic_t running_workload_num;
161 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
162 struct i915_gem_context *shadow_ctx;
163 struct notifier_block shadow_ctx_notifier_block;
164
165#if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT)
166 struct {
167 struct mdev_device *mdev;
168 struct vfio_region *region;
169 int num_regions;
170 struct eventfd_ctx *intx_trigger;
171 struct eventfd_ctx *msi_trigger;
172 struct rb_root cache;
173 struct mutex cache_lock;
174 struct notifier_block iommu_notifier;
175 struct notifier_block group_notifier;
176 struct kvm *kvm;
177 struct work_struct release_work;
178 atomic_t released;
179 } vdev;
180#endif
181};
182
183struct intel_gvt_gm {
184 unsigned long vgpu_allocated_low_gm_size;
185 unsigned long vgpu_allocated_high_gm_size;
186};
187
188struct intel_gvt_fence {
189 unsigned long vgpu_allocated_fence_num;
190};
191
192#define INTEL_GVT_MMIO_HASH_BITS 9
193
194struct intel_gvt_mmio {
195 u32 *mmio_attribute;
196 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
197};
198
199struct intel_gvt_firmware {
200 void *cfg_space;
201 void *mmio;
202 bool firmware_loaded;
203};
204
205struct intel_gvt_opregion {
206 void __iomem *opregion_va;
207 u32 opregion_pa;
208};
209
210#define NR_MAX_INTEL_VGPU_TYPES 20
211struct intel_vgpu_type {
212 char name[16];
213 unsigned int max_instance;
214 unsigned int avail_instance;
215 unsigned int low_gm_size;
216 unsigned int high_gm_size;
217 unsigned int fence;
218};
219
220struct intel_gvt {
221 struct mutex lock;
222 struct drm_i915_private *dev_priv;
223 struct idr vgpu_idr; /* vGPU IDR pool */
224
225 struct intel_gvt_device_info device_info;
226 struct intel_gvt_gm gm;
227 struct intel_gvt_fence fence;
228 struct intel_gvt_mmio mmio;
229 struct intel_gvt_firmware firmware;
230 struct intel_gvt_irq irq;
231 struct intel_gvt_gtt gtt;
232 struct intel_gvt_opregion opregion;
233 struct intel_gvt_workload_scheduler scheduler;
234 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS);
235 struct intel_vgpu_type *types;
236 unsigned int num_types;
237
238 struct task_struct *service_thread;
239 wait_queue_head_t service_thread_wq;
240 unsigned long service_request;
241};
242
243static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915)
244{
245 return i915->gvt;
246}
247
248enum {
249 INTEL_GVT_REQUEST_EMULATE_VBLANK = 0,
250};
251
252static inline void intel_gvt_request_service(struct intel_gvt *gvt,
253 int service)
254{
255 set_bit(service, (void *)&gvt->service_request);
256 wake_up(&gvt->service_thread_wq);
257}
258
259void intel_gvt_free_firmware(struct intel_gvt *gvt);
260int intel_gvt_load_firmware(struct intel_gvt *gvt);
261
262/* Aperture/GM space definitions for GVT device */
263#define MB_TO_BYTES(mb) ((mb) << 20ULL)
264#define BYTES_TO_MB(b) ((b) >> 20ULL)
265
266#define HOST_LOW_GM_SIZE MB_TO_BYTES(128)
267#define HOST_HIGH_GM_SIZE MB_TO_BYTES(384)
268#define HOST_FENCE 4
269
270/* Aperture/GM space definitions for GVT device */
271#define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end)
272#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base)
273
274#define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total)
275#define gvt_ggtt_sz(gvt) \
276 ((gvt->dev_priv->ggtt.base.total >> PAGE_SHIFT) << 3)
277#define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))
278
279#define gvt_aperture_gmadr_base(gvt) (0)
280#define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \
281 + gvt_aperture_sz(gvt) - 1)
282
283#define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \
284 + gvt_aperture_sz(gvt))
285#define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \
286 + gvt_hidden_sz(gvt) - 1)
287
288#define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs)
289
290/* Aperture/GM space definitions for vGPU */
291#define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start)
292#define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start)
293#define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz)
294#define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz)
295
296#define vgpu_aperture_pa_base(vgpu) \
297 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))
298
299#define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz)
300
301#define vgpu_aperture_pa_end(vgpu) \
302 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
303
304#define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu))
305#define vgpu_aperture_gmadr_end(vgpu) \
306 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
307
308#define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu))
309#define vgpu_hidden_gmadr_end(vgpu) \
310 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
311
312#define vgpu_fence_base(vgpu) (vgpu->fence.base)
313#define vgpu_fence_sz(vgpu) (vgpu->fence.size)
314
315struct intel_vgpu_creation_params {
316 __u64 handle;
317 __u64 low_gm_sz; /* in MB */
318 __u64 high_gm_sz; /* in MB */
319 __u64 fence_sz;
320 __s32 primary;
321 __u64 vgpu_id;
322};
323
324int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
325 struct intel_vgpu_creation_params *param);
326void intel_vgpu_reset_resource(struct intel_vgpu *vgpu);
327void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
328void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
329 u32 fence, u64 value);
330
331/* Macros for easily accessing vGPU virtual/shadow register */
332#define vgpu_vreg(vgpu, reg) \
333 (*(u32 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
334#define vgpu_vreg8(vgpu, reg) \
335 (*(u8 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
336#define vgpu_vreg16(vgpu, reg) \
337 (*(u16 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
338#define vgpu_vreg64(vgpu, reg) \
339 (*(u64 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
340#define vgpu_sreg(vgpu, reg) \
341 (*(u32 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
342#define vgpu_sreg8(vgpu, reg) \
343 (*(u8 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
344#define vgpu_sreg16(vgpu, reg) \
345 (*(u16 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
346#define vgpu_sreg64(vgpu, reg) \
347 (*(u64 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
348
349#define for_each_active_vgpu(gvt, vgpu, id) \
350 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
351 for_each_if(vgpu->active)
352
353static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,
354 u32 offset, u32 val, bool low)
355{
356 u32 *pval;
357
358 /* BAR offset should be 32 bits algiend */
359 offset = rounddown(offset, 4);
360 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
361
362 if (low) {
363 /*
364 * only update bit 31 - bit 4,
365 * leave the bit 3 - bit 0 unchanged.
366 */
367 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
368 } else {
369 *pval = val;
370 }
371}
372
373int intel_gvt_init_vgpu_types(struct intel_gvt *gvt);
374void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt);
375
376struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
377 struct intel_vgpu_type *type);
378void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu);
379void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
380 unsigned int engine_mask);
381void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu);
382
383
384/* validating GM functions */
385#define vgpu_gmadr_is_aperture(vgpu, gmadr) \
386 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \
387 (gmadr <= vgpu_aperture_gmadr_end(vgpu)))
388
389#define vgpu_gmadr_is_hidden(vgpu, gmadr) \
390 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \
391 (gmadr <= vgpu_hidden_gmadr_end(vgpu)))
392
393#define vgpu_gmadr_is_valid(vgpu, gmadr) \
394 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \
395 (vgpu_gmadr_is_hidden(vgpu, gmadr))))
396
397#define gvt_gmadr_is_aperture(gvt, gmadr) \
398 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \
399 (gmadr <= gvt_aperture_gmadr_end(gvt)))
400
401#define gvt_gmadr_is_hidden(gvt, gmadr) \
402 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \
403 (gmadr <= gvt_hidden_gmadr_end(gvt)))
404
405#define gvt_gmadr_is_valid(gvt, gmadr) \
406 (gvt_gmadr_is_aperture(gvt, gmadr) || \
407 gvt_gmadr_is_hidden(gvt, gmadr))
408
409bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);
410int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr);
411int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr);
412int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
413 unsigned long *h_index);
414int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
415 unsigned long *g_index);
416
417void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
418 bool primary);
419void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu);
420
421int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
422 void *p_data, unsigned int bytes);
423
424int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
425 void *p_data, unsigned int bytes);
426
427void intel_gvt_clean_opregion(struct intel_gvt *gvt);
428int intel_gvt_init_opregion(struct intel_gvt *gvt);
429
430void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu);
431int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa);
432
433int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci);
434void populate_pvinfo_page(struct intel_vgpu *vgpu);
435
436struct intel_gvt_ops {
437 int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *,
438 unsigned int);
439 int (*emulate_cfg_write)(struct intel_vgpu *, unsigned int, void *,
440 unsigned int);
441 int (*emulate_mmio_read)(struct intel_vgpu *, u64, void *,
442 unsigned int);
443 int (*emulate_mmio_write)(struct intel_vgpu *, u64, void *,
444 unsigned int);
445 struct intel_vgpu *(*vgpu_create)(struct intel_gvt *,
446 struct intel_vgpu_type *);
447 void (*vgpu_destroy)(struct intel_vgpu *);
448 void (*vgpu_reset)(struct intel_vgpu *);
449};
450
451
452#include "mpt.h"
453
454#endif