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1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Ke Yu
25 * Zhiyuan Lv <zhiyuan.lv@intel.com>
26 *
27 * Contributors:
28 * Terrence Xu <terrence.xu@intel.com>
29 * Changbin Du <changbin.du@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 * Zhi Wang <zhi.a.wang@intel.com>
32 *
33 */
34
35#include "display/intel_gmbus_regs.h"
36#include "gvt.h"
37#include "i915_drv.h"
38#include "i915_reg.h"
39
40#define GMBUS1_TOTAL_BYTES_SHIFT 16
41#define GMBUS1_TOTAL_BYTES_MASK 0x1ff
42#define gmbus1_total_byte_count(v) (((v) >> \
43 GMBUS1_TOTAL_BYTES_SHIFT) & GMBUS1_TOTAL_BYTES_MASK)
44#define gmbus1_slave_addr(v) (((v) & 0xff) >> 1)
45#define gmbus1_slave_index(v) (((v) >> 8) & 0xff)
46#define gmbus1_bus_cycle(v) (((v) >> 25) & 0x7)
47
48/* GMBUS0 bits definitions */
49#define _GMBUS_PIN_SEL_MASK (0x7)
50
51static unsigned char edid_get_byte(struct intel_vgpu *vgpu)
52{
53 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
54 unsigned char chr = 0;
55
56 if (edid->state == I2C_NOT_SPECIFIED || !edid->slave_selected) {
57 gvt_vgpu_err("Driver tries to read EDID without proper sequence!\n");
58 return 0;
59 }
60 if (edid->current_edid_read >= EDID_SIZE) {
61 gvt_vgpu_err("edid_get_byte() exceeds the size of EDID!\n");
62 return 0;
63 }
64
65 if (!edid->edid_available) {
66 gvt_vgpu_err("Reading EDID but EDID is not available!\n");
67 return 0;
68 }
69
70 if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) {
71 struct intel_vgpu_edid_data *edid_data =
72 intel_vgpu_port(vgpu, edid->port)->edid;
73
74 chr = edid_data->edid_block[edid->current_edid_read];
75 edid->current_edid_read++;
76 } else {
77 gvt_vgpu_err("No EDID available during the reading?\n");
78 }
79 return chr;
80}
81
82static inline int cnp_get_port_from_gmbus0(u32 gmbus0)
83{
84 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
85 int port = -EINVAL;
86
87 if (port_select == GMBUS_PIN_1_BXT)
88 port = PORT_B;
89 else if (port_select == GMBUS_PIN_2_BXT)
90 port = PORT_C;
91 else if (port_select == GMBUS_PIN_3_BXT)
92 port = PORT_D;
93 else if (port_select == GMBUS_PIN_4_CNP)
94 port = PORT_E;
95 return port;
96}
97
98static inline int bxt_get_port_from_gmbus0(u32 gmbus0)
99{
100 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
101 int port = -EINVAL;
102
103 if (port_select == GMBUS_PIN_1_BXT)
104 port = PORT_B;
105 else if (port_select == GMBUS_PIN_2_BXT)
106 port = PORT_C;
107 else if (port_select == GMBUS_PIN_3_BXT)
108 port = PORT_D;
109 return port;
110}
111
112static inline int get_port_from_gmbus0(u32 gmbus0)
113{
114 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
115 int port = -EINVAL;
116
117 if (port_select == GMBUS_PIN_VGADDC)
118 port = PORT_E;
119 else if (port_select == GMBUS_PIN_DPC)
120 port = PORT_C;
121 else if (port_select == GMBUS_PIN_DPB)
122 port = PORT_B;
123 else if (port_select == GMBUS_PIN_DPD)
124 port = PORT_D;
125 return port;
126}
127
128static void reset_gmbus_controller(struct intel_vgpu *vgpu)
129{
130 vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;
131 if (!vgpu->display.i2c_edid.edid_available)
132 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
133 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
134}
135
136/* GMBUS0 */
137static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
138 unsigned int offset, void *p_data, unsigned int bytes)
139{
140 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
141 int port, pin_select;
142
143 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
144
145 pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK;
146
147 intel_vgpu_init_i2c_edid(vgpu);
148
149 if (pin_select == 0)
150 return 0;
151
152 if (IS_BROXTON(i915))
153 port = bxt_get_port_from_gmbus0(pin_select);
154 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
155 port = cnp_get_port_from_gmbus0(pin_select);
156 else
157 port = get_port_from_gmbus0(pin_select);
158 if (drm_WARN_ON(&i915->drm, port < 0))
159 return 0;
160
161 vgpu->display.i2c_edid.state = I2C_GMBUS;
162 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
163
164 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
165 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
166
167 if (intel_vgpu_has_monitor_on_port(vgpu, port) &&
168 !intel_vgpu_port_is_dp(vgpu, port)) {
169 vgpu->display.i2c_edid.port = port;
170 vgpu->display.i2c_edid.edid_available = true;
171 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;
172 } else
173 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
174 return 0;
175}
176
177static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
178 void *p_data, unsigned int bytes)
179{
180 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
181 u32 slave_addr;
182 u32 wvalue = *(u32 *)p_data;
183
184 if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) {
185 if (!(wvalue & GMBUS_SW_CLR_INT)) {
186 vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT;
187 reset_gmbus_controller(vgpu);
188 }
189 /*
190 * TODO: "This bit is cleared to zero when an event
191 * causes the HW_RDY bit transition to occur "
192 */
193 } else {
194 /*
195 * per bspec setting this bit can cause:
196 * 1) INT status bit cleared
197 * 2) HW_RDY bit asserted
198 */
199 if (wvalue & GMBUS_SW_CLR_INT) {
200 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;
201 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;
202 }
203
204 /* For virtualization, we suppose that HW is always ready,
205 * so GMBUS_SW_RDY should always be cleared
206 */
207 if (wvalue & GMBUS_SW_RDY)
208 wvalue &= ~GMBUS_SW_RDY;
209
210 i2c_edid->gmbus.total_byte_count =
211 gmbus1_total_byte_count(wvalue);
212 slave_addr = gmbus1_slave_addr(wvalue);
213
214 /* vgpu gmbus only support EDID */
215 if (slave_addr == EDID_ADDR) {
216 i2c_edid->slave_selected = true;
217 } else if (slave_addr != 0) {
218 gvt_dbg_dpy(
219 "vgpu%d: unsupported gmbus slave addr(0x%x)\n"
220 " gmbus operations will be ignored.\n",
221 vgpu->id, slave_addr);
222 }
223
224 if (wvalue & GMBUS_CYCLE_INDEX)
225 i2c_edid->current_edid_read =
226 gmbus1_slave_index(wvalue);
227
228 i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue);
229 switch (gmbus1_bus_cycle(wvalue)) {
230 case GMBUS_NOCYCLE:
231 break;
232 case GMBUS_STOP:
233 /* From spec:
234 * This can only cause a STOP to be generated
235 * if a GMBUS cycle is generated, the GMBUS is
236 * currently in a data/wait/idle phase, or it is in a
237 * WAIT phase
238 */
239 if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset))
240 != GMBUS_NOCYCLE) {
241 intel_vgpu_init_i2c_edid(vgpu);
242 /* After the 'stop' cycle, hw state would become
243 * 'stop phase' and then 'idle phase' after a
244 * few milliseconds. In emulation, we just set
245 * it as 'idle phase' ('stop phase' is not
246 * visible in gmbus interface)
247 */
248 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
249 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
250 }
251 break;
252 case NIDX_NS_W:
253 case IDX_NS_W:
254 case NIDX_STOP:
255 case IDX_STOP:
256 /* From hw spec the GMBUS phase
257 * transition like this:
258 * START (-->INDEX) -->DATA
259 */
260 i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;
261 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;
262 break;
263 default:
264 gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n");
265 break;
266 }
267 /*
268 * From hw spec the WAIT state will be
269 * cleared:
270 * (1) in a new GMBUS cycle
271 * (2) by generating a stop
272 */
273 vgpu_vreg(vgpu, offset) = wvalue;
274 }
275 return 0;
276}
277
278static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
279 void *p_data, unsigned int bytes)
280{
281 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
282
283 drm_WARN_ON(&i915->drm, 1);
284 return 0;
285}
286
287static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
288 void *p_data, unsigned int bytes)
289{
290 int i;
291 unsigned char byte_data;
292 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
293 int byte_left = i2c_edid->gmbus.total_byte_count -
294 i2c_edid->current_edid_read;
295 int byte_count = byte_left;
296 u32 reg_data = 0;
297
298 /* Data can only be recevied if previous settings correct */
299 if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {
300 if (byte_left <= 0) {
301 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
302 return 0;
303 }
304
305 if (byte_count > 4)
306 byte_count = 4;
307 for (i = 0; i < byte_count; i++) {
308 byte_data = edid_get_byte(vgpu);
309 reg_data |= (byte_data << (i << 3));
310 }
311
312 memcpy(&vgpu_vreg(vgpu, offset), ®_data, byte_count);
313 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
314
315 if (byte_left <= 4) {
316 switch (i2c_edid->gmbus.cycle_type) {
317 case NIDX_STOP:
318 case IDX_STOP:
319 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
320 break;
321 case NIDX_NS_W:
322 case IDX_NS_W:
323 default:
324 i2c_edid->gmbus.phase = GMBUS_WAIT_PHASE;
325 break;
326 }
327 intel_vgpu_init_i2c_edid(vgpu);
328 }
329 /*
330 * Read GMBUS3 during send operation,
331 * return the latest written value
332 */
333 } else {
334 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
335 gvt_vgpu_err("warning: gmbus3 read with nothing returned\n");
336 }
337 return 0;
338}
339
340static int gmbus2_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
341 void *p_data, unsigned int bytes)
342{
343 u32 value = vgpu_vreg(vgpu, offset);
344
345 if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE))
346 vgpu_vreg(vgpu, offset) |= GMBUS_INUSE;
347 memcpy(p_data, (void *)&value, bytes);
348 return 0;
349}
350
351static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
352 void *p_data, unsigned int bytes)
353{
354 u32 wvalue = *(u32 *)p_data;
355
356 if (wvalue & GMBUS_INUSE)
357 vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE;
358 /* All other bits are read-only */
359 return 0;
360}
361
362/**
363 * intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read
364 * @vgpu: a vGPU
365 * @offset: reg offset
366 * @p_data: data return buffer
367 * @bytes: access data length
368 *
369 * This function is used to emulate gmbus register mmio read
370 *
371 * Returns:
372 * Zero on success, negative error code if failed.
373 *
374 */
375int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
376 unsigned int offset, void *p_data, unsigned int bytes)
377{
378 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
379
380 if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
381 return -EINVAL;
382
383 if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
384 return gmbus2_mmio_read(vgpu, offset, p_data, bytes);
385 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
386 return gmbus3_mmio_read(vgpu, offset, p_data, bytes);
387
388 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
389 return 0;
390}
391
392/**
393 * intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write
394 * @vgpu: a vGPU
395 * @offset: reg offset
396 * @p_data: data return buffer
397 * @bytes: access data length
398 *
399 * This function is used to emulate gmbus register mmio write
400 *
401 * Returns:
402 * Zero on success, negative error code if failed.
403 *
404 */
405int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
406 unsigned int offset, void *p_data, unsigned int bytes)
407{
408 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
409
410 if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
411 return -EINVAL;
412
413 if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
414 return gmbus0_mmio_write(vgpu, offset, p_data, bytes);
415 else if (offset == i915_mmio_reg_offset(PCH_GMBUS1))
416 return gmbus1_mmio_write(vgpu, offset, p_data, bytes);
417 else if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
418 return gmbus2_mmio_write(vgpu, offset, p_data, bytes);
419 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
420 return gmbus3_mmio_write(vgpu, offset, p_data, bytes);
421
422 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
423 return 0;
424}
425
426enum {
427 AUX_CH_CTL = 0,
428 AUX_CH_DATA1,
429 AUX_CH_DATA2,
430 AUX_CH_DATA3,
431 AUX_CH_DATA4,
432 AUX_CH_DATA5
433};
434
435static inline int get_aux_ch_reg(unsigned int offset)
436{
437 int reg;
438
439 switch (offset & 0xff) {
440 case 0x10:
441 reg = AUX_CH_CTL;
442 break;
443 case 0x14:
444 reg = AUX_CH_DATA1;
445 break;
446 case 0x18:
447 reg = AUX_CH_DATA2;
448 break;
449 case 0x1c:
450 reg = AUX_CH_DATA3;
451 break;
452 case 0x20:
453 reg = AUX_CH_DATA4;
454 break;
455 case 0x24:
456 reg = AUX_CH_DATA5;
457 break;
458 default:
459 reg = -1;
460 break;
461 }
462 return reg;
463}
464
465#define AUX_CTL_MSG_LENGTH(reg) \
466 ((reg & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> \
467 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT)
468
469/**
470 * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
471 * @vgpu: a vGPU
472 * @port_idx: port index
473 * @offset: reg offset
474 * @p_data: write ptr
475 *
476 * This function is used to emulate AUX channel register write
477 *
478 */
479void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
480 int port_idx,
481 unsigned int offset,
482 void *p_data)
483{
484 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
485 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
486 int msg_length, ret_msg_size;
487 int msg, addr, ctrl, op;
488 u32 value = *(u32 *)p_data;
489 int aux_data_for_write = 0;
490 int reg = get_aux_ch_reg(offset);
491
492 if (reg != AUX_CH_CTL) {
493 vgpu_vreg(vgpu, offset) = value;
494 return;
495 }
496
497 msg_length = AUX_CTL_MSG_LENGTH(value);
498 // check the msg in DATA register.
499 msg = vgpu_vreg(vgpu, offset + 4);
500 addr = (msg >> 8) & 0xffff;
501 ctrl = (msg >> 24) & 0xff;
502 op = ctrl >> 4;
503 if (!(value & DP_AUX_CH_CTL_SEND_BUSY)) {
504 /* The ctl write to clear some states */
505 return;
506 }
507
508 /* Always set the wanted value for vms. */
509 ret_msg_size = (((op & 0x1) == GVT_AUX_I2C_READ) ? 2 : 1);
510 vgpu_vreg(vgpu, offset) =
511 DP_AUX_CH_CTL_DONE |
512 ((ret_msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) &
513 DP_AUX_CH_CTL_MESSAGE_SIZE_MASK);
514
515 if (msg_length == 3) {
516 if (!(op & GVT_AUX_I2C_MOT)) {
517 /* stop */
518 intel_vgpu_init_i2c_edid(vgpu);
519 } else {
520 /* start or restart */
521 i2c_edid->aux_ch.i2c_over_aux_ch = true;
522 i2c_edid->aux_ch.aux_ch_mot = true;
523 if (addr == 0) {
524 /* reset the address */
525 intel_vgpu_init_i2c_edid(vgpu);
526 } else if (addr == EDID_ADDR) {
527 i2c_edid->state = I2C_AUX_CH;
528 i2c_edid->port = port_idx;
529 i2c_edid->slave_selected = true;
530 if (intel_vgpu_has_monitor_on_port(vgpu,
531 port_idx) &&
532 intel_vgpu_port_is_dp(vgpu, port_idx))
533 i2c_edid->edid_available = true;
534 }
535 }
536 } else if ((op & 0x1) == GVT_AUX_I2C_WRITE) {
537 /* TODO
538 * We only support EDID reading from I2C_over_AUX. And
539 * we do not expect the index mode to be used. Right now
540 * the WRITE operation is ignored. It is good enough to
541 * support the gfx driver to do EDID access.
542 */
543 } else {
544 if (drm_WARN_ON(&i915->drm, (op & 0x1) != GVT_AUX_I2C_READ))
545 return;
546 if (drm_WARN_ON(&i915->drm, msg_length != 4))
547 return;
548 if (i2c_edid->edid_available && i2c_edid->slave_selected) {
549 unsigned char val = edid_get_byte(vgpu);
550
551 aux_data_for_write = (val << 16);
552 } else
553 aux_data_for_write = (0xff << 16);
554 }
555 /* write the return value in AUX_CH_DATA reg which includes:
556 * ACK of I2C_WRITE
557 * returned byte if it is READ
558 */
559 aux_data_for_write |= GVT_AUX_I2C_REPLY_ACK << 24;
560 vgpu_vreg(vgpu, offset + 4) = aux_data_for_write;
561}
562
563/**
564 * intel_vgpu_init_i2c_edid - initialize vGPU i2c edid emulation
565 * @vgpu: a vGPU
566 *
567 * This function is used to initialize vGPU i2c edid emulation stuffs
568 *
569 */
570void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu)
571{
572 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
573
574 edid->state = I2C_NOT_SPECIFIED;
575
576 edid->port = -1;
577 edid->slave_selected = false;
578 edid->edid_available = false;
579 edid->current_edid_read = 0;
580
581 memset(&edid->gmbus, 0, sizeof(struct intel_vgpu_i2c_gmbus));
582
583 edid->aux_ch.i2c_over_aux_ch = false;
584 edid->aux_ch.aux_ch_mot = false;
585}