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1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Ke Yu
25 * Zhiyuan Lv <zhiyuan.lv@intel.com>
26 *
27 * Contributors:
28 * Terrence Xu <terrence.xu@intel.com>
29 * Changbin Du <changbin.du@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 * Zhi Wang <zhi.a.wang@intel.com>
32 *
33 */
34
35#include <drm/display/drm_dp.h>
36
37#include "display/intel_dp_aux_regs.h"
38#include "display/intel_gmbus_regs.h"
39#include "gvt.h"
40#include "i915_drv.h"
41#include "i915_reg.h"
42
43#define GMBUS1_TOTAL_BYTES_SHIFT 16
44#define GMBUS1_TOTAL_BYTES_MASK 0x1ff
45#define gmbus1_total_byte_count(v) (((v) >> \
46 GMBUS1_TOTAL_BYTES_SHIFT) & GMBUS1_TOTAL_BYTES_MASK)
47#define gmbus1_target_addr(v) (((v) & 0xff) >> 1)
48#define gmbus1_target_index(v) (((v) >> 8) & 0xff)
49#define gmbus1_bus_cycle(v) (((v) >> 25) & 0x7)
50
51/* GMBUS0 bits definitions */
52#define _GMBUS_PIN_SEL_MASK (0x7)
53
54static unsigned char edid_get_byte(struct intel_vgpu *vgpu)
55{
56 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
57 unsigned char chr = 0;
58
59 if (edid->state == I2C_NOT_SPECIFIED || !edid->target_selected) {
60 gvt_vgpu_err("Driver tries to read EDID without proper sequence!\n");
61 return 0;
62 }
63 if (edid->current_edid_read >= EDID_SIZE) {
64 gvt_vgpu_err("edid_get_byte() exceeds the size of EDID!\n");
65 return 0;
66 }
67
68 if (!edid->edid_available) {
69 gvt_vgpu_err("Reading EDID but EDID is not available!\n");
70 return 0;
71 }
72
73 if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) {
74 struct intel_vgpu_edid_data *edid_data =
75 intel_vgpu_port(vgpu, edid->port)->edid;
76
77 chr = edid_data->edid_block[edid->current_edid_read];
78 edid->current_edid_read++;
79 } else {
80 gvt_vgpu_err("No EDID available during the reading?\n");
81 }
82 return chr;
83}
84
85static inline int cnp_get_port_from_gmbus0(u32 gmbus0)
86{
87 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
88 int port = -EINVAL;
89
90 if (port_select == GMBUS_PIN_1_BXT)
91 port = PORT_B;
92 else if (port_select == GMBUS_PIN_2_BXT)
93 port = PORT_C;
94 else if (port_select == GMBUS_PIN_3_BXT)
95 port = PORT_D;
96 else if (port_select == GMBUS_PIN_4_CNP)
97 port = PORT_E;
98 return port;
99}
100
101static inline int bxt_get_port_from_gmbus0(u32 gmbus0)
102{
103 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
104 int port = -EINVAL;
105
106 if (port_select == GMBUS_PIN_1_BXT)
107 port = PORT_B;
108 else if (port_select == GMBUS_PIN_2_BXT)
109 port = PORT_C;
110 else if (port_select == GMBUS_PIN_3_BXT)
111 port = PORT_D;
112 return port;
113}
114
115static inline int get_port_from_gmbus0(u32 gmbus0)
116{
117 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
118 int port = -EINVAL;
119
120 if (port_select == GMBUS_PIN_VGADDC)
121 port = PORT_E;
122 else if (port_select == GMBUS_PIN_DPC)
123 port = PORT_C;
124 else if (port_select == GMBUS_PIN_DPB)
125 port = PORT_B;
126 else if (port_select == GMBUS_PIN_DPD)
127 port = PORT_D;
128 return port;
129}
130
131static void reset_gmbus_controller(struct intel_vgpu *vgpu)
132{
133 vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;
134 if (!vgpu->display.i2c_edid.edid_available)
135 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
136 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
137}
138
139/* GMBUS0 */
140static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
141 unsigned int offset, void *p_data, unsigned int bytes)
142{
143 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
144 int port, pin_select;
145
146 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
147
148 pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK;
149
150 intel_vgpu_init_i2c_edid(vgpu);
151
152 if (pin_select == 0)
153 return 0;
154
155 if (IS_BROXTON(i915))
156 port = bxt_get_port_from_gmbus0(pin_select);
157 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
158 port = cnp_get_port_from_gmbus0(pin_select);
159 else
160 port = get_port_from_gmbus0(pin_select);
161 if (drm_WARN_ON(&i915->drm, port < 0))
162 return 0;
163
164 vgpu->display.i2c_edid.state = I2C_GMBUS;
165 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
166
167 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
168 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
169
170 if (intel_vgpu_has_monitor_on_port(vgpu, port) &&
171 !intel_vgpu_port_is_dp(vgpu, port)) {
172 vgpu->display.i2c_edid.port = port;
173 vgpu->display.i2c_edid.edid_available = true;
174 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;
175 } else
176 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
177 return 0;
178}
179
180static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
181 void *p_data, unsigned int bytes)
182{
183 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
184 u32 target_addr;
185 u32 wvalue = *(u32 *)p_data;
186
187 if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) {
188 if (!(wvalue & GMBUS_SW_CLR_INT)) {
189 vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT;
190 reset_gmbus_controller(vgpu);
191 }
192 /*
193 * TODO: "This bit is cleared to zero when an event
194 * causes the HW_RDY bit transition to occur "
195 */
196 } else {
197 /*
198 * per bspec setting this bit can cause:
199 * 1) INT status bit cleared
200 * 2) HW_RDY bit asserted
201 */
202 if (wvalue & GMBUS_SW_CLR_INT) {
203 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;
204 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;
205 }
206
207 /* For virtualization, we suppose that HW is always ready,
208 * so GMBUS_SW_RDY should always be cleared
209 */
210 if (wvalue & GMBUS_SW_RDY)
211 wvalue &= ~GMBUS_SW_RDY;
212
213 i2c_edid->gmbus.total_byte_count =
214 gmbus1_total_byte_count(wvalue);
215 target_addr = gmbus1_target_addr(wvalue);
216
217 /* vgpu gmbus only support EDID */
218 if (target_addr == EDID_ADDR) {
219 i2c_edid->target_selected = true;
220 } else if (target_addr != 0) {
221 gvt_dbg_dpy(
222 "vgpu%d: unsupported gmbus target addr(0x%x)\n"
223 " gmbus operations will be ignored.\n",
224 vgpu->id, target_addr);
225 }
226
227 if (wvalue & GMBUS_CYCLE_INDEX)
228 i2c_edid->current_edid_read =
229 gmbus1_target_index(wvalue);
230
231 i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue);
232 switch (gmbus1_bus_cycle(wvalue)) {
233 case GMBUS_NOCYCLE:
234 break;
235 case GMBUS_STOP:
236 /* From spec:
237 * This can only cause a STOP to be generated
238 * if a GMBUS cycle is generated, the GMBUS is
239 * currently in a data/wait/idle phase, or it is in a
240 * WAIT phase
241 */
242 if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset))
243 != GMBUS_NOCYCLE) {
244 intel_vgpu_init_i2c_edid(vgpu);
245 /* After the 'stop' cycle, hw state would become
246 * 'stop phase' and then 'idle phase' after a
247 * few milliseconds. In emulation, we just set
248 * it as 'idle phase' ('stop phase' is not
249 * visible in gmbus interface)
250 */
251 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
252 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
253 }
254 break;
255 case NIDX_NS_W:
256 case IDX_NS_W:
257 case NIDX_STOP:
258 case IDX_STOP:
259 /* From hw spec the GMBUS phase
260 * transition like this:
261 * START (-->INDEX) -->DATA
262 */
263 i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;
264 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;
265 break;
266 default:
267 gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n");
268 break;
269 }
270 /*
271 * From hw spec the WAIT state will be
272 * cleared:
273 * (1) in a new GMBUS cycle
274 * (2) by generating a stop
275 */
276 vgpu_vreg(vgpu, offset) = wvalue;
277 }
278 return 0;
279}
280
281static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
282 void *p_data, unsigned int bytes)
283{
284 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
285
286 drm_WARN_ON(&i915->drm, 1);
287 return 0;
288}
289
290static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
291 void *p_data, unsigned int bytes)
292{
293 int i;
294 unsigned char byte_data;
295 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
296 int byte_left = i2c_edid->gmbus.total_byte_count -
297 i2c_edid->current_edid_read;
298 int byte_count = byte_left;
299 u32 reg_data = 0;
300
301 /* Data can only be recevied if previous settings correct */
302 if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {
303 if (byte_left <= 0) {
304 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
305 return 0;
306 }
307
308 if (byte_count > 4)
309 byte_count = 4;
310 for (i = 0; i < byte_count; i++) {
311 byte_data = edid_get_byte(vgpu);
312 reg_data |= (byte_data << (i << 3));
313 }
314
315 memcpy(&vgpu_vreg(vgpu, offset), ®_data, byte_count);
316 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
317
318 if (byte_left <= 4) {
319 switch (i2c_edid->gmbus.cycle_type) {
320 case NIDX_STOP:
321 case IDX_STOP:
322 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
323 break;
324 case NIDX_NS_W:
325 case IDX_NS_W:
326 default:
327 i2c_edid->gmbus.phase = GMBUS_WAIT_PHASE;
328 break;
329 }
330 intel_vgpu_init_i2c_edid(vgpu);
331 }
332 /*
333 * Read GMBUS3 during send operation,
334 * return the latest written value
335 */
336 } else {
337 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
338 gvt_vgpu_err("warning: gmbus3 read with nothing returned\n");
339 }
340 return 0;
341}
342
343static int gmbus2_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
344 void *p_data, unsigned int bytes)
345{
346 u32 value = vgpu_vreg(vgpu, offset);
347
348 if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE))
349 vgpu_vreg(vgpu, offset) |= GMBUS_INUSE;
350 memcpy(p_data, (void *)&value, bytes);
351 return 0;
352}
353
354static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
355 void *p_data, unsigned int bytes)
356{
357 u32 wvalue = *(u32 *)p_data;
358
359 if (wvalue & GMBUS_INUSE)
360 vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE;
361 /* All other bits are read-only */
362 return 0;
363}
364
365/**
366 * intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read
367 * @vgpu: a vGPU
368 * @offset: reg offset
369 * @p_data: data return buffer
370 * @bytes: access data length
371 *
372 * This function is used to emulate gmbus register mmio read
373 *
374 * Returns:
375 * Zero on success, negative error code if failed.
376 *
377 */
378int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
379 unsigned int offset, void *p_data, unsigned int bytes)
380{
381 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
382
383 if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
384 return -EINVAL;
385
386 if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
387 return gmbus2_mmio_read(vgpu, offset, p_data, bytes);
388 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
389 return gmbus3_mmio_read(vgpu, offset, p_data, bytes);
390
391 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
392 return 0;
393}
394
395/**
396 * intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write
397 * @vgpu: a vGPU
398 * @offset: reg offset
399 * @p_data: data return buffer
400 * @bytes: access data length
401 *
402 * This function is used to emulate gmbus register mmio write
403 *
404 * Returns:
405 * Zero on success, negative error code if failed.
406 *
407 */
408int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
409 unsigned int offset, void *p_data, unsigned int bytes)
410{
411 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
412
413 if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
414 return -EINVAL;
415
416 if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
417 return gmbus0_mmio_write(vgpu, offset, p_data, bytes);
418 else if (offset == i915_mmio_reg_offset(PCH_GMBUS1))
419 return gmbus1_mmio_write(vgpu, offset, p_data, bytes);
420 else if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
421 return gmbus2_mmio_write(vgpu, offset, p_data, bytes);
422 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
423 return gmbus3_mmio_write(vgpu, offset, p_data, bytes);
424
425 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
426 return 0;
427}
428
429enum {
430 AUX_CH_CTL = 0,
431 AUX_CH_DATA1,
432 AUX_CH_DATA2,
433 AUX_CH_DATA3,
434 AUX_CH_DATA4,
435 AUX_CH_DATA5
436};
437
438static inline int get_aux_ch_reg(unsigned int offset)
439{
440 int reg;
441
442 switch (offset & 0xff) {
443 case 0x10:
444 reg = AUX_CH_CTL;
445 break;
446 case 0x14:
447 reg = AUX_CH_DATA1;
448 break;
449 case 0x18:
450 reg = AUX_CH_DATA2;
451 break;
452 case 0x1c:
453 reg = AUX_CH_DATA3;
454 break;
455 case 0x20:
456 reg = AUX_CH_DATA4;
457 break;
458 case 0x24:
459 reg = AUX_CH_DATA5;
460 break;
461 default:
462 reg = -1;
463 break;
464 }
465 return reg;
466}
467
468/**
469 * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
470 * @vgpu: a vGPU
471 * @port_idx: port index
472 * @offset: reg offset
473 * @p_data: write ptr
474 *
475 * This function is used to emulate AUX channel register write
476 *
477 */
478void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
479 int port_idx,
480 unsigned int offset,
481 void *p_data)
482{
483 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
484 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
485 int msg_length, ret_msg_size;
486 int msg, addr, ctrl, op;
487 u32 value = *(u32 *)p_data;
488 int aux_data_for_write = 0;
489 int reg = get_aux_ch_reg(offset);
490
491 if (reg != AUX_CH_CTL) {
492 vgpu_vreg(vgpu, offset) = value;
493 return;
494 }
495
496 msg_length = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, value);
497
498 // check the msg in DATA register.
499 msg = vgpu_vreg(vgpu, offset + 4);
500 addr = (msg >> 8) & 0xffff;
501 ctrl = (msg >> 24) & 0xff;
502 op = ctrl >> 4;
503 if (!(value & DP_AUX_CH_CTL_SEND_BUSY)) {
504 /* The ctl write to clear some states */
505 return;
506 }
507
508 /* Always set the wanted value for vms. */
509 ret_msg_size = (((op & 0x1) == DP_AUX_I2C_READ) ? 2 : 1);
510 vgpu_vreg(vgpu, offset) =
511 DP_AUX_CH_CTL_DONE |
512 DP_AUX_CH_CTL_MESSAGE_SIZE(ret_msg_size);
513
514 if (msg_length == 3) {
515 if (!(op & DP_AUX_I2C_MOT)) {
516 /* stop */
517 intel_vgpu_init_i2c_edid(vgpu);
518 } else {
519 /* start or restart */
520 i2c_edid->aux_ch.i2c_over_aux_ch = true;
521 i2c_edid->aux_ch.aux_ch_mot = true;
522 if (addr == 0) {
523 /* reset the address */
524 intel_vgpu_init_i2c_edid(vgpu);
525 } else if (addr == EDID_ADDR) {
526 i2c_edid->state = I2C_AUX_CH;
527 i2c_edid->port = port_idx;
528 i2c_edid->target_selected = true;
529 if (intel_vgpu_has_monitor_on_port(vgpu,
530 port_idx) &&
531 intel_vgpu_port_is_dp(vgpu, port_idx))
532 i2c_edid->edid_available = true;
533 }
534 }
535 } else if ((op & 0x1) == DP_AUX_I2C_WRITE) {
536 /* TODO
537 * We only support EDID reading from I2C_over_AUX. And
538 * we do not expect the index mode to be used. Right now
539 * the WRITE operation is ignored. It is good enough to
540 * support the gfx driver to do EDID access.
541 */
542 } else {
543 if (drm_WARN_ON(&i915->drm, (op & 0x1) != DP_AUX_I2C_READ))
544 return;
545 if (drm_WARN_ON(&i915->drm, msg_length != 4))
546 return;
547 if (i2c_edid->edid_available && i2c_edid->target_selected) {
548 unsigned char val = edid_get_byte(vgpu);
549
550 aux_data_for_write = (val << 16);
551 } else
552 aux_data_for_write = (0xff << 16);
553 }
554 /* write the return value in AUX_CH_DATA reg which includes:
555 * ACK of I2C_WRITE
556 * returned byte if it is READ
557 */
558 aux_data_for_write |= DP_AUX_I2C_REPLY_ACK << 24;
559 vgpu_vreg(vgpu, offset + 4) = aux_data_for_write;
560}
561
562/**
563 * intel_vgpu_init_i2c_edid - initialize vGPU i2c edid emulation
564 * @vgpu: a vGPU
565 *
566 * This function is used to initialize vGPU i2c edid emulation stuffs
567 *
568 */
569void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu)
570{
571 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
572
573 edid->state = I2C_NOT_SPECIFIED;
574
575 edid->port = -1;
576 edid->target_selected = false;
577 edid->edid_available = false;
578 edid->current_edid_read = 0;
579
580 memset(&edid->gmbus, 0, sizeof(struct intel_vgpu_i2c_gmbus));
581
582 edid->aux_ch.i2c_over_aux_ch = false;
583 edid->aux_ch.aux_ch_mot = false;
584}