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1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Ke Yu
25 * Zhiyuan Lv <zhiyuan.lv@intel.com>
26 *
27 * Contributors:
28 * Terrence Xu <terrence.xu@intel.com>
29 * Changbin Du <changbin.du@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 * Zhi Wang <zhi.a.wang@intel.com>
32 *
33 */
34
35#include "i915_drv.h"
36#include "gvt.h"
37
38#define GMBUS1_TOTAL_BYTES_SHIFT 16
39#define GMBUS1_TOTAL_BYTES_MASK 0x1ff
40#define gmbus1_total_byte_count(v) (((v) >> \
41 GMBUS1_TOTAL_BYTES_SHIFT) & GMBUS1_TOTAL_BYTES_MASK)
42#define gmbus1_slave_addr(v) (((v) & 0xff) >> 1)
43#define gmbus1_slave_index(v) (((v) >> 8) & 0xff)
44#define gmbus1_bus_cycle(v) (((v) >> 25) & 0x7)
45
46/* GMBUS0 bits definitions */
47#define _GMBUS_PIN_SEL_MASK (0x7)
48
49static unsigned char edid_get_byte(struct intel_vgpu *vgpu)
50{
51 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
52 unsigned char chr = 0;
53
54 if (edid->state == I2C_NOT_SPECIFIED || !edid->slave_selected) {
55 gvt_vgpu_err("Driver tries to read EDID without proper sequence!\n");
56 return 0;
57 }
58 if (edid->current_edid_read >= EDID_SIZE) {
59 gvt_vgpu_err("edid_get_byte() exceeds the size of EDID!\n");
60 return 0;
61 }
62
63 if (!edid->edid_available) {
64 gvt_vgpu_err("Reading EDID but EDID is not available!\n");
65 return 0;
66 }
67
68 if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) {
69 struct intel_vgpu_edid_data *edid_data =
70 intel_vgpu_port(vgpu, edid->port)->edid;
71
72 chr = edid_data->edid_block[edid->current_edid_read];
73 edid->current_edid_read++;
74 } else {
75 gvt_vgpu_err("No EDID available during the reading?\n");
76 }
77 return chr;
78}
79
80static inline int cnp_get_port_from_gmbus0(u32 gmbus0)
81{
82 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
83 int port = -EINVAL;
84
85 if (port_select == GMBUS_PIN_1_BXT)
86 port = PORT_B;
87 else if (port_select == GMBUS_PIN_2_BXT)
88 port = PORT_C;
89 else if (port_select == GMBUS_PIN_3_BXT)
90 port = PORT_D;
91 else if (port_select == GMBUS_PIN_4_CNP)
92 port = PORT_E;
93 return port;
94}
95
96static inline int bxt_get_port_from_gmbus0(u32 gmbus0)
97{
98 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
99 int port = -EINVAL;
100
101 if (port_select == GMBUS_PIN_1_BXT)
102 port = PORT_B;
103 else if (port_select == GMBUS_PIN_2_BXT)
104 port = PORT_C;
105 else if (port_select == GMBUS_PIN_3_BXT)
106 port = PORT_D;
107 return port;
108}
109
110static inline int get_port_from_gmbus0(u32 gmbus0)
111{
112 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
113 int port = -EINVAL;
114
115 if (port_select == GMBUS_PIN_VGADDC)
116 port = PORT_E;
117 else if (port_select == GMBUS_PIN_DPC)
118 port = PORT_C;
119 else if (port_select == GMBUS_PIN_DPB)
120 port = PORT_B;
121 else if (port_select == GMBUS_PIN_DPD)
122 port = PORT_D;
123 return port;
124}
125
126static void reset_gmbus_controller(struct intel_vgpu *vgpu)
127{
128 vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;
129 if (!vgpu->display.i2c_edid.edid_available)
130 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
131 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
132}
133
134/* GMBUS0 */
135static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
136 unsigned int offset, void *p_data, unsigned int bytes)
137{
138 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
139 int port, pin_select;
140
141 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
142
143 pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK;
144
145 intel_vgpu_init_i2c_edid(vgpu);
146
147 if (pin_select == 0)
148 return 0;
149
150 if (IS_BROXTON(i915))
151 port = bxt_get_port_from_gmbus0(pin_select);
152 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
153 port = cnp_get_port_from_gmbus0(pin_select);
154 else
155 port = get_port_from_gmbus0(pin_select);
156 if (drm_WARN_ON(&i915->drm, port < 0))
157 return 0;
158
159 vgpu->display.i2c_edid.state = I2C_GMBUS;
160 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
161
162 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
163 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
164
165 if (intel_vgpu_has_monitor_on_port(vgpu, port) &&
166 !intel_vgpu_port_is_dp(vgpu, port)) {
167 vgpu->display.i2c_edid.port = port;
168 vgpu->display.i2c_edid.edid_available = true;
169 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;
170 } else
171 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
172 return 0;
173}
174
175static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
176 void *p_data, unsigned int bytes)
177{
178 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
179 u32 slave_addr;
180 u32 wvalue = *(u32 *)p_data;
181
182 if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) {
183 if (!(wvalue & GMBUS_SW_CLR_INT)) {
184 vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT;
185 reset_gmbus_controller(vgpu);
186 }
187 /*
188 * TODO: "This bit is cleared to zero when an event
189 * causes the HW_RDY bit transition to occur "
190 */
191 } else {
192 /*
193 * per bspec setting this bit can cause:
194 * 1) INT status bit cleared
195 * 2) HW_RDY bit asserted
196 */
197 if (wvalue & GMBUS_SW_CLR_INT) {
198 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;
199 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;
200 }
201
202 /* For virtualization, we suppose that HW is always ready,
203 * so GMBUS_SW_RDY should always be cleared
204 */
205 if (wvalue & GMBUS_SW_RDY)
206 wvalue &= ~GMBUS_SW_RDY;
207
208 i2c_edid->gmbus.total_byte_count =
209 gmbus1_total_byte_count(wvalue);
210 slave_addr = gmbus1_slave_addr(wvalue);
211
212 /* vgpu gmbus only support EDID */
213 if (slave_addr == EDID_ADDR) {
214 i2c_edid->slave_selected = true;
215 } else if (slave_addr != 0) {
216 gvt_dbg_dpy(
217 "vgpu%d: unsupported gmbus slave addr(0x%x)\n"
218 " gmbus operations will be ignored.\n",
219 vgpu->id, slave_addr);
220 }
221
222 if (wvalue & GMBUS_CYCLE_INDEX)
223 i2c_edid->current_edid_read =
224 gmbus1_slave_index(wvalue);
225
226 i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue);
227 switch (gmbus1_bus_cycle(wvalue)) {
228 case GMBUS_NOCYCLE:
229 break;
230 case GMBUS_STOP:
231 /* From spec:
232 * This can only cause a STOP to be generated
233 * if a GMBUS cycle is generated, the GMBUS is
234 * currently in a data/wait/idle phase, or it is in a
235 * WAIT phase
236 */
237 if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset))
238 != GMBUS_NOCYCLE) {
239 intel_vgpu_init_i2c_edid(vgpu);
240 /* After the 'stop' cycle, hw state would become
241 * 'stop phase' and then 'idle phase' after a
242 * few milliseconds. In emulation, we just set
243 * it as 'idle phase' ('stop phase' is not
244 * visible in gmbus interface)
245 */
246 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
247 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
248 }
249 break;
250 case NIDX_NS_W:
251 case IDX_NS_W:
252 case NIDX_STOP:
253 case IDX_STOP:
254 /* From hw spec the GMBUS phase
255 * transition like this:
256 * START (-->INDEX) -->DATA
257 */
258 i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;
259 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;
260 break;
261 default:
262 gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n");
263 break;
264 }
265 /*
266 * From hw spec the WAIT state will be
267 * cleared:
268 * (1) in a new GMBUS cycle
269 * (2) by generating a stop
270 */
271 vgpu_vreg(vgpu, offset) = wvalue;
272 }
273 return 0;
274}
275
276static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
277 void *p_data, unsigned int bytes)
278{
279 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
280
281 drm_WARN_ON(&i915->drm, 1);
282 return 0;
283}
284
285static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
286 void *p_data, unsigned int bytes)
287{
288 int i;
289 unsigned char byte_data;
290 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
291 int byte_left = i2c_edid->gmbus.total_byte_count -
292 i2c_edid->current_edid_read;
293 int byte_count = byte_left;
294 u32 reg_data = 0;
295
296 /* Data can only be recevied if previous settings correct */
297 if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {
298 if (byte_left <= 0) {
299 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
300 return 0;
301 }
302
303 if (byte_count > 4)
304 byte_count = 4;
305 for (i = 0; i < byte_count; i++) {
306 byte_data = edid_get_byte(vgpu);
307 reg_data |= (byte_data << (i << 3));
308 }
309
310 memcpy(&vgpu_vreg(vgpu, offset), ®_data, byte_count);
311 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
312
313 if (byte_left <= 4) {
314 switch (i2c_edid->gmbus.cycle_type) {
315 case NIDX_STOP:
316 case IDX_STOP:
317 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
318 break;
319 case NIDX_NS_W:
320 case IDX_NS_W:
321 default:
322 i2c_edid->gmbus.phase = GMBUS_WAIT_PHASE;
323 break;
324 }
325 intel_vgpu_init_i2c_edid(vgpu);
326 }
327 /*
328 * Read GMBUS3 during send operation,
329 * return the latest written value
330 */
331 } else {
332 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
333 gvt_vgpu_err("warning: gmbus3 read with nothing returned\n");
334 }
335 return 0;
336}
337
338static int gmbus2_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
339 void *p_data, unsigned int bytes)
340{
341 u32 value = vgpu_vreg(vgpu, offset);
342
343 if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE))
344 vgpu_vreg(vgpu, offset) |= GMBUS_INUSE;
345 memcpy(p_data, (void *)&value, bytes);
346 return 0;
347}
348
349static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
350 void *p_data, unsigned int bytes)
351{
352 u32 wvalue = *(u32 *)p_data;
353
354 if (wvalue & GMBUS_INUSE)
355 vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE;
356 /* All other bits are read-only */
357 return 0;
358}
359
360/**
361 * intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read
362 * @vgpu: a vGPU
363 * @offset: reg offset
364 * @p_data: data return buffer
365 * @bytes: access data length
366 *
367 * This function is used to emulate gmbus register mmio read
368 *
369 * Returns:
370 * Zero on success, negative error code if failed.
371 *
372 */
373int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
374 unsigned int offset, void *p_data, unsigned int bytes)
375{
376 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
377
378 if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
379 return -EINVAL;
380
381 if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
382 return gmbus2_mmio_read(vgpu, offset, p_data, bytes);
383 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
384 return gmbus3_mmio_read(vgpu, offset, p_data, bytes);
385
386 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
387 return 0;
388}
389
390/**
391 * intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write
392 * @vgpu: a vGPU
393 * @offset: reg offset
394 * @p_data: data return buffer
395 * @bytes: access data length
396 *
397 * This function is used to emulate gmbus register mmio write
398 *
399 * Returns:
400 * Zero on success, negative error code if failed.
401 *
402 */
403int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
404 unsigned int offset, void *p_data, unsigned int bytes)
405{
406 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
407
408 if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
409 return -EINVAL;
410
411 if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
412 return gmbus0_mmio_write(vgpu, offset, p_data, bytes);
413 else if (offset == i915_mmio_reg_offset(PCH_GMBUS1))
414 return gmbus1_mmio_write(vgpu, offset, p_data, bytes);
415 else if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
416 return gmbus2_mmio_write(vgpu, offset, p_data, bytes);
417 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
418 return gmbus3_mmio_write(vgpu, offset, p_data, bytes);
419
420 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
421 return 0;
422}
423
424enum {
425 AUX_CH_CTL = 0,
426 AUX_CH_DATA1,
427 AUX_CH_DATA2,
428 AUX_CH_DATA3,
429 AUX_CH_DATA4,
430 AUX_CH_DATA5
431};
432
433static inline int get_aux_ch_reg(unsigned int offset)
434{
435 int reg;
436
437 switch (offset & 0xff) {
438 case 0x10:
439 reg = AUX_CH_CTL;
440 break;
441 case 0x14:
442 reg = AUX_CH_DATA1;
443 break;
444 case 0x18:
445 reg = AUX_CH_DATA2;
446 break;
447 case 0x1c:
448 reg = AUX_CH_DATA3;
449 break;
450 case 0x20:
451 reg = AUX_CH_DATA4;
452 break;
453 case 0x24:
454 reg = AUX_CH_DATA5;
455 break;
456 default:
457 reg = -1;
458 break;
459 }
460 return reg;
461}
462
463#define AUX_CTL_MSG_LENGTH(reg) \
464 ((reg & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> \
465 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT)
466
467/**
468 * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
469 * @vgpu: a vGPU
470 * @port_idx: port index
471 * @offset: reg offset
472 * @p_data: write ptr
473 *
474 * This function is used to emulate AUX channel register write
475 *
476 */
477void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
478 int port_idx,
479 unsigned int offset,
480 void *p_data)
481{
482 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
483 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
484 int msg_length, ret_msg_size;
485 int msg, addr, ctrl, op;
486 u32 value = *(u32 *)p_data;
487 int aux_data_for_write = 0;
488 int reg = get_aux_ch_reg(offset);
489
490 if (reg != AUX_CH_CTL) {
491 vgpu_vreg(vgpu, offset) = value;
492 return;
493 }
494
495 msg_length = AUX_CTL_MSG_LENGTH(value);
496 // check the msg in DATA register.
497 msg = vgpu_vreg(vgpu, offset + 4);
498 addr = (msg >> 8) & 0xffff;
499 ctrl = (msg >> 24) & 0xff;
500 op = ctrl >> 4;
501 if (!(value & DP_AUX_CH_CTL_SEND_BUSY)) {
502 /* The ctl write to clear some states */
503 return;
504 }
505
506 /* Always set the wanted value for vms. */
507 ret_msg_size = (((op & 0x1) == GVT_AUX_I2C_READ) ? 2 : 1);
508 vgpu_vreg(vgpu, offset) =
509 DP_AUX_CH_CTL_DONE |
510 ((ret_msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) &
511 DP_AUX_CH_CTL_MESSAGE_SIZE_MASK);
512
513 if (msg_length == 3) {
514 if (!(op & GVT_AUX_I2C_MOT)) {
515 /* stop */
516 intel_vgpu_init_i2c_edid(vgpu);
517 } else {
518 /* start or restart */
519 i2c_edid->aux_ch.i2c_over_aux_ch = true;
520 i2c_edid->aux_ch.aux_ch_mot = true;
521 if (addr == 0) {
522 /* reset the address */
523 intel_vgpu_init_i2c_edid(vgpu);
524 } else if (addr == EDID_ADDR) {
525 i2c_edid->state = I2C_AUX_CH;
526 i2c_edid->port = port_idx;
527 i2c_edid->slave_selected = true;
528 if (intel_vgpu_has_monitor_on_port(vgpu,
529 port_idx) &&
530 intel_vgpu_port_is_dp(vgpu, port_idx))
531 i2c_edid->edid_available = true;
532 }
533 }
534 } else if ((op & 0x1) == GVT_AUX_I2C_WRITE) {
535 /* TODO
536 * We only support EDID reading from I2C_over_AUX. And
537 * we do not expect the index mode to be used. Right now
538 * the WRITE operation is ignored. It is good enough to
539 * support the gfx driver to do EDID access.
540 */
541 } else {
542 if (drm_WARN_ON(&i915->drm, (op & 0x1) != GVT_AUX_I2C_READ))
543 return;
544 if (drm_WARN_ON(&i915->drm, msg_length != 4))
545 return;
546 if (i2c_edid->edid_available && i2c_edid->slave_selected) {
547 unsigned char val = edid_get_byte(vgpu);
548
549 aux_data_for_write = (val << 16);
550 } else
551 aux_data_for_write = (0xff << 16);
552 }
553 /* write the return value in AUX_CH_DATA reg which includes:
554 * ACK of I2C_WRITE
555 * returned byte if it is READ
556 */
557 aux_data_for_write |= GVT_AUX_I2C_REPLY_ACK << 24;
558 vgpu_vreg(vgpu, offset + 4) = aux_data_for_write;
559}
560
561/**
562 * intel_vgpu_init_i2c_edid - initialize vGPU i2c edid emulation
563 * @vgpu: a vGPU
564 *
565 * This function is used to initialize vGPU i2c edid emulation stuffs
566 *
567 */
568void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu)
569{
570 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
571
572 edid->state = I2C_NOT_SPECIFIED;
573
574 edid->port = -1;
575 edid->slave_selected = false;
576 edid->edid_available = false;
577 edid->current_edid_read = 0;
578
579 memset(&edid->gmbus, 0, sizeof(struct intel_vgpu_i2c_gmbus));
580
581 edid->aux_ch.i2c_over_aux_ch = false;
582 edid->aux_ch.aux_ch_mot = false;
583}