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1/**
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * S3C USB2.0 High-speed / OtG driver
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/spinlock.h>
20#include <linux/interrupt.h>
21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h>
23#include <linux/mutex.h>
24#include <linux/seq_file.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/slab.h>
28#include <linux/of_platform.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32#include <linux/usb/phy.h>
33
34#include "core.h"
35#include "hw.h"
36
37/* conversion functions */
38static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
39{
40 return container_of(req, struct dwc2_hsotg_req, req);
41}
42
43static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
44{
45 return container_of(ep, struct dwc2_hsotg_ep, ep);
46}
47
48static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
49{
50 return container_of(gadget, struct dwc2_hsotg, gadget);
51}
52
53static inline void __orr32(void __iomem *ptr, u32 val)
54{
55 dwc2_writel(dwc2_readl(ptr) | val, ptr);
56}
57
58static inline void __bic32(void __iomem *ptr, u32 val)
59{
60 dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
61}
62
63static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
64 u32 ep_index, u32 dir_in)
65{
66 if (dir_in)
67 return hsotg->eps_in[ep_index];
68 else
69 return hsotg->eps_out[ep_index];
70}
71
72/* forward declaration of functions */
73static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
74
75/**
76 * using_dma - return the DMA status of the driver.
77 * @hsotg: The driver state.
78 *
79 * Return true if we're using DMA.
80 *
81 * Currently, we have the DMA support code worked into everywhere
82 * that needs it, but the AMBA DMA implementation in the hardware can
83 * only DMA from 32bit aligned addresses. This means that gadgets such
84 * as the CDC Ethernet cannot work as they often pass packets which are
85 * not 32bit aligned.
86 *
87 * Unfortunately the choice to use DMA or not is global to the controller
88 * and seems to be only settable when the controller is being put through
89 * a core reset. This means we either need to fix the gadgets to take
90 * account of DMA alignment, or add bounce buffers (yuerk).
91 *
92 * g_using_dma is set depending on dts flag.
93 */
94static inline bool using_dma(struct dwc2_hsotg *hsotg)
95{
96 return hsotg->g_using_dma;
97}
98
99/**
100 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
101 * @hsotg: The device state
102 * @ints: A bitmask of the interrupts to enable
103 */
104static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
105{
106 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
107 u32 new_gsintmsk;
108
109 new_gsintmsk = gsintmsk | ints;
110
111 if (new_gsintmsk != gsintmsk) {
112 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
113 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
114 }
115}
116
117/**
118 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
119 * @hsotg: The device state
120 * @ints: A bitmask of the interrupts to enable
121 */
122static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
123{
124 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
125 u32 new_gsintmsk;
126
127 new_gsintmsk = gsintmsk & ~ints;
128
129 if (new_gsintmsk != gsintmsk)
130 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
131}
132
133/**
134 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
135 * @hsotg: The device state
136 * @ep: The endpoint index
137 * @dir_in: True if direction is in.
138 * @en: The enable value, true to enable
139 *
140 * Set or clear the mask for an individual endpoint's interrupt
141 * request.
142 */
143static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
144 unsigned int ep, unsigned int dir_in,
145 unsigned int en)
146{
147 unsigned long flags;
148 u32 bit = 1 << ep;
149 u32 daint;
150
151 if (!dir_in)
152 bit <<= 16;
153
154 local_irq_save(flags);
155 daint = dwc2_readl(hsotg->regs + DAINTMSK);
156 if (en)
157 daint |= bit;
158 else
159 daint &= ~bit;
160 dwc2_writel(daint, hsotg->regs + DAINTMSK);
161 local_irq_restore(flags);
162}
163
164/**
165 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
166 * @hsotg: The device instance.
167 */
168static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
169{
170 unsigned int ep;
171 unsigned int addr;
172 int timeout;
173 u32 val;
174
175 /* Reset fifo map if not correctly cleared during previous session */
176 WARN_ON(hsotg->fifo_map);
177 hsotg->fifo_map = 0;
178
179 /* set RX/NPTX FIFO sizes */
180 dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ);
181 dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) |
182 (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT),
183 hsotg->regs + GNPTXFSIZ);
184
185 /*
186 * arange all the rest of the TX FIFOs, as some versions of this
187 * block have overlapping default addresses. This also ensures
188 * that if the settings have been changed, then they are set to
189 * known values.
190 */
191
192 /* start at the end of the GNPTXFSIZ, rounded up */
193 addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz;
194
195 /*
196 * Configure fifos sizes from provided configuration and assign
197 * them to endpoints dynamically according to maxpacket size value of
198 * given endpoint.
199 */
200 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
201 if (!hsotg->g_tx_fifo_sz[ep])
202 continue;
203 val = addr;
204 val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT;
205 WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem,
206 "insufficient fifo memory");
207 addr += hsotg->g_tx_fifo_sz[ep];
208
209 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
210 }
211
212 /*
213 * according to p428 of the design guide, we need to ensure that
214 * all fifos are flushed before continuing
215 */
216
217 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
218 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
219
220 /* wait until the fifos are both flushed */
221 timeout = 100;
222 while (1) {
223 val = dwc2_readl(hsotg->regs + GRSTCTL);
224
225 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
226 break;
227
228 if (--timeout == 0) {
229 dev_err(hsotg->dev,
230 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
231 __func__, val);
232 break;
233 }
234
235 udelay(1);
236 }
237
238 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
239}
240
241/**
242 * @ep: USB endpoint to allocate request for.
243 * @flags: Allocation flags
244 *
245 * Allocate a new USB request structure appropriate for the specified endpoint
246 */
247static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
248 gfp_t flags)
249{
250 struct dwc2_hsotg_req *req;
251
252 req = kzalloc(sizeof(struct dwc2_hsotg_req), flags);
253 if (!req)
254 return NULL;
255
256 INIT_LIST_HEAD(&req->queue);
257
258 return &req->req;
259}
260
261/**
262 * is_ep_periodic - return true if the endpoint is in periodic mode.
263 * @hs_ep: The endpoint to query.
264 *
265 * Returns true if the endpoint is in periodic mode, meaning it is being
266 * used for an Interrupt or ISO transfer.
267 */
268static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
269{
270 return hs_ep->periodic;
271}
272
273/**
274 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
275 * @hsotg: The device state.
276 * @hs_ep: The endpoint for the request
277 * @hs_req: The request being processed.
278 *
279 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
280 * of a request to ensure the buffer is ready for access by the caller.
281 */
282static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
283 struct dwc2_hsotg_ep *hs_ep,
284 struct dwc2_hsotg_req *hs_req)
285{
286 struct usb_request *req = &hs_req->req;
287
288 /* ignore this if we're not moving any data */
289 if (hs_req->req.length == 0)
290 return;
291
292 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
293}
294
295/**
296 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
297 * @hsotg: The controller state.
298 * @hs_ep: The endpoint we're going to write for.
299 * @hs_req: The request to write data for.
300 *
301 * This is called when the TxFIFO has some space in it to hold a new
302 * transmission and we have something to give it. The actual setup of
303 * the data size is done elsewhere, so all we have to do is to actually
304 * write the data.
305 *
306 * The return value is zero if there is more space (or nothing was done)
307 * otherwise -ENOSPC is returned if the FIFO space was used up.
308 *
309 * This routine is only needed for PIO
310 */
311static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
312 struct dwc2_hsotg_ep *hs_ep,
313 struct dwc2_hsotg_req *hs_req)
314{
315 bool periodic = is_ep_periodic(hs_ep);
316 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
317 int buf_pos = hs_req->req.actual;
318 int to_write = hs_ep->size_loaded;
319 void *data;
320 int can_write;
321 int pkt_round;
322 int max_transfer;
323
324 to_write -= (buf_pos - hs_ep->last_load);
325
326 /* if there's nothing to write, get out early */
327 if (to_write == 0)
328 return 0;
329
330 if (periodic && !hsotg->dedicated_fifos) {
331 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
332 int size_left;
333 int size_done;
334
335 /*
336 * work out how much data was loaded so we can calculate
337 * how much data is left in the fifo.
338 */
339
340 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
341
342 /*
343 * if shared fifo, we cannot write anything until the
344 * previous data has been completely sent.
345 */
346 if (hs_ep->fifo_load != 0) {
347 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
348 return -ENOSPC;
349 }
350
351 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
352 __func__, size_left,
353 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
354
355 /* how much of the data has moved */
356 size_done = hs_ep->size_loaded - size_left;
357
358 /* how much data is left in the fifo */
359 can_write = hs_ep->fifo_load - size_done;
360 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
361 __func__, can_write);
362
363 can_write = hs_ep->fifo_size - can_write;
364 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
365 __func__, can_write);
366
367 if (can_write <= 0) {
368 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
369 return -ENOSPC;
370 }
371 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
372 can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index));
373
374 can_write &= 0xffff;
375 can_write *= 4;
376 } else {
377 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
378 dev_dbg(hsotg->dev,
379 "%s: no queue slots available (0x%08x)\n",
380 __func__, gnptxsts);
381
382 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
383 return -ENOSPC;
384 }
385
386 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
387 can_write *= 4; /* fifo size is in 32bit quantities. */
388 }
389
390 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
391
392 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
393 __func__, gnptxsts, can_write, to_write, max_transfer);
394
395 /*
396 * limit to 512 bytes of data, it seems at least on the non-periodic
397 * FIFO, requests of >512 cause the endpoint to get stuck with a
398 * fragment of the end of the transfer in it.
399 */
400 if (can_write > 512 && !periodic)
401 can_write = 512;
402
403 /*
404 * limit the write to one max-packet size worth of data, but allow
405 * the transfer to return that it did not run out of fifo space
406 * doing it.
407 */
408 if (to_write > max_transfer) {
409 to_write = max_transfer;
410
411 /* it's needed only when we do not use dedicated fifos */
412 if (!hsotg->dedicated_fifos)
413 dwc2_hsotg_en_gsint(hsotg,
414 periodic ? GINTSTS_PTXFEMP :
415 GINTSTS_NPTXFEMP);
416 }
417
418 /* see if we can write data */
419
420 if (to_write > can_write) {
421 to_write = can_write;
422 pkt_round = to_write % max_transfer;
423
424 /*
425 * Round the write down to an
426 * exact number of packets.
427 *
428 * Note, we do not currently check to see if we can ever
429 * write a full packet or not to the FIFO.
430 */
431
432 if (pkt_round)
433 to_write -= pkt_round;
434
435 /*
436 * enable correct FIFO interrupt to alert us when there
437 * is more room left.
438 */
439
440 /* it's needed only when we do not use dedicated fifos */
441 if (!hsotg->dedicated_fifos)
442 dwc2_hsotg_en_gsint(hsotg,
443 periodic ? GINTSTS_PTXFEMP :
444 GINTSTS_NPTXFEMP);
445 }
446
447 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
448 to_write, hs_req->req.length, can_write, buf_pos);
449
450 if (to_write <= 0)
451 return -ENOSPC;
452
453 hs_req->req.actual = buf_pos + to_write;
454 hs_ep->total_data += to_write;
455
456 if (periodic)
457 hs_ep->fifo_load += to_write;
458
459 to_write = DIV_ROUND_UP(to_write, 4);
460 data = hs_req->req.buf + buf_pos;
461
462 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
463
464 return (to_write >= can_write) ? -ENOSPC : 0;
465}
466
467/**
468 * get_ep_limit - get the maximum data legnth for this endpoint
469 * @hs_ep: The endpoint
470 *
471 * Return the maximum data that can be queued in one go on a given endpoint
472 * so that transfers that are too long can be split.
473 */
474static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
475{
476 int index = hs_ep->index;
477 unsigned maxsize;
478 unsigned maxpkt;
479
480 if (index != 0) {
481 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
482 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
483 } else {
484 maxsize = 64+64;
485 if (hs_ep->dir_in)
486 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
487 else
488 maxpkt = 2;
489 }
490
491 /* we made the constant loading easier above by using +1 */
492 maxpkt--;
493 maxsize--;
494
495 /*
496 * constrain by packet count if maxpkts*pktsize is greater
497 * than the length register size.
498 */
499
500 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
501 maxsize = maxpkt * hs_ep->ep.maxpacket;
502
503 return maxsize;
504}
505
506/**
507 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
508 * @hsotg: The controller state.
509 * @hs_ep: The endpoint to process a request for
510 * @hs_req: The request to start.
511 * @continuing: True if we are doing more for the current request.
512 *
513 * Start the given request running by setting the endpoint registers
514 * appropriately, and writing any data to the FIFOs.
515 */
516static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
517 struct dwc2_hsotg_ep *hs_ep,
518 struct dwc2_hsotg_req *hs_req,
519 bool continuing)
520{
521 struct usb_request *ureq = &hs_req->req;
522 int index = hs_ep->index;
523 int dir_in = hs_ep->dir_in;
524 u32 epctrl_reg;
525 u32 epsize_reg;
526 u32 epsize;
527 u32 ctrl;
528 unsigned length;
529 unsigned packets;
530 unsigned maxreq;
531
532 if (index != 0) {
533 if (hs_ep->req && !continuing) {
534 dev_err(hsotg->dev, "%s: active request\n", __func__);
535 WARN_ON(1);
536 return;
537 } else if (hs_ep->req != hs_req && continuing) {
538 dev_err(hsotg->dev,
539 "%s: continue different req\n", __func__);
540 WARN_ON(1);
541 return;
542 }
543 }
544
545 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
546 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
547
548 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
549 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
550 hs_ep->dir_in ? "in" : "out");
551
552 /* If endpoint is stalled, we will restart request later */
553 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
554
555 if (index && ctrl & DXEPCTL_STALL) {
556 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
557 return;
558 }
559
560 length = ureq->length - ureq->actual;
561 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
562 ureq->length, ureq->actual);
563
564 maxreq = get_ep_limit(hs_ep);
565 if (length > maxreq) {
566 int round = maxreq % hs_ep->ep.maxpacket;
567
568 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
569 __func__, length, maxreq, round);
570
571 /* round down to multiple of packets */
572 if (round)
573 maxreq -= round;
574
575 length = maxreq;
576 }
577
578 if (length)
579 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
580 else
581 packets = 1; /* send one packet if length is zero. */
582
583 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
584 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
585 return;
586 }
587
588 if (dir_in && index != 0)
589 if (hs_ep->isochronous)
590 epsize = DXEPTSIZ_MC(packets);
591 else
592 epsize = DXEPTSIZ_MC(1);
593 else
594 epsize = 0;
595
596 /*
597 * zero length packet should be programmed on its own and should not
598 * be counted in DIEPTSIZ.PktCnt with other packets.
599 */
600 if (dir_in && ureq->zero && !continuing) {
601 /* Test if zlp is actually required. */
602 if ((ureq->length >= hs_ep->ep.maxpacket) &&
603 !(ureq->length % hs_ep->ep.maxpacket))
604 hs_ep->send_zlp = 1;
605 }
606
607 epsize |= DXEPTSIZ_PKTCNT(packets);
608 epsize |= DXEPTSIZ_XFERSIZE(length);
609
610 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
611 __func__, packets, length, ureq->length, epsize, epsize_reg);
612
613 /* store the request as the current one we're doing */
614 hs_ep->req = hs_req;
615
616 /* write size / packets */
617 dwc2_writel(epsize, hsotg->regs + epsize_reg);
618
619 if (using_dma(hsotg) && !continuing) {
620 unsigned int dma_reg;
621
622 /*
623 * write DMA address to control register, buffer already
624 * synced by dwc2_hsotg_ep_queue().
625 */
626
627 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
628 dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
629
630 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
631 __func__, &ureq->dma, dma_reg);
632 }
633
634 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
635 ctrl |= DXEPCTL_USBACTEP;
636
637 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
638
639 /* For Setup request do not clear NAK */
640 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
641 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
642
643 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
644 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
645
646 /*
647 * set these, it seems that DMA support increments past the end
648 * of the packet buffer so we need to calculate the length from
649 * this information.
650 */
651 hs_ep->size_loaded = length;
652 hs_ep->last_load = ureq->actual;
653
654 if (dir_in && !using_dma(hsotg)) {
655 /* set these anyway, we may need them for non-periodic in */
656 hs_ep->fifo_load = 0;
657
658 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
659 }
660
661 /*
662 * clear the INTknTXFEmpMsk when we start request, more as a aide
663 * to debugging to see what is going on.
664 */
665 if (dir_in)
666 dwc2_writel(DIEPMSK_INTKNTXFEMPMSK,
667 hsotg->regs + DIEPINT(index));
668
669 /*
670 * Note, trying to clear the NAK here causes problems with transmit
671 * on the S3C6400 ending up with the TXFIFO becoming full.
672 */
673
674 /* check ep is enabled */
675 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
676 dev_dbg(hsotg->dev,
677 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
678 index, dwc2_readl(hsotg->regs + epctrl_reg));
679
680 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
681 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
682
683 /* enable ep interrupts */
684 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
685}
686
687/**
688 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
689 * @hsotg: The device state.
690 * @hs_ep: The endpoint the request is on.
691 * @req: The request being processed.
692 *
693 * We've been asked to queue a request, so ensure that the memory buffer
694 * is correctly setup for DMA. If we've been passed an extant DMA address
695 * then ensure the buffer has been synced to memory. If our buffer has no
696 * DMA memory, then we map the memory and mark our request to allow us to
697 * cleanup on completion.
698 */
699static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
700 struct dwc2_hsotg_ep *hs_ep,
701 struct usb_request *req)
702{
703 struct dwc2_hsotg_req *hs_req = our_req(req);
704 int ret;
705
706 /* if the length is zero, ignore the DMA data */
707 if (hs_req->req.length == 0)
708 return 0;
709
710 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
711 if (ret)
712 goto dma_error;
713
714 return 0;
715
716dma_error:
717 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
718 __func__, req->buf, req->length);
719
720 return -EIO;
721}
722
723static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
724 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
725{
726 void *req_buf = hs_req->req.buf;
727
728 /* If dma is not being used or buffer is aligned */
729 if (!using_dma(hsotg) || !((long)req_buf & 3))
730 return 0;
731
732 WARN_ON(hs_req->saved_req_buf);
733
734 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
735 hs_ep->ep.name, req_buf, hs_req->req.length);
736
737 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
738 if (!hs_req->req.buf) {
739 hs_req->req.buf = req_buf;
740 dev_err(hsotg->dev,
741 "%s: unable to allocate memory for bounce buffer\n",
742 __func__);
743 return -ENOMEM;
744 }
745
746 /* Save actual buffer */
747 hs_req->saved_req_buf = req_buf;
748
749 if (hs_ep->dir_in)
750 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
751 return 0;
752}
753
754static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
755 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
756{
757 /* If dma is not being used or buffer was aligned */
758 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
759 return;
760
761 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
762 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
763
764 /* Copy data from bounce buffer on successful out transfer */
765 if (!hs_ep->dir_in && !hs_req->req.status)
766 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
767 hs_req->req.actual);
768
769 /* Free bounce buffer */
770 kfree(hs_req->req.buf);
771
772 hs_req->req.buf = hs_req->saved_req_buf;
773 hs_req->saved_req_buf = NULL;
774}
775
776static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
777 gfp_t gfp_flags)
778{
779 struct dwc2_hsotg_req *hs_req = our_req(req);
780 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
781 struct dwc2_hsotg *hs = hs_ep->parent;
782 bool first;
783 int ret;
784
785 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
786 ep->name, req, req->length, req->buf, req->no_interrupt,
787 req->zero, req->short_not_ok);
788
789 /* Prevent new request submission when controller is suspended */
790 if (hs->lx_state == DWC2_L2) {
791 dev_dbg(hs->dev, "%s: don't submit request while suspended\n",
792 __func__);
793 return -EAGAIN;
794 }
795
796 /* initialise status of the request */
797 INIT_LIST_HEAD(&hs_req->queue);
798 req->actual = 0;
799 req->status = -EINPROGRESS;
800
801 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
802 if (ret)
803 return ret;
804
805 /* if we're using DMA, sync the buffers as necessary */
806 if (using_dma(hs)) {
807 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
808 if (ret)
809 return ret;
810 }
811
812 first = list_empty(&hs_ep->queue);
813 list_add_tail(&hs_req->queue, &hs_ep->queue);
814
815 if (first)
816 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
817
818 return 0;
819}
820
821static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
822 gfp_t gfp_flags)
823{
824 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
825 struct dwc2_hsotg *hs = hs_ep->parent;
826 unsigned long flags = 0;
827 int ret = 0;
828
829 spin_lock_irqsave(&hs->lock, flags);
830 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
831 spin_unlock_irqrestore(&hs->lock, flags);
832
833 return ret;
834}
835
836static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
837 struct usb_request *req)
838{
839 struct dwc2_hsotg_req *hs_req = our_req(req);
840
841 kfree(hs_req);
842}
843
844/**
845 * dwc2_hsotg_complete_oursetup - setup completion callback
846 * @ep: The endpoint the request was on.
847 * @req: The request completed.
848 *
849 * Called on completion of any requests the driver itself
850 * submitted that need cleaning up.
851 */
852static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
853 struct usb_request *req)
854{
855 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
856 struct dwc2_hsotg *hsotg = hs_ep->parent;
857
858 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
859
860 dwc2_hsotg_ep_free_request(ep, req);
861}
862
863/**
864 * ep_from_windex - convert control wIndex value to endpoint
865 * @hsotg: The driver state.
866 * @windex: The control request wIndex field (in host order).
867 *
868 * Convert the given wIndex into a pointer to an driver endpoint
869 * structure, or return NULL if it is not a valid endpoint.
870 */
871static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
872 u32 windex)
873{
874 struct dwc2_hsotg_ep *ep;
875 int dir = (windex & USB_DIR_IN) ? 1 : 0;
876 int idx = windex & 0x7F;
877
878 if (windex >= 0x100)
879 return NULL;
880
881 if (idx > hsotg->num_of_eps)
882 return NULL;
883
884 ep = index_to_ep(hsotg, idx, dir);
885
886 if (idx && ep->dir_in != dir)
887 return NULL;
888
889 return ep;
890}
891
892/**
893 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
894 * @hsotg: The driver state.
895 * @testmode: requested usb test mode
896 * Enable usb Test Mode requested by the Host.
897 */
898int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
899{
900 int dctl = dwc2_readl(hsotg->regs + DCTL);
901
902 dctl &= ~DCTL_TSTCTL_MASK;
903 switch (testmode) {
904 case TEST_J:
905 case TEST_K:
906 case TEST_SE0_NAK:
907 case TEST_PACKET:
908 case TEST_FORCE_EN:
909 dctl |= testmode << DCTL_TSTCTL_SHIFT;
910 break;
911 default:
912 return -EINVAL;
913 }
914 dwc2_writel(dctl, hsotg->regs + DCTL);
915 return 0;
916}
917
918/**
919 * dwc2_hsotg_send_reply - send reply to control request
920 * @hsotg: The device state
921 * @ep: Endpoint 0
922 * @buff: Buffer for request
923 * @length: Length of reply.
924 *
925 * Create a request and queue it on the given endpoint. This is useful as
926 * an internal method of sending replies to certain control requests, etc.
927 */
928static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
929 struct dwc2_hsotg_ep *ep,
930 void *buff,
931 int length)
932{
933 struct usb_request *req;
934 int ret;
935
936 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
937
938 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
939 hsotg->ep0_reply = req;
940 if (!req) {
941 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
942 return -ENOMEM;
943 }
944
945 req->buf = hsotg->ep0_buff;
946 req->length = length;
947 /*
948 * zero flag is for sending zlp in DATA IN stage. It has no impact on
949 * STATUS stage.
950 */
951 req->zero = 0;
952 req->complete = dwc2_hsotg_complete_oursetup;
953
954 if (length)
955 memcpy(req->buf, buff, length);
956
957 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
958 if (ret) {
959 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
960 return ret;
961 }
962
963 return 0;
964}
965
966/**
967 * dwc2_hsotg_process_req_status - process request GET_STATUS
968 * @hsotg: The device state
969 * @ctrl: USB control request
970 */
971static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
972 struct usb_ctrlrequest *ctrl)
973{
974 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
975 struct dwc2_hsotg_ep *ep;
976 __le16 reply;
977 int ret;
978
979 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
980
981 if (!ep0->dir_in) {
982 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
983 return -EINVAL;
984 }
985
986 switch (ctrl->bRequestType & USB_RECIP_MASK) {
987 case USB_RECIP_DEVICE:
988 reply = cpu_to_le16(0); /* bit 0 => self powered,
989 * bit 1 => remote wakeup */
990 break;
991
992 case USB_RECIP_INTERFACE:
993 /* currently, the data result should be zero */
994 reply = cpu_to_le16(0);
995 break;
996
997 case USB_RECIP_ENDPOINT:
998 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
999 if (!ep)
1000 return -ENOENT;
1001
1002 reply = cpu_to_le16(ep->halted ? 1 : 0);
1003 break;
1004
1005 default:
1006 return 0;
1007 }
1008
1009 if (le16_to_cpu(ctrl->wLength) != 2)
1010 return -EINVAL;
1011
1012 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1013 if (ret) {
1014 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1015 return ret;
1016 }
1017
1018 return 1;
1019}
1020
1021static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1022
1023/**
1024 * get_ep_head - return the first request on the endpoint
1025 * @hs_ep: The controller endpoint to get
1026 *
1027 * Get the first request on the endpoint.
1028 */
1029static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1030{
1031 if (list_empty(&hs_ep->queue))
1032 return NULL;
1033
1034 return list_first_entry(&hs_ep->queue, struct dwc2_hsotg_req, queue);
1035}
1036
1037/**
1038 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1039 * @hsotg: The device state
1040 * @ctrl: USB control request
1041 */
1042static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1043 struct usb_ctrlrequest *ctrl)
1044{
1045 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1046 struct dwc2_hsotg_req *hs_req;
1047 bool restart;
1048 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1049 struct dwc2_hsotg_ep *ep;
1050 int ret;
1051 bool halted;
1052 u32 recip;
1053 u32 wValue;
1054 u32 wIndex;
1055
1056 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1057 __func__, set ? "SET" : "CLEAR");
1058
1059 wValue = le16_to_cpu(ctrl->wValue);
1060 wIndex = le16_to_cpu(ctrl->wIndex);
1061 recip = ctrl->bRequestType & USB_RECIP_MASK;
1062
1063 switch (recip) {
1064 case USB_RECIP_DEVICE:
1065 switch (wValue) {
1066 case USB_DEVICE_TEST_MODE:
1067 if ((wIndex & 0xff) != 0)
1068 return -EINVAL;
1069 if (!set)
1070 return -EINVAL;
1071
1072 hsotg->test_mode = wIndex >> 8;
1073 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1074 if (ret) {
1075 dev_err(hsotg->dev,
1076 "%s: failed to send reply\n", __func__);
1077 return ret;
1078 }
1079 break;
1080 default:
1081 return -ENOENT;
1082 }
1083 break;
1084
1085 case USB_RECIP_ENDPOINT:
1086 ep = ep_from_windex(hsotg, wIndex);
1087 if (!ep) {
1088 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1089 __func__, wIndex);
1090 return -ENOENT;
1091 }
1092
1093 switch (wValue) {
1094 case USB_ENDPOINT_HALT:
1095 halted = ep->halted;
1096
1097 dwc2_hsotg_ep_sethalt(&ep->ep, set);
1098
1099 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1100 if (ret) {
1101 dev_err(hsotg->dev,
1102 "%s: failed to send reply\n", __func__);
1103 return ret;
1104 }
1105
1106 /*
1107 * we have to complete all requests for ep if it was
1108 * halted, and the halt was cleared by CLEAR_FEATURE
1109 */
1110
1111 if (!set && halted) {
1112 /*
1113 * If we have request in progress,
1114 * then complete it
1115 */
1116 if (ep->req) {
1117 hs_req = ep->req;
1118 ep->req = NULL;
1119 list_del_init(&hs_req->queue);
1120 if (hs_req->req.complete) {
1121 spin_unlock(&hsotg->lock);
1122 usb_gadget_giveback_request(
1123 &ep->ep, &hs_req->req);
1124 spin_lock(&hsotg->lock);
1125 }
1126 }
1127
1128 /* If we have pending request, then start it */
1129 if (!ep->req) {
1130 restart = !list_empty(&ep->queue);
1131 if (restart) {
1132 hs_req = get_ep_head(ep);
1133 dwc2_hsotg_start_req(hsotg, ep,
1134 hs_req, false);
1135 }
1136 }
1137 }
1138
1139 break;
1140
1141 default:
1142 return -ENOENT;
1143 }
1144 break;
1145 default:
1146 return -ENOENT;
1147 }
1148 return 1;
1149}
1150
1151static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1152
1153/**
1154 * dwc2_hsotg_stall_ep0 - stall ep0
1155 * @hsotg: The device state
1156 *
1157 * Set stall for ep0 as response for setup request.
1158 */
1159static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1160{
1161 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1162 u32 reg;
1163 u32 ctrl;
1164
1165 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1166 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1167
1168 /*
1169 * DxEPCTL_Stall will be cleared by EP once it has
1170 * taken effect, so no need to clear later.
1171 */
1172
1173 ctrl = dwc2_readl(hsotg->regs + reg);
1174 ctrl |= DXEPCTL_STALL;
1175 ctrl |= DXEPCTL_CNAK;
1176 dwc2_writel(ctrl, hsotg->regs + reg);
1177
1178 dev_dbg(hsotg->dev,
1179 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1180 ctrl, reg, dwc2_readl(hsotg->regs + reg));
1181
1182 /*
1183 * complete won't be called, so we enqueue
1184 * setup request here
1185 */
1186 dwc2_hsotg_enqueue_setup(hsotg);
1187}
1188
1189/**
1190 * dwc2_hsotg_process_control - process a control request
1191 * @hsotg: The device state
1192 * @ctrl: The control request received
1193 *
1194 * The controller has received the SETUP phase of a control request, and
1195 * needs to work out what to do next (and whether to pass it on to the
1196 * gadget driver).
1197 */
1198static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1199 struct usb_ctrlrequest *ctrl)
1200{
1201 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1202 int ret = 0;
1203 u32 dcfg;
1204
1205 dev_dbg(hsotg->dev,
1206 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1207 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1208 ctrl->wIndex, ctrl->wLength);
1209
1210 if (ctrl->wLength == 0) {
1211 ep0->dir_in = 1;
1212 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1213 } else if (ctrl->bRequestType & USB_DIR_IN) {
1214 ep0->dir_in = 1;
1215 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1216 } else {
1217 ep0->dir_in = 0;
1218 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1219 }
1220
1221 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1222 switch (ctrl->bRequest) {
1223 case USB_REQ_SET_ADDRESS:
1224 hsotg->connected = 1;
1225 dcfg = dwc2_readl(hsotg->regs + DCFG);
1226 dcfg &= ~DCFG_DEVADDR_MASK;
1227 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1228 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1229 dwc2_writel(dcfg, hsotg->regs + DCFG);
1230
1231 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1232
1233 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1234 return;
1235
1236 case USB_REQ_GET_STATUS:
1237 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1238 break;
1239
1240 case USB_REQ_CLEAR_FEATURE:
1241 case USB_REQ_SET_FEATURE:
1242 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1243 break;
1244 }
1245 }
1246
1247 /* as a fallback, try delivering it to the driver to deal with */
1248
1249 if (ret == 0 && hsotg->driver) {
1250 spin_unlock(&hsotg->lock);
1251 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1252 spin_lock(&hsotg->lock);
1253 if (ret < 0)
1254 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1255 }
1256
1257 /*
1258 * the request is either unhandlable, or is not formatted correctly
1259 * so respond with a STALL for the status stage to indicate failure.
1260 */
1261
1262 if (ret < 0)
1263 dwc2_hsotg_stall_ep0(hsotg);
1264}
1265
1266/**
1267 * dwc2_hsotg_complete_setup - completion of a setup transfer
1268 * @ep: The endpoint the request was on.
1269 * @req: The request completed.
1270 *
1271 * Called on completion of any requests the driver itself submitted for
1272 * EP0 setup packets
1273 */
1274static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1275 struct usb_request *req)
1276{
1277 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1278 struct dwc2_hsotg *hsotg = hs_ep->parent;
1279
1280 if (req->status < 0) {
1281 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1282 return;
1283 }
1284
1285 spin_lock(&hsotg->lock);
1286 if (req->actual == 0)
1287 dwc2_hsotg_enqueue_setup(hsotg);
1288 else
1289 dwc2_hsotg_process_control(hsotg, req->buf);
1290 spin_unlock(&hsotg->lock);
1291}
1292
1293/**
1294 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1295 * @hsotg: The device state.
1296 *
1297 * Enqueue a request on EP0 if necessary to received any SETUP packets
1298 * received from the host.
1299 */
1300static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1301{
1302 struct usb_request *req = hsotg->ctrl_req;
1303 struct dwc2_hsotg_req *hs_req = our_req(req);
1304 int ret;
1305
1306 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1307
1308 req->zero = 0;
1309 req->length = 8;
1310 req->buf = hsotg->ctrl_buff;
1311 req->complete = dwc2_hsotg_complete_setup;
1312
1313 if (!list_empty(&hs_req->queue)) {
1314 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1315 return;
1316 }
1317
1318 hsotg->eps_out[0]->dir_in = 0;
1319 hsotg->eps_out[0]->send_zlp = 0;
1320 hsotg->ep0_state = DWC2_EP0_SETUP;
1321
1322 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1323 if (ret < 0) {
1324 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1325 /*
1326 * Don't think there's much we can do other than watch the
1327 * driver fail.
1328 */
1329 }
1330}
1331
1332static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1333 struct dwc2_hsotg_ep *hs_ep)
1334{
1335 u32 ctrl;
1336 u8 index = hs_ep->index;
1337 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1338 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1339
1340 if (hs_ep->dir_in)
1341 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
1342 index);
1343 else
1344 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1345 index);
1346
1347 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1348 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1349 epsiz_reg);
1350
1351 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1352 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1353 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1354 ctrl |= DXEPCTL_USBACTEP;
1355 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1356}
1357
1358/**
1359 * dwc2_hsotg_complete_request - complete a request given to us
1360 * @hsotg: The device state.
1361 * @hs_ep: The endpoint the request was on.
1362 * @hs_req: The request to complete.
1363 * @result: The result code (0 => Ok, otherwise errno)
1364 *
1365 * The given request has finished, so call the necessary completion
1366 * if it has one and then look to see if we can start a new request
1367 * on the endpoint.
1368 *
1369 * Note, expects the ep to already be locked as appropriate.
1370 */
1371static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1372 struct dwc2_hsotg_ep *hs_ep,
1373 struct dwc2_hsotg_req *hs_req,
1374 int result)
1375{
1376 bool restart;
1377
1378 if (!hs_req) {
1379 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1380 return;
1381 }
1382
1383 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1384 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1385
1386 /*
1387 * only replace the status if we've not already set an error
1388 * from a previous transaction
1389 */
1390
1391 if (hs_req->req.status == -EINPROGRESS)
1392 hs_req->req.status = result;
1393
1394 if (using_dma(hsotg))
1395 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1396
1397 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
1398
1399 hs_ep->req = NULL;
1400 list_del_init(&hs_req->queue);
1401
1402 /*
1403 * call the complete request with the locks off, just in case the
1404 * request tries to queue more work for this endpoint.
1405 */
1406
1407 if (hs_req->req.complete) {
1408 spin_unlock(&hsotg->lock);
1409 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
1410 spin_lock(&hsotg->lock);
1411 }
1412
1413 /*
1414 * Look to see if there is anything else to do. Note, the completion
1415 * of the previous request may have caused a new request to be started
1416 * so be careful when doing this.
1417 */
1418
1419 if (!hs_ep->req && result >= 0) {
1420 restart = !list_empty(&hs_ep->queue);
1421 if (restart) {
1422 hs_req = get_ep_head(hs_ep);
1423 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1424 }
1425 }
1426}
1427
1428/**
1429 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
1430 * @hsotg: The device state.
1431 * @ep_idx: The endpoint index for the data
1432 * @size: The size of data in the fifo, in bytes
1433 *
1434 * The FIFO status shows there is data to read from the FIFO for a given
1435 * endpoint, so sort out whether we need to read the data into a request
1436 * that has been made for that endpoint.
1437 */
1438static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
1439{
1440 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
1441 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1442 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1443 int to_read;
1444 int max_req;
1445 int read_ptr;
1446
1447
1448 if (!hs_req) {
1449 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
1450 int ptr;
1451
1452 dev_dbg(hsotg->dev,
1453 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1454 __func__, size, ep_idx, epctl);
1455
1456 /* dump the data from the FIFO, we've nothing we can do */
1457 for (ptr = 0; ptr < size; ptr += 4)
1458 (void)dwc2_readl(fifo);
1459
1460 return;
1461 }
1462
1463 to_read = size;
1464 read_ptr = hs_req->req.actual;
1465 max_req = hs_req->req.length - read_ptr;
1466
1467 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1468 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1469
1470 if (to_read > max_req) {
1471 /*
1472 * more data appeared than we where willing
1473 * to deal with in this request.
1474 */
1475
1476 /* currently we don't deal this */
1477 WARN_ON_ONCE(1);
1478 }
1479
1480 hs_ep->total_data += to_read;
1481 hs_req->req.actual += to_read;
1482 to_read = DIV_ROUND_UP(to_read, 4);
1483
1484 /*
1485 * note, we might over-write the buffer end by 3 bytes depending on
1486 * alignment of the data.
1487 */
1488 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
1489}
1490
1491/**
1492 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
1493 * @hsotg: The device instance
1494 * @dir_in: If IN zlp
1495 *
1496 * Generate a zero-length IN packet request for terminating a SETUP
1497 * transaction.
1498 *
1499 * Note, since we don't write any data to the TxFIFO, then it is
1500 * currently believed that we do not need to wait for any space in
1501 * the TxFIFO.
1502 */
1503static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
1504{
1505 /* eps_out[0] is used in both directions */
1506 hsotg->eps_out[0]->dir_in = dir_in;
1507 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
1508
1509 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
1510}
1511
1512static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
1513 u32 epctl_reg)
1514{
1515 u32 ctrl;
1516
1517 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1518 if (ctrl & DXEPCTL_EOFRNUM)
1519 ctrl |= DXEPCTL_SETEVENFR;
1520 else
1521 ctrl |= DXEPCTL_SETODDFR;
1522 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1523}
1524
1525/**
1526 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1527 * @hsotg: The device instance
1528 * @epnum: The endpoint received from
1529 *
1530 * The RXFIFO has delivered an OutDone event, which means that the data
1531 * transfer for an OUT endpoint has been completed, either by a short
1532 * packet or by the finish of a transfer.
1533 */
1534static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
1535{
1536 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
1537 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
1538 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1539 struct usb_request *req = &hs_req->req;
1540 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1541 int result = 0;
1542
1543 if (!hs_req) {
1544 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1545 return;
1546 }
1547
1548 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
1549 dev_dbg(hsotg->dev, "zlp packet received\n");
1550 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1551 dwc2_hsotg_enqueue_setup(hsotg);
1552 return;
1553 }
1554
1555 if (using_dma(hsotg)) {
1556 unsigned size_done;
1557
1558 /*
1559 * Calculate the size of the transfer by checking how much
1560 * is left in the endpoint size register and then working it
1561 * out from the amount we loaded for the transfer.
1562 *
1563 * We need to do this as DMA pointers are always 32bit aligned
1564 * so may overshoot/undershoot the transfer.
1565 */
1566
1567 size_done = hs_ep->size_loaded - size_left;
1568 size_done += hs_ep->last_load;
1569
1570 req->actual = size_done;
1571 }
1572
1573 /* if there is more request to do, schedule new transfer */
1574 if (req->actual < req->length && size_left == 0) {
1575 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1576 return;
1577 }
1578
1579 if (req->actual < req->length && req->short_not_ok) {
1580 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1581 __func__, req->actual, req->length);
1582
1583 /*
1584 * todo - what should we return here? there's no one else
1585 * even bothering to check the status.
1586 */
1587 }
1588
1589 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
1590 /* Move to STATUS IN */
1591 dwc2_hsotg_ep0_zlp(hsotg, true);
1592 return;
1593 }
1594
1595 /*
1596 * Slave mode OUT transfers do not go through XferComplete so
1597 * adjust the ISOC parity here.
1598 */
1599 if (!using_dma(hsotg)) {
1600 hs_ep->has_correct_parity = 1;
1601 if (hs_ep->isochronous && hs_ep->interval == 1)
1602 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
1603 }
1604
1605 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1606}
1607
1608/**
1609 * dwc2_hsotg_read_frameno - read current frame number
1610 * @hsotg: The device instance
1611 *
1612 * Return the current frame number
1613 */
1614static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
1615{
1616 u32 dsts;
1617
1618 dsts = dwc2_readl(hsotg->regs + DSTS);
1619 dsts &= DSTS_SOFFN_MASK;
1620 dsts >>= DSTS_SOFFN_SHIFT;
1621
1622 return dsts;
1623}
1624
1625/**
1626 * dwc2_hsotg_handle_rx - RX FIFO has data
1627 * @hsotg: The device instance
1628 *
1629 * The IRQ handler has detected that the RX FIFO has some data in it
1630 * that requires processing, so find out what is in there and do the
1631 * appropriate read.
1632 *
1633 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1634 * chunks, so if you have x packets received on an endpoint you'll get x
1635 * FIFO events delivered, each with a packet's worth of data in it.
1636 *
1637 * When using DMA, we should not be processing events from the RXFIFO
1638 * as the actual data should be sent to the memory directly and we turn
1639 * on the completion interrupts to get notifications of transfer completion.
1640 */
1641static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
1642{
1643 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
1644 u32 epnum, status, size;
1645
1646 WARN_ON(using_dma(hsotg));
1647
1648 epnum = grxstsr & GRXSTS_EPNUM_MASK;
1649 status = grxstsr & GRXSTS_PKTSTS_MASK;
1650
1651 size = grxstsr & GRXSTS_BYTECNT_MASK;
1652 size >>= GRXSTS_BYTECNT_SHIFT;
1653
1654 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1655 __func__, grxstsr, size, epnum);
1656
1657 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
1658 case GRXSTS_PKTSTS_GLOBALOUTNAK:
1659 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
1660 break;
1661
1662 case GRXSTS_PKTSTS_OUTDONE:
1663 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1664 dwc2_hsotg_read_frameno(hsotg));
1665
1666 if (!using_dma(hsotg))
1667 dwc2_hsotg_handle_outdone(hsotg, epnum);
1668 break;
1669
1670 case GRXSTS_PKTSTS_SETUPDONE:
1671 dev_dbg(hsotg->dev,
1672 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1673 dwc2_hsotg_read_frameno(hsotg),
1674 dwc2_readl(hsotg->regs + DOEPCTL(0)));
1675 /*
1676 * Call dwc2_hsotg_handle_outdone here if it was not called from
1677 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
1678 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
1679 */
1680 if (hsotg->ep0_state == DWC2_EP0_SETUP)
1681 dwc2_hsotg_handle_outdone(hsotg, epnum);
1682 break;
1683
1684 case GRXSTS_PKTSTS_OUTRX:
1685 dwc2_hsotg_rx_data(hsotg, epnum, size);
1686 break;
1687
1688 case GRXSTS_PKTSTS_SETUPRX:
1689 dev_dbg(hsotg->dev,
1690 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1691 dwc2_hsotg_read_frameno(hsotg),
1692 dwc2_readl(hsotg->regs + DOEPCTL(0)));
1693
1694 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
1695
1696 dwc2_hsotg_rx_data(hsotg, epnum, size);
1697 break;
1698
1699 default:
1700 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1701 __func__, grxstsr);
1702
1703 dwc2_hsotg_dump(hsotg);
1704 break;
1705 }
1706}
1707
1708/**
1709 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
1710 * @mps: The maximum packet size in bytes.
1711 */
1712static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
1713{
1714 switch (mps) {
1715 case 64:
1716 return D0EPCTL_MPS_64;
1717 case 32:
1718 return D0EPCTL_MPS_32;
1719 case 16:
1720 return D0EPCTL_MPS_16;
1721 case 8:
1722 return D0EPCTL_MPS_8;
1723 }
1724
1725 /* bad max packet size, warn and return invalid result */
1726 WARN_ON(1);
1727 return (u32)-1;
1728}
1729
1730/**
1731 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1732 * @hsotg: The driver state.
1733 * @ep: The index number of the endpoint
1734 * @mps: The maximum packet size in bytes
1735 *
1736 * Configure the maximum packet size for the given endpoint, updating
1737 * the hardware control registers to reflect this.
1738 */
1739static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
1740 unsigned int ep, unsigned int mps, unsigned int dir_in)
1741{
1742 struct dwc2_hsotg_ep *hs_ep;
1743 void __iomem *regs = hsotg->regs;
1744 u32 mpsval;
1745 u32 mcval;
1746 u32 reg;
1747
1748 hs_ep = index_to_ep(hsotg, ep, dir_in);
1749 if (!hs_ep)
1750 return;
1751
1752 if (ep == 0) {
1753 /* EP0 is a special case */
1754 mpsval = dwc2_hsotg_ep0_mps(mps);
1755 if (mpsval > 3)
1756 goto bad_mps;
1757 hs_ep->ep.maxpacket = mps;
1758 hs_ep->mc = 1;
1759 } else {
1760 mpsval = mps & DXEPCTL_MPS_MASK;
1761 if (mpsval > 1024)
1762 goto bad_mps;
1763 mcval = ((mps >> 11) & 0x3) + 1;
1764 hs_ep->mc = mcval;
1765 if (mcval > 3)
1766 goto bad_mps;
1767 hs_ep->ep.maxpacket = mpsval;
1768 }
1769
1770 if (dir_in) {
1771 reg = dwc2_readl(regs + DIEPCTL(ep));
1772 reg &= ~DXEPCTL_MPS_MASK;
1773 reg |= mpsval;
1774 dwc2_writel(reg, regs + DIEPCTL(ep));
1775 } else {
1776 reg = dwc2_readl(regs + DOEPCTL(ep));
1777 reg &= ~DXEPCTL_MPS_MASK;
1778 reg |= mpsval;
1779 dwc2_writel(reg, regs + DOEPCTL(ep));
1780 }
1781
1782 return;
1783
1784bad_mps:
1785 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1786}
1787
1788/**
1789 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
1790 * @hsotg: The driver state
1791 * @idx: The index for the endpoint (0..15)
1792 */
1793static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
1794{
1795 int timeout;
1796 int val;
1797
1798 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1799 hsotg->regs + GRSTCTL);
1800
1801 /* wait until the fifo is flushed */
1802 timeout = 100;
1803
1804 while (1) {
1805 val = dwc2_readl(hsotg->regs + GRSTCTL);
1806
1807 if ((val & (GRSTCTL_TXFFLSH)) == 0)
1808 break;
1809
1810 if (--timeout == 0) {
1811 dev_err(hsotg->dev,
1812 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1813 __func__, val);
1814 break;
1815 }
1816
1817 udelay(1);
1818 }
1819}
1820
1821/**
1822 * dwc2_hsotg_trytx - check to see if anything needs transmitting
1823 * @hsotg: The driver state
1824 * @hs_ep: The driver endpoint to check.
1825 *
1826 * Check to see if there is a request that has data to send, and if so
1827 * make an attempt to write data into the FIFO.
1828 */
1829static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
1830 struct dwc2_hsotg_ep *hs_ep)
1831{
1832 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1833
1834 if (!hs_ep->dir_in || !hs_req) {
1835 /**
1836 * if request is not enqueued, we disable interrupts
1837 * for endpoints, excepting ep0
1838 */
1839 if (hs_ep->index != 0)
1840 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
1841 hs_ep->dir_in, 0);
1842 return 0;
1843 }
1844
1845 if (hs_req->req.actual < hs_req->req.length) {
1846 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1847 hs_ep->index);
1848 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1849 }
1850
1851 return 0;
1852}
1853
1854/**
1855 * dwc2_hsotg_complete_in - complete IN transfer
1856 * @hsotg: The device state.
1857 * @hs_ep: The endpoint that has just completed.
1858 *
1859 * An IN transfer has been completed, update the transfer's state and then
1860 * call the relevant completion routines.
1861 */
1862static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
1863 struct dwc2_hsotg_ep *hs_ep)
1864{
1865 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1866 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1867 int size_left, size_done;
1868
1869 if (!hs_req) {
1870 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1871 return;
1872 }
1873
1874 /* Finish ZLP handling for IN EP0 transactions */
1875 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
1876 dev_dbg(hsotg->dev, "zlp packet sent\n");
1877 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1878 if (hsotg->test_mode) {
1879 int ret;
1880
1881 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
1882 if (ret < 0) {
1883 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
1884 hsotg->test_mode);
1885 dwc2_hsotg_stall_ep0(hsotg);
1886 return;
1887 }
1888 }
1889 dwc2_hsotg_enqueue_setup(hsotg);
1890 return;
1891 }
1892
1893 /*
1894 * Calculate the size of the transfer by checking how much is left
1895 * in the endpoint size register and then working it out from
1896 * the amount we loaded for the transfer.
1897 *
1898 * We do this even for DMA, as the transfer may have incremented
1899 * past the end of the buffer (DMA transfers are always 32bit
1900 * aligned).
1901 */
1902
1903 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1904
1905 size_done = hs_ep->size_loaded - size_left;
1906 size_done += hs_ep->last_load;
1907
1908 if (hs_req->req.actual != size_done)
1909 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1910 __func__, hs_req->req.actual, size_done);
1911
1912 hs_req->req.actual = size_done;
1913 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1914 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1915
1916 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1917 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1918 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1919 return;
1920 }
1921
1922 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
1923 if (hs_ep->send_zlp) {
1924 dwc2_hsotg_program_zlp(hsotg, hs_ep);
1925 hs_ep->send_zlp = 0;
1926 /* transfer will be completed on next complete interrupt */
1927 return;
1928 }
1929
1930 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
1931 /* Move to STATUS OUT */
1932 dwc2_hsotg_ep0_zlp(hsotg, false);
1933 return;
1934 }
1935
1936 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1937}
1938
1939/**
1940 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
1941 * @hsotg: The driver state
1942 * @idx: The index for the endpoint (0..15)
1943 * @dir_in: Set if this is an IN endpoint
1944 *
1945 * Process and clear any interrupt pending for an individual endpoint
1946 */
1947static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
1948 int dir_in)
1949{
1950 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
1951 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1952 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1953 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1954 u32 ints;
1955 u32 ctrl;
1956
1957 ints = dwc2_readl(hsotg->regs + epint_reg);
1958 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1959
1960 /* Clear endpoint interrupts */
1961 dwc2_writel(ints, hsotg->regs + epint_reg);
1962
1963 if (!hs_ep) {
1964 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
1965 __func__, idx, dir_in ? "in" : "out");
1966 return;
1967 }
1968
1969 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1970 __func__, idx, dir_in ? "in" : "out", ints);
1971
1972 /* Don't process XferCompl interrupt if it is a setup packet */
1973 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
1974 ints &= ~DXEPINT_XFERCOMPL;
1975
1976 if (ints & DXEPINT_XFERCOMPL) {
1977 hs_ep->has_correct_parity = 1;
1978 if (hs_ep->isochronous && hs_ep->interval == 1)
1979 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
1980
1981 dev_dbg(hsotg->dev,
1982 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
1983 __func__, dwc2_readl(hsotg->regs + epctl_reg),
1984 dwc2_readl(hsotg->regs + epsiz_reg));
1985
1986 /*
1987 * we get OutDone from the FIFO, so we only need to look
1988 * at completing IN requests here
1989 */
1990 if (dir_in) {
1991 dwc2_hsotg_complete_in(hsotg, hs_ep);
1992
1993 if (idx == 0 && !hs_ep->req)
1994 dwc2_hsotg_enqueue_setup(hsotg);
1995 } else if (using_dma(hsotg)) {
1996 /*
1997 * We're using DMA, we need to fire an OutDone here
1998 * as we ignore the RXFIFO.
1999 */
2000
2001 dwc2_hsotg_handle_outdone(hsotg, idx);
2002 }
2003 }
2004
2005 if (ints & DXEPINT_EPDISBLD) {
2006 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2007
2008 if (dir_in) {
2009 int epctl = dwc2_readl(hsotg->regs + epctl_reg);
2010
2011 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2012
2013 if ((epctl & DXEPCTL_STALL) &&
2014 (epctl & DXEPCTL_EPTYPE_BULK)) {
2015 int dctl = dwc2_readl(hsotg->regs + DCTL);
2016
2017 dctl |= DCTL_CGNPINNAK;
2018 dwc2_writel(dctl, hsotg->regs + DCTL);
2019 }
2020 }
2021 }
2022
2023 if (ints & DXEPINT_AHBERR)
2024 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2025
2026 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
2027 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2028
2029 if (using_dma(hsotg) && idx == 0) {
2030 /*
2031 * this is the notification we've received a
2032 * setup packet. In non-DMA mode we'd get this
2033 * from the RXFIFO, instead we need to process
2034 * the setup here.
2035 */
2036
2037 if (dir_in)
2038 WARN_ON_ONCE(1);
2039 else
2040 dwc2_hsotg_handle_outdone(hsotg, 0);
2041 }
2042 }
2043
2044 if (ints & DXEPINT_BACK2BACKSETUP)
2045 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2046
2047 if (dir_in && !hs_ep->isochronous) {
2048 /* not sure if this is important, but we'll clear it anyway */
2049 if (ints & DIEPMSK_INTKNTXFEMPMSK) {
2050 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2051 __func__, idx);
2052 }
2053
2054 /* this probably means something bad is happening */
2055 if (ints & DIEPMSK_INTKNEPMISMSK) {
2056 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2057 __func__, idx);
2058 }
2059
2060 /* FIFO has space or is empty (see GAHBCFG) */
2061 if (hsotg->dedicated_fifos &&
2062 ints & DIEPMSK_TXFIFOEMPTY) {
2063 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2064 __func__, idx);
2065 if (!using_dma(hsotg))
2066 dwc2_hsotg_trytx(hsotg, hs_ep);
2067 }
2068 }
2069}
2070
2071/**
2072 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2073 * @hsotg: The device state.
2074 *
2075 * Handle updating the device settings after the enumeration phase has
2076 * been completed.
2077 */
2078static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
2079{
2080 u32 dsts = dwc2_readl(hsotg->regs + DSTS);
2081 int ep0_mps = 0, ep_mps = 8;
2082
2083 /*
2084 * This should signal the finish of the enumeration phase
2085 * of the USB handshaking, so we should now know what rate
2086 * we connected at.
2087 */
2088
2089 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
2090
2091 /*
2092 * note, since we're limited by the size of transfer on EP0, and
2093 * it seems IN transfers must be a even number of packets we do
2094 * not advertise a 64byte MPS on EP0.
2095 */
2096
2097 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2098 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
2099 case DSTS_ENUMSPD_FS:
2100 case DSTS_ENUMSPD_FS48:
2101 hsotg->gadget.speed = USB_SPEED_FULL;
2102 ep0_mps = EP0_MPS_LIMIT;
2103 ep_mps = 1023;
2104 break;
2105
2106 case DSTS_ENUMSPD_HS:
2107 hsotg->gadget.speed = USB_SPEED_HIGH;
2108 ep0_mps = EP0_MPS_LIMIT;
2109 ep_mps = 1024;
2110 break;
2111
2112 case DSTS_ENUMSPD_LS:
2113 hsotg->gadget.speed = USB_SPEED_LOW;
2114 /*
2115 * note, we don't actually support LS in this driver at the
2116 * moment, and the documentation seems to imply that it isn't
2117 * supported by the PHYs on some of the devices.
2118 */
2119 break;
2120 }
2121 dev_info(hsotg->dev, "new device is %s\n",
2122 usb_speed_string(hsotg->gadget.speed));
2123
2124 /*
2125 * we should now know the maximum packet size for an
2126 * endpoint, so set the endpoints to a default value.
2127 */
2128
2129 if (ep0_mps) {
2130 int i;
2131 /* Initialize ep0 for both in and out directions */
2132 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1);
2133 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0);
2134 for (i = 1; i < hsotg->num_of_eps; i++) {
2135 if (hsotg->eps_in[i])
2136 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1);
2137 if (hsotg->eps_out[i])
2138 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0);
2139 }
2140 }
2141
2142 /* ensure after enumeration our EP0 is active */
2143
2144 dwc2_hsotg_enqueue_setup(hsotg);
2145
2146 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2147 dwc2_readl(hsotg->regs + DIEPCTL0),
2148 dwc2_readl(hsotg->regs + DOEPCTL0));
2149}
2150
2151/**
2152 * kill_all_requests - remove all requests from the endpoint's queue
2153 * @hsotg: The device state.
2154 * @ep: The endpoint the requests may be on.
2155 * @result: The result code to use.
2156 *
2157 * Go through the requests on the given endpoint and mark them
2158 * completed with the given result code.
2159 */
2160static void kill_all_requests(struct dwc2_hsotg *hsotg,
2161 struct dwc2_hsotg_ep *ep,
2162 int result)
2163{
2164 struct dwc2_hsotg_req *req, *treq;
2165 unsigned size;
2166
2167 ep->req = NULL;
2168
2169 list_for_each_entry_safe(req, treq, &ep->queue, queue)
2170 dwc2_hsotg_complete_request(hsotg, ep, req,
2171 result);
2172
2173 if (!hsotg->dedicated_fifos)
2174 return;
2175 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
2176 if (size < ep->fifo_size)
2177 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
2178}
2179
2180/**
2181 * dwc2_hsotg_disconnect - disconnect service
2182 * @hsotg: The device state.
2183 *
2184 * The device has been disconnected. Remove all current
2185 * transactions and signal the gadget driver that this
2186 * has happened.
2187 */
2188void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
2189{
2190 unsigned ep;
2191
2192 if (!hsotg->connected)
2193 return;
2194
2195 hsotg->connected = 0;
2196 hsotg->test_mode = 0;
2197
2198 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
2199 if (hsotg->eps_in[ep])
2200 kill_all_requests(hsotg, hsotg->eps_in[ep],
2201 -ESHUTDOWN);
2202 if (hsotg->eps_out[ep])
2203 kill_all_requests(hsotg, hsotg->eps_out[ep],
2204 -ESHUTDOWN);
2205 }
2206
2207 call_gadget(hsotg, disconnect);
2208 hsotg->lx_state = DWC2_L3;
2209}
2210
2211/**
2212 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2213 * @hsotg: The device state:
2214 * @periodic: True if this is a periodic FIFO interrupt
2215 */
2216static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
2217{
2218 struct dwc2_hsotg_ep *ep;
2219 int epno, ret;
2220
2221 /* look through for any more data to transmit */
2222 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2223 ep = index_to_ep(hsotg, epno, 1);
2224
2225 if (!ep)
2226 continue;
2227
2228 if (!ep->dir_in)
2229 continue;
2230
2231 if ((periodic && !ep->periodic) ||
2232 (!periodic && ep->periodic))
2233 continue;
2234
2235 ret = dwc2_hsotg_trytx(hsotg, ep);
2236 if (ret < 0)
2237 break;
2238 }
2239}
2240
2241/* IRQ flags which will trigger a retry around the IRQ loop */
2242#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2243 GINTSTS_PTXFEMP | \
2244 GINTSTS_RXFLVL)
2245
2246/**
2247 * dwc2_hsotg_core_init - issue softreset to the core
2248 * @hsotg: The device state
2249 *
2250 * Issue a soft reset to the core, and await the core finishing it.
2251 */
2252void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
2253 bool is_usb_reset)
2254{
2255 u32 intmsk;
2256 u32 val;
2257 u32 usbcfg;
2258
2259 /* Kill any ep0 requests as controller will be reinitialized */
2260 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
2261
2262 if (!is_usb_reset)
2263 if (dwc2_core_reset(hsotg))
2264 return;
2265
2266 /*
2267 * we must now enable ep0 ready for host detection and then
2268 * set configuration.
2269 */
2270
2271 /* keep other bits untouched (so e.g. forced modes are not lost) */
2272 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2273 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
2274 GUSBCFG_HNPCAP);
2275
2276 /* set the PLL on, remove the HNP/SRP and set the PHY */
2277 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
2278 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
2279 (val << GUSBCFG_USBTRDTIM_SHIFT);
2280 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2281
2282 dwc2_hsotg_init_fifo(hsotg);
2283
2284 if (!is_usb_reset)
2285 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2286
2287 dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
2288
2289 /* Clear any pending OTG interrupts */
2290 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
2291
2292 /* Clear any pending interrupts */
2293 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
2294 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
2295 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
2296 GINTSTS_USBRST | GINTSTS_RESETDET |
2297 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
2298 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
2299 GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
2300
2301 if (hsotg->core_params->external_id_pin_ctl <= 0)
2302 intmsk |= GINTSTS_CONIDSTSCHNG;
2303
2304 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
2305
2306 if (using_dma(hsotg))
2307 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
2308 (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT),
2309 hsotg->regs + GAHBCFG);
2310 else
2311 dwc2_writel(((hsotg->dedicated_fifos) ?
2312 (GAHBCFG_NP_TXF_EMP_LVL |
2313 GAHBCFG_P_TXF_EMP_LVL) : 0) |
2314 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
2315
2316 /*
2317 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2318 * when we have no data to transfer. Otherwise we get being flooded by
2319 * interrupts.
2320 */
2321
2322 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
2323 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
2324 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
2325 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2326 DIEPMSK_INTKNEPMISMSK,
2327 hsotg->regs + DIEPMSK);
2328
2329 /*
2330 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2331 * DMA mode we may need this.
2332 */
2333 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
2334 DIEPMSK_TIMEOUTMSK) : 0) |
2335 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
2336 DOEPMSK_SETUPMSK,
2337 hsotg->regs + DOEPMSK);
2338
2339 dwc2_writel(0, hsotg->regs + DAINTMSK);
2340
2341 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2342 dwc2_readl(hsotg->regs + DIEPCTL0),
2343 dwc2_readl(hsotg->regs + DOEPCTL0));
2344
2345 /* enable in and out endpoint interrupts */
2346 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
2347
2348 /*
2349 * Enable the RXFIFO when in slave mode, as this is how we collect
2350 * the data. In DMA mode, we get events from the FIFO but also
2351 * things we cannot process, so do not use it.
2352 */
2353 if (!using_dma(hsotg))
2354 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
2355
2356 /* Enable interrupts for EP0 in and out */
2357 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2358 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2359
2360 if (!is_usb_reset) {
2361 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2362 udelay(10); /* see openiboot */
2363 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2364 }
2365
2366 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
2367
2368 /*
2369 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2370 * writing to the EPCTL register..
2371 */
2372
2373 /* set to read 1 8byte packet */
2374 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2375 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
2376
2377 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2378 DXEPCTL_CNAK | DXEPCTL_EPENA |
2379 DXEPCTL_USBACTEP,
2380 hsotg->regs + DOEPCTL0);
2381
2382 /* enable, but don't activate EP0in */
2383 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2384 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
2385
2386 dwc2_hsotg_enqueue_setup(hsotg);
2387
2388 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2389 dwc2_readl(hsotg->regs + DIEPCTL0),
2390 dwc2_readl(hsotg->regs + DOEPCTL0));
2391
2392 /* clear global NAKs */
2393 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
2394 if (!is_usb_reset)
2395 val |= DCTL_SFTDISCON;
2396 __orr32(hsotg->regs + DCTL, val);
2397
2398 /* must be at-least 3ms to allow bus to see disconnect */
2399 mdelay(3);
2400
2401 hsotg->lx_state = DWC2_L0;
2402}
2403
2404static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
2405{
2406 /* set the soft-disconnect bit */
2407 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2408}
2409
2410void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
2411{
2412 /* remove the soft-disconnect and let's go */
2413 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2414}
2415
2416/**
2417 * dwc2_hsotg_irq - handle device interrupt
2418 * @irq: The IRQ number triggered
2419 * @pw: The pw value when registered the handler.
2420 */
2421static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
2422{
2423 struct dwc2_hsotg *hsotg = pw;
2424 int retry_count = 8;
2425 u32 gintsts;
2426 u32 gintmsk;
2427
2428 spin_lock(&hsotg->lock);
2429irq_retry:
2430 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
2431 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2432
2433 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2434 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2435
2436 gintsts &= gintmsk;
2437
2438 if (gintsts & GINTSTS_RESETDET) {
2439 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
2440
2441 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
2442
2443 /* This event must be used only if controller is suspended */
2444 if (hsotg->lx_state == DWC2_L2) {
2445 dwc2_exit_hibernation(hsotg, true);
2446 hsotg->lx_state = DWC2_L0;
2447 }
2448 }
2449
2450 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
2451
2452 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
2453 u32 connected = hsotg->connected;
2454
2455 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
2456 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2457 dwc2_readl(hsotg->regs + GNPTXSTS));
2458
2459 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
2460
2461 /* Report disconnection if it is not already done. */
2462 dwc2_hsotg_disconnect(hsotg);
2463
2464 if (usb_status & GOTGCTL_BSESVLD && connected)
2465 dwc2_hsotg_core_init_disconnected(hsotg, true);
2466 }
2467
2468 if (gintsts & GINTSTS_ENUMDONE) {
2469 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
2470
2471 dwc2_hsotg_irq_enumdone(hsotg);
2472 }
2473
2474 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
2475 u32 daint = dwc2_readl(hsotg->regs + DAINT);
2476 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
2477 u32 daint_out, daint_in;
2478 int ep;
2479
2480 daint &= daintmsk;
2481 daint_out = daint >> DAINT_OUTEP_SHIFT;
2482 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
2483
2484 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2485
2486 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
2487 ep++, daint_out >>= 1) {
2488 if (daint_out & 1)
2489 dwc2_hsotg_epint(hsotg, ep, 0);
2490 }
2491
2492 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
2493 ep++, daint_in >>= 1) {
2494 if (daint_in & 1)
2495 dwc2_hsotg_epint(hsotg, ep, 1);
2496 }
2497 }
2498
2499 /* check both FIFOs */
2500
2501 if (gintsts & GINTSTS_NPTXFEMP) {
2502 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2503
2504 /*
2505 * Disable the interrupt to stop it happening again
2506 * unless one of these endpoint routines decides that
2507 * it needs re-enabling
2508 */
2509
2510 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
2511 dwc2_hsotg_irq_fifoempty(hsotg, false);
2512 }
2513
2514 if (gintsts & GINTSTS_PTXFEMP) {
2515 dev_dbg(hsotg->dev, "PTxFEmp\n");
2516
2517 /* See note in GINTSTS_NPTxFEmp */
2518
2519 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
2520 dwc2_hsotg_irq_fifoempty(hsotg, true);
2521 }
2522
2523 if (gintsts & GINTSTS_RXFLVL) {
2524 /*
2525 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2526 * we need to retry dwc2_hsotg_handle_rx if this is still
2527 * set.
2528 */
2529
2530 dwc2_hsotg_handle_rx(hsotg);
2531 }
2532
2533 if (gintsts & GINTSTS_ERLYSUSP) {
2534 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2535 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
2536 }
2537
2538 /*
2539 * these next two seem to crop-up occasionally causing the core
2540 * to shutdown the USB transfer, so try clearing them and logging
2541 * the occurrence.
2542 */
2543
2544 if (gintsts & GINTSTS_GOUTNAKEFF) {
2545 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2546
2547 __orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK);
2548
2549 dwc2_hsotg_dump(hsotg);
2550 }
2551
2552 if (gintsts & GINTSTS_GINNAKEFF) {
2553 dev_info(hsotg->dev, "GINNakEff triggered\n");
2554
2555 __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
2556
2557 dwc2_hsotg_dump(hsotg);
2558 }
2559
2560 if (gintsts & GINTSTS_INCOMPL_SOIN) {
2561 u32 idx, epctl_reg;
2562 struct dwc2_hsotg_ep *hs_ep;
2563
2564 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOIN\n", __func__);
2565 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
2566 hs_ep = hsotg->eps_in[idx];
2567
2568 if (!hs_ep->isochronous || hs_ep->has_correct_parity)
2569 continue;
2570
2571 epctl_reg = DIEPCTL(idx);
2572 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
2573 }
2574 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS);
2575 }
2576
2577 if (gintsts & GINTSTS_INCOMPL_SOOUT) {
2578 u32 idx, epctl_reg;
2579 struct dwc2_hsotg_ep *hs_ep;
2580
2581 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
2582 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
2583 hs_ep = hsotg->eps_out[idx];
2584
2585 if (!hs_ep->isochronous || hs_ep->has_correct_parity)
2586 continue;
2587
2588 epctl_reg = DOEPCTL(idx);
2589 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
2590 }
2591 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS);
2592 }
2593
2594 /*
2595 * if we've had fifo events, we should try and go around the
2596 * loop again to see if there's any point in returning yet.
2597 */
2598
2599 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2600 goto irq_retry;
2601
2602 spin_unlock(&hsotg->lock);
2603
2604 return IRQ_HANDLED;
2605}
2606
2607/**
2608 * dwc2_hsotg_ep_enable - enable the given endpoint
2609 * @ep: The USB endpint to configure
2610 * @desc: The USB endpoint descriptor to configure with.
2611 *
2612 * This is called from the USB gadget code's usb_ep_enable().
2613 */
2614static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
2615 const struct usb_endpoint_descriptor *desc)
2616{
2617 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2618 struct dwc2_hsotg *hsotg = hs_ep->parent;
2619 unsigned long flags;
2620 unsigned int index = hs_ep->index;
2621 u32 epctrl_reg;
2622 u32 epctrl;
2623 u32 mps;
2624 unsigned int dir_in;
2625 unsigned int i, val, size;
2626 int ret = 0;
2627
2628 dev_dbg(hsotg->dev,
2629 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2630 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2631 desc->wMaxPacketSize, desc->bInterval);
2632
2633 /* not to be called for EP0 */
2634 WARN_ON(index == 0);
2635
2636 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2637 if (dir_in != hs_ep->dir_in) {
2638 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2639 return -EINVAL;
2640 }
2641
2642 mps = usb_endpoint_maxp(desc);
2643
2644 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
2645
2646 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2647 epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2648
2649 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2650 __func__, epctrl, epctrl_reg);
2651
2652 spin_lock_irqsave(&hsotg->lock, flags);
2653
2654 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
2655 epctrl |= DXEPCTL_MPS(mps);
2656
2657 /*
2658 * mark the endpoint as active, otherwise the core may ignore
2659 * transactions entirely for this endpoint
2660 */
2661 epctrl |= DXEPCTL_USBACTEP;
2662
2663 /*
2664 * set the NAK status on the endpoint, otherwise we might try and
2665 * do something with data that we've yet got a request to process
2666 * since the RXFIFO will take data for an endpoint even if the
2667 * size register hasn't been set.
2668 */
2669
2670 epctrl |= DXEPCTL_SNAK;
2671
2672 /* update the endpoint state */
2673 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in);
2674
2675 /* default, set to non-periodic */
2676 hs_ep->isochronous = 0;
2677 hs_ep->periodic = 0;
2678 hs_ep->halted = 0;
2679 hs_ep->interval = desc->bInterval;
2680 hs_ep->has_correct_parity = 0;
2681
2682 if (hs_ep->interval > 1 && hs_ep->mc > 1)
2683 dev_err(hsotg->dev, "MC > 1 when interval is not 1\n");
2684
2685 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2686 case USB_ENDPOINT_XFER_ISOC:
2687 epctrl |= DXEPCTL_EPTYPE_ISO;
2688 epctrl |= DXEPCTL_SETEVENFR;
2689 hs_ep->isochronous = 1;
2690 if (dir_in)
2691 hs_ep->periodic = 1;
2692 break;
2693
2694 case USB_ENDPOINT_XFER_BULK:
2695 epctrl |= DXEPCTL_EPTYPE_BULK;
2696 break;
2697
2698 case USB_ENDPOINT_XFER_INT:
2699 if (dir_in)
2700 hs_ep->periodic = 1;
2701
2702 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
2703 break;
2704
2705 case USB_ENDPOINT_XFER_CONTROL:
2706 epctrl |= DXEPCTL_EPTYPE_CONTROL;
2707 break;
2708 }
2709
2710 /* If fifo is already allocated for this ep */
2711 if (hs_ep->fifo_index) {
2712 size = hs_ep->ep.maxpacket * hs_ep->mc;
2713 /* If bigger fifo is required deallocate current one */
2714 if (size > hs_ep->fifo_size) {
2715 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
2716 hs_ep->fifo_index = 0;
2717 hs_ep->fifo_size = 0;
2718 }
2719 }
2720
2721 /*
2722 * if the hardware has dedicated fifos, we must give each IN EP
2723 * a unique tx-fifo even if it is non-periodic.
2724 */
2725 if (dir_in && hsotg->dedicated_fifos && !hs_ep->fifo_index) {
2726 u32 fifo_index = 0;
2727 u32 fifo_size = UINT_MAX;
2728 size = hs_ep->ep.maxpacket*hs_ep->mc;
2729 for (i = 1; i < hsotg->num_of_eps; ++i) {
2730 if (hsotg->fifo_map & (1<<i))
2731 continue;
2732 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
2733 val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
2734 if (val < size)
2735 continue;
2736 /* Search for smallest acceptable fifo */
2737 if (val < fifo_size) {
2738 fifo_size = val;
2739 fifo_index = i;
2740 }
2741 }
2742 if (!fifo_index) {
2743 dev_err(hsotg->dev,
2744 "%s: No suitable fifo found\n", __func__);
2745 ret = -ENOMEM;
2746 goto error;
2747 }
2748 hsotg->fifo_map |= 1 << fifo_index;
2749 epctrl |= DXEPCTL_TXFNUM(fifo_index);
2750 hs_ep->fifo_index = fifo_index;
2751 hs_ep->fifo_size = fifo_size;
2752 }
2753
2754 /* for non control endpoints, set PID to D0 */
2755 if (index)
2756 epctrl |= DXEPCTL_SETD0PID;
2757
2758 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2759 __func__, epctrl);
2760
2761 dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
2762 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2763 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
2764
2765 /* enable the endpoint interrupt */
2766 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2767
2768error:
2769 spin_unlock_irqrestore(&hsotg->lock, flags);
2770 return ret;
2771}
2772
2773/**
2774 * dwc2_hsotg_ep_disable - disable given endpoint
2775 * @ep: The endpoint to disable.
2776 */
2777static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
2778{
2779 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2780 struct dwc2_hsotg *hsotg = hs_ep->parent;
2781 int dir_in = hs_ep->dir_in;
2782 int index = hs_ep->index;
2783 unsigned long flags;
2784 u32 epctrl_reg;
2785 u32 ctrl;
2786
2787 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2788
2789 if (ep == &hsotg->eps_out[0]->ep) {
2790 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2791 return -EINVAL;
2792 }
2793
2794 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2795
2796 spin_lock_irqsave(&hsotg->lock, flags);
2797
2798 hsotg->fifo_map &= ~(1<<hs_ep->fifo_index);
2799 hs_ep->fifo_index = 0;
2800 hs_ep->fifo_size = 0;
2801
2802 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2803 ctrl &= ~DXEPCTL_EPENA;
2804 ctrl &= ~DXEPCTL_USBACTEP;
2805 ctrl |= DXEPCTL_SNAK;
2806
2807 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2808 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
2809
2810 /* disable endpoint interrupts */
2811 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2812
2813 /* terminate all requests with shutdown */
2814 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
2815
2816 spin_unlock_irqrestore(&hsotg->lock, flags);
2817 return 0;
2818}
2819
2820/**
2821 * on_list - check request is on the given endpoint
2822 * @ep: The endpoint to check.
2823 * @test: The request to test if it is on the endpoint.
2824 */
2825static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
2826{
2827 struct dwc2_hsotg_req *req, *treq;
2828
2829 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2830 if (req == test)
2831 return true;
2832 }
2833
2834 return false;
2835}
2836
2837static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg,
2838 u32 bit, u32 timeout)
2839{
2840 u32 i;
2841
2842 for (i = 0; i < timeout; i++) {
2843 if (dwc2_readl(hs_otg->regs + reg) & bit)
2844 return 0;
2845 udelay(1);
2846 }
2847
2848 return -ETIMEDOUT;
2849}
2850
2851static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2852 struct dwc2_hsotg_ep *hs_ep)
2853{
2854 u32 epctrl_reg;
2855 u32 epint_reg;
2856
2857 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
2858 DOEPCTL(hs_ep->index);
2859 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
2860 DOEPINT(hs_ep->index);
2861
2862 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
2863 hs_ep->name);
2864 if (hs_ep->dir_in) {
2865 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
2866 /* Wait for Nak effect */
2867 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
2868 DXEPINT_INEPNAKEFF, 100))
2869 dev_warn(hsotg->dev,
2870 "%s: timeout DIEPINT.NAKEFF\n", __func__);
2871 } else {
2872 /* Clear any pending nak effect interrupt */
2873 dwc2_writel(GINTSTS_GOUTNAKEFF, hsotg->regs + GINTSTS);
2874
2875 __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
2876
2877 /* Wait for global nak to take effect */
2878 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
2879 GINTSTS_GOUTNAKEFF, 100))
2880 dev_warn(hsotg->dev,
2881 "%s: timeout GINTSTS.GOUTNAKEFF\n", __func__);
2882 }
2883
2884 /* Disable ep */
2885 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
2886
2887 /* Wait for ep to be disabled */
2888 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
2889 dev_warn(hsotg->dev,
2890 "%s: timeout DOEPCTL.EPDisable\n", __func__);
2891
2892 if (hs_ep->dir_in) {
2893 if (hsotg->dedicated_fifos) {
2894 dwc2_writel(GRSTCTL_TXFNUM(hs_ep->fifo_index) |
2895 GRSTCTL_TXFFLSH, hsotg->regs + GRSTCTL);
2896 /* Wait for fifo flush */
2897 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
2898 GRSTCTL_TXFFLSH, 100))
2899 dev_warn(hsotg->dev,
2900 "%s: timeout flushing fifos\n",
2901 __func__);
2902 }
2903 /* TODO: Flush shared tx fifo */
2904 } else {
2905 /* Remove global NAKs */
2906 __bic32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
2907 }
2908}
2909
2910/**
2911 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
2912 * @ep: The endpoint to dequeue.
2913 * @req: The request to be removed from a queue.
2914 */
2915static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2916{
2917 struct dwc2_hsotg_req *hs_req = our_req(req);
2918 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2919 struct dwc2_hsotg *hs = hs_ep->parent;
2920 unsigned long flags;
2921
2922 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2923
2924 spin_lock_irqsave(&hs->lock, flags);
2925
2926 if (!on_list(hs_ep, hs_req)) {
2927 spin_unlock_irqrestore(&hs->lock, flags);
2928 return -EINVAL;
2929 }
2930
2931 /* Dequeue already started request */
2932 if (req == &hs_ep->req->req)
2933 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
2934
2935 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2936 spin_unlock_irqrestore(&hs->lock, flags);
2937
2938 return 0;
2939}
2940
2941/**
2942 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
2943 * @ep: The endpoint to set halt.
2944 * @value: Set or unset the halt.
2945 */
2946static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2947{
2948 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2949 struct dwc2_hsotg *hs = hs_ep->parent;
2950 int index = hs_ep->index;
2951 u32 epreg;
2952 u32 epctl;
2953 u32 xfertype;
2954
2955 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2956
2957 if (index == 0) {
2958 if (value)
2959 dwc2_hsotg_stall_ep0(hs);
2960 else
2961 dev_warn(hs->dev,
2962 "%s: can't clear halt on ep0\n", __func__);
2963 return 0;
2964 }
2965
2966 if (hs_ep->dir_in) {
2967 epreg = DIEPCTL(index);
2968 epctl = dwc2_readl(hs->regs + epreg);
2969
2970 if (value) {
2971 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
2972 if (epctl & DXEPCTL_EPENA)
2973 epctl |= DXEPCTL_EPDIS;
2974 } else {
2975 epctl &= ~DXEPCTL_STALL;
2976 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2977 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2978 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2979 epctl |= DXEPCTL_SETD0PID;
2980 }
2981 dwc2_writel(epctl, hs->regs + epreg);
2982 } else {
2983
2984 epreg = DOEPCTL(index);
2985 epctl = dwc2_readl(hs->regs + epreg);
2986
2987 if (value)
2988 epctl |= DXEPCTL_STALL;
2989 else {
2990 epctl &= ~DXEPCTL_STALL;
2991 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2992 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2993 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2994 epctl |= DXEPCTL_SETD0PID;
2995 }
2996 dwc2_writel(epctl, hs->regs + epreg);
2997 }
2998
2999 hs_ep->halted = value;
3000
3001 return 0;
3002}
3003
3004/**
3005 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
3006 * @ep: The endpoint to set halt.
3007 * @value: Set or unset the halt.
3008 */
3009static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
3010{
3011 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3012 struct dwc2_hsotg *hs = hs_ep->parent;
3013 unsigned long flags = 0;
3014 int ret = 0;
3015
3016 spin_lock_irqsave(&hs->lock, flags);
3017 ret = dwc2_hsotg_ep_sethalt(ep, value);
3018 spin_unlock_irqrestore(&hs->lock, flags);
3019
3020 return ret;
3021}
3022
3023static struct usb_ep_ops dwc2_hsotg_ep_ops = {
3024 .enable = dwc2_hsotg_ep_enable,
3025 .disable = dwc2_hsotg_ep_disable,
3026 .alloc_request = dwc2_hsotg_ep_alloc_request,
3027 .free_request = dwc2_hsotg_ep_free_request,
3028 .queue = dwc2_hsotg_ep_queue_lock,
3029 .dequeue = dwc2_hsotg_ep_dequeue,
3030 .set_halt = dwc2_hsotg_ep_sethalt_lock,
3031 /* note, don't believe we have any call for the fifo routines */
3032};
3033
3034/**
3035 * dwc2_hsotg_init - initalize the usb core
3036 * @hsotg: The driver state
3037 */
3038static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
3039{
3040 u32 trdtim;
3041 u32 usbcfg;
3042 /* unmask subset of endpoint interrupts */
3043
3044 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
3045 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
3046 hsotg->regs + DIEPMSK);
3047
3048 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
3049 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
3050 hsotg->regs + DOEPMSK);
3051
3052 dwc2_writel(0, hsotg->regs + DAINTMSK);
3053
3054 /* Be in disconnected state until gadget is registered */
3055 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3056
3057 /* setup fifos */
3058
3059 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3060 dwc2_readl(hsotg->regs + GRXFSIZ),
3061 dwc2_readl(hsotg->regs + GNPTXFSIZ));
3062
3063 dwc2_hsotg_init_fifo(hsotg);
3064
3065 /* keep other bits untouched (so e.g. forced modes are not lost) */
3066 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3067 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3068 GUSBCFG_HNPCAP);
3069
3070 /* set the PLL on, remove the HNP/SRP and set the PHY */
3071 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3072 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3073 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
3074 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
3075
3076 if (using_dma(hsotg))
3077 __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
3078}
3079
3080/**
3081 * dwc2_hsotg_udc_start - prepare the udc for work
3082 * @gadget: The usb gadget state
3083 * @driver: The usb gadget driver
3084 *
3085 * Perform initialization to prepare udc device and driver
3086 * to work.
3087 */
3088static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
3089 struct usb_gadget_driver *driver)
3090{
3091 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3092 unsigned long flags;
3093 int ret;
3094
3095 if (!hsotg) {
3096 pr_err("%s: called with no device\n", __func__);
3097 return -ENODEV;
3098 }
3099
3100 if (!driver) {
3101 dev_err(hsotg->dev, "%s: no driver\n", __func__);
3102 return -EINVAL;
3103 }
3104
3105 if (driver->max_speed < USB_SPEED_FULL)
3106 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
3107
3108 if (!driver->setup) {
3109 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
3110 return -EINVAL;
3111 }
3112
3113 WARN_ON(hsotg->driver);
3114
3115 driver->driver.bus = NULL;
3116 hsotg->driver = driver;
3117 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
3118 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3119
3120 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
3121 ret = dwc2_lowlevel_hw_enable(hsotg);
3122 if (ret)
3123 goto err;
3124 }
3125
3126 if (!IS_ERR_OR_NULL(hsotg->uphy))
3127 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
3128
3129 spin_lock_irqsave(&hsotg->lock, flags);
3130 dwc2_hsotg_init(hsotg);
3131 dwc2_hsotg_core_init_disconnected(hsotg, false);
3132 hsotg->enabled = 0;
3133 spin_unlock_irqrestore(&hsotg->lock, flags);
3134
3135 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
3136
3137 return 0;
3138
3139err:
3140 hsotg->driver = NULL;
3141 return ret;
3142}
3143
3144/**
3145 * dwc2_hsotg_udc_stop - stop the udc
3146 * @gadget: The usb gadget state
3147 * @driver: The usb gadget driver
3148 *
3149 * Stop udc hw block and stay tunned for future transmissions
3150 */
3151static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
3152{
3153 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3154 unsigned long flags = 0;
3155 int ep;
3156
3157 if (!hsotg)
3158 return -ENODEV;
3159
3160 /* all endpoints should be shutdown */
3161 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3162 if (hsotg->eps_in[ep])
3163 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3164 if (hsotg->eps_out[ep])
3165 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3166 }
3167
3168 spin_lock_irqsave(&hsotg->lock, flags);
3169
3170 hsotg->driver = NULL;
3171 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3172 hsotg->enabled = 0;
3173
3174 spin_unlock_irqrestore(&hsotg->lock, flags);
3175
3176 if (!IS_ERR_OR_NULL(hsotg->uphy))
3177 otg_set_peripheral(hsotg->uphy->otg, NULL);
3178
3179 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3180 dwc2_lowlevel_hw_disable(hsotg);
3181
3182 return 0;
3183}
3184
3185/**
3186 * dwc2_hsotg_gadget_getframe - read the frame number
3187 * @gadget: The usb gadget state
3188 *
3189 * Read the {micro} frame number
3190 */
3191static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
3192{
3193 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
3194}
3195
3196/**
3197 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
3198 * @gadget: The usb gadget state
3199 * @is_on: Current state of the USB PHY
3200 *
3201 * Connect/Disconnect the USB PHY pullup
3202 */
3203static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
3204{
3205 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3206 unsigned long flags = 0;
3207
3208 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
3209 hsotg->op_state);
3210
3211 /* Don't modify pullup state while in host mode */
3212 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
3213 hsotg->enabled = is_on;
3214 return 0;
3215 }
3216
3217 spin_lock_irqsave(&hsotg->lock, flags);
3218 if (is_on) {
3219 hsotg->enabled = 1;
3220 dwc2_hsotg_core_init_disconnected(hsotg, false);
3221 dwc2_hsotg_core_connect(hsotg);
3222 } else {
3223 dwc2_hsotg_core_disconnect(hsotg);
3224 dwc2_hsotg_disconnect(hsotg);
3225 hsotg->enabled = 0;
3226 }
3227
3228 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3229 spin_unlock_irqrestore(&hsotg->lock, flags);
3230
3231 return 0;
3232}
3233
3234static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
3235{
3236 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3237 unsigned long flags;
3238
3239 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
3240 spin_lock_irqsave(&hsotg->lock, flags);
3241
3242 /*
3243 * If controller is hibernated, it must exit from hibernation
3244 * before being initialized / de-initialized
3245 */
3246 if (hsotg->lx_state == DWC2_L2)
3247 dwc2_exit_hibernation(hsotg, false);
3248
3249 if (is_active) {
3250 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3251
3252 dwc2_hsotg_core_init_disconnected(hsotg, false);
3253 if (hsotg->enabled)
3254 dwc2_hsotg_core_connect(hsotg);
3255 } else {
3256 dwc2_hsotg_core_disconnect(hsotg);
3257 dwc2_hsotg_disconnect(hsotg);
3258 }
3259
3260 spin_unlock_irqrestore(&hsotg->lock, flags);
3261 return 0;
3262}
3263
3264/**
3265 * dwc2_hsotg_vbus_draw - report bMaxPower field
3266 * @gadget: The usb gadget state
3267 * @mA: Amount of current
3268 *
3269 * Report how much power the device may consume to the phy.
3270 */
3271static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA)
3272{
3273 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3274
3275 if (IS_ERR_OR_NULL(hsotg->uphy))
3276 return -ENOTSUPP;
3277 return usb_phy_set_power(hsotg->uphy, mA);
3278}
3279
3280static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
3281 .get_frame = dwc2_hsotg_gadget_getframe,
3282 .udc_start = dwc2_hsotg_udc_start,
3283 .udc_stop = dwc2_hsotg_udc_stop,
3284 .pullup = dwc2_hsotg_pullup,
3285 .vbus_session = dwc2_hsotg_vbus_session,
3286 .vbus_draw = dwc2_hsotg_vbus_draw,
3287};
3288
3289/**
3290 * dwc2_hsotg_initep - initialise a single endpoint
3291 * @hsotg: The device state.
3292 * @hs_ep: The endpoint to be initialised.
3293 * @epnum: The endpoint number
3294 *
3295 * Initialise the given endpoint (as part of the probe and device state
3296 * creation) to give to the gadget driver. Setup the endpoint name, any
3297 * direction information and other state that may be required.
3298 */
3299static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
3300 struct dwc2_hsotg_ep *hs_ep,
3301 int epnum,
3302 bool dir_in)
3303{
3304 char *dir;
3305
3306 if (epnum == 0)
3307 dir = "";
3308 else if (dir_in)
3309 dir = "in";
3310 else
3311 dir = "out";
3312
3313 hs_ep->dir_in = dir_in;
3314 hs_ep->index = epnum;
3315
3316 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3317
3318 INIT_LIST_HEAD(&hs_ep->queue);
3319 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3320
3321 /* add to the list of endpoints known by the gadget driver */
3322 if (epnum)
3323 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3324
3325 hs_ep->parent = hsotg;
3326 hs_ep->ep.name = hs_ep->name;
3327 usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT);
3328 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
3329
3330 if (epnum == 0) {
3331 hs_ep->ep.caps.type_control = true;
3332 } else {
3333 hs_ep->ep.caps.type_iso = true;
3334 hs_ep->ep.caps.type_bulk = true;
3335 hs_ep->ep.caps.type_int = true;
3336 }
3337
3338 if (dir_in)
3339 hs_ep->ep.caps.dir_in = true;
3340 else
3341 hs_ep->ep.caps.dir_out = true;
3342
3343 /*
3344 * if we're using dma, we need to set the next-endpoint pointer
3345 * to be something valid.
3346 */
3347
3348 if (using_dma(hsotg)) {
3349 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
3350 if (dir_in)
3351 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
3352 else
3353 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
3354 }
3355}
3356
3357/**
3358 * dwc2_hsotg_hw_cfg - read HW configuration registers
3359 * @param: The device state
3360 *
3361 * Read the USB core HW configuration registers
3362 */
3363static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
3364{
3365 u32 cfg;
3366 u32 ep_type;
3367 u32 i;
3368
3369 /* check hardware configuration */
3370
3371 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
3372
3373 /* Add ep0 */
3374 hsotg->num_of_eps++;
3375
3376 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct dwc2_hsotg_ep),
3377 GFP_KERNEL);
3378 if (!hsotg->eps_in[0])
3379 return -ENOMEM;
3380 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
3381 hsotg->eps_out[0] = hsotg->eps_in[0];
3382
3383 cfg = hsotg->hw_params.dev_ep_dirs;
3384 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
3385 ep_type = cfg & 3;
3386 /* Direction in or both */
3387 if (!(ep_type & 2)) {
3388 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
3389 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
3390 if (!hsotg->eps_in[i])
3391 return -ENOMEM;
3392 }
3393 /* Direction out or both */
3394 if (!(ep_type & 1)) {
3395 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
3396 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
3397 if (!hsotg->eps_out[i])
3398 return -ENOMEM;
3399 }
3400 }
3401
3402 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
3403 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
3404
3405 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3406 hsotg->num_of_eps,
3407 hsotg->dedicated_fifos ? "dedicated" : "shared",
3408 hsotg->fifo_mem);
3409 return 0;
3410}
3411
3412/**
3413 * dwc2_hsotg_dump - dump state of the udc
3414 * @param: The device state
3415 */
3416static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
3417{
3418#ifdef DEBUG
3419 struct device *dev = hsotg->dev;
3420 void __iomem *regs = hsotg->regs;
3421 u32 val;
3422 int idx;
3423
3424 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3425 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
3426 dwc2_readl(regs + DIEPMSK));
3427
3428 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
3429 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
3430
3431 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3432 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
3433
3434 /* show periodic fifo settings */
3435
3436 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3437 val = dwc2_readl(regs + DPTXFSIZN(idx));
3438 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3439 val >> FIFOSIZE_DEPTH_SHIFT,
3440 val & FIFOSIZE_STARTADDR_MASK);
3441 }
3442
3443 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
3444 dev_info(dev,
3445 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3446 dwc2_readl(regs + DIEPCTL(idx)),
3447 dwc2_readl(regs + DIEPTSIZ(idx)),
3448 dwc2_readl(regs + DIEPDMA(idx)));
3449
3450 val = dwc2_readl(regs + DOEPCTL(idx));
3451 dev_info(dev,
3452 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3453 idx, dwc2_readl(regs + DOEPCTL(idx)),
3454 dwc2_readl(regs + DOEPTSIZ(idx)),
3455 dwc2_readl(regs + DOEPDMA(idx)));
3456
3457 }
3458
3459 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3460 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
3461#endif
3462}
3463
3464#ifdef CONFIG_OF
3465static void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg)
3466{
3467 struct device_node *np = hsotg->dev->of_node;
3468 u32 len = 0;
3469 u32 i = 0;
3470
3471 /* Enable dma if requested in device tree */
3472 hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma");
3473
3474 /*
3475 * Register TX periodic fifo size per endpoint.
3476 * EP0 is excluded since it has no fifo configuration.
3477 */
3478 if (!of_find_property(np, "g-tx-fifo-size", &len))
3479 goto rx_fifo;
3480
3481 len /= sizeof(u32);
3482
3483 /* Read tx fifo sizes other than ep0 */
3484 if (of_property_read_u32_array(np, "g-tx-fifo-size",
3485 &hsotg->g_tx_fifo_sz[1], len))
3486 goto rx_fifo;
3487
3488 /* Add ep0 */
3489 len++;
3490
3491 /* Make remaining TX fifos unavailable */
3492 if (len < MAX_EPS_CHANNELS) {
3493 for (i = len; i < MAX_EPS_CHANNELS; i++)
3494 hsotg->g_tx_fifo_sz[i] = 0;
3495 }
3496
3497rx_fifo:
3498 /* Register RX fifo size */
3499 of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz);
3500
3501 /* Register NPTX fifo size */
3502 of_property_read_u32(np, "g-np-tx-fifo-size",
3503 &hsotg->g_np_g_tx_fifo_sz);
3504}
3505#else
3506static inline void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) { }
3507#endif
3508
3509/**
3510 * dwc2_gadget_init - init function for gadget
3511 * @dwc2: The data structure for the DWC2 driver.
3512 * @irq: The IRQ number for the controller.
3513 */
3514int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
3515{
3516 struct device *dev = hsotg->dev;
3517 int epnum;
3518 int ret;
3519 int i;
3520 u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE;
3521
3522 /* Initialize to legacy fifo configuration values */
3523 hsotg->g_rx_fifo_sz = 2048;
3524 hsotg->g_np_g_tx_fifo_sz = 1024;
3525 memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo));
3526 /* Device tree specific probe */
3527 dwc2_hsotg_of_probe(hsotg);
3528
3529 /* Check against largest possible value. */
3530 if (hsotg->g_np_g_tx_fifo_sz >
3531 hsotg->hw_params.dev_nperio_tx_fifo_size) {
3532 dev_warn(dev, "Specified GNPTXFDEP=%d > %d\n",
3533 hsotg->g_np_g_tx_fifo_sz,
3534 hsotg->hw_params.dev_nperio_tx_fifo_size);
3535 hsotg->g_np_g_tx_fifo_sz =
3536 hsotg->hw_params.dev_nperio_tx_fifo_size;
3537 }
3538
3539 /* Dump fifo information */
3540 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
3541 hsotg->g_np_g_tx_fifo_sz);
3542 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz);
3543 for (i = 0; i < MAX_EPS_CHANNELS; i++)
3544 dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i,
3545 hsotg->g_tx_fifo_sz[i]);
3546
3547 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3548 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
3549 hsotg->gadget.name = dev_name(dev);
3550 if (hsotg->dr_mode == USB_DR_MODE_OTG)
3551 hsotg->gadget.is_otg = 1;
3552 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3553 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3554
3555 ret = dwc2_hsotg_hw_cfg(hsotg);
3556 if (ret) {
3557 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
3558 return ret;
3559 }
3560
3561 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
3562 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3563 if (!hsotg->ctrl_buff) {
3564 dev_err(dev, "failed to allocate ctrl request buff\n");
3565 return -ENOMEM;
3566 }
3567
3568 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
3569 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3570 if (!hsotg->ep0_buff) {
3571 dev_err(dev, "failed to allocate ctrl reply buff\n");
3572 return -ENOMEM;
3573 }
3574
3575 ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED,
3576 dev_name(hsotg->dev), hsotg);
3577 if (ret < 0) {
3578 dev_err(dev, "cannot claim IRQ for gadget\n");
3579 return ret;
3580 }
3581
3582 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3583
3584 if (hsotg->num_of_eps == 0) {
3585 dev_err(dev, "wrong number of EPs (zero)\n");
3586 return -EINVAL;
3587 }
3588
3589 /* setup endpoint information */
3590
3591 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3592 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
3593
3594 /* allocate EP0 request */
3595
3596 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
3597 GFP_KERNEL);
3598 if (!hsotg->ctrl_req) {
3599 dev_err(dev, "failed to allocate ctrl req\n");
3600 return -ENOMEM;
3601 }
3602
3603 /* initialise the endpoints now the core has been initialised */
3604 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
3605 if (hsotg->eps_in[epnum])
3606 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
3607 epnum, 1);
3608 if (hsotg->eps_out[epnum])
3609 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
3610 epnum, 0);
3611 }
3612
3613 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
3614 if (ret)
3615 return ret;
3616
3617 dwc2_hsotg_dump(hsotg);
3618
3619 return 0;
3620}
3621
3622/**
3623 * dwc2_hsotg_remove - remove function for hsotg driver
3624 * @pdev: The platform information for the driver
3625 */
3626int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
3627{
3628 usb_del_gadget_udc(&hsotg->gadget);
3629
3630 return 0;
3631}
3632
3633int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
3634{
3635 unsigned long flags;
3636
3637 if (hsotg->lx_state != DWC2_L0)
3638 return 0;
3639
3640 if (hsotg->driver) {
3641 int ep;
3642
3643 dev_info(hsotg->dev, "suspending usb gadget %s\n",
3644 hsotg->driver->driver.name);
3645
3646 spin_lock_irqsave(&hsotg->lock, flags);
3647 if (hsotg->enabled)
3648 dwc2_hsotg_core_disconnect(hsotg);
3649 dwc2_hsotg_disconnect(hsotg);
3650 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3651 spin_unlock_irqrestore(&hsotg->lock, flags);
3652
3653 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3654 if (hsotg->eps_in[ep])
3655 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3656 if (hsotg->eps_out[ep])
3657 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3658 }
3659 }
3660
3661 return 0;
3662}
3663
3664int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
3665{
3666 unsigned long flags;
3667
3668 if (hsotg->lx_state == DWC2_L2)
3669 return 0;
3670
3671 if (hsotg->driver) {
3672 dev_info(hsotg->dev, "resuming usb gadget %s\n",
3673 hsotg->driver->driver.name);
3674
3675 spin_lock_irqsave(&hsotg->lock, flags);
3676 dwc2_hsotg_core_init_disconnected(hsotg, false);
3677 if (hsotg->enabled)
3678 dwc2_hsotg_core_connect(hsotg);
3679 spin_unlock_irqrestore(&hsotg->lock, flags);
3680 }
3681
3682 return 0;
3683}
3684
3685/**
3686 * dwc2_backup_device_registers() - Backup controller device registers.
3687 * When suspending usb bus, registers needs to be backuped
3688 * if controller power is disabled once suspended.
3689 *
3690 * @hsotg: Programming view of the DWC_otg controller
3691 */
3692int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
3693{
3694 struct dwc2_dregs_backup *dr;
3695 int i;
3696
3697 dev_dbg(hsotg->dev, "%s\n", __func__);
3698
3699 /* Backup dev regs */
3700 dr = &hsotg->dr_backup;
3701
3702 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
3703 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
3704 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3705 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
3706 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
3707
3708 for (i = 0; i < hsotg->num_of_eps; i++) {
3709 /* Backup IN EPs */
3710 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
3711
3712 /* Ensure DATA PID is correctly configured */
3713 if (dr->diepctl[i] & DXEPCTL_DPID)
3714 dr->diepctl[i] |= DXEPCTL_SETD1PID;
3715 else
3716 dr->diepctl[i] |= DXEPCTL_SETD0PID;
3717
3718 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
3719 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
3720
3721 /* Backup OUT EPs */
3722 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
3723
3724 /* Ensure DATA PID is correctly configured */
3725 if (dr->doepctl[i] & DXEPCTL_DPID)
3726 dr->doepctl[i] |= DXEPCTL_SETD1PID;
3727 else
3728 dr->doepctl[i] |= DXEPCTL_SETD0PID;
3729
3730 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
3731 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
3732 }
3733 dr->valid = true;
3734 return 0;
3735}
3736
3737/**
3738 * dwc2_restore_device_registers() - Restore controller device registers.
3739 * When resuming usb bus, device registers needs to be restored
3740 * if controller power were disabled.
3741 *
3742 * @hsotg: Programming view of the DWC_otg controller
3743 */
3744int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
3745{
3746 struct dwc2_dregs_backup *dr;
3747 u32 dctl;
3748 int i;
3749
3750 dev_dbg(hsotg->dev, "%s\n", __func__);
3751
3752 /* Restore dev regs */
3753 dr = &hsotg->dr_backup;
3754 if (!dr->valid) {
3755 dev_err(hsotg->dev, "%s: no device registers to restore\n",
3756 __func__);
3757 return -EINVAL;
3758 }
3759 dr->valid = false;
3760
3761 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
3762 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
3763 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
3764 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
3765 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
3766
3767 for (i = 0; i < hsotg->num_of_eps; i++) {
3768 /* Restore IN EPs */
3769 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
3770 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
3771 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
3772
3773 /* Restore OUT EPs */
3774 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
3775 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
3776 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
3777 }
3778
3779 /* Set the Power-On Programming done bit */
3780 dctl = dwc2_readl(hsotg->regs + DCTL);
3781 dctl |= DCTL_PWRONPRGDONE;
3782 dwc2_writel(dctl, hsotg->regs + DCTL);
3783
3784 return 0;
3785}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * S3C USB2.0 High-speed / OtG driver
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/spinlock.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
20#include <linux/mutex.h>
21#include <linux/seq_file.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25
26#include <linux/usb/ch9.h>
27#include <linux/usb/gadget.h>
28#include <linux/usb/phy.h>
29#include <linux/usb/composite.h>
30
31
32#include "core.h"
33#include "hw.h"
34
35/* conversion functions */
36static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
37{
38 return container_of(req, struct dwc2_hsotg_req, req);
39}
40
41static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
42{
43 return container_of(ep, struct dwc2_hsotg_ep, ep);
44}
45
46static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
47{
48 return container_of(gadget, struct dwc2_hsotg, gadget);
49}
50
51static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
52{
53 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
54}
55
56static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
57{
58 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
59}
60
61static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
62 u32 ep_index, u32 dir_in)
63{
64 if (dir_in)
65 return hsotg->eps_in[ep_index];
66 else
67 return hsotg->eps_out[ep_index];
68}
69
70/* forward declaration of functions */
71static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
72
73/**
74 * using_dma - return the DMA status of the driver.
75 * @hsotg: The driver state.
76 *
77 * Return true if we're using DMA.
78 *
79 * Currently, we have the DMA support code worked into everywhere
80 * that needs it, but the AMBA DMA implementation in the hardware can
81 * only DMA from 32bit aligned addresses. This means that gadgets such
82 * as the CDC Ethernet cannot work as they often pass packets which are
83 * not 32bit aligned.
84 *
85 * Unfortunately the choice to use DMA or not is global to the controller
86 * and seems to be only settable when the controller is being put through
87 * a core reset. This means we either need to fix the gadgets to take
88 * account of DMA alignment, or add bounce buffers (yuerk).
89 *
90 * g_using_dma is set depending on dts flag.
91 */
92static inline bool using_dma(struct dwc2_hsotg *hsotg)
93{
94 return hsotg->params.g_dma;
95}
96
97/*
98 * using_desc_dma - return the descriptor DMA status of the driver.
99 * @hsotg: The driver state.
100 *
101 * Return true if we're using descriptor DMA.
102 */
103static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
104{
105 return hsotg->params.g_dma_desc;
106}
107
108/**
109 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
110 * @hs_ep: The endpoint
111 *
112 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
113 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
114 */
115static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
116{
117 struct dwc2_hsotg *hsotg = hs_ep->parent;
118 u16 limit = DSTS_SOFFN_LIMIT;
119
120 if (hsotg->gadget.speed != USB_SPEED_HIGH)
121 limit >>= 3;
122
123 hs_ep->target_frame += hs_ep->interval;
124 if (hs_ep->target_frame > limit) {
125 hs_ep->frame_overrun = true;
126 hs_ep->target_frame &= limit;
127 } else {
128 hs_ep->frame_overrun = false;
129 }
130}
131
132/**
133 * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
134 * by one.
135 * @hs_ep: The endpoint.
136 *
137 * This function used in service interval based scheduling flow to calculate
138 * descriptor frame number filed value. For service interval mode frame
139 * number in descriptor should point to last (u)frame in the interval.
140 *
141 */
142static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
143{
144 struct dwc2_hsotg *hsotg = hs_ep->parent;
145 u16 limit = DSTS_SOFFN_LIMIT;
146
147 if (hsotg->gadget.speed != USB_SPEED_HIGH)
148 limit >>= 3;
149
150 if (hs_ep->target_frame)
151 hs_ep->target_frame -= 1;
152 else
153 hs_ep->target_frame = limit;
154}
155
156/**
157 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
158 * @hsotg: The device state
159 * @ints: A bitmask of the interrupts to enable
160 */
161static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
162{
163 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
164 u32 new_gsintmsk;
165
166 new_gsintmsk = gsintmsk | ints;
167
168 if (new_gsintmsk != gsintmsk) {
169 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
170 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
171 }
172}
173
174/**
175 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
176 * @hsotg: The device state
177 * @ints: A bitmask of the interrupts to enable
178 */
179static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
180{
181 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
182 u32 new_gsintmsk;
183
184 new_gsintmsk = gsintmsk & ~ints;
185
186 if (new_gsintmsk != gsintmsk)
187 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
188}
189
190/**
191 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
192 * @hsotg: The device state
193 * @ep: The endpoint index
194 * @dir_in: True if direction is in.
195 * @en: The enable value, true to enable
196 *
197 * Set or clear the mask for an individual endpoint's interrupt
198 * request.
199 */
200static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
201 unsigned int ep, unsigned int dir_in,
202 unsigned int en)
203{
204 unsigned long flags;
205 u32 bit = 1 << ep;
206 u32 daint;
207
208 if (!dir_in)
209 bit <<= 16;
210
211 local_irq_save(flags);
212 daint = dwc2_readl(hsotg, DAINTMSK);
213 if (en)
214 daint |= bit;
215 else
216 daint &= ~bit;
217 dwc2_writel(hsotg, daint, DAINTMSK);
218 local_irq_restore(flags);
219}
220
221/**
222 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
223 *
224 * @hsotg: Programming view of the DWC_otg controller
225 */
226int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
227{
228 if (hsotg->hw_params.en_multiple_tx_fifo)
229 /* In dedicated FIFO mode we need count of IN EPs */
230 return hsotg->hw_params.num_dev_in_eps;
231 else
232 /* In shared FIFO mode we need count of Periodic IN EPs */
233 return hsotg->hw_params.num_dev_perio_in_ep;
234}
235
236/**
237 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
238 * device mode TX FIFOs
239 *
240 * @hsotg: Programming view of the DWC_otg controller
241 */
242int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
243{
244 int addr;
245 int tx_addr_max;
246 u32 np_tx_fifo_size;
247
248 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
249 hsotg->params.g_np_tx_fifo_size);
250
251 /* Get Endpoint Info Control block size in DWORDs. */
252 tx_addr_max = hsotg->hw_params.total_fifo_size;
253
254 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
255 if (tx_addr_max <= addr)
256 return 0;
257
258 return tx_addr_max - addr;
259}
260
261/**
262 * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
263 *
264 * @hsotg: Programming view of the DWC_otg controller
265 *
266 */
267static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
268{
269 u32 gintsts2;
270 u32 gintmsk2;
271
272 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
273 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
274 gintsts2 &= gintmsk2;
275
276 if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
277 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
278 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
279 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
280 }
281}
282
283/**
284 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
285 * TX FIFOs
286 *
287 * @hsotg: Programming view of the DWC_otg controller
288 */
289int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
290{
291 int tx_fifo_count;
292 int tx_fifo_depth;
293
294 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
295
296 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
297
298 if (!tx_fifo_count)
299 return tx_fifo_depth;
300 else
301 return tx_fifo_depth / tx_fifo_count;
302}
303
304/**
305 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
306 * @hsotg: The device instance.
307 */
308static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
309{
310 unsigned int ep;
311 unsigned int addr;
312 int timeout;
313
314 u32 val;
315 u32 *txfsz = hsotg->params.g_tx_fifo_size;
316
317 /* Reset fifo map if not correctly cleared during previous session */
318 WARN_ON(hsotg->fifo_map);
319 hsotg->fifo_map = 0;
320
321 /* set RX/NPTX FIFO sizes */
322 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
323 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
324 FIFOSIZE_STARTADDR_SHIFT) |
325 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
326 GNPTXFSIZ);
327
328 /*
329 * arange all the rest of the TX FIFOs, as some versions of this
330 * block have overlapping default addresses. This also ensures
331 * that if the settings have been changed, then they are set to
332 * known values.
333 */
334
335 /* start at the end of the GNPTXFSIZ, rounded up */
336 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
337
338 /*
339 * Configure fifos sizes from provided configuration and assign
340 * them to endpoints dynamically according to maxpacket size value of
341 * given endpoint.
342 */
343 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
344 if (!txfsz[ep])
345 continue;
346 val = addr;
347 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
348 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
349 "insufficient fifo memory");
350 addr += txfsz[ep];
351
352 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
353 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
354 }
355
356 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
357 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
358 GDFIFOCFG);
359 /*
360 * according to p428 of the design guide, we need to ensure that
361 * all fifos are flushed before continuing
362 */
363
364 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
365 GRSTCTL_RXFFLSH, GRSTCTL);
366
367 /* wait until the fifos are both flushed */
368 timeout = 100;
369 while (1) {
370 val = dwc2_readl(hsotg, GRSTCTL);
371
372 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
373 break;
374
375 if (--timeout == 0) {
376 dev_err(hsotg->dev,
377 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
378 __func__, val);
379 break;
380 }
381
382 udelay(1);
383 }
384
385 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
386}
387
388/**
389 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
390 * @ep: USB endpoint to allocate request for.
391 * @flags: Allocation flags
392 *
393 * Allocate a new USB request structure appropriate for the specified endpoint
394 */
395static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
396 gfp_t flags)
397{
398 struct dwc2_hsotg_req *req;
399
400 req = kzalloc(sizeof(*req), flags);
401 if (!req)
402 return NULL;
403
404 INIT_LIST_HEAD(&req->queue);
405
406 return &req->req;
407}
408
409/**
410 * is_ep_periodic - return true if the endpoint is in periodic mode.
411 * @hs_ep: The endpoint to query.
412 *
413 * Returns true if the endpoint is in periodic mode, meaning it is being
414 * used for an Interrupt or ISO transfer.
415 */
416static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
417{
418 return hs_ep->periodic;
419}
420
421/**
422 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
423 * @hsotg: The device state.
424 * @hs_ep: The endpoint for the request
425 * @hs_req: The request being processed.
426 *
427 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
428 * of a request to ensure the buffer is ready for access by the caller.
429 */
430static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
431 struct dwc2_hsotg_ep *hs_ep,
432 struct dwc2_hsotg_req *hs_req)
433{
434 struct usb_request *req = &hs_req->req;
435
436 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir);
437}
438
439/*
440 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
441 * for Control endpoint
442 * @hsotg: The device state.
443 *
444 * This function will allocate 4 descriptor chains for EP 0: 2 for
445 * Setup stage, per one for IN and OUT data/status transactions.
446 */
447static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
448{
449 hsotg->setup_desc[0] =
450 dmam_alloc_coherent(hsotg->dev,
451 sizeof(struct dwc2_dma_desc),
452 &hsotg->setup_desc_dma[0],
453 GFP_KERNEL);
454 if (!hsotg->setup_desc[0])
455 goto fail;
456
457 hsotg->setup_desc[1] =
458 dmam_alloc_coherent(hsotg->dev,
459 sizeof(struct dwc2_dma_desc),
460 &hsotg->setup_desc_dma[1],
461 GFP_KERNEL);
462 if (!hsotg->setup_desc[1])
463 goto fail;
464
465 hsotg->ctrl_in_desc =
466 dmam_alloc_coherent(hsotg->dev,
467 sizeof(struct dwc2_dma_desc),
468 &hsotg->ctrl_in_desc_dma,
469 GFP_KERNEL);
470 if (!hsotg->ctrl_in_desc)
471 goto fail;
472
473 hsotg->ctrl_out_desc =
474 dmam_alloc_coherent(hsotg->dev,
475 sizeof(struct dwc2_dma_desc),
476 &hsotg->ctrl_out_desc_dma,
477 GFP_KERNEL);
478 if (!hsotg->ctrl_out_desc)
479 goto fail;
480
481 return 0;
482
483fail:
484 return -ENOMEM;
485}
486
487/**
488 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
489 * @hsotg: The controller state.
490 * @hs_ep: The endpoint we're going to write for.
491 * @hs_req: The request to write data for.
492 *
493 * This is called when the TxFIFO has some space in it to hold a new
494 * transmission and we have something to give it. The actual setup of
495 * the data size is done elsewhere, so all we have to do is to actually
496 * write the data.
497 *
498 * The return value is zero if there is more space (or nothing was done)
499 * otherwise -ENOSPC is returned if the FIFO space was used up.
500 *
501 * This routine is only needed for PIO
502 */
503static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
504 struct dwc2_hsotg_ep *hs_ep,
505 struct dwc2_hsotg_req *hs_req)
506{
507 bool periodic = is_ep_periodic(hs_ep);
508 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
509 int buf_pos = hs_req->req.actual;
510 int to_write = hs_ep->size_loaded;
511 void *data;
512 int can_write;
513 int pkt_round;
514 int max_transfer;
515
516 to_write -= (buf_pos - hs_ep->last_load);
517
518 /* if there's nothing to write, get out early */
519 if (to_write == 0)
520 return 0;
521
522 if (periodic && !hsotg->dedicated_fifos) {
523 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
524 int size_left;
525 int size_done;
526
527 /*
528 * work out how much data was loaded so we can calculate
529 * how much data is left in the fifo.
530 */
531
532 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
533
534 /*
535 * if shared fifo, we cannot write anything until the
536 * previous data has been completely sent.
537 */
538 if (hs_ep->fifo_load != 0) {
539 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
540 return -ENOSPC;
541 }
542
543 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
544 __func__, size_left,
545 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
546
547 /* how much of the data has moved */
548 size_done = hs_ep->size_loaded - size_left;
549
550 /* how much data is left in the fifo */
551 can_write = hs_ep->fifo_load - size_done;
552 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
553 __func__, can_write);
554
555 can_write = hs_ep->fifo_size - can_write;
556 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
557 __func__, can_write);
558
559 if (can_write <= 0) {
560 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
561 return -ENOSPC;
562 }
563 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
564 can_write = dwc2_readl(hsotg,
565 DTXFSTS(hs_ep->fifo_index));
566
567 can_write &= 0xffff;
568 can_write *= 4;
569 } else {
570 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
571 dev_dbg(hsotg->dev,
572 "%s: no queue slots available (0x%08x)\n",
573 __func__, gnptxsts);
574
575 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
576 return -ENOSPC;
577 }
578
579 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
580 can_write *= 4; /* fifo size is in 32bit quantities. */
581 }
582
583 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
584
585 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
586 __func__, gnptxsts, can_write, to_write, max_transfer);
587
588 /*
589 * limit to 512 bytes of data, it seems at least on the non-periodic
590 * FIFO, requests of >512 cause the endpoint to get stuck with a
591 * fragment of the end of the transfer in it.
592 */
593 if (can_write > 512 && !periodic)
594 can_write = 512;
595
596 /*
597 * limit the write to one max-packet size worth of data, but allow
598 * the transfer to return that it did not run out of fifo space
599 * doing it.
600 */
601 if (to_write > max_transfer) {
602 to_write = max_transfer;
603
604 /* it's needed only when we do not use dedicated fifos */
605 if (!hsotg->dedicated_fifos)
606 dwc2_hsotg_en_gsint(hsotg,
607 periodic ? GINTSTS_PTXFEMP :
608 GINTSTS_NPTXFEMP);
609 }
610
611 /* see if we can write data */
612
613 if (to_write > can_write) {
614 to_write = can_write;
615 pkt_round = to_write % max_transfer;
616
617 /*
618 * Round the write down to an
619 * exact number of packets.
620 *
621 * Note, we do not currently check to see if we can ever
622 * write a full packet or not to the FIFO.
623 */
624
625 if (pkt_round)
626 to_write -= pkt_round;
627
628 /*
629 * enable correct FIFO interrupt to alert us when there
630 * is more room left.
631 */
632
633 /* it's needed only when we do not use dedicated fifos */
634 if (!hsotg->dedicated_fifos)
635 dwc2_hsotg_en_gsint(hsotg,
636 periodic ? GINTSTS_PTXFEMP :
637 GINTSTS_NPTXFEMP);
638 }
639
640 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
641 to_write, hs_req->req.length, can_write, buf_pos);
642
643 if (to_write <= 0)
644 return -ENOSPC;
645
646 hs_req->req.actual = buf_pos + to_write;
647 hs_ep->total_data += to_write;
648
649 if (periodic)
650 hs_ep->fifo_load += to_write;
651
652 to_write = DIV_ROUND_UP(to_write, 4);
653 data = hs_req->req.buf + buf_pos;
654
655 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
656
657 return (to_write >= can_write) ? -ENOSPC : 0;
658}
659
660/**
661 * get_ep_limit - get the maximum data legnth for this endpoint
662 * @hs_ep: The endpoint
663 *
664 * Return the maximum data that can be queued in one go on a given endpoint
665 * so that transfers that are too long can be split.
666 */
667static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
668{
669 int index = hs_ep->index;
670 unsigned int maxsize;
671 unsigned int maxpkt;
672
673 if (index != 0) {
674 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
675 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
676 } else {
677 maxsize = 64 + 64;
678 if (hs_ep->dir_in)
679 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
680 else
681 maxpkt = 2;
682 }
683
684 /* we made the constant loading easier above by using +1 */
685 maxpkt--;
686 maxsize--;
687
688 /*
689 * constrain by packet count if maxpkts*pktsize is greater
690 * than the length register size.
691 */
692
693 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
694 maxsize = maxpkt * hs_ep->ep.maxpacket;
695
696 return maxsize;
697}
698
699/**
700 * dwc2_hsotg_read_frameno - read current frame number
701 * @hsotg: The device instance
702 *
703 * Return the current frame number
704 */
705static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
706{
707 u32 dsts;
708
709 dsts = dwc2_readl(hsotg, DSTS);
710 dsts &= DSTS_SOFFN_MASK;
711 dsts >>= DSTS_SOFFN_SHIFT;
712
713 return dsts;
714}
715
716/**
717 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
718 * DMA descriptor chain prepared for specific endpoint
719 * @hs_ep: The endpoint
720 *
721 * Return the maximum data that can be queued in one go on a given endpoint
722 * depending on its descriptor chain capacity so that transfers that
723 * are too long can be split.
724 */
725static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
726{
727 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
728 int is_isoc = hs_ep->isochronous;
729 unsigned int maxsize;
730 u32 mps = hs_ep->ep.maxpacket;
731 int dir_in = hs_ep->dir_in;
732
733 if (is_isoc)
734 maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
735 DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
736 MAX_DMA_DESC_NUM_HS_ISOC;
737 else
738 maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
739
740 /* Interrupt OUT EP with mps not multiple of 4 */
741 if (hs_ep->index)
742 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
743 maxsize = mps * MAX_DMA_DESC_NUM_GENERIC;
744
745 return maxsize;
746}
747
748/*
749 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
750 * @hs_ep: The endpoint
751 * @mask: RX/TX bytes mask to be defined
752 *
753 * Returns maximum data payload for one descriptor after analyzing endpoint
754 * characteristics.
755 * DMA descriptor transfer bytes limit depends on EP type:
756 * Control out - MPS,
757 * Isochronous - descriptor rx/tx bytes bitfield limit,
758 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
759 * have concatenations from various descriptors within one packet.
760 * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds
761 * to a single descriptor.
762 *
763 * Selects corresponding mask for RX/TX bytes as well.
764 */
765static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
766{
767 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
768 u32 mps = hs_ep->ep.maxpacket;
769 int dir_in = hs_ep->dir_in;
770 u32 desc_size = 0;
771
772 if (!hs_ep->index && !dir_in) {
773 desc_size = mps;
774 *mask = DEV_DMA_NBYTES_MASK;
775 } else if (hs_ep->isochronous) {
776 if (dir_in) {
777 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
778 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
779 } else {
780 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
781 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
782 }
783 } else {
784 desc_size = DEV_DMA_NBYTES_LIMIT;
785 *mask = DEV_DMA_NBYTES_MASK;
786
787 /* Round down desc_size to be mps multiple */
788 desc_size -= desc_size % mps;
789 }
790
791 /* Interrupt OUT EP with mps not multiple of 4 */
792 if (hs_ep->index)
793 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) {
794 desc_size = mps;
795 *mask = DEV_DMA_NBYTES_MASK;
796 }
797
798 return desc_size;
799}
800
801static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
802 struct dwc2_dma_desc **desc,
803 dma_addr_t dma_buff,
804 unsigned int len,
805 bool true_last)
806{
807 int dir_in = hs_ep->dir_in;
808 u32 mps = hs_ep->ep.maxpacket;
809 u32 maxsize = 0;
810 u32 offset = 0;
811 u32 mask = 0;
812 int i;
813
814 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
815
816 hs_ep->desc_count = (len / maxsize) +
817 ((len % maxsize) ? 1 : 0);
818 if (len == 0)
819 hs_ep->desc_count = 1;
820
821 for (i = 0; i < hs_ep->desc_count; ++i) {
822 (*desc)->status = 0;
823 (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
824 << DEV_DMA_BUFF_STS_SHIFT);
825
826 if (len > maxsize) {
827 if (!hs_ep->index && !dir_in)
828 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
829
830 (*desc)->status |=
831 maxsize << DEV_DMA_NBYTES_SHIFT & mask;
832 (*desc)->buf = dma_buff + offset;
833
834 len -= maxsize;
835 offset += maxsize;
836 } else {
837 if (true_last)
838 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
839
840 if (dir_in)
841 (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
842 ((hs_ep->send_zlp && true_last) ?
843 DEV_DMA_SHORT : 0);
844
845 (*desc)->status |=
846 len << DEV_DMA_NBYTES_SHIFT & mask;
847 (*desc)->buf = dma_buff + offset;
848 }
849
850 (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
851 (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
852 << DEV_DMA_BUFF_STS_SHIFT);
853 (*desc)++;
854 }
855}
856
857/*
858 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
859 * @hs_ep: The endpoint
860 * @ureq: Request to transfer
861 * @offset: offset in bytes
862 * @len: Length of the transfer
863 *
864 * This function will iterate over descriptor chain and fill its entries
865 * with corresponding information based on transfer data.
866 */
867static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
868 dma_addr_t dma_buff,
869 unsigned int len)
870{
871 struct usb_request *ureq = NULL;
872 struct dwc2_dma_desc *desc = hs_ep->desc_list;
873 struct scatterlist *sg;
874 int i;
875 u8 desc_count = 0;
876
877 if (hs_ep->req)
878 ureq = &hs_ep->req->req;
879
880 /* non-DMA sg buffer */
881 if (!ureq || !ureq->num_sgs) {
882 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
883 dma_buff, len, true);
884 return;
885 }
886
887 /* DMA sg buffer */
888 for_each_sg(ureq->sg, sg, ureq->num_mapped_sgs, i) {
889 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
890 sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
891 (i == (ureq->num_mapped_sgs - 1)));
892 desc_count += hs_ep->desc_count;
893 }
894
895 hs_ep->desc_count = desc_count;
896}
897
898/*
899 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
900 * @hs_ep: The isochronous endpoint.
901 * @dma_buff: usb requests dma buffer.
902 * @len: usb request transfer length.
903 *
904 * Fills next free descriptor with the data of the arrived usb request,
905 * frame info, sets Last and IOC bits increments next_desc. If filled
906 * descriptor is not the first one, removes L bit from the previous descriptor
907 * status.
908 */
909static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
910 dma_addr_t dma_buff, unsigned int len)
911{
912 struct dwc2_dma_desc *desc;
913 struct dwc2_hsotg *hsotg = hs_ep->parent;
914 u32 index;
915 u32 mask = 0;
916 u8 pid = 0;
917
918 dwc2_gadget_get_desc_params(hs_ep, &mask);
919
920 index = hs_ep->next_desc;
921 desc = &hs_ep->desc_list[index];
922
923 /* Check if descriptor chain full */
924 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
925 DEV_DMA_BUFF_STS_HREADY) {
926 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
927 return 1;
928 }
929
930 /* Clear L bit of previous desc if more than one entries in the chain */
931 if (hs_ep->next_desc)
932 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
933
934 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
935 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
936
937 desc->status = 0;
938 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
939
940 desc->buf = dma_buff;
941 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
942 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
943
944 if (hs_ep->dir_in) {
945 if (len)
946 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
947 else
948 pid = 1;
949 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
950 DEV_DMA_ISOC_PID_MASK) |
951 ((len % hs_ep->ep.maxpacket) ?
952 DEV_DMA_SHORT : 0) |
953 ((hs_ep->target_frame <<
954 DEV_DMA_ISOC_FRNUM_SHIFT) &
955 DEV_DMA_ISOC_FRNUM_MASK);
956 }
957
958 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
959 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
960
961 /* Increment frame number by interval for IN */
962 if (hs_ep->dir_in)
963 dwc2_gadget_incr_frame_num(hs_ep);
964
965 /* Update index of last configured entry in the chain */
966 hs_ep->next_desc++;
967 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
968 hs_ep->next_desc = 0;
969
970 return 0;
971}
972
973/*
974 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
975 * @hs_ep: The isochronous endpoint.
976 *
977 * Prepare descriptor chain for isochronous endpoints. Afterwards
978 * write DMA address to HW and enable the endpoint.
979 */
980static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
981{
982 struct dwc2_hsotg *hsotg = hs_ep->parent;
983 struct dwc2_hsotg_req *hs_req, *treq;
984 int index = hs_ep->index;
985 int ret;
986 int i;
987 u32 dma_reg;
988 u32 depctl;
989 u32 ctrl;
990 struct dwc2_dma_desc *desc;
991
992 if (list_empty(&hs_ep->queue)) {
993 hs_ep->target_frame = TARGET_FRAME_INITIAL;
994 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
995 return;
996 }
997
998 /* Initialize descriptor chain by Host Busy status */
999 for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
1000 desc = &hs_ep->desc_list[i];
1001 desc->status = 0;
1002 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
1003 << DEV_DMA_BUFF_STS_SHIFT);
1004 }
1005
1006 hs_ep->next_desc = 0;
1007 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
1008 dma_addr_t dma_addr = hs_req->req.dma;
1009
1010 if (hs_req->req.num_sgs) {
1011 WARN_ON(hs_req->req.num_sgs > 1);
1012 dma_addr = sg_dma_address(hs_req->req.sg);
1013 }
1014 ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1015 hs_req->req.length);
1016 if (ret)
1017 break;
1018 }
1019
1020 hs_ep->compl_desc = 0;
1021 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1022 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
1023
1024 /* write descriptor chain address to control register */
1025 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1026
1027 ctrl = dwc2_readl(hsotg, depctl);
1028 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
1029 dwc2_writel(hsotg, ctrl, depctl);
1030}
1031
1032static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep);
1033static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1034 struct dwc2_hsotg_ep *hs_ep,
1035 struct dwc2_hsotg_req *hs_req,
1036 int result);
1037
1038/**
1039 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
1040 * @hsotg: The controller state.
1041 * @hs_ep: The endpoint to process a request for
1042 * @hs_req: The request to start.
1043 * @continuing: True if we are doing more for the current request.
1044 *
1045 * Start the given request running by setting the endpoint registers
1046 * appropriately, and writing any data to the FIFOs.
1047 */
1048static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1049 struct dwc2_hsotg_ep *hs_ep,
1050 struct dwc2_hsotg_req *hs_req,
1051 bool continuing)
1052{
1053 struct usb_request *ureq = &hs_req->req;
1054 int index = hs_ep->index;
1055 int dir_in = hs_ep->dir_in;
1056 u32 epctrl_reg;
1057 u32 epsize_reg;
1058 u32 epsize;
1059 u32 ctrl;
1060 unsigned int length;
1061 unsigned int packets;
1062 unsigned int maxreq;
1063 unsigned int dma_reg;
1064
1065 if (index != 0) {
1066 if (hs_ep->req && !continuing) {
1067 dev_err(hsotg->dev, "%s: active request\n", __func__);
1068 WARN_ON(1);
1069 return;
1070 } else if (hs_ep->req != hs_req && continuing) {
1071 dev_err(hsotg->dev,
1072 "%s: continue different req\n", __func__);
1073 WARN_ON(1);
1074 return;
1075 }
1076 }
1077
1078 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1079 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1080 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1081
1082 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1083 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1084 hs_ep->dir_in ? "in" : "out");
1085
1086 /* If endpoint is stalled, we will restart request later */
1087 ctrl = dwc2_readl(hsotg, epctrl_reg);
1088
1089 if (index && ctrl & DXEPCTL_STALL) {
1090 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1091 return;
1092 }
1093
1094 length = ureq->length - ureq->actual;
1095 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1096 ureq->length, ureq->actual);
1097
1098 if (!using_desc_dma(hsotg))
1099 maxreq = get_ep_limit(hs_ep);
1100 else
1101 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1102
1103 if (length > maxreq) {
1104 int round = maxreq % hs_ep->ep.maxpacket;
1105
1106 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1107 __func__, length, maxreq, round);
1108
1109 /* round down to multiple of packets */
1110 if (round)
1111 maxreq -= round;
1112
1113 length = maxreq;
1114 }
1115
1116 if (length)
1117 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1118 else
1119 packets = 1; /* send one packet if length is zero. */
1120
1121 if (dir_in && index != 0)
1122 if (hs_ep->isochronous)
1123 epsize = DXEPTSIZ_MC(packets);
1124 else
1125 epsize = DXEPTSIZ_MC(1);
1126 else
1127 epsize = 0;
1128
1129 /*
1130 * zero length packet should be programmed on its own and should not
1131 * be counted in DIEPTSIZ.PktCnt with other packets.
1132 */
1133 if (dir_in && ureq->zero && !continuing) {
1134 /* Test if zlp is actually required. */
1135 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1136 !(ureq->length % hs_ep->ep.maxpacket))
1137 hs_ep->send_zlp = 1;
1138 }
1139
1140 epsize |= DXEPTSIZ_PKTCNT(packets);
1141 epsize |= DXEPTSIZ_XFERSIZE(length);
1142
1143 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1144 __func__, packets, length, ureq->length, epsize, epsize_reg);
1145
1146 /* store the request as the current one we're doing */
1147 hs_ep->req = hs_req;
1148
1149 if (using_desc_dma(hsotg)) {
1150 u32 offset = 0;
1151 u32 mps = hs_ep->ep.maxpacket;
1152
1153 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1154 if (!dir_in) {
1155 if (!index)
1156 length = mps;
1157 else if (length % mps)
1158 length += (mps - (length % mps));
1159 }
1160
1161 if (continuing)
1162 offset = ureq->actual;
1163
1164 /* Fill DDMA chain entries */
1165 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1166 length);
1167
1168 /* write descriptor chain address to control register */
1169 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1170
1171 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1172 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1173 } else {
1174 /* write size / packets */
1175 dwc2_writel(hsotg, epsize, epsize_reg);
1176
1177 if (using_dma(hsotg) && !continuing && (length != 0)) {
1178 /*
1179 * write DMA address to control register, buffer
1180 * already synced by dwc2_hsotg_ep_queue().
1181 */
1182
1183 dwc2_writel(hsotg, ureq->dma, dma_reg);
1184
1185 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1186 __func__, &ureq->dma, dma_reg);
1187 }
1188 }
1189
1190 if (hs_ep->isochronous) {
1191 if (!dwc2_gadget_target_frame_elapsed(hs_ep)) {
1192 if (hs_ep->interval == 1) {
1193 if (hs_ep->target_frame & 0x1)
1194 ctrl |= DXEPCTL_SETODDFR;
1195 else
1196 ctrl |= DXEPCTL_SETEVENFR;
1197 }
1198 ctrl |= DXEPCTL_CNAK;
1199 } else {
1200 hs_req->req.frame_number = hs_ep->target_frame;
1201 hs_req->req.actual = 0;
1202 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
1203 return;
1204 }
1205 }
1206
1207 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1208
1209 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1210
1211 /* For Setup request do not clear NAK */
1212 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1213 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1214
1215 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1216 dwc2_writel(hsotg, ctrl, epctrl_reg);
1217
1218 /*
1219 * set these, it seems that DMA support increments past the end
1220 * of the packet buffer so we need to calculate the length from
1221 * this information.
1222 */
1223 hs_ep->size_loaded = length;
1224 hs_ep->last_load = ureq->actual;
1225
1226 if (dir_in && !using_dma(hsotg)) {
1227 /* set these anyway, we may need them for non-periodic in */
1228 hs_ep->fifo_load = 0;
1229
1230 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1231 }
1232
1233 /*
1234 * Note, trying to clear the NAK here causes problems with transmit
1235 * on the S3C6400 ending up with the TXFIFO becoming full.
1236 */
1237
1238 /* check ep is enabled */
1239 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1240 dev_dbg(hsotg->dev,
1241 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1242 index, dwc2_readl(hsotg, epctrl_reg));
1243
1244 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1245 __func__, dwc2_readl(hsotg, epctrl_reg));
1246
1247 /* enable ep interrupts */
1248 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1249}
1250
1251/**
1252 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1253 * @hsotg: The device state.
1254 * @hs_ep: The endpoint the request is on.
1255 * @req: The request being processed.
1256 *
1257 * We've been asked to queue a request, so ensure that the memory buffer
1258 * is correctly setup for DMA. If we've been passed an extant DMA address
1259 * then ensure the buffer has been synced to memory. If our buffer has no
1260 * DMA memory, then we map the memory and mark our request to allow us to
1261 * cleanup on completion.
1262 */
1263static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1264 struct dwc2_hsotg_ep *hs_ep,
1265 struct usb_request *req)
1266{
1267 int ret;
1268
1269 hs_ep->map_dir = hs_ep->dir_in;
1270 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1271 if (ret)
1272 goto dma_error;
1273
1274 return 0;
1275
1276dma_error:
1277 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1278 __func__, req->buf, req->length);
1279
1280 return -EIO;
1281}
1282
1283static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1284 struct dwc2_hsotg_ep *hs_ep,
1285 struct dwc2_hsotg_req *hs_req)
1286{
1287 void *req_buf = hs_req->req.buf;
1288
1289 /* If dma is not being used or buffer is aligned */
1290 if (!using_dma(hsotg) || !((long)req_buf & 3))
1291 return 0;
1292
1293 WARN_ON(hs_req->saved_req_buf);
1294
1295 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1296 hs_ep->ep.name, req_buf, hs_req->req.length);
1297
1298 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1299 if (!hs_req->req.buf) {
1300 hs_req->req.buf = req_buf;
1301 dev_err(hsotg->dev,
1302 "%s: unable to allocate memory for bounce buffer\n",
1303 __func__);
1304 return -ENOMEM;
1305 }
1306
1307 /* Save actual buffer */
1308 hs_req->saved_req_buf = req_buf;
1309
1310 if (hs_ep->dir_in)
1311 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1312 return 0;
1313}
1314
1315static void
1316dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1317 struct dwc2_hsotg_ep *hs_ep,
1318 struct dwc2_hsotg_req *hs_req)
1319{
1320 /* If dma is not being used or buffer was aligned */
1321 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1322 return;
1323
1324 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1325 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1326
1327 /* Copy data from bounce buffer on successful out transfer */
1328 if (!hs_ep->dir_in && !hs_req->req.status)
1329 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1330 hs_req->req.actual);
1331
1332 /* Free bounce buffer */
1333 kfree(hs_req->req.buf);
1334
1335 hs_req->req.buf = hs_req->saved_req_buf;
1336 hs_req->saved_req_buf = NULL;
1337}
1338
1339/**
1340 * dwc2_gadget_target_frame_elapsed - Checks target frame
1341 * @hs_ep: The driver endpoint to check
1342 *
1343 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1344 * corresponding transfer.
1345 */
1346static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1347{
1348 struct dwc2_hsotg *hsotg = hs_ep->parent;
1349 u32 target_frame = hs_ep->target_frame;
1350 u32 current_frame = hsotg->frame_number;
1351 bool frame_overrun = hs_ep->frame_overrun;
1352 u16 limit = DSTS_SOFFN_LIMIT;
1353
1354 if (hsotg->gadget.speed != USB_SPEED_HIGH)
1355 limit >>= 3;
1356
1357 if (!frame_overrun && current_frame >= target_frame)
1358 return true;
1359
1360 if (frame_overrun && current_frame >= target_frame &&
1361 ((current_frame - target_frame) < limit / 2))
1362 return true;
1363
1364 return false;
1365}
1366
1367/*
1368 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1369 * @hsotg: The driver state
1370 * @hs_ep: the ep descriptor chain is for
1371 *
1372 * Called to update EP0 structure's pointers depend on stage of
1373 * control transfer.
1374 */
1375static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1376 struct dwc2_hsotg_ep *hs_ep)
1377{
1378 switch (hsotg->ep0_state) {
1379 case DWC2_EP0_SETUP:
1380 case DWC2_EP0_STATUS_OUT:
1381 hs_ep->desc_list = hsotg->setup_desc[0];
1382 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1383 break;
1384 case DWC2_EP0_DATA_IN:
1385 case DWC2_EP0_STATUS_IN:
1386 hs_ep->desc_list = hsotg->ctrl_in_desc;
1387 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1388 break;
1389 case DWC2_EP0_DATA_OUT:
1390 hs_ep->desc_list = hsotg->ctrl_out_desc;
1391 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1392 break;
1393 default:
1394 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1395 hsotg->ep0_state);
1396 return -EINVAL;
1397 }
1398
1399 return 0;
1400}
1401
1402static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1403 gfp_t gfp_flags)
1404{
1405 struct dwc2_hsotg_req *hs_req = our_req(req);
1406 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1407 struct dwc2_hsotg *hs = hs_ep->parent;
1408 bool first;
1409 int ret;
1410 u32 maxsize = 0;
1411 u32 mask = 0;
1412
1413
1414 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1415 ep->name, req, req->length, req->buf, req->no_interrupt,
1416 req->zero, req->short_not_ok);
1417
1418 if (hs->lx_state == DWC2_L1) {
1419 dwc2_wakeup_from_lpm_l1(hs, true);
1420 }
1421
1422 /* Prevent new request submission when controller is suspended */
1423 if (hs->lx_state != DWC2_L0) {
1424 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1425 __func__);
1426 return -EAGAIN;
1427 }
1428
1429 /* initialise status of the request */
1430 INIT_LIST_HEAD(&hs_req->queue);
1431 req->actual = 0;
1432 req->status = -EINPROGRESS;
1433
1434 /* Don't queue ISOC request if length greater than mps*mc */
1435 if (hs_ep->isochronous &&
1436 req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1437 dev_err(hs->dev, "req length > maxpacket*mc\n");
1438 return -EINVAL;
1439 }
1440
1441 /* In DDMA mode for ISOC's don't queue request if length greater
1442 * than descriptor limits.
1443 */
1444 if (using_desc_dma(hs) && hs_ep->isochronous) {
1445 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1446 if (hs_ep->dir_in && req->length > maxsize) {
1447 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1448 req->length, maxsize);
1449 return -EINVAL;
1450 }
1451
1452 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1453 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1454 req->length, hs_ep->ep.maxpacket);
1455 return -EINVAL;
1456 }
1457 }
1458
1459 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1460 if (ret)
1461 return ret;
1462
1463 /* if we're using DMA, sync the buffers as necessary */
1464 if (using_dma(hs)) {
1465 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1466 if (ret)
1467 return ret;
1468 }
1469 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1470 if (using_desc_dma(hs) && !hs_ep->index) {
1471 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1472 if (ret)
1473 return ret;
1474 }
1475
1476 first = list_empty(&hs_ep->queue);
1477 list_add_tail(&hs_req->queue, &hs_ep->queue);
1478
1479 /*
1480 * Handle DDMA isochronous transfers separately - just add new entry
1481 * to the descriptor chain.
1482 * Transfer will be started once SW gets either one of NAK or
1483 * OutTknEpDis interrupts.
1484 */
1485 if (using_desc_dma(hs) && hs_ep->isochronous) {
1486 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1487 dma_addr_t dma_addr = hs_req->req.dma;
1488
1489 if (hs_req->req.num_sgs) {
1490 WARN_ON(hs_req->req.num_sgs > 1);
1491 dma_addr = sg_dma_address(hs_req->req.sg);
1492 }
1493 dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1494 hs_req->req.length);
1495 }
1496 return 0;
1497 }
1498
1499 /* Change EP direction if status phase request is after data out */
1500 if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1501 hs->ep0_state == DWC2_EP0_DATA_OUT)
1502 hs_ep->dir_in = 1;
1503
1504 if (first) {
1505 if (!hs_ep->isochronous) {
1506 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1507 return 0;
1508 }
1509
1510 /* Update current frame number value. */
1511 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1512 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1513 dwc2_gadget_incr_frame_num(hs_ep);
1514 /* Update current frame number value once more as it
1515 * changes here.
1516 */
1517 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1518 }
1519
1520 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1521 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1522 }
1523 return 0;
1524}
1525
1526static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1527 gfp_t gfp_flags)
1528{
1529 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1530 struct dwc2_hsotg *hs = hs_ep->parent;
1531 unsigned long flags;
1532 int ret;
1533
1534 spin_lock_irqsave(&hs->lock, flags);
1535 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1536 spin_unlock_irqrestore(&hs->lock, flags);
1537
1538 return ret;
1539}
1540
1541static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1542 struct usb_request *req)
1543{
1544 struct dwc2_hsotg_req *hs_req = our_req(req);
1545
1546 kfree(hs_req);
1547}
1548
1549/**
1550 * dwc2_hsotg_complete_oursetup - setup completion callback
1551 * @ep: The endpoint the request was on.
1552 * @req: The request completed.
1553 *
1554 * Called on completion of any requests the driver itself
1555 * submitted that need cleaning up.
1556 */
1557static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1558 struct usb_request *req)
1559{
1560 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1561 struct dwc2_hsotg *hsotg = hs_ep->parent;
1562
1563 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1564
1565 dwc2_hsotg_ep_free_request(ep, req);
1566}
1567
1568/**
1569 * ep_from_windex - convert control wIndex value to endpoint
1570 * @hsotg: The driver state.
1571 * @windex: The control request wIndex field (in host order).
1572 *
1573 * Convert the given wIndex into a pointer to an driver endpoint
1574 * structure, or return NULL if it is not a valid endpoint.
1575 */
1576static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1577 u32 windex)
1578{
1579 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1580 int idx = windex & 0x7F;
1581
1582 if (windex >= 0x100)
1583 return NULL;
1584
1585 if (idx > hsotg->num_of_eps)
1586 return NULL;
1587
1588 return index_to_ep(hsotg, idx, dir);
1589}
1590
1591/**
1592 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1593 * @hsotg: The driver state.
1594 * @testmode: requested usb test mode
1595 * Enable usb Test Mode requested by the Host.
1596 */
1597int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1598{
1599 int dctl = dwc2_readl(hsotg, DCTL);
1600
1601 dctl &= ~DCTL_TSTCTL_MASK;
1602 switch (testmode) {
1603 case USB_TEST_J:
1604 case USB_TEST_K:
1605 case USB_TEST_SE0_NAK:
1606 case USB_TEST_PACKET:
1607 case USB_TEST_FORCE_ENABLE:
1608 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1609 break;
1610 default:
1611 return -EINVAL;
1612 }
1613 dwc2_writel(hsotg, dctl, DCTL);
1614 return 0;
1615}
1616
1617/**
1618 * dwc2_hsotg_send_reply - send reply to control request
1619 * @hsotg: The device state
1620 * @ep: Endpoint 0
1621 * @buff: Buffer for request
1622 * @length: Length of reply.
1623 *
1624 * Create a request and queue it on the given endpoint. This is useful as
1625 * an internal method of sending replies to certain control requests, etc.
1626 */
1627static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1628 struct dwc2_hsotg_ep *ep,
1629 void *buff,
1630 int length)
1631{
1632 struct usb_request *req;
1633 int ret;
1634
1635 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1636
1637 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1638 hsotg->ep0_reply = req;
1639 if (!req) {
1640 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1641 return -ENOMEM;
1642 }
1643
1644 req->buf = hsotg->ep0_buff;
1645 req->length = length;
1646 /*
1647 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1648 * STATUS stage.
1649 */
1650 req->zero = 0;
1651 req->complete = dwc2_hsotg_complete_oursetup;
1652
1653 if (length)
1654 memcpy(req->buf, buff, length);
1655
1656 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1657 if (ret) {
1658 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1659 return ret;
1660 }
1661
1662 return 0;
1663}
1664
1665/**
1666 * dwc2_hsotg_process_req_status - process request GET_STATUS
1667 * @hsotg: The device state
1668 * @ctrl: USB control request
1669 */
1670static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1671 struct usb_ctrlrequest *ctrl)
1672{
1673 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1674 struct dwc2_hsotg_ep *ep;
1675 __le16 reply;
1676 u16 status;
1677 int ret;
1678
1679 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1680
1681 if (!ep0->dir_in) {
1682 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1683 return -EINVAL;
1684 }
1685
1686 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1687 case USB_RECIP_DEVICE:
1688 status = hsotg->gadget.is_selfpowered <<
1689 USB_DEVICE_SELF_POWERED;
1690 status |= hsotg->remote_wakeup_allowed <<
1691 USB_DEVICE_REMOTE_WAKEUP;
1692 reply = cpu_to_le16(status);
1693 break;
1694
1695 case USB_RECIP_INTERFACE:
1696 /* currently, the data result should be zero */
1697 reply = cpu_to_le16(0);
1698 break;
1699
1700 case USB_RECIP_ENDPOINT:
1701 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1702 if (!ep)
1703 return -ENOENT;
1704
1705 reply = cpu_to_le16(ep->halted ? 1 : 0);
1706 break;
1707
1708 default:
1709 return 0;
1710 }
1711
1712 if (le16_to_cpu(ctrl->wLength) != 2)
1713 return -EINVAL;
1714
1715 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1716 if (ret) {
1717 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1718 return ret;
1719 }
1720
1721 return 1;
1722}
1723
1724static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1725
1726/**
1727 * get_ep_head - return the first request on the endpoint
1728 * @hs_ep: The controller endpoint to get
1729 *
1730 * Get the first request on the endpoint.
1731 */
1732static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1733{
1734 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1735 queue);
1736}
1737
1738/**
1739 * dwc2_gadget_start_next_request - Starts next request from ep queue
1740 * @hs_ep: Endpoint structure
1741 *
1742 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1743 * in its handler. Hence we need to unmask it here to be able to do
1744 * resynchronization.
1745 */
1746static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1747{
1748 struct dwc2_hsotg *hsotg = hs_ep->parent;
1749 int dir_in = hs_ep->dir_in;
1750 struct dwc2_hsotg_req *hs_req;
1751
1752 if (!list_empty(&hs_ep->queue)) {
1753 hs_req = get_ep_head(hs_ep);
1754 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1755 return;
1756 }
1757 if (!hs_ep->isochronous)
1758 return;
1759
1760 if (dir_in) {
1761 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1762 __func__);
1763 } else {
1764 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1765 __func__);
1766 }
1767}
1768
1769/**
1770 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1771 * @hsotg: The device state
1772 * @ctrl: USB control request
1773 */
1774static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1775 struct usb_ctrlrequest *ctrl)
1776{
1777 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1778 struct dwc2_hsotg_req *hs_req;
1779 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1780 struct dwc2_hsotg_ep *ep;
1781 int ret;
1782 bool halted;
1783 u32 recip;
1784 u32 wValue;
1785 u32 wIndex;
1786
1787 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1788 __func__, set ? "SET" : "CLEAR");
1789
1790 wValue = le16_to_cpu(ctrl->wValue);
1791 wIndex = le16_to_cpu(ctrl->wIndex);
1792 recip = ctrl->bRequestType & USB_RECIP_MASK;
1793
1794 switch (recip) {
1795 case USB_RECIP_DEVICE:
1796 switch (wValue) {
1797 case USB_DEVICE_REMOTE_WAKEUP:
1798 if (set)
1799 hsotg->remote_wakeup_allowed = 1;
1800 else
1801 hsotg->remote_wakeup_allowed = 0;
1802 break;
1803
1804 case USB_DEVICE_TEST_MODE:
1805 if ((wIndex & 0xff) != 0)
1806 return -EINVAL;
1807 if (!set)
1808 return -EINVAL;
1809
1810 hsotg->test_mode = wIndex >> 8;
1811 break;
1812 default:
1813 return -ENOENT;
1814 }
1815
1816 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1817 if (ret) {
1818 dev_err(hsotg->dev,
1819 "%s: failed to send reply\n", __func__);
1820 return ret;
1821 }
1822 break;
1823
1824 case USB_RECIP_ENDPOINT:
1825 ep = ep_from_windex(hsotg, wIndex);
1826 if (!ep) {
1827 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1828 __func__, wIndex);
1829 return -ENOENT;
1830 }
1831
1832 switch (wValue) {
1833 case USB_ENDPOINT_HALT:
1834 halted = ep->halted;
1835
1836 if (!ep->wedged)
1837 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1838
1839 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1840 if (ret) {
1841 dev_err(hsotg->dev,
1842 "%s: failed to send reply\n", __func__);
1843 return ret;
1844 }
1845
1846 /*
1847 * we have to complete all requests for ep if it was
1848 * halted, and the halt was cleared by CLEAR_FEATURE
1849 */
1850
1851 if (!set && halted) {
1852 /*
1853 * If we have request in progress,
1854 * then complete it
1855 */
1856 if (ep->req) {
1857 hs_req = ep->req;
1858 ep->req = NULL;
1859 list_del_init(&hs_req->queue);
1860 if (hs_req->req.complete) {
1861 spin_unlock(&hsotg->lock);
1862 usb_gadget_giveback_request(
1863 &ep->ep, &hs_req->req);
1864 spin_lock(&hsotg->lock);
1865 }
1866 }
1867
1868 /* If we have pending request, then start it */
1869 if (!ep->req)
1870 dwc2_gadget_start_next_request(ep);
1871 }
1872
1873 break;
1874
1875 default:
1876 return -ENOENT;
1877 }
1878 break;
1879 default:
1880 return -ENOENT;
1881 }
1882 return 1;
1883}
1884
1885static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1886
1887/**
1888 * dwc2_hsotg_stall_ep0 - stall ep0
1889 * @hsotg: The device state
1890 *
1891 * Set stall for ep0 as response for setup request.
1892 */
1893static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1894{
1895 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1896 u32 reg;
1897 u32 ctrl;
1898
1899 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1900 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1901
1902 /*
1903 * DxEPCTL_Stall will be cleared by EP once it has
1904 * taken effect, so no need to clear later.
1905 */
1906
1907 ctrl = dwc2_readl(hsotg, reg);
1908 ctrl |= DXEPCTL_STALL;
1909 ctrl |= DXEPCTL_CNAK;
1910 dwc2_writel(hsotg, ctrl, reg);
1911
1912 dev_dbg(hsotg->dev,
1913 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1914 ctrl, reg, dwc2_readl(hsotg, reg));
1915
1916 /*
1917 * complete won't be called, so we enqueue
1918 * setup request here
1919 */
1920 dwc2_hsotg_enqueue_setup(hsotg);
1921}
1922
1923/**
1924 * dwc2_hsotg_process_control - process a control request
1925 * @hsotg: The device state
1926 * @ctrl: The control request received
1927 *
1928 * The controller has received the SETUP phase of a control request, and
1929 * needs to work out what to do next (and whether to pass it on to the
1930 * gadget driver).
1931 */
1932static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1933 struct usb_ctrlrequest *ctrl)
1934{
1935 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1936 int ret = 0;
1937 u32 dcfg;
1938
1939 dev_dbg(hsotg->dev,
1940 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1941 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1942 ctrl->wIndex, ctrl->wLength);
1943
1944 if (ctrl->wLength == 0) {
1945 ep0->dir_in = 1;
1946 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1947 } else if (ctrl->bRequestType & USB_DIR_IN) {
1948 ep0->dir_in = 1;
1949 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1950 } else {
1951 ep0->dir_in = 0;
1952 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1953 }
1954
1955 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1956 switch (ctrl->bRequest) {
1957 case USB_REQ_SET_ADDRESS:
1958 hsotg->connected = 1;
1959 dcfg = dwc2_readl(hsotg, DCFG);
1960 dcfg &= ~DCFG_DEVADDR_MASK;
1961 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1962 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1963 dwc2_writel(hsotg, dcfg, DCFG);
1964
1965 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1966
1967 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1968 return;
1969
1970 case USB_REQ_GET_STATUS:
1971 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1972 break;
1973
1974 case USB_REQ_CLEAR_FEATURE:
1975 case USB_REQ_SET_FEATURE:
1976 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1977 break;
1978 }
1979 }
1980
1981 /* as a fallback, try delivering it to the driver to deal with */
1982
1983 if (ret == 0 && hsotg->driver) {
1984 spin_unlock(&hsotg->lock);
1985 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1986 spin_lock(&hsotg->lock);
1987 if (ret < 0)
1988 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1989 }
1990
1991 hsotg->delayed_status = false;
1992 if (ret == USB_GADGET_DELAYED_STATUS)
1993 hsotg->delayed_status = true;
1994
1995 /*
1996 * the request is either unhandlable, or is not formatted correctly
1997 * so respond with a STALL for the status stage to indicate failure.
1998 */
1999
2000 if (ret < 0)
2001 dwc2_hsotg_stall_ep0(hsotg);
2002}
2003
2004/**
2005 * dwc2_hsotg_complete_setup - completion of a setup transfer
2006 * @ep: The endpoint the request was on.
2007 * @req: The request completed.
2008 *
2009 * Called on completion of any requests the driver itself submitted for
2010 * EP0 setup packets
2011 */
2012static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
2013 struct usb_request *req)
2014{
2015 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2016 struct dwc2_hsotg *hsotg = hs_ep->parent;
2017
2018 if (req->status < 0) {
2019 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
2020 return;
2021 }
2022
2023 spin_lock(&hsotg->lock);
2024 if (req->actual == 0)
2025 dwc2_hsotg_enqueue_setup(hsotg);
2026 else
2027 dwc2_hsotg_process_control(hsotg, req->buf);
2028 spin_unlock(&hsotg->lock);
2029}
2030
2031/**
2032 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
2033 * @hsotg: The device state.
2034 *
2035 * Enqueue a request on EP0 if necessary to received any SETUP packets
2036 * received from the host.
2037 */
2038static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
2039{
2040 struct usb_request *req = hsotg->ctrl_req;
2041 struct dwc2_hsotg_req *hs_req = our_req(req);
2042 int ret;
2043
2044 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2045
2046 req->zero = 0;
2047 req->length = 8;
2048 req->buf = hsotg->ctrl_buff;
2049 req->complete = dwc2_hsotg_complete_setup;
2050
2051 if (!list_empty(&hs_req->queue)) {
2052 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2053 return;
2054 }
2055
2056 hsotg->eps_out[0]->dir_in = 0;
2057 hsotg->eps_out[0]->send_zlp = 0;
2058 hsotg->ep0_state = DWC2_EP0_SETUP;
2059
2060 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2061 if (ret < 0) {
2062 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2063 /*
2064 * Don't think there's much we can do other than watch the
2065 * driver fail.
2066 */
2067 }
2068}
2069
2070static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2071 struct dwc2_hsotg_ep *hs_ep)
2072{
2073 u32 ctrl;
2074 u8 index = hs_ep->index;
2075 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2076 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
2077
2078 if (hs_ep->dir_in)
2079 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2080 index);
2081 else
2082 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2083 index);
2084 if (using_desc_dma(hsotg)) {
2085 /* Not specific buffer needed for ep0 ZLP */
2086 dma_addr_t dma = hs_ep->desc_list_dma;
2087
2088 if (!index)
2089 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2090
2091 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
2092 } else {
2093 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2094 DXEPTSIZ_XFERSIZE(0),
2095 epsiz_reg);
2096 }
2097
2098 ctrl = dwc2_readl(hsotg, epctl_reg);
2099 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
2100 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
2101 ctrl |= DXEPCTL_USBACTEP;
2102 dwc2_writel(hsotg, ctrl, epctl_reg);
2103}
2104
2105/**
2106 * dwc2_hsotg_complete_request - complete a request given to us
2107 * @hsotg: The device state.
2108 * @hs_ep: The endpoint the request was on.
2109 * @hs_req: The request to complete.
2110 * @result: The result code (0 => Ok, otherwise errno)
2111 *
2112 * The given request has finished, so call the necessary completion
2113 * if it has one and then look to see if we can start a new request
2114 * on the endpoint.
2115 *
2116 * Note, expects the ep to already be locked as appropriate.
2117 */
2118static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2119 struct dwc2_hsotg_ep *hs_ep,
2120 struct dwc2_hsotg_req *hs_req,
2121 int result)
2122{
2123 if (!hs_req) {
2124 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2125 return;
2126 }
2127
2128 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2129 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2130
2131 /*
2132 * only replace the status if we've not already set an error
2133 * from a previous transaction
2134 */
2135
2136 if (hs_req->req.status == -EINPROGRESS)
2137 hs_req->req.status = result;
2138
2139 if (using_dma(hsotg))
2140 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2141
2142 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2143
2144 hs_ep->req = NULL;
2145 list_del_init(&hs_req->queue);
2146
2147 /*
2148 * call the complete request with the locks off, just in case the
2149 * request tries to queue more work for this endpoint.
2150 */
2151
2152 if (hs_req->req.complete) {
2153 spin_unlock(&hsotg->lock);
2154 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2155 spin_lock(&hsotg->lock);
2156 }
2157
2158 /* In DDMA don't need to proceed to starting of next ISOC request */
2159 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2160 return;
2161
2162 /*
2163 * Look to see if there is anything else to do. Note, the completion
2164 * of the previous request may have caused a new request to be started
2165 * so be careful when doing this.
2166 */
2167
2168 if (!hs_ep->req && result >= 0)
2169 dwc2_gadget_start_next_request(hs_ep);
2170}
2171
2172/*
2173 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2174 * @hs_ep: The endpoint the request was on.
2175 *
2176 * Get first request from the ep queue, determine descriptor on which complete
2177 * happened. SW discovers which descriptor currently in use by HW, adjusts
2178 * dma_address and calculates index of completed descriptor based on the value
2179 * of DEPDMA register. Update actual length of request, giveback to gadget.
2180 */
2181static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2182{
2183 struct dwc2_hsotg *hsotg = hs_ep->parent;
2184 struct dwc2_hsotg_req *hs_req;
2185 struct usb_request *ureq;
2186 u32 desc_sts;
2187 u32 mask;
2188
2189 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2190
2191 /* Process only descriptors with buffer status set to DMA done */
2192 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2193 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2194
2195 hs_req = get_ep_head(hs_ep);
2196 if (!hs_req) {
2197 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2198 return;
2199 }
2200 ureq = &hs_req->req;
2201
2202 /* Check completion status */
2203 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2204 DEV_DMA_STS_SUCC) {
2205 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2206 DEV_DMA_ISOC_RX_NBYTES_MASK;
2207 ureq->actual = ureq->length - ((desc_sts & mask) >>
2208 DEV_DMA_ISOC_NBYTES_SHIFT);
2209
2210 /* Adjust actual len for ISOC Out if len is
2211 * not align of 4
2212 */
2213 if (!hs_ep->dir_in && ureq->length & 0x3)
2214 ureq->actual += 4 - (ureq->length & 0x3);
2215
2216 /* Set actual frame number for completed transfers */
2217 ureq->frame_number =
2218 (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2219 DEV_DMA_ISOC_FRNUM_SHIFT;
2220 }
2221
2222 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2223
2224 hs_ep->compl_desc++;
2225 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
2226 hs_ep->compl_desc = 0;
2227 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2228 }
2229}
2230
2231/*
2232 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2233 * @hs_ep: The isochronous endpoint.
2234 *
2235 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2236 * interrupt. Reset target frame and next_desc to allow to start
2237 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2238 * interrupt for OUT direction.
2239 */
2240static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2241{
2242 struct dwc2_hsotg *hsotg = hs_ep->parent;
2243
2244 if (!hs_ep->dir_in)
2245 dwc2_flush_rx_fifo(hsotg);
2246 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2247
2248 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2249 hs_ep->next_desc = 0;
2250 hs_ep->compl_desc = 0;
2251}
2252
2253/**
2254 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2255 * @hsotg: The device state.
2256 * @ep_idx: The endpoint index for the data
2257 * @size: The size of data in the fifo, in bytes
2258 *
2259 * The FIFO status shows there is data to read from the FIFO for a given
2260 * endpoint, so sort out whether we need to read the data into a request
2261 * that has been made for that endpoint.
2262 */
2263static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2264{
2265 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2266 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2267 int to_read;
2268 int max_req;
2269 int read_ptr;
2270
2271 if (!hs_req) {
2272 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2273 int ptr;
2274
2275 dev_dbg(hsotg->dev,
2276 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2277 __func__, size, ep_idx, epctl);
2278
2279 /* dump the data from the FIFO, we've nothing we can do */
2280 for (ptr = 0; ptr < size; ptr += 4)
2281 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2282
2283 return;
2284 }
2285
2286 to_read = size;
2287 read_ptr = hs_req->req.actual;
2288 max_req = hs_req->req.length - read_ptr;
2289
2290 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2291 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2292
2293 if (to_read > max_req) {
2294 /*
2295 * more data appeared than we where willing
2296 * to deal with in this request.
2297 */
2298
2299 /* currently we don't deal this */
2300 WARN_ON_ONCE(1);
2301 }
2302
2303 hs_ep->total_data += to_read;
2304 hs_req->req.actual += to_read;
2305 to_read = DIV_ROUND_UP(to_read, 4);
2306
2307 /*
2308 * note, we might over-write the buffer end by 3 bytes depending on
2309 * alignment of the data.
2310 */
2311 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2312 hs_req->req.buf + read_ptr, to_read);
2313}
2314
2315/**
2316 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2317 * @hsotg: The device instance
2318 * @dir_in: If IN zlp
2319 *
2320 * Generate a zero-length IN packet request for terminating a SETUP
2321 * transaction.
2322 *
2323 * Note, since we don't write any data to the TxFIFO, then it is
2324 * currently believed that we do not need to wait for any space in
2325 * the TxFIFO.
2326 */
2327static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2328{
2329 /* eps_out[0] is used in both directions */
2330 hsotg->eps_out[0]->dir_in = dir_in;
2331 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2332
2333 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2334}
2335
2336/*
2337 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2338 * @hs_ep - The endpoint on which transfer went
2339 *
2340 * Iterate over endpoints descriptor chain and get info on bytes remained
2341 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2342 */
2343static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2344{
2345 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
2346 struct dwc2_hsotg *hsotg = hs_ep->parent;
2347 unsigned int bytes_rem = 0;
2348 unsigned int bytes_rem_correction = 0;
2349 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2350 int i;
2351 u32 status;
2352 u32 mps = hs_ep->ep.maxpacket;
2353 int dir_in = hs_ep->dir_in;
2354
2355 if (!desc)
2356 return -EINVAL;
2357
2358 /* Interrupt OUT EP with mps not multiple of 4 */
2359 if (hs_ep->index)
2360 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
2361 bytes_rem_correction = 4 - (mps % 4);
2362
2363 for (i = 0; i < hs_ep->desc_count; ++i) {
2364 status = desc->status;
2365 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2366 bytes_rem -= bytes_rem_correction;
2367
2368 if (status & DEV_DMA_STS_MASK)
2369 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2370 i, status & DEV_DMA_STS_MASK);
2371
2372 if (status & DEV_DMA_L)
2373 break;
2374
2375 desc++;
2376 }
2377
2378 return bytes_rem;
2379}
2380
2381/**
2382 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2383 * @hsotg: The device instance
2384 * @epnum: The endpoint received from
2385 *
2386 * The RXFIFO has delivered an OutDone event, which means that the data
2387 * transfer for an OUT endpoint has been completed, either by a short
2388 * packet or by the finish of a transfer.
2389 */
2390static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2391{
2392 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2393 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2394 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2395 struct usb_request *req = &hs_req->req;
2396 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2397 int result = 0;
2398
2399 if (!hs_req) {
2400 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2401 return;
2402 }
2403
2404 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2405 dev_dbg(hsotg->dev, "zlp packet received\n");
2406 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2407 dwc2_hsotg_enqueue_setup(hsotg);
2408 return;
2409 }
2410
2411 if (using_desc_dma(hsotg))
2412 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2413
2414 if (using_dma(hsotg)) {
2415 unsigned int size_done;
2416
2417 /*
2418 * Calculate the size of the transfer by checking how much
2419 * is left in the endpoint size register and then working it
2420 * out from the amount we loaded for the transfer.
2421 *
2422 * We need to do this as DMA pointers are always 32bit aligned
2423 * so may overshoot/undershoot the transfer.
2424 */
2425
2426 size_done = hs_ep->size_loaded - size_left;
2427 size_done += hs_ep->last_load;
2428
2429 req->actual = size_done;
2430 }
2431
2432 /* if there is more request to do, schedule new transfer */
2433 if (req->actual < req->length && size_left == 0) {
2434 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2435 return;
2436 }
2437
2438 if (req->actual < req->length && req->short_not_ok) {
2439 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2440 __func__, req->actual, req->length);
2441
2442 /*
2443 * todo - what should we return here? there's no one else
2444 * even bothering to check the status.
2445 */
2446 }
2447
2448 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2449 if (!using_desc_dma(hsotg) && epnum == 0 &&
2450 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2451 /* Move to STATUS IN */
2452 if (!hsotg->delayed_status)
2453 dwc2_hsotg_ep0_zlp(hsotg, true);
2454 }
2455
2456 /* Set actual frame number for completed transfers */
2457 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2458 req->frame_number = hs_ep->target_frame;
2459 dwc2_gadget_incr_frame_num(hs_ep);
2460 }
2461
2462 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2463}
2464
2465/**
2466 * dwc2_hsotg_handle_rx - RX FIFO has data
2467 * @hsotg: The device instance
2468 *
2469 * The IRQ handler has detected that the RX FIFO has some data in it
2470 * that requires processing, so find out what is in there and do the
2471 * appropriate read.
2472 *
2473 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2474 * chunks, so if you have x packets received on an endpoint you'll get x
2475 * FIFO events delivered, each with a packet's worth of data in it.
2476 *
2477 * When using DMA, we should not be processing events from the RXFIFO
2478 * as the actual data should be sent to the memory directly and we turn
2479 * on the completion interrupts to get notifications of transfer completion.
2480 */
2481static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2482{
2483 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2484 u32 epnum, status, size;
2485
2486 WARN_ON(using_dma(hsotg));
2487
2488 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2489 status = grxstsr & GRXSTS_PKTSTS_MASK;
2490
2491 size = grxstsr & GRXSTS_BYTECNT_MASK;
2492 size >>= GRXSTS_BYTECNT_SHIFT;
2493
2494 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2495 __func__, grxstsr, size, epnum);
2496
2497 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2498 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2499 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2500 break;
2501
2502 case GRXSTS_PKTSTS_OUTDONE:
2503 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2504 dwc2_hsotg_read_frameno(hsotg));
2505
2506 if (!using_dma(hsotg))
2507 dwc2_hsotg_handle_outdone(hsotg, epnum);
2508 break;
2509
2510 case GRXSTS_PKTSTS_SETUPDONE:
2511 dev_dbg(hsotg->dev,
2512 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2513 dwc2_hsotg_read_frameno(hsotg),
2514 dwc2_readl(hsotg, DOEPCTL(0)));
2515 /*
2516 * Call dwc2_hsotg_handle_outdone here if it was not called from
2517 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2518 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2519 */
2520 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2521 dwc2_hsotg_handle_outdone(hsotg, epnum);
2522 break;
2523
2524 case GRXSTS_PKTSTS_OUTRX:
2525 dwc2_hsotg_rx_data(hsotg, epnum, size);
2526 break;
2527
2528 case GRXSTS_PKTSTS_SETUPRX:
2529 dev_dbg(hsotg->dev,
2530 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2531 dwc2_hsotg_read_frameno(hsotg),
2532 dwc2_readl(hsotg, DOEPCTL(0)));
2533
2534 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2535
2536 dwc2_hsotg_rx_data(hsotg, epnum, size);
2537 break;
2538
2539 default:
2540 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2541 __func__, grxstsr);
2542
2543 dwc2_hsotg_dump(hsotg);
2544 break;
2545 }
2546}
2547
2548/**
2549 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2550 * @mps: The maximum packet size in bytes.
2551 */
2552static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2553{
2554 switch (mps) {
2555 case 64:
2556 return D0EPCTL_MPS_64;
2557 case 32:
2558 return D0EPCTL_MPS_32;
2559 case 16:
2560 return D0EPCTL_MPS_16;
2561 case 8:
2562 return D0EPCTL_MPS_8;
2563 }
2564
2565 /* bad max packet size, warn and return invalid result */
2566 WARN_ON(1);
2567 return (u32)-1;
2568}
2569
2570/**
2571 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2572 * @hsotg: The driver state.
2573 * @ep: The index number of the endpoint
2574 * @mps: The maximum packet size in bytes
2575 * @mc: The multicount value
2576 * @dir_in: True if direction is in.
2577 *
2578 * Configure the maximum packet size for the given endpoint, updating
2579 * the hardware control registers to reflect this.
2580 */
2581static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2582 unsigned int ep, unsigned int mps,
2583 unsigned int mc, unsigned int dir_in)
2584{
2585 struct dwc2_hsotg_ep *hs_ep;
2586 u32 reg;
2587
2588 hs_ep = index_to_ep(hsotg, ep, dir_in);
2589 if (!hs_ep)
2590 return;
2591
2592 if (ep == 0) {
2593 u32 mps_bytes = mps;
2594
2595 /* EP0 is a special case */
2596 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2597 if (mps > 3)
2598 goto bad_mps;
2599 hs_ep->ep.maxpacket = mps_bytes;
2600 hs_ep->mc = 1;
2601 } else {
2602 if (mps > 1024)
2603 goto bad_mps;
2604 hs_ep->mc = mc;
2605 if (mc > 3)
2606 goto bad_mps;
2607 hs_ep->ep.maxpacket = mps;
2608 }
2609
2610 if (dir_in) {
2611 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2612 reg &= ~DXEPCTL_MPS_MASK;
2613 reg |= mps;
2614 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2615 } else {
2616 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2617 reg &= ~DXEPCTL_MPS_MASK;
2618 reg |= mps;
2619 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2620 }
2621
2622 return;
2623
2624bad_mps:
2625 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2626}
2627
2628/**
2629 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2630 * @hsotg: The driver state
2631 * @idx: The index for the endpoint (0..15)
2632 */
2633static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2634{
2635 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2636 GRSTCTL);
2637
2638 /* wait until the fifo is flushed */
2639 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2640 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2641 __func__);
2642}
2643
2644/**
2645 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2646 * @hsotg: The driver state
2647 * @hs_ep: The driver endpoint to check.
2648 *
2649 * Check to see if there is a request that has data to send, and if so
2650 * make an attempt to write data into the FIFO.
2651 */
2652static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2653 struct dwc2_hsotg_ep *hs_ep)
2654{
2655 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2656
2657 if (!hs_ep->dir_in || !hs_req) {
2658 /**
2659 * if request is not enqueued, we disable interrupts
2660 * for endpoints, excepting ep0
2661 */
2662 if (hs_ep->index != 0)
2663 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2664 hs_ep->dir_in, 0);
2665 return 0;
2666 }
2667
2668 if (hs_req->req.actual < hs_req->req.length) {
2669 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2670 hs_ep->index);
2671 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2672 }
2673
2674 return 0;
2675}
2676
2677/**
2678 * dwc2_hsotg_complete_in - complete IN transfer
2679 * @hsotg: The device state.
2680 * @hs_ep: The endpoint that has just completed.
2681 *
2682 * An IN transfer has been completed, update the transfer's state and then
2683 * call the relevant completion routines.
2684 */
2685static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2686 struct dwc2_hsotg_ep *hs_ep)
2687{
2688 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2689 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2690 int size_left, size_done;
2691
2692 if (!hs_req) {
2693 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2694 return;
2695 }
2696
2697 /* Finish ZLP handling for IN EP0 transactions */
2698 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2699 dev_dbg(hsotg->dev, "zlp packet sent\n");
2700
2701 /*
2702 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2703 * changed to IN. Change back to complete OUT transfer request
2704 */
2705 hs_ep->dir_in = 0;
2706
2707 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2708 if (hsotg->test_mode) {
2709 int ret;
2710
2711 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2712 if (ret < 0) {
2713 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2714 hsotg->test_mode);
2715 dwc2_hsotg_stall_ep0(hsotg);
2716 return;
2717 }
2718 }
2719 dwc2_hsotg_enqueue_setup(hsotg);
2720 return;
2721 }
2722
2723 /*
2724 * Calculate the size of the transfer by checking how much is left
2725 * in the endpoint size register and then working it out from
2726 * the amount we loaded for the transfer.
2727 *
2728 * We do this even for DMA, as the transfer may have incremented
2729 * past the end of the buffer (DMA transfers are always 32bit
2730 * aligned).
2731 */
2732 if (using_desc_dma(hsotg)) {
2733 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2734 if (size_left < 0)
2735 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2736 size_left);
2737 } else {
2738 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2739 }
2740
2741 size_done = hs_ep->size_loaded - size_left;
2742 size_done += hs_ep->last_load;
2743
2744 if (hs_req->req.actual != size_done)
2745 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2746 __func__, hs_req->req.actual, size_done);
2747
2748 hs_req->req.actual = size_done;
2749 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2750 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2751
2752 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2753 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2754 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2755 return;
2756 }
2757
2758 /* Zlp for all endpoints in non DDMA, for ep0 only in DATA IN stage */
2759 if (hs_ep->send_zlp) {
2760 hs_ep->send_zlp = 0;
2761 if (!using_desc_dma(hsotg)) {
2762 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2763 /* transfer will be completed on next complete interrupt */
2764 return;
2765 }
2766 }
2767
2768 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2769 /* Move to STATUS OUT */
2770 dwc2_hsotg_ep0_zlp(hsotg, false);
2771 return;
2772 }
2773
2774 /* Set actual frame number for completed transfers */
2775 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2776 hs_req->req.frame_number = hs_ep->target_frame;
2777 dwc2_gadget_incr_frame_num(hs_ep);
2778 }
2779
2780 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2781}
2782
2783/**
2784 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2785 * @hsotg: The device state.
2786 * @idx: Index of ep.
2787 * @dir_in: Endpoint direction 1-in 0-out.
2788 *
2789 * Reads for endpoint with given index and direction, by masking
2790 * epint_reg with coresponding mask.
2791 */
2792static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2793 unsigned int idx, int dir_in)
2794{
2795 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2796 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2797 u32 ints;
2798 u32 mask;
2799 u32 diepempmsk;
2800
2801 mask = dwc2_readl(hsotg, epmsk_reg);
2802 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2803 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2804 mask |= DXEPINT_SETUP_RCVD;
2805
2806 ints = dwc2_readl(hsotg, epint_reg);
2807 ints &= mask;
2808 return ints;
2809}
2810
2811/**
2812 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2813 * @hs_ep: The endpoint on which interrupt is asserted.
2814 *
2815 * This interrupt indicates that the endpoint has been disabled per the
2816 * application's request.
2817 *
2818 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2819 * in case of ISOC completes current request.
2820 *
2821 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2822 * request starts it.
2823 */
2824static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2825{
2826 struct dwc2_hsotg *hsotg = hs_ep->parent;
2827 struct dwc2_hsotg_req *hs_req;
2828 unsigned char idx = hs_ep->index;
2829 int dir_in = hs_ep->dir_in;
2830 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2831 int dctl = dwc2_readl(hsotg, DCTL);
2832
2833 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2834
2835 if (dir_in) {
2836 int epctl = dwc2_readl(hsotg, epctl_reg);
2837
2838 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2839
2840 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2841 int dctl = dwc2_readl(hsotg, DCTL);
2842
2843 dctl |= DCTL_CGNPINNAK;
2844 dwc2_writel(hsotg, dctl, DCTL);
2845 }
2846 } else {
2847
2848 if (dctl & DCTL_GOUTNAKSTS) {
2849 dctl |= DCTL_CGOUTNAK;
2850 dwc2_writel(hsotg, dctl, DCTL);
2851 }
2852 }
2853
2854 if (!hs_ep->isochronous)
2855 return;
2856
2857 if (list_empty(&hs_ep->queue)) {
2858 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2859 __func__, hs_ep);
2860 return;
2861 }
2862
2863 do {
2864 hs_req = get_ep_head(hs_ep);
2865 if (hs_req) {
2866 hs_req->req.frame_number = hs_ep->target_frame;
2867 hs_req->req.actual = 0;
2868 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2869 -ENODATA);
2870 }
2871 dwc2_gadget_incr_frame_num(hs_ep);
2872 /* Update current frame number value. */
2873 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2874 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2875}
2876
2877/**
2878 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2879 * @ep: The endpoint on which interrupt is asserted.
2880 *
2881 * This is starting point for ISOC-OUT transfer, synchronization done with
2882 * first out token received from host while corresponding EP is disabled.
2883 *
2884 * Device does not know initial frame in which out token will come. For this
2885 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2886 * getting this interrupt SW starts calculation for next transfer frame.
2887 */
2888static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2889{
2890 struct dwc2_hsotg *hsotg = ep->parent;
2891 struct dwc2_hsotg_req *hs_req;
2892 int dir_in = ep->dir_in;
2893
2894 if (dir_in || !ep->isochronous)
2895 return;
2896
2897 if (using_desc_dma(hsotg)) {
2898 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2899 /* Start first ISO Out */
2900 ep->target_frame = hsotg->frame_number;
2901 dwc2_gadget_start_isoc_ddma(ep);
2902 }
2903 return;
2904 }
2905
2906 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2907 u32 ctrl;
2908
2909 ep->target_frame = hsotg->frame_number;
2910 if (ep->interval > 1) {
2911 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2912 if (ep->target_frame & 0x1)
2913 ctrl |= DXEPCTL_SETODDFR;
2914 else
2915 ctrl |= DXEPCTL_SETEVENFR;
2916
2917 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2918 }
2919 }
2920
2921 while (dwc2_gadget_target_frame_elapsed(ep)) {
2922 hs_req = get_ep_head(ep);
2923 if (hs_req) {
2924 hs_req->req.frame_number = ep->target_frame;
2925 hs_req->req.actual = 0;
2926 dwc2_hsotg_complete_request(hsotg, ep, hs_req, -ENODATA);
2927 }
2928
2929 dwc2_gadget_incr_frame_num(ep);
2930 /* Update current frame number value. */
2931 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2932 }
2933
2934 if (!ep->req)
2935 dwc2_gadget_start_next_request(ep);
2936
2937}
2938
2939static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2940 struct dwc2_hsotg_ep *hs_ep);
2941
2942/**
2943 * dwc2_gadget_handle_nak - handle NAK interrupt
2944 * @hs_ep: The endpoint on which interrupt is asserted.
2945 *
2946 * This is starting point for ISOC-IN transfer, synchronization done with
2947 * first IN token received from host while corresponding EP is disabled.
2948 *
2949 * Device does not know when first one token will arrive from host. On first
2950 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2951 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2952 * sent in response to that as there was no data in FIFO. SW is basing on this
2953 * interrupt to obtain frame in which token has come and then based on the
2954 * interval calculates next frame for transfer.
2955 */
2956static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2957{
2958 struct dwc2_hsotg *hsotg = hs_ep->parent;
2959 struct dwc2_hsotg_req *hs_req;
2960 int dir_in = hs_ep->dir_in;
2961 u32 ctrl;
2962
2963 if (!dir_in || !hs_ep->isochronous)
2964 return;
2965
2966 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2967
2968 if (using_desc_dma(hsotg)) {
2969 hs_ep->target_frame = hsotg->frame_number;
2970 dwc2_gadget_incr_frame_num(hs_ep);
2971
2972 /* In service interval mode target_frame must
2973 * be set to last (u)frame of the service interval.
2974 */
2975 if (hsotg->params.service_interval) {
2976 /* Set target_frame to the first (u)frame of
2977 * the service interval
2978 */
2979 hs_ep->target_frame &= ~hs_ep->interval + 1;
2980
2981 /* Set target_frame to the last (u)frame of
2982 * the service interval
2983 */
2984 dwc2_gadget_incr_frame_num(hs_ep);
2985 dwc2_gadget_dec_frame_num_by_one(hs_ep);
2986 }
2987
2988 dwc2_gadget_start_isoc_ddma(hs_ep);
2989 return;
2990 }
2991
2992 hs_ep->target_frame = hsotg->frame_number;
2993 if (hs_ep->interval > 1) {
2994 u32 ctrl = dwc2_readl(hsotg,
2995 DIEPCTL(hs_ep->index));
2996 if (hs_ep->target_frame & 0x1)
2997 ctrl |= DXEPCTL_SETODDFR;
2998 else
2999 ctrl |= DXEPCTL_SETEVENFR;
3000
3001 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
3002 }
3003 }
3004
3005 if (using_desc_dma(hsotg))
3006 return;
3007
3008 ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index));
3009 if (ctrl & DXEPCTL_EPENA)
3010 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
3011 else
3012 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
3013
3014 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
3015 hs_req = get_ep_head(hs_ep);
3016 if (hs_req) {
3017 hs_req->req.frame_number = hs_ep->target_frame;
3018 hs_req->req.actual = 0;
3019 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
3020 }
3021
3022 dwc2_gadget_incr_frame_num(hs_ep);
3023 /* Update current frame number value. */
3024 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
3025 }
3026
3027 if (!hs_ep->req)
3028 dwc2_gadget_start_next_request(hs_ep);
3029}
3030
3031/**
3032 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
3033 * @hsotg: The driver state
3034 * @idx: The index for the endpoint (0..15)
3035 * @dir_in: Set if this is an IN endpoint
3036 *
3037 * Process and clear any interrupt pending for an individual endpoint
3038 */
3039static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
3040 int dir_in)
3041{
3042 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
3043 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
3044 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
3045 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
3046 u32 ints;
3047
3048 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
3049
3050 /* Clear endpoint interrupts */
3051 dwc2_writel(hsotg, ints, epint_reg);
3052
3053 if (!hs_ep) {
3054 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
3055 __func__, idx, dir_in ? "in" : "out");
3056 return;
3057 }
3058
3059 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
3060 __func__, idx, dir_in ? "in" : "out", ints);
3061
3062 /* Don't process XferCompl interrupt if it is a setup packet */
3063 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
3064 ints &= ~DXEPINT_XFERCOMPL;
3065
3066 /*
3067 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
3068 * stage and xfercomplete was generated without SETUP phase done
3069 * interrupt. SW should parse received setup packet only after host's
3070 * exit from setup phase of control transfer.
3071 */
3072 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
3073 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
3074 ints &= ~DXEPINT_XFERCOMPL;
3075
3076 if (ints & DXEPINT_XFERCOMPL) {
3077 dev_dbg(hsotg->dev,
3078 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
3079 __func__, dwc2_readl(hsotg, epctl_reg),
3080 dwc2_readl(hsotg, epsiz_reg));
3081
3082 /* In DDMA handle isochronous requests separately */
3083 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3084 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
3085 } else if (dir_in) {
3086 /*
3087 * We get OutDone from the FIFO, so we only
3088 * need to look at completing IN requests here
3089 * if operating slave mode
3090 */
3091 if (!hs_ep->isochronous || !(ints & DXEPINT_NAKINTRPT))
3092 dwc2_hsotg_complete_in(hsotg, hs_ep);
3093
3094 if (idx == 0 && !hs_ep->req)
3095 dwc2_hsotg_enqueue_setup(hsotg);
3096 } else if (using_dma(hsotg)) {
3097 /*
3098 * We're using DMA, we need to fire an OutDone here
3099 * as we ignore the RXFIFO.
3100 */
3101 if (!hs_ep->isochronous || !(ints & DXEPINT_OUTTKNEPDIS))
3102 dwc2_hsotg_handle_outdone(hsotg, idx);
3103 }
3104 }
3105
3106 if (ints & DXEPINT_EPDISBLD)
3107 dwc2_gadget_handle_ep_disabled(hs_ep);
3108
3109 if (ints & DXEPINT_OUTTKNEPDIS)
3110 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3111
3112 if (ints & DXEPINT_NAKINTRPT)
3113 dwc2_gadget_handle_nak(hs_ep);
3114
3115 if (ints & DXEPINT_AHBERR)
3116 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3117
3118 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
3119 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3120
3121 if (using_dma(hsotg) && idx == 0) {
3122 /*
3123 * this is the notification we've received a
3124 * setup packet. In non-DMA mode we'd get this
3125 * from the RXFIFO, instead we need to process
3126 * the setup here.
3127 */
3128
3129 if (dir_in)
3130 WARN_ON_ONCE(1);
3131 else
3132 dwc2_hsotg_handle_outdone(hsotg, 0);
3133 }
3134 }
3135
3136 if (ints & DXEPINT_STSPHSERCVD) {
3137 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3138
3139 /* Safety check EP0 state when STSPHSERCVD asserted */
3140 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3141 /* Move to STATUS IN for DDMA */
3142 if (using_desc_dma(hsotg)) {
3143 if (!hsotg->delayed_status)
3144 dwc2_hsotg_ep0_zlp(hsotg, true);
3145 else
3146 /* In case of 3 stage Control Write with delayed
3147 * status, when Status IN transfer started
3148 * before STSPHSERCVD asserted, NAKSTS bit not
3149 * cleared by CNAK in dwc2_hsotg_start_req()
3150 * function. Clear now NAKSTS to allow complete
3151 * transfer.
3152 */
3153 dwc2_set_bit(hsotg, DIEPCTL(0),
3154 DXEPCTL_CNAK);
3155 }
3156 }
3157
3158 }
3159
3160 if (ints & DXEPINT_BACK2BACKSETUP)
3161 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3162
3163 if (ints & DXEPINT_BNAINTR) {
3164 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3165 if (hs_ep->isochronous)
3166 dwc2_gadget_handle_isoc_bna(hs_ep);
3167 }
3168
3169 if (dir_in && !hs_ep->isochronous) {
3170 /* not sure if this is important, but we'll clear it anyway */
3171 if (ints & DXEPINT_INTKNTXFEMP) {
3172 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3173 __func__, idx);
3174 }
3175
3176 /* this probably means something bad is happening */
3177 if (ints & DXEPINT_INTKNEPMIS) {
3178 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3179 __func__, idx);
3180 }
3181
3182 /* FIFO has space or is empty (see GAHBCFG) */
3183 if (hsotg->dedicated_fifos &&
3184 ints & DXEPINT_TXFEMP) {
3185 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3186 __func__, idx);
3187 if (!using_dma(hsotg))
3188 dwc2_hsotg_trytx(hsotg, hs_ep);
3189 }
3190 }
3191}
3192
3193/**
3194 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3195 * @hsotg: The device state.
3196 *
3197 * Handle updating the device settings after the enumeration phase has
3198 * been completed.
3199 */
3200static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3201{
3202 u32 dsts = dwc2_readl(hsotg, DSTS);
3203 int ep0_mps = 0, ep_mps = 8;
3204
3205 /*
3206 * This should signal the finish of the enumeration phase
3207 * of the USB handshaking, so we should now know what rate
3208 * we connected at.
3209 */
3210
3211 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3212
3213 /*
3214 * note, since we're limited by the size of transfer on EP0, and
3215 * it seems IN transfers must be a even number of packets we do
3216 * not advertise a 64byte MPS on EP0.
3217 */
3218
3219 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3220 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3221 case DSTS_ENUMSPD_FS:
3222 case DSTS_ENUMSPD_FS48:
3223 hsotg->gadget.speed = USB_SPEED_FULL;
3224 ep0_mps = EP0_MPS_LIMIT;
3225 ep_mps = 1023;
3226 break;
3227
3228 case DSTS_ENUMSPD_HS:
3229 hsotg->gadget.speed = USB_SPEED_HIGH;
3230 ep0_mps = EP0_MPS_LIMIT;
3231 ep_mps = 1024;
3232 break;
3233
3234 case DSTS_ENUMSPD_LS:
3235 hsotg->gadget.speed = USB_SPEED_LOW;
3236 ep0_mps = 8;
3237 ep_mps = 8;
3238 /*
3239 * note, we don't actually support LS in this driver at the
3240 * moment, and the documentation seems to imply that it isn't
3241 * supported by the PHYs on some of the devices.
3242 */
3243 break;
3244 }
3245 dev_info(hsotg->dev, "new device is %s\n",
3246 usb_speed_string(hsotg->gadget.speed));
3247
3248 /*
3249 * we should now know the maximum packet size for an
3250 * endpoint, so set the endpoints to a default value.
3251 */
3252
3253 if (ep0_mps) {
3254 int i;
3255 /* Initialize ep0 for both in and out directions */
3256 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3257 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3258 for (i = 1; i < hsotg->num_of_eps; i++) {
3259 if (hsotg->eps_in[i])
3260 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3261 0, 1);
3262 if (hsotg->eps_out[i])
3263 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3264 0, 0);
3265 }
3266 }
3267
3268 /* ensure after enumeration our EP0 is active */
3269
3270 dwc2_hsotg_enqueue_setup(hsotg);
3271
3272 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3273 dwc2_readl(hsotg, DIEPCTL0),
3274 dwc2_readl(hsotg, DOEPCTL0));
3275}
3276
3277/**
3278 * kill_all_requests - remove all requests from the endpoint's queue
3279 * @hsotg: The device state.
3280 * @ep: The endpoint the requests may be on.
3281 * @result: The result code to use.
3282 *
3283 * Go through the requests on the given endpoint and mark them
3284 * completed with the given result code.
3285 */
3286static void kill_all_requests(struct dwc2_hsotg *hsotg,
3287 struct dwc2_hsotg_ep *ep,
3288 int result)
3289{
3290 unsigned int size;
3291
3292 ep->req = NULL;
3293
3294 while (!list_empty(&ep->queue)) {
3295 struct dwc2_hsotg_req *req = get_ep_head(ep);
3296
3297 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3298 }
3299
3300 if (!hsotg->dedicated_fifos)
3301 return;
3302 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3303 if (size < ep->fifo_size)
3304 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3305}
3306
3307/**
3308 * dwc2_hsotg_disconnect - disconnect service
3309 * @hsotg: The device state.
3310 *
3311 * The device has been disconnected. Remove all current
3312 * transactions and signal the gadget driver that this
3313 * has happened.
3314 */
3315void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3316{
3317 unsigned int ep;
3318
3319 if (!hsotg->connected)
3320 return;
3321
3322 hsotg->connected = 0;
3323 hsotg->test_mode = 0;
3324
3325 /* all endpoints should be shutdown */
3326 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3327 if (hsotg->eps_in[ep])
3328 kill_all_requests(hsotg, hsotg->eps_in[ep],
3329 -ESHUTDOWN);
3330 if (hsotg->eps_out[ep])
3331 kill_all_requests(hsotg, hsotg->eps_out[ep],
3332 -ESHUTDOWN);
3333 }
3334
3335 call_gadget(hsotg, disconnect);
3336 hsotg->lx_state = DWC2_L3;
3337
3338 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3339}
3340
3341/**
3342 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3343 * @hsotg: The device state:
3344 * @periodic: True if this is a periodic FIFO interrupt
3345 */
3346static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3347{
3348 struct dwc2_hsotg_ep *ep;
3349 int epno, ret;
3350
3351 /* look through for any more data to transmit */
3352 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3353 ep = index_to_ep(hsotg, epno, 1);
3354
3355 if (!ep)
3356 continue;
3357
3358 if (!ep->dir_in)
3359 continue;
3360
3361 if ((periodic && !ep->periodic) ||
3362 (!periodic && ep->periodic))
3363 continue;
3364
3365 ret = dwc2_hsotg_trytx(hsotg, ep);
3366 if (ret < 0)
3367 break;
3368 }
3369}
3370
3371/* IRQ flags which will trigger a retry around the IRQ loop */
3372#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3373 GINTSTS_PTXFEMP | \
3374 GINTSTS_RXFLVL)
3375
3376static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3377/**
3378 * dwc2_hsotg_core_init_disconnected - issue softreset to the core
3379 * @hsotg: The device state
3380 * @is_usb_reset: Usb resetting flag
3381 *
3382 * Issue a soft reset to the core, and await the core finishing it.
3383 */
3384void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3385 bool is_usb_reset)
3386{
3387 u32 intmsk;
3388 u32 val;
3389 u32 usbcfg;
3390 u32 dcfg = 0;
3391 int ep;
3392
3393 /* Kill any ep0 requests as controller will be reinitialized */
3394 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3395
3396 if (!is_usb_reset) {
3397 if (dwc2_core_reset(hsotg, true))
3398 return;
3399 } else {
3400 /* all endpoints should be shutdown */
3401 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3402 if (hsotg->eps_in[ep])
3403 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3404 if (hsotg->eps_out[ep])
3405 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3406 }
3407 }
3408
3409 /*
3410 * we must now enable ep0 ready for host detection and then
3411 * set configuration.
3412 */
3413
3414 /* keep other bits untouched (so e.g. forced modes are not lost) */
3415 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3416 usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3417 usbcfg |= GUSBCFG_TOUTCAL(7);
3418
3419 /* remove the HNP/SRP and set the PHY */
3420 usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3421 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3422
3423 dwc2_phy_init(hsotg, true);
3424
3425 dwc2_hsotg_init_fifo(hsotg);
3426
3427 if (!is_usb_reset) {
3428 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3429 if (hsotg->params.eusb2_disc)
3430 dwc2_set_bit(hsotg, GOTGCTL, GOTGCTL_EUSB2_DISC_SUPP);
3431 }
3432
3433 dcfg |= DCFG_EPMISCNT(1);
3434
3435 switch (hsotg->params.speed) {
3436 case DWC2_SPEED_PARAM_LOW:
3437 dcfg |= DCFG_DEVSPD_LS;
3438 break;
3439 case DWC2_SPEED_PARAM_FULL:
3440 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3441 dcfg |= DCFG_DEVSPD_FS48;
3442 else
3443 dcfg |= DCFG_DEVSPD_FS;
3444 break;
3445 default:
3446 dcfg |= DCFG_DEVSPD_HS;
3447 }
3448
3449 if (hsotg->params.ipg_isoc_en)
3450 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3451
3452 dwc2_writel(hsotg, dcfg, DCFG);
3453
3454 /* Clear any pending OTG interrupts */
3455 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3456
3457 /* Clear any pending interrupts */
3458 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3459 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3460 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3461 GINTSTS_USBRST | GINTSTS_RESETDET |
3462 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3463 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3464 GINTSTS_LPMTRANRCVD;
3465
3466 if (!using_desc_dma(hsotg))
3467 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3468
3469 if (!hsotg->params.external_id_pin_ctl)
3470 intmsk |= GINTSTS_CONIDSTSCHNG;
3471
3472 dwc2_writel(hsotg, intmsk, GINTMSK);
3473
3474 if (using_dma(hsotg)) {
3475 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3476 hsotg->params.ahbcfg,
3477 GAHBCFG);
3478
3479 /* Set DDMA mode support in the core if needed */
3480 if (using_desc_dma(hsotg))
3481 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3482
3483 } else {
3484 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3485 (GAHBCFG_NP_TXF_EMP_LVL |
3486 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3487 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3488 }
3489
3490 /*
3491 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3492 * when we have no data to transfer. Otherwise we get being flooded by
3493 * interrupts.
3494 */
3495
3496 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3497 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3498 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3499 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3500 DIEPMSK);
3501
3502 /*
3503 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3504 * DMA mode we may need this and StsPhseRcvd.
3505 */
3506 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3507 DOEPMSK_STSPHSERCVDMSK) : 0) |
3508 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3509 DOEPMSK_SETUPMSK,
3510 DOEPMSK);
3511
3512 /* Enable BNA interrupt for DDMA */
3513 if (using_desc_dma(hsotg)) {
3514 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3515 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3516 }
3517
3518 /* Enable Service Interval mode if supported */
3519 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3520 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3521
3522 dwc2_writel(hsotg, 0, DAINTMSK);
3523
3524 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3525 dwc2_readl(hsotg, DIEPCTL0),
3526 dwc2_readl(hsotg, DOEPCTL0));
3527
3528 /* enable in and out endpoint interrupts */
3529 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3530
3531 /*
3532 * Enable the RXFIFO when in slave mode, as this is how we collect
3533 * the data. In DMA mode, we get events from the FIFO but also
3534 * things we cannot process, so do not use it.
3535 */
3536 if (!using_dma(hsotg))
3537 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3538
3539 /* Enable interrupts for EP0 in and out */
3540 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3541 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3542
3543 if (!is_usb_reset) {
3544 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3545 udelay(10); /* see openiboot */
3546 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3547 }
3548
3549 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3550
3551 /*
3552 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3553 * writing to the EPCTL register..
3554 */
3555
3556 /* set to read 1 8byte packet */
3557 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3558 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3559
3560 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3561 DXEPCTL_CNAK | DXEPCTL_EPENA |
3562 DXEPCTL_USBACTEP,
3563 DOEPCTL0);
3564
3565 /* enable, but don't activate EP0in */
3566 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3567 DXEPCTL_USBACTEP, DIEPCTL0);
3568
3569 /* clear global NAKs */
3570 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3571 if (!is_usb_reset)
3572 val |= DCTL_SFTDISCON;
3573 dwc2_set_bit(hsotg, DCTL, val);
3574
3575 /* configure the core to support LPM */
3576 dwc2_gadget_init_lpm(hsotg);
3577
3578 /* program GREFCLK register if needed */
3579 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3580 dwc2_gadget_program_ref_clk(hsotg);
3581
3582 /* must be at-least 3ms to allow bus to see disconnect */
3583 mdelay(3);
3584
3585 hsotg->lx_state = DWC2_L0;
3586
3587 dwc2_hsotg_enqueue_setup(hsotg);
3588
3589 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3590 dwc2_readl(hsotg, DIEPCTL0),
3591 dwc2_readl(hsotg, DOEPCTL0));
3592}
3593
3594void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3595{
3596 /* set the soft-disconnect bit */
3597 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3598}
3599
3600void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3601{
3602 /* remove the soft-disconnect and let's go */
3603 if (!hsotg->role_sw || (dwc2_readl(hsotg, GOTGCTL) & GOTGCTL_BSESVLD))
3604 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3605}
3606
3607/**
3608 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3609 * @hsotg: The device state:
3610 *
3611 * This interrupt indicates one of the following conditions occurred while
3612 * transmitting an ISOC transaction.
3613 * - Corrupted IN Token for ISOC EP.
3614 * - Packet not complete in FIFO.
3615 *
3616 * The following actions will be taken:
3617 * - Determine the EP
3618 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3619 */
3620static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3621{
3622 struct dwc2_hsotg_ep *hs_ep;
3623 u32 epctrl;
3624 u32 daintmsk;
3625 u32 idx;
3626
3627 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3628
3629 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3630
3631 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3632 hs_ep = hsotg->eps_in[idx];
3633 /* Proceed only unmasked ISOC EPs */
3634 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3635 continue;
3636
3637 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3638 if ((epctrl & DXEPCTL_EPENA) &&
3639 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3640 epctrl |= DXEPCTL_SNAK;
3641 epctrl |= DXEPCTL_EPDIS;
3642 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3643 }
3644 }
3645
3646 /* Clear interrupt */
3647 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3648}
3649
3650/**
3651 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3652 * @hsotg: The device state:
3653 *
3654 * This interrupt indicates one of the following conditions occurred while
3655 * transmitting an ISOC transaction.
3656 * - Corrupted OUT Token for ISOC EP.
3657 * - Packet not complete in FIFO.
3658 *
3659 * The following actions will be taken:
3660 * - Determine the EP
3661 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3662 */
3663static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3664{
3665 u32 gintsts;
3666 u32 gintmsk;
3667 u32 daintmsk;
3668 u32 epctrl;
3669 struct dwc2_hsotg_ep *hs_ep;
3670 int idx;
3671
3672 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3673
3674 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3675 daintmsk >>= DAINT_OUTEP_SHIFT;
3676
3677 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3678 hs_ep = hsotg->eps_out[idx];
3679 /* Proceed only unmasked ISOC EPs */
3680 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3681 continue;
3682
3683 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3684 if ((epctrl & DXEPCTL_EPENA) &&
3685 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3686 /* Unmask GOUTNAKEFF interrupt */
3687 gintmsk = dwc2_readl(hsotg, GINTMSK);
3688 gintmsk |= GINTSTS_GOUTNAKEFF;
3689 dwc2_writel(hsotg, gintmsk, GINTMSK);
3690
3691 gintsts = dwc2_readl(hsotg, GINTSTS);
3692 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3693 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3694 break;
3695 }
3696 }
3697 }
3698
3699 /* Clear interrupt */
3700 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3701}
3702
3703/**
3704 * dwc2_hsotg_irq - handle device interrupt
3705 * @irq: The IRQ number triggered
3706 * @pw: The pw value when registered the handler.
3707 */
3708static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3709{
3710 struct dwc2_hsotg *hsotg = pw;
3711 int retry_count = 8;
3712 u32 gintsts;
3713 u32 gintmsk;
3714
3715 if (!dwc2_is_device_mode(hsotg))
3716 return IRQ_NONE;
3717
3718 spin_lock(&hsotg->lock);
3719irq_retry:
3720 gintsts = dwc2_readl(hsotg, GINTSTS);
3721 gintmsk = dwc2_readl(hsotg, GINTMSK);
3722
3723 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3724 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3725
3726 gintsts &= gintmsk;
3727
3728 if (gintsts & GINTSTS_RESETDET) {
3729 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3730
3731 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3732
3733 /* This event must be used only if controller is suspended */
3734 if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2)
3735 dwc2_exit_partial_power_down(hsotg, 0, true);
3736
3737 /* Exit gadget mode clock gating. */
3738 if (hsotg->params.power_down ==
3739 DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended &&
3740 !hsotg->params.no_clock_gating)
3741 dwc2_gadget_exit_clock_gating(hsotg, 0);
3742
3743 hsotg->lx_state = DWC2_L0;
3744 }
3745
3746 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3747 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3748 u32 connected = hsotg->connected;
3749
3750 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3751 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3752 dwc2_readl(hsotg, GNPTXSTS));
3753
3754 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3755
3756 /* Report disconnection if it is not already done. */
3757 dwc2_hsotg_disconnect(hsotg);
3758
3759 /* Reset device address to zero */
3760 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3761
3762 if (usb_status & GOTGCTL_BSESVLD && connected)
3763 dwc2_hsotg_core_init_disconnected(hsotg, true);
3764 }
3765
3766 if (gintsts & GINTSTS_ENUMDONE) {
3767 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3768
3769 dwc2_hsotg_irq_enumdone(hsotg);
3770 }
3771
3772 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3773 u32 daint = dwc2_readl(hsotg, DAINT);
3774 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3775 u32 daint_out, daint_in;
3776 int ep;
3777
3778 daint &= daintmsk;
3779 daint_out = daint >> DAINT_OUTEP_SHIFT;
3780 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3781
3782 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3783
3784 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3785 ep++, daint_out >>= 1) {
3786 if (daint_out & 1)
3787 dwc2_hsotg_epint(hsotg, ep, 0);
3788 }
3789
3790 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3791 ep++, daint_in >>= 1) {
3792 if (daint_in & 1)
3793 dwc2_hsotg_epint(hsotg, ep, 1);
3794 }
3795 }
3796
3797 /* check both FIFOs */
3798
3799 if (gintsts & GINTSTS_NPTXFEMP) {
3800 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3801
3802 /*
3803 * Disable the interrupt to stop it happening again
3804 * unless one of these endpoint routines decides that
3805 * it needs re-enabling
3806 */
3807
3808 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3809 dwc2_hsotg_irq_fifoempty(hsotg, false);
3810 }
3811
3812 if (gintsts & GINTSTS_PTXFEMP) {
3813 dev_dbg(hsotg->dev, "PTxFEmp\n");
3814
3815 /* See note in GINTSTS_NPTxFEmp */
3816
3817 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3818 dwc2_hsotg_irq_fifoempty(hsotg, true);
3819 }
3820
3821 if (gintsts & GINTSTS_RXFLVL) {
3822 /*
3823 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3824 * we need to retry dwc2_hsotg_handle_rx if this is still
3825 * set.
3826 */
3827
3828 dwc2_hsotg_handle_rx(hsotg);
3829 }
3830
3831 if (gintsts & GINTSTS_ERLYSUSP) {
3832 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3833 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3834 }
3835
3836 /*
3837 * these next two seem to crop-up occasionally causing the core
3838 * to shutdown the USB transfer, so try clearing them and logging
3839 * the occurrence.
3840 */
3841
3842 if (gintsts & GINTSTS_GOUTNAKEFF) {
3843 u8 idx;
3844 u32 epctrl;
3845 u32 gintmsk;
3846 u32 daintmsk;
3847 struct dwc2_hsotg_ep *hs_ep;
3848
3849 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3850 daintmsk >>= DAINT_OUTEP_SHIFT;
3851 /* Mask this interrupt */
3852 gintmsk = dwc2_readl(hsotg, GINTMSK);
3853 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3854 dwc2_writel(hsotg, gintmsk, GINTMSK);
3855
3856 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3857 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3858 hs_ep = hsotg->eps_out[idx];
3859 /* Proceed only unmasked ISOC EPs */
3860 if (BIT(idx) & ~daintmsk)
3861 continue;
3862
3863 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3864
3865 //ISOC Ep's only
3866 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3867 epctrl |= DXEPCTL_SNAK;
3868 epctrl |= DXEPCTL_EPDIS;
3869 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3870 continue;
3871 }
3872
3873 //Non-ISOC EP's
3874 if (hs_ep->halted) {
3875 if (!(epctrl & DXEPCTL_EPENA))
3876 epctrl |= DXEPCTL_EPENA;
3877 epctrl |= DXEPCTL_EPDIS;
3878 epctrl |= DXEPCTL_STALL;
3879 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3880 }
3881 }
3882
3883 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3884 }
3885
3886 if (gintsts & GINTSTS_GINNAKEFF) {
3887 dev_info(hsotg->dev, "GINNakEff triggered\n");
3888
3889 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3890
3891 dwc2_hsotg_dump(hsotg);
3892 }
3893
3894 if (gintsts & GINTSTS_INCOMPL_SOIN)
3895 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3896
3897 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3898 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3899
3900 /*
3901 * if we've had fifo events, we should try and go around the
3902 * loop again to see if there's any point in returning yet.
3903 */
3904
3905 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3906 goto irq_retry;
3907
3908 /* Check WKUP_ALERT interrupt*/
3909 if (hsotg->params.service_interval)
3910 dwc2_gadget_wkup_alert_handler(hsotg);
3911
3912 spin_unlock(&hsotg->lock);
3913
3914 return IRQ_HANDLED;
3915}
3916
3917static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3918 struct dwc2_hsotg_ep *hs_ep)
3919{
3920 u32 epctrl_reg;
3921 u32 epint_reg;
3922
3923 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3924 DOEPCTL(hs_ep->index);
3925 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3926 DOEPINT(hs_ep->index);
3927
3928 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3929 hs_ep->name);
3930
3931 if (hs_ep->dir_in) {
3932 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3933 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3934 /* Wait for Nak effect */
3935 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3936 DXEPINT_INEPNAKEFF, 100))
3937 dev_warn(hsotg->dev,
3938 "%s: timeout DIEPINT.NAKEFF\n",
3939 __func__);
3940 } else {
3941 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3942 /* Wait for Nak effect */
3943 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3944 GINTSTS_GINNAKEFF, 100))
3945 dev_warn(hsotg->dev,
3946 "%s: timeout GINTSTS.GINNAKEFF\n",
3947 __func__);
3948 }
3949 } else {
3950 /* Mask GINTSTS_GOUTNAKEFF interrupt */
3951 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF);
3952
3953 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3954 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3955
3956 if (!using_dma(hsotg)) {
3957 /* Wait for GINTSTS_RXFLVL interrupt */
3958 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3959 GINTSTS_RXFLVL, 100)) {
3960 dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n",
3961 __func__);
3962 } else {
3963 /*
3964 * Pop GLOBAL OUT NAK status packet from RxFIFO
3965 * to assert GOUTNAKEFF interrupt
3966 */
3967 dwc2_readl(hsotg, GRXSTSP);
3968 }
3969 }
3970
3971 /* Wait for global nak to take effect */
3972 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3973 GINTSTS_GOUTNAKEFF, 100))
3974 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3975 __func__);
3976 }
3977
3978 /* Disable ep */
3979 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3980
3981 /* Wait for ep to be disabled */
3982 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3983 dev_warn(hsotg->dev,
3984 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3985
3986 /* Clear EPDISBLD interrupt */
3987 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3988
3989 if (hs_ep->dir_in) {
3990 unsigned short fifo_index;
3991
3992 if (hsotg->dedicated_fifos || hs_ep->periodic)
3993 fifo_index = hs_ep->fifo_index;
3994 else
3995 fifo_index = 0;
3996
3997 /* Flush TX FIFO */
3998 dwc2_flush_tx_fifo(hsotg, fifo_index);
3999
4000 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
4001 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
4002 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
4003
4004 } else {
4005 /* Remove global NAKs */
4006 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
4007 }
4008}
4009
4010/**
4011 * dwc2_hsotg_ep_enable - enable the given endpoint
4012 * @ep: The USB endpint to configure
4013 * @desc: The USB endpoint descriptor to configure with.
4014 *
4015 * This is called from the USB gadget code's usb_ep_enable().
4016 */
4017static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
4018 const struct usb_endpoint_descriptor *desc)
4019{
4020 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4021 struct dwc2_hsotg *hsotg = hs_ep->parent;
4022 unsigned long flags;
4023 unsigned int index = hs_ep->index;
4024 u32 epctrl_reg;
4025 u32 epctrl;
4026 u32 mps;
4027 u32 mc;
4028 u32 mask;
4029 unsigned int dir_in;
4030 unsigned int i, val, size;
4031 int ret = 0;
4032 unsigned char ep_type;
4033 int desc_num;
4034
4035 dev_dbg(hsotg->dev,
4036 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
4037 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
4038 desc->wMaxPacketSize, desc->bInterval);
4039
4040 /* not to be called for EP0 */
4041 if (index == 0) {
4042 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
4043 return -EINVAL;
4044 }
4045
4046 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
4047 if (dir_in != hs_ep->dir_in) {
4048 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
4049 return -EINVAL;
4050 }
4051
4052 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
4053 mps = usb_endpoint_maxp(desc);
4054 mc = usb_endpoint_maxp_mult(desc);
4055
4056 /* ISOC IN in DDMA supported bInterval up to 10 */
4057 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4058 dir_in && desc->bInterval > 10) {
4059 dev_err(hsotg->dev,
4060 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
4061 return -EINVAL;
4062 }
4063
4064 /* High bandwidth ISOC OUT in DDMA not supported */
4065 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4066 !dir_in && mc > 1) {
4067 dev_err(hsotg->dev,
4068 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
4069 return -EINVAL;
4070 }
4071
4072 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
4073
4074 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4075 epctrl = dwc2_readl(hsotg, epctrl_reg);
4076
4077 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
4078 __func__, epctrl, epctrl_reg);
4079
4080 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
4081 desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
4082 else
4083 desc_num = MAX_DMA_DESC_NUM_GENERIC;
4084
4085 /* Allocate DMA descriptor chain for non-ctrl endpoints */
4086 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
4087 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
4088 desc_num * sizeof(struct dwc2_dma_desc),
4089 &hs_ep->desc_list_dma, GFP_ATOMIC);
4090 if (!hs_ep->desc_list) {
4091 ret = -ENOMEM;
4092 goto error2;
4093 }
4094 }
4095
4096 spin_lock_irqsave(&hsotg->lock, flags);
4097
4098 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
4099 epctrl |= DXEPCTL_MPS(mps);
4100
4101 /*
4102 * mark the endpoint as active, otherwise the core may ignore
4103 * transactions entirely for this endpoint
4104 */
4105 epctrl |= DXEPCTL_USBACTEP;
4106
4107 /* update the endpoint state */
4108 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
4109
4110 /* default, set to non-periodic */
4111 hs_ep->isochronous = 0;
4112 hs_ep->periodic = 0;
4113 hs_ep->halted = 0;
4114 hs_ep->wedged = 0;
4115 hs_ep->interval = desc->bInterval;
4116
4117 switch (ep_type) {
4118 case USB_ENDPOINT_XFER_ISOC:
4119 epctrl |= DXEPCTL_EPTYPE_ISO;
4120 epctrl |= DXEPCTL_SETEVENFR;
4121 hs_ep->isochronous = 1;
4122 hs_ep->interval = 1 << (desc->bInterval - 1);
4123 hs_ep->target_frame = TARGET_FRAME_INITIAL;
4124 hs_ep->next_desc = 0;
4125 hs_ep->compl_desc = 0;
4126 if (dir_in) {
4127 hs_ep->periodic = 1;
4128 mask = dwc2_readl(hsotg, DIEPMSK);
4129 mask |= DIEPMSK_NAKMSK;
4130 dwc2_writel(hsotg, mask, DIEPMSK);
4131 } else {
4132 epctrl |= DXEPCTL_SNAK;
4133 mask = dwc2_readl(hsotg, DOEPMSK);
4134 mask |= DOEPMSK_OUTTKNEPDISMSK;
4135 dwc2_writel(hsotg, mask, DOEPMSK);
4136 }
4137 break;
4138
4139 case USB_ENDPOINT_XFER_BULK:
4140 epctrl |= DXEPCTL_EPTYPE_BULK;
4141 break;
4142
4143 case USB_ENDPOINT_XFER_INT:
4144 if (dir_in)
4145 hs_ep->periodic = 1;
4146
4147 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4148 hs_ep->interval = 1 << (desc->bInterval - 1);
4149
4150 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
4151 break;
4152
4153 case USB_ENDPOINT_XFER_CONTROL:
4154 epctrl |= DXEPCTL_EPTYPE_CONTROL;
4155 break;
4156 }
4157
4158 /*
4159 * if the hardware has dedicated fifos, we must give each IN EP
4160 * a unique tx-fifo even if it is non-periodic.
4161 */
4162 if (dir_in && hsotg->dedicated_fifos) {
4163 unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
4164 u32 fifo_index = 0;
4165 u32 fifo_size = UINT_MAX;
4166
4167 size = hs_ep->ep.maxpacket * hs_ep->mc;
4168 for (i = 1; i <= fifo_count; ++i) {
4169 if (hsotg->fifo_map & (1 << i))
4170 continue;
4171 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4172 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
4173 if (val < size)
4174 continue;
4175 /* Search for smallest acceptable fifo */
4176 if (val < fifo_size) {
4177 fifo_size = val;
4178 fifo_index = i;
4179 }
4180 }
4181 if (!fifo_index) {
4182 dev_err(hsotg->dev,
4183 "%s: No suitable fifo found\n", __func__);
4184 ret = -ENOMEM;
4185 goto error1;
4186 }
4187 epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
4188 hsotg->fifo_map |= 1 << fifo_index;
4189 epctrl |= DXEPCTL_TXFNUM(fifo_index);
4190 hs_ep->fifo_index = fifo_index;
4191 hs_ep->fifo_size = fifo_size;
4192 }
4193
4194 /* for non control endpoints, set PID to D0 */
4195 if (index && !hs_ep->isochronous)
4196 epctrl |= DXEPCTL_SETD0PID;
4197
4198 /* WA for Full speed ISOC IN in DDMA mode.
4199 * By Clear NAK status of EP, core will send ZLP
4200 * to IN token and assert NAK interrupt relying
4201 * on TxFIFO status only
4202 */
4203
4204 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4205 hs_ep->isochronous && dir_in) {
4206 /* The WA applies only to core versions from 2.72a
4207 * to 4.00a (including both). Also for FS_IOT_1.00a
4208 * and HS_IOT_1.00a.
4209 */
4210 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4211
4212 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
4213 gsnpsid <= DWC2_CORE_REV_4_00a) ||
4214 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
4215 gsnpsid == DWC2_HS_IOT_REV_1_00a)
4216 epctrl |= DXEPCTL_CNAK;
4217 }
4218
4219 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4220 __func__, epctrl);
4221
4222 dwc2_writel(hsotg, epctrl, epctrl_reg);
4223 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4224 __func__, dwc2_readl(hsotg, epctrl_reg));
4225
4226 /* enable the endpoint interrupt */
4227 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4228
4229error1:
4230 spin_unlock_irqrestore(&hsotg->lock, flags);
4231
4232error2:
4233 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4234 dmam_free_coherent(hsotg->dev, desc_num *
4235 sizeof(struct dwc2_dma_desc),
4236 hs_ep->desc_list, hs_ep->desc_list_dma);
4237 hs_ep->desc_list = NULL;
4238 }
4239
4240 return ret;
4241}
4242
4243/**
4244 * dwc2_hsotg_ep_disable - disable given endpoint
4245 * @ep: The endpoint to disable.
4246 */
4247static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4248{
4249 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4250 struct dwc2_hsotg *hsotg = hs_ep->parent;
4251 int dir_in = hs_ep->dir_in;
4252 int index = hs_ep->index;
4253 u32 epctrl_reg;
4254 u32 ctrl;
4255
4256 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4257
4258 if (ep == &hsotg->eps_out[0]->ep) {
4259 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4260 return -EINVAL;
4261 }
4262
4263 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4264 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4265 return -EINVAL;
4266 }
4267
4268 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4269
4270 ctrl = dwc2_readl(hsotg, epctrl_reg);
4271
4272 if (ctrl & DXEPCTL_EPENA)
4273 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4274
4275 ctrl &= ~DXEPCTL_EPENA;
4276 ctrl &= ~DXEPCTL_USBACTEP;
4277 ctrl |= DXEPCTL_SNAK;
4278
4279 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4280 dwc2_writel(hsotg, ctrl, epctrl_reg);
4281
4282 /* disable endpoint interrupts */
4283 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4284
4285 /* terminate all requests with shutdown */
4286 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4287
4288 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4289 hs_ep->fifo_index = 0;
4290 hs_ep->fifo_size = 0;
4291
4292 return 0;
4293}
4294
4295static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
4296{
4297 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4298 struct dwc2_hsotg *hsotg = hs_ep->parent;
4299 unsigned long flags;
4300 int ret;
4301
4302 spin_lock_irqsave(&hsotg->lock, flags);
4303 ret = dwc2_hsotg_ep_disable(ep);
4304 spin_unlock_irqrestore(&hsotg->lock, flags);
4305 return ret;
4306}
4307
4308/**
4309 * on_list - check request is on the given endpoint
4310 * @ep: The endpoint to check.
4311 * @test: The request to test if it is on the endpoint.
4312 */
4313static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4314{
4315 struct dwc2_hsotg_req *req, *treq;
4316
4317 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4318 if (req == test)
4319 return true;
4320 }
4321
4322 return false;
4323}
4324
4325/**
4326 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4327 * @ep: The endpoint to dequeue.
4328 * @req: The request to be removed from a queue.
4329 */
4330static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4331{
4332 struct dwc2_hsotg_req *hs_req = our_req(req);
4333 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4334 struct dwc2_hsotg *hs = hs_ep->parent;
4335 unsigned long flags;
4336
4337 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4338
4339 spin_lock_irqsave(&hs->lock, flags);
4340
4341 if (!on_list(hs_ep, hs_req)) {
4342 spin_unlock_irqrestore(&hs->lock, flags);
4343 return -EINVAL;
4344 }
4345
4346 /* Dequeue already started request */
4347 if (req == &hs_ep->req->req)
4348 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4349
4350 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4351 spin_unlock_irqrestore(&hs->lock, flags);
4352
4353 return 0;
4354}
4355
4356/**
4357 * dwc2_gadget_ep_set_wedge - set wedge on a given endpoint
4358 * @ep: The endpoint to be wedged.
4359 *
4360 */
4361static int dwc2_gadget_ep_set_wedge(struct usb_ep *ep)
4362{
4363 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4364 struct dwc2_hsotg *hs = hs_ep->parent;
4365
4366 unsigned long flags;
4367 int ret;
4368
4369 spin_lock_irqsave(&hs->lock, flags);
4370 hs_ep->wedged = 1;
4371 ret = dwc2_hsotg_ep_sethalt(ep, 1, false);
4372 spin_unlock_irqrestore(&hs->lock, flags);
4373
4374 return ret;
4375}
4376
4377/**
4378 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4379 * @ep: The endpoint to set halt.
4380 * @value: Set or unset the halt.
4381 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4382 * the endpoint is busy processing requests.
4383 *
4384 * We need to stall the endpoint immediately if request comes from set_feature
4385 * protocol command handler.
4386 */
4387static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4388{
4389 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4390 struct dwc2_hsotg *hs = hs_ep->parent;
4391 int index = hs_ep->index;
4392 u32 epreg;
4393 u32 epctl;
4394 u32 xfertype;
4395
4396 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4397
4398 if (index == 0) {
4399 if (value)
4400 dwc2_hsotg_stall_ep0(hs);
4401 else
4402 dev_warn(hs->dev,
4403 "%s: can't clear halt on ep0\n", __func__);
4404 return 0;
4405 }
4406
4407 if (hs_ep->isochronous) {
4408 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4409 return -EINVAL;
4410 }
4411
4412 if (!now && value && !list_empty(&hs_ep->queue)) {
4413 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4414 ep->name);
4415 return -EAGAIN;
4416 }
4417
4418 if (hs_ep->dir_in) {
4419 epreg = DIEPCTL(index);
4420 epctl = dwc2_readl(hs, epreg);
4421
4422 if (value) {
4423 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4424 if (epctl & DXEPCTL_EPENA)
4425 epctl |= DXEPCTL_EPDIS;
4426 } else {
4427 epctl &= ~DXEPCTL_STALL;
4428 hs_ep->wedged = 0;
4429 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4430 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4431 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4432 epctl |= DXEPCTL_SETD0PID;
4433 }
4434 dwc2_writel(hs, epctl, epreg);
4435 } else {
4436 epreg = DOEPCTL(index);
4437 epctl = dwc2_readl(hs, epreg);
4438
4439 if (value) {
4440 /* Unmask GOUTNAKEFF interrupt */
4441 dwc2_hsotg_en_gsint(hs, GINTSTS_GOUTNAKEFF);
4442
4443 if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
4444 dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
4445 // STALL bit will be set in GOUTNAKEFF interrupt handler
4446 } else {
4447 epctl &= ~DXEPCTL_STALL;
4448 hs_ep->wedged = 0;
4449 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4450 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4451 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4452 epctl |= DXEPCTL_SETD0PID;
4453 dwc2_writel(hs, epctl, epreg);
4454 }
4455 }
4456
4457 hs_ep->halted = value;
4458 return 0;
4459}
4460
4461/**
4462 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4463 * @ep: The endpoint to set halt.
4464 * @value: Set or unset the halt.
4465 */
4466static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4467{
4468 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4469 struct dwc2_hsotg *hs = hs_ep->parent;
4470 unsigned long flags;
4471 int ret;
4472
4473 spin_lock_irqsave(&hs->lock, flags);
4474 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4475 spin_unlock_irqrestore(&hs->lock, flags);
4476
4477 return ret;
4478}
4479
4480static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4481 .enable = dwc2_hsotg_ep_enable,
4482 .disable = dwc2_hsotg_ep_disable_lock,
4483 .alloc_request = dwc2_hsotg_ep_alloc_request,
4484 .free_request = dwc2_hsotg_ep_free_request,
4485 .queue = dwc2_hsotg_ep_queue_lock,
4486 .dequeue = dwc2_hsotg_ep_dequeue,
4487 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4488 .set_wedge = dwc2_gadget_ep_set_wedge,
4489 /* note, don't believe we have any call for the fifo routines */
4490};
4491
4492/**
4493 * dwc2_hsotg_init - initialize the usb core
4494 * @hsotg: The driver state
4495 */
4496static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4497{
4498 /* unmask subset of endpoint interrupts */
4499
4500 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4501 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4502 DIEPMSK);
4503
4504 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4505 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4506 DOEPMSK);
4507
4508 dwc2_writel(hsotg, 0, DAINTMSK);
4509
4510 /* Be in disconnected state until gadget is registered */
4511 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4512
4513 /* setup fifos */
4514
4515 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4516 dwc2_readl(hsotg, GRXFSIZ),
4517 dwc2_readl(hsotg, GNPTXFSIZ));
4518
4519 dwc2_hsotg_init_fifo(hsotg);
4520
4521 if (using_dma(hsotg))
4522 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4523}
4524
4525/**
4526 * dwc2_hsotg_udc_start - prepare the udc for work
4527 * @gadget: The usb gadget state
4528 * @driver: The usb gadget driver
4529 *
4530 * Perform initialization to prepare udc device and driver
4531 * to work.
4532 */
4533static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4534 struct usb_gadget_driver *driver)
4535{
4536 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4537 unsigned long flags;
4538 int ret;
4539
4540 if (!hsotg) {
4541 pr_err("%s: called with no device\n", __func__);
4542 return -ENODEV;
4543 }
4544
4545 if (!driver) {
4546 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4547 return -EINVAL;
4548 }
4549
4550 if (driver->max_speed < USB_SPEED_FULL)
4551 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4552
4553 if (!driver->setup) {
4554 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4555 return -EINVAL;
4556 }
4557
4558 WARN_ON(hsotg->driver);
4559
4560 hsotg->driver = driver;
4561 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4562 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4563
4564 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4565 ret = dwc2_lowlevel_hw_enable(hsotg);
4566 if (ret)
4567 goto err;
4568 }
4569
4570 if (!IS_ERR_OR_NULL(hsotg->uphy))
4571 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4572
4573 spin_lock_irqsave(&hsotg->lock, flags);
4574 if (dwc2_hw_is_device(hsotg)) {
4575 dwc2_hsotg_init(hsotg);
4576 dwc2_hsotg_core_init_disconnected(hsotg, false);
4577 }
4578
4579 hsotg->enabled = 0;
4580 spin_unlock_irqrestore(&hsotg->lock, flags);
4581
4582 gadget->sg_supported = using_desc_dma(hsotg);
4583 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4584
4585 return 0;
4586
4587err:
4588 hsotg->driver = NULL;
4589 return ret;
4590}
4591
4592/**
4593 * dwc2_hsotg_udc_stop - stop the udc
4594 * @gadget: The usb gadget state
4595 *
4596 * Stop udc hw block and stay tunned for future transmissions
4597 */
4598static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4599{
4600 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4601 unsigned long flags;
4602 int ep;
4603
4604 if (!hsotg)
4605 return -ENODEV;
4606
4607 /* all endpoints should be shutdown */
4608 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4609 if (hsotg->eps_in[ep])
4610 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4611 if (hsotg->eps_out[ep])
4612 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4613 }
4614
4615 spin_lock_irqsave(&hsotg->lock, flags);
4616
4617 hsotg->driver = NULL;
4618 hsotg->gadget.dev.of_node = NULL;
4619 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4620 hsotg->enabled = 0;
4621
4622 spin_unlock_irqrestore(&hsotg->lock, flags);
4623
4624 if (!IS_ERR_OR_NULL(hsotg->uphy))
4625 otg_set_peripheral(hsotg->uphy->otg, NULL);
4626
4627 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4628 dwc2_lowlevel_hw_disable(hsotg);
4629
4630 return 0;
4631}
4632
4633/**
4634 * dwc2_hsotg_gadget_getframe - read the frame number
4635 * @gadget: The usb gadget state
4636 *
4637 * Read the {micro} frame number
4638 */
4639static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4640{
4641 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4642}
4643
4644/**
4645 * dwc2_hsotg_set_selfpowered - set if device is self/bus powered
4646 * @gadget: The usb gadget state
4647 * @is_selfpowered: Whether the device is self-powered
4648 *
4649 * Set if the device is self or bus powered.
4650 */
4651static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
4652 int is_selfpowered)
4653{
4654 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4655 unsigned long flags;
4656
4657 spin_lock_irqsave(&hsotg->lock, flags);
4658 gadget->is_selfpowered = !!is_selfpowered;
4659 spin_unlock_irqrestore(&hsotg->lock, flags);
4660
4661 return 0;
4662}
4663
4664/**
4665 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4666 * @gadget: The usb gadget state
4667 * @is_on: Current state of the USB PHY
4668 *
4669 * Connect/Disconnect the USB PHY pullup
4670 */
4671static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4672{
4673 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4674 unsigned long flags;
4675
4676 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4677 hsotg->op_state);
4678
4679 /* Don't modify pullup state while in host mode */
4680 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4681 hsotg->enabled = is_on;
4682 return 0;
4683 }
4684
4685 spin_lock_irqsave(&hsotg->lock, flags);
4686 if (is_on) {
4687 hsotg->enabled = 1;
4688 dwc2_hsotg_core_init_disconnected(hsotg, false);
4689 /* Enable ACG feature in device mode,if supported */
4690 dwc2_enable_acg(hsotg);
4691 dwc2_hsotg_core_connect(hsotg);
4692 } else {
4693 dwc2_hsotg_core_disconnect(hsotg);
4694 dwc2_hsotg_disconnect(hsotg);
4695 hsotg->enabled = 0;
4696 }
4697
4698 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4699 spin_unlock_irqrestore(&hsotg->lock, flags);
4700
4701 return 0;
4702}
4703
4704static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4705{
4706 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4707 unsigned long flags;
4708
4709 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4710 spin_lock_irqsave(&hsotg->lock, flags);
4711
4712 /*
4713 * If controller is in partial power down state, it must exit from
4714 * that state before being initialized / de-initialized
4715 */
4716 if (hsotg->lx_state == DWC2_L2 && hsotg->in_ppd)
4717 /*
4718 * No need to check the return value as
4719 * registers are not being restored.
4720 */
4721 dwc2_exit_partial_power_down(hsotg, 0, false);
4722
4723 if (is_active) {
4724 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4725
4726 dwc2_hsotg_core_init_disconnected(hsotg, false);
4727 if (hsotg->enabled) {
4728 /* Enable ACG feature in device mode,if supported */
4729 dwc2_enable_acg(hsotg);
4730 dwc2_hsotg_core_connect(hsotg);
4731 }
4732 } else {
4733 dwc2_hsotg_core_disconnect(hsotg);
4734 dwc2_hsotg_disconnect(hsotg);
4735 }
4736
4737 spin_unlock_irqrestore(&hsotg->lock, flags);
4738 return 0;
4739}
4740
4741/**
4742 * dwc2_hsotg_vbus_draw - report bMaxPower field
4743 * @gadget: The usb gadget state
4744 * @mA: Amount of current
4745 *
4746 * Report how much power the device may consume to the phy.
4747 */
4748static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4749{
4750 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4751
4752 if (IS_ERR_OR_NULL(hsotg->uphy))
4753 return -ENOTSUPP;
4754 return usb_phy_set_power(hsotg->uphy, mA);
4755}
4756
4757static void dwc2_gadget_set_speed(struct usb_gadget *g, enum usb_device_speed speed)
4758{
4759 struct dwc2_hsotg *hsotg = to_hsotg(g);
4760 unsigned long flags;
4761
4762 spin_lock_irqsave(&hsotg->lock, flags);
4763 switch (speed) {
4764 case USB_SPEED_HIGH:
4765 hsotg->params.speed = DWC2_SPEED_PARAM_HIGH;
4766 break;
4767 case USB_SPEED_FULL:
4768 hsotg->params.speed = DWC2_SPEED_PARAM_FULL;
4769 break;
4770 case USB_SPEED_LOW:
4771 hsotg->params.speed = DWC2_SPEED_PARAM_LOW;
4772 break;
4773 default:
4774 dev_err(hsotg->dev, "invalid speed (%d)\n", speed);
4775 }
4776 spin_unlock_irqrestore(&hsotg->lock, flags);
4777}
4778
4779static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4780 .get_frame = dwc2_hsotg_gadget_getframe,
4781 .set_selfpowered = dwc2_hsotg_set_selfpowered,
4782 .udc_start = dwc2_hsotg_udc_start,
4783 .udc_stop = dwc2_hsotg_udc_stop,
4784 .pullup = dwc2_hsotg_pullup,
4785 .udc_set_speed = dwc2_gadget_set_speed,
4786 .vbus_session = dwc2_hsotg_vbus_session,
4787 .vbus_draw = dwc2_hsotg_vbus_draw,
4788};
4789
4790/**
4791 * dwc2_hsotg_initep - initialise a single endpoint
4792 * @hsotg: The device state.
4793 * @hs_ep: The endpoint to be initialised.
4794 * @epnum: The endpoint number
4795 * @dir_in: True if direction is in.
4796 *
4797 * Initialise the given endpoint (as part of the probe and device state
4798 * creation) to give to the gadget driver. Setup the endpoint name, any
4799 * direction information and other state that may be required.
4800 */
4801static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4802 struct dwc2_hsotg_ep *hs_ep,
4803 int epnum,
4804 bool dir_in)
4805{
4806 char *dir;
4807
4808 if (epnum == 0)
4809 dir = "";
4810 else if (dir_in)
4811 dir = "in";
4812 else
4813 dir = "out";
4814
4815 hs_ep->dir_in = dir_in;
4816 hs_ep->index = epnum;
4817
4818 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4819
4820 INIT_LIST_HEAD(&hs_ep->queue);
4821 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4822
4823 /* add to the list of endpoints known by the gadget driver */
4824 if (epnum)
4825 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4826
4827 hs_ep->parent = hsotg;
4828 hs_ep->ep.name = hs_ep->name;
4829
4830 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4831 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4832 else
4833 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4834 epnum ? 1024 : EP0_MPS_LIMIT);
4835 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4836
4837 if (epnum == 0) {
4838 hs_ep->ep.caps.type_control = true;
4839 } else {
4840 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4841 hs_ep->ep.caps.type_iso = true;
4842 hs_ep->ep.caps.type_bulk = true;
4843 }
4844 hs_ep->ep.caps.type_int = true;
4845 }
4846
4847 if (dir_in)
4848 hs_ep->ep.caps.dir_in = true;
4849 else
4850 hs_ep->ep.caps.dir_out = true;
4851
4852 /*
4853 * if we're using dma, we need to set the next-endpoint pointer
4854 * to be something valid.
4855 */
4856
4857 if (using_dma(hsotg)) {
4858 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4859
4860 if (dir_in)
4861 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4862 else
4863 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4864 }
4865}
4866
4867/**
4868 * dwc2_hsotg_hw_cfg - read HW configuration registers
4869 * @hsotg: Programming view of the DWC_otg controller
4870 *
4871 * Read the USB core HW configuration registers
4872 */
4873static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4874{
4875 u32 cfg;
4876 u32 ep_type;
4877 u32 i;
4878
4879 /* check hardware configuration */
4880
4881 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4882
4883 /* Add ep0 */
4884 hsotg->num_of_eps++;
4885
4886 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4887 sizeof(struct dwc2_hsotg_ep),
4888 GFP_KERNEL);
4889 if (!hsotg->eps_in[0])
4890 return -ENOMEM;
4891 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4892 hsotg->eps_out[0] = hsotg->eps_in[0];
4893
4894 cfg = hsotg->hw_params.dev_ep_dirs;
4895 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4896 ep_type = cfg & 3;
4897 /* Direction in or both */
4898 if (!(ep_type & 2)) {
4899 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4900 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4901 if (!hsotg->eps_in[i])
4902 return -ENOMEM;
4903 }
4904 /* Direction out or both */
4905 if (!(ep_type & 1)) {
4906 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4907 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4908 if (!hsotg->eps_out[i])
4909 return -ENOMEM;
4910 }
4911 }
4912
4913 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4914 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4915
4916 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4917 hsotg->num_of_eps,
4918 hsotg->dedicated_fifos ? "dedicated" : "shared",
4919 hsotg->fifo_mem);
4920 return 0;
4921}
4922
4923/**
4924 * dwc2_hsotg_dump - dump state of the udc
4925 * @hsotg: Programming view of the DWC_otg controller
4926 *
4927 */
4928static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4929{
4930#ifdef DEBUG
4931 struct device *dev = hsotg->dev;
4932 u32 val;
4933 int idx;
4934
4935 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4936 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4937 dwc2_readl(hsotg, DIEPMSK));
4938
4939 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4940 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4941
4942 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4943 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4944
4945 /* show periodic fifo settings */
4946
4947 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4948 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4949 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4950 val >> FIFOSIZE_DEPTH_SHIFT,
4951 val & FIFOSIZE_STARTADDR_MASK);
4952 }
4953
4954 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4955 dev_info(dev,
4956 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4957 dwc2_readl(hsotg, DIEPCTL(idx)),
4958 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4959 dwc2_readl(hsotg, DIEPDMA(idx)));
4960
4961 val = dwc2_readl(hsotg, DOEPCTL(idx));
4962 dev_info(dev,
4963 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4964 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4965 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4966 dwc2_readl(hsotg, DOEPDMA(idx)));
4967 }
4968
4969 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4970 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4971#endif
4972}
4973
4974/**
4975 * dwc2_gadget_init - init function for gadget
4976 * @hsotg: Programming view of the DWC_otg controller
4977 *
4978 */
4979int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4980{
4981 struct device *dev = hsotg->dev;
4982 int epnum;
4983 int ret;
4984
4985 /* Dump fifo information */
4986 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4987 hsotg->params.g_np_tx_fifo_size);
4988 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4989
4990 switch (hsotg->params.speed) {
4991 case DWC2_SPEED_PARAM_LOW:
4992 hsotg->gadget.max_speed = USB_SPEED_LOW;
4993 break;
4994 case DWC2_SPEED_PARAM_FULL:
4995 hsotg->gadget.max_speed = USB_SPEED_FULL;
4996 break;
4997 default:
4998 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4999 break;
5000 }
5001
5002 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
5003 hsotg->gadget.name = dev_name(dev);
5004 hsotg->gadget.otg_caps = &hsotg->params.otg_caps;
5005 hsotg->remote_wakeup_allowed = 0;
5006
5007 if (hsotg->params.lpm)
5008 hsotg->gadget.lpm_capable = true;
5009
5010 if (hsotg->dr_mode == USB_DR_MODE_OTG)
5011 hsotg->gadget.is_otg = 1;
5012 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
5013 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
5014
5015 ret = dwc2_hsotg_hw_cfg(hsotg);
5016 if (ret) {
5017 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
5018 return ret;
5019 }
5020
5021 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
5022 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
5023 if (!hsotg->ctrl_buff)
5024 return -ENOMEM;
5025
5026 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
5027 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
5028 if (!hsotg->ep0_buff)
5029 return -ENOMEM;
5030
5031 if (using_desc_dma(hsotg)) {
5032 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
5033 if (ret < 0)
5034 return ret;
5035 }
5036
5037 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
5038 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
5039 if (ret < 0) {
5040 dev_err(dev, "cannot claim IRQ for gadget\n");
5041 return ret;
5042 }
5043
5044 /* hsotg->num_of_eps holds number of EPs other than ep0 */
5045
5046 if (hsotg->num_of_eps == 0) {
5047 dev_err(dev, "wrong number of EPs (zero)\n");
5048 return -EINVAL;
5049 }
5050
5051 /* setup endpoint information */
5052
5053 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
5054 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
5055
5056 /* allocate EP0 request */
5057
5058 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
5059 GFP_KERNEL);
5060 if (!hsotg->ctrl_req) {
5061 dev_err(dev, "failed to allocate ctrl req\n");
5062 return -ENOMEM;
5063 }
5064
5065 /* initialise the endpoints now the core has been initialised */
5066 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
5067 if (hsotg->eps_in[epnum])
5068 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
5069 epnum, 1);
5070 if (hsotg->eps_out[epnum])
5071 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
5072 epnum, 0);
5073 }
5074
5075 dwc2_hsotg_dump(hsotg);
5076
5077 return 0;
5078}
5079
5080/**
5081 * dwc2_hsotg_remove - remove function for hsotg driver
5082 * @hsotg: Programming view of the DWC_otg controller
5083 *
5084 */
5085int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
5086{
5087 usb_del_gadget_udc(&hsotg->gadget);
5088 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
5089
5090 return 0;
5091}
5092
5093int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
5094{
5095 unsigned long flags;
5096
5097 if (hsotg->lx_state != DWC2_L0)
5098 return 0;
5099
5100 if (hsotg->driver) {
5101 int ep;
5102
5103 dev_info(hsotg->dev, "suspending usb gadget %s\n",
5104 hsotg->driver->driver.name);
5105
5106 spin_lock_irqsave(&hsotg->lock, flags);
5107 if (hsotg->enabled)
5108 dwc2_hsotg_core_disconnect(hsotg);
5109 dwc2_hsotg_disconnect(hsotg);
5110 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
5111 spin_unlock_irqrestore(&hsotg->lock, flags);
5112
5113 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
5114 if (hsotg->eps_in[ep])
5115 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
5116 if (hsotg->eps_out[ep])
5117 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
5118 }
5119 }
5120
5121 return 0;
5122}
5123
5124int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
5125{
5126 unsigned long flags;
5127
5128 if (hsotg->lx_state == DWC2_L2)
5129 return 0;
5130
5131 if (hsotg->driver) {
5132 dev_info(hsotg->dev, "resuming usb gadget %s\n",
5133 hsotg->driver->driver.name);
5134
5135 spin_lock_irqsave(&hsotg->lock, flags);
5136 dwc2_hsotg_core_init_disconnected(hsotg, false);
5137 if (hsotg->enabled) {
5138 /* Enable ACG feature in device mode,if supported */
5139 dwc2_enable_acg(hsotg);
5140 dwc2_hsotg_core_connect(hsotg);
5141 }
5142 spin_unlock_irqrestore(&hsotg->lock, flags);
5143 }
5144
5145 return 0;
5146}
5147
5148/**
5149 * dwc2_backup_device_registers() - Backup controller device registers.
5150 * When suspending usb bus, registers needs to be backuped
5151 * if controller power is disabled once suspended.
5152 *
5153 * @hsotg: Programming view of the DWC_otg controller
5154 */
5155int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
5156{
5157 struct dwc2_dregs_backup *dr;
5158 int i;
5159
5160 dev_dbg(hsotg->dev, "%s\n", __func__);
5161
5162 /* Backup dev regs */
5163 dr = &hsotg->dr_backup;
5164
5165 dr->dcfg = dwc2_readl(hsotg, DCFG);
5166 dr->dctl = dwc2_readl(hsotg, DCTL);
5167 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
5168 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
5169 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
5170
5171 for (i = 0; i < hsotg->num_of_eps; i++) {
5172 /* Backup IN EPs */
5173 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
5174
5175 /* Ensure DATA PID is correctly configured */
5176 if (dr->diepctl[i] & DXEPCTL_DPID)
5177 dr->diepctl[i] |= DXEPCTL_SETD1PID;
5178 else
5179 dr->diepctl[i] |= DXEPCTL_SETD0PID;
5180
5181 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
5182 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
5183
5184 /* Backup OUT EPs */
5185 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
5186
5187 /* Ensure DATA PID is correctly configured */
5188 if (dr->doepctl[i] & DXEPCTL_DPID)
5189 dr->doepctl[i] |= DXEPCTL_SETD1PID;
5190 else
5191 dr->doepctl[i] |= DXEPCTL_SETD0PID;
5192
5193 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
5194 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
5195 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5196 }
5197 dr->valid = true;
5198 return 0;
5199}
5200
5201/**
5202 * dwc2_restore_device_registers() - Restore controller device registers.
5203 * When resuming usb bus, device registers needs to be restored
5204 * if controller power were disabled.
5205 *
5206 * @hsotg: Programming view of the DWC_otg controller
5207 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
5208 *
5209 * Return: 0 if successful, negative error code otherwise
5210 */
5211int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5212{
5213 struct dwc2_dregs_backup *dr;
5214 int i;
5215
5216 dev_dbg(hsotg->dev, "%s\n", __func__);
5217
5218 /* Restore dev regs */
5219 dr = &hsotg->dr_backup;
5220 if (!dr->valid) {
5221 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5222 __func__);
5223 return -EINVAL;
5224 }
5225 dr->valid = false;
5226
5227 if (!remote_wakeup)
5228 dwc2_writel(hsotg, dr->dctl, DCTL);
5229
5230 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5231 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5232 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5233
5234 for (i = 0; i < hsotg->num_of_eps; i++) {
5235 /* Restore IN EPs */
5236 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5237 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5238 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5239 /** WA for enabled EPx's IN in DDMA mode. On entering to
5240 * hibernation wrong value read and saved from DIEPDMAx,
5241 * as result BNA interrupt asserted on hibernation exit
5242 * by restoring from saved area.
5243 */
5244 if (using_desc_dma(hsotg) &&
5245 (dr->diepctl[i] & DXEPCTL_EPENA))
5246 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5247 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5248 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5249 /* Restore OUT EPs */
5250 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5251 /* WA for enabled EPx's OUT in DDMA mode. On entering to
5252 * hibernation wrong value read and saved from DOEPDMAx,
5253 * as result BNA interrupt asserted on hibernation exit
5254 * by restoring from saved area.
5255 */
5256 if (using_desc_dma(hsotg) &&
5257 (dr->doepctl[i] & DXEPCTL_EPENA))
5258 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5259 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5260 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5261 }
5262
5263 return 0;
5264}
5265
5266/**
5267 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
5268 *
5269 * @hsotg: Programming view of DWC_otg controller
5270 *
5271 */
5272void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5273{
5274 u32 val;
5275
5276 if (!hsotg->params.lpm)
5277 return;
5278
5279 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
5280 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5281 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5282 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5283 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5284 val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5285 val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
5286 dwc2_writel(hsotg, val, GLPMCFG);
5287 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5288
5289 /* Unmask WKUP_ALERT Interrupt */
5290 if (hsotg->params.service_interval)
5291 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5292}
5293
5294/**
5295 * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
5296 *
5297 * @hsotg: Programming view of DWC_otg controller
5298 *
5299 */
5300void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5301{
5302 u32 val = 0;
5303
5304 val |= GREFCLK_REF_CLK_MODE;
5305 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5306 val |= hsotg->params.sof_cnt_wkup_alert <<
5307 GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5308
5309 dwc2_writel(hsotg, val, GREFCLK);
5310 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5311}
5312
5313/**
5314 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
5315 *
5316 * @hsotg: Programming view of the DWC_otg controller
5317 *
5318 * Return non-zero if failed to enter to hibernation.
5319 */
5320int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5321{
5322 u32 gpwrdn;
5323 u32 gusbcfg;
5324 u32 pcgcctl;
5325 int ret = 0;
5326
5327 /* Change to L2(suspend) state */
5328 hsotg->lx_state = DWC2_L2;
5329 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5330 ret = dwc2_backup_global_registers(hsotg);
5331 if (ret) {
5332 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5333 __func__);
5334 return ret;
5335 }
5336 ret = dwc2_backup_device_registers(hsotg);
5337 if (ret) {
5338 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5339 __func__);
5340 return ret;
5341 }
5342
5343 gpwrdn = GPWRDN_PWRDNRSTN;
5344 udelay(10);
5345 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
5346 if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) {
5347 /* ULPI interface */
5348 gpwrdn |= GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY;
5349 }
5350 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5351 udelay(10);
5352
5353 /* Suspend the Phy Clock */
5354 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5355 pcgcctl |= PCGCTL_STOPPCLK;
5356 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5357 udelay(10);
5358
5359 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5360 gpwrdn |= GPWRDN_PMUACTV;
5361 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5362 udelay(10);
5363
5364 /* Set flag to indicate that we are in hibernation */
5365 hsotg->hibernated = 1;
5366
5367 /* Enable interrupts from wake up logic */
5368 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5369 gpwrdn |= GPWRDN_PMUINTSEL;
5370 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5371 udelay(10);
5372
5373 /* Unmask device mode interrupts in GPWRDN */
5374 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5375 gpwrdn |= GPWRDN_RST_DET_MSK;
5376 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5377 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5378 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5379 udelay(10);
5380
5381 /* Enable Power Down Clamp */
5382 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5383 gpwrdn |= GPWRDN_PWRDNCLMP;
5384 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5385 udelay(10);
5386
5387 /* Switch off VDD */
5388 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5389 gpwrdn |= GPWRDN_PWRDNSWTCH;
5390 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5391 udelay(10);
5392
5393 /* Save gpwrdn register for further usage if stschng interrupt */
5394 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5395 dev_dbg(hsotg->dev, "Hibernation completed\n");
5396
5397 return ret;
5398}
5399
5400/**
5401 * dwc2_gadget_exit_hibernation()
5402 * This function is for exiting from Device mode hibernation by host initiated
5403 * resume/reset and device initiated remote-wakeup.
5404 *
5405 * @hsotg: Programming view of the DWC_otg controller
5406 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5407 * @reset: indicates whether resume is initiated by Reset.
5408 *
5409 * Return non-zero if failed to exit from hibernation.
5410 */
5411int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5412 int rem_wakeup, int reset)
5413{
5414 u32 pcgcctl;
5415 u32 gpwrdn;
5416 u32 dctl;
5417 int ret = 0;
5418 struct dwc2_gregs_backup *gr;
5419 struct dwc2_dregs_backup *dr;
5420
5421 gr = &hsotg->gr_backup;
5422 dr = &hsotg->dr_backup;
5423
5424 if (!hsotg->hibernated) {
5425 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5426 return 1;
5427 }
5428 dev_dbg(hsotg->dev,
5429 "%s: called with rem_wakeup = %d reset = %d\n",
5430 __func__, rem_wakeup, reset);
5431
5432 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5433
5434 if (!reset) {
5435 /* Clear all pending interupts */
5436 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5437 }
5438
5439 /* De-assert Restore */
5440 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5441 gpwrdn &= ~GPWRDN_RESTORE;
5442 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5443 udelay(10);
5444
5445 if (!rem_wakeup) {
5446 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5447 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5448 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5449 }
5450
5451 /* Restore GUSBCFG, DCFG and DCTL */
5452 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5453 dwc2_writel(hsotg, dr->dcfg, DCFG);
5454 dwc2_writel(hsotg, dr->dctl, DCTL);
5455
5456 /* On USB Reset, reset device address to zero */
5457 if (reset)
5458 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
5459
5460 /* Reset ULPI latch */
5461 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5462 gpwrdn &= ~GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY;
5463 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5464
5465 /* De-assert Wakeup Logic */
5466 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5467 gpwrdn &= ~GPWRDN_PMUACTV;
5468 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5469
5470 if (rem_wakeup) {
5471 udelay(10);
5472 /* Start Remote Wakeup Signaling */
5473 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5474 } else {
5475 udelay(50);
5476 /* Set Device programming done bit */
5477 dctl = dwc2_readl(hsotg, DCTL);
5478 dctl |= DCTL_PWRONPRGDONE;
5479 dwc2_writel(hsotg, dctl, DCTL);
5480 }
5481 /* Wait for interrupts which must be cleared */
5482 mdelay(2);
5483 /* Clear all pending interupts */
5484 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5485
5486 /* Restore global registers */
5487 ret = dwc2_restore_global_registers(hsotg);
5488 if (ret) {
5489 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5490 __func__);
5491 return ret;
5492 }
5493
5494 /* Restore device registers */
5495 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5496 if (ret) {
5497 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5498 __func__);
5499 return ret;
5500 }
5501
5502 if (rem_wakeup) {
5503 mdelay(10);
5504 dctl = dwc2_readl(hsotg, DCTL);
5505 dctl &= ~DCTL_RMTWKUPSIG;
5506 dwc2_writel(hsotg, dctl, DCTL);
5507 }
5508
5509 hsotg->hibernated = 0;
5510 hsotg->lx_state = DWC2_L0;
5511 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
5512
5513 return ret;
5514}
5515
5516/**
5517 * dwc2_gadget_enter_partial_power_down() - Put controller in partial
5518 * power down.
5519 *
5520 * @hsotg: Programming view of the DWC_otg controller
5521 *
5522 * Return: non-zero if failed to enter device partial power down.
5523 *
5524 * This function is for entering device mode partial power down.
5525 */
5526int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
5527{
5528 u32 pcgcctl;
5529 int ret = 0;
5530
5531 dev_dbg(hsotg->dev, "Entering device partial power down started.\n");
5532
5533 /* Backup all registers */
5534 ret = dwc2_backup_global_registers(hsotg);
5535 if (ret) {
5536 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5537 __func__);
5538 return ret;
5539 }
5540
5541 ret = dwc2_backup_device_registers(hsotg);
5542 if (ret) {
5543 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5544 __func__);
5545 return ret;
5546 }
5547
5548 /*
5549 * Clear any pending interrupts since dwc2 will not be able to
5550 * clear them after entering partial_power_down.
5551 */
5552 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5553
5554 /* Put the controller in low power state */
5555 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5556
5557 pcgcctl |= PCGCTL_PWRCLMP;
5558 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5559 udelay(5);
5560
5561 pcgcctl |= PCGCTL_RSTPDWNMODULE;
5562 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5563 udelay(5);
5564
5565 pcgcctl |= PCGCTL_STOPPCLK;
5566 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5567
5568 /* Set in_ppd flag to 1 as here core enters suspend. */
5569 hsotg->in_ppd = 1;
5570 hsotg->lx_state = DWC2_L2;
5571
5572 dev_dbg(hsotg->dev, "Entering device partial power down completed.\n");
5573
5574 return ret;
5575}
5576
5577/*
5578 * dwc2_gadget_exit_partial_power_down() - Exit controller from device partial
5579 * power down.
5580 *
5581 * @hsotg: Programming view of the DWC_otg controller
5582 * @restore: indicates whether need to restore the registers or not.
5583 *
5584 * Return: non-zero if failed to exit device partial power down.
5585 *
5586 * This function is for exiting from device mode partial power down.
5587 */
5588int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
5589 bool restore)
5590{
5591 u32 pcgcctl;
5592 u32 dctl;
5593 struct dwc2_dregs_backup *dr;
5594 int ret = 0;
5595
5596 dr = &hsotg->dr_backup;
5597
5598 dev_dbg(hsotg->dev, "Exiting device partial Power Down started.\n");
5599
5600 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5601 pcgcctl &= ~PCGCTL_STOPPCLK;
5602 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5603
5604 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5605 pcgcctl &= ~PCGCTL_PWRCLMP;
5606 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5607
5608 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5609 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5610 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5611
5612 udelay(100);
5613 if (restore) {
5614 ret = dwc2_restore_global_registers(hsotg);
5615 if (ret) {
5616 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5617 __func__);
5618 return ret;
5619 }
5620 /* Restore DCFG */
5621 dwc2_writel(hsotg, dr->dcfg, DCFG);
5622
5623 ret = dwc2_restore_device_registers(hsotg, 0);
5624 if (ret) {
5625 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5626 __func__);
5627 return ret;
5628 }
5629 }
5630
5631 /* Set the Power-On Programming done bit */
5632 dctl = dwc2_readl(hsotg, DCTL);
5633 dctl |= DCTL_PWRONPRGDONE;
5634 dwc2_writel(hsotg, dctl, DCTL);
5635
5636 /* Set in_ppd flag to 0 as here core exits from suspend. */
5637 hsotg->in_ppd = 0;
5638 hsotg->lx_state = DWC2_L0;
5639
5640 dev_dbg(hsotg->dev, "Exiting device partial Power Down completed.\n");
5641 return ret;
5642}
5643
5644/**
5645 * dwc2_gadget_enter_clock_gating() - Put controller in clock gating.
5646 *
5647 * @hsotg: Programming view of the DWC_otg controller
5648 *
5649 * Return: non-zero if failed to enter device partial power down.
5650 *
5651 * This function is for entering device mode clock gating.
5652 */
5653void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg)
5654{
5655 u32 pcgctl;
5656
5657 dev_dbg(hsotg->dev, "Entering device clock gating.\n");
5658
5659 /* Set the Phy Clock bit as suspend is received. */
5660 pcgctl = dwc2_readl(hsotg, PCGCTL);
5661 pcgctl |= PCGCTL_STOPPCLK;
5662 dwc2_writel(hsotg, pcgctl, PCGCTL);
5663 udelay(5);
5664
5665 /* Set the Gate hclk as suspend is received. */
5666 pcgctl = dwc2_readl(hsotg, PCGCTL);
5667 pcgctl |= PCGCTL_GATEHCLK;
5668 dwc2_writel(hsotg, pcgctl, PCGCTL);
5669 udelay(5);
5670
5671 hsotg->lx_state = DWC2_L2;
5672 hsotg->bus_suspended = true;
5673}
5674
5675/*
5676 * dwc2_gadget_exit_clock_gating() - Exit controller from device clock gating.
5677 *
5678 * @hsotg: Programming view of the DWC_otg controller
5679 * @rem_wakeup: indicates whether remote wake up is enabled.
5680 *
5681 * This function is for exiting from device mode clock gating.
5682 */
5683void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup)
5684{
5685 u32 pcgctl;
5686 u32 dctl;
5687
5688 dev_dbg(hsotg->dev, "Exiting device clock gating.\n");
5689
5690 /* Clear the Gate hclk. */
5691 pcgctl = dwc2_readl(hsotg, PCGCTL);
5692 pcgctl &= ~PCGCTL_GATEHCLK;
5693 dwc2_writel(hsotg, pcgctl, PCGCTL);
5694 udelay(5);
5695
5696 /* Phy Clock bit. */
5697 pcgctl = dwc2_readl(hsotg, PCGCTL);
5698 pcgctl &= ~PCGCTL_STOPPCLK;
5699 dwc2_writel(hsotg, pcgctl, PCGCTL);
5700 udelay(5);
5701
5702 if (rem_wakeup) {
5703 /* Set Remote Wakeup Signaling */
5704 dctl = dwc2_readl(hsotg, DCTL);
5705 dctl |= DCTL_RMTWKUPSIG;
5706 dwc2_writel(hsotg, dctl, DCTL);
5707 }
5708
5709 /* Change to L0 state */
5710 call_gadget(hsotg, resume);
5711 hsotg->lx_state = DWC2_L0;
5712 hsotg->bus_suspended = false;
5713}