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1/**
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * S3C USB2.0 High-speed / OtG driver
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/spinlock.h>
20#include <linux/interrupt.h>
21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h>
23#include <linux/mutex.h>
24#include <linux/seq_file.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/slab.h>
28#include <linux/of_platform.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32#include <linux/usb/phy.h>
33
34#include "core.h"
35#include "hw.h"
36
37/* conversion functions */
38static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
39{
40 return container_of(req, struct dwc2_hsotg_req, req);
41}
42
43static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
44{
45 return container_of(ep, struct dwc2_hsotg_ep, ep);
46}
47
48static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
49{
50 return container_of(gadget, struct dwc2_hsotg, gadget);
51}
52
53static inline void __orr32(void __iomem *ptr, u32 val)
54{
55 dwc2_writel(dwc2_readl(ptr) | val, ptr);
56}
57
58static inline void __bic32(void __iomem *ptr, u32 val)
59{
60 dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
61}
62
63static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
64 u32 ep_index, u32 dir_in)
65{
66 if (dir_in)
67 return hsotg->eps_in[ep_index];
68 else
69 return hsotg->eps_out[ep_index];
70}
71
72/* forward declaration of functions */
73static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
74
75/**
76 * using_dma - return the DMA status of the driver.
77 * @hsotg: The driver state.
78 *
79 * Return true if we're using DMA.
80 *
81 * Currently, we have the DMA support code worked into everywhere
82 * that needs it, but the AMBA DMA implementation in the hardware can
83 * only DMA from 32bit aligned addresses. This means that gadgets such
84 * as the CDC Ethernet cannot work as they often pass packets which are
85 * not 32bit aligned.
86 *
87 * Unfortunately the choice to use DMA or not is global to the controller
88 * and seems to be only settable when the controller is being put through
89 * a core reset. This means we either need to fix the gadgets to take
90 * account of DMA alignment, or add bounce buffers (yuerk).
91 *
92 * g_using_dma is set depending on dts flag.
93 */
94static inline bool using_dma(struct dwc2_hsotg *hsotg)
95{
96 return hsotg->g_using_dma;
97}
98
99/**
100 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
101 * @hsotg: The device state
102 * @ints: A bitmask of the interrupts to enable
103 */
104static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
105{
106 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
107 u32 new_gsintmsk;
108
109 new_gsintmsk = gsintmsk | ints;
110
111 if (new_gsintmsk != gsintmsk) {
112 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
113 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
114 }
115}
116
117/**
118 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
119 * @hsotg: The device state
120 * @ints: A bitmask of the interrupts to enable
121 */
122static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
123{
124 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
125 u32 new_gsintmsk;
126
127 new_gsintmsk = gsintmsk & ~ints;
128
129 if (new_gsintmsk != gsintmsk)
130 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
131}
132
133/**
134 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
135 * @hsotg: The device state
136 * @ep: The endpoint index
137 * @dir_in: True if direction is in.
138 * @en: The enable value, true to enable
139 *
140 * Set or clear the mask for an individual endpoint's interrupt
141 * request.
142 */
143static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
144 unsigned int ep, unsigned int dir_in,
145 unsigned int en)
146{
147 unsigned long flags;
148 u32 bit = 1 << ep;
149 u32 daint;
150
151 if (!dir_in)
152 bit <<= 16;
153
154 local_irq_save(flags);
155 daint = dwc2_readl(hsotg->regs + DAINTMSK);
156 if (en)
157 daint |= bit;
158 else
159 daint &= ~bit;
160 dwc2_writel(daint, hsotg->regs + DAINTMSK);
161 local_irq_restore(flags);
162}
163
164/**
165 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
166 * @hsotg: The device instance.
167 */
168static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
169{
170 unsigned int ep;
171 unsigned int addr;
172 int timeout;
173 u32 val;
174
175 /* Reset fifo map if not correctly cleared during previous session */
176 WARN_ON(hsotg->fifo_map);
177 hsotg->fifo_map = 0;
178
179 /* set RX/NPTX FIFO sizes */
180 dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ);
181 dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) |
182 (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT),
183 hsotg->regs + GNPTXFSIZ);
184
185 /*
186 * arange all the rest of the TX FIFOs, as some versions of this
187 * block have overlapping default addresses. This also ensures
188 * that if the settings have been changed, then they are set to
189 * known values.
190 */
191
192 /* start at the end of the GNPTXFSIZ, rounded up */
193 addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz;
194
195 /*
196 * Configure fifos sizes from provided configuration and assign
197 * them to endpoints dynamically according to maxpacket size value of
198 * given endpoint.
199 */
200 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
201 if (!hsotg->g_tx_fifo_sz[ep])
202 continue;
203 val = addr;
204 val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT;
205 WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem,
206 "insufficient fifo memory");
207 addr += hsotg->g_tx_fifo_sz[ep];
208
209 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
210 }
211
212 /*
213 * according to p428 of the design guide, we need to ensure that
214 * all fifos are flushed before continuing
215 */
216
217 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
218 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
219
220 /* wait until the fifos are both flushed */
221 timeout = 100;
222 while (1) {
223 val = dwc2_readl(hsotg->regs + GRSTCTL);
224
225 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
226 break;
227
228 if (--timeout == 0) {
229 dev_err(hsotg->dev,
230 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
231 __func__, val);
232 break;
233 }
234
235 udelay(1);
236 }
237
238 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
239}
240
241/**
242 * @ep: USB endpoint to allocate request for.
243 * @flags: Allocation flags
244 *
245 * Allocate a new USB request structure appropriate for the specified endpoint
246 */
247static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
248 gfp_t flags)
249{
250 struct dwc2_hsotg_req *req;
251
252 req = kzalloc(sizeof(struct dwc2_hsotg_req), flags);
253 if (!req)
254 return NULL;
255
256 INIT_LIST_HEAD(&req->queue);
257
258 return &req->req;
259}
260
261/**
262 * is_ep_periodic - return true if the endpoint is in periodic mode.
263 * @hs_ep: The endpoint to query.
264 *
265 * Returns true if the endpoint is in periodic mode, meaning it is being
266 * used for an Interrupt or ISO transfer.
267 */
268static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
269{
270 return hs_ep->periodic;
271}
272
273/**
274 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
275 * @hsotg: The device state.
276 * @hs_ep: The endpoint for the request
277 * @hs_req: The request being processed.
278 *
279 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
280 * of a request to ensure the buffer is ready for access by the caller.
281 */
282static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
283 struct dwc2_hsotg_ep *hs_ep,
284 struct dwc2_hsotg_req *hs_req)
285{
286 struct usb_request *req = &hs_req->req;
287
288 /* ignore this if we're not moving any data */
289 if (hs_req->req.length == 0)
290 return;
291
292 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
293}
294
295/**
296 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
297 * @hsotg: The controller state.
298 * @hs_ep: The endpoint we're going to write for.
299 * @hs_req: The request to write data for.
300 *
301 * This is called when the TxFIFO has some space in it to hold a new
302 * transmission and we have something to give it. The actual setup of
303 * the data size is done elsewhere, so all we have to do is to actually
304 * write the data.
305 *
306 * The return value is zero if there is more space (or nothing was done)
307 * otherwise -ENOSPC is returned if the FIFO space was used up.
308 *
309 * This routine is only needed for PIO
310 */
311static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
312 struct dwc2_hsotg_ep *hs_ep,
313 struct dwc2_hsotg_req *hs_req)
314{
315 bool periodic = is_ep_periodic(hs_ep);
316 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
317 int buf_pos = hs_req->req.actual;
318 int to_write = hs_ep->size_loaded;
319 void *data;
320 int can_write;
321 int pkt_round;
322 int max_transfer;
323
324 to_write -= (buf_pos - hs_ep->last_load);
325
326 /* if there's nothing to write, get out early */
327 if (to_write == 0)
328 return 0;
329
330 if (periodic && !hsotg->dedicated_fifos) {
331 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
332 int size_left;
333 int size_done;
334
335 /*
336 * work out how much data was loaded so we can calculate
337 * how much data is left in the fifo.
338 */
339
340 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
341
342 /*
343 * if shared fifo, we cannot write anything until the
344 * previous data has been completely sent.
345 */
346 if (hs_ep->fifo_load != 0) {
347 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
348 return -ENOSPC;
349 }
350
351 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
352 __func__, size_left,
353 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
354
355 /* how much of the data has moved */
356 size_done = hs_ep->size_loaded - size_left;
357
358 /* how much data is left in the fifo */
359 can_write = hs_ep->fifo_load - size_done;
360 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
361 __func__, can_write);
362
363 can_write = hs_ep->fifo_size - can_write;
364 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
365 __func__, can_write);
366
367 if (can_write <= 0) {
368 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
369 return -ENOSPC;
370 }
371 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
372 can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index));
373
374 can_write &= 0xffff;
375 can_write *= 4;
376 } else {
377 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
378 dev_dbg(hsotg->dev,
379 "%s: no queue slots available (0x%08x)\n",
380 __func__, gnptxsts);
381
382 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
383 return -ENOSPC;
384 }
385
386 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
387 can_write *= 4; /* fifo size is in 32bit quantities. */
388 }
389
390 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
391
392 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
393 __func__, gnptxsts, can_write, to_write, max_transfer);
394
395 /*
396 * limit to 512 bytes of data, it seems at least on the non-periodic
397 * FIFO, requests of >512 cause the endpoint to get stuck with a
398 * fragment of the end of the transfer in it.
399 */
400 if (can_write > 512 && !periodic)
401 can_write = 512;
402
403 /*
404 * limit the write to one max-packet size worth of data, but allow
405 * the transfer to return that it did not run out of fifo space
406 * doing it.
407 */
408 if (to_write > max_transfer) {
409 to_write = max_transfer;
410
411 /* it's needed only when we do not use dedicated fifos */
412 if (!hsotg->dedicated_fifos)
413 dwc2_hsotg_en_gsint(hsotg,
414 periodic ? GINTSTS_PTXFEMP :
415 GINTSTS_NPTXFEMP);
416 }
417
418 /* see if we can write data */
419
420 if (to_write > can_write) {
421 to_write = can_write;
422 pkt_round = to_write % max_transfer;
423
424 /*
425 * Round the write down to an
426 * exact number of packets.
427 *
428 * Note, we do not currently check to see if we can ever
429 * write a full packet or not to the FIFO.
430 */
431
432 if (pkt_round)
433 to_write -= pkt_round;
434
435 /*
436 * enable correct FIFO interrupt to alert us when there
437 * is more room left.
438 */
439
440 /* it's needed only when we do not use dedicated fifos */
441 if (!hsotg->dedicated_fifos)
442 dwc2_hsotg_en_gsint(hsotg,
443 periodic ? GINTSTS_PTXFEMP :
444 GINTSTS_NPTXFEMP);
445 }
446
447 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
448 to_write, hs_req->req.length, can_write, buf_pos);
449
450 if (to_write <= 0)
451 return -ENOSPC;
452
453 hs_req->req.actual = buf_pos + to_write;
454 hs_ep->total_data += to_write;
455
456 if (periodic)
457 hs_ep->fifo_load += to_write;
458
459 to_write = DIV_ROUND_UP(to_write, 4);
460 data = hs_req->req.buf + buf_pos;
461
462 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
463
464 return (to_write >= can_write) ? -ENOSPC : 0;
465}
466
467/**
468 * get_ep_limit - get the maximum data legnth for this endpoint
469 * @hs_ep: The endpoint
470 *
471 * Return the maximum data that can be queued in one go on a given endpoint
472 * so that transfers that are too long can be split.
473 */
474static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
475{
476 int index = hs_ep->index;
477 unsigned maxsize;
478 unsigned maxpkt;
479
480 if (index != 0) {
481 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
482 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
483 } else {
484 maxsize = 64+64;
485 if (hs_ep->dir_in)
486 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
487 else
488 maxpkt = 2;
489 }
490
491 /* we made the constant loading easier above by using +1 */
492 maxpkt--;
493 maxsize--;
494
495 /*
496 * constrain by packet count if maxpkts*pktsize is greater
497 * than the length register size.
498 */
499
500 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
501 maxsize = maxpkt * hs_ep->ep.maxpacket;
502
503 return maxsize;
504}
505
506/**
507 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
508 * @hsotg: The controller state.
509 * @hs_ep: The endpoint to process a request for
510 * @hs_req: The request to start.
511 * @continuing: True if we are doing more for the current request.
512 *
513 * Start the given request running by setting the endpoint registers
514 * appropriately, and writing any data to the FIFOs.
515 */
516static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
517 struct dwc2_hsotg_ep *hs_ep,
518 struct dwc2_hsotg_req *hs_req,
519 bool continuing)
520{
521 struct usb_request *ureq = &hs_req->req;
522 int index = hs_ep->index;
523 int dir_in = hs_ep->dir_in;
524 u32 epctrl_reg;
525 u32 epsize_reg;
526 u32 epsize;
527 u32 ctrl;
528 unsigned length;
529 unsigned packets;
530 unsigned maxreq;
531
532 if (index != 0) {
533 if (hs_ep->req && !continuing) {
534 dev_err(hsotg->dev, "%s: active request\n", __func__);
535 WARN_ON(1);
536 return;
537 } else if (hs_ep->req != hs_req && continuing) {
538 dev_err(hsotg->dev,
539 "%s: continue different req\n", __func__);
540 WARN_ON(1);
541 return;
542 }
543 }
544
545 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
546 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
547
548 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
549 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
550 hs_ep->dir_in ? "in" : "out");
551
552 /* If endpoint is stalled, we will restart request later */
553 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
554
555 if (index && ctrl & DXEPCTL_STALL) {
556 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
557 return;
558 }
559
560 length = ureq->length - ureq->actual;
561 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
562 ureq->length, ureq->actual);
563
564 maxreq = get_ep_limit(hs_ep);
565 if (length > maxreq) {
566 int round = maxreq % hs_ep->ep.maxpacket;
567
568 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
569 __func__, length, maxreq, round);
570
571 /* round down to multiple of packets */
572 if (round)
573 maxreq -= round;
574
575 length = maxreq;
576 }
577
578 if (length)
579 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
580 else
581 packets = 1; /* send one packet if length is zero. */
582
583 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
584 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
585 return;
586 }
587
588 if (dir_in && index != 0)
589 if (hs_ep->isochronous)
590 epsize = DXEPTSIZ_MC(packets);
591 else
592 epsize = DXEPTSIZ_MC(1);
593 else
594 epsize = 0;
595
596 /*
597 * zero length packet should be programmed on its own and should not
598 * be counted in DIEPTSIZ.PktCnt with other packets.
599 */
600 if (dir_in && ureq->zero && !continuing) {
601 /* Test if zlp is actually required. */
602 if ((ureq->length >= hs_ep->ep.maxpacket) &&
603 !(ureq->length % hs_ep->ep.maxpacket))
604 hs_ep->send_zlp = 1;
605 }
606
607 epsize |= DXEPTSIZ_PKTCNT(packets);
608 epsize |= DXEPTSIZ_XFERSIZE(length);
609
610 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
611 __func__, packets, length, ureq->length, epsize, epsize_reg);
612
613 /* store the request as the current one we're doing */
614 hs_ep->req = hs_req;
615
616 /* write size / packets */
617 dwc2_writel(epsize, hsotg->regs + epsize_reg);
618
619 if (using_dma(hsotg) && !continuing) {
620 unsigned int dma_reg;
621
622 /*
623 * write DMA address to control register, buffer already
624 * synced by dwc2_hsotg_ep_queue().
625 */
626
627 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
628 dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
629
630 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
631 __func__, &ureq->dma, dma_reg);
632 }
633
634 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
635 ctrl |= DXEPCTL_USBACTEP;
636
637 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
638
639 /* For Setup request do not clear NAK */
640 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
641 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
642
643 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
644 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
645
646 /*
647 * set these, it seems that DMA support increments past the end
648 * of the packet buffer so we need to calculate the length from
649 * this information.
650 */
651 hs_ep->size_loaded = length;
652 hs_ep->last_load = ureq->actual;
653
654 if (dir_in && !using_dma(hsotg)) {
655 /* set these anyway, we may need them for non-periodic in */
656 hs_ep->fifo_load = 0;
657
658 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
659 }
660
661 /*
662 * clear the INTknTXFEmpMsk when we start request, more as a aide
663 * to debugging to see what is going on.
664 */
665 if (dir_in)
666 dwc2_writel(DIEPMSK_INTKNTXFEMPMSK,
667 hsotg->regs + DIEPINT(index));
668
669 /*
670 * Note, trying to clear the NAK here causes problems with transmit
671 * on the S3C6400 ending up with the TXFIFO becoming full.
672 */
673
674 /* check ep is enabled */
675 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
676 dev_dbg(hsotg->dev,
677 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
678 index, dwc2_readl(hsotg->regs + epctrl_reg));
679
680 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
681 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
682
683 /* enable ep interrupts */
684 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
685}
686
687/**
688 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
689 * @hsotg: The device state.
690 * @hs_ep: The endpoint the request is on.
691 * @req: The request being processed.
692 *
693 * We've been asked to queue a request, so ensure that the memory buffer
694 * is correctly setup for DMA. If we've been passed an extant DMA address
695 * then ensure the buffer has been synced to memory. If our buffer has no
696 * DMA memory, then we map the memory and mark our request to allow us to
697 * cleanup on completion.
698 */
699static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
700 struct dwc2_hsotg_ep *hs_ep,
701 struct usb_request *req)
702{
703 struct dwc2_hsotg_req *hs_req = our_req(req);
704 int ret;
705
706 /* if the length is zero, ignore the DMA data */
707 if (hs_req->req.length == 0)
708 return 0;
709
710 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
711 if (ret)
712 goto dma_error;
713
714 return 0;
715
716dma_error:
717 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
718 __func__, req->buf, req->length);
719
720 return -EIO;
721}
722
723static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
724 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
725{
726 void *req_buf = hs_req->req.buf;
727
728 /* If dma is not being used or buffer is aligned */
729 if (!using_dma(hsotg) || !((long)req_buf & 3))
730 return 0;
731
732 WARN_ON(hs_req->saved_req_buf);
733
734 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
735 hs_ep->ep.name, req_buf, hs_req->req.length);
736
737 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
738 if (!hs_req->req.buf) {
739 hs_req->req.buf = req_buf;
740 dev_err(hsotg->dev,
741 "%s: unable to allocate memory for bounce buffer\n",
742 __func__);
743 return -ENOMEM;
744 }
745
746 /* Save actual buffer */
747 hs_req->saved_req_buf = req_buf;
748
749 if (hs_ep->dir_in)
750 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
751 return 0;
752}
753
754static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
755 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
756{
757 /* If dma is not being used or buffer was aligned */
758 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
759 return;
760
761 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
762 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
763
764 /* Copy data from bounce buffer on successful out transfer */
765 if (!hs_ep->dir_in && !hs_req->req.status)
766 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
767 hs_req->req.actual);
768
769 /* Free bounce buffer */
770 kfree(hs_req->req.buf);
771
772 hs_req->req.buf = hs_req->saved_req_buf;
773 hs_req->saved_req_buf = NULL;
774}
775
776static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
777 gfp_t gfp_flags)
778{
779 struct dwc2_hsotg_req *hs_req = our_req(req);
780 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
781 struct dwc2_hsotg *hs = hs_ep->parent;
782 bool first;
783 int ret;
784
785 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
786 ep->name, req, req->length, req->buf, req->no_interrupt,
787 req->zero, req->short_not_ok);
788
789 /* Prevent new request submission when controller is suspended */
790 if (hs->lx_state == DWC2_L2) {
791 dev_dbg(hs->dev, "%s: don't submit request while suspended\n",
792 __func__);
793 return -EAGAIN;
794 }
795
796 /* initialise status of the request */
797 INIT_LIST_HEAD(&hs_req->queue);
798 req->actual = 0;
799 req->status = -EINPROGRESS;
800
801 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
802 if (ret)
803 return ret;
804
805 /* if we're using DMA, sync the buffers as necessary */
806 if (using_dma(hs)) {
807 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
808 if (ret)
809 return ret;
810 }
811
812 first = list_empty(&hs_ep->queue);
813 list_add_tail(&hs_req->queue, &hs_ep->queue);
814
815 if (first)
816 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
817
818 return 0;
819}
820
821static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
822 gfp_t gfp_flags)
823{
824 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
825 struct dwc2_hsotg *hs = hs_ep->parent;
826 unsigned long flags = 0;
827 int ret = 0;
828
829 spin_lock_irqsave(&hs->lock, flags);
830 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
831 spin_unlock_irqrestore(&hs->lock, flags);
832
833 return ret;
834}
835
836static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
837 struct usb_request *req)
838{
839 struct dwc2_hsotg_req *hs_req = our_req(req);
840
841 kfree(hs_req);
842}
843
844/**
845 * dwc2_hsotg_complete_oursetup - setup completion callback
846 * @ep: The endpoint the request was on.
847 * @req: The request completed.
848 *
849 * Called on completion of any requests the driver itself
850 * submitted that need cleaning up.
851 */
852static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
853 struct usb_request *req)
854{
855 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
856 struct dwc2_hsotg *hsotg = hs_ep->parent;
857
858 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
859
860 dwc2_hsotg_ep_free_request(ep, req);
861}
862
863/**
864 * ep_from_windex - convert control wIndex value to endpoint
865 * @hsotg: The driver state.
866 * @windex: The control request wIndex field (in host order).
867 *
868 * Convert the given wIndex into a pointer to an driver endpoint
869 * structure, or return NULL if it is not a valid endpoint.
870 */
871static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
872 u32 windex)
873{
874 struct dwc2_hsotg_ep *ep;
875 int dir = (windex & USB_DIR_IN) ? 1 : 0;
876 int idx = windex & 0x7F;
877
878 if (windex >= 0x100)
879 return NULL;
880
881 if (idx > hsotg->num_of_eps)
882 return NULL;
883
884 ep = index_to_ep(hsotg, idx, dir);
885
886 if (idx && ep->dir_in != dir)
887 return NULL;
888
889 return ep;
890}
891
892/**
893 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
894 * @hsotg: The driver state.
895 * @testmode: requested usb test mode
896 * Enable usb Test Mode requested by the Host.
897 */
898int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
899{
900 int dctl = dwc2_readl(hsotg->regs + DCTL);
901
902 dctl &= ~DCTL_TSTCTL_MASK;
903 switch (testmode) {
904 case TEST_J:
905 case TEST_K:
906 case TEST_SE0_NAK:
907 case TEST_PACKET:
908 case TEST_FORCE_EN:
909 dctl |= testmode << DCTL_TSTCTL_SHIFT;
910 break;
911 default:
912 return -EINVAL;
913 }
914 dwc2_writel(dctl, hsotg->regs + DCTL);
915 return 0;
916}
917
918/**
919 * dwc2_hsotg_send_reply - send reply to control request
920 * @hsotg: The device state
921 * @ep: Endpoint 0
922 * @buff: Buffer for request
923 * @length: Length of reply.
924 *
925 * Create a request and queue it on the given endpoint. This is useful as
926 * an internal method of sending replies to certain control requests, etc.
927 */
928static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
929 struct dwc2_hsotg_ep *ep,
930 void *buff,
931 int length)
932{
933 struct usb_request *req;
934 int ret;
935
936 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
937
938 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
939 hsotg->ep0_reply = req;
940 if (!req) {
941 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
942 return -ENOMEM;
943 }
944
945 req->buf = hsotg->ep0_buff;
946 req->length = length;
947 /*
948 * zero flag is for sending zlp in DATA IN stage. It has no impact on
949 * STATUS stage.
950 */
951 req->zero = 0;
952 req->complete = dwc2_hsotg_complete_oursetup;
953
954 if (length)
955 memcpy(req->buf, buff, length);
956
957 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
958 if (ret) {
959 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
960 return ret;
961 }
962
963 return 0;
964}
965
966/**
967 * dwc2_hsotg_process_req_status - process request GET_STATUS
968 * @hsotg: The device state
969 * @ctrl: USB control request
970 */
971static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
972 struct usb_ctrlrequest *ctrl)
973{
974 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
975 struct dwc2_hsotg_ep *ep;
976 __le16 reply;
977 int ret;
978
979 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
980
981 if (!ep0->dir_in) {
982 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
983 return -EINVAL;
984 }
985
986 switch (ctrl->bRequestType & USB_RECIP_MASK) {
987 case USB_RECIP_DEVICE:
988 reply = cpu_to_le16(0); /* bit 0 => self powered,
989 * bit 1 => remote wakeup */
990 break;
991
992 case USB_RECIP_INTERFACE:
993 /* currently, the data result should be zero */
994 reply = cpu_to_le16(0);
995 break;
996
997 case USB_RECIP_ENDPOINT:
998 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
999 if (!ep)
1000 return -ENOENT;
1001
1002 reply = cpu_to_le16(ep->halted ? 1 : 0);
1003 break;
1004
1005 default:
1006 return 0;
1007 }
1008
1009 if (le16_to_cpu(ctrl->wLength) != 2)
1010 return -EINVAL;
1011
1012 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1013 if (ret) {
1014 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1015 return ret;
1016 }
1017
1018 return 1;
1019}
1020
1021static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1022
1023/**
1024 * get_ep_head - return the first request on the endpoint
1025 * @hs_ep: The controller endpoint to get
1026 *
1027 * Get the first request on the endpoint.
1028 */
1029static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1030{
1031 if (list_empty(&hs_ep->queue))
1032 return NULL;
1033
1034 return list_first_entry(&hs_ep->queue, struct dwc2_hsotg_req, queue);
1035}
1036
1037/**
1038 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1039 * @hsotg: The device state
1040 * @ctrl: USB control request
1041 */
1042static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1043 struct usb_ctrlrequest *ctrl)
1044{
1045 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1046 struct dwc2_hsotg_req *hs_req;
1047 bool restart;
1048 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1049 struct dwc2_hsotg_ep *ep;
1050 int ret;
1051 bool halted;
1052 u32 recip;
1053 u32 wValue;
1054 u32 wIndex;
1055
1056 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1057 __func__, set ? "SET" : "CLEAR");
1058
1059 wValue = le16_to_cpu(ctrl->wValue);
1060 wIndex = le16_to_cpu(ctrl->wIndex);
1061 recip = ctrl->bRequestType & USB_RECIP_MASK;
1062
1063 switch (recip) {
1064 case USB_RECIP_DEVICE:
1065 switch (wValue) {
1066 case USB_DEVICE_TEST_MODE:
1067 if ((wIndex & 0xff) != 0)
1068 return -EINVAL;
1069 if (!set)
1070 return -EINVAL;
1071
1072 hsotg->test_mode = wIndex >> 8;
1073 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1074 if (ret) {
1075 dev_err(hsotg->dev,
1076 "%s: failed to send reply\n", __func__);
1077 return ret;
1078 }
1079 break;
1080 default:
1081 return -ENOENT;
1082 }
1083 break;
1084
1085 case USB_RECIP_ENDPOINT:
1086 ep = ep_from_windex(hsotg, wIndex);
1087 if (!ep) {
1088 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1089 __func__, wIndex);
1090 return -ENOENT;
1091 }
1092
1093 switch (wValue) {
1094 case USB_ENDPOINT_HALT:
1095 halted = ep->halted;
1096
1097 dwc2_hsotg_ep_sethalt(&ep->ep, set);
1098
1099 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1100 if (ret) {
1101 dev_err(hsotg->dev,
1102 "%s: failed to send reply\n", __func__);
1103 return ret;
1104 }
1105
1106 /*
1107 * we have to complete all requests for ep if it was
1108 * halted, and the halt was cleared by CLEAR_FEATURE
1109 */
1110
1111 if (!set && halted) {
1112 /*
1113 * If we have request in progress,
1114 * then complete it
1115 */
1116 if (ep->req) {
1117 hs_req = ep->req;
1118 ep->req = NULL;
1119 list_del_init(&hs_req->queue);
1120 if (hs_req->req.complete) {
1121 spin_unlock(&hsotg->lock);
1122 usb_gadget_giveback_request(
1123 &ep->ep, &hs_req->req);
1124 spin_lock(&hsotg->lock);
1125 }
1126 }
1127
1128 /* If we have pending request, then start it */
1129 if (!ep->req) {
1130 restart = !list_empty(&ep->queue);
1131 if (restart) {
1132 hs_req = get_ep_head(ep);
1133 dwc2_hsotg_start_req(hsotg, ep,
1134 hs_req, false);
1135 }
1136 }
1137 }
1138
1139 break;
1140
1141 default:
1142 return -ENOENT;
1143 }
1144 break;
1145 default:
1146 return -ENOENT;
1147 }
1148 return 1;
1149}
1150
1151static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1152
1153/**
1154 * dwc2_hsotg_stall_ep0 - stall ep0
1155 * @hsotg: The device state
1156 *
1157 * Set stall for ep0 as response for setup request.
1158 */
1159static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1160{
1161 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1162 u32 reg;
1163 u32 ctrl;
1164
1165 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1166 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1167
1168 /*
1169 * DxEPCTL_Stall will be cleared by EP once it has
1170 * taken effect, so no need to clear later.
1171 */
1172
1173 ctrl = dwc2_readl(hsotg->regs + reg);
1174 ctrl |= DXEPCTL_STALL;
1175 ctrl |= DXEPCTL_CNAK;
1176 dwc2_writel(ctrl, hsotg->regs + reg);
1177
1178 dev_dbg(hsotg->dev,
1179 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1180 ctrl, reg, dwc2_readl(hsotg->regs + reg));
1181
1182 /*
1183 * complete won't be called, so we enqueue
1184 * setup request here
1185 */
1186 dwc2_hsotg_enqueue_setup(hsotg);
1187}
1188
1189/**
1190 * dwc2_hsotg_process_control - process a control request
1191 * @hsotg: The device state
1192 * @ctrl: The control request received
1193 *
1194 * The controller has received the SETUP phase of a control request, and
1195 * needs to work out what to do next (and whether to pass it on to the
1196 * gadget driver).
1197 */
1198static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1199 struct usb_ctrlrequest *ctrl)
1200{
1201 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1202 int ret = 0;
1203 u32 dcfg;
1204
1205 dev_dbg(hsotg->dev,
1206 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1207 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1208 ctrl->wIndex, ctrl->wLength);
1209
1210 if (ctrl->wLength == 0) {
1211 ep0->dir_in = 1;
1212 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1213 } else if (ctrl->bRequestType & USB_DIR_IN) {
1214 ep0->dir_in = 1;
1215 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1216 } else {
1217 ep0->dir_in = 0;
1218 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1219 }
1220
1221 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1222 switch (ctrl->bRequest) {
1223 case USB_REQ_SET_ADDRESS:
1224 hsotg->connected = 1;
1225 dcfg = dwc2_readl(hsotg->regs + DCFG);
1226 dcfg &= ~DCFG_DEVADDR_MASK;
1227 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1228 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1229 dwc2_writel(dcfg, hsotg->regs + DCFG);
1230
1231 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1232
1233 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1234 return;
1235
1236 case USB_REQ_GET_STATUS:
1237 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1238 break;
1239
1240 case USB_REQ_CLEAR_FEATURE:
1241 case USB_REQ_SET_FEATURE:
1242 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1243 break;
1244 }
1245 }
1246
1247 /* as a fallback, try delivering it to the driver to deal with */
1248
1249 if (ret == 0 && hsotg->driver) {
1250 spin_unlock(&hsotg->lock);
1251 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1252 spin_lock(&hsotg->lock);
1253 if (ret < 0)
1254 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1255 }
1256
1257 /*
1258 * the request is either unhandlable, or is not formatted correctly
1259 * so respond with a STALL for the status stage to indicate failure.
1260 */
1261
1262 if (ret < 0)
1263 dwc2_hsotg_stall_ep0(hsotg);
1264}
1265
1266/**
1267 * dwc2_hsotg_complete_setup - completion of a setup transfer
1268 * @ep: The endpoint the request was on.
1269 * @req: The request completed.
1270 *
1271 * Called on completion of any requests the driver itself submitted for
1272 * EP0 setup packets
1273 */
1274static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1275 struct usb_request *req)
1276{
1277 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1278 struct dwc2_hsotg *hsotg = hs_ep->parent;
1279
1280 if (req->status < 0) {
1281 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1282 return;
1283 }
1284
1285 spin_lock(&hsotg->lock);
1286 if (req->actual == 0)
1287 dwc2_hsotg_enqueue_setup(hsotg);
1288 else
1289 dwc2_hsotg_process_control(hsotg, req->buf);
1290 spin_unlock(&hsotg->lock);
1291}
1292
1293/**
1294 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1295 * @hsotg: The device state.
1296 *
1297 * Enqueue a request on EP0 if necessary to received any SETUP packets
1298 * received from the host.
1299 */
1300static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1301{
1302 struct usb_request *req = hsotg->ctrl_req;
1303 struct dwc2_hsotg_req *hs_req = our_req(req);
1304 int ret;
1305
1306 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1307
1308 req->zero = 0;
1309 req->length = 8;
1310 req->buf = hsotg->ctrl_buff;
1311 req->complete = dwc2_hsotg_complete_setup;
1312
1313 if (!list_empty(&hs_req->queue)) {
1314 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1315 return;
1316 }
1317
1318 hsotg->eps_out[0]->dir_in = 0;
1319 hsotg->eps_out[0]->send_zlp = 0;
1320 hsotg->ep0_state = DWC2_EP0_SETUP;
1321
1322 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1323 if (ret < 0) {
1324 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1325 /*
1326 * Don't think there's much we can do other than watch the
1327 * driver fail.
1328 */
1329 }
1330}
1331
1332static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1333 struct dwc2_hsotg_ep *hs_ep)
1334{
1335 u32 ctrl;
1336 u8 index = hs_ep->index;
1337 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1338 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1339
1340 if (hs_ep->dir_in)
1341 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
1342 index);
1343 else
1344 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1345 index);
1346
1347 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1348 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1349 epsiz_reg);
1350
1351 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1352 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1353 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1354 ctrl |= DXEPCTL_USBACTEP;
1355 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1356}
1357
1358/**
1359 * dwc2_hsotg_complete_request - complete a request given to us
1360 * @hsotg: The device state.
1361 * @hs_ep: The endpoint the request was on.
1362 * @hs_req: The request to complete.
1363 * @result: The result code (0 => Ok, otherwise errno)
1364 *
1365 * The given request has finished, so call the necessary completion
1366 * if it has one and then look to see if we can start a new request
1367 * on the endpoint.
1368 *
1369 * Note, expects the ep to already be locked as appropriate.
1370 */
1371static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1372 struct dwc2_hsotg_ep *hs_ep,
1373 struct dwc2_hsotg_req *hs_req,
1374 int result)
1375{
1376 bool restart;
1377
1378 if (!hs_req) {
1379 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1380 return;
1381 }
1382
1383 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1384 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1385
1386 /*
1387 * only replace the status if we've not already set an error
1388 * from a previous transaction
1389 */
1390
1391 if (hs_req->req.status == -EINPROGRESS)
1392 hs_req->req.status = result;
1393
1394 if (using_dma(hsotg))
1395 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1396
1397 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
1398
1399 hs_ep->req = NULL;
1400 list_del_init(&hs_req->queue);
1401
1402 /*
1403 * call the complete request with the locks off, just in case the
1404 * request tries to queue more work for this endpoint.
1405 */
1406
1407 if (hs_req->req.complete) {
1408 spin_unlock(&hsotg->lock);
1409 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
1410 spin_lock(&hsotg->lock);
1411 }
1412
1413 /*
1414 * Look to see if there is anything else to do. Note, the completion
1415 * of the previous request may have caused a new request to be started
1416 * so be careful when doing this.
1417 */
1418
1419 if (!hs_ep->req && result >= 0) {
1420 restart = !list_empty(&hs_ep->queue);
1421 if (restart) {
1422 hs_req = get_ep_head(hs_ep);
1423 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1424 }
1425 }
1426}
1427
1428/**
1429 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
1430 * @hsotg: The device state.
1431 * @ep_idx: The endpoint index for the data
1432 * @size: The size of data in the fifo, in bytes
1433 *
1434 * The FIFO status shows there is data to read from the FIFO for a given
1435 * endpoint, so sort out whether we need to read the data into a request
1436 * that has been made for that endpoint.
1437 */
1438static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
1439{
1440 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
1441 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1442 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1443 int to_read;
1444 int max_req;
1445 int read_ptr;
1446
1447
1448 if (!hs_req) {
1449 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
1450 int ptr;
1451
1452 dev_dbg(hsotg->dev,
1453 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1454 __func__, size, ep_idx, epctl);
1455
1456 /* dump the data from the FIFO, we've nothing we can do */
1457 for (ptr = 0; ptr < size; ptr += 4)
1458 (void)dwc2_readl(fifo);
1459
1460 return;
1461 }
1462
1463 to_read = size;
1464 read_ptr = hs_req->req.actual;
1465 max_req = hs_req->req.length - read_ptr;
1466
1467 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1468 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1469
1470 if (to_read > max_req) {
1471 /*
1472 * more data appeared than we where willing
1473 * to deal with in this request.
1474 */
1475
1476 /* currently we don't deal this */
1477 WARN_ON_ONCE(1);
1478 }
1479
1480 hs_ep->total_data += to_read;
1481 hs_req->req.actual += to_read;
1482 to_read = DIV_ROUND_UP(to_read, 4);
1483
1484 /*
1485 * note, we might over-write the buffer end by 3 bytes depending on
1486 * alignment of the data.
1487 */
1488 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
1489}
1490
1491/**
1492 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
1493 * @hsotg: The device instance
1494 * @dir_in: If IN zlp
1495 *
1496 * Generate a zero-length IN packet request for terminating a SETUP
1497 * transaction.
1498 *
1499 * Note, since we don't write any data to the TxFIFO, then it is
1500 * currently believed that we do not need to wait for any space in
1501 * the TxFIFO.
1502 */
1503static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
1504{
1505 /* eps_out[0] is used in both directions */
1506 hsotg->eps_out[0]->dir_in = dir_in;
1507 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
1508
1509 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
1510}
1511
1512static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
1513 u32 epctl_reg)
1514{
1515 u32 ctrl;
1516
1517 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1518 if (ctrl & DXEPCTL_EOFRNUM)
1519 ctrl |= DXEPCTL_SETEVENFR;
1520 else
1521 ctrl |= DXEPCTL_SETODDFR;
1522 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1523}
1524
1525/**
1526 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1527 * @hsotg: The device instance
1528 * @epnum: The endpoint received from
1529 *
1530 * The RXFIFO has delivered an OutDone event, which means that the data
1531 * transfer for an OUT endpoint has been completed, either by a short
1532 * packet or by the finish of a transfer.
1533 */
1534static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
1535{
1536 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
1537 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
1538 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1539 struct usb_request *req = &hs_req->req;
1540 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1541 int result = 0;
1542
1543 if (!hs_req) {
1544 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1545 return;
1546 }
1547
1548 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
1549 dev_dbg(hsotg->dev, "zlp packet received\n");
1550 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1551 dwc2_hsotg_enqueue_setup(hsotg);
1552 return;
1553 }
1554
1555 if (using_dma(hsotg)) {
1556 unsigned size_done;
1557
1558 /*
1559 * Calculate the size of the transfer by checking how much
1560 * is left in the endpoint size register and then working it
1561 * out from the amount we loaded for the transfer.
1562 *
1563 * We need to do this as DMA pointers are always 32bit aligned
1564 * so may overshoot/undershoot the transfer.
1565 */
1566
1567 size_done = hs_ep->size_loaded - size_left;
1568 size_done += hs_ep->last_load;
1569
1570 req->actual = size_done;
1571 }
1572
1573 /* if there is more request to do, schedule new transfer */
1574 if (req->actual < req->length && size_left == 0) {
1575 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1576 return;
1577 }
1578
1579 if (req->actual < req->length && req->short_not_ok) {
1580 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1581 __func__, req->actual, req->length);
1582
1583 /*
1584 * todo - what should we return here? there's no one else
1585 * even bothering to check the status.
1586 */
1587 }
1588
1589 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
1590 /* Move to STATUS IN */
1591 dwc2_hsotg_ep0_zlp(hsotg, true);
1592 return;
1593 }
1594
1595 /*
1596 * Slave mode OUT transfers do not go through XferComplete so
1597 * adjust the ISOC parity here.
1598 */
1599 if (!using_dma(hsotg)) {
1600 hs_ep->has_correct_parity = 1;
1601 if (hs_ep->isochronous && hs_ep->interval == 1)
1602 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
1603 }
1604
1605 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1606}
1607
1608/**
1609 * dwc2_hsotg_read_frameno - read current frame number
1610 * @hsotg: The device instance
1611 *
1612 * Return the current frame number
1613 */
1614static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
1615{
1616 u32 dsts;
1617
1618 dsts = dwc2_readl(hsotg->regs + DSTS);
1619 dsts &= DSTS_SOFFN_MASK;
1620 dsts >>= DSTS_SOFFN_SHIFT;
1621
1622 return dsts;
1623}
1624
1625/**
1626 * dwc2_hsotg_handle_rx - RX FIFO has data
1627 * @hsotg: The device instance
1628 *
1629 * The IRQ handler has detected that the RX FIFO has some data in it
1630 * that requires processing, so find out what is in there and do the
1631 * appropriate read.
1632 *
1633 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1634 * chunks, so if you have x packets received on an endpoint you'll get x
1635 * FIFO events delivered, each with a packet's worth of data in it.
1636 *
1637 * When using DMA, we should not be processing events from the RXFIFO
1638 * as the actual data should be sent to the memory directly and we turn
1639 * on the completion interrupts to get notifications of transfer completion.
1640 */
1641static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
1642{
1643 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
1644 u32 epnum, status, size;
1645
1646 WARN_ON(using_dma(hsotg));
1647
1648 epnum = grxstsr & GRXSTS_EPNUM_MASK;
1649 status = grxstsr & GRXSTS_PKTSTS_MASK;
1650
1651 size = grxstsr & GRXSTS_BYTECNT_MASK;
1652 size >>= GRXSTS_BYTECNT_SHIFT;
1653
1654 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1655 __func__, grxstsr, size, epnum);
1656
1657 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
1658 case GRXSTS_PKTSTS_GLOBALOUTNAK:
1659 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
1660 break;
1661
1662 case GRXSTS_PKTSTS_OUTDONE:
1663 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1664 dwc2_hsotg_read_frameno(hsotg));
1665
1666 if (!using_dma(hsotg))
1667 dwc2_hsotg_handle_outdone(hsotg, epnum);
1668 break;
1669
1670 case GRXSTS_PKTSTS_SETUPDONE:
1671 dev_dbg(hsotg->dev,
1672 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1673 dwc2_hsotg_read_frameno(hsotg),
1674 dwc2_readl(hsotg->regs + DOEPCTL(0)));
1675 /*
1676 * Call dwc2_hsotg_handle_outdone here if it was not called from
1677 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
1678 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
1679 */
1680 if (hsotg->ep0_state == DWC2_EP0_SETUP)
1681 dwc2_hsotg_handle_outdone(hsotg, epnum);
1682 break;
1683
1684 case GRXSTS_PKTSTS_OUTRX:
1685 dwc2_hsotg_rx_data(hsotg, epnum, size);
1686 break;
1687
1688 case GRXSTS_PKTSTS_SETUPRX:
1689 dev_dbg(hsotg->dev,
1690 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1691 dwc2_hsotg_read_frameno(hsotg),
1692 dwc2_readl(hsotg->regs + DOEPCTL(0)));
1693
1694 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
1695
1696 dwc2_hsotg_rx_data(hsotg, epnum, size);
1697 break;
1698
1699 default:
1700 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1701 __func__, grxstsr);
1702
1703 dwc2_hsotg_dump(hsotg);
1704 break;
1705 }
1706}
1707
1708/**
1709 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
1710 * @mps: The maximum packet size in bytes.
1711 */
1712static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
1713{
1714 switch (mps) {
1715 case 64:
1716 return D0EPCTL_MPS_64;
1717 case 32:
1718 return D0EPCTL_MPS_32;
1719 case 16:
1720 return D0EPCTL_MPS_16;
1721 case 8:
1722 return D0EPCTL_MPS_8;
1723 }
1724
1725 /* bad max packet size, warn and return invalid result */
1726 WARN_ON(1);
1727 return (u32)-1;
1728}
1729
1730/**
1731 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1732 * @hsotg: The driver state.
1733 * @ep: The index number of the endpoint
1734 * @mps: The maximum packet size in bytes
1735 *
1736 * Configure the maximum packet size for the given endpoint, updating
1737 * the hardware control registers to reflect this.
1738 */
1739static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
1740 unsigned int ep, unsigned int mps, unsigned int dir_in)
1741{
1742 struct dwc2_hsotg_ep *hs_ep;
1743 void __iomem *regs = hsotg->regs;
1744 u32 mpsval;
1745 u32 mcval;
1746 u32 reg;
1747
1748 hs_ep = index_to_ep(hsotg, ep, dir_in);
1749 if (!hs_ep)
1750 return;
1751
1752 if (ep == 0) {
1753 /* EP0 is a special case */
1754 mpsval = dwc2_hsotg_ep0_mps(mps);
1755 if (mpsval > 3)
1756 goto bad_mps;
1757 hs_ep->ep.maxpacket = mps;
1758 hs_ep->mc = 1;
1759 } else {
1760 mpsval = mps & DXEPCTL_MPS_MASK;
1761 if (mpsval > 1024)
1762 goto bad_mps;
1763 mcval = ((mps >> 11) & 0x3) + 1;
1764 hs_ep->mc = mcval;
1765 if (mcval > 3)
1766 goto bad_mps;
1767 hs_ep->ep.maxpacket = mpsval;
1768 }
1769
1770 if (dir_in) {
1771 reg = dwc2_readl(regs + DIEPCTL(ep));
1772 reg &= ~DXEPCTL_MPS_MASK;
1773 reg |= mpsval;
1774 dwc2_writel(reg, regs + DIEPCTL(ep));
1775 } else {
1776 reg = dwc2_readl(regs + DOEPCTL(ep));
1777 reg &= ~DXEPCTL_MPS_MASK;
1778 reg |= mpsval;
1779 dwc2_writel(reg, regs + DOEPCTL(ep));
1780 }
1781
1782 return;
1783
1784bad_mps:
1785 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1786}
1787
1788/**
1789 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
1790 * @hsotg: The driver state
1791 * @idx: The index for the endpoint (0..15)
1792 */
1793static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
1794{
1795 int timeout;
1796 int val;
1797
1798 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1799 hsotg->regs + GRSTCTL);
1800
1801 /* wait until the fifo is flushed */
1802 timeout = 100;
1803
1804 while (1) {
1805 val = dwc2_readl(hsotg->regs + GRSTCTL);
1806
1807 if ((val & (GRSTCTL_TXFFLSH)) == 0)
1808 break;
1809
1810 if (--timeout == 0) {
1811 dev_err(hsotg->dev,
1812 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1813 __func__, val);
1814 break;
1815 }
1816
1817 udelay(1);
1818 }
1819}
1820
1821/**
1822 * dwc2_hsotg_trytx - check to see if anything needs transmitting
1823 * @hsotg: The driver state
1824 * @hs_ep: The driver endpoint to check.
1825 *
1826 * Check to see if there is a request that has data to send, and if so
1827 * make an attempt to write data into the FIFO.
1828 */
1829static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
1830 struct dwc2_hsotg_ep *hs_ep)
1831{
1832 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1833
1834 if (!hs_ep->dir_in || !hs_req) {
1835 /**
1836 * if request is not enqueued, we disable interrupts
1837 * for endpoints, excepting ep0
1838 */
1839 if (hs_ep->index != 0)
1840 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
1841 hs_ep->dir_in, 0);
1842 return 0;
1843 }
1844
1845 if (hs_req->req.actual < hs_req->req.length) {
1846 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1847 hs_ep->index);
1848 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1849 }
1850
1851 return 0;
1852}
1853
1854/**
1855 * dwc2_hsotg_complete_in - complete IN transfer
1856 * @hsotg: The device state.
1857 * @hs_ep: The endpoint that has just completed.
1858 *
1859 * An IN transfer has been completed, update the transfer's state and then
1860 * call the relevant completion routines.
1861 */
1862static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
1863 struct dwc2_hsotg_ep *hs_ep)
1864{
1865 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1866 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1867 int size_left, size_done;
1868
1869 if (!hs_req) {
1870 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1871 return;
1872 }
1873
1874 /* Finish ZLP handling for IN EP0 transactions */
1875 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
1876 dev_dbg(hsotg->dev, "zlp packet sent\n");
1877 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1878 if (hsotg->test_mode) {
1879 int ret;
1880
1881 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
1882 if (ret < 0) {
1883 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
1884 hsotg->test_mode);
1885 dwc2_hsotg_stall_ep0(hsotg);
1886 return;
1887 }
1888 }
1889 dwc2_hsotg_enqueue_setup(hsotg);
1890 return;
1891 }
1892
1893 /*
1894 * Calculate the size of the transfer by checking how much is left
1895 * in the endpoint size register and then working it out from
1896 * the amount we loaded for the transfer.
1897 *
1898 * We do this even for DMA, as the transfer may have incremented
1899 * past the end of the buffer (DMA transfers are always 32bit
1900 * aligned).
1901 */
1902
1903 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1904
1905 size_done = hs_ep->size_loaded - size_left;
1906 size_done += hs_ep->last_load;
1907
1908 if (hs_req->req.actual != size_done)
1909 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1910 __func__, hs_req->req.actual, size_done);
1911
1912 hs_req->req.actual = size_done;
1913 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1914 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1915
1916 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1917 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1918 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1919 return;
1920 }
1921
1922 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
1923 if (hs_ep->send_zlp) {
1924 dwc2_hsotg_program_zlp(hsotg, hs_ep);
1925 hs_ep->send_zlp = 0;
1926 /* transfer will be completed on next complete interrupt */
1927 return;
1928 }
1929
1930 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
1931 /* Move to STATUS OUT */
1932 dwc2_hsotg_ep0_zlp(hsotg, false);
1933 return;
1934 }
1935
1936 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1937}
1938
1939/**
1940 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
1941 * @hsotg: The driver state
1942 * @idx: The index for the endpoint (0..15)
1943 * @dir_in: Set if this is an IN endpoint
1944 *
1945 * Process and clear any interrupt pending for an individual endpoint
1946 */
1947static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
1948 int dir_in)
1949{
1950 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
1951 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1952 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1953 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1954 u32 ints;
1955 u32 ctrl;
1956
1957 ints = dwc2_readl(hsotg->regs + epint_reg);
1958 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1959
1960 /* Clear endpoint interrupts */
1961 dwc2_writel(ints, hsotg->regs + epint_reg);
1962
1963 if (!hs_ep) {
1964 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
1965 __func__, idx, dir_in ? "in" : "out");
1966 return;
1967 }
1968
1969 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1970 __func__, idx, dir_in ? "in" : "out", ints);
1971
1972 /* Don't process XferCompl interrupt if it is a setup packet */
1973 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
1974 ints &= ~DXEPINT_XFERCOMPL;
1975
1976 if (ints & DXEPINT_XFERCOMPL) {
1977 hs_ep->has_correct_parity = 1;
1978 if (hs_ep->isochronous && hs_ep->interval == 1)
1979 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
1980
1981 dev_dbg(hsotg->dev,
1982 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
1983 __func__, dwc2_readl(hsotg->regs + epctl_reg),
1984 dwc2_readl(hsotg->regs + epsiz_reg));
1985
1986 /*
1987 * we get OutDone from the FIFO, so we only need to look
1988 * at completing IN requests here
1989 */
1990 if (dir_in) {
1991 dwc2_hsotg_complete_in(hsotg, hs_ep);
1992
1993 if (idx == 0 && !hs_ep->req)
1994 dwc2_hsotg_enqueue_setup(hsotg);
1995 } else if (using_dma(hsotg)) {
1996 /*
1997 * We're using DMA, we need to fire an OutDone here
1998 * as we ignore the RXFIFO.
1999 */
2000
2001 dwc2_hsotg_handle_outdone(hsotg, idx);
2002 }
2003 }
2004
2005 if (ints & DXEPINT_EPDISBLD) {
2006 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2007
2008 if (dir_in) {
2009 int epctl = dwc2_readl(hsotg->regs + epctl_reg);
2010
2011 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2012
2013 if ((epctl & DXEPCTL_STALL) &&
2014 (epctl & DXEPCTL_EPTYPE_BULK)) {
2015 int dctl = dwc2_readl(hsotg->regs + DCTL);
2016
2017 dctl |= DCTL_CGNPINNAK;
2018 dwc2_writel(dctl, hsotg->regs + DCTL);
2019 }
2020 }
2021 }
2022
2023 if (ints & DXEPINT_AHBERR)
2024 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2025
2026 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
2027 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2028
2029 if (using_dma(hsotg) && idx == 0) {
2030 /*
2031 * this is the notification we've received a
2032 * setup packet. In non-DMA mode we'd get this
2033 * from the RXFIFO, instead we need to process
2034 * the setup here.
2035 */
2036
2037 if (dir_in)
2038 WARN_ON_ONCE(1);
2039 else
2040 dwc2_hsotg_handle_outdone(hsotg, 0);
2041 }
2042 }
2043
2044 if (ints & DXEPINT_BACK2BACKSETUP)
2045 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2046
2047 if (dir_in && !hs_ep->isochronous) {
2048 /* not sure if this is important, but we'll clear it anyway */
2049 if (ints & DIEPMSK_INTKNTXFEMPMSK) {
2050 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2051 __func__, idx);
2052 }
2053
2054 /* this probably means something bad is happening */
2055 if (ints & DIEPMSK_INTKNEPMISMSK) {
2056 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2057 __func__, idx);
2058 }
2059
2060 /* FIFO has space or is empty (see GAHBCFG) */
2061 if (hsotg->dedicated_fifos &&
2062 ints & DIEPMSK_TXFIFOEMPTY) {
2063 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2064 __func__, idx);
2065 if (!using_dma(hsotg))
2066 dwc2_hsotg_trytx(hsotg, hs_ep);
2067 }
2068 }
2069}
2070
2071/**
2072 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2073 * @hsotg: The device state.
2074 *
2075 * Handle updating the device settings after the enumeration phase has
2076 * been completed.
2077 */
2078static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
2079{
2080 u32 dsts = dwc2_readl(hsotg->regs + DSTS);
2081 int ep0_mps = 0, ep_mps = 8;
2082
2083 /*
2084 * This should signal the finish of the enumeration phase
2085 * of the USB handshaking, so we should now know what rate
2086 * we connected at.
2087 */
2088
2089 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
2090
2091 /*
2092 * note, since we're limited by the size of transfer on EP0, and
2093 * it seems IN transfers must be a even number of packets we do
2094 * not advertise a 64byte MPS on EP0.
2095 */
2096
2097 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2098 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
2099 case DSTS_ENUMSPD_FS:
2100 case DSTS_ENUMSPD_FS48:
2101 hsotg->gadget.speed = USB_SPEED_FULL;
2102 ep0_mps = EP0_MPS_LIMIT;
2103 ep_mps = 1023;
2104 break;
2105
2106 case DSTS_ENUMSPD_HS:
2107 hsotg->gadget.speed = USB_SPEED_HIGH;
2108 ep0_mps = EP0_MPS_LIMIT;
2109 ep_mps = 1024;
2110 break;
2111
2112 case DSTS_ENUMSPD_LS:
2113 hsotg->gadget.speed = USB_SPEED_LOW;
2114 /*
2115 * note, we don't actually support LS in this driver at the
2116 * moment, and the documentation seems to imply that it isn't
2117 * supported by the PHYs on some of the devices.
2118 */
2119 break;
2120 }
2121 dev_info(hsotg->dev, "new device is %s\n",
2122 usb_speed_string(hsotg->gadget.speed));
2123
2124 /*
2125 * we should now know the maximum packet size for an
2126 * endpoint, so set the endpoints to a default value.
2127 */
2128
2129 if (ep0_mps) {
2130 int i;
2131 /* Initialize ep0 for both in and out directions */
2132 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1);
2133 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0);
2134 for (i = 1; i < hsotg->num_of_eps; i++) {
2135 if (hsotg->eps_in[i])
2136 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1);
2137 if (hsotg->eps_out[i])
2138 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0);
2139 }
2140 }
2141
2142 /* ensure after enumeration our EP0 is active */
2143
2144 dwc2_hsotg_enqueue_setup(hsotg);
2145
2146 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2147 dwc2_readl(hsotg->regs + DIEPCTL0),
2148 dwc2_readl(hsotg->regs + DOEPCTL0));
2149}
2150
2151/**
2152 * kill_all_requests - remove all requests from the endpoint's queue
2153 * @hsotg: The device state.
2154 * @ep: The endpoint the requests may be on.
2155 * @result: The result code to use.
2156 *
2157 * Go through the requests on the given endpoint and mark them
2158 * completed with the given result code.
2159 */
2160static void kill_all_requests(struct dwc2_hsotg *hsotg,
2161 struct dwc2_hsotg_ep *ep,
2162 int result)
2163{
2164 struct dwc2_hsotg_req *req, *treq;
2165 unsigned size;
2166
2167 ep->req = NULL;
2168
2169 list_for_each_entry_safe(req, treq, &ep->queue, queue)
2170 dwc2_hsotg_complete_request(hsotg, ep, req,
2171 result);
2172
2173 if (!hsotg->dedicated_fifos)
2174 return;
2175 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
2176 if (size < ep->fifo_size)
2177 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
2178}
2179
2180/**
2181 * dwc2_hsotg_disconnect - disconnect service
2182 * @hsotg: The device state.
2183 *
2184 * The device has been disconnected. Remove all current
2185 * transactions and signal the gadget driver that this
2186 * has happened.
2187 */
2188void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
2189{
2190 unsigned ep;
2191
2192 if (!hsotg->connected)
2193 return;
2194
2195 hsotg->connected = 0;
2196 hsotg->test_mode = 0;
2197
2198 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
2199 if (hsotg->eps_in[ep])
2200 kill_all_requests(hsotg, hsotg->eps_in[ep],
2201 -ESHUTDOWN);
2202 if (hsotg->eps_out[ep])
2203 kill_all_requests(hsotg, hsotg->eps_out[ep],
2204 -ESHUTDOWN);
2205 }
2206
2207 call_gadget(hsotg, disconnect);
2208 hsotg->lx_state = DWC2_L3;
2209}
2210
2211/**
2212 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2213 * @hsotg: The device state:
2214 * @periodic: True if this is a periodic FIFO interrupt
2215 */
2216static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
2217{
2218 struct dwc2_hsotg_ep *ep;
2219 int epno, ret;
2220
2221 /* look through for any more data to transmit */
2222 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2223 ep = index_to_ep(hsotg, epno, 1);
2224
2225 if (!ep)
2226 continue;
2227
2228 if (!ep->dir_in)
2229 continue;
2230
2231 if ((periodic && !ep->periodic) ||
2232 (!periodic && ep->periodic))
2233 continue;
2234
2235 ret = dwc2_hsotg_trytx(hsotg, ep);
2236 if (ret < 0)
2237 break;
2238 }
2239}
2240
2241/* IRQ flags which will trigger a retry around the IRQ loop */
2242#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2243 GINTSTS_PTXFEMP | \
2244 GINTSTS_RXFLVL)
2245
2246/**
2247 * dwc2_hsotg_core_init - issue softreset to the core
2248 * @hsotg: The device state
2249 *
2250 * Issue a soft reset to the core, and await the core finishing it.
2251 */
2252void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
2253 bool is_usb_reset)
2254{
2255 u32 intmsk;
2256 u32 val;
2257 u32 usbcfg;
2258
2259 /* Kill any ep0 requests as controller will be reinitialized */
2260 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
2261
2262 if (!is_usb_reset)
2263 if (dwc2_core_reset(hsotg))
2264 return;
2265
2266 /*
2267 * we must now enable ep0 ready for host detection and then
2268 * set configuration.
2269 */
2270
2271 /* keep other bits untouched (so e.g. forced modes are not lost) */
2272 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2273 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
2274 GUSBCFG_HNPCAP);
2275
2276 /* set the PLL on, remove the HNP/SRP and set the PHY */
2277 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
2278 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
2279 (val << GUSBCFG_USBTRDTIM_SHIFT);
2280 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2281
2282 dwc2_hsotg_init_fifo(hsotg);
2283
2284 if (!is_usb_reset)
2285 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2286
2287 dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
2288
2289 /* Clear any pending OTG interrupts */
2290 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
2291
2292 /* Clear any pending interrupts */
2293 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
2294 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
2295 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
2296 GINTSTS_USBRST | GINTSTS_RESETDET |
2297 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
2298 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
2299 GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
2300
2301 if (hsotg->core_params->external_id_pin_ctl <= 0)
2302 intmsk |= GINTSTS_CONIDSTSCHNG;
2303
2304 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
2305
2306 if (using_dma(hsotg))
2307 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
2308 (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT),
2309 hsotg->regs + GAHBCFG);
2310 else
2311 dwc2_writel(((hsotg->dedicated_fifos) ?
2312 (GAHBCFG_NP_TXF_EMP_LVL |
2313 GAHBCFG_P_TXF_EMP_LVL) : 0) |
2314 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
2315
2316 /*
2317 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2318 * when we have no data to transfer. Otherwise we get being flooded by
2319 * interrupts.
2320 */
2321
2322 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
2323 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
2324 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
2325 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2326 DIEPMSK_INTKNEPMISMSK,
2327 hsotg->regs + DIEPMSK);
2328
2329 /*
2330 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2331 * DMA mode we may need this.
2332 */
2333 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
2334 DIEPMSK_TIMEOUTMSK) : 0) |
2335 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
2336 DOEPMSK_SETUPMSK,
2337 hsotg->regs + DOEPMSK);
2338
2339 dwc2_writel(0, hsotg->regs + DAINTMSK);
2340
2341 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2342 dwc2_readl(hsotg->regs + DIEPCTL0),
2343 dwc2_readl(hsotg->regs + DOEPCTL0));
2344
2345 /* enable in and out endpoint interrupts */
2346 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
2347
2348 /*
2349 * Enable the RXFIFO when in slave mode, as this is how we collect
2350 * the data. In DMA mode, we get events from the FIFO but also
2351 * things we cannot process, so do not use it.
2352 */
2353 if (!using_dma(hsotg))
2354 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
2355
2356 /* Enable interrupts for EP0 in and out */
2357 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2358 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2359
2360 if (!is_usb_reset) {
2361 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2362 udelay(10); /* see openiboot */
2363 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2364 }
2365
2366 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
2367
2368 /*
2369 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2370 * writing to the EPCTL register..
2371 */
2372
2373 /* set to read 1 8byte packet */
2374 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2375 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
2376
2377 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2378 DXEPCTL_CNAK | DXEPCTL_EPENA |
2379 DXEPCTL_USBACTEP,
2380 hsotg->regs + DOEPCTL0);
2381
2382 /* enable, but don't activate EP0in */
2383 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2384 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
2385
2386 dwc2_hsotg_enqueue_setup(hsotg);
2387
2388 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2389 dwc2_readl(hsotg->regs + DIEPCTL0),
2390 dwc2_readl(hsotg->regs + DOEPCTL0));
2391
2392 /* clear global NAKs */
2393 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
2394 if (!is_usb_reset)
2395 val |= DCTL_SFTDISCON;
2396 __orr32(hsotg->regs + DCTL, val);
2397
2398 /* must be at-least 3ms to allow bus to see disconnect */
2399 mdelay(3);
2400
2401 hsotg->lx_state = DWC2_L0;
2402}
2403
2404static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
2405{
2406 /* set the soft-disconnect bit */
2407 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2408}
2409
2410void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
2411{
2412 /* remove the soft-disconnect and let's go */
2413 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2414}
2415
2416/**
2417 * dwc2_hsotg_irq - handle device interrupt
2418 * @irq: The IRQ number triggered
2419 * @pw: The pw value when registered the handler.
2420 */
2421static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
2422{
2423 struct dwc2_hsotg *hsotg = pw;
2424 int retry_count = 8;
2425 u32 gintsts;
2426 u32 gintmsk;
2427
2428 spin_lock(&hsotg->lock);
2429irq_retry:
2430 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
2431 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2432
2433 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2434 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2435
2436 gintsts &= gintmsk;
2437
2438 if (gintsts & GINTSTS_RESETDET) {
2439 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
2440
2441 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
2442
2443 /* This event must be used only if controller is suspended */
2444 if (hsotg->lx_state == DWC2_L2) {
2445 dwc2_exit_hibernation(hsotg, true);
2446 hsotg->lx_state = DWC2_L0;
2447 }
2448 }
2449
2450 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
2451
2452 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
2453 u32 connected = hsotg->connected;
2454
2455 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
2456 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2457 dwc2_readl(hsotg->regs + GNPTXSTS));
2458
2459 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
2460
2461 /* Report disconnection if it is not already done. */
2462 dwc2_hsotg_disconnect(hsotg);
2463
2464 if (usb_status & GOTGCTL_BSESVLD && connected)
2465 dwc2_hsotg_core_init_disconnected(hsotg, true);
2466 }
2467
2468 if (gintsts & GINTSTS_ENUMDONE) {
2469 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
2470
2471 dwc2_hsotg_irq_enumdone(hsotg);
2472 }
2473
2474 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
2475 u32 daint = dwc2_readl(hsotg->regs + DAINT);
2476 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
2477 u32 daint_out, daint_in;
2478 int ep;
2479
2480 daint &= daintmsk;
2481 daint_out = daint >> DAINT_OUTEP_SHIFT;
2482 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
2483
2484 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2485
2486 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
2487 ep++, daint_out >>= 1) {
2488 if (daint_out & 1)
2489 dwc2_hsotg_epint(hsotg, ep, 0);
2490 }
2491
2492 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
2493 ep++, daint_in >>= 1) {
2494 if (daint_in & 1)
2495 dwc2_hsotg_epint(hsotg, ep, 1);
2496 }
2497 }
2498
2499 /* check both FIFOs */
2500
2501 if (gintsts & GINTSTS_NPTXFEMP) {
2502 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2503
2504 /*
2505 * Disable the interrupt to stop it happening again
2506 * unless one of these endpoint routines decides that
2507 * it needs re-enabling
2508 */
2509
2510 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
2511 dwc2_hsotg_irq_fifoempty(hsotg, false);
2512 }
2513
2514 if (gintsts & GINTSTS_PTXFEMP) {
2515 dev_dbg(hsotg->dev, "PTxFEmp\n");
2516
2517 /* See note in GINTSTS_NPTxFEmp */
2518
2519 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
2520 dwc2_hsotg_irq_fifoempty(hsotg, true);
2521 }
2522
2523 if (gintsts & GINTSTS_RXFLVL) {
2524 /*
2525 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2526 * we need to retry dwc2_hsotg_handle_rx if this is still
2527 * set.
2528 */
2529
2530 dwc2_hsotg_handle_rx(hsotg);
2531 }
2532
2533 if (gintsts & GINTSTS_ERLYSUSP) {
2534 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2535 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
2536 }
2537
2538 /*
2539 * these next two seem to crop-up occasionally causing the core
2540 * to shutdown the USB transfer, so try clearing them and logging
2541 * the occurrence.
2542 */
2543
2544 if (gintsts & GINTSTS_GOUTNAKEFF) {
2545 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2546
2547 __orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK);
2548
2549 dwc2_hsotg_dump(hsotg);
2550 }
2551
2552 if (gintsts & GINTSTS_GINNAKEFF) {
2553 dev_info(hsotg->dev, "GINNakEff triggered\n");
2554
2555 __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
2556
2557 dwc2_hsotg_dump(hsotg);
2558 }
2559
2560 if (gintsts & GINTSTS_INCOMPL_SOIN) {
2561 u32 idx, epctl_reg;
2562 struct dwc2_hsotg_ep *hs_ep;
2563
2564 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOIN\n", __func__);
2565 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
2566 hs_ep = hsotg->eps_in[idx];
2567
2568 if (!hs_ep->isochronous || hs_ep->has_correct_parity)
2569 continue;
2570
2571 epctl_reg = DIEPCTL(idx);
2572 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
2573 }
2574 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS);
2575 }
2576
2577 if (gintsts & GINTSTS_INCOMPL_SOOUT) {
2578 u32 idx, epctl_reg;
2579 struct dwc2_hsotg_ep *hs_ep;
2580
2581 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
2582 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
2583 hs_ep = hsotg->eps_out[idx];
2584
2585 if (!hs_ep->isochronous || hs_ep->has_correct_parity)
2586 continue;
2587
2588 epctl_reg = DOEPCTL(idx);
2589 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
2590 }
2591 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS);
2592 }
2593
2594 /*
2595 * if we've had fifo events, we should try and go around the
2596 * loop again to see if there's any point in returning yet.
2597 */
2598
2599 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2600 goto irq_retry;
2601
2602 spin_unlock(&hsotg->lock);
2603
2604 return IRQ_HANDLED;
2605}
2606
2607/**
2608 * dwc2_hsotg_ep_enable - enable the given endpoint
2609 * @ep: The USB endpint to configure
2610 * @desc: The USB endpoint descriptor to configure with.
2611 *
2612 * This is called from the USB gadget code's usb_ep_enable().
2613 */
2614static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
2615 const struct usb_endpoint_descriptor *desc)
2616{
2617 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2618 struct dwc2_hsotg *hsotg = hs_ep->parent;
2619 unsigned long flags;
2620 unsigned int index = hs_ep->index;
2621 u32 epctrl_reg;
2622 u32 epctrl;
2623 u32 mps;
2624 unsigned int dir_in;
2625 unsigned int i, val, size;
2626 int ret = 0;
2627
2628 dev_dbg(hsotg->dev,
2629 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2630 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2631 desc->wMaxPacketSize, desc->bInterval);
2632
2633 /* not to be called for EP0 */
2634 WARN_ON(index == 0);
2635
2636 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2637 if (dir_in != hs_ep->dir_in) {
2638 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2639 return -EINVAL;
2640 }
2641
2642 mps = usb_endpoint_maxp(desc);
2643
2644 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
2645
2646 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2647 epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2648
2649 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2650 __func__, epctrl, epctrl_reg);
2651
2652 spin_lock_irqsave(&hsotg->lock, flags);
2653
2654 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
2655 epctrl |= DXEPCTL_MPS(mps);
2656
2657 /*
2658 * mark the endpoint as active, otherwise the core may ignore
2659 * transactions entirely for this endpoint
2660 */
2661 epctrl |= DXEPCTL_USBACTEP;
2662
2663 /*
2664 * set the NAK status on the endpoint, otherwise we might try and
2665 * do something with data that we've yet got a request to process
2666 * since the RXFIFO will take data for an endpoint even if the
2667 * size register hasn't been set.
2668 */
2669
2670 epctrl |= DXEPCTL_SNAK;
2671
2672 /* update the endpoint state */
2673 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in);
2674
2675 /* default, set to non-periodic */
2676 hs_ep->isochronous = 0;
2677 hs_ep->periodic = 0;
2678 hs_ep->halted = 0;
2679 hs_ep->interval = desc->bInterval;
2680 hs_ep->has_correct_parity = 0;
2681
2682 if (hs_ep->interval > 1 && hs_ep->mc > 1)
2683 dev_err(hsotg->dev, "MC > 1 when interval is not 1\n");
2684
2685 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2686 case USB_ENDPOINT_XFER_ISOC:
2687 epctrl |= DXEPCTL_EPTYPE_ISO;
2688 epctrl |= DXEPCTL_SETEVENFR;
2689 hs_ep->isochronous = 1;
2690 if (dir_in)
2691 hs_ep->periodic = 1;
2692 break;
2693
2694 case USB_ENDPOINT_XFER_BULK:
2695 epctrl |= DXEPCTL_EPTYPE_BULK;
2696 break;
2697
2698 case USB_ENDPOINT_XFER_INT:
2699 if (dir_in)
2700 hs_ep->periodic = 1;
2701
2702 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
2703 break;
2704
2705 case USB_ENDPOINT_XFER_CONTROL:
2706 epctrl |= DXEPCTL_EPTYPE_CONTROL;
2707 break;
2708 }
2709
2710 /* If fifo is already allocated for this ep */
2711 if (hs_ep->fifo_index) {
2712 size = hs_ep->ep.maxpacket * hs_ep->mc;
2713 /* If bigger fifo is required deallocate current one */
2714 if (size > hs_ep->fifo_size) {
2715 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
2716 hs_ep->fifo_index = 0;
2717 hs_ep->fifo_size = 0;
2718 }
2719 }
2720
2721 /*
2722 * if the hardware has dedicated fifos, we must give each IN EP
2723 * a unique tx-fifo even if it is non-periodic.
2724 */
2725 if (dir_in && hsotg->dedicated_fifos && !hs_ep->fifo_index) {
2726 u32 fifo_index = 0;
2727 u32 fifo_size = UINT_MAX;
2728 size = hs_ep->ep.maxpacket*hs_ep->mc;
2729 for (i = 1; i < hsotg->num_of_eps; ++i) {
2730 if (hsotg->fifo_map & (1<<i))
2731 continue;
2732 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
2733 val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
2734 if (val < size)
2735 continue;
2736 /* Search for smallest acceptable fifo */
2737 if (val < fifo_size) {
2738 fifo_size = val;
2739 fifo_index = i;
2740 }
2741 }
2742 if (!fifo_index) {
2743 dev_err(hsotg->dev,
2744 "%s: No suitable fifo found\n", __func__);
2745 ret = -ENOMEM;
2746 goto error;
2747 }
2748 hsotg->fifo_map |= 1 << fifo_index;
2749 epctrl |= DXEPCTL_TXFNUM(fifo_index);
2750 hs_ep->fifo_index = fifo_index;
2751 hs_ep->fifo_size = fifo_size;
2752 }
2753
2754 /* for non control endpoints, set PID to D0 */
2755 if (index)
2756 epctrl |= DXEPCTL_SETD0PID;
2757
2758 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2759 __func__, epctrl);
2760
2761 dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
2762 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2763 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
2764
2765 /* enable the endpoint interrupt */
2766 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2767
2768error:
2769 spin_unlock_irqrestore(&hsotg->lock, flags);
2770 return ret;
2771}
2772
2773/**
2774 * dwc2_hsotg_ep_disable - disable given endpoint
2775 * @ep: The endpoint to disable.
2776 */
2777static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
2778{
2779 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2780 struct dwc2_hsotg *hsotg = hs_ep->parent;
2781 int dir_in = hs_ep->dir_in;
2782 int index = hs_ep->index;
2783 unsigned long flags;
2784 u32 epctrl_reg;
2785 u32 ctrl;
2786
2787 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2788
2789 if (ep == &hsotg->eps_out[0]->ep) {
2790 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2791 return -EINVAL;
2792 }
2793
2794 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2795
2796 spin_lock_irqsave(&hsotg->lock, flags);
2797
2798 hsotg->fifo_map &= ~(1<<hs_ep->fifo_index);
2799 hs_ep->fifo_index = 0;
2800 hs_ep->fifo_size = 0;
2801
2802 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2803 ctrl &= ~DXEPCTL_EPENA;
2804 ctrl &= ~DXEPCTL_USBACTEP;
2805 ctrl |= DXEPCTL_SNAK;
2806
2807 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2808 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
2809
2810 /* disable endpoint interrupts */
2811 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2812
2813 /* terminate all requests with shutdown */
2814 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
2815
2816 spin_unlock_irqrestore(&hsotg->lock, flags);
2817 return 0;
2818}
2819
2820/**
2821 * on_list - check request is on the given endpoint
2822 * @ep: The endpoint to check.
2823 * @test: The request to test if it is on the endpoint.
2824 */
2825static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
2826{
2827 struct dwc2_hsotg_req *req, *treq;
2828
2829 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2830 if (req == test)
2831 return true;
2832 }
2833
2834 return false;
2835}
2836
2837static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg,
2838 u32 bit, u32 timeout)
2839{
2840 u32 i;
2841
2842 for (i = 0; i < timeout; i++) {
2843 if (dwc2_readl(hs_otg->regs + reg) & bit)
2844 return 0;
2845 udelay(1);
2846 }
2847
2848 return -ETIMEDOUT;
2849}
2850
2851static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2852 struct dwc2_hsotg_ep *hs_ep)
2853{
2854 u32 epctrl_reg;
2855 u32 epint_reg;
2856
2857 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
2858 DOEPCTL(hs_ep->index);
2859 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
2860 DOEPINT(hs_ep->index);
2861
2862 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
2863 hs_ep->name);
2864 if (hs_ep->dir_in) {
2865 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
2866 /* Wait for Nak effect */
2867 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
2868 DXEPINT_INEPNAKEFF, 100))
2869 dev_warn(hsotg->dev,
2870 "%s: timeout DIEPINT.NAKEFF\n", __func__);
2871 } else {
2872 /* Clear any pending nak effect interrupt */
2873 dwc2_writel(GINTSTS_GOUTNAKEFF, hsotg->regs + GINTSTS);
2874
2875 __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
2876
2877 /* Wait for global nak to take effect */
2878 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
2879 GINTSTS_GOUTNAKEFF, 100))
2880 dev_warn(hsotg->dev,
2881 "%s: timeout GINTSTS.GOUTNAKEFF\n", __func__);
2882 }
2883
2884 /* Disable ep */
2885 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
2886
2887 /* Wait for ep to be disabled */
2888 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
2889 dev_warn(hsotg->dev,
2890 "%s: timeout DOEPCTL.EPDisable\n", __func__);
2891
2892 if (hs_ep->dir_in) {
2893 if (hsotg->dedicated_fifos) {
2894 dwc2_writel(GRSTCTL_TXFNUM(hs_ep->fifo_index) |
2895 GRSTCTL_TXFFLSH, hsotg->regs + GRSTCTL);
2896 /* Wait for fifo flush */
2897 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
2898 GRSTCTL_TXFFLSH, 100))
2899 dev_warn(hsotg->dev,
2900 "%s: timeout flushing fifos\n",
2901 __func__);
2902 }
2903 /* TODO: Flush shared tx fifo */
2904 } else {
2905 /* Remove global NAKs */
2906 __bic32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
2907 }
2908}
2909
2910/**
2911 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
2912 * @ep: The endpoint to dequeue.
2913 * @req: The request to be removed from a queue.
2914 */
2915static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2916{
2917 struct dwc2_hsotg_req *hs_req = our_req(req);
2918 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2919 struct dwc2_hsotg *hs = hs_ep->parent;
2920 unsigned long flags;
2921
2922 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2923
2924 spin_lock_irqsave(&hs->lock, flags);
2925
2926 if (!on_list(hs_ep, hs_req)) {
2927 spin_unlock_irqrestore(&hs->lock, flags);
2928 return -EINVAL;
2929 }
2930
2931 /* Dequeue already started request */
2932 if (req == &hs_ep->req->req)
2933 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
2934
2935 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2936 spin_unlock_irqrestore(&hs->lock, flags);
2937
2938 return 0;
2939}
2940
2941/**
2942 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
2943 * @ep: The endpoint to set halt.
2944 * @value: Set or unset the halt.
2945 */
2946static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2947{
2948 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2949 struct dwc2_hsotg *hs = hs_ep->parent;
2950 int index = hs_ep->index;
2951 u32 epreg;
2952 u32 epctl;
2953 u32 xfertype;
2954
2955 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2956
2957 if (index == 0) {
2958 if (value)
2959 dwc2_hsotg_stall_ep0(hs);
2960 else
2961 dev_warn(hs->dev,
2962 "%s: can't clear halt on ep0\n", __func__);
2963 return 0;
2964 }
2965
2966 if (hs_ep->dir_in) {
2967 epreg = DIEPCTL(index);
2968 epctl = dwc2_readl(hs->regs + epreg);
2969
2970 if (value) {
2971 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
2972 if (epctl & DXEPCTL_EPENA)
2973 epctl |= DXEPCTL_EPDIS;
2974 } else {
2975 epctl &= ~DXEPCTL_STALL;
2976 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2977 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2978 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2979 epctl |= DXEPCTL_SETD0PID;
2980 }
2981 dwc2_writel(epctl, hs->regs + epreg);
2982 } else {
2983
2984 epreg = DOEPCTL(index);
2985 epctl = dwc2_readl(hs->regs + epreg);
2986
2987 if (value)
2988 epctl |= DXEPCTL_STALL;
2989 else {
2990 epctl &= ~DXEPCTL_STALL;
2991 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2992 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2993 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2994 epctl |= DXEPCTL_SETD0PID;
2995 }
2996 dwc2_writel(epctl, hs->regs + epreg);
2997 }
2998
2999 hs_ep->halted = value;
3000
3001 return 0;
3002}
3003
3004/**
3005 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
3006 * @ep: The endpoint to set halt.
3007 * @value: Set or unset the halt.
3008 */
3009static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
3010{
3011 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3012 struct dwc2_hsotg *hs = hs_ep->parent;
3013 unsigned long flags = 0;
3014 int ret = 0;
3015
3016 spin_lock_irqsave(&hs->lock, flags);
3017 ret = dwc2_hsotg_ep_sethalt(ep, value);
3018 spin_unlock_irqrestore(&hs->lock, flags);
3019
3020 return ret;
3021}
3022
3023static struct usb_ep_ops dwc2_hsotg_ep_ops = {
3024 .enable = dwc2_hsotg_ep_enable,
3025 .disable = dwc2_hsotg_ep_disable,
3026 .alloc_request = dwc2_hsotg_ep_alloc_request,
3027 .free_request = dwc2_hsotg_ep_free_request,
3028 .queue = dwc2_hsotg_ep_queue_lock,
3029 .dequeue = dwc2_hsotg_ep_dequeue,
3030 .set_halt = dwc2_hsotg_ep_sethalt_lock,
3031 /* note, don't believe we have any call for the fifo routines */
3032};
3033
3034/**
3035 * dwc2_hsotg_init - initalize the usb core
3036 * @hsotg: The driver state
3037 */
3038static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
3039{
3040 u32 trdtim;
3041 u32 usbcfg;
3042 /* unmask subset of endpoint interrupts */
3043
3044 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
3045 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
3046 hsotg->regs + DIEPMSK);
3047
3048 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
3049 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
3050 hsotg->regs + DOEPMSK);
3051
3052 dwc2_writel(0, hsotg->regs + DAINTMSK);
3053
3054 /* Be in disconnected state until gadget is registered */
3055 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3056
3057 /* setup fifos */
3058
3059 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3060 dwc2_readl(hsotg->regs + GRXFSIZ),
3061 dwc2_readl(hsotg->regs + GNPTXFSIZ));
3062
3063 dwc2_hsotg_init_fifo(hsotg);
3064
3065 /* keep other bits untouched (so e.g. forced modes are not lost) */
3066 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3067 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3068 GUSBCFG_HNPCAP);
3069
3070 /* set the PLL on, remove the HNP/SRP and set the PHY */
3071 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3072 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3073 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
3074 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
3075
3076 if (using_dma(hsotg))
3077 __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
3078}
3079
3080/**
3081 * dwc2_hsotg_udc_start - prepare the udc for work
3082 * @gadget: The usb gadget state
3083 * @driver: The usb gadget driver
3084 *
3085 * Perform initialization to prepare udc device and driver
3086 * to work.
3087 */
3088static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
3089 struct usb_gadget_driver *driver)
3090{
3091 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3092 unsigned long flags;
3093 int ret;
3094
3095 if (!hsotg) {
3096 pr_err("%s: called with no device\n", __func__);
3097 return -ENODEV;
3098 }
3099
3100 if (!driver) {
3101 dev_err(hsotg->dev, "%s: no driver\n", __func__);
3102 return -EINVAL;
3103 }
3104
3105 if (driver->max_speed < USB_SPEED_FULL)
3106 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
3107
3108 if (!driver->setup) {
3109 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
3110 return -EINVAL;
3111 }
3112
3113 WARN_ON(hsotg->driver);
3114
3115 driver->driver.bus = NULL;
3116 hsotg->driver = driver;
3117 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
3118 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3119
3120 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
3121 ret = dwc2_lowlevel_hw_enable(hsotg);
3122 if (ret)
3123 goto err;
3124 }
3125
3126 if (!IS_ERR_OR_NULL(hsotg->uphy))
3127 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
3128
3129 spin_lock_irqsave(&hsotg->lock, flags);
3130 dwc2_hsotg_init(hsotg);
3131 dwc2_hsotg_core_init_disconnected(hsotg, false);
3132 hsotg->enabled = 0;
3133 spin_unlock_irqrestore(&hsotg->lock, flags);
3134
3135 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
3136
3137 return 0;
3138
3139err:
3140 hsotg->driver = NULL;
3141 return ret;
3142}
3143
3144/**
3145 * dwc2_hsotg_udc_stop - stop the udc
3146 * @gadget: The usb gadget state
3147 * @driver: The usb gadget driver
3148 *
3149 * Stop udc hw block and stay tunned for future transmissions
3150 */
3151static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
3152{
3153 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3154 unsigned long flags = 0;
3155 int ep;
3156
3157 if (!hsotg)
3158 return -ENODEV;
3159
3160 /* all endpoints should be shutdown */
3161 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3162 if (hsotg->eps_in[ep])
3163 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3164 if (hsotg->eps_out[ep])
3165 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3166 }
3167
3168 spin_lock_irqsave(&hsotg->lock, flags);
3169
3170 hsotg->driver = NULL;
3171 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3172 hsotg->enabled = 0;
3173
3174 spin_unlock_irqrestore(&hsotg->lock, flags);
3175
3176 if (!IS_ERR_OR_NULL(hsotg->uphy))
3177 otg_set_peripheral(hsotg->uphy->otg, NULL);
3178
3179 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3180 dwc2_lowlevel_hw_disable(hsotg);
3181
3182 return 0;
3183}
3184
3185/**
3186 * dwc2_hsotg_gadget_getframe - read the frame number
3187 * @gadget: The usb gadget state
3188 *
3189 * Read the {micro} frame number
3190 */
3191static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
3192{
3193 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
3194}
3195
3196/**
3197 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
3198 * @gadget: The usb gadget state
3199 * @is_on: Current state of the USB PHY
3200 *
3201 * Connect/Disconnect the USB PHY pullup
3202 */
3203static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
3204{
3205 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3206 unsigned long flags = 0;
3207
3208 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
3209 hsotg->op_state);
3210
3211 /* Don't modify pullup state while in host mode */
3212 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
3213 hsotg->enabled = is_on;
3214 return 0;
3215 }
3216
3217 spin_lock_irqsave(&hsotg->lock, flags);
3218 if (is_on) {
3219 hsotg->enabled = 1;
3220 dwc2_hsotg_core_init_disconnected(hsotg, false);
3221 dwc2_hsotg_core_connect(hsotg);
3222 } else {
3223 dwc2_hsotg_core_disconnect(hsotg);
3224 dwc2_hsotg_disconnect(hsotg);
3225 hsotg->enabled = 0;
3226 }
3227
3228 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3229 spin_unlock_irqrestore(&hsotg->lock, flags);
3230
3231 return 0;
3232}
3233
3234static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
3235{
3236 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3237 unsigned long flags;
3238
3239 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
3240 spin_lock_irqsave(&hsotg->lock, flags);
3241
3242 /*
3243 * If controller is hibernated, it must exit from hibernation
3244 * before being initialized / de-initialized
3245 */
3246 if (hsotg->lx_state == DWC2_L2)
3247 dwc2_exit_hibernation(hsotg, false);
3248
3249 if (is_active) {
3250 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3251
3252 dwc2_hsotg_core_init_disconnected(hsotg, false);
3253 if (hsotg->enabled)
3254 dwc2_hsotg_core_connect(hsotg);
3255 } else {
3256 dwc2_hsotg_core_disconnect(hsotg);
3257 dwc2_hsotg_disconnect(hsotg);
3258 }
3259
3260 spin_unlock_irqrestore(&hsotg->lock, flags);
3261 return 0;
3262}
3263
3264/**
3265 * dwc2_hsotg_vbus_draw - report bMaxPower field
3266 * @gadget: The usb gadget state
3267 * @mA: Amount of current
3268 *
3269 * Report how much power the device may consume to the phy.
3270 */
3271static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA)
3272{
3273 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3274
3275 if (IS_ERR_OR_NULL(hsotg->uphy))
3276 return -ENOTSUPP;
3277 return usb_phy_set_power(hsotg->uphy, mA);
3278}
3279
3280static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
3281 .get_frame = dwc2_hsotg_gadget_getframe,
3282 .udc_start = dwc2_hsotg_udc_start,
3283 .udc_stop = dwc2_hsotg_udc_stop,
3284 .pullup = dwc2_hsotg_pullup,
3285 .vbus_session = dwc2_hsotg_vbus_session,
3286 .vbus_draw = dwc2_hsotg_vbus_draw,
3287};
3288
3289/**
3290 * dwc2_hsotg_initep - initialise a single endpoint
3291 * @hsotg: The device state.
3292 * @hs_ep: The endpoint to be initialised.
3293 * @epnum: The endpoint number
3294 *
3295 * Initialise the given endpoint (as part of the probe and device state
3296 * creation) to give to the gadget driver. Setup the endpoint name, any
3297 * direction information and other state that may be required.
3298 */
3299static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
3300 struct dwc2_hsotg_ep *hs_ep,
3301 int epnum,
3302 bool dir_in)
3303{
3304 char *dir;
3305
3306 if (epnum == 0)
3307 dir = "";
3308 else if (dir_in)
3309 dir = "in";
3310 else
3311 dir = "out";
3312
3313 hs_ep->dir_in = dir_in;
3314 hs_ep->index = epnum;
3315
3316 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3317
3318 INIT_LIST_HEAD(&hs_ep->queue);
3319 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3320
3321 /* add to the list of endpoints known by the gadget driver */
3322 if (epnum)
3323 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3324
3325 hs_ep->parent = hsotg;
3326 hs_ep->ep.name = hs_ep->name;
3327 usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT);
3328 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
3329
3330 if (epnum == 0) {
3331 hs_ep->ep.caps.type_control = true;
3332 } else {
3333 hs_ep->ep.caps.type_iso = true;
3334 hs_ep->ep.caps.type_bulk = true;
3335 hs_ep->ep.caps.type_int = true;
3336 }
3337
3338 if (dir_in)
3339 hs_ep->ep.caps.dir_in = true;
3340 else
3341 hs_ep->ep.caps.dir_out = true;
3342
3343 /*
3344 * if we're using dma, we need to set the next-endpoint pointer
3345 * to be something valid.
3346 */
3347
3348 if (using_dma(hsotg)) {
3349 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
3350 if (dir_in)
3351 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
3352 else
3353 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
3354 }
3355}
3356
3357/**
3358 * dwc2_hsotg_hw_cfg - read HW configuration registers
3359 * @param: The device state
3360 *
3361 * Read the USB core HW configuration registers
3362 */
3363static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
3364{
3365 u32 cfg;
3366 u32 ep_type;
3367 u32 i;
3368
3369 /* check hardware configuration */
3370
3371 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
3372
3373 /* Add ep0 */
3374 hsotg->num_of_eps++;
3375
3376 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct dwc2_hsotg_ep),
3377 GFP_KERNEL);
3378 if (!hsotg->eps_in[0])
3379 return -ENOMEM;
3380 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
3381 hsotg->eps_out[0] = hsotg->eps_in[0];
3382
3383 cfg = hsotg->hw_params.dev_ep_dirs;
3384 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
3385 ep_type = cfg & 3;
3386 /* Direction in or both */
3387 if (!(ep_type & 2)) {
3388 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
3389 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
3390 if (!hsotg->eps_in[i])
3391 return -ENOMEM;
3392 }
3393 /* Direction out or both */
3394 if (!(ep_type & 1)) {
3395 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
3396 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
3397 if (!hsotg->eps_out[i])
3398 return -ENOMEM;
3399 }
3400 }
3401
3402 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
3403 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
3404
3405 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3406 hsotg->num_of_eps,
3407 hsotg->dedicated_fifos ? "dedicated" : "shared",
3408 hsotg->fifo_mem);
3409 return 0;
3410}
3411
3412/**
3413 * dwc2_hsotg_dump - dump state of the udc
3414 * @param: The device state
3415 */
3416static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
3417{
3418#ifdef DEBUG
3419 struct device *dev = hsotg->dev;
3420 void __iomem *regs = hsotg->regs;
3421 u32 val;
3422 int idx;
3423
3424 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3425 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
3426 dwc2_readl(regs + DIEPMSK));
3427
3428 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
3429 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
3430
3431 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3432 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
3433
3434 /* show periodic fifo settings */
3435
3436 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3437 val = dwc2_readl(regs + DPTXFSIZN(idx));
3438 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3439 val >> FIFOSIZE_DEPTH_SHIFT,
3440 val & FIFOSIZE_STARTADDR_MASK);
3441 }
3442
3443 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
3444 dev_info(dev,
3445 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3446 dwc2_readl(regs + DIEPCTL(idx)),
3447 dwc2_readl(regs + DIEPTSIZ(idx)),
3448 dwc2_readl(regs + DIEPDMA(idx)));
3449
3450 val = dwc2_readl(regs + DOEPCTL(idx));
3451 dev_info(dev,
3452 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3453 idx, dwc2_readl(regs + DOEPCTL(idx)),
3454 dwc2_readl(regs + DOEPTSIZ(idx)),
3455 dwc2_readl(regs + DOEPDMA(idx)));
3456
3457 }
3458
3459 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3460 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
3461#endif
3462}
3463
3464#ifdef CONFIG_OF
3465static void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg)
3466{
3467 struct device_node *np = hsotg->dev->of_node;
3468 u32 len = 0;
3469 u32 i = 0;
3470
3471 /* Enable dma if requested in device tree */
3472 hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma");
3473
3474 /*
3475 * Register TX periodic fifo size per endpoint.
3476 * EP0 is excluded since it has no fifo configuration.
3477 */
3478 if (!of_find_property(np, "g-tx-fifo-size", &len))
3479 goto rx_fifo;
3480
3481 len /= sizeof(u32);
3482
3483 /* Read tx fifo sizes other than ep0 */
3484 if (of_property_read_u32_array(np, "g-tx-fifo-size",
3485 &hsotg->g_tx_fifo_sz[1], len))
3486 goto rx_fifo;
3487
3488 /* Add ep0 */
3489 len++;
3490
3491 /* Make remaining TX fifos unavailable */
3492 if (len < MAX_EPS_CHANNELS) {
3493 for (i = len; i < MAX_EPS_CHANNELS; i++)
3494 hsotg->g_tx_fifo_sz[i] = 0;
3495 }
3496
3497rx_fifo:
3498 /* Register RX fifo size */
3499 of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz);
3500
3501 /* Register NPTX fifo size */
3502 of_property_read_u32(np, "g-np-tx-fifo-size",
3503 &hsotg->g_np_g_tx_fifo_sz);
3504}
3505#else
3506static inline void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) { }
3507#endif
3508
3509/**
3510 * dwc2_gadget_init - init function for gadget
3511 * @dwc2: The data structure for the DWC2 driver.
3512 * @irq: The IRQ number for the controller.
3513 */
3514int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
3515{
3516 struct device *dev = hsotg->dev;
3517 int epnum;
3518 int ret;
3519 int i;
3520 u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE;
3521
3522 /* Initialize to legacy fifo configuration values */
3523 hsotg->g_rx_fifo_sz = 2048;
3524 hsotg->g_np_g_tx_fifo_sz = 1024;
3525 memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo));
3526 /* Device tree specific probe */
3527 dwc2_hsotg_of_probe(hsotg);
3528
3529 /* Check against largest possible value. */
3530 if (hsotg->g_np_g_tx_fifo_sz >
3531 hsotg->hw_params.dev_nperio_tx_fifo_size) {
3532 dev_warn(dev, "Specified GNPTXFDEP=%d > %d\n",
3533 hsotg->g_np_g_tx_fifo_sz,
3534 hsotg->hw_params.dev_nperio_tx_fifo_size);
3535 hsotg->g_np_g_tx_fifo_sz =
3536 hsotg->hw_params.dev_nperio_tx_fifo_size;
3537 }
3538
3539 /* Dump fifo information */
3540 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
3541 hsotg->g_np_g_tx_fifo_sz);
3542 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz);
3543 for (i = 0; i < MAX_EPS_CHANNELS; i++)
3544 dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i,
3545 hsotg->g_tx_fifo_sz[i]);
3546
3547 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3548 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
3549 hsotg->gadget.name = dev_name(dev);
3550 if (hsotg->dr_mode == USB_DR_MODE_OTG)
3551 hsotg->gadget.is_otg = 1;
3552 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3553 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3554
3555 ret = dwc2_hsotg_hw_cfg(hsotg);
3556 if (ret) {
3557 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
3558 return ret;
3559 }
3560
3561 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
3562 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3563 if (!hsotg->ctrl_buff) {
3564 dev_err(dev, "failed to allocate ctrl request buff\n");
3565 return -ENOMEM;
3566 }
3567
3568 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
3569 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3570 if (!hsotg->ep0_buff) {
3571 dev_err(dev, "failed to allocate ctrl reply buff\n");
3572 return -ENOMEM;
3573 }
3574
3575 ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED,
3576 dev_name(hsotg->dev), hsotg);
3577 if (ret < 0) {
3578 dev_err(dev, "cannot claim IRQ for gadget\n");
3579 return ret;
3580 }
3581
3582 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3583
3584 if (hsotg->num_of_eps == 0) {
3585 dev_err(dev, "wrong number of EPs (zero)\n");
3586 return -EINVAL;
3587 }
3588
3589 /* setup endpoint information */
3590
3591 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3592 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
3593
3594 /* allocate EP0 request */
3595
3596 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
3597 GFP_KERNEL);
3598 if (!hsotg->ctrl_req) {
3599 dev_err(dev, "failed to allocate ctrl req\n");
3600 return -ENOMEM;
3601 }
3602
3603 /* initialise the endpoints now the core has been initialised */
3604 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
3605 if (hsotg->eps_in[epnum])
3606 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
3607 epnum, 1);
3608 if (hsotg->eps_out[epnum])
3609 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
3610 epnum, 0);
3611 }
3612
3613 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
3614 if (ret)
3615 return ret;
3616
3617 dwc2_hsotg_dump(hsotg);
3618
3619 return 0;
3620}
3621
3622/**
3623 * dwc2_hsotg_remove - remove function for hsotg driver
3624 * @pdev: The platform information for the driver
3625 */
3626int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
3627{
3628 usb_del_gadget_udc(&hsotg->gadget);
3629
3630 return 0;
3631}
3632
3633int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
3634{
3635 unsigned long flags;
3636
3637 if (hsotg->lx_state != DWC2_L0)
3638 return 0;
3639
3640 if (hsotg->driver) {
3641 int ep;
3642
3643 dev_info(hsotg->dev, "suspending usb gadget %s\n",
3644 hsotg->driver->driver.name);
3645
3646 spin_lock_irqsave(&hsotg->lock, flags);
3647 if (hsotg->enabled)
3648 dwc2_hsotg_core_disconnect(hsotg);
3649 dwc2_hsotg_disconnect(hsotg);
3650 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3651 spin_unlock_irqrestore(&hsotg->lock, flags);
3652
3653 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3654 if (hsotg->eps_in[ep])
3655 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3656 if (hsotg->eps_out[ep])
3657 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3658 }
3659 }
3660
3661 return 0;
3662}
3663
3664int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
3665{
3666 unsigned long flags;
3667
3668 if (hsotg->lx_state == DWC2_L2)
3669 return 0;
3670
3671 if (hsotg->driver) {
3672 dev_info(hsotg->dev, "resuming usb gadget %s\n",
3673 hsotg->driver->driver.name);
3674
3675 spin_lock_irqsave(&hsotg->lock, flags);
3676 dwc2_hsotg_core_init_disconnected(hsotg, false);
3677 if (hsotg->enabled)
3678 dwc2_hsotg_core_connect(hsotg);
3679 spin_unlock_irqrestore(&hsotg->lock, flags);
3680 }
3681
3682 return 0;
3683}
3684
3685/**
3686 * dwc2_backup_device_registers() - Backup controller device registers.
3687 * When suspending usb bus, registers needs to be backuped
3688 * if controller power is disabled once suspended.
3689 *
3690 * @hsotg: Programming view of the DWC_otg controller
3691 */
3692int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
3693{
3694 struct dwc2_dregs_backup *dr;
3695 int i;
3696
3697 dev_dbg(hsotg->dev, "%s\n", __func__);
3698
3699 /* Backup dev regs */
3700 dr = &hsotg->dr_backup;
3701
3702 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
3703 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
3704 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3705 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
3706 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
3707
3708 for (i = 0; i < hsotg->num_of_eps; i++) {
3709 /* Backup IN EPs */
3710 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
3711
3712 /* Ensure DATA PID is correctly configured */
3713 if (dr->diepctl[i] & DXEPCTL_DPID)
3714 dr->diepctl[i] |= DXEPCTL_SETD1PID;
3715 else
3716 dr->diepctl[i] |= DXEPCTL_SETD0PID;
3717
3718 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
3719 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
3720
3721 /* Backup OUT EPs */
3722 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
3723
3724 /* Ensure DATA PID is correctly configured */
3725 if (dr->doepctl[i] & DXEPCTL_DPID)
3726 dr->doepctl[i] |= DXEPCTL_SETD1PID;
3727 else
3728 dr->doepctl[i] |= DXEPCTL_SETD0PID;
3729
3730 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
3731 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
3732 }
3733 dr->valid = true;
3734 return 0;
3735}
3736
3737/**
3738 * dwc2_restore_device_registers() - Restore controller device registers.
3739 * When resuming usb bus, device registers needs to be restored
3740 * if controller power were disabled.
3741 *
3742 * @hsotg: Programming view of the DWC_otg controller
3743 */
3744int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
3745{
3746 struct dwc2_dregs_backup *dr;
3747 u32 dctl;
3748 int i;
3749
3750 dev_dbg(hsotg->dev, "%s\n", __func__);
3751
3752 /* Restore dev regs */
3753 dr = &hsotg->dr_backup;
3754 if (!dr->valid) {
3755 dev_err(hsotg->dev, "%s: no device registers to restore\n",
3756 __func__);
3757 return -EINVAL;
3758 }
3759 dr->valid = false;
3760
3761 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
3762 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
3763 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
3764 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
3765 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
3766
3767 for (i = 0; i < hsotg->num_of_eps; i++) {
3768 /* Restore IN EPs */
3769 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
3770 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
3771 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
3772
3773 /* Restore OUT EPs */
3774 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
3775 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
3776 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
3777 }
3778
3779 /* Set the Power-On Programming done bit */
3780 dctl = dwc2_readl(hsotg->regs + DCTL);
3781 dctl |= DCTL_PWRONPRGDONE;
3782 dwc2_writel(dctl, hsotg->regs + DCTL);
3783
3784 return 0;
3785}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * S3C USB2.0 High-speed / OtG driver
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/spinlock.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
20#include <linux/mutex.h>
21#include <linux/seq_file.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25#include <linux/of_platform.h>
26
27#include <linux/usb/ch9.h>
28#include <linux/usb/gadget.h>
29#include <linux/usb/phy.h>
30#include <linux/usb/composite.h>
31
32
33#include "core.h"
34#include "hw.h"
35
36/* conversion functions */
37static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
38{
39 return container_of(req, struct dwc2_hsotg_req, req);
40}
41
42static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
43{
44 return container_of(ep, struct dwc2_hsotg_ep, ep);
45}
46
47static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
48{
49 return container_of(gadget, struct dwc2_hsotg, gadget);
50}
51
52static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
53{
54 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
55}
56
57static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
58{
59 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
60}
61
62static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
63 u32 ep_index, u32 dir_in)
64{
65 if (dir_in)
66 return hsotg->eps_in[ep_index];
67 else
68 return hsotg->eps_out[ep_index];
69}
70
71/* forward declaration of functions */
72static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
73
74/**
75 * using_dma - return the DMA status of the driver.
76 * @hsotg: The driver state.
77 *
78 * Return true if we're using DMA.
79 *
80 * Currently, we have the DMA support code worked into everywhere
81 * that needs it, but the AMBA DMA implementation in the hardware can
82 * only DMA from 32bit aligned addresses. This means that gadgets such
83 * as the CDC Ethernet cannot work as they often pass packets which are
84 * not 32bit aligned.
85 *
86 * Unfortunately the choice to use DMA or not is global to the controller
87 * and seems to be only settable when the controller is being put through
88 * a core reset. This means we either need to fix the gadgets to take
89 * account of DMA alignment, or add bounce buffers (yuerk).
90 *
91 * g_using_dma is set depending on dts flag.
92 */
93static inline bool using_dma(struct dwc2_hsotg *hsotg)
94{
95 return hsotg->params.g_dma;
96}
97
98/*
99 * using_desc_dma - return the descriptor DMA status of the driver.
100 * @hsotg: The driver state.
101 *
102 * Return true if we're using descriptor DMA.
103 */
104static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
105{
106 return hsotg->params.g_dma_desc;
107}
108
109/**
110 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
111 * @hs_ep: The endpoint
112 *
113 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
114 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
115 */
116static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
117{
118 hs_ep->target_frame += hs_ep->interval;
119 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
120 hs_ep->frame_overrun = true;
121 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
122 } else {
123 hs_ep->frame_overrun = false;
124 }
125}
126
127/**
128 * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
129 * by one.
130 * @hs_ep: The endpoint.
131 *
132 * This function used in service interval based scheduling flow to calculate
133 * descriptor frame number filed value. For service interval mode frame
134 * number in descriptor should point to last (u)frame in the interval.
135 *
136 */
137static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
138{
139 if (hs_ep->target_frame)
140 hs_ep->target_frame -= 1;
141 else
142 hs_ep->target_frame = DSTS_SOFFN_LIMIT;
143}
144
145/**
146 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
147 * @hsotg: The device state
148 * @ints: A bitmask of the interrupts to enable
149 */
150static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
151{
152 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
153 u32 new_gsintmsk;
154
155 new_gsintmsk = gsintmsk | ints;
156
157 if (new_gsintmsk != gsintmsk) {
158 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
159 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
160 }
161}
162
163/**
164 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
165 * @hsotg: The device state
166 * @ints: A bitmask of the interrupts to enable
167 */
168static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
169{
170 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
171 u32 new_gsintmsk;
172
173 new_gsintmsk = gsintmsk & ~ints;
174
175 if (new_gsintmsk != gsintmsk)
176 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
177}
178
179/**
180 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
181 * @hsotg: The device state
182 * @ep: The endpoint index
183 * @dir_in: True if direction is in.
184 * @en: The enable value, true to enable
185 *
186 * Set or clear the mask for an individual endpoint's interrupt
187 * request.
188 */
189static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
190 unsigned int ep, unsigned int dir_in,
191 unsigned int en)
192{
193 unsigned long flags;
194 u32 bit = 1 << ep;
195 u32 daint;
196
197 if (!dir_in)
198 bit <<= 16;
199
200 local_irq_save(flags);
201 daint = dwc2_readl(hsotg, DAINTMSK);
202 if (en)
203 daint |= bit;
204 else
205 daint &= ~bit;
206 dwc2_writel(hsotg, daint, DAINTMSK);
207 local_irq_restore(flags);
208}
209
210/**
211 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
212 *
213 * @hsotg: Programming view of the DWC_otg controller
214 */
215int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
216{
217 if (hsotg->hw_params.en_multiple_tx_fifo)
218 /* In dedicated FIFO mode we need count of IN EPs */
219 return hsotg->hw_params.num_dev_in_eps;
220 else
221 /* In shared FIFO mode we need count of Periodic IN EPs */
222 return hsotg->hw_params.num_dev_perio_in_ep;
223}
224
225/**
226 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
227 * device mode TX FIFOs
228 *
229 * @hsotg: Programming view of the DWC_otg controller
230 */
231int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
232{
233 int addr;
234 int tx_addr_max;
235 u32 np_tx_fifo_size;
236
237 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
238 hsotg->params.g_np_tx_fifo_size);
239
240 /* Get Endpoint Info Control block size in DWORDs. */
241 tx_addr_max = hsotg->hw_params.total_fifo_size;
242
243 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
244 if (tx_addr_max <= addr)
245 return 0;
246
247 return tx_addr_max - addr;
248}
249
250/**
251 * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
252 *
253 * @hsotg: Programming view of the DWC_otg controller
254 *
255 */
256static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
257{
258 u32 gintsts2;
259 u32 gintmsk2;
260
261 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
262 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
263 gintsts2 &= gintmsk2;
264
265 if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
266 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
267 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
268 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
269 }
270}
271
272/**
273 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
274 * TX FIFOs
275 *
276 * @hsotg: Programming view of the DWC_otg controller
277 */
278int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
279{
280 int tx_fifo_count;
281 int tx_fifo_depth;
282
283 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
284
285 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
286
287 if (!tx_fifo_count)
288 return tx_fifo_depth;
289 else
290 return tx_fifo_depth / tx_fifo_count;
291}
292
293/**
294 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
295 * @hsotg: The device instance.
296 */
297static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
298{
299 unsigned int ep;
300 unsigned int addr;
301 int timeout;
302
303 u32 val;
304 u32 *txfsz = hsotg->params.g_tx_fifo_size;
305
306 /* Reset fifo map if not correctly cleared during previous session */
307 WARN_ON(hsotg->fifo_map);
308 hsotg->fifo_map = 0;
309
310 /* set RX/NPTX FIFO sizes */
311 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
312 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
313 FIFOSIZE_STARTADDR_SHIFT) |
314 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
315 GNPTXFSIZ);
316
317 /*
318 * arange all the rest of the TX FIFOs, as some versions of this
319 * block have overlapping default addresses. This also ensures
320 * that if the settings have been changed, then they are set to
321 * known values.
322 */
323
324 /* start at the end of the GNPTXFSIZ, rounded up */
325 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
326
327 /*
328 * Configure fifos sizes from provided configuration and assign
329 * them to endpoints dynamically according to maxpacket size value of
330 * given endpoint.
331 */
332 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
333 if (!txfsz[ep])
334 continue;
335 val = addr;
336 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
337 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
338 "insufficient fifo memory");
339 addr += txfsz[ep];
340
341 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
342 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
343 }
344
345 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
346 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
347 GDFIFOCFG);
348 /*
349 * according to p428 of the design guide, we need to ensure that
350 * all fifos are flushed before continuing
351 */
352
353 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
354 GRSTCTL_RXFFLSH, GRSTCTL);
355
356 /* wait until the fifos are both flushed */
357 timeout = 100;
358 while (1) {
359 val = dwc2_readl(hsotg, GRSTCTL);
360
361 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
362 break;
363
364 if (--timeout == 0) {
365 dev_err(hsotg->dev,
366 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
367 __func__, val);
368 break;
369 }
370
371 udelay(1);
372 }
373
374 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
375}
376
377/**
378 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
379 * @ep: USB endpoint to allocate request for.
380 * @flags: Allocation flags
381 *
382 * Allocate a new USB request structure appropriate for the specified endpoint
383 */
384static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
385 gfp_t flags)
386{
387 struct dwc2_hsotg_req *req;
388
389 req = kzalloc(sizeof(*req), flags);
390 if (!req)
391 return NULL;
392
393 INIT_LIST_HEAD(&req->queue);
394
395 return &req->req;
396}
397
398/**
399 * is_ep_periodic - return true if the endpoint is in periodic mode.
400 * @hs_ep: The endpoint to query.
401 *
402 * Returns true if the endpoint is in periodic mode, meaning it is being
403 * used for an Interrupt or ISO transfer.
404 */
405static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
406{
407 return hs_ep->periodic;
408}
409
410/**
411 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
412 * @hsotg: The device state.
413 * @hs_ep: The endpoint for the request
414 * @hs_req: The request being processed.
415 *
416 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
417 * of a request to ensure the buffer is ready for access by the caller.
418 */
419static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
420 struct dwc2_hsotg_ep *hs_ep,
421 struct dwc2_hsotg_req *hs_req)
422{
423 struct usb_request *req = &hs_req->req;
424
425 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
426}
427
428/*
429 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
430 * for Control endpoint
431 * @hsotg: The device state.
432 *
433 * This function will allocate 4 descriptor chains for EP 0: 2 for
434 * Setup stage, per one for IN and OUT data/status transactions.
435 */
436static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
437{
438 hsotg->setup_desc[0] =
439 dmam_alloc_coherent(hsotg->dev,
440 sizeof(struct dwc2_dma_desc),
441 &hsotg->setup_desc_dma[0],
442 GFP_KERNEL);
443 if (!hsotg->setup_desc[0])
444 goto fail;
445
446 hsotg->setup_desc[1] =
447 dmam_alloc_coherent(hsotg->dev,
448 sizeof(struct dwc2_dma_desc),
449 &hsotg->setup_desc_dma[1],
450 GFP_KERNEL);
451 if (!hsotg->setup_desc[1])
452 goto fail;
453
454 hsotg->ctrl_in_desc =
455 dmam_alloc_coherent(hsotg->dev,
456 sizeof(struct dwc2_dma_desc),
457 &hsotg->ctrl_in_desc_dma,
458 GFP_KERNEL);
459 if (!hsotg->ctrl_in_desc)
460 goto fail;
461
462 hsotg->ctrl_out_desc =
463 dmam_alloc_coherent(hsotg->dev,
464 sizeof(struct dwc2_dma_desc),
465 &hsotg->ctrl_out_desc_dma,
466 GFP_KERNEL);
467 if (!hsotg->ctrl_out_desc)
468 goto fail;
469
470 return 0;
471
472fail:
473 return -ENOMEM;
474}
475
476/**
477 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
478 * @hsotg: The controller state.
479 * @hs_ep: The endpoint we're going to write for.
480 * @hs_req: The request to write data for.
481 *
482 * This is called when the TxFIFO has some space in it to hold a new
483 * transmission and we have something to give it. The actual setup of
484 * the data size is done elsewhere, so all we have to do is to actually
485 * write the data.
486 *
487 * The return value is zero if there is more space (or nothing was done)
488 * otherwise -ENOSPC is returned if the FIFO space was used up.
489 *
490 * This routine is only needed for PIO
491 */
492static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
493 struct dwc2_hsotg_ep *hs_ep,
494 struct dwc2_hsotg_req *hs_req)
495{
496 bool periodic = is_ep_periodic(hs_ep);
497 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
498 int buf_pos = hs_req->req.actual;
499 int to_write = hs_ep->size_loaded;
500 void *data;
501 int can_write;
502 int pkt_round;
503 int max_transfer;
504
505 to_write -= (buf_pos - hs_ep->last_load);
506
507 /* if there's nothing to write, get out early */
508 if (to_write == 0)
509 return 0;
510
511 if (periodic && !hsotg->dedicated_fifos) {
512 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
513 int size_left;
514 int size_done;
515
516 /*
517 * work out how much data was loaded so we can calculate
518 * how much data is left in the fifo.
519 */
520
521 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
522
523 /*
524 * if shared fifo, we cannot write anything until the
525 * previous data has been completely sent.
526 */
527 if (hs_ep->fifo_load != 0) {
528 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
529 return -ENOSPC;
530 }
531
532 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
533 __func__, size_left,
534 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
535
536 /* how much of the data has moved */
537 size_done = hs_ep->size_loaded - size_left;
538
539 /* how much data is left in the fifo */
540 can_write = hs_ep->fifo_load - size_done;
541 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
542 __func__, can_write);
543
544 can_write = hs_ep->fifo_size - can_write;
545 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
546 __func__, can_write);
547
548 if (can_write <= 0) {
549 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
550 return -ENOSPC;
551 }
552 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
553 can_write = dwc2_readl(hsotg,
554 DTXFSTS(hs_ep->fifo_index));
555
556 can_write &= 0xffff;
557 can_write *= 4;
558 } else {
559 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
560 dev_dbg(hsotg->dev,
561 "%s: no queue slots available (0x%08x)\n",
562 __func__, gnptxsts);
563
564 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
565 return -ENOSPC;
566 }
567
568 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
569 can_write *= 4; /* fifo size is in 32bit quantities. */
570 }
571
572 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
573
574 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
575 __func__, gnptxsts, can_write, to_write, max_transfer);
576
577 /*
578 * limit to 512 bytes of data, it seems at least on the non-periodic
579 * FIFO, requests of >512 cause the endpoint to get stuck with a
580 * fragment of the end of the transfer in it.
581 */
582 if (can_write > 512 && !periodic)
583 can_write = 512;
584
585 /*
586 * limit the write to one max-packet size worth of data, but allow
587 * the transfer to return that it did not run out of fifo space
588 * doing it.
589 */
590 if (to_write > max_transfer) {
591 to_write = max_transfer;
592
593 /* it's needed only when we do not use dedicated fifos */
594 if (!hsotg->dedicated_fifos)
595 dwc2_hsotg_en_gsint(hsotg,
596 periodic ? GINTSTS_PTXFEMP :
597 GINTSTS_NPTXFEMP);
598 }
599
600 /* see if we can write data */
601
602 if (to_write > can_write) {
603 to_write = can_write;
604 pkt_round = to_write % max_transfer;
605
606 /*
607 * Round the write down to an
608 * exact number of packets.
609 *
610 * Note, we do not currently check to see if we can ever
611 * write a full packet or not to the FIFO.
612 */
613
614 if (pkt_round)
615 to_write -= pkt_round;
616
617 /*
618 * enable correct FIFO interrupt to alert us when there
619 * is more room left.
620 */
621
622 /* it's needed only when we do not use dedicated fifos */
623 if (!hsotg->dedicated_fifos)
624 dwc2_hsotg_en_gsint(hsotg,
625 periodic ? GINTSTS_PTXFEMP :
626 GINTSTS_NPTXFEMP);
627 }
628
629 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
630 to_write, hs_req->req.length, can_write, buf_pos);
631
632 if (to_write <= 0)
633 return -ENOSPC;
634
635 hs_req->req.actual = buf_pos + to_write;
636 hs_ep->total_data += to_write;
637
638 if (periodic)
639 hs_ep->fifo_load += to_write;
640
641 to_write = DIV_ROUND_UP(to_write, 4);
642 data = hs_req->req.buf + buf_pos;
643
644 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
645
646 return (to_write >= can_write) ? -ENOSPC : 0;
647}
648
649/**
650 * get_ep_limit - get the maximum data legnth for this endpoint
651 * @hs_ep: The endpoint
652 *
653 * Return the maximum data that can be queued in one go on a given endpoint
654 * so that transfers that are too long can be split.
655 */
656static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
657{
658 int index = hs_ep->index;
659 unsigned int maxsize;
660 unsigned int maxpkt;
661
662 if (index != 0) {
663 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
664 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
665 } else {
666 maxsize = 64 + 64;
667 if (hs_ep->dir_in)
668 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
669 else
670 maxpkt = 2;
671 }
672
673 /* we made the constant loading easier above by using +1 */
674 maxpkt--;
675 maxsize--;
676
677 /*
678 * constrain by packet count if maxpkts*pktsize is greater
679 * than the length register size.
680 */
681
682 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
683 maxsize = maxpkt * hs_ep->ep.maxpacket;
684
685 return maxsize;
686}
687
688/**
689 * dwc2_hsotg_read_frameno - read current frame number
690 * @hsotg: The device instance
691 *
692 * Return the current frame number
693 */
694static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
695{
696 u32 dsts;
697
698 dsts = dwc2_readl(hsotg, DSTS);
699 dsts &= DSTS_SOFFN_MASK;
700 dsts >>= DSTS_SOFFN_SHIFT;
701
702 return dsts;
703}
704
705/**
706 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
707 * DMA descriptor chain prepared for specific endpoint
708 * @hs_ep: The endpoint
709 *
710 * Return the maximum data that can be queued in one go on a given endpoint
711 * depending on its descriptor chain capacity so that transfers that
712 * are too long can be split.
713 */
714static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
715{
716 int is_isoc = hs_ep->isochronous;
717 unsigned int maxsize;
718
719 if (is_isoc)
720 maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
721 DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
722 MAX_DMA_DESC_NUM_HS_ISOC;
723 else
724 maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
725
726 return maxsize;
727}
728
729/*
730 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
731 * @hs_ep: The endpoint
732 * @mask: RX/TX bytes mask to be defined
733 *
734 * Returns maximum data payload for one descriptor after analyzing endpoint
735 * characteristics.
736 * DMA descriptor transfer bytes limit depends on EP type:
737 * Control out - MPS,
738 * Isochronous - descriptor rx/tx bytes bitfield limit,
739 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
740 * have concatenations from various descriptors within one packet.
741 *
742 * Selects corresponding mask for RX/TX bytes as well.
743 */
744static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
745{
746 u32 mps = hs_ep->ep.maxpacket;
747 int dir_in = hs_ep->dir_in;
748 u32 desc_size = 0;
749
750 if (!hs_ep->index && !dir_in) {
751 desc_size = mps;
752 *mask = DEV_DMA_NBYTES_MASK;
753 } else if (hs_ep->isochronous) {
754 if (dir_in) {
755 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
756 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
757 } else {
758 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
759 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
760 }
761 } else {
762 desc_size = DEV_DMA_NBYTES_LIMIT;
763 *mask = DEV_DMA_NBYTES_MASK;
764
765 /* Round down desc_size to be mps multiple */
766 desc_size -= desc_size % mps;
767 }
768
769 return desc_size;
770}
771
772static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
773 struct dwc2_dma_desc **desc,
774 dma_addr_t dma_buff,
775 unsigned int len,
776 bool true_last)
777{
778 int dir_in = hs_ep->dir_in;
779 u32 mps = hs_ep->ep.maxpacket;
780 u32 maxsize = 0;
781 u32 offset = 0;
782 u32 mask = 0;
783 int i;
784
785 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
786
787 hs_ep->desc_count = (len / maxsize) +
788 ((len % maxsize) ? 1 : 0);
789 if (len == 0)
790 hs_ep->desc_count = 1;
791
792 for (i = 0; i < hs_ep->desc_count; ++i) {
793 (*desc)->status = 0;
794 (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
795 << DEV_DMA_BUFF_STS_SHIFT);
796
797 if (len > maxsize) {
798 if (!hs_ep->index && !dir_in)
799 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
800
801 (*desc)->status |=
802 maxsize << DEV_DMA_NBYTES_SHIFT & mask;
803 (*desc)->buf = dma_buff + offset;
804
805 len -= maxsize;
806 offset += maxsize;
807 } else {
808 if (true_last)
809 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
810
811 if (dir_in)
812 (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
813 ((hs_ep->send_zlp && true_last) ?
814 DEV_DMA_SHORT : 0);
815
816 (*desc)->status |=
817 len << DEV_DMA_NBYTES_SHIFT & mask;
818 (*desc)->buf = dma_buff + offset;
819 }
820
821 (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
822 (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
823 << DEV_DMA_BUFF_STS_SHIFT);
824 (*desc)++;
825 }
826}
827
828/*
829 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
830 * @hs_ep: The endpoint
831 * @ureq: Request to transfer
832 * @offset: offset in bytes
833 * @len: Length of the transfer
834 *
835 * This function will iterate over descriptor chain and fill its entries
836 * with corresponding information based on transfer data.
837 */
838static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
839 dma_addr_t dma_buff,
840 unsigned int len)
841{
842 struct usb_request *ureq = NULL;
843 struct dwc2_dma_desc *desc = hs_ep->desc_list;
844 struct scatterlist *sg;
845 int i;
846 u8 desc_count = 0;
847
848 if (hs_ep->req)
849 ureq = &hs_ep->req->req;
850
851 /* non-DMA sg buffer */
852 if (!ureq || !ureq->num_sgs) {
853 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
854 dma_buff, len, true);
855 return;
856 }
857
858 /* DMA sg buffer */
859 for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
860 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
861 sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
862 sg_is_last(sg));
863 desc_count += hs_ep->desc_count;
864 }
865
866 hs_ep->desc_count = desc_count;
867}
868
869/*
870 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
871 * @hs_ep: The isochronous endpoint.
872 * @dma_buff: usb requests dma buffer.
873 * @len: usb request transfer length.
874 *
875 * Fills next free descriptor with the data of the arrived usb request,
876 * frame info, sets Last and IOC bits increments next_desc. If filled
877 * descriptor is not the first one, removes L bit from the previous descriptor
878 * status.
879 */
880static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
881 dma_addr_t dma_buff, unsigned int len)
882{
883 struct dwc2_dma_desc *desc;
884 struct dwc2_hsotg *hsotg = hs_ep->parent;
885 u32 index;
886 u32 mask = 0;
887 u8 pid = 0;
888
889 dwc2_gadget_get_desc_params(hs_ep, &mask);
890
891 index = hs_ep->next_desc;
892 desc = &hs_ep->desc_list[index];
893
894 /* Check if descriptor chain full */
895 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
896 DEV_DMA_BUFF_STS_HREADY) {
897 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
898 return 1;
899 }
900
901 /* Clear L bit of previous desc if more than one entries in the chain */
902 if (hs_ep->next_desc)
903 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
904
905 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
906 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
907
908 desc->status = 0;
909 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
910
911 desc->buf = dma_buff;
912 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
913 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
914
915 if (hs_ep->dir_in) {
916 if (len)
917 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
918 else
919 pid = 1;
920 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
921 DEV_DMA_ISOC_PID_MASK) |
922 ((len % hs_ep->ep.maxpacket) ?
923 DEV_DMA_SHORT : 0) |
924 ((hs_ep->target_frame <<
925 DEV_DMA_ISOC_FRNUM_SHIFT) &
926 DEV_DMA_ISOC_FRNUM_MASK);
927 }
928
929 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
930 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
931
932 /* Increment frame number by interval for IN */
933 if (hs_ep->dir_in)
934 dwc2_gadget_incr_frame_num(hs_ep);
935
936 /* Update index of last configured entry in the chain */
937 hs_ep->next_desc++;
938 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
939 hs_ep->next_desc = 0;
940
941 return 0;
942}
943
944/*
945 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
946 * @hs_ep: The isochronous endpoint.
947 *
948 * Prepare descriptor chain for isochronous endpoints. Afterwards
949 * write DMA address to HW and enable the endpoint.
950 */
951static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
952{
953 struct dwc2_hsotg *hsotg = hs_ep->parent;
954 struct dwc2_hsotg_req *hs_req, *treq;
955 int index = hs_ep->index;
956 int ret;
957 int i;
958 u32 dma_reg;
959 u32 depctl;
960 u32 ctrl;
961 struct dwc2_dma_desc *desc;
962
963 if (list_empty(&hs_ep->queue)) {
964 hs_ep->target_frame = TARGET_FRAME_INITIAL;
965 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
966 return;
967 }
968
969 /* Initialize descriptor chain by Host Busy status */
970 for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
971 desc = &hs_ep->desc_list[i];
972 desc->status = 0;
973 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
974 << DEV_DMA_BUFF_STS_SHIFT);
975 }
976
977 hs_ep->next_desc = 0;
978 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
979 dma_addr_t dma_addr = hs_req->req.dma;
980
981 if (hs_req->req.num_sgs) {
982 WARN_ON(hs_req->req.num_sgs > 1);
983 dma_addr = sg_dma_address(hs_req->req.sg);
984 }
985 ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
986 hs_req->req.length);
987 if (ret)
988 break;
989 }
990
991 hs_ep->compl_desc = 0;
992 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
993 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
994
995 /* write descriptor chain address to control register */
996 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
997
998 ctrl = dwc2_readl(hsotg, depctl);
999 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
1000 dwc2_writel(hsotg, ctrl, depctl);
1001}
1002
1003/**
1004 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
1005 * @hsotg: The controller state.
1006 * @hs_ep: The endpoint to process a request for
1007 * @hs_req: The request to start.
1008 * @continuing: True if we are doing more for the current request.
1009 *
1010 * Start the given request running by setting the endpoint registers
1011 * appropriately, and writing any data to the FIFOs.
1012 */
1013static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1014 struct dwc2_hsotg_ep *hs_ep,
1015 struct dwc2_hsotg_req *hs_req,
1016 bool continuing)
1017{
1018 struct usb_request *ureq = &hs_req->req;
1019 int index = hs_ep->index;
1020 int dir_in = hs_ep->dir_in;
1021 u32 epctrl_reg;
1022 u32 epsize_reg;
1023 u32 epsize;
1024 u32 ctrl;
1025 unsigned int length;
1026 unsigned int packets;
1027 unsigned int maxreq;
1028 unsigned int dma_reg;
1029
1030 if (index != 0) {
1031 if (hs_ep->req && !continuing) {
1032 dev_err(hsotg->dev, "%s: active request\n", __func__);
1033 WARN_ON(1);
1034 return;
1035 } else if (hs_ep->req != hs_req && continuing) {
1036 dev_err(hsotg->dev,
1037 "%s: continue different req\n", __func__);
1038 WARN_ON(1);
1039 return;
1040 }
1041 }
1042
1043 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1044 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1045 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1046
1047 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1048 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1049 hs_ep->dir_in ? "in" : "out");
1050
1051 /* If endpoint is stalled, we will restart request later */
1052 ctrl = dwc2_readl(hsotg, epctrl_reg);
1053
1054 if (index && ctrl & DXEPCTL_STALL) {
1055 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1056 return;
1057 }
1058
1059 length = ureq->length - ureq->actual;
1060 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1061 ureq->length, ureq->actual);
1062
1063 if (!using_desc_dma(hsotg))
1064 maxreq = get_ep_limit(hs_ep);
1065 else
1066 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1067
1068 if (length > maxreq) {
1069 int round = maxreq % hs_ep->ep.maxpacket;
1070
1071 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1072 __func__, length, maxreq, round);
1073
1074 /* round down to multiple of packets */
1075 if (round)
1076 maxreq -= round;
1077
1078 length = maxreq;
1079 }
1080
1081 if (length)
1082 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1083 else
1084 packets = 1; /* send one packet if length is zero. */
1085
1086 if (dir_in && index != 0)
1087 if (hs_ep->isochronous)
1088 epsize = DXEPTSIZ_MC(packets);
1089 else
1090 epsize = DXEPTSIZ_MC(1);
1091 else
1092 epsize = 0;
1093
1094 /*
1095 * zero length packet should be programmed on its own and should not
1096 * be counted in DIEPTSIZ.PktCnt with other packets.
1097 */
1098 if (dir_in && ureq->zero && !continuing) {
1099 /* Test if zlp is actually required. */
1100 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1101 !(ureq->length % hs_ep->ep.maxpacket))
1102 hs_ep->send_zlp = 1;
1103 }
1104
1105 epsize |= DXEPTSIZ_PKTCNT(packets);
1106 epsize |= DXEPTSIZ_XFERSIZE(length);
1107
1108 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1109 __func__, packets, length, ureq->length, epsize, epsize_reg);
1110
1111 /* store the request as the current one we're doing */
1112 hs_ep->req = hs_req;
1113
1114 if (using_desc_dma(hsotg)) {
1115 u32 offset = 0;
1116 u32 mps = hs_ep->ep.maxpacket;
1117
1118 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1119 if (!dir_in) {
1120 if (!index)
1121 length = mps;
1122 else if (length % mps)
1123 length += (mps - (length % mps));
1124 }
1125
1126 /*
1127 * If more data to send, adjust DMA for EP0 out data stage.
1128 * ureq->dma stays unchanged, hence increment it by already
1129 * passed passed data count before starting new transaction.
1130 */
1131 if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT &&
1132 continuing)
1133 offset = ureq->actual;
1134
1135 /* Fill DDMA chain entries */
1136 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1137 length);
1138
1139 /* write descriptor chain address to control register */
1140 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1141
1142 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1143 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1144 } else {
1145 /* write size / packets */
1146 dwc2_writel(hsotg, epsize, epsize_reg);
1147
1148 if (using_dma(hsotg) && !continuing && (length != 0)) {
1149 /*
1150 * write DMA address to control register, buffer
1151 * already synced by dwc2_hsotg_ep_queue().
1152 */
1153
1154 dwc2_writel(hsotg, ureq->dma, dma_reg);
1155
1156 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1157 __func__, &ureq->dma, dma_reg);
1158 }
1159 }
1160
1161 if (hs_ep->isochronous && hs_ep->interval == 1) {
1162 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
1163 dwc2_gadget_incr_frame_num(hs_ep);
1164
1165 if (hs_ep->target_frame & 0x1)
1166 ctrl |= DXEPCTL_SETODDFR;
1167 else
1168 ctrl |= DXEPCTL_SETEVENFR;
1169 }
1170
1171 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1172
1173 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1174
1175 /* For Setup request do not clear NAK */
1176 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1177 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1178
1179 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1180 dwc2_writel(hsotg, ctrl, epctrl_reg);
1181
1182 /*
1183 * set these, it seems that DMA support increments past the end
1184 * of the packet buffer so we need to calculate the length from
1185 * this information.
1186 */
1187 hs_ep->size_loaded = length;
1188 hs_ep->last_load = ureq->actual;
1189
1190 if (dir_in && !using_dma(hsotg)) {
1191 /* set these anyway, we may need them for non-periodic in */
1192 hs_ep->fifo_load = 0;
1193
1194 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1195 }
1196
1197 /*
1198 * Note, trying to clear the NAK here causes problems with transmit
1199 * on the S3C6400 ending up with the TXFIFO becoming full.
1200 */
1201
1202 /* check ep is enabled */
1203 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1204 dev_dbg(hsotg->dev,
1205 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1206 index, dwc2_readl(hsotg, epctrl_reg));
1207
1208 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1209 __func__, dwc2_readl(hsotg, epctrl_reg));
1210
1211 /* enable ep interrupts */
1212 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1213}
1214
1215/**
1216 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1217 * @hsotg: The device state.
1218 * @hs_ep: The endpoint the request is on.
1219 * @req: The request being processed.
1220 *
1221 * We've been asked to queue a request, so ensure that the memory buffer
1222 * is correctly setup for DMA. If we've been passed an extant DMA address
1223 * then ensure the buffer has been synced to memory. If our buffer has no
1224 * DMA memory, then we map the memory and mark our request to allow us to
1225 * cleanup on completion.
1226 */
1227static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1228 struct dwc2_hsotg_ep *hs_ep,
1229 struct usb_request *req)
1230{
1231 int ret;
1232
1233 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1234 if (ret)
1235 goto dma_error;
1236
1237 return 0;
1238
1239dma_error:
1240 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1241 __func__, req->buf, req->length);
1242
1243 return -EIO;
1244}
1245
1246static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1247 struct dwc2_hsotg_ep *hs_ep,
1248 struct dwc2_hsotg_req *hs_req)
1249{
1250 void *req_buf = hs_req->req.buf;
1251
1252 /* If dma is not being used or buffer is aligned */
1253 if (!using_dma(hsotg) || !((long)req_buf & 3))
1254 return 0;
1255
1256 WARN_ON(hs_req->saved_req_buf);
1257
1258 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1259 hs_ep->ep.name, req_buf, hs_req->req.length);
1260
1261 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1262 if (!hs_req->req.buf) {
1263 hs_req->req.buf = req_buf;
1264 dev_err(hsotg->dev,
1265 "%s: unable to allocate memory for bounce buffer\n",
1266 __func__);
1267 return -ENOMEM;
1268 }
1269
1270 /* Save actual buffer */
1271 hs_req->saved_req_buf = req_buf;
1272
1273 if (hs_ep->dir_in)
1274 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1275 return 0;
1276}
1277
1278static void
1279dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1280 struct dwc2_hsotg_ep *hs_ep,
1281 struct dwc2_hsotg_req *hs_req)
1282{
1283 /* If dma is not being used or buffer was aligned */
1284 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1285 return;
1286
1287 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1288 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1289
1290 /* Copy data from bounce buffer on successful out transfer */
1291 if (!hs_ep->dir_in && !hs_req->req.status)
1292 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1293 hs_req->req.actual);
1294
1295 /* Free bounce buffer */
1296 kfree(hs_req->req.buf);
1297
1298 hs_req->req.buf = hs_req->saved_req_buf;
1299 hs_req->saved_req_buf = NULL;
1300}
1301
1302/**
1303 * dwc2_gadget_target_frame_elapsed - Checks target frame
1304 * @hs_ep: The driver endpoint to check
1305 *
1306 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1307 * corresponding transfer.
1308 */
1309static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1310{
1311 struct dwc2_hsotg *hsotg = hs_ep->parent;
1312 u32 target_frame = hs_ep->target_frame;
1313 u32 current_frame = hsotg->frame_number;
1314 bool frame_overrun = hs_ep->frame_overrun;
1315
1316 if (!frame_overrun && current_frame >= target_frame)
1317 return true;
1318
1319 if (frame_overrun && current_frame >= target_frame &&
1320 ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
1321 return true;
1322
1323 return false;
1324}
1325
1326/*
1327 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1328 * @hsotg: The driver state
1329 * @hs_ep: the ep descriptor chain is for
1330 *
1331 * Called to update EP0 structure's pointers depend on stage of
1332 * control transfer.
1333 */
1334static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1335 struct dwc2_hsotg_ep *hs_ep)
1336{
1337 switch (hsotg->ep0_state) {
1338 case DWC2_EP0_SETUP:
1339 case DWC2_EP0_STATUS_OUT:
1340 hs_ep->desc_list = hsotg->setup_desc[0];
1341 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1342 break;
1343 case DWC2_EP0_DATA_IN:
1344 case DWC2_EP0_STATUS_IN:
1345 hs_ep->desc_list = hsotg->ctrl_in_desc;
1346 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1347 break;
1348 case DWC2_EP0_DATA_OUT:
1349 hs_ep->desc_list = hsotg->ctrl_out_desc;
1350 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1351 break;
1352 default:
1353 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1354 hsotg->ep0_state);
1355 return -EINVAL;
1356 }
1357
1358 return 0;
1359}
1360
1361static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1362 gfp_t gfp_flags)
1363{
1364 struct dwc2_hsotg_req *hs_req = our_req(req);
1365 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1366 struct dwc2_hsotg *hs = hs_ep->parent;
1367 bool first;
1368 int ret;
1369 u32 maxsize = 0;
1370 u32 mask = 0;
1371
1372
1373 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1374 ep->name, req, req->length, req->buf, req->no_interrupt,
1375 req->zero, req->short_not_ok);
1376
1377 /* Prevent new request submission when controller is suspended */
1378 if (hs->lx_state != DWC2_L0) {
1379 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1380 __func__);
1381 return -EAGAIN;
1382 }
1383
1384 /* initialise status of the request */
1385 INIT_LIST_HEAD(&hs_req->queue);
1386 req->actual = 0;
1387 req->status = -EINPROGRESS;
1388
1389 /* Don't queue ISOC request if length greater than mps*mc */
1390 if (hs_ep->isochronous &&
1391 req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1392 dev_err(hs->dev, "req length > maxpacket*mc\n");
1393 return -EINVAL;
1394 }
1395
1396 /* In DDMA mode for ISOC's don't queue request if length greater
1397 * than descriptor limits.
1398 */
1399 if (using_desc_dma(hs) && hs_ep->isochronous) {
1400 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1401 if (hs_ep->dir_in && req->length > maxsize) {
1402 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1403 req->length, maxsize);
1404 return -EINVAL;
1405 }
1406
1407 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1408 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1409 req->length, hs_ep->ep.maxpacket);
1410 return -EINVAL;
1411 }
1412 }
1413
1414 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1415 if (ret)
1416 return ret;
1417
1418 /* if we're using DMA, sync the buffers as necessary */
1419 if (using_dma(hs)) {
1420 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1421 if (ret)
1422 return ret;
1423 }
1424 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1425 if (using_desc_dma(hs) && !hs_ep->index) {
1426 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1427 if (ret)
1428 return ret;
1429 }
1430
1431 first = list_empty(&hs_ep->queue);
1432 list_add_tail(&hs_req->queue, &hs_ep->queue);
1433
1434 /*
1435 * Handle DDMA isochronous transfers separately - just add new entry
1436 * to the descriptor chain.
1437 * Transfer will be started once SW gets either one of NAK or
1438 * OutTknEpDis interrupts.
1439 */
1440 if (using_desc_dma(hs) && hs_ep->isochronous) {
1441 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1442 dma_addr_t dma_addr = hs_req->req.dma;
1443
1444 if (hs_req->req.num_sgs) {
1445 WARN_ON(hs_req->req.num_sgs > 1);
1446 dma_addr = sg_dma_address(hs_req->req.sg);
1447 }
1448 dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1449 hs_req->req.length);
1450 }
1451 return 0;
1452 }
1453
1454 /* Change EP direction if status phase request is after data out */
1455 if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1456 hs->ep0_state == DWC2_EP0_DATA_OUT)
1457 hs_ep->dir_in = 1;
1458
1459 if (first) {
1460 if (!hs_ep->isochronous) {
1461 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1462 return 0;
1463 }
1464
1465 /* Update current frame number value. */
1466 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1467 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1468 dwc2_gadget_incr_frame_num(hs_ep);
1469 /* Update current frame number value once more as it
1470 * changes here.
1471 */
1472 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1473 }
1474
1475 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1476 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1477 }
1478 return 0;
1479}
1480
1481static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1482 gfp_t gfp_flags)
1483{
1484 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1485 struct dwc2_hsotg *hs = hs_ep->parent;
1486 unsigned long flags = 0;
1487 int ret = 0;
1488
1489 spin_lock_irqsave(&hs->lock, flags);
1490 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1491 spin_unlock_irqrestore(&hs->lock, flags);
1492
1493 return ret;
1494}
1495
1496static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1497 struct usb_request *req)
1498{
1499 struct dwc2_hsotg_req *hs_req = our_req(req);
1500
1501 kfree(hs_req);
1502}
1503
1504/**
1505 * dwc2_hsotg_complete_oursetup - setup completion callback
1506 * @ep: The endpoint the request was on.
1507 * @req: The request completed.
1508 *
1509 * Called on completion of any requests the driver itself
1510 * submitted that need cleaning up.
1511 */
1512static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1513 struct usb_request *req)
1514{
1515 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1516 struct dwc2_hsotg *hsotg = hs_ep->parent;
1517
1518 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1519
1520 dwc2_hsotg_ep_free_request(ep, req);
1521}
1522
1523/**
1524 * ep_from_windex - convert control wIndex value to endpoint
1525 * @hsotg: The driver state.
1526 * @windex: The control request wIndex field (in host order).
1527 *
1528 * Convert the given wIndex into a pointer to an driver endpoint
1529 * structure, or return NULL if it is not a valid endpoint.
1530 */
1531static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1532 u32 windex)
1533{
1534 struct dwc2_hsotg_ep *ep;
1535 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1536 int idx = windex & 0x7F;
1537
1538 if (windex >= 0x100)
1539 return NULL;
1540
1541 if (idx > hsotg->num_of_eps)
1542 return NULL;
1543
1544 ep = index_to_ep(hsotg, idx, dir);
1545
1546 if (idx && ep->dir_in != dir)
1547 return NULL;
1548
1549 return ep;
1550}
1551
1552/**
1553 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1554 * @hsotg: The driver state.
1555 * @testmode: requested usb test mode
1556 * Enable usb Test Mode requested by the Host.
1557 */
1558int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1559{
1560 int dctl = dwc2_readl(hsotg, DCTL);
1561
1562 dctl &= ~DCTL_TSTCTL_MASK;
1563 switch (testmode) {
1564 case USB_TEST_J:
1565 case USB_TEST_K:
1566 case USB_TEST_SE0_NAK:
1567 case USB_TEST_PACKET:
1568 case USB_TEST_FORCE_ENABLE:
1569 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1570 break;
1571 default:
1572 return -EINVAL;
1573 }
1574 dwc2_writel(hsotg, dctl, DCTL);
1575 return 0;
1576}
1577
1578/**
1579 * dwc2_hsotg_send_reply - send reply to control request
1580 * @hsotg: The device state
1581 * @ep: Endpoint 0
1582 * @buff: Buffer for request
1583 * @length: Length of reply.
1584 *
1585 * Create a request and queue it on the given endpoint. This is useful as
1586 * an internal method of sending replies to certain control requests, etc.
1587 */
1588static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1589 struct dwc2_hsotg_ep *ep,
1590 void *buff,
1591 int length)
1592{
1593 struct usb_request *req;
1594 int ret;
1595
1596 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1597
1598 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1599 hsotg->ep0_reply = req;
1600 if (!req) {
1601 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1602 return -ENOMEM;
1603 }
1604
1605 req->buf = hsotg->ep0_buff;
1606 req->length = length;
1607 /*
1608 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1609 * STATUS stage.
1610 */
1611 req->zero = 0;
1612 req->complete = dwc2_hsotg_complete_oursetup;
1613
1614 if (length)
1615 memcpy(req->buf, buff, length);
1616
1617 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1618 if (ret) {
1619 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1620 return ret;
1621 }
1622
1623 return 0;
1624}
1625
1626/**
1627 * dwc2_hsotg_process_req_status - process request GET_STATUS
1628 * @hsotg: The device state
1629 * @ctrl: USB control request
1630 */
1631static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1632 struct usb_ctrlrequest *ctrl)
1633{
1634 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1635 struct dwc2_hsotg_ep *ep;
1636 __le16 reply;
1637 u16 status;
1638 int ret;
1639
1640 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1641
1642 if (!ep0->dir_in) {
1643 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1644 return -EINVAL;
1645 }
1646
1647 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1648 case USB_RECIP_DEVICE:
1649 status = hsotg->gadget.is_selfpowered <<
1650 USB_DEVICE_SELF_POWERED;
1651 status |= hsotg->remote_wakeup_allowed <<
1652 USB_DEVICE_REMOTE_WAKEUP;
1653 reply = cpu_to_le16(status);
1654 break;
1655
1656 case USB_RECIP_INTERFACE:
1657 /* currently, the data result should be zero */
1658 reply = cpu_to_le16(0);
1659 break;
1660
1661 case USB_RECIP_ENDPOINT:
1662 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1663 if (!ep)
1664 return -ENOENT;
1665
1666 reply = cpu_to_le16(ep->halted ? 1 : 0);
1667 break;
1668
1669 default:
1670 return 0;
1671 }
1672
1673 if (le16_to_cpu(ctrl->wLength) != 2)
1674 return -EINVAL;
1675
1676 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1677 if (ret) {
1678 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1679 return ret;
1680 }
1681
1682 return 1;
1683}
1684
1685static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1686
1687/**
1688 * get_ep_head - return the first request on the endpoint
1689 * @hs_ep: The controller endpoint to get
1690 *
1691 * Get the first request on the endpoint.
1692 */
1693static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1694{
1695 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1696 queue);
1697}
1698
1699/**
1700 * dwc2_gadget_start_next_request - Starts next request from ep queue
1701 * @hs_ep: Endpoint structure
1702 *
1703 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1704 * in its handler. Hence we need to unmask it here to be able to do
1705 * resynchronization.
1706 */
1707static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1708{
1709 u32 mask;
1710 struct dwc2_hsotg *hsotg = hs_ep->parent;
1711 int dir_in = hs_ep->dir_in;
1712 struct dwc2_hsotg_req *hs_req;
1713 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1714
1715 if (!list_empty(&hs_ep->queue)) {
1716 hs_req = get_ep_head(hs_ep);
1717 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1718 return;
1719 }
1720 if (!hs_ep->isochronous)
1721 return;
1722
1723 if (dir_in) {
1724 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1725 __func__);
1726 } else {
1727 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1728 __func__);
1729 mask = dwc2_readl(hsotg, epmsk_reg);
1730 mask |= DOEPMSK_OUTTKNEPDISMSK;
1731 dwc2_writel(hsotg, mask, epmsk_reg);
1732 }
1733}
1734
1735/**
1736 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1737 * @hsotg: The device state
1738 * @ctrl: USB control request
1739 */
1740static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1741 struct usb_ctrlrequest *ctrl)
1742{
1743 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1744 struct dwc2_hsotg_req *hs_req;
1745 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1746 struct dwc2_hsotg_ep *ep;
1747 int ret;
1748 bool halted;
1749 u32 recip;
1750 u32 wValue;
1751 u32 wIndex;
1752
1753 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1754 __func__, set ? "SET" : "CLEAR");
1755
1756 wValue = le16_to_cpu(ctrl->wValue);
1757 wIndex = le16_to_cpu(ctrl->wIndex);
1758 recip = ctrl->bRequestType & USB_RECIP_MASK;
1759
1760 switch (recip) {
1761 case USB_RECIP_DEVICE:
1762 switch (wValue) {
1763 case USB_DEVICE_REMOTE_WAKEUP:
1764 if (set)
1765 hsotg->remote_wakeup_allowed = 1;
1766 else
1767 hsotg->remote_wakeup_allowed = 0;
1768 break;
1769
1770 case USB_DEVICE_TEST_MODE:
1771 if ((wIndex & 0xff) != 0)
1772 return -EINVAL;
1773 if (!set)
1774 return -EINVAL;
1775
1776 hsotg->test_mode = wIndex >> 8;
1777 break;
1778 default:
1779 return -ENOENT;
1780 }
1781
1782 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1783 if (ret) {
1784 dev_err(hsotg->dev,
1785 "%s: failed to send reply\n", __func__);
1786 return ret;
1787 }
1788 break;
1789
1790 case USB_RECIP_ENDPOINT:
1791 ep = ep_from_windex(hsotg, wIndex);
1792 if (!ep) {
1793 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1794 __func__, wIndex);
1795 return -ENOENT;
1796 }
1797
1798 switch (wValue) {
1799 case USB_ENDPOINT_HALT:
1800 halted = ep->halted;
1801
1802 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1803
1804 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1805 if (ret) {
1806 dev_err(hsotg->dev,
1807 "%s: failed to send reply\n", __func__);
1808 return ret;
1809 }
1810
1811 /*
1812 * we have to complete all requests for ep if it was
1813 * halted, and the halt was cleared by CLEAR_FEATURE
1814 */
1815
1816 if (!set && halted) {
1817 /*
1818 * If we have request in progress,
1819 * then complete it
1820 */
1821 if (ep->req) {
1822 hs_req = ep->req;
1823 ep->req = NULL;
1824 list_del_init(&hs_req->queue);
1825 if (hs_req->req.complete) {
1826 spin_unlock(&hsotg->lock);
1827 usb_gadget_giveback_request(
1828 &ep->ep, &hs_req->req);
1829 spin_lock(&hsotg->lock);
1830 }
1831 }
1832
1833 /* If we have pending request, then start it */
1834 if (!ep->req)
1835 dwc2_gadget_start_next_request(ep);
1836 }
1837
1838 break;
1839
1840 default:
1841 return -ENOENT;
1842 }
1843 break;
1844 default:
1845 return -ENOENT;
1846 }
1847 return 1;
1848}
1849
1850static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1851
1852/**
1853 * dwc2_hsotg_stall_ep0 - stall ep0
1854 * @hsotg: The device state
1855 *
1856 * Set stall for ep0 as response for setup request.
1857 */
1858static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1859{
1860 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1861 u32 reg;
1862 u32 ctrl;
1863
1864 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1865 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1866
1867 /*
1868 * DxEPCTL_Stall will be cleared by EP once it has
1869 * taken effect, so no need to clear later.
1870 */
1871
1872 ctrl = dwc2_readl(hsotg, reg);
1873 ctrl |= DXEPCTL_STALL;
1874 ctrl |= DXEPCTL_CNAK;
1875 dwc2_writel(hsotg, ctrl, reg);
1876
1877 dev_dbg(hsotg->dev,
1878 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1879 ctrl, reg, dwc2_readl(hsotg, reg));
1880
1881 /*
1882 * complete won't be called, so we enqueue
1883 * setup request here
1884 */
1885 dwc2_hsotg_enqueue_setup(hsotg);
1886}
1887
1888/**
1889 * dwc2_hsotg_process_control - process a control request
1890 * @hsotg: The device state
1891 * @ctrl: The control request received
1892 *
1893 * The controller has received the SETUP phase of a control request, and
1894 * needs to work out what to do next (and whether to pass it on to the
1895 * gadget driver).
1896 */
1897static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1898 struct usb_ctrlrequest *ctrl)
1899{
1900 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1901 int ret = 0;
1902 u32 dcfg;
1903
1904 dev_dbg(hsotg->dev,
1905 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1906 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1907 ctrl->wIndex, ctrl->wLength);
1908
1909 if (ctrl->wLength == 0) {
1910 ep0->dir_in = 1;
1911 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1912 } else if (ctrl->bRequestType & USB_DIR_IN) {
1913 ep0->dir_in = 1;
1914 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1915 } else {
1916 ep0->dir_in = 0;
1917 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1918 }
1919
1920 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1921 switch (ctrl->bRequest) {
1922 case USB_REQ_SET_ADDRESS:
1923 hsotg->connected = 1;
1924 dcfg = dwc2_readl(hsotg, DCFG);
1925 dcfg &= ~DCFG_DEVADDR_MASK;
1926 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1927 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1928 dwc2_writel(hsotg, dcfg, DCFG);
1929
1930 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1931
1932 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1933 return;
1934
1935 case USB_REQ_GET_STATUS:
1936 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1937 break;
1938
1939 case USB_REQ_CLEAR_FEATURE:
1940 case USB_REQ_SET_FEATURE:
1941 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1942 break;
1943 }
1944 }
1945
1946 /* as a fallback, try delivering it to the driver to deal with */
1947
1948 if (ret == 0 && hsotg->driver) {
1949 spin_unlock(&hsotg->lock);
1950 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1951 spin_lock(&hsotg->lock);
1952 if (ret < 0)
1953 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1954 }
1955
1956 hsotg->delayed_status = false;
1957 if (ret == USB_GADGET_DELAYED_STATUS)
1958 hsotg->delayed_status = true;
1959
1960 /*
1961 * the request is either unhandlable, or is not formatted correctly
1962 * so respond with a STALL for the status stage to indicate failure.
1963 */
1964
1965 if (ret < 0)
1966 dwc2_hsotg_stall_ep0(hsotg);
1967}
1968
1969/**
1970 * dwc2_hsotg_complete_setup - completion of a setup transfer
1971 * @ep: The endpoint the request was on.
1972 * @req: The request completed.
1973 *
1974 * Called on completion of any requests the driver itself submitted for
1975 * EP0 setup packets
1976 */
1977static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1978 struct usb_request *req)
1979{
1980 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1981 struct dwc2_hsotg *hsotg = hs_ep->parent;
1982
1983 if (req->status < 0) {
1984 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1985 return;
1986 }
1987
1988 spin_lock(&hsotg->lock);
1989 if (req->actual == 0)
1990 dwc2_hsotg_enqueue_setup(hsotg);
1991 else
1992 dwc2_hsotg_process_control(hsotg, req->buf);
1993 spin_unlock(&hsotg->lock);
1994}
1995
1996/**
1997 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1998 * @hsotg: The device state.
1999 *
2000 * Enqueue a request on EP0 if necessary to received any SETUP packets
2001 * received from the host.
2002 */
2003static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
2004{
2005 struct usb_request *req = hsotg->ctrl_req;
2006 struct dwc2_hsotg_req *hs_req = our_req(req);
2007 int ret;
2008
2009 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2010
2011 req->zero = 0;
2012 req->length = 8;
2013 req->buf = hsotg->ctrl_buff;
2014 req->complete = dwc2_hsotg_complete_setup;
2015
2016 if (!list_empty(&hs_req->queue)) {
2017 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2018 return;
2019 }
2020
2021 hsotg->eps_out[0]->dir_in = 0;
2022 hsotg->eps_out[0]->send_zlp = 0;
2023 hsotg->ep0_state = DWC2_EP0_SETUP;
2024
2025 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2026 if (ret < 0) {
2027 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2028 /*
2029 * Don't think there's much we can do other than watch the
2030 * driver fail.
2031 */
2032 }
2033}
2034
2035static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2036 struct dwc2_hsotg_ep *hs_ep)
2037{
2038 u32 ctrl;
2039 u8 index = hs_ep->index;
2040 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2041 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
2042
2043 if (hs_ep->dir_in)
2044 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2045 index);
2046 else
2047 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2048 index);
2049 if (using_desc_dma(hsotg)) {
2050 /* Not specific buffer needed for ep0 ZLP */
2051 dma_addr_t dma = hs_ep->desc_list_dma;
2052
2053 if (!index)
2054 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2055
2056 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
2057 } else {
2058 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2059 DXEPTSIZ_XFERSIZE(0),
2060 epsiz_reg);
2061 }
2062
2063 ctrl = dwc2_readl(hsotg, epctl_reg);
2064 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
2065 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
2066 ctrl |= DXEPCTL_USBACTEP;
2067 dwc2_writel(hsotg, ctrl, epctl_reg);
2068}
2069
2070/**
2071 * dwc2_hsotg_complete_request - complete a request given to us
2072 * @hsotg: The device state.
2073 * @hs_ep: The endpoint the request was on.
2074 * @hs_req: The request to complete.
2075 * @result: The result code (0 => Ok, otherwise errno)
2076 *
2077 * The given request has finished, so call the necessary completion
2078 * if it has one and then look to see if we can start a new request
2079 * on the endpoint.
2080 *
2081 * Note, expects the ep to already be locked as appropriate.
2082 */
2083static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2084 struct dwc2_hsotg_ep *hs_ep,
2085 struct dwc2_hsotg_req *hs_req,
2086 int result)
2087{
2088 if (!hs_req) {
2089 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2090 return;
2091 }
2092
2093 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2094 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2095
2096 /*
2097 * only replace the status if we've not already set an error
2098 * from a previous transaction
2099 */
2100
2101 if (hs_req->req.status == -EINPROGRESS)
2102 hs_req->req.status = result;
2103
2104 if (using_dma(hsotg))
2105 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2106
2107 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2108
2109 hs_ep->req = NULL;
2110 list_del_init(&hs_req->queue);
2111
2112 /*
2113 * call the complete request with the locks off, just in case the
2114 * request tries to queue more work for this endpoint.
2115 */
2116
2117 if (hs_req->req.complete) {
2118 spin_unlock(&hsotg->lock);
2119 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2120 spin_lock(&hsotg->lock);
2121 }
2122
2123 /* In DDMA don't need to proceed to starting of next ISOC request */
2124 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2125 return;
2126
2127 /*
2128 * Look to see if there is anything else to do. Note, the completion
2129 * of the previous request may have caused a new request to be started
2130 * so be careful when doing this.
2131 */
2132
2133 if (!hs_ep->req && result >= 0)
2134 dwc2_gadget_start_next_request(hs_ep);
2135}
2136
2137/*
2138 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2139 * @hs_ep: The endpoint the request was on.
2140 *
2141 * Get first request from the ep queue, determine descriptor on which complete
2142 * happened. SW discovers which descriptor currently in use by HW, adjusts
2143 * dma_address and calculates index of completed descriptor based on the value
2144 * of DEPDMA register. Update actual length of request, giveback to gadget.
2145 */
2146static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2147{
2148 struct dwc2_hsotg *hsotg = hs_ep->parent;
2149 struct dwc2_hsotg_req *hs_req;
2150 struct usb_request *ureq;
2151 u32 desc_sts;
2152 u32 mask;
2153
2154 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2155
2156 /* Process only descriptors with buffer status set to DMA done */
2157 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2158 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2159
2160 hs_req = get_ep_head(hs_ep);
2161 if (!hs_req) {
2162 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2163 return;
2164 }
2165 ureq = &hs_req->req;
2166
2167 /* Check completion status */
2168 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2169 DEV_DMA_STS_SUCC) {
2170 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2171 DEV_DMA_ISOC_RX_NBYTES_MASK;
2172 ureq->actual = ureq->length - ((desc_sts & mask) >>
2173 DEV_DMA_ISOC_NBYTES_SHIFT);
2174
2175 /* Adjust actual len for ISOC Out if len is
2176 * not align of 4
2177 */
2178 if (!hs_ep->dir_in && ureq->length & 0x3)
2179 ureq->actual += 4 - (ureq->length & 0x3);
2180
2181 /* Set actual frame number for completed transfers */
2182 ureq->frame_number =
2183 (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2184 DEV_DMA_ISOC_FRNUM_SHIFT;
2185 }
2186
2187 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2188
2189 hs_ep->compl_desc++;
2190 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
2191 hs_ep->compl_desc = 0;
2192 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2193 }
2194}
2195
2196/*
2197 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2198 * @hs_ep: The isochronous endpoint.
2199 *
2200 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2201 * interrupt. Reset target frame and next_desc to allow to start
2202 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2203 * interrupt for OUT direction.
2204 */
2205static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2206{
2207 struct dwc2_hsotg *hsotg = hs_ep->parent;
2208
2209 if (!hs_ep->dir_in)
2210 dwc2_flush_rx_fifo(hsotg);
2211 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2212
2213 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2214 hs_ep->next_desc = 0;
2215 hs_ep->compl_desc = 0;
2216}
2217
2218/**
2219 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2220 * @hsotg: The device state.
2221 * @ep_idx: The endpoint index for the data
2222 * @size: The size of data in the fifo, in bytes
2223 *
2224 * The FIFO status shows there is data to read from the FIFO for a given
2225 * endpoint, so sort out whether we need to read the data into a request
2226 * that has been made for that endpoint.
2227 */
2228static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2229{
2230 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2231 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2232 int to_read;
2233 int max_req;
2234 int read_ptr;
2235
2236 if (!hs_req) {
2237 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2238 int ptr;
2239
2240 dev_dbg(hsotg->dev,
2241 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2242 __func__, size, ep_idx, epctl);
2243
2244 /* dump the data from the FIFO, we've nothing we can do */
2245 for (ptr = 0; ptr < size; ptr += 4)
2246 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2247
2248 return;
2249 }
2250
2251 to_read = size;
2252 read_ptr = hs_req->req.actual;
2253 max_req = hs_req->req.length - read_ptr;
2254
2255 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2256 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2257
2258 if (to_read > max_req) {
2259 /*
2260 * more data appeared than we where willing
2261 * to deal with in this request.
2262 */
2263
2264 /* currently we don't deal this */
2265 WARN_ON_ONCE(1);
2266 }
2267
2268 hs_ep->total_data += to_read;
2269 hs_req->req.actual += to_read;
2270 to_read = DIV_ROUND_UP(to_read, 4);
2271
2272 /*
2273 * note, we might over-write the buffer end by 3 bytes depending on
2274 * alignment of the data.
2275 */
2276 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2277 hs_req->req.buf + read_ptr, to_read);
2278}
2279
2280/**
2281 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2282 * @hsotg: The device instance
2283 * @dir_in: If IN zlp
2284 *
2285 * Generate a zero-length IN packet request for terminating a SETUP
2286 * transaction.
2287 *
2288 * Note, since we don't write any data to the TxFIFO, then it is
2289 * currently believed that we do not need to wait for any space in
2290 * the TxFIFO.
2291 */
2292static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2293{
2294 /* eps_out[0] is used in both directions */
2295 hsotg->eps_out[0]->dir_in = dir_in;
2296 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2297
2298 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2299}
2300
2301static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
2302 u32 epctl_reg)
2303{
2304 u32 ctrl;
2305
2306 ctrl = dwc2_readl(hsotg, epctl_reg);
2307 if (ctrl & DXEPCTL_EOFRNUM)
2308 ctrl |= DXEPCTL_SETEVENFR;
2309 else
2310 ctrl |= DXEPCTL_SETODDFR;
2311 dwc2_writel(hsotg, ctrl, epctl_reg);
2312}
2313
2314/*
2315 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2316 * @hs_ep - The endpoint on which transfer went
2317 *
2318 * Iterate over endpoints descriptor chain and get info on bytes remained
2319 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2320 */
2321static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2322{
2323 struct dwc2_hsotg *hsotg = hs_ep->parent;
2324 unsigned int bytes_rem = 0;
2325 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2326 int i;
2327 u32 status;
2328
2329 if (!desc)
2330 return -EINVAL;
2331
2332 for (i = 0; i < hs_ep->desc_count; ++i) {
2333 status = desc->status;
2334 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2335
2336 if (status & DEV_DMA_STS_MASK)
2337 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2338 i, status & DEV_DMA_STS_MASK);
2339 desc++;
2340 }
2341
2342 return bytes_rem;
2343}
2344
2345/**
2346 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2347 * @hsotg: The device instance
2348 * @epnum: The endpoint received from
2349 *
2350 * The RXFIFO has delivered an OutDone event, which means that the data
2351 * transfer for an OUT endpoint has been completed, either by a short
2352 * packet or by the finish of a transfer.
2353 */
2354static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2355{
2356 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2357 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2358 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2359 struct usb_request *req = &hs_req->req;
2360 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2361 int result = 0;
2362
2363 if (!hs_req) {
2364 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2365 return;
2366 }
2367
2368 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2369 dev_dbg(hsotg->dev, "zlp packet received\n");
2370 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2371 dwc2_hsotg_enqueue_setup(hsotg);
2372 return;
2373 }
2374
2375 if (using_desc_dma(hsotg))
2376 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2377
2378 if (using_dma(hsotg)) {
2379 unsigned int size_done;
2380
2381 /*
2382 * Calculate the size of the transfer by checking how much
2383 * is left in the endpoint size register and then working it
2384 * out from the amount we loaded for the transfer.
2385 *
2386 * We need to do this as DMA pointers are always 32bit aligned
2387 * so may overshoot/undershoot the transfer.
2388 */
2389
2390 size_done = hs_ep->size_loaded - size_left;
2391 size_done += hs_ep->last_load;
2392
2393 req->actual = size_done;
2394 }
2395
2396 /* if there is more request to do, schedule new transfer */
2397 if (req->actual < req->length && size_left == 0) {
2398 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2399 return;
2400 }
2401
2402 if (req->actual < req->length && req->short_not_ok) {
2403 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2404 __func__, req->actual, req->length);
2405
2406 /*
2407 * todo - what should we return here? there's no one else
2408 * even bothering to check the status.
2409 */
2410 }
2411
2412 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2413 if (!using_desc_dma(hsotg) && epnum == 0 &&
2414 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2415 /* Move to STATUS IN */
2416 if (!hsotg->delayed_status)
2417 dwc2_hsotg_ep0_zlp(hsotg, true);
2418 }
2419
2420 /*
2421 * Slave mode OUT transfers do not go through XferComplete so
2422 * adjust the ISOC parity here.
2423 */
2424 if (!using_dma(hsotg)) {
2425 if (hs_ep->isochronous && hs_ep->interval == 1)
2426 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
2427 else if (hs_ep->isochronous && hs_ep->interval > 1)
2428 dwc2_gadget_incr_frame_num(hs_ep);
2429 }
2430
2431 /* Set actual frame number for completed transfers */
2432 if (!using_desc_dma(hsotg) && hs_ep->isochronous)
2433 req->frame_number = hsotg->frame_number;
2434
2435 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2436}
2437
2438/**
2439 * dwc2_hsotg_handle_rx - RX FIFO has data
2440 * @hsotg: The device instance
2441 *
2442 * The IRQ handler has detected that the RX FIFO has some data in it
2443 * that requires processing, so find out what is in there and do the
2444 * appropriate read.
2445 *
2446 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2447 * chunks, so if you have x packets received on an endpoint you'll get x
2448 * FIFO events delivered, each with a packet's worth of data in it.
2449 *
2450 * When using DMA, we should not be processing events from the RXFIFO
2451 * as the actual data should be sent to the memory directly and we turn
2452 * on the completion interrupts to get notifications of transfer completion.
2453 */
2454static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2455{
2456 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2457 u32 epnum, status, size;
2458
2459 WARN_ON(using_dma(hsotg));
2460
2461 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2462 status = grxstsr & GRXSTS_PKTSTS_MASK;
2463
2464 size = grxstsr & GRXSTS_BYTECNT_MASK;
2465 size >>= GRXSTS_BYTECNT_SHIFT;
2466
2467 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2468 __func__, grxstsr, size, epnum);
2469
2470 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2471 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2472 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2473 break;
2474
2475 case GRXSTS_PKTSTS_OUTDONE:
2476 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2477 dwc2_hsotg_read_frameno(hsotg));
2478
2479 if (!using_dma(hsotg))
2480 dwc2_hsotg_handle_outdone(hsotg, epnum);
2481 break;
2482
2483 case GRXSTS_PKTSTS_SETUPDONE:
2484 dev_dbg(hsotg->dev,
2485 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2486 dwc2_hsotg_read_frameno(hsotg),
2487 dwc2_readl(hsotg, DOEPCTL(0)));
2488 /*
2489 * Call dwc2_hsotg_handle_outdone here if it was not called from
2490 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2491 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2492 */
2493 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2494 dwc2_hsotg_handle_outdone(hsotg, epnum);
2495 break;
2496
2497 case GRXSTS_PKTSTS_OUTRX:
2498 dwc2_hsotg_rx_data(hsotg, epnum, size);
2499 break;
2500
2501 case GRXSTS_PKTSTS_SETUPRX:
2502 dev_dbg(hsotg->dev,
2503 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2504 dwc2_hsotg_read_frameno(hsotg),
2505 dwc2_readl(hsotg, DOEPCTL(0)));
2506
2507 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2508
2509 dwc2_hsotg_rx_data(hsotg, epnum, size);
2510 break;
2511
2512 default:
2513 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2514 __func__, grxstsr);
2515
2516 dwc2_hsotg_dump(hsotg);
2517 break;
2518 }
2519}
2520
2521/**
2522 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2523 * @mps: The maximum packet size in bytes.
2524 */
2525static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2526{
2527 switch (mps) {
2528 case 64:
2529 return D0EPCTL_MPS_64;
2530 case 32:
2531 return D0EPCTL_MPS_32;
2532 case 16:
2533 return D0EPCTL_MPS_16;
2534 case 8:
2535 return D0EPCTL_MPS_8;
2536 }
2537
2538 /* bad max packet size, warn and return invalid result */
2539 WARN_ON(1);
2540 return (u32)-1;
2541}
2542
2543/**
2544 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2545 * @hsotg: The driver state.
2546 * @ep: The index number of the endpoint
2547 * @mps: The maximum packet size in bytes
2548 * @mc: The multicount value
2549 * @dir_in: True if direction is in.
2550 *
2551 * Configure the maximum packet size for the given endpoint, updating
2552 * the hardware control registers to reflect this.
2553 */
2554static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2555 unsigned int ep, unsigned int mps,
2556 unsigned int mc, unsigned int dir_in)
2557{
2558 struct dwc2_hsotg_ep *hs_ep;
2559 u32 reg;
2560
2561 hs_ep = index_to_ep(hsotg, ep, dir_in);
2562 if (!hs_ep)
2563 return;
2564
2565 if (ep == 0) {
2566 u32 mps_bytes = mps;
2567
2568 /* EP0 is a special case */
2569 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2570 if (mps > 3)
2571 goto bad_mps;
2572 hs_ep->ep.maxpacket = mps_bytes;
2573 hs_ep->mc = 1;
2574 } else {
2575 if (mps > 1024)
2576 goto bad_mps;
2577 hs_ep->mc = mc;
2578 if (mc > 3)
2579 goto bad_mps;
2580 hs_ep->ep.maxpacket = mps;
2581 }
2582
2583 if (dir_in) {
2584 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2585 reg &= ~DXEPCTL_MPS_MASK;
2586 reg |= mps;
2587 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2588 } else {
2589 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2590 reg &= ~DXEPCTL_MPS_MASK;
2591 reg |= mps;
2592 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2593 }
2594
2595 return;
2596
2597bad_mps:
2598 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2599}
2600
2601/**
2602 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2603 * @hsotg: The driver state
2604 * @idx: The index for the endpoint (0..15)
2605 */
2606static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2607{
2608 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2609 GRSTCTL);
2610
2611 /* wait until the fifo is flushed */
2612 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2613 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2614 __func__);
2615}
2616
2617/**
2618 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2619 * @hsotg: The driver state
2620 * @hs_ep: The driver endpoint to check.
2621 *
2622 * Check to see if there is a request that has data to send, and if so
2623 * make an attempt to write data into the FIFO.
2624 */
2625static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2626 struct dwc2_hsotg_ep *hs_ep)
2627{
2628 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2629
2630 if (!hs_ep->dir_in || !hs_req) {
2631 /**
2632 * if request is not enqueued, we disable interrupts
2633 * for endpoints, excepting ep0
2634 */
2635 if (hs_ep->index != 0)
2636 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2637 hs_ep->dir_in, 0);
2638 return 0;
2639 }
2640
2641 if (hs_req->req.actual < hs_req->req.length) {
2642 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2643 hs_ep->index);
2644 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2645 }
2646
2647 return 0;
2648}
2649
2650/**
2651 * dwc2_hsotg_complete_in - complete IN transfer
2652 * @hsotg: The device state.
2653 * @hs_ep: The endpoint that has just completed.
2654 *
2655 * An IN transfer has been completed, update the transfer's state and then
2656 * call the relevant completion routines.
2657 */
2658static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2659 struct dwc2_hsotg_ep *hs_ep)
2660{
2661 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2662 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2663 int size_left, size_done;
2664
2665 if (!hs_req) {
2666 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2667 return;
2668 }
2669
2670 /* Finish ZLP handling for IN EP0 transactions */
2671 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2672 dev_dbg(hsotg->dev, "zlp packet sent\n");
2673
2674 /*
2675 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2676 * changed to IN. Change back to complete OUT transfer request
2677 */
2678 hs_ep->dir_in = 0;
2679
2680 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2681 if (hsotg->test_mode) {
2682 int ret;
2683
2684 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2685 if (ret < 0) {
2686 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2687 hsotg->test_mode);
2688 dwc2_hsotg_stall_ep0(hsotg);
2689 return;
2690 }
2691 }
2692 dwc2_hsotg_enqueue_setup(hsotg);
2693 return;
2694 }
2695
2696 /*
2697 * Calculate the size of the transfer by checking how much is left
2698 * in the endpoint size register and then working it out from
2699 * the amount we loaded for the transfer.
2700 *
2701 * We do this even for DMA, as the transfer may have incremented
2702 * past the end of the buffer (DMA transfers are always 32bit
2703 * aligned).
2704 */
2705 if (using_desc_dma(hsotg)) {
2706 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2707 if (size_left < 0)
2708 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2709 size_left);
2710 } else {
2711 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2712 }
2713
2714 size_done = hs_ep->size_loaded - size_left;
2715 size_done += hs_ep->last_load;
2716
2717 if (hs_req->req.actual != size_done)
2718 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2719 __func__, hs_req->req.actual, size_done);
2720
2721 hs_req->req.actual = size_done;
2722 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2723 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2724
2725 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2726 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2727 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2728 return;
2729 }
2730
2731 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
2732 if (hs_ep->send_zlp) {
2733 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2734 hs_ep->send_zlp = 0;
2735 /* transfer will be completed on next complete interrupt */
2736 return;
2737 }
2738
2739 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2740 /* Move to STATUS OUT */
2741 dwc2_hsotg_ep0_zlp(hsotg, false);
2742 return;
2743 }
2744
2745 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2746}
2747
2748/**
2749 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2750 * @hsotg: The device state.
2751 * @idx: Index of ep.
2752 * @dir_in: Endpoint direction 1-in 0-out.
2753 *
2754 * Reads for endpoint with given index and direction, by masking
2755 * epint_reg with coresponding mask.
2756 */
2757static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2758 unsigned int idx, int dir_in)
2759{
2760 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2761 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2762 u32 ints;
2763 u32 mask;
2764 u32 diepempmsk;
2765
2766 mask = dwc2_readl(hsotg, epmsk_reg);
2767 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2768 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2769 mask |= DXEPINT_SETUP_RCVD;
2770
2771 ints = dwc2_readl(hsotg, epint_reg);
2772 ints &= mask;
2773 return ints;
2774}
2775
2776/**
2777 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2778 * @hs_ep: The endpoint on which interrupt is asserted.
2779 *
2780 * This interrupt indicates that the endpoint has been disabled per the
2781 * application's request.
2782 *
2783 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2784 * in case of ISOC completes current request.
2785 *
2786 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2787 * request starts it.
2788 */
2789static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2790{
2791 struct dwc2_hsotg *hsotg = hs_ep->parent;
2792 struct dwc2_hsotg_req *hs_req;
2793 unsigned char idx = hs_ep->index;
2794 int dir_in = hs_ep->dir_in;
2795 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2796 int dctl = dwc2_readl(hsotg, DCTL);
2797
2798 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2799
2800 if (dir_in) {
2801 int epctl = dwc2_readl(hsotg, epctl_reg);
2802
2803 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2804
2805 if (hs_ep->isochronous) {
2806 dwc2_hsotg_complete_in(hsotg, hs_ep);
2807 return;
2808 }
2809
2810 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2811 int dctl = dwc2_readl(hsotg, DCTL);
2812
2813 dctl |= DCTL_CGNPINNAK;
2814 dwc2_writel(hsotg, dctl, DCTL);
2815 }
2816 return;
2817 }
2818
2819 if (dctl & DCTL_GOUTNAKSTS) {
2820 dctl |= DCTL_CGOUTNAK;
2821 dwc2_writel(hsotg, dctl, DCTL);
2822 }
2823
2824 if (!hs_ep->isochronous)
2825 return;
2826
2827 if (list_empty(&hs_ep->queue)) {
2828 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2829 __func__, hs_ep);
2830 return;
2831 }
2832
2833 do {
2834 hs_req = get_ep_head(hs_ep);
2835 if (hs_req)
2836 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2837 -ENODATA);
2838 dwc2_gadget_incr_frame_num(hs_ep);
2839 /* Update current frame number value. */
2840 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2841 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2842
2843 dwc2_gadget_start_next_request(hs_ep);
2844}
2845
2846/**
2847 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2848 * @ep: The endpoint on which interrupt is asserted.
2849 *
2850 * This is starting point for ISOC-OUT transfer, synchronization done with
2851 * first out token received from host while corresponding EP is disabled.
2852 *
2853 * Device does not know initial frame in which out token will come. For this
2854 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2855 * getting this interrupt SW starts calculation for next transfer frame.
2856 */
2857static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2858{
2859 struct dwc2_hsotg *hsotg = ep->parent;
2860 int dir_in = ep->dir_in;
2861 u32 doepmsk;
2862
2863 if (dir_in || !ep->isochronous)
2864 return;
2865
2866 if (using_desc_dma(hsotg)) {
2867 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2868 /* Start first ISO Out */
2869 ep->target_frame = hsotg->frame_number;
2870 dwc2_gadget_start_isoc_ddma(ep);
2871 }
2872 return;
2873 }
2874
2875 if (ep->interval > 1 &&
2876 ep->target_frame == TARGET_FRAME_INITIAL) {
2877 u32 ctrl;
2878
2879 ep->target_frame = hsotg->frame_number;
2880 dwc2_gadget_incr_frame_num(ep);
2881
2882 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2883 if (ep->target_frame & 0x1)
2884 ctrl |= DXEPCTL_SETODDFR;
2885 else
2886 ctrl |= DXEPCTL_SETEVENFR;
2887
2888 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2889 }
2890
2891 dwc2_gadget_start_next_request(ep);
2892 doepmsk = dwc2_readl(hsotg, DOEPMSK);
2893 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2894 dwc2_writel(hsotg, doepmsk, DOEPMSK);
2895}
2896
2897/**
2898 * dwc2_gadget_handle_nak - handle NAK interrupt
2899 * @hs_ep: The endpoint on which interrupt is asserted.
2900 *
2901 * This is starting point for ISOC-IN transfer, synchronization done with
2902 * first IN token received from host while corresponding EP is disabled.
2903 *
2904 * Device does not know when first one token will arrive from host. On first
2905 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2906 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2907 * sent in response to that as there was no data in FIFO. SW is basing on this
2908 * interrupt to obtain frame in which token has come and then based on the
2909 * interval calculates next frame for transfer.
2910 */
2911static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2912{
2913 struct dwc2_hsotg *hsotg = hs_ep->parent;
2914 int dir_in = hs_ep->dir_in;
2915
2916 if (!dir_in || !hs_ep->isochronous)
2917 return;
2918
2919 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2920
2921 if (using_desc_dma(hsotg)) {
2922 hs_ep->target_frame = hsotg->frame_number;
2923 dwc2_gadget_incr_frame_num(hs_ep);
2924
2925 /* In service interval mode target_frame must
2926 * be set to last (u)frame of the service interval.
2927 */
2928 if (hsotg->params.service_interval) {
2929 /* Set target_frame to the first (u)frame of
2930 * the service interval
2931 */
2932 hs_ep->target_frame &= ~hs_ep->interval + 1;
2933
2934 /* Set target_frame to the last (u)frame of
2935 * the service interval
2936 */
2937 dwc2_gadget_incr_frame_num(hs_ep);
2938 dwc2_gadget_dec_frame_num_by_one(hs_ep);
2939 }
2940
2941 dwc2_gadget_start_isoc_ddma(hs_ep);
2942 return;
2943 }
2944
2945 hs_ep->target_frame = hsotg->frame_number;
2946 if (hs_ep->interval > 1) {
2947 u32 ctrl = dwc2_readl(hsotg,
2948 DIEPCTL(hs_ep->index));
2949 if (hs_ep->target_frame & 0x1)
2950 ctrl |= DXEPCTL_SETODDFR;
2951 else
2952 ctrl |= DXEPCTL_SETEVENFR;
2953
2954 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
2955 }
2956
2957 dwc2_hsotg_complete_request(hsotg, hs_ep,
2958 get_ep_head(hs_ep), 0);
2959 }
2960
2961 if (!using_desc_dma(hsotg))
2962 dwc2_gadget_incr_frame_num(hs_ep);
2963}
2964
2965/**
2966 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2967 * @hsotg: The driver state
2968 * @idx: The index for the endpoint (0..15)
2969 * @dir_in: Set if this is an IN endpoint
2970 *
2971 * Process and clear any interrupt pending for an individual endpoint
2972 */
2973static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2974 int dir_in)
2975{
2976 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
2977 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2978 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2979 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
2980 u32 ints;
2981
2982 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
2983
2984 /* Clear endpoint interrupts */
2985 dwc2_writel(hsotg, ints, epint_reg);
2986
2987 if (!hs_ep) {
2988 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
2989 __func__, idx, dir_in ? "in" : "out");
2990 return;
2991 }
2992
2993 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2994 __func__, idx, dir_in ? "in" : "out", ints);
2995
2996 /* Don't process XferCompl interrupt if it is a setup packet */
2997 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
2998 ints &= ~DXEPINT_XFERCOMPL;
2999
3000 /*
3001 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
3002 * stage and xfercomplete was generated without SETUP phase done
3003 * interrupt. SW should parse received setup packet only after host's
3004 * exit from setup phase of control transfer.
3005 */
3006 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
3007 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
3008 ints &= ~DXEPINT_XFERCOMPL;
3009
3010 if (ints & DXEPINT_XFERCOMPL) {
3011 dev_dbg(hsotg->dev,
3012 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
3013 __func__, dwc2_readl(hsotg, epctl_reg),
3014 dwc2_readl(hsotg, epsiz_reg));
3015
3016 /* In DDMA handle isochronous requests separately */
3017 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3018 /* XferCompl set along with BNA */
3019 if (!(ints & DXEPINT_BNAINTR))
3020 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
3021 } else if (dir_in) {
3022 /*
3023 * We get OutDone from the FIFO, so we only
3024 * need to look at completing IN requests here
3025 * if operating slave mode
3026 */
3027 if (hs_ep->isochronous && hs_ep->interval > 1)
3028 dwc2_gadget_incr_frame_num(hs_ep);
3029
3030 dwc2_hsotg_complete_in(hsotg, hs_ep);
3031 if (ints & DXEPINT_NAKINTRPT)
3032 ints &= ~DXEPINT_NAKINTRPT;
3033
3034 if (idx == 0 && !hs_ep->req)
3035 dwc2_hsotg_enqueue_setup(hsotg);
3036 } else if (using_dma(hsotg)) {
3037 /*
3038 * We're using DMA, we need to fire an OutDone here
3039 * as we ignore the RXFIFO.
3040 */
3041 if (hs_ep->isochronous && hs_ep->interval > 1)
3042 dwc2_gadget_incr_frame_num(hs_ep);
3043
3044 dwc2_hsotg_handle_outdone(hsotg, idx);
3045 }
3046 }
3047
3048 if (ints & DXEPINT_EPDISBLD)
3049 dwc2_gadget_handle_ep_disabled(hs_ep);
3050
3051 if (ints & DXEPINT_OUTTKNEPDIS)
3052 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3053
3054 if (ints & DXEPINT_NAKINTRPT)
3055 dwc2_gadget_handle_nak(hs_ep);
3056
3057 if (ints & DXEPINT_AHBERR)
3058 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3059
3060 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
3061 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3062
3063 if (using_dma(hsotg) && idx == 0) {
3064 /*
3065 * this is the notification we've received a
3066 * setup packet. In non-DMA mode we'd get this
3067 * from the RXFIFO, instead we need to process
3068 * the setup here.
3069 */
3070
3071 if (dir_in)
3072 WARN_ON_ONCE(1);
3073 else
3074 dwc2_hsotg_handle_outdone(hsotg, 0);
3075 }
3076 }
3077
3078 if (ints & DXEPINT_STSPHSERCVD) {
3079 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3080
3081 /* Safety check EP0 state when STSPHSERCVD asserted */
3082 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3083 /* Move to STATUS IN for DDMA */
3084 if (using_desc_dma(hsotg)) {
3085 if (!hsotg->delayed_status)
3086 dwc2_hsotg_ep0_zlp(hsotg, true);
3087 else
3088 /* In case of 3 stage Control Write with delayed
3089 * status, when Status IN transfer started
3090 * before STSPHSERCVD asserted, NAKSTS bit not
3091 * cleared by CNAK in dwc2_hsotg_start_req()
3092 * function. Clear now NAKSTS to allow complete
3093 * transfer.
3094 */
3095 dwc2_set_bit(hsotg, DIEPCTL(0),
3096 DXEPCTL_CNAK);
3097 }
3098 }
3099
3100 }
3101
3102 if (ints & DXEPINT_BACK2BACKSETUP)
3103 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3104
3105 if (ints & DXEPINT_BNAINTR) {
3106 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3107 if (hs_ep->isochronous)
3108 dwc2_gadget_handle_isoc_bna(hs_ep);
3109 }
3110
3111 if (dir_in && !hs_ep->isochronous) {
3112 /* not sure if this is important, but we'll clear it anyway */
3113 if (ints & DXEPINT_INTKNTXFEMP) {
3114 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3115 __func__, idx);
3116 }
3117
3118 /* this probably means something bad is happening */
3119 if (ints & DXEPINT_INTKNEPMIS) {
3120 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3121 __func__, idx);
3122 }
3123
3124 /* FIFO has space or is empty (see GAHBCFG) */
3125 if (hsotg->dedicated_fifos &&
3126 ints & DXEPINT_TXFEMP) {
3127 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3128 __func__, idx);
3129 if (!using_dma(hsotg))
3130 dwc2_hsotg_trytx(hsotg, hs_ep);
3131 }
3132 }
3133}
3134
3135/**
3136 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3137 * @hsotg: The device state.
3138 *
3139 * Handle updating the device settings after the enumeration phase has
3140 * been completed.
3141 */
3142static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3143{
3144 u32 dsts = dwc2_readl(hsotg, DSTS);
3145 int ep0_mps = 0, ep_mps = 8;
3146
3147 /*
3148 * This should signal the finish of the enumeration phase
3149 * of the USB handshaking, so we should now know what rate
3150 * we connected at.
3151 */
3152
3153 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3154
3155 /*
3156 * note, since we're limited by the size of transfer on EP0, and
3157 * it seems IN transfers must be a even number of packets we do
3158 * not advertise a 64byte MPS on EP0.
3159 */
3160
3161 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3162 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3163 case DSTS_ENUMSPD_FS:
3164 case DSTS_ENUMSPD_FS48:
3165 hsotg->gadget.speed = USB_SPEED_FULL;
3166 ep0_mps = EP0_MPS_LIMIT;
3167 ep_mps = 1023;
3168 break;
3169
3170 case DSTS_ENUMSPD_HS:
3171 hsotg->gadget.speed = USB_SPEED_HIGH;
3172 ep0_mps = EP0_MPS_LIMIT;
3173 ep_mps = 1024;
3174 break;
3175
3176 case DSTS_ENUMSPD_LS:
3177 hsotg->gadget.speed = USB_SPEED_LOW;
3178 ep0_mps = 8;
3179 ep_mps = 8;
3180 /*
3181 * note, we don't actually support LS in this driver at the
3182 * moment, and the documentation seems to imply that it isn't
3183 * supported by the PHYs on some of the devices.
3184 */
3185 break;
3186 }
3187 dev_info(hsotg->dev, "new device is %s\n",
3188 usb_speed_string(hsotg->gadget.speed));
3189
3190 /*
3191 * we should now know the maximum packet size for an
3192 * endpoint, so set the endpoints to a default value.
3193 */
3194
3195 if (ep0_mps) {
3196 int i;
3197 /* Initialize ep0 for both in and out directions */
3198 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3199 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3200 for (i = 1; i < hsotg->num_of_eps; i++) {
3201 if (hsotg->eps_in[i])
3202 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3203 0, 1);
3204 if (hsotg->eps_out[i])
3205 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3206 0, 0);
3207 }
3208 }
3209
3210 /* ensure after enumeration our EP0 is active */
3211
3212 dwc2_hsotg_enqueue_setup(hsotg);
3213
3214 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3215 dwc2_readl(hsotg, DIEPCTL0),
3216 dwc2_readl(hsotg, DOEPCTL0));
3217}
3218
3219/**
3220 * kill_all_requests - remove all requests from the endpoint's queue
3221 * @hsotg: The device state.
3222 * @ep: The endpoint the requests may be on.
3223 * @result: The result code to use.
3224 *
3225 * Go through the requests on the given endpoint and mark them
3226 * completed with the given result code.
3227 */
3228static void kill_all_requests(struct dwc2_hsotg *hsotg,
3229 struct dwc2_hsotg_ep *ep,
3230 int result)
3231{
3232 unsigned int size;
3233
3234 ep->req = NULL;
3235
3236 while (!list_empty(&ep->queue)) {
3237 struct dwc2_hsotg_req *req = get_ep_head(ep);
3238
3239 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3240 }
3241
3242 if (!hsotg->dedicated_fifos)
3243 return;
3244 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3245 if (size < ep->fifo_size)
3246 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3247}
3248
3249/**
3250 * dwc2_hsotg_disconnect - disconnect service
3251 * @hsotg: The device state.
3252 *
3253 * The device has been disconnected. Remove all current
3254 * transactions and signal the gadget driver that this
3255 * has happened.
3256 */
3257void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3258{
3259 unsigned int ep;
3260
3261 if (!hsotg->connected)
3262 return;
3263
3264 hsotg->connected = 0;
3265 hsotg->test_mode = 0;
3266
3267 /* all endpoints should be shutdown */
3268 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3269 if (hsotg->eps_in[ep])
3270 kill_all_requests(hsotg, hsotg->eps_in[ep],
3271 -ESHUTDOWN);
3272 if (hsotg->eps_out[ep])
3273 kill_all_requests(hsotg, hsotg->eps_out[ep],
3274 -ESHUTDOWN);
3275 }
3276
3277 call_gadget(hsotg, disconnect);
3278 hsotg->lx_state = DWC2_L3;
3279
3280 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3281}
3282
3283/**
3284 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3285 * @hsotg: The device state:
3286 * @periodic: True if this is a periodic FIFO interrupt
3287 */
3288static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3289{
3290 struct dwc2_hsotg_ep *ep;
3291 int epno, ret;
3292
3293 /* look through for any more data to transmit */
3294 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3295 ep = index_to_ep(hsotg, epno, 1);
3296
3297 if (!ep)
3298 continue;
3299
3300 if (!ep->dir_in)
3301 continue;
3302
3303 if ((periodic && !ep->periodic) ||
3304 (!periodic && ep->periodic))
3305 continue;
3306
3307 ret = dwc2_hsotg_trytx(hsotg, ep);
3308 if (ret < 0)
3309 break;
3310 }
3311}
3312
3313/* IRQ flags which will trigger a retry around the IRQ loop */
3314#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3315 GINTSTS_PTXFEMP | \
3316 GINTSTS_RXFLVL)
3317
3318static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3319/**
3320 * dwc2_hsotg_core_init - issue softreset to the core
3321 * @hsotg: The device state
3322 * @is_usb_reset: Usb resetting flag
3323 *
3324 * Issue a soft reset to the core, and await the core finishing it.
3325 */
3326void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3327 bool is_usb_reset)
3328{
3329 u32 intmsk;
3330 u32 val;
3331 u32 usbcfg;
3332 u32 dcfg = 0;
3333 int ep;
3334
3335 /* Kill any ep0 requests as controller will be reinitialized */
3336 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3337
3338 if (!is_usb_reset) {
3339 if (dwc2_core_reset(hsotg, true))
3340 return;
3341 } else {
3342 /* all endpoints should be shutdown */
3343 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3344 if (hsotg->eps_in[ep])
3345 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3346 if (hsotg->eps_out[ep])
3347 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3348 }
3349 }
3350
3351 /*
3352 * we must now enable ep0 ready for host detection and then
3353 * set configuration.
3354 */
3355
3356 /* keep other bits untouched (so e.g. forced modes are not lost) */
3357 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3358 usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3359 usbcfg |= GUSBCFG_TOUTCAL(7);
3360
3361 /* remove the HNP/SRP and set the PHY */
3362 usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3363 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3364
3365 dwc2_phy_init(hsotg, true);
3366
3367 dwc2_hsotg_init_fifo(hsotg);
3368
3369 if (!is_usb_reset)
3370 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3371
3372 dcfg |= DCFG_EPMISCNT(1);
3373
3374 switch (hsotg->params.speed) {
3375 case DWC2_SPEED_PARAM_LOW:
3376 dcfg |= DCFG_DEVSPD_LS;
3377 break;
3378 case DWC2_SPEED_PARAM_FULL:
3379 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3380 dcfg |= DCFG_DEVSPD_FS48;
3381 else
3382 dcfg |= DCFG_DEVSPD_FS;
3383 break;
3384 default:
3385 dcfg |= DCFG_DEVSPD_HS;
3386 }
3387
3388 if (hsotg->params.ipg_isoc_en)
3389 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3390
3391 dwc2_writel(hsotg, dcfg, DCFG);
3392
3393 /* Clear any pending OTG interrupts */
3394 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3395
3396 /* Clear any pending interrupts */
3397 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3398 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3399 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3400 GINTSTS_USBRST | GINTSTS_RESETDET |
3401 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3402 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3403 GINTSTS_LPMTRANRCVD;
3404
3405 if (!using_desc_dma(hsotg))
3406 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3407
3408 if (!hsotg->params.external_id_pin_ctl)
3409 intmsk |= GINTSTS_CONIDSTSCHNG;
3410
3411 dwc2_writel(hsotg, intmsk, GINTMSK);
3412
3413 if (using_dma(hsotg)) {
3414 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3415 hsotg->params.ahbcfg,
3416 GAHBCFG);
3417
3418 /* Set DDMA mode support in the core if needed */
3419 if (using_desc_dma(hsotg))
3420 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3421
3422 } else {
3423 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3424 (GAHBCFG_NP_TXF_EMP_LVL |
3425 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3426 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3427 }
3428
3429 /*
3430 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3431 * when we have no data to transfer. Otherwise we get being flooded by
3432 * interrupts.
3433 */
3434
3435 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3436 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3437 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3438 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3439 DIEPMSK);
3440
3441 /*
3442 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3443 * DMA mode we may need this and StsPhseRcvd.
3444 */
3445 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3446 DOEPMSK_STSPHSERCVDMSK) : 0) |
3447 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3448 DOEPMSK_SETUPMSK,
3449 DOEPMSK);
3450
3451 /* Enable BNA interrupt for DDMA */
3452 if (using_desc_dma(hsotg)) {
3453 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3454 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3455 }
3456
3457 /* Enable Service Interval mode if supported */
3458 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3459 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3460
3461 dwc2_writel(hsotg, 0, DAINTMSK);
3462
3463 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3464 dwc2_readl(hsotg, DIEPCTL0),
3465 dwc2_readl(hsotg, DOEPCTL0));
3466
3467 /* enable in and out endpoint interrupts */
3468 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3469
3470 /*
3471 * Enable the RXFIFO when in slave mode, as this is how we collect
3472 * the data. In DMA mode, we get events from the FIFO but also
3473 * things we cannot process, so do not use it.
3474 */
3475 if (!using_dma(hsotg))
3476 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3477
3478 /* Enable interrupts for EP0 in and out */
3479 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3480 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3481
3482 if (!is_usb_reset) {
3483 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3484 udelay(10); /* see openiboot */
3485 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3486 }
3487
3488 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3489
3490 /*
3491 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3492 * writing to the EPCTL register..
3493 */
3494
3495 /* set to read 1 8byte packet */
3496 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3497 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3498
3499 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3500 DXEPCTL_CNAK | DXEPCTL_EPENA |
3501 DXEPCTL_USBACTEP,
3502 DOEPCTL0);
3503
3504 /* enable, but don't activate EP0in */
3505 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3506 DXEPCTL_USBACTEP, DIEPCTL0);
3507
3508 /* clear global NAKs */
3509 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3510 if (!is_usb_reset)
3511 val |= DCTL_SFTDISCON;
3512 dwc2_set_bit(hsotg, DCTL, val);
3513
3514 /* configure the core to support LPM */
3515 dwc2_gadget_init_lpm(hsotg);
3516
3517 /* program GREFCLK register if needed */
3518 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3519 dwc2_gadget_program_ref_clk(hsotg);
3520
3521 /* must be at-least 3ms to allow bus to see disconnect */
3522 mdelay(3);
3523
3524 hsotg->lx_state = DWC2_L0;
3525
3526 dwc2_hsotg_enqueue_setup(hsotg);
3527
3528 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3529 dwc2_readl(hsotg, DIEPCTL0),
3530 dwc2_readl(hsotg, DOEPCTL0));
3531}
3532
3533static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3534{
3535 /* set the soft-disconnect bit */
3536 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3537}
3538
3539void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3540{
3541 /* remove the soft-disconnect and let's go */
3542 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3543}
3544
3545/**
3546 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3547 * @hsotg: The device state:
3548 *
3549 * This interrupt indicates one of the following conditions occurred while
3550 * transmitting an ISOC transaction.
3551 * - Corrupted IN Token for ISOC EP.
3552 * - Packet not complete in FIFO.
3553 *
3554 * The following actions will be taken:
3555 * - Determine the EP
3556 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3557 */
3558static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3559{
3560 struct dwc2_hsotg_ep *hs_ep;
3561 u32 epctrl;
3562 u32 daintmsk;
3563 u32 idx;
3564
3565 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3566
3567 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3568
3569 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3570 hs_ep = hsotg->eps_in[idx];
3571 /* Proceed only unmasked ISOC EPs */
3572 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3573 continue;
3574
3575 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3576 if ((epctrl & DXEPCTL_EPENA) &&
3577 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3578 epctrl |= DXEPCTL_SNAK;
3579 epctrl |= DXEPCTL_EPDIS;
3580 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3581 }
3582 }
3583
3584 /* Clear interrupt */
3585 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3586}
3587
3588/**
3589 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3590 * @hsotg: The device state:
3591 *
3592 * This interrupt indicates one of the following conditions occurred while
3593 * transmitting an ISOC transaction.
3594 * - Corrupted OUT Token for ISOC EP.
3595 * - Packet not complete in FIFO.
3596 *
3597 * The following actions will be taken:
3598 * - Determine the EP
3599 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3600 */
3601static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3602{
3603 u32 gintsts;
3604 u32 gintmsk;
3605 u32 daintmsk;
3606 u32 epctrl;
3607 struct dwc2_hsotg_ep *hs_ep;
3608 int idx;
3609
3610 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3611
3612 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3613 daintmsk >>= DAINT_OUTEP_SHIFT;
3614
3615 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3616 hs_ep = hsotg->eps_out[idx];
3617 /* Proceed only unmasked ISOC EPs */
3618 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3619 continue;
3620
3621 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3622 if ((epctrl & DXEPCTL_EPENA) &&
3623 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3624 /* Unmask GOUTNAKEFF interrupt */
3625 gintmsk = dwc2_readl(hsotg, GINTMSK);
3626 gintmsk |= GINTSTS_GOUTNAKEFF;
3627 dwc2_writel(hsotg, gintmsk, GINTMSK);
3628
3629 gintsts = dwc2_readl(hsotg, GINTSTS);
3630 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3631 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3632 break;
3633 }
3634 }
3635 }
3636
3637 /* Clear interrupt */
3638 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3639}
3640
3641/**
3642 * dwc2_hsotg_irq - handle device interrupt
3643 * @irq: The IRQ number triggered
3644 * @pw: The pw value when registered the handler.
3645 */
3646static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3647{
3648 struct dwc2_hsotg *hsotg = pw;
3649 int retry_count = 8;
3650 u32 gintsts;
3651 u32 gintmsk;
3652
3653 if (!dwc2_is_device_mode(hsotg))
3654 return IRQ_NONE;
3655
3656 spin_lock(&hsotg->lock);
3657irq_retry:
3658 gintsts = dwc2_readl(hsotg, GINTSTS);
3659 gintmsk = dwc2_readl(hsotg, GINTMSK);
3660
3661 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3662 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3663
3664 gintsts &= gintmsk;
3665
3666 if (gintsts & GINTSTS_RESETDET) {
3667 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3668
3669 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3670
3671 /* This event must be used only if controller is suspended */
3672 if (hsotg->lx_state == DWC2_L2) {
3673 dwc2_exit_partial_power_down(hsotg, true);
3674 hsotg->lx_state = DWC2_L0;
3675 }
3676 }
3677
3678 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3679 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3680 u32 connected = hsotg->connected;
3681
3682 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3683 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3684 dwc2_readl(hsotg, GNPTXSTS));
3685
3686 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3687
3688 /* Report disconnection if it is not already done. */
3689 dwc2_hsotg_disconnect(hsotg);
3690
3691 /* Reset device address to zero */
3692 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3693
3694 if (usb_status & GOTGCTL_BSESVLD && connected)
3695 dwc2_hsotg_core_init_disconnected(hsotg, true);
3696 }
3697
3698 if (gintsts & GINTSTS_ENUMDONE) {
3699 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3700
3701 dwc2_hsotg_irq_enumdone(hsotg);
3702 }
3703
3704 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3705 u32 daint = dwc2_readl(hsotg, DAINT);
3706 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3707 u32 daint_out, daint_in;
3708 int ep;
3709
3710 daint &= daintmsk;
3711 daint_out = daint >> DAINT_OUTEP_SHIFT;
3712 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3713
3714 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3715
3716 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3717 ep++, daint_out >>= 1) {
3718 if (daint_out & 1)
3719 dwc2_hsotg_epint(hsotg, ep, 0);
3720 }
3721
3722 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3723 ep++, daint_in >>= 1) {
3724 if (daint_in & 1)
3725 dwc2_hsotg_epint(hsotg, ep, 1);
3726 }
3727 }
3728
3729 /* check both FIFOs */
3730
3731 if (gintsts & GINTSTS_NPTXFEMP) {
3732 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3733
3734 /*
3735 * Disable the interrupt to stop it happening again
3736 * unless one of these endpoint routines decides that
3737 * it needs re-enabling
3738 */
3739
3740 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3741 dwc2_hsotg_irq_fifoempty(hsotg, false);
3742 }
3743
3744 if (gintsts & GINTSTS_PTXFEMP) {
3745 dev_dbg(hsotg->dev, "PTxFEmp\n");
3746
3747 /* See note in GINTSTS_NPTxFEmp */
3748
3749 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3750 dwc2_hsotg_irq_fifoempty(hsotg, true);
3751 }
3752
3753 if (gintsts & GINTSTS_RXFLVL) {
3754 /*
3755 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3756 * we need to retry dwc2_hsotg_handle_rx if this is still
3757 * set.
3758 */
3759
3760 dwc2_hsotg_handle_rx(hsotg);
3761 }
3762
3763 if (gintsts & GINTSTS_ERLYSUSP) {
3764 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3765 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3766 }
3767
3768 /*
3769 * these next two seem to crop-up occasionally causing the core
3770 * to shutdown the USB transfer, so try clearing them and logging
3771 * the occurrence.
3772 */
3773
3774 if (gintsts & GINTSTS_GOUTNAKEFF) {
3775 u8 idx;
3776 u32 epctrl;
3777 u32 gintmsk;
3778 u32 daintmsk;
3779 struct dwc2_hsotg_ep *hs_ep;
3780
3781 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3782 daintmsk >>= DAINT_OUTEP_SHIFT;
3783 /* Mask this interrupt */
3784 gintmsk = dwc2_readl(hsotg, GINTMSK);
3785 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3786 dwc2_writel(hsotg, gintmsk, GINTMSK);
3787
3788 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3789 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3790 hs_ep = hsotg->eps_out[idx];
3791 /* Proceed only unmasked ISOC EPs */
3792 if (BIT(idx) & ~daintmsk)
3793 continue;
3794
3795 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3796
3797 //ISOC Ep's only
3798 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3799 epctrl |= DXEPCTL_SNAK;
3800 epctrl |= DXEPCTL_EPDIS;
3801 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3802 continue;
3803 }
3804
3805 //Non-ISOC EP's
3806 if (hs_ep->halted) {
3807 if (!(epctrl & DXEPCTL_EPENA))
3808 epctrl |= DXEPCTL_EPENA;
3809 epctrl |= DXEPCTL_EPDIS;
3810 epctrl |= DXEPCTL_STALL;
3811 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3812 }
3813 }
3814
3815 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3816 }
3817
3818 if (gintsts & GINTSTS_GINNAKEFF) {
3819 dev_info(hsotg->dev, "GINNakEff triggered\n");
3820
3821 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3822
3823 dwc2_hsotg_dump(hsotg);
3824 }
3825
3826 if (gintsts & GINTSTS_INCOMPL_SOIN)
3827 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3828
3829 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3830 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3831
3832 /*
3833 * if we've had fifo events, we should try and go around the
3834 * loop again to see if there's any point in returning yet.
3835 */
3836
3837 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3838 goto irq_retry;
3839
3840 /* Check WKUP_ALERT interrupt*/
3841 if (hsotg->params.service_interval)
3842 dwc2_gadget_wkup_alert_handler(hsotg);
3843
3844 spin_unlock(&hsotg->lock);
3845
3846 return IRQ_HANDLED;
3847}
3848
3849static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3850 struct dwc2_hsotg_ep *hs_ep)
3851{
3852 u32 epctrl_reg;
3853 u32 epint_reg;
3854
3855 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3856 DOEPCTL(hs_ep->index);
3857 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3858 DOEPINT(hs_ep->index);
3859
3860 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3861 hs_ep->name);
3862
3863 if (hs_ep->dir_in) {
3864 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3865 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3866 /* Wait for Nak effect */
3867 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3868 DXEPINT_INEPNAKEFF, 100))
3869 dev_warn(hsotg->dev,
3870 "%s: timeout DIEPINT.NAKEFF\n",
3871 __func__);
3872 } else {
3873 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3874 /* Wait for Nak effect */
3875 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3876 GINTSTS_GINNAKEFF, 100))
3877 dev_warn(hsotg->dev,
3878 "%s: timeout GINTSTS.GINNAKEFF\n",
3879 __func__);
3880 }
3881 } else {
3882 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3883 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3884
3885 /* Wait for global nak to take effect */
3886 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3887 GINTSTS_GOUTNAKEFF, 100))
3888 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3889 __func__);
3890 }
3891
3892 /* Disable ep */
3893 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3894
3895 /* Wait for ep to be disabled */
3896 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3897 dev_warn(hsotg->dev,
3898 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3899
3900 /* Clear EPDISBLD interrupt */
3901 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3902
3903 if (hs_ep->dir_in) {
3904 unsigned short fifo_index;
3905
3906 if (hsotg->dedicated_fifos || hs_ep->periodic)
3907 fifo_index = hs_ep->fifo_index;
3908 else
3909 fifo_index = 0;
3910
3911 /* Flush TX FIFO */
3912 dwc2_flush_tx_fifo(hsotg, fifo_index);
3913
3914 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3915 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3916 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3917
3918 } else {
3919 /* Remove global NAKs */
3920 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
3921 }
3922}
3923
3924/**
3925 * dwc2_hsotg_ep_enable - enable the given endpoint
3926 * @ep: The USB endpint to configure
3927 * @desc: The USB endpoint descriptor to configure with.
3928 *
3929 * This is called from the USB gadget code's usb_ep_enable().
3930 */
3931static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3932 const struct usb_endpoint_descriptor *desc)
3933{
3934 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3935 struct dwc2_hsotg *hsotg = hs_ep->parent;
3936 unsigned long flags;
3937 unsigned int index = hs_ep->index;
3938 u32 epctrl_reg;
3939 u32 epctrl;
3940 u32 mps;
3941 u32 mc;
3942 u32 mask;
3943 unsigned int dir_in;
3944 unsigned int i, val, size;
3945 int ret = 0;
3946 unsigned char ep_type;
3947 int desc_num;
3948
3949 dev_dbg(hsotg->dev,
3950 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3951 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
3952 desc->wMaxPacketSize, desc->bInterval);
3953
3954 /* not to be called for EP0 */
3955 if (index == 0) {
3956 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
3957 return -EINVAL;
3958 }
3959
3960 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
3961 if (dir_in != hs_ep->dir_in) {
3962 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
3963 return -EINVAL;
3964 }
3965
3966 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
3967 mps = usb_endpoint_maxp(desc);
3968 mc = usb_endpoint_maxp_mult(desc);
3969
3970 /* ISOC IN in DDMA supported bInterval up to 10 */
3971 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
3972 dir_in && desc->bInterval > 10) {
3973 dev_err(hsotg->dev,
3974 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
3975 return -EINVAL;
3976 }
3977
3978 /* High bandwidth ISOC OUT in DDMA not supported */
3979 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
3980 !dir_in && mc > 1) {
3981 dev_err(hsotg->dev,
3982 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
3983 return -EINVAL;
3984 }
3985
3986 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
3987
3988 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
3989 epctrl = dwc2_readl(hsotg, epctrl_reg);
3990
3991 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
3992 __func__, epctrl, epctrl_reg);
3993
3994 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
3995 desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
3996 else
3997 desc_num = MAX_DMA_DESC_NUM_GENERIC;
3998
3999 /* Allocate DMA descriptor chain for non-ctrl endpoints */
4000 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
4001 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
4002 desc_num * sizeof(struct dwc2_dma_desc),
4003 &hs_ep->desc_list_dma, GFP_ATOMIC);
4004 if (!hs_ep->desc_list) {
4005 ret = -ENOMEM;
4006 goto error2;
4007 }
4008 }
4009
4010 spin_lock_irqsave(&hsotg->lock, flags);
4011
4012 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
4013 epctrl |= DXEPCTL_MPS(mps);
4014
4015 /*
4016 * mark the endpoint as active, otherwise the core may ignore
4017 * transactions entirely for this endpoint
4018 */
4019 epctrl |= DXEPCTL_USBACTEP;
4020
4021 /* update the endpoint state */
4022 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
4023
4024 /* default, set to non-periodic */
4025 hs_ep->isochronous = 0;
4026 hs_ep->periodic = 0;
4027 hs_ep->halted = 0;
4028 hs_ep->interval = desc->bInterval;
4029
4030 switch (ep_type) {
4031 case USB_ENDPOINT_XFER_ISOC:
4032 epctrl |= DXEPCTL_EPTYPE_ISO;
4033 epctrl |= DXEPCTL_SETEVENFR;
4034 hs_ep->isochronous = 1;
4035 hs_ep->interval = 1 << (desc->bInterval - 1);
4036 hs_ep->target_frame = TARGET_FRAME_INITIAL;
4037 hs_ep->next_desc = 0;
4038 hs_ep->compl_desc = 0;
4039 if (dir_in) {
4040 hs_ep->periodic = 1;
4041 mask = dwc2_readl(hsotg, DIEPMSK);
4042 mask |= DIEPMSK_NAKMSK;
4043 dwc2_writel(hsotg, mask, DIEPMSK);
4044 } else {
4045 mask = dwc2_readl(hsotg, DOEPMSK);
4046 mask |= DOEPMSK_OUTTKNEPDISMSK;
4047 dwc2_writel(hsotg, mask, DOEPMSK);
4048 }
4049 break;
4050
4051 case USB_ENDPOINT_XFER_BULK:
4052 epctrl |= DXEPCTL_EPTYPE_BULK;
4053 break;
4054
4055 case USB_ENDPOINT_XFER_INT:
4056 if (dir_in)
4057 hs_ep->periodic = 1;
4058
4059 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4060 hs_ep->interval = 1 << (desc->bInterval - 1);
4061
4062 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
4063 break;
4064
4065 case USB_ENDPOINT_XFER_CONTROL:
4066 epctrl |= DXEPCTL_EPTYPE_CONTROL;
4067 break;
4068 }
4069
4070 /*
4071 * if the hardware has dedicated fifos, we must give each IN EP
4072 * a unique tx-fifo even if it is non-periodic.
4073 */
4074 if (dir_in && hsotg->dedicated_fifos) {
4075 unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
4076 u32 fifo_index = 0;
4077 u32 fifo_size = UINT_MAX;
4078
4079 size = hs_ep->ep.maxpacket * hs_ep->mc;
4080 for (i = 1; i <= fifo_count; ++i) {
4081 if (hsotg->fifo_map & (1 << i))
4082 continue;
4083 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4084 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
4085 if (val < size)
4086 continue;
4087 /* Search for smallest acceptable fifo */
4088 if (val < fifo_size) {
4089 fifo_size = val;
4090 fifo_index = i;
4091 }
4092 }
4093 if (!fifo_index) {
4094 dev_err(hsotg->dev,
4095 "%s: No suitable fifo found\n", __func__);
4096 ret = -ENOMEM;
4097 goto error1;
4098 }
4099 epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
4100 hsotg->fifo_map |= 1 << fifo_index;
4101 epctrl |= DXEPCTL_TXFNUM(fifo_index);
4102 hs_ep->fifo_index = fifo_index;
4103 hs_ep->fifo_size = fifo_size;
4104 }
4105
4106 /* for non control endpoints, set PID to D0 */
4107 if (index && !hs_ep->isochronous)
4108 epctrl |= DXEPCTL_SETD0PID;
4109
4110 /* WA for Full speed ISOC IN in DDMA mode.
4111 * By Clear NAK status of EP, core will send ZLP
4112 * to IN token and assert NAK interrupt relying
4113 * on TxFIFO status only
4114 */
4115
4116 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4117 hs_ep->isochronous && dir_in) {
4118 /* The WA applies only to core versions from 2.72a
4119 * to 4.00a (including both). Also for FS_IOT_1.00a
4120 * and HS_IOT_1.00a.
4121 */
4122 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4123
4124 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
4125 gsnpsid <= DWC2_CORE_REV_4_00a) ||
4126 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
4127 gsnpsid == DWC2_HS_IOT_REV_1_00a)
4128 epctrl |= DXEPCTL_CNAK;
4129 }
4130
4131 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4132 __func__, epctrl);
4133
4134 dwc2_writel(hsotg, epctrl, epctrl_reg);
4135 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4136 __func__, dwc2_readl(hsotg, epctrl_reg));
4137
4138 /* enable the endpoint interrupt */
4139 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4140
4141error1:
4142 spin_unlock_irqrestore(&hsotg->lock, flags);
4143
4144error2:
4145 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4146 dmam_free_coherent(hsotg->dev, desc_num *
4147 sizeof(struct dwc2_dma_desc),
4148 hs_ep->desc_list, hs_ep->desc_list_dma);
4149 hs_ep->desc_list = NULL;
4150 }
4151
4152 return ret;
4153}
4154
4155/**
4156 * dwc2_hsotg_ep_disable - disable given endpoint
4157 * @ep: The endpoint to disable.
4158 */
4159static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4160{
4161 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4162 struct dwc2_hsotg *hsotg = hs_ep->parent;
4163 int dir_in = hs_ep->dir_in;
4164 int index = hs_ep->index;
4165 u32 epctrl_reg;
4166 u32 ctrl;
4167
4168 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4169
4170 if (ep == &hsotg->eps_out[0]->ep) {
4171 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4172 return -EINVAL;
4173 }
4174
4175 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4176 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4177 return -EINVAL;
4178 }
4179
4180 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4181
4182 ctrl = dwc2_readl(hsotg, epctrl_reg);
4183
4184 if (ctrl & DXEPCTL_EPENA)
4185 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4186
4187 ctrl &= ~DXEPCTL_EPENA;
4188 ctrl &= ~DXEPCTL_USBACTEP;
4189 ctrl |= DXEPCTL_SNAK;
4190
4191 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4192 dwc2_writel(hsotg, ctrl, epctrl_reg);
4193
4194 /* disable endpoint interrupts */
4195 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4196
4197 /* terminate all requests with shutdown */
4198 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4199
4200 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4201 hs_ep->fifo_index = 0;
4202 hs_ep->fifo_size = 0;
4203
4204 return 0;
4205}
4206
4207static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
4208{
4209 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4210 struct dwc2_hsotg *hsotg = hs_ep->parent;
4211 unsigned long flags;
4212 int ret;
4213
4214 spin_lock_irqsave(&hsotg->lock, flags);
4215 ret = dwc2_hsotg_ep_disable(ep);
4216 spin_unlock_irqrestore(&hsotg->lock, flags);
4217 return ret;
4218}
4219
4220/**
4221 * on_list - check request is on the given endpoint
4222 * @ep: The endpoint to check.
4223 * @test: The request to test if it is on the endpoint.
4224 */
4225static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4226{
4227 struct dwc2_hsotg_req *req, *treq;
4228
4229 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4230 if (req == test)
4231 return true;
4232 }
4233
4234 return false;
4235}
4236
4237/**
4238 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4239 * @ep: The endpoint to dequeue.
4240 * @req: The request to be removed from a queue.
4241 */
4242static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4243{
4244 struct dwc2_hsotg_req *hs_req = our_req(req);
4245 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4246 struct dwc2_hsotg *hs = hs_ep->parent;
4247 unsigned long flags;
4248
4249 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4250
4251 spin_lock_irqsave(&hs->lock, flags);
4252
4253 if (!on_list(hs_ep, hs_req)) {
4254 spin_unlock_irqrestore(&hs->lock, flags);
4255 return -EINVAL;
4256 }
4257
4258 /* Dequeue already started request */
4259 if (req == &hs_ep->req->req)
4260 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4261
4262 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4263 spin_unlock_irqrestore(&hs->lock, flags);
4264
4265 return 0;
4266}
4267
4268/**
4269 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4270 * @ep: The endpoint to set halt.
4271 * @value: Set or unset the halt.
4272 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4273 * the endpoint is busy processing requests.
4274 *
4275 * We need to stall the endpoint immediately if request comes from set_feature
4276 * protocol command handler.
4277 */
4278static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4279{
4280 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4281 struct dwc2_hsotg *hs = hs_ep->parent;
4282 int index = hs_ep->index;
4283 u32 epreg;
4284 u32 epctl;
4285 u32 xfertype;
4286
4287 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4288
4289 if (index == 0) {
4290 if (value)
4291 dwc2_hsotg_stall_ep0(hs);
4292 else
4293 dev_warn(hs->dev,
4294 "%s: can't clear halt on ep0\n", __func__);
4295 return 0;
4296 }
4297
4298 if (hs_ep->isochronous) {
4299 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4300 return -EINVAL;
4301 }
4302
4303 if (!now && value && !list_empty(&hs_ep->queue)) {
4304 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4305 ep->name);
4306 return -EAGAIN;
4307 }
4308
4309 if (hs_ep->dir_in) {
4310 epreg = DIEPCTL(index);
4311 epctl = dwc2_readl(hs, epreg);
4312
4313 if (value) {
4314 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4315 if (epctl & DXEPCTL_EPENA)
4316 epctl |= DXEPCTL_EPDIS;
4317 } else {
4318 epctl &= ~DXEPCTL_STALL;
4319 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4320 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4321 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4322 epctl |= DXEPCTL_SETD0PID;
4323 }
4324 dwc2_writel(hs, epctl, epreg);
4325 } else {
4326 epreg = DOEPCTL(index);
4327 epctl = dwc2_readl(hs, epreg);
4328
4329 if (value) {
4330 if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
4331 dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
4332 // STALL bit will be set in GOUTNAKEFF interrupt handler
4333 } else {
4334 epctl &= ~DXEPCTL_STALL;
4335 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4336 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4337 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4338 epctl |= DXEPCTL_SETD0PID;
4339 dwc2_writel(hs, epctl, epreg);
4340 }
4341 }
4342
4343 hs_ep->halted = value;
4344 return 0;
4345}
4346
4347/**
4348 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4349 * @ep: The endpoint to set halt.
4350 * @value: Set or unset the halt.
4351 */
4352static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4353{
4354 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4355 struct dwc2_hsotg *hs = hs_ep->parent;
4356 unsigned long flags = 0;
4357 int ret = 0;
4358
4359 spin_lock_irqsave(&hs->lock, flags);
4360 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4361 spin_unlock_irqrestore(&hs->lock, flags);
4362
4363 return ret;
4364}
4365
4366static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4367 .enable = dwc2_hsotg_ep_enable,
4368 .disable = dwc2_hsotg_ep_disable_lock,
4369 .alloc_request = dwc2_hsotg_ep_alloc_request,
4370 .free_request = dwc2_hsotg_ep_free_request,
4371 .queue = dwc2_hsotg_ep_queue_lock,
4372 .dequeue = dwc2_hsotg_ep_dequeue,
4373 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4374 /* note, don't believe we have any call for the fifo routines */
4375};
4376
4377/**
4378 * dwc2_hsotg_init - initialize the usb core
4379 * @hsotg: The driver state
4380 */
4381static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4382{
4383 /* unmask subset of endpoint interrupts */
4384
4385 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4386 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4387 DIEPMSK);
4388
4389 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4390 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4391 DOEPMSK);
4392
4393 dwc2_writel(hsotg, 0, DAINTMSK);
4394
4395 /* Be in disconnected state until gadget is registered */
4396 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4397
4398 /* setup fifos */
4399
4400 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4401 dwc2_readl(hsotg, GRXFSIZ),
4402 dwc2_readl(hsotg, GNPTXFSIZ));
4403
4404 dwc2_hsotg_init_fifo(hsotg);
4405
4406 if (using_dma(hsotg))
4407 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4408}
4409
4410/**
4411 * dwc2_hsotg_udc_start - prepare the udc for work
4412 * @gadget: The usb gadget state
4413 * @driver: The usb gadget driver
4414 *
4415 * Perform initialization to prepare udc device and driver
4416 * to work.
4417 */
4418static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4419 struct usb_gadget_driver *driver)
4420{
4421 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4422 unsigned long flags;
4423 int ret;
4424
4425 if (!hsotg) {
4426 pr_err("%s: called with no device\n", __func__);
4427 return -ENODEV;
4428 }
4429
4430 if (!driver) {
4431 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4432 return -EINVAL;
4433 }
4434
4435 if (driver->max_speed < USB_SPEED_FULL)
4436 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4437
4438 if (!driver->setup) {
4439 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4440 return -EINVAL;
4441 }
4442
4443 WARN_ON(hsotg->driver);
4444
4445 driver->driver.bus = NULL;
4446 hsotg->driver = driver;
4447 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4448 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4449
4450 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4451 ret = dwc2_lowlevel_hw_enable(hsotg);
4452 if (ret)
4453 goto err;
4454 }
4455
4456 if (!IS_ERR_OR_NULL(hsotg->uphy))
4457 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4458
4459 spin_lock_irqsave(&hsotg->lock, flags);
4460 if (dwc2_hw_is_device(hsotg)) {
4461 dwc2_hsotg_init(hsotg);
4462 dwc2_hsotg_core_init_disconnected(hsotg, false);
4463 }
4464
4465 hsotg->enabled = 0;
4466 spin_unlock_irqrestore(&hsotg->lock, flags);
4467
4468 gadget->sg_supported = using_desc_dma(hsotg);
4469 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4470
4471 return 0;
4472
4473err:
4474 hsotg->driver = NULL;
4475 return ret;
4476}
4477
4478/**
4479 * dwc2_hsotg_udc_stop - stop the udc
4480 * @gadget: The usb gadget state
4481 *
4482 * Stop udc hw block and stay tunned for future transmissions
4483 */
4484static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4485{
4486 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4487 unsigned long flags = 0;
4488 int ep;
4489
4490 if (!hsotg)
4491 return -ENODEV;
4492
4493 /* all endpoints should be shutdown */
4494 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4495 if (hsotg->eps_in[ep])
4496 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4497 if (hsotg->eps_out[ep])
4498 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4499 }
4500
4501 spin_lock_irqsave(&hsotg->lock, flags);
4502
4503 hsotg->driver = NULL;
4504 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4505 hsotg->enabled = 0;
4506
4507 spin_unlock_irqrestore(&hsotg->lock, flags);
4508
4509 if (!IS_ERR_OR_NULL(hsotg->uphy))
4510 otg_set_peripheral(hsotg->uphy->otg, NULL);
4511
4512 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4513 dwc2_lowlevel_hw_disable(hsotg);
4514
4515 return 0;
4516}
4517
4518/**
4519 * dwc2_hsotg_gadget_getframe - read the frame number
4520 * @gadget: The usb gadget state
4521 *
4522 * Read the {micro} frame number
4523 */
4524static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4525{
4526 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4527}
4528
4529/**
4530 * dwc2_hsotg_set_selfpowered - set if device is self/bus powered
4531 * @gadget: The usb gadget state
4532 * @is_selfpowered: Whether the device is self-powered
4533 *
4534 * Set if the device is self or bus powered.
4535 */
4536static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
4537 int is_selfpowered)
4538{
4539 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4540 unsigned long flags;
4541
4542 spin_lock_irqsave(&hsotg->lock, flags);
4543 gadget->is_selfpowered = !!is_selfpowered;
4544 spin_unlock_irqrestore(&hsotg->lock, flags);
4545
4546 return 0;
4547}
4548
4549/**
4550 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4551 * @gadget: The usb gadget state
4552 * @is_on: Current state of the USB PHY
4553 *
4554 * Connect/Disconnect the USB PHY pullup
4555 */
4556static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4557{
4558 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4559 unsigned long flags = 0;
4560
4561 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4562 hsotg->op_state);
4563
4564 /* Don't modify pullup state while in host mode */
4565 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4566 hsotg->enabled = is_on;
4567 return 0;
4568 }
4569
4570 spin_lock_irqsave(&hsotg->lock, flags);
4571 if (is_on) {
4572 hsotg->enabled = 1;
4573 dwc2_hsotg_core_init_disconnected(hsotg, false);
4574 /* Enable ACG feature in device mode,if supported */
4575 dwc2_enable_acg(hsotg);
4576 dwc2_hsotg_core_connect(hsotg);
4577 } else {
4578 dwc2_hsotg_core_disconnect(hsotg);
4579 dwc2_hsotg_disconnect(hsotg);
4580 hsotg->enabled = 0;
4581 }
4582
4583 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4584 spin_unlock_irqrestore(&hsotg->lock, flags);
4585
4586 return 0;
4587}
4588
4589static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4590{
4591 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4592 unsigned long flags;
4593
4594 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4595 spin_lock_irqsave(&hsotg->lock, flags);
4596
4597 /*
4598 * If controller is hibernated, it must exit from power_down
4599 * before being initialized / de-initialized
4600 */
4601 if (hsotg->lx_state == DWC2_L2)
4602 dwc2_exit_partial_power_down(hsotg, false);
4603
4604 if (is_active) {
4605 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4606
4607 dwc2_hsotg_core_init_disconnected(hsotg, false);
4608 if (hsotg->enabled) {
4609 /* Enable ACG feature in device mode,if supported */
4610 dwc2_enable_acg(hsotg);
4611 dwc2_hsotg_core_connect(hsotg);
4612 }
4613 } else {
4614 dwc2_hsotg_core_disconnect(hsotg);
4615 dwc2_hsotg_disconnect(hsotg);
4616 }
4617
4618 spin_unlock_irqrestore(&hsotg->lock, flags);
4619 return 0;
4620}
4621
4622/**
4623 * dwc2_hsotg_vbus_draw - report bMaxPower field
4624 * @gadget: The usb gadget state
4625 * @mA: Amount of current
4626 *
4627 * Report how much power the device may consume to the phy.
4628 */
4629static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4630{
4631 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4632
4633 if (IS_ERR_OR_NULL(hsotg->uphy))
4634 return -ENOTSUPP;
4635 return usb_phy_set_power(hsotg->uphy, mA);
4636}
4637
4638static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4639 .get_frame = dwc2_hsotg_gadget_getframe,
4640 .set_selfpowered = dwc2_hsotg_set_selfpowered,
4641 .udc_start = dwc2_hsotg_udc_start,
4642 .udc_stop = dwc2_hsotg_udc_stop,
4643 .pullup = dwc2_hsotg_pullup,
4644 .vbus_session = dwc2_hsotg_vbus_session,
4645 .vbus_draw = dwc2_hsotg_vbus_draw,
4646};
4647
4648/**
4649 * dwc2_hsotg_initep - initialise a single endpoint
4650 * @hsotg: The device state.
4651 * @hs_ep: The endpoint to be initialised.
4652 * @epnum: The endpoint number
4653 * @dir_in: True if direction is in.
4654 *
4655 * Initialise the given endpoint (as part of the probe and device state
4656 * creation) to give to the gadget driver. Setup the endpoint name, any
4657 * direction information and other state that may be required.
4658 */
4659static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4660 struct dwc2_hsotg_ep *hs_ep,
4661 int epnum,
4662 bool dir_in)
4663{
4664 char *dir;
4665
4666 if (epnum == 0)
4667 dir = "";
4668 else if (dir_in)
4669 dir = "in";
4670 else
4671 dir = "out";
4672
4673 hs_ep->dir_in = dir_in;
4674 hs_ep->index = epnum;
4675
4676 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4677
4678 INIT_LIST_HEAD(&hs_ep->queue);
4679 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4680
4681 /* add to the list of endpoints known by the gadget driver */
4682 if (epnum)
4683 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4684
4685 hs_ep->parent = hsotg;
4686 hs_ep->ep.name = hs_ep->name;
4687
4688 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4689 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4690 else
4691 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4692 epnum ? 1024 : EP0_MPS_LIMIT);
4693 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4694
4695 if (epnum == 0) {
4696 hs_ep->ep.caps.type_control = true;
4697 } else {
4698 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4699 hs_ep->ep.caps.type_iso = true;
4700 hs_ep->ep.caps.type_bulk = true;
4701 }
4702 hs_ep->ep.caps.type_int = true;
4703 }
4704
4705 if (dir_in)
4706 hs_ep->ep.caps.dir_in = true;
4707 else
4708 hs_ep->ep.caps.dir_out = true;
4709
4710 /*
4711 * if we're using dma, we need to set the next-endpoint pointer
4712 * to be something valid.
4713 */
4714
4715 if (using_dma(hsotg)) {
4716 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4717
4718 if (dir_in)
4719 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4720 else
4721 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4722 }
4723}
4724
4725/**
4726 * dwc2_hsotg_hw_cfg - read HW configuration registers
4727 * @hsotg: Programming view of the DWC_otg controller
4728 *
4729 * Read the USB core HW configuration registers
4730 */
4731static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4732{
4733 u32 cfg;
4734 u32 ep_type;
4735 u32 i;
4736
4737 /* check hardware configuration */
4738
4739 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4740
4741 /* Add ep0 */
4742 hsotg->num_of_eps++;
4743
4744 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4745 sizeof(struct dwc2_hsotg_ep),
4746 GFP_KERNEL);
4747 if (!hsotg->eps_in[0])
4748 return -ENOMEM;
4749 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4750 hsotg->eps_out[0] = hsotg->eps_in[0];
4751
4752 cfg = hsotg->hw_params.dev_ep_dirs;
4753 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4754 ep_type = cfg & 3;
4755 /* Direction in or both */
4756 if (!(ep_type & 2)) {
4757 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4758 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4759 if (!hsotg->eps_in[i])
4760 return -ENOMEM;
4761 }
4762 /* Direction out or both */
4763 if (!(ep_type & 1)) {
4764 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4765 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4766 if (!hsotg->eps_out[i])
4767 return -ENOMEM;
4768 }
4769 }
4770
4771 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4772 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4773
4774 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4775 hsotg->num_of_eps,
4776 hsotg->dedicated_fifos ? "dedicated" : "shared",
4777 hsotg->fifo_mem);
4778 return 0;
4779}
4780
4781/**
4782 * dwc2_hsotg_dump - dump state of the udc
4783 * @hsotg: Programming view of the DWC_otg controller
4784 *
4785 */
4786static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4787{
4788#ifdef DEBUG
4789 struct device *dev = hsotg->dev;
4790 u32 val;
4791 int idx;
4792
4793 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4794 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4795 dwc2_readl(hsotg, DIEPMSK));
4796
4797 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4798 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4799
4800 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4801 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4802
4803 /* show periodic fifo settings */
4804
4805 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4806 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4807 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4808 val >> FIFOSIZE_DEPTH_SHIFT,
4809 val & FIFOSIZE_STARTADDR_MASK);
4810 }
4811
4812 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4813 dev_info(dev,
4814 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4815 dwc2_readl(hsotg, DIEPCTL(idx)),
4816 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4817 dwc2_readl(hsotg, DIEPDMA(idx)));
4818
4819 val = dwc2_readl(hsotg, DOEPCTL(idx));
4820 dev_info(dev,
4821 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4822 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4823 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4824 dwc2_readl(hsotg, DOEPDMA(idx)));
4825 }
4826
4827 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4828 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4829#endif
4830}
4831
4832/**
4833 * dwc2_gadget_init - init function for gadget
4834 * @hsotg: Programming view of the DWC_otg controller
4835 *
4836 */
4837int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4838{
4839 struct device *dev = hsotg->dev;
4840 int epnum;
4841 int ret;
4842
4843 /* Dump fifo information */
4844 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4845 hsotg->params.g_np_tx_fifo_size);
4846 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4847
4848 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4849 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4850 hsotg->gadget.name = dev_name(dev);
4851 hsotg->remote_wakeup_allowed = 0;
4852
4853 if (hsotg->params.lpm)
4854 hsotg->gadget.lpm_capable = true;
4855
4856 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4857 hsotg->gadget.is_otg = 1;
4858 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4859 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4860
4861 ret = dwc2_hsotg_hw_cfg(hsotg);
4862 if (ret) {
4863 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4864 return ret;
4865 }
4866
4867 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4868 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4869 if (!hsotg->ctrl_buff)
4870 return -ENOMEM;
4871
4872 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4873 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4874 if (!hsotg->ep0_buff)
4875 return -ENOMEM;
4876
4877 if (using_desc_dma(hsotg)) {
4878 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4879 if (ret < 0)
4880 return ret;
4881 }
4882
4883 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
4884 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
4885 if (ret < 0) {
4886 dev_err(dev, "cannot claim IRQ for gadget\n");
4887 return ret;
4888 }
4889
4890 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4891
4892 if (hsotg->num_of_eps == 0) {
4893 dev_err(dev, "wrong number of EPs (zero)\n");
4894 return -EINVAL;
4895 }
4896
4897 /* setup endpoint information */
4898
4899 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4900 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4901
4902 /* allocate EP0 request */
4903
4904 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
4905 GFP_KERNEL);
4906 if (!hsotg->ctrl_req) {
4907 dev_err(dev, "failed to allocate ctrl req\n");
4908 return -ENOMEM;
4909 }
4910
4911 /* initialise the endpoints now the core has been initialised */
4912 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4913 if (hsotg->eps_in[epnum])
4914 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4915 epnum, 1);
4916 if (hsotg->eps_out[epnum])
4917 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
4918 epnum, 0);
4919 }
4920
4921 dwc2_hsotg_dump(hsotg);
4922
4923 return 0;
4924}
4925
4926/**
4927 * dwc2_hsotg_remove - remove function for hsotg driver
4928 * @hsotg: Programming view of the DWC_otg controller
4929 *
4930 */
4931int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
4932{
4933 usb_del_gadget_udc(&hsotg->gadget);
4934 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
4935
4936 return 0;
4937}
4938
4939int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
4940{
4941 unsigned long flags;
4942
4943 if (hsotg->lx_state != DWC2_L0)
4944 return 0;
4945
4946 if (hsotg->driver) {
4947 int ep;
4948
4949 dev_info(hsotg->dev, "suspending usb gadget %s\n",
4950 hsotg->driver->driver.name);
4951
4952 spin_lock_irqsave(&hsotg->lock, flags);
4953 if (hsotg->enabled)
4954 dwc2_hsotg_core_disconnect(hsotg);
4955 dwc2_hsotg_disconnect(hsotg);
4956 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4957 spin_unlock_irqrestore(&hsotg->lock, flags);
4958
4959 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
4960 if (hsotg->eps_in[ep])
4961 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4962 if (hsotg->eps_out[ep])
4963 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4964 }
4965 }
4966
4967 return 0;
4968}
4969
4970int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
4971{
4972 unsigned long flags;
4973
4974 if (hsotg->lx_state == DWC2_L2)
4975 return 0;
4976
4977 if (hsotg->driver) {
4978 dev_info(hsotg->dev, "resuming usb gadget %s\n",
4979 hsotg->driver->driver.name);
4980
4981 spin_lock_irqsave(&hsotg->lock, flags);
4982 dwc2_hsotg_core_init_disconnected(hsotg, false);
4983 if (hsotg->enabled) {
4984 /* Enable ACG feature in device mode,if supported */
4985 dwc2_enable_acg(hsotg);
4986 dwc2_hsotg_core_connect(hsotg);
4987 }
4988 spin_unlock_irqrestore(&hsotg->lock, flags);
4989 }
4990
4991 return 0;
4992}
4993
4994/**
4995 * dwc2_backup_device_registers() - Backup controller device registers.
4996 * When suspending usb bus, registers needs to be backuped
4997 * if controller power is disabled once suspended.
4998 *
4999 * @hsotg: Programming view of the DWC_otg controller
5000 */
5001int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
5002{
5003 struct dwc2_dregs_backup *dr;
5004 int i;
5005
5006 dev_dbg(hsotg->dev, "%s\n", __func__);
5007
5008 /* Backup dev regs */
5009 dr = &hsotg->dr_backup;
5010
5011 dr->dcfg = dwc2_readl(hsotg, DCFG);
5012 dr->dctl = dwc2_readl(hsotg, DCTL);
5013 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
5014 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
5015 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
5016
5017 for (i = 0; i < hsotg->num_of_eps; i++) {
5018 /* Backup IN EPs */
5019 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
5020
5021 /* Ensure DATA PID is correctly configured */
5022 if (dr->diepctl[i] & DXEPCTL_DPID)
5023 dr->diepctl[i] |= DXEPCTL_SETD1PID;
5024 else
5025 dr->diepctl[i] |= DXEPCTL_SETD0PID;
5026
5027 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
5028 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
5029
5030 /* Backup OUT EPs */
5031 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
5032
5033 /* Ensure DATA PID is correctly configured */
5034 if (dr->doepctl[i] & DXEPCTL_DPID)
5035 dr->doepctl[i] |= DXEPCTL_SETD1PID;
5036 else
5037 dr->doepctl[i] |= DXEPCTL_SETD0PID;
5038
5039 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
5040 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
5041 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5042 }
5043 dr->valid = true;
5044 return 0;
5045}
5046
5047/**
5048 * dwc2_restore_device_registers() - Restore controller device registers.
5049 * When resuming usb bus, device registers needs to be restored
5050 * if controller power were disabled.
5051 *
5052 * @hsotg: Programming view of the DWC_otg controller
5053 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
5054 *
5055 * Return: 0 if successful, negative error code otherwise
5056 */
5057int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5058{
5059 struct dwc2_dregs_backup *dr;
5060 int i;
5061
5062 dev_dbg(hsotg->dev, "%s\n", __func__);
5063
5064 /* Restore dev regs */
5065 dr = &hsotg->dr_backup;
5066 if (!dr->valid) {
5067 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5068 __func__);
5069 return -EINVAL;
5070 }
5071 dr->valid = false;
5072
5073 if (!remote_wakeup)
5074 dwc2_writel(hsotg, dr->dctl, DCTL);
5075
5076 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5077 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5078 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5079
5080 for (i = 0; i < hsotg->num_of_eps; i++) {
5081 /* Restore IN EPs */
5082 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5083 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5084 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5085 /** WA for enabled EPx's IN in DDMA mode. On entering to
5086 * hibernation wrong value read and saved from DIEPDMAx,
5087 * as result BNA interrupt asserted on hibernation exit
5088 * by restoring from saved area.
5089 */
5090 if (hsotg->params.g_dma_desc &&
5091 (dr->diepctl[i] & DXEPCTL_EPENA))
5092 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5093 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5094 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5095 /* Restore OUT EPs */
5096 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5097 /* WA for enabled EPx's OUT in DDMA mode. On entering to
5098 * hibernation wrong value read and saved from DOEPDMAx,
5099 * as result BNA interrupt asserted on hibernation exit
5100 * by restoring from saved area.
5101 */
5102 if (hsotg->params.g_dma_desc &&
5103 (dr->doepctl[i] & DXEPCTL_EPENA))
5104 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5105 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5106 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5107 }
5108
5109 return 0;
5110}
5111
5112/**
5113 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
5114 *
5115 * @hsotg: Programming view of DWC_otg controller
5116 *
5117 */
5118void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5119{
5120 u32 val;
5121
5122 if (!hsotg->params.lpm)
5123 return;
5124
5125 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
5126 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5127 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5128 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5129 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5130 val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5131 val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
5132 dwc2_writel(hsotg, val, GLPMCFG);
5133 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5134
5135 /* Unmask WKUP_ALERT Interrupt */
5136 if (hsotg->params.service_interval)
5137 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5138}
5139
5140/**
5141 * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
5142 *
5143 * @hsotg: Programming view of DWC_otg controller
5144 *
5145 */
5146void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5147{
5148 u32 val = 0;
5149
5150 val |= GREFCLK_REF_CLK_MODE;
5151 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5152 val |= hsotg->params.sof_cnt_wkup_alert <<
5153 GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5154
5155 dwc2_writel(hsotg, val, GREFCLK);
5156 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5157}
5158
5159/**
5160 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
5161 *
5162 * @hsotg: Programming view of the DWC_otg controller
5163 *
5164 * Return non-zero if failed to enter to hibernation.
5165 */
5166int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5167{
5168 u32 gpwrdn;
5169 int ret = 0;
5170
5171 /* Change to L2(suspend) state */
5172 hsotg->lx_state = DWC2_L2;
5173 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5174 ret = dwc2_backup_global_registers(hsotg);
5175 if (ret) {
5176 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5177 __func__);
5178 return ret;
5179 }
5180 ret = dwc2_backup_device_registers(hsotg);
5181 if (ret) {
5182 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5183 __func__);
5184 return ret;
5185 }
5186
5187 gpwrdn = GPWRDN_PWRDNRSTN;
5188 gpwrdn |= GPWRDN_PMUACTV;
5189 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5190 udelay(10);
5191
5192 /* Set flag to indicate that we are in hibernation */
5193 hsotg->hibernated = 1;
5194
5195 /* Enable interrupts from wake up logic */
5196 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5197 gpwrdn |= GPWRDN_PMUINTSEL;
5198 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5199 udelay(10);
5200
5201 /* Unmask device mode interrupts in GPWRDN */
5202 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5203 gpwrdn |= GPWRDN_RST_DET_MSK;
5204 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5205 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5206 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5207 udelay(10);
5208
5209 /* Enable Power Down Clamp */
5210 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5211 gpwrdn |= GPWRDN_PWRDNCLMP;
5212 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5213 udelay(10);
5214
5215 /* Switch off VDD */
5216 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5217 gpwrdn |= GPWRDN_PWRDNSWTCH;
5218 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5219 udelay(10);
5220
5221 /* Save gpwrdn register for further usage if stschng interrupt */
5222 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5223 dev_dbg(hsotg->dev, "Hibernation completed\n");
5224
5225 return ret;
5226}
5227
5228/**
5229 * dwc2_gadget_exit_hibernation()
5230 * This function is for exiting from Device mode hibernation by host initiated
5231 * resume/reset and device initiated remote-wakeup.
5232 *
5233 * @hsotg: Programming view of the DWC_otg controller
5234 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5235 * @reset: indicates whether resume is initiated by Reset.
5236 *
5237 * Return non-zero if failed to exit from hibernation.
5238 */
5239int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5240 int rem_wakeup, int reset)
5241{
5242 u32 pcgcctl;
5243 u32 gpwrdn;
5244 u32 dctl;
5245 int ret = 0;
5246 struct dwc2_gregs_backup *gr;
5247 struct dwc2_dregs_backup *dr;
5248
5249 gr = &hsotg->gr_backup;
5250 dr = &hsotg->dr_backup;
5251
5252 if (!hsotg->hibernated) {
5253 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5254 return 1;
5255 }
5256 dev_dbg(hsotg->dev,
5257 "%s: called with rem_wakeup = %d reset = %d\n",
5258 __func__, rem_wakeup, reset);
5259
5260 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5261
5262 if (!reset) {
5263 /* Clear all pending interupts */
5264 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5265 }
5266
5267 /* De-assert Restore */
5268 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5269 gpwrdn &= ~GPWRDN_RESTORE;
5270 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5271 udelay(10);
5272
5273 if (!rem_wakeup) {
5274 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5275 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5276 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5277 }
5278
5279 /* Restore GUSBCFG, DCFG and DCTL */
5280 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5281 dwc2_writel(hsotg, dr->dcfg, DCFG);
5282 dwc2_writel(hsotg, dr->dctl, DCTL);
5283
5284 /* De-assert Wakeup Logic */
5285 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5286 gpwrdn &= ~GPWRDN_PMUACTV;
5287 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5288
5289 if (rem_wakeup) {
5290 udelay(10);
5291 /* Start Remote Wakeup Signaling */
5292 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5293 } else {
5294 udelay(50);
5295 /* Set Device programming done bit */
5296 dctl = dwc2_readl(hsotg, DCTL);
5297 dctl |= DCTL_PWRONPRGDONE;
5298 dwc2_writel(hsotg, dctl, DCTL);
5299 }
5300 /* Wait for interrupts which must be cleared */
5301 mdelay(2);
5302 /* Clear all pending interupts */
5303 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5304
5305 /* Restore global registers */
5306 ret = dwc2_restore_global_registers(hsotg);
5307 if (ret) {
5308 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5309 __func__);
5310 return ret;
5311 }
5312
5313 /* Restore device registers */
5314 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5315 if (ret) {
5316 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5317 __func__);
5318 return ret;
5319 }
5320
5321 if (rem_wakeup) {
5322 mdelay(10);
5323 dctl = dwc2_readl(hsotg, DCTL);
5324 dctl &= ~DCTL_RMTWKUPSIG;
5325 dwc2_writel(hsotg, dctl, DCTL);
5326 }
5327
5328 hsotg->hibernated = 0;
5329 hsotg->lx_state = DWC2_L0;
5330 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
5331
5332 return ret;
5333}