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1/**
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * S3C USB2.0 High-speed / OtG driver
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/spinlock.h>
20#include <linux/interrupt.h>
21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h>
23#include <linux/mutex.h>
24#include <linux/seq_file.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/slab.h>
28#include <linux/of_platform.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32#include <linux/usb/phy.h>
33
34#include "core.h"
35#include "hw.h"
36
37/* conversion functions */
38static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
39{
40 return container_of(req, struct dwc2_hsotg_req, req);
41}
42
43static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
44{
45 return container_of(ep, struct dwc2_hsotg_ep, ep);
46}
47
48static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
49{
50 return container_of(gadget, struct dwc2_hsotg, gadget);
51}
52
53static inline void __orr32(void __iomem *ptr, u32 val)
54{
55 dwc2_writel(dwc2_readl(ptr) | val, ptr);
56}
57
58static inline void __bic32(void __iomem *ptr, u32 val)
59{
60 dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
61}
62
63static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
64 u32 ep_index, u32 dir_in)
65{
66 if (dir_in)
67 return hsotg->eps_in[ep_index];
68 else
69 return hsotg->eps_out[ep_index];
70}
71
72/* forward declaration of functions */
73static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
74
75/**
76 * using_dma - return the DMA status of the driver.
77 * @hsotg: The driver state.
78 *
79 * Return true if we're using DMA.
80 *
81 * Currently, we have the DMA support code worked into everywhere
82 * that needs it, but the AMBA DMA implementation in the hardware can
83 * only DMA from 32bit aligned addresses. This means that gadgets such
84 * as the CDC Ethernet cannot work as they often pass packets which are
85 * not 32bit aligned.
86 *
87 * Unfortunately the choice to use DMA or not is global to the controller
88 * and seems to be only settable when the controller is being put through
89 * a core reset. This means we either need to fix the gadgets to take
90 * account of DMA alignment, or add bounce buffers (yuerk).
91 *
92 * g_using_dma is set depending on dts flag.
93 */
94static inline bool using_dma(struct dwc2_hsotg *hsotg)
95{
96 return hsotg->g_using_dma;
97}
98
99/**
100 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
101 * @hsotg: The device state
102 * @ints: A bitmask of the interrupts to enable
103 */
104static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
105{
106 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
107 u32 new_gsintmsk;
108
109 new_gsintmsk = gsintmsk | ints;
110
111 if (new_gsintmsk != gsintmsk) {
112 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
113 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
114 }
115}
116
117/**
118 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
119 * @hsotg: The device state
120 * @ints: A bitmask of the interrupts to enable
121 */
122static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
123{
124 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
125 u32 new_gsintmsk;
126
127 new_gsintmsk = gsintmsk & ~ints;
128
129 if (new_gsintmsk != gsintmsk)
130 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
131}
132
133/**
134 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
135 * @hsotg: The device state
136 * @ep: The endpoint index
137 * @dir_in: True if direction is in.
138 * @en: The enable value, true to enable
139 *
140 * Set or clear the mask for an individual endpoint's interrupt
141 * request.
142 */
143static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
144 unsigned int ep, unsigned int dir_in,
145 unsigned int en)
146{
147 unsigned long flags;
148 u32 bit = 1 << ep;
149 u32 daint;
150
151 if (!dir_in)
152 bit <<= 16;
153
154 local_irq_save(flags);
155 daint = dwc2_readl(hsotg->regs + DAINTMSK);
156 if (en)
157 daint |= bit;
158 else
159 daint &= ~bit;
160 dwc2_writel(daint, hsotg->regs + DAINTMSK);
161 local_irq_restore(flags);
162}
163
164/**
165 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
166 * @hsotg: The device instance.
167 */
168static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
169{
170 unsigned int ep;
171 unsigned int addr;
172 int timeout;
173 u32 val;
174
175 /* Reset fifo map if not correctly cleared during previous session */
176 WARN_ON(hsotg->fifo_map);
177 hsotg->fifo_map = 0;
178
179 /* set RX/NPTX FIFO sizes */
180 dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ);
181 dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) |
182 (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT),
183 hsotg->regs + GNPTXFSIZ);
184
185 /*
186 * arange all the rest of the TX FIFOs, as some versions of this
187 * block have overlapping default addresses. This also ensures
188 * that if the settings have been changed, then they are set to
189 * known values.
190 */
191
192 /* start at the end of the GNPTXFSIZ, rounded up */
193 addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz;
194
195 /*
196 * Configure fifos sizes from provided configuration and assign
197 * them to endpoints dynamically according to maxpacket size value of
198 * given endpoint.
199 */
200 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
201 if (!hsotg->g_tx_fifo_sz[ep])
202 continue;
203 val = addr;
204 val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT;
205 WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem,
206 "insufficient fifo memory");
207 addr += hsotg->g_tx_fifo_sz[ep];
208
209 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
210 }
211
212 /*
213 * according to p428 of the design guide, we need to ensure that
214 * all fifos are flushed before continuing
215 */
216
217 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
218 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
219
220 /* wait until the fifos are both flushed */
221 timeout = 100;
222 while (1) {
223 val = dwc2_readl(hsotg->regs + GRSTCTL);
224
225 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
226 break;
227
228 if (--timeout == 0) {
229 dev_err(hsotg->dev,
230 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
231 __func__, val);
232 break;
233 }
234
235 udelay(1);
236 }
237
238 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
239}
240
241/**
242 * @ep: USB endpoint to allocate request for.
243 * @flags: Allocation flags
244 *
245 * Allocate a new USB request structure appropriate for the specified endpoint
246 */
247static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
248 gfp_t flags)
249{
250 struct dwc2_hsotg_req *req;
251
252 req = kzalloc(sizeof(struct dwc2_hsotg_req), flags);
253 if (!req)
254 return NULL;
255
256 INIT_LIST_HEAD(&req->queue);
257
258 return &req->req;
259}
260
261/**
262 * is_ep_periodic - return true if the endpoint is in periodic mode.
263 * @hs_ep: The endpoint to query.
264 *
265 * Returns true if the endpoint is in periodic mode, meaning it is being
266 * used for an Interrupt or ISO transfer.
267 */
268static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
269{
270 return hs_ep->periodic;
271}
272
273/**
274 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
275 * @hsotg: The device state.
276 * @hs_ep: The endpoint for the request
277 * @hs_req: The request being processed.
278 *
279 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
280 * of a request to ensure the buffer is ready for access by the caller.
281 */
282static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
283 struct dwc2_hsotg_ep *hs_ep,
284 struct dwc2_hsotg_req *hs_req)
285{
286 struct usb_request *req = &hs_req->req;
287
288 /* ignore this if we're not moving any data */
289 if (hs_req->req.length == 0)
290 return;
291
292 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
293}
294
295/**
296 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
297 * @hsotg: The controller state.
298 * @hs_ep: The endpoint we're going to write for.
299 * @hs_req: The request to write data for.
300 *
301 * This is called when the TxFIFO has some space in it to hold a new
302 * transmission and we have something to give it. The actual setup of
303 * the data size is done elsewhere, so all we have to do is to actually
304 * write the data.
305 *
306 * The return value is zero if there is more space (or nothing was done)
307 * otherwise -ENOSPC is returned if the FIFO space was used up.
308 *
309 * This routine is only needed for PIO
310 */
311static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
312 struct dwc2_hsotg_ep *hs_ep,
313 struct dwc2_hsotg_req *hs_req)
314{
315 bool periodic = is_ep_periodic(hs_ep);
316 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
317 int buf_pos = hs_req->req.actual;
318 int to_write = hs_ep->size_loaded;
319 void *data;
320 int can_write;
321 int pkt_round;
322 int max_transfer;
323
324 to_write -= (buf_pos - hs_ep->last_load);
325
326 /* if there's nothing to write, get out early */
327 if (to_write == 0)
328 return 0;
329
330 if (periodic && !hsotg->dedicated_fifos) {
331 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
332 int size_left;
333 int size_done;
334
335 /*
336 * work out how much data was loaded so we can calculate
337 * how much data is left in the fifo.
338 */
339
340 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
341
342 /*
343 * if shared fifo, we cannot write anything until the
344 * previous data has been completely sent.
345 */
346 if (hs_ep->fifo_load != 0) {
347 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
348 return -ENOSPC;
349 }
350
351 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
352 __func__, size_left,
353 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
354
355 /* how much of the data has moved */
356 size_done = hs_ep->size_loaded - size_left;
357
358 /* how much data is left in the fifo */
359 can_write = hs_ep->fifo_load - size_done;
360 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
361 __func__, can_write);
362
363 can_write = hs_ep->fifo_size - can_write;
364 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
365 __func__, can_write);
366
367 if (can_write <= 0) {
368 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
369 return -ENOSPC;
370 }
371 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
372 can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index));
373
374 can_write &= 0xffff;
375 can_write *= 4;
376 } else {
377 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
378 dev_dbg(hsotg->dev,
379 "%s: no queue slots available (0x%08x)\n",
380 __func__, gnptxsts);
381
382 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
383 return -ENOSPC;
384 }
385
386 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
387 can_write *= 4; /* fifo size is in 32bit quantities. */
388 }
389
390 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
391
392 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
393 __func__, gnptxsts, can_write, to_write, max_transfer);
394
395 /*
396 * limit to 512 bytes of data, it seems at least on the non-periodic
397 * FIFO, requests of >512 cause the endpoint to get stuck with a
398 * fragment of the end of the transfer in it.
399 */
400 if (can_write > 512 && !periodic)
401 can_write = 512;
402
403 /*
404 * limit the write to one max-packet size worth of data, but allow
405 * the transfer to return that it did not run out of fifo space
406 * doing it.
407 */
408 if (to_write > max_transfer) {
409 to_write = max_transfer;
410
411 /* it's needed only when we do not use dedicated fifos */
412 if (!hsotg->dedicated_fifos)
413 dwc2_hsotg_en_gsint(hsotg,
414 periodic ? GINTSTS_PTXFEMP :
415 GINTSTS_NPTXFEMP);
416 }
417
418 /* see if we can write data */
419
420 if (to_write > can_write) {
421 to_write = can_write;
422 pkt_round = to_write % max_transfer;
423
424 /*
425 * Round the write down to an
426 * exact number of packets.
427 *
428 * Note, we do not currently check to see if we can ever
429 * write a full packet or not to the FIFO.
430 */
431
432 if (pkt_round)
433 to_write -= pkt_round;
434
435 /*
436 * enable correct FIFO interrupt to alert us when there
437 * is more room left.
438 */
439
440 /* it's needed only when we do not use dedicated fifos */
441 if (!hsotg->dedicated_fifos)
442 dwc2_hsotg_en_gsint(hsotg,
443 periodic ? GINTSTS_PTXFEMP :
444 GINTSTS_NPTXFEMP);
445 }
446
447 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
448 to_write, hs_req->req.length, can_write, buf_pos);
449
450 if (to_write <= 0)
451 return -ENOSPC;
452
453 hs_req->req.actual = buf_pos + to_write;
454 hs_ep->total_data += to_write;
455
456 if (periodic)
457 hs_ep->fifo_load += to_write;
458
459 to_write = DIV_ROUND_UP(to_write, 4);
460 data = hs_req->req.buf + buf_pos;
461
462 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
463
464 return (to_write >= can_write) ? -ENOSPC : 0;
465}
466
467/**
468 * get_ep_limit - get the maximum data legnth for this endpoint
469 * @hs_ep: The endpoint
470 *
471 * Return the maximum data that can be queued in one go on a given endpoint
472 * so that transfers that are too long can be split.
473 */
474static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
475{
476 int index = hs_ep->index;
477 unsigned maxsize;
478 unsigned maxpkt;
479
480 if (index != 0) {
481 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
482 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
483 } else {
484 maxsize = 64+64;
485 if (hs_ep->dir_in)
486 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
487 else
488 maxpkt = 2;
489 }
490
491 /* we made the constant loading easier above by using +1 */
492 maxpkt--;
493 maxsize--;
494
495 /*
496 * constrain by packet count if maxpkts*pktsize is greater
497 * than the length register size.
498 */
499
500 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
501 maxsize = maxpkt * hs_ep->ep.maxpacket;
502
503 return maxsize;
504}
505
506/**
507 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
508 * @hsotg: The controller state.
509 * @hs_ep: The endpoint to process a request for
510 * @hs_req: The request to start.
511 * @continuing: True if we are doing more for the current request.
512 *
513 * Start the given request running by setting the endpoint registers
514 * appropriately, and writing any data to the FIFOs.
515 */
516static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
517 struct dwc2_hsotg_ep *hs_ep,
518 struct dwc2_hsotg_req *hs_req,
519 bool continuing)
520{
521 struct usb_request *ureq = &hs_req->req;
522 int index = hs_ep->index;
523 int dir_in = hs_ep->dir_in;
524 u32 epctrl_reg;
525 u32 epsize_reg;
526 u32 epsize;
527 u32 ctrl;
528 unsigned length;
529 unsigned packets;
530 unsigned maxreq;
531
532 if (index != 0) {
533 if (hs_ep->req && !continuing) {
534 dev_err(hsotg->dev, "%s: active request\n", __func__);
535 WARN_ON(1);
536 return;
537 } else if (hs_ep->req != hs_req && continuing) {
538 dev_err(hsotg->dev,
539 "%s: continue different req\n", __func__);
540 WARN_ON(1);
541 return;
542 }
543 }
544
545 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
546 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
547
548 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
549 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
550 hs_ep->dir_in ? "in" : "out");
551
552 /* If endpoint is stalled, we will restart request later */
553 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
554
555 if (index && ctrl & DXEPCTL_STALL) {
556 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
557 return;
558 }
559
560 length = ureq->length - ureq->actual;
561 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
562 ureq->length, ureq->actual);
563
564 maxreq = get_ep_limit(hs_ep);
565 if (length > maxreq) {
566 int round = maxreq % hs_ep->ep.maxpacket;
567
568 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
569 __func__, length, maxreq, round);
570
571 /* round down to multiple of packets */
572 if (round)
573 maxreq -= round;
574
575 length = maxreq;
576 }
577
578 if (length)
579 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
580 else
581 packets = 1; /* send one packet if length is zero. */
582
583 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
584 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
585 return;
586 }
587
588 if (dir_in && index != 0)
589 if (hs_ep->isochronous)
590 epsize = DXEPTSIZ_MC(packets);
591 else
592 epsize = DXEPTSIZ_MC(1);
593 else
594 epsize = 0;
595
596 /*
597 * zero length packet should be programmed on its own and should not
598 * be counted in DIEPTSIZ.PktCnt with other packets.
599 */
600 if (dir_in && ureq->zero && !continuing) {
601 /* Test if zlp is actually required. */
602 if ((ureq->length >= hs_ep->ep.maxpacket) &&
603 !(ureq->length % hs_ep->ep.maxpacket))
604 hs_ep->send_zlp = 1;
605 }
606
607 epsize |= DXEPTSIZ_PKTCNT(packets);
608 epsize |= DXEPTSIZ_XFERSIZE(length);
609
610 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
611 __func__, packets, length, ureq->length, epsize, epsize_reg);
612
613 /* store the request as the current one we're doing */
614 hs_ep->req = hs_req;
615
616 /* write size / packets */
617 dwc2_writel(epsize, hsotg->regs + epsize_reg);
618
619 if (using_dma(hsotg) && !continuing) {
620 unsigned int dma_reg;
621
622 /*
623 * write DMA address to control register, buffer already
624 * synced by dwc2_hsotg_ep_queue().
625 */
626
627 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
628 dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
629
630 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
631 __func__, &ureq->dma, dma_reg);
632 }
633
634 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
635 ctrl |= DXEPCTL_USBACTEP;
636
637 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
638
639 /* For Setup request do not clear NAK */
640 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
641 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
642
643 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
644 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
645
646 /*
647 * set these, it seems that DMA support increments past the end
648 * of the packet buffer so we need to calculate the length from
649 * this information.
650 */
651 hs_ep->size_loaded = length;
652 hs_ep->last_load = ureq->actual;
653
654 if (dir_in && !using_dma(hsotg)) {
655 /* set these anyway, we may need them for non-periodic in */
656 hs_ep->fifo_load = 0;
657
658 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
659 }
660
661 /*
662 * clear the INTknTXFEmpMsk when we start request, more as a aide
663 * to debugging to see what is going on.
664 */
665 if (dir_in)
666 dwc2_writel(DIEPMSK_INTKNTXFEMPMSK,
667 hsotg->regs + DIEPINT(index));
668
669 /*
670 * Note, trying to clear the NAK here causes problems with transmit
671 * on the S3C6400 ending up with the TXFIFO becoming full.
672 */
673
674 /* check ep is enabled */
675 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
676 dev_dbg(hsotg->dev,
677 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
678 index, dwc2_readl(hsotg->regs + epctrl_reg));
679
680 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
681 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
682
683 /* enable ep interrupts */
684 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
685}
686
687/**
688 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
689 * @hsotg: The device state.
690 * @hs_ep: The endpoint the request is on.
691 * @req: The request being processed.
692 *
693 * We've been asked to queue a request, so ensure that the memory buffer
694 * is correctly setup for DMA. If we've been passed an extant DMA address
695 * then ensure the buffer has been synced to memory. If our buffer has no
696 * DMA memory, then we map the memory and mark our request to allow us to
697 * cleanup on completion.
698 */
699static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
700 struct dwc2_hsotg_ep *hs_ep,
701 struct usb_request *req)
702{
703 struct dwc2_hsotg_req *hs_req = our_req(req);
704 int ret;
705
706 /* if the length is zero, ignore the DMA data */
707 if (hs_req->req.length == 0)
708 return 0;
709
710 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
711 if (ret)
712 goto dma_error;
713
714 return 0;
715
716dma_error:
717 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
718 __func__, req->buf, req->length);
719
720 return -EIO;
721}
722
723static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
724 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
725{
726 void *req_buf = hs_req->req.buf;
727
728 /* If dma is not being used or buffer is aligned */
729 if (!using_dma(hsotg) || !((long)req_buf & 3))
730 return 0;
731
732 WARN_ON(hs_req->saved_req_buf);
733
734 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
735 hs_ep->ep.name, req_buf, hs_req->req.length);
736
737 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
738 if (!hs_req->req.buf) {
739 hs_req->req.buf = req_buf;
740 dev_err(hsotg->dev,
741 "%s: unable to allocate memory for bounce buffer\n",
742 __func__);
743 return -ENOMEM;
744 }
745
746 /* Save actual buffer */
747 hs_req->saved_req_buf = req_buf;
748
749 if (hs_ep->dir_in)
750 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
751 return 0;
752}
753
754static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
755 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
756{
757 /* If dma is not being used or buffer was aligned */
758 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
759 return;
760
761 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
762 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
763
764 /* Copy data from bounce buffer on successful out transfer */
765 if (!hs_ep->dir_in && !hs_req->req.status)
766 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
767 hs_req->req.actual);
768
769 /* Free bounce buffer */
770 kfree(hs_req->req.buf);
771
772 hs_req->req.buf = hs_req->saved_req_buf;
773 hs_req->saved_req_buf = NULL;
774}
775
776static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
777 gfp_t gfp_flags)
778{
779 struct dwc2_hsotg_req *hs_req = our_req(req);
780 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
781 struct dwc2_hsotg *hs = hs_ep->parent;
782 bool first;
783 int ret;
784
785 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
786 ep->name, req, req->length, req->buf, req->no_interrupt,
787 req->zero, req->short_not_ok);
788
789 /* Prevent new request submission when controller is suspended */
790 if (hs->lx_state == DWC2_L2) {
791 dev_dbg(hs->dev, "%s: don't submit request while suspended\n",
792 __func__);
793 return -EAGAIN;
794 }
795
796 /* initialise status of the request */
797 INIT_LIST_HEAD(&hs_req->queue);
798 req->actual = 0;
799 req->status = -EINPROGRESS;
800
801 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
802 if (ret)
803 return ret;
804
805 /* if we're using DMA, sync the buffers as necessary */
806 if (using_dma(hs)) {
807 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
808 if (ret)
809 return ret;
810 }
811
812 first = list_empty(&hs_ep->queue);
813 list_add_tail(&hs_req->queue, &hs_ep->queue);
814
815 if (first)
816 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
817
818 return 0;
819}
820
821static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
822 gfp_t gfp_flags)
823{
824 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
825 struct dwc2_hsotg *hs = hs_ep->parent;
826 unsigned long flags = 0;
827 int ret = 0;
828
829 spin_lock_irqsave(&hs->lock, flags);
830 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
831 spin_unlock_irqrestore(&hs->lock, flags);
832
833 return ret;
834}
835
836static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
837 struct usb_request *req)
838{
839 struct dwc2_hsotg_req *hs_req = our_req(req);
840
841 kfree(hs_req);
842}
843
844/**
845 * dwc2_hsotg_complete_oursetup - setup completion callback
846 * @ep: The endpoint the request was on.
847 * @req: The request completed.
848 *
849 * Called on completion of any requests the driver itself
850 * submitted that need cleaning up.
851 */
852static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
853 struct usb_request *req)
854{
855 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
856 struct dwc2_hsotg *hsotg = hs_ep->parent;
857
858 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
859
860 dwc2_hsotg_ep_free_request(ep, req);
861}
862
863/**
864 * ep_from_windex - convert control wIndex value to endpoint
865 * @hsotg: The driver state.
866 * @windex: The control request wIndex field (in host order).
867 *
868 * Convert the given wIndex into a pointer to an driver endpoint
869 * structure, or return NULL if it is not a valid endpoint.
870 */
871static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
872 u32 windex)
873{
874 struct dwc2_hsotg_ep *ep;
875 int dir = (windex & USB_DIR_IN) ? 1 : 0;
876 int idx = windex & 0x7F;
877
878 if (windex >= 0x100)
879 return NULL;
880
881 if (idx > hsotg->num_of_eps)
882 return NULL;
883
884 ep = index_to_ep(hsotg, idx, dir);
885
886 if (idx && ep->dir_in != dir)
887 return NULL;
888
889 return ep;
890}
891
892/**
893 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
894 * @hsotg: The driver state.
895 * @testmode: requested usb test mode
896 * Enable usb Test Mode requested by the Host.
897 */
898int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
899{
900 int dctl = dwc2_readl(hsotg->regs + DCTL);
901
902 dctl &= ~DCTL_TSTCTL_MASK;
903 switch (testmode) {
904 case TEST_J:
905 case TEST_K:
906 case TEST_SE0_NAK:
907 case TEST_PACKET:
908 case TEST_FORCE_EN:
909 dctl |= testmode << DCTL_TSTCTL_SHIFT;
910 break;
911 default:
912 return -EINVAL;
913 }
914 dwc2_writel(dctl, hsotg->regs + DCTL);
915 return 0;
916}
917
918/**
919 * dwc2_hsotg_send_reply - send reply to control request
920 * @hsotg: The device state
921 * @ep: Endpoint 0
922 * @buff: Buffer for request
923 * @length: Length of reply.
924 *
925 * Create a request and queue it on the given endpoint. This is useful as
926 * an internal method of sending replies to certain control requests, etc.
927 */
928static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
929 struct dwc2_hsotg_ep *ep,
930 void *buff,
931 int length)
932{
933 struct usb_request *req;
934 int ret;
935
936 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
937
938 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
939 hsotg->ep0_reply = req;
940 if (!req) {
941 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
942 return -ENOMEM;
943 }
944
945 req->buf = hsotg->ep0_buff;
946 req->length = length;
947 /*
948 * zero flag is for sending zlp in DATA IN stage. It has no impact on
949 * STATUS stage.
950 */
951 req->zero = 0;
952 req->complete = dwc2_hsotg_complete_oursetup;
953
954 if (length)
955 memcpy(req->buf, buff, length);
956
957 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
958 if (ret) {
959 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
960 return ret;
961 }
962
963 return 0;
964}
965
966/**
967 * dwc2_hsotg_process_req_status - process request GET_STATUS
968 * @hsotg: The device state
969 * @ctrl: USB control request
970 */
971static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
972 struct usb_ctrlrequest *ctrl)
973{
974 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
975 struct dwc2_hsotg_ep *ep;
976 __le16 reply;
977 int ret;
978
979 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
980
981 if (!ep0->dir_in) {
982 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
983 return -EINVAL;
984 }
985
986 switch (ctrl->bRequestType & USB_RECIP_MASK) {
987 case USB_RECIP_DEVICE:
988 reply = cpu_to_le16(0); /* bit 0 => self powered,
989 * bit 1 => remote wakeup */
990 break;
991
992 case USB_RECIP_INTERFACE:
993 /* currently, the data result should be zero */
994 reply = cpu_to_le16(0);
995 break;
996
997 case USB_RECIP_ENDPOINT:
998 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
999 if (!ep)
1000 return -ENOENT;
1001
1002 reply = cpu_to_le16(ep->halted ? 1 : 0);
1003 break;
1004
1005 default:
1006 return 0;
1007 }
1008
1009 if (le16_to_cpu(ctrl->wLength) != 2)
1010 return -EINVAL;
1011
1012 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1013 if (ret) {
1014 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1015 return ret;
1016 }
1017
1018 return 1;
1019}
1020
1021static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1022
1023/**
1024 * get_ep_head - return the first request on the endpoint
1025 * @hs_ep: The controller endpoint to get
1026 *
1027 * Get the first request on the endpoint.
1028 */
1029static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1030{
1031 if (list_empty(&hs_ep->queue))
1032 return NULL;
1033
1034 return list_first_entry(&hs_ep->queue, struct dwc2_hsotg_req, queue);
1035}
1036
1037/**
1038 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1039 * @hsotg: The device state
1040 * @ctrl: USB control request
1041 */
1042static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1043 struct usb_ctrlrequest *ctrl)
1044{
1045 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1046 struct dwc2_hsotg_req *hs_req;
1047 bool restart;
1048 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1049 struct dwc2_hsotg_ep *ep;
1050 int ret;
1051 bool halted;
1052 u32 recip;
1053 u32 wValue;
1054 u32 wIndex;
1055
1056 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1057 __func__, set ? "SET" : "CLEAR");
1058
1059 wValue = le16_to_cpu(ctrl->wValue);
1060 wIndex = le16_to_cpu(ctrl->wIndex);
1061 recip = ctrl->bRequestType & USB_RECIP_MASK;
1062
1063 switch (recip) {
1064 case USB_RECIP_DEVICE:
1065 switch (wValue) {
1066 case USB_DEVICE_TEST_MODE:
1067 if ((wIndex & 0xff) != 0)
1068 return -EINVAL;
1069 if (!set)
1070 return -EINVAL;
1071
1072 hsotg->test_mode = wIndex >> 8;
1073 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1074 if (ret) {
1075 dev_err(hsotg->dev,
1076 "%s: failed to send reply\n", __func__);
1077 return ret;
1078 }
1079 break;
1080 default:
1081 return -ENOENT;
1082 }
1083 break;
1084
1085 case USB_RECIP_ENDPOINT:
1086 ep = ep_from_windex(hsotg, wIndex);
1087 if (!ep) {
1088 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1089 __func__, wIndex);
1090 return -ENOENT;
1091 }
1092
1093 switch (wValue) {
1094 case USB_ENDPOINT_HALT:
1095 halted = ep->halted;
1096
1097 dwc2_hsotg_ep_sethalt(&ep->ep, set);
1098
1099 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1100 if (ret) {
1101 dev_err(hsotg->dev,
1102 "%s: failed to send reply\n", __func__);
1103 return ret;
1104 }
1105
1106 /*
1107 * we have to complete all requests for ep if it was
1108 * halted, and the halt was cleared by CLEAR_FEATURE
1109 */
1110
1111 if (!set && halted) {
1112 /*
1113 * If we have request in progress,
1114 * then complete it
1115 */
1116 if (ep->req) {
1117 hs_req = ep->req;
1118 ep->req = NULL;
1119 list_del_init(&hs_req->queue);
1120 if (hs_req->req.complete) {
1121 spin_unlock(&hsotg->lock);
1122 usb_gadget_giveback_request(
1123 &ep->ep, &hs_req->req);
1124 spin_lock(&hsotg->lock);
1125 }
1126 }
1127
1128 /* If we have pending request, then start it */
1129 if (!ep->req) {
1130 restart = !list_empty(&ep->queue);
1131 if (restart) {
1132 hs_req = get_ep_head(ep);
1133 dwc2_hsotg_start_req(hsotg, ep,
1134 hs_req, false);
1135 }
1136 }
1137 }
1138
1139 break;
1140
1141 default:
1142 return -ENOENT;
1143 }
1144 break;
1145 default:
1146 return -ENOENT;
1147 }
1148 return 1;
1149}
1150
1151static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1152
1153/**
1154 * dwc2_hsotg_stall_ep0 - stall ep0
1155 * @hsotg: The device state
1156 *
1157 * Set stall for ep0 as response for setup request.
1158 */
1159static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1160{
1161 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1162 u32 reg;
1163 u32 ctrl;
1164
1165 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1166 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1167
1168 /*
1169 * DxEPCTL_Stall will be cleared by EP once it has
1170 * taken effect, so no need to clear later.
1171 */
1172
1173 ctrl = dwc2_readl(hsotg->regs + reg);
1174 ctrl |= DXEPCTL_STALL;
1175 ctrl |= DXEPCTL_CNAK;
1176 dwc2_writel(ctrl, hsotg->regs + reg);
1177
1178 dev_dbg(hsotg->dev,
1179 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1180 ctrl, reg, dwc2_readl(hsotg->regs + reg));
1181
1182 /*
1183 * complete won't be called, so we enqueue
1184 * setup request here
1185 */
1186 dwc2_hsotg_enqueue_setup(hsotg);
1187}
1188
1189/**
1190 * dwc2_hsotg_process_control - process a control request
1191 * @hsotg: The device state
1192 * @ctrl: The control request received
1193 *
1194 * The controller has received the SETUP phase of a control request, and
1195 * needs to work out what to do next (and whether to pass it on to the
1196 * gadget driver).
1197 */
1198static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1199 struct usb_ctrlrequest *ctrl)
1200{
1201 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1202 int ret = 0;
1203 u32 dcfg;
1204
1205 dev_dbg(hsotg->dev,
1206 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1207 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1208 ctrl->wIndex, ctrl->wLength);
1209
1210 if (ctrl->wLength == 0) {
1211 ep0->dir_in = 1;
1212 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1213 } else if (ctrl->bRequestType & USB_DIR_IN) {
1214 ep0->dir_in = 1;
1215 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1216 } else {
1217 ep0->dir_in = 0;
1218 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1219 }
1220
1221 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1222 switch (ctrl->bRequest) {
1223 case USB_REQ_SET_ADDRESS:
1224 hsotg->connected = 1;
1225 dcfg = dwc2_readl(hsotg->regs + DCFG);
1226 dcfg &= ~DCFG_DEVADDR_MASK;
1227 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1228 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1229 dwc2_writel(dcfg, hsotg->regs + DCFG);
1230
1231 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1232
1233 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1234 return;
1235
1236 case USB_REQ_GET_STATUS:
1237 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1238 break;
1239
1240 case USB_REQ_CLEAR_FEATURE:
1241 case USB_REQ_SET_FEATURE:
1242 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1243 break;
1244 }
1245 }
1246
1247 /* as a fallback, try delivering it to the driver to deal with */
1248
1249 if (ret == 0 && hsotg->driver) {
1250 spin_unlock(&hsotg->lock);
1251 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1252 spin_lock(&hsotg->lock);
1253 if (ret < 0)
1254 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1255 }
1256
1257 /*
1258 * the request is either unhandlable, or is not formatted correctly
1259 * so respond with a STALL for the status stage to indicate failure.
1260 */
1261
1262 if (ret < 0)
1263 dwc2_hsotg_stall_ep0(hsotg);
1264}
1265
1266/**
1267 * dwc2_hsotg_complete_setup - completion of a setup transfer
1268 * @ep: The endpoint the request was on.
1269 * @req: The request completed.
1270 *
1271 * Called on completion of any requests the driver itself submitted for
1272 * EP0 setup packets
1273 */
1274static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1275 struct usb_request *req)
1276{
1277 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1278 struct dwc2_hsotg *hsotg = hs_ep->parent;
1279
1280 if (req->status < 0) {
1281 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1282 return;
1283 }
1284
1285 spin_lock(&hsotg->lock);
1286 if (req->actual == 0)
1287 dwc2_hsotg_enqueue_setup(hsotg);
1288 else
1289 dwc2_hsotg_process_control(hsotg, req->buf);
1290 spin_unlock(&hsotg->lock);
1291}
1292
1293/**
1294 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1295 * @hsotg: The device state.
1296 *
1297 * Enqueue a request on EP0 if necessary to received any SETUP packets
1298 * received from the host.
1299 */
1300static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1301{
1302 struct usb_request *req = hsotg->ctrl_req;
1303 struct dwc2_hsotg_req *hs_req = our_req(req);
1304 int ret;
1305
1306 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1307
1308 req->zero = 0;
1309 req->length = 8;
1310 req->buf = hsotg->ctrl_buff;
1311 req->complete = dwc2_hsotg_complete_setup;
1312
1313 if (!list_empty(&hs_req->queue)) {
1314 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1315 return;
1316 }
1317
1318 hsotg->eps_out[0]->dir_in = 0;
1319 hsotg->eps_out[0]->send_zlp = 0;
1320 hsotg->ep0_state = DWC2_EP0_SETUP;
1321
1322 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1323 if (ret < 0) {
1324 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1325 /*
1326 * Don't think there's much we can do other than watch the
1327 * driver fail.
1328 */
1329 }
1330}
1331
1332static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1333 struct dwc2_hsotg_ep *hs_ep)
1334{
1335 u32 ctrl;
1336 u8 index = hs_ep->index;
1337 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1338 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1339
1340 if (hs_ep->dir_in)
1341 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
1342 index);
1343 else
1344 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1345 index);
1346
1347 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1348 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1349 epsiz_reg);
1350
1351 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1352 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1353 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1354 ctrl |= DXEPCTL_USBACTEP;
1355 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1356}
1357
1358/**
1359 * dwc2_hsotg_complete_request - complete a request given to us
1360 * @hsotg: The device state.
1361 * @hs_ep: The endpoint the request was on.
1362 * @hs_req: The request to complete.
1363 * @result: The result code (0 => Ok, otherwise errno)
1364 *
1365 * The given request has finished, so call the necessary completion
1366 * if it has one and then look to see if we can start a new request
1367 * on the endpoint.
1368 *
1369 * Note, expects the ep to already be locked as appropriate.
1370 */
1371static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1372 struct dwc2_hsotg_ep *hs_ep,
1373 struct dwc2_hsotg_req *hs_req,
1374 int result)
1375{
1376 bool restart;
1377
1378 if (!hs_req) {
1379 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1380 return;
1381 }
1382
1383 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1384 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1385
1386 /*
1387 * only replace the status if we've not already set an error
1388 * from a previous transaction
1389 */
1390
1391 if (hs_req->req.status == -EINPROGRESS)
1392 hs_req->req.status = result;
1393
1394 if (using_dma(hsotg))
1395 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1396
1397 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
1398
1399 hs_ep->req = NULL;
1400 list_del_init(&hs_req->queue);
1401
1402 /*
1403 * call the complete request with the locks off, just in case the
1404 * request tries to queue more work for this endpoint.
1405 */
1406
1407 if (hs_req->req.complete) {
1408 spin_unlock(&hsotg->lock);
1409 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
1410 spin_lock(&hsotg->lock);
1411 }
1412
1413 /*
1414 * Look to see if there is anything else to do. Note, the completion
1415 * of the previous request may have caused a new request to be started
1416 * so be careful when doing this.
1417 */
1418
1419 if (!hs_ep->req && result >= 0) {
1420 restart = !list_empty(&hs_ep->queue);
1421 if (restart) {
1422 hs_req = get_ep_head(hs_ep);
1423 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1424 }
1425 }
1426}
1427
1428/**
1429 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
1430 * @hsotg: The device state.
1431 * @ep_idx: The endpoint index for the data
1432 * @size: The size of data in the fifo, in bytes
1433 *
1434 * The FIFO status shows there is data to read from the FIFO for a given
1435 * endpoint, so sort out whether we need to read the data into a request
1436 * that has been made for that endpoint.
1437 */
1438static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
1439{
1440 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
1441 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1442 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1443 int to_read;
1444 int max_req;
1445 int read_ptr;
1446
1447
1448 if (!hs_req) {
1449 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
1450 int ptr;
1451
1452 dev_dbg(hsotg->dev,
1453 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1454 __func__, size, ep_idx, epctl);
1455
1456 /* dump the data from the FIFO, we've nothing we can do */
1457 for (ptr = 0; ptr < size; ptr += 4)
1458 (void)dwc2_readl(fifo);
1459
1460 return;
1461 }
1462
1463 to_read = size;
1464 read_ptr = hs_req->req.actual;
1465 max_req = hs_req->req.length - read_ptr;
1466
1467 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1468 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1469
1470 if (to_read > max_req) {
1471 /*
1472 * more data appeared than we where willing
1473 * to deal with in this request.
1474 */
1475
1476 /* currently we don't deal this */
1477 WARN_ON_ONCE(1);
1478 }
1479
1480 hs_ep->total_data += to_read;
1481 hs_req->req.actual += to_read;
1482 to_read = DIV_ROUND_UP(to_read, 4);
1483
1484 /*
1485 * note, we might over-write the buffer end by 3 bytes depending on
1486 * alignment of the data.
1487 */
1488 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
1489}
1490
1491/**
1492 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
1493 * @hsotg: The device instance
1494 * @dir_in: If IN zlp
1495 *
1496 * Generate a zero-length IN packet request for terminating a SETUP
1497 * transaction.
1498 *
1499 * Note, since we don't write any data to the TxFIFO, then it is
1500 * currently believed that we do not need to wait for any space in
1501 * the TxFIFO.
1502 */
1503static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
1504{
1505 /* eps_out[0] is used in both directions */
1506 hsotg->eps_out[0]->dir_in = dir_in;
1507 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
1508
1509 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
1510}
1511
1512static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
1513 u32 epctl_reg)
1514{
1515 u32 ctrl;
1516
1517 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1518 if (ctrl & DXEPCTL_EOFRNUM)
1519 ctrl |= DXEPCTL_SETEVENFR;
1520 else
1521 ctrl |= DXEPCTL_SETODDFR;
1522 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1523}
1524
1525/**
1526 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1527 * @hsotg: The device instance
1528 * @epnum: The endpoint received from
1529 *
1530 * The RXFIFO has delivered an OutDone event, which means that the data
1531 * transfer for an OUT endpoint has been completed, either by a short
1532 * packet or by the finish of a transfer.
1533 */
1534static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
1535{
1536 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
1537 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
1538 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1539 struct usb_request *req = &hs_req->req;
1540 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1541 int result = 0;
1542
1543 if (!hs_req) {
1544 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1545 return;
1546 }
1547
1548 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
1549 dev_dbg(hsotg->dev, "zlp packet received\n");
1550 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1551 dwc2_hsotg_enqueue_setup(hsotg);
1552 return;
1553 }
1554
1555 if (using_dma(hsotg)) {
1556 unsigned size_done;
1557
1558 /*
1559 * Calculate the size of the transfer by checking how much
1560 * is left in the endpoint size register and then working it
1561 * out from the amount we loaded for the transfer.
1562 *
1563 * We need to do this as DMA pointers are always 32bit aligned
1564 * so may overshoot/undershoot the transfer.
1565 */
1566
1567 size_done = hs_ep->size_loaded - size_left;
1568 size_done += hs_ep->last_load;
1569
1570 req->actual = size_done;
1571 }
1572
1573 /* if there is more request to do, schedule new transfer */
1574 if (req->actual < req->length && size_left == 0) {
1575 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1576 return;
1577 }
1578
1579 if (req->actual < req->length && req->short_not_ok) {
1580 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1581 __func__, req->actual, req->length);
1582
1583 /*
1584 * todo - what should we return here? there's no one else
1585 * even bothering to check the status.
1586 */
1587 }
1588
1589 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
1590 /* Move to STATUS IN */
1591 dwc2_hsotg_ep0_zlp(hsotg, true);
1592 return;
1593 }
1594
1595 /*
1596 * Slave mode OUT transfers do not go through XferComplete so
1597 * adjust the ISOC parity here.
1598 */
1599 if (!using_dma(hsotg)) {
1600 hs_ep->has_correct_parity = 1;
1601 if (hs_ep->isochronous && hs_ep->interval == 1)
1602 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
1603 }
1604
1605 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1606}
1607
1608/**
1609 * dwc2_hsotg_read_frameno - read current frame number
1610 * @hsotg: The device instance
1611 *
1612 * Return the current frame number
1613 */
1614static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
1615{
1616 u32 dsts;
1617
1618 dsts = dwc2_readl(hsotg->regs + DSTS);
1619 dsts &= DSTS_SOFFN_MASK;
1620 dsts >>= DSTS_SOFFN_SHIFT;
1621
1622 return dsts;
1623}
1624
1625/**
1626 * dwc2_hsotg_handle_rx - RX FIFO has data
1627 * @hsotg: The device instance
1628 *
1629 * The IRQ handler has detected that the RX FIFO has some data in it
1630 * that requires processing, so find out what is in there and do the
1631 * appropriate read.
1632 *
1633 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1634 * chunks, so if you have x packets received on an endpoint you'll get x
1635 * FIFO events delivered, each with a packet's worth of data in it.
1636 *
1637 * When using DMA, we should not be processing events from the RXFIFO
1638 * as the actual data should be sent to the memory directly and we turn
1639 * on the completion interrupts to get notifications of transfer completion.
1640 */
1641static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
1642{
1643 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
1644 u32 epnum, status, size;
1645
1646 WARN_ON(using_dma(hsotg));
1647
1648 epnum = grxstsr & GRXSTS_EPNUM_MASK;
1649 status = grxstsr & GRXSTS_PKTSTS_MASK;
1650
1651 size = grxstsr & GRXSTS_BYTECNT_MASK;
1652 size >>= GRXSTS_BYTECNT_SHIFT;
1653
1654 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1655 __func__, grxstsr, size, epnum);
1656
1657 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
1658 case GRXSTS_PKTSTS_GLOBALOUTNAK:
1659 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
1660 break;
1661
1662 case GRXSTS_PKTSTS_OUTDONE:
1663 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1664 dwc2_hsotg_read_frameno(hsotg));
1665
1666 if (!using_dma(hsotg))
1667 dwc2_hsotg_handle_outdone(hsotg, epnum);
1668 break;
1669
1670 case GRXSTS_PKTSTS_SETUPDONE:
1671 dev_dbg(hsotg->dev,
1672 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1673 dwc2_hsotg_read_frameno(hsotg),
1674 dwc2_readl(hsotg->regs + DOEPCTL(0)));
1675 /*
1676 * Call dwc2_hsotg_handle_outdone here if it was not called from
1677 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
1678 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
1679 */
1680 if (hsotg->ep0_state == DWC2_EP0_SETUP)
1681 dwc2_hsotg_handle_outdone(hsotg, epnum);
1682 break;
1683
1684 case GRXSTS_PKTSTS_OUTRX:
1685 dwc2_hsotg_rx_data(hsotg, epnum, size);
1686 break;
1687
1688 case GRXSTS_PKTSTS_SETUPRX:
1689 dev_dbg(hsotg->dev,
1690 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1691 dwc2_hsotg_read_frameno(hsotg),
1692 dwc2_readl(hsotg->regs + DOEPCTL(0)));
1693
1694 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
1695
1696 dwc2_hsotg_rx_data(hsotg, epnum, size);
1697 break;
1698
1699 default:
1700 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1701 __func__, grxstsr);
1702
1703 dwc2_hsotg_dump(hsotg);
1704 break;
1705 }
1706}
1707
1708/**
1709 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
1710 * @mps: The maximum packet size in bytes.
1711 */
1712static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
1713{
1714 switch (mps) {
1715 case 64:
1716 return D0EPCTL_MPS_64;
1717 case 32:
1718 return D0EPCTL_MPS_32;
1719 case 16:
1720 return D0EPCTL_MPS_16;
1721 case 8:
1722 return D0EPCTL_MPS_8;
1723 }
1724
1725 /* bad max packet size, warn and return invalid result */
1726 WARN_ON(1);
1727 return (u32)-1;
1728}
1729
1730/**
1731 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1732 * @hsotg: The driver state.
1733 * @ep: The index number of the endpoint
1734 * @mps: The maximum packet size in bytes
1735 *
1736 * Configure the maximum packet size for the given endpoint, updating
1737 * the hardware control registers to reflect this.
1738 */
1739static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
1740 unsigned int ep, unsigned int mps, unsigned int dir_in)
1741{
1742 struct dwc2_hsotg_ep *hs_ep;
1743 void __iomem *regs = hsotg->regs;
1744 u32 mpsval;
1745 u32 mcval;
1746 u32 reg;
1747
1748 hs_ep = index_to_ep(hsotg, ep, dir_in);
1749 if (!hs_ep)
1750 return;
1751
1752 if (ep == 0) {
1753 /* EP0 is a special case */
1754 mpsval = dwc2_hsotg_ep0_mps(mps);
1755 if (mpsval > 3)
1756 goto bad_mps;
1757 hs_ep->ep.maxpacket = mps;
1758 hs_ep->mc = 1;
1759 } else {
1760 mpsval = mps & DXEPCTL_MPS_MASK;
1761 if (mpsval > 1024)
1762 goto bad_mps;
1763 mcval = ((mps >> 11) & 0x3) + 1;
1764 hs_ep->mc = mcval;
1765 if (mcval > 3)
1766 goto bad_mps;
1767 hs_ep->ep.maxpacket = mpsval;
1768 }
1769
1770 if (dir_in) {
1771 reg = dwc2_readl(regs + DIEPCTL(ep));
1772 reg &= ~DXEPCTL_MPS_MASK;
1773 reg |= mpsval;
1774 dwc2_writel(reg, regs + DIEPCTL(ep));
1775 } else {
1776 reg = dwc2_readl(regs + DOEPCTL(ep));
1777 reg &= ~DXEPCTL_MPS_MASK;
1778 reg |= mpsval;
1779 dwc2_writel(reg, regs + DOEPCTL(ep));
1780 }
1781
1782 return;
1783
1784bad_mps:
1785 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1786}
1787
1788/**
1789 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
1790 * @hsotg: The driver state
1791 * @idx: The index for the endpoint (0..15)
1792 */
1793static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
1794{
1795 int timeout;
1796 int val;
1797
1798 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1799 hsotg->regs + GRSTCTL);
1800
1801 /* wait until the fifo is flushed */
1802 timeout = 100;
1803
1804 while (1) {
1805 val = dwc2_readl(hsotg->regs + GRSTCTL);
1806
1807 if ((val & (GRSTCTL_TXFFLSH)) == 0)
1808 break;
1809
1810 if (--timeout == 0) {
1811 dev_err(hsotg->dev,
1812 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1813 __func__, val);
1814 break;
1815 }
1816
1817 udelay(1);
1818 }
1819}
1820
1821/**
1822 * dwc2_hsotg_trytx - check to see if anything needs transmitting
1823 * @hsotg: The driver state
1824 * @hs_ep: The driver endpoint to check.
1825 *
1826 * Check to see if there is a request that has data to send, and if so
1827 * make an attempt to write data into the FIFO.
1828 */
1829static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
1830 struct dwc2_hsotg_ep *hs_ep)
1831{
1832 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1833
1834 if (!hs_ep->dir_in || !hs_req) {
1835 /**
1836 * if request is not enqueued, we disable interrupts
1837 * for endpoints, excepting ep0
1838 */
1839 if (hs_ep->index != 0)
1840 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
1841 hs_ep->dir_in, 0);
1842 return 0;
1843 }
1844
1845 if (hs_req->req.actual < hs_req->req.length) {
1846 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1847 hs_ep->index);
1848 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1849 }
1850
1851 return 0;
1852}
1853
1854/**
1855 * dwc2_hsotg_complete_in - complete IN transfer
1856 * @hsotg: The device state.
1857 * @hs_ep: The endpoint that has just completed.
1858 *
1859 * An IN transfer has been completed, update the transfer's state and then
1860 * call the relevant completion routines.
1861 */
1862static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
1863 struct dwc2_hsotg_ep *hs_ep)
1864{
1865 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1866 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1867 int size_left, size_done;
1868
1869 if (!hs_req) {
1870 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1871 return;
1872 }
1873
1874 /* Finish ZLP handling for IN EP0 transactions */
1875 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
1876 dev_dbg(hsotg->dev, "zlp packet sent\n");
1877 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1878 if (hsotg->test_mode) {
1879 int ret;
1880
1881 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
1882 if (ret < 0) {
1883 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
1884 hsotg->test_mode);
1885 dwc2_hsotg_stall_ep0(hsotg);
1886 return;
1887 }
1888 }
1889 dwc2_hsotg_enqueue_setup(hsotg);
1890 return;
1891 }
1892
1893 /*
1894 * Calculate the size of the transfer by checking how much is left
1895 * in the endpoint size register and then working it out from
1896 * the amount we loaded for the transfer.
1897 *
1898 * We do this even for DMA, as the transfer may have incremented
1899 * past the end of the buffer (DMA transfers are always 32bit
1900 * aligned).
1901 */
1902
1903 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1904
1905 size_done = hs_ep->size_loaded - size_left;
1906 size_done += hs_ep->last_load;
1907
1908 if (hs_req->req.actual != size_done)
1909 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1910 __func__, hs_req->req.actual, size_done);
1911
1912 hs_req->req.actual = size_done;
1913 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1914 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1915
1916 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1917 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1918 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1919 return;
1920 }
1921
1922 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
1923 if (hs_ep->send_zlp) {
1924 dwc2_hsotg_program_zlp(hsotg, hs_ep);
1925 hs_ep->send_zlp = 0;
1926 /* transfer will be completed on next complete interrupt */
1927 return;
1928 }
1929
1930 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
1931 /* Move to STATUS OUT */
1932 dwc2_hsotg_ep0_zlp(hsotg, false);
1933 return;
1934 }
1935
1936 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1937}
1938
1939/**
1940 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
1941 * @hsotg: The driver state
1942 * @idx: The index for the endpoint (0..15)
1943 * @dir_in: Set if this is an IN endpoint
1944 *
1945 * Process and clear any interrupt pending for an individual endpoint
1946 */
1947static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
1948 int dir_in)
1949{
1950 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
1951 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1952 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1953 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1954 u32 ints;
1955 u32 ctrl;
1956
1957 ints = dwc2_readl(hsotg->regs + epint_reg);
1958 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1959
1960 /* Clear endpoint interrupts */
1961 dwc2_writel(ints, hsotg->regs + epint_reg);
1962
1963 if (!hs_ep) {
1964 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
1965 __func__, idx, dir_in ? "in" : "out");
1966 return;
1967 }
1968
1969 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1970 __func__, idx, dir_in ? "in" : "out", ints);
1971
1972 /* Don't process XferCompl interrupt if it is a setup packet */
1973 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
1974 ints &= ~DXEPINT_XFERCOMPL;
1975
1976 if (ints & DXEPINT_XFERCOMPL) {
1977 hs_ep->has_correct_parity = 1;
1978 if (hs_ep->isochronous && hs_ep->interval == 1)
1979 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
1980
1981 dev_dbg(hsotg->dev,
1982 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
1983 __func__, dwc2_readl(hsotg->regs + epctl_reg),
1984 dwc2_readl(hsotg->regs + epsiz_reg));
1985
1986 /*
1987 * we get OutDone from the FIFO, so we only need to look
1988 * at completing IN requests here
1989 */
1990 if (dir_in) {
1991 dwc2_hsotg_complete_in(hsotg, hs_ep);
1992
1993 if (idx == 0 && !hs_ep->req)
1994 dwc2_hsotg_enqueue_setup(hsotg);
1995 } else if (using_dma(hsotg)) {
1996 /*
1997 * We're using DMA, we need to fire an OutDone here
1998 * as we ignore the RXFIFO.
1999 */
2000
2001 dwc2_hsotg_handle_outdone(hsotg, idx);
2002 }
2003 }
2004
2005 if (ints & DXEPINT_EPDISBLD) {
2006 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2007
2008 if (dir_in) {
2009 int epctl = dwc2_readl(hsotg->regs + epctl_reg);
2010
2011 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2012
2013 if ((epctl & DXEPCTL_STALL) &&
2014 (epctl & DXEPCTL_EPTYPE_BULK)) {
2015 int dctl = dwc2_readl(hsotg->regs + DCTL);
2016
2017 dctl |= DCTL_CGNPINNAK;
2018 dwc2_writel(dctl, hsotg->regs + DCTL);
2019 }
2020 }
2021 }
2022
2023 if (ints & DXEPINT_AHBERR)
2024 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2025
2026 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
2027 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2028
2029 if (using_dma(hsotg) && idx == 0) {
2030 /*
2031 * this is the notification we've received a
2032 * setup packet. In non-DMA mode we'd get this
2033 * from the RXFIFO, instead we need to process
2034 * the setup here.
2035 */
2036
2037 if (dir_in)
2038 WARN_ON_ONCE(1);
2039 else
2040 dwc2_hsotg_handle_outdone(hsotg, 0);
2041 }
2042 }
2043
2044 if (ints & DXEPINT_BACK2BACKSETUP)
2045 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2046
2047 if (dir_in && !hs_ep->isochronous) {
2048 /* not sure if this is important, but we'll clear it anyway */
2049 if (ints & DIEPMSK_INTKNTXFEMPMSK) {
2050 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2051 __func__, idx);
2052 }
2053
2054 /* this probably means something bad is happening */
2055 if (ints & DIEPMSK_INTKNEPMISMSK) {
2056 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2057 __func__, idx);
2058 }
2059
2060 /* FIFO has space or is empty (see GAHBCFG) */
2061 if (hsotg->dedicated_fifos &&
2062 ints & DIEPMSK_TXFIFOEMPTY) {
2063 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2064 __func__, idx);
2065 if (!using_dma(hsotg))
2066 dwc2_hsotg_trytx(hsotg, hs_ep);
2067 }
2068 }
2069}
2070
2071/**
2072 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2073 * @hsotg: The device state.
2074 *
2075 * Handle updating the device settings after the enumeration phase has
2076 * been completed.
2077 */
2078static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
2079{
2080 u32 dsts = dwc2_readl(hsotg->regs + DSTS);
2081 int ep0_mps = 0, ep_mps = 8;
2082
2083 /*
2084 * This should signal the finish of the enumeration phase
2085 * of the USB handshaking, so we should now know what rate
2086 * we connected at.
2087 */
2088
2089 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
2090
2091 /*
2092 * note, since we're limited by the size of transfer on EP0, and
2093 * it seems IN transfers must be a even number of packets we do
2094 * not advertise a 64byte MPS on EP0.
2095 */
2096
2097 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2098 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
2099 case DSTS_ENUMSPD_FS:
2100 case DSTS_ENUMSPD_FS48:
2101 hsotg->gadget.speed = USB_SPEED_FULL;
2102 ep0_mps = EP0_MPS_LIMIT;
2103 ep_mps = 1023;
2104 break;
2105
2106 case DSTS_ENUMSPD_HS:
2107 hsotg->gadget.speed = USB_SPEED_HIGH;
2108 ep0_mps = EP0_MPS_LIMIT;
2109 ep_mps = 1024;
2110 break;
2111
2112 case DSTS_ENUMSPD_LS:
2113 hsotg->gadget.speed = USB_SPEED_LOW;
2114 /*
2115 * note, we don't actually support LS in this driver at the
2116 * moment, and the documentation seems to imply that it isn't
2117 * supported by the PHYs on some of the devices.
2118 */
2119 break;
2120 }
2121 dev_info(hsotg->dev, "new device is %s\n",
2122 usb_speed_string(hsotg->gadget.speed));
2123
2124 /*
2125 * we should now know the maximum packet size for an
2126 * endpoint, so set the endpoints to a default value.
2127 */
2128
2129 if (ep0_mps) {
2130 int i;
2131 /* Initialize ep0 for both in and out directions */
2132 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1);
2133 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0);
2134 for (i = 1; i < hsotg->num_of_eps; i++) {
2135 if (hsotg->eps_in[i])
2136 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1);
2137 if (hsotg->eps_out[i])
2138 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0);
2139 }
2140 }
2141
2142 /* ensure after enumeration our EP0 is active */
2143
2144 dwc2_hsotg_enqueue_setup(hsotg);
2145
2146 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2147 dwc2_readl(hsotg->regs + DIEPCTL0),
2148 dwc2_readl(hsotg->regs + DOEPCTL0));
2149}
2150
2151/**
2152 * kill_all_requests - remove all requests from the endpoint's queue
2153 * @hsotg: The device state.
2154 * @ep: The endpoint the requests may be on.
2155 * @result: The result code to use.
2156 *
2157 * Go through the requests on the given endpoint and mark them
2158 * completed with the given result code.
2159 */
2160static void kill_all_requests(struct dwc2_hsotg *hsotg,
2161 struct dwc2_hsotg_ep *ep,
2162 int result)
2163{
2164 struct dwc2_hsotg_req *req, *treq;
2165 unsigned size;
2166
2167 ep->req = NULL;
2168
2169 list_for_each_entry_safe(req, treq, &ep->queue, queue)
2170 dwc2_hsotg_complete_request(hsotg, ep, req,
2171 result);
2172
2173 if (!hsotg->dedicated_fifos)
2174 return;
2175 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
2176 if (size < ep->fifo_size)
2177 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
2178}
2179
2180/**
2181 * dwc2_hsotg_disconnect - disconnect service
2182 * @hsotg: The device state.
2183 *
2184 * The device has been disconnected. Remove all current
2185 * transactions and signal the gadget driver that this
2186 * has happened.
2187 */
2188void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
2189{
2190 unsigned ep;
2191
2192 if (!hsotg->connected)
2193 return;
2194
2195 hsotg->connected = 0;
2196 hsotg->test_mode = 0;
2197
2198 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
2199 if (hsotg->eps_in[ep])
2200 kill_all_requests(hsotg, hsotg->eps_in[ep],
2201 -ESHUTDOWN);
2202 if (hsotg->eps_out[ep])
2203 kill_all_requests(hsotg, hsotg->eps_out[ep],
2204 -ESHUTDOWN);
2205 }
2206
2207 call_gadget(hsotg, disconnect);
2208 hsotg->lx_state = DWC2_L3;
2209}
2210
2211/**
2212 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2213 * @hsotg: The device state:
2214 * @periodic: True if this is a periodic FIFO interrupt
2215 */
2216static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
2217{
2218 struct dwc2_hsotg_ep *ep;
2219 int epno, ret;
2220
2221 /* look through for any more data to transmit */
2222 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2223 ep = index_to_ep(hsotg, epno, 1);
2224
2225 if (!ep)
2226 continue;
2227
2228 if (!ep->dir_in)
2229 continue;
2230
2231 if ((periodic && !ep->periodic) ||
2232 (!periodic && ep->periodic))
2233 continue;
2234
2235 ret = dwc2_hsotg_trytx(hsotg, ep);
2236 if (ret < 0)
2237 break;
2238 }
2239}
2240
2241/* IRQ flags which will trigger a retry around the IRQ loop */
2242#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2243 GINTSTS_PTXFEMP | \
2244 GINTSTS_RXFLVL)
2245
2246/**
2247 * dwc2_hsotg_core_init - issue softreset to the core
2248 * @hsotg: The device state
2249 *
2250 * Issue a soft reset to the core, and await the core finishing it.
2251 */
2252void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
2253 bool is_usb_reset)
2254{
2255 u32 intmsk;
2256 u32 val;
2257 u32 usbcfg;
2258
2259 /* Kill any ep0 requests as controller will be reinitialized */
2260 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
2261
2262 if (!is_usb_reset)
2263 if (dwc2_core_reset(hsotg))
2264 return;
2265
2266 /*
2267 * we must now enable ep0 ready for host detection and then
2268 * set configuration.
2269 */
2270
2271 /* keep other bits untouched (so e.g. forced modes are not lost) */
2272 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2273 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
2274 GUSBCFG_HNPCAP);
2275
2276 /* set the PLL on, remove the HNP/SRP and set the PHY */
2277 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
2278 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
2279 (val << GUSBCFG_USBTRDTIM_SHIFT);
2280 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2281
2282 dwc2_hsotg_init_fifo(hsotg);
2283
2284 if (!is_usb_reset)
2285 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2286
2287 dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
2288
2289 /* Clear any pending OTG interrupts */
2290 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
2291
2292 /* Clear any pending interrupts */
2293 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
2294 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
2295 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
2296 GINTSTS_USBRST | GINTSTS_RESETDET |
2297 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
2298 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
2299 GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
2300
2301 if (hsotg->core_params->external_id_pin_ctl <= 0)
2302 intmsk |= GINTSTS_CONIDSTSCHNG;
2303
2304 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
2305
2306 if (using_dma(hsotg))
2307 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
2308 (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT),
2309 hsotg->regs + GAHBCFG);
2310 else
2311 dwc2_writel(((hsotg->dedicated_fifos) ?
2312 (GAHBCFG_NP_TXF_EMP_LVL |
2313 GAHBCFG_P_TXF_EMP_LVL) : 0) |
2314 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
2315
2316 /*
2317 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2318 * when we have no data to transfer. Otherwise we get being flooded by
2319 * interrupts.
2320 */
2321
2322 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
2323 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
2324 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
2325 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2326 DIEPMSK_INTKNEPMISMSK,
2327 hsotg->regs + DIEPMSK);
2328
2329 /*
2330 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2331 * DMA mode we may need this.
2332 */
2333 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
2334 DIEPMSK_TIMEOUTMSK) : 0) |
2335 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
2336 DOEPMSK_SETUPMSK,
2337 hsotg->regs + DOEPMSK);
2338
2339 dwc2_writel(0, hsotg->regs + DAINTMSK);
2340
2341 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2342 dwc2_readl(hsotg->regs + DIEPCTL0),
2343 dwc2_readl(hsotg->regs + DOEPCTL0));
2344
2345 /* enable in and out endpoint interrupts */
2346 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
2347
2348 /*
2349 * Enable the RXFIFO when in slave mode, as this is how we collect
2350 * the data. In DMA mode, we get events from the FIFO but also
2351 * things we cannot process, so do not use it.
2352 */
2353 if (!using_dma(hsotg))
2354 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
2355
2356 /* Enable interrupts for EP0 in and out */
2357 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2358 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2359
2360 if (!is_usb_reset) {
2361 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2362 udelay(10); /* see openiboot */
2363 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2364 }
2365
2366 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
2367
2368 /*
2369 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2370 * writing to the EPCTL register..
2371 */
2372
2373 /* set to read 1 8byte packet */
2374 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2375 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
2376
2377 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2378 DXEPCTL_CNAK | DXEPCTL_EPENA |
2379 DXEPCTL_USBACTEP,
2380 hsotg->regs + DOEPCTL0);
2381
2382 /* enable, but don't activate EP0in */
2383 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2384 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
2385
2386 dwc2_hsotg_enqueue_setup(hsotg);
2387
2388 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2389 dwc2_readl(hsotg->regs + DIEPCTL0),
2390 dwc2_readl(hsotg->regs + DOEPCTL0));
2391
2392 /* clear global NAKs */
2393 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
2394 if (!is_usb_reset)
2395 val |= DCTL_SFTDISCON;
2396 __orr32(hsotg->regs + DCTL, val);
2397
2398 /* must be at-least 3ms to allow bus to see disconnect */
2399 mdelay(3);
2400
2401 hsotg->lx_state = DWC2_L0;
2402}
2403
2404static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
2405{
2406 /* set the soft-disconnect bit */
2407 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2408}
2409
2410void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
2411{
2412 /* remove the soft-disconnect and let's go */
2413 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2414}
2415
2416/**
2417 * dwc2_hsotg_irq - handle device interrupt
2418 * @irq: The IRQ number triggered
2419 * @pw: The pw value when registered the handler.
2420 */
2421static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
2422{
2423 struct dwc2_hsotg *hsotg = pw;
2424 int retry_count = 8;
2425 u32 gintsts;
2426 u32 gintmsk;
2427
2428 spin_lock(&hsotg->lock);
2429irq_retry:
2430 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
2431 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2432
2433 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2434 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2435
2436 gintsts &= gintmsk;
2437
2438 if (gintsts & GINTSTS_RESETDET) {
2439 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
2440
2441 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
2442
2443 /* This event must be used only if controller is suspended */
2444 if (hsotg->lx_state == DWC2_L2) {
2445 dwc2_exit_hibernation(hsotg, true);
2446 hsotg->lx_state = DWC2_L0;
2447 }
2448 }
2449
2450 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
2451
2452 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
2453 u32 connected = hsotg->connected;
2454
2455 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
2456 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2457 dwc2_readl(hsotg->regs + GNPTXSTS));
2458
2459 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
2460
2461 /* Report disconnection if it is not already done. */
2462 dwc2_hsotg_disconnect(hsotg);
2463
2464 if (usb_status & GOTGCTL_BSESVLD && connected)
2465 dwc2_hsotg_core_init_disconnected(hsotg, true);
2466 }
2467
2468 if (gintsts & GINTSTS_ENUMDONE) {
2469 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
2470
2471 dwc2_hsotg_irq_enumdone(hsotg);
2472 }
2473
2474 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
2475 u32 daint = dwc2_readl(hsotg->regs + DAINT);
2476 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
2477 u32 daint_out, daint_in;
2478 int ep;
2479
2480 daint &= daintmsk;
2481 daint_out = daint >> DAINT_OUTEP_SHIFT;
2482 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
2483
2484 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2485
2486 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
2487 ep++, daint_out >>= 1) {
2488 if (daint_out & 1)
2489 dwc2_hsotg_epint(hsotg, ep, 0);
2490 }
2491
2492 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
2493 ep++, daint_in >>= 1) {
2494 if (daint_in & 1)
2495 dwc2_hsotg_epint(hsotg, ep, 1);
2496 }
2497 }
2498
2499 /* check both FIFOs */
2500
2501 if (gintsts & GINTSTS_NPTXFEMP) {
2502 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2503
2504 /*
2505 * Disable the interrupt to stop it happening again
2506 * unless one of these endpoint routines decides that
2507 * it needs re-enabling
2508 */
2509
2510 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
2511 dwc2_hsotg_irq_fifoempty(hsotg, false);
2512 }
2513
2514 if (gintsts & GINTSTS_PTXFEMP) {
2515 dev_dbg(hsotg->dev, "PTxFEmp\n");
2516
2517 /* See note in GINTSTS_NPTxFEmp */
2518
2519 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
2520 dwc2_hsotg_irq_fifoempty(hsotg, true);
2521 }
2522
2523 if (gintsts & GINTSTS_RXFLVL) {
2524 /*
2525 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2526 * we need to retry dwc2_hsotg_handle_rx if this is still
2527 * set.
2528 */
2529
2530 dwc2_hsotg_handle_rx(hsotg);
2531 }
2532
2533 if (gintsts & GINTSTS_ERLYSUSP) {
2534 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2535 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
2536 }
2537
2538 /*
2539 * these next two seem to crop-up occasionally causing the core
2540 * to shutdown the USB transfer, so try clearing them and logging
2541 * the occurrence.
2542 */
2543
2544 if (gintsts & GINTSTS_GOUTNAKEFF) {
2545 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2546
2547 __orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK);
2548
2549 dwc2_hsotg_dump(hsotg);
2550 }
2551
2552 if (gintsts & GINTSTS_GINNAKEFF) {
2553 dev_info(hsotg->dev, "GINNakEff triggered\n");
2554
2555 __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
2556
2557 dwc2_hsotg_dump(hsotg);
2558 }
2559
2560 if (gintsts & GINTSTS_INCOMPL_SOIN) {
2561 u32 idx, epctl_reg;
2562 struct dwc2_hsotg_ep *hs_ep;
2563
2564 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOIN\n", __func__);
2565 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
2566 hs_ep = hsotg->eps_in[idx];
2567
2568 if (!hs_ep->isochronous || hs_ep->has_correct_parity)
2569 continue;
2570
2571 epctl_reg = DIEPCTL(idx);
2572 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
2573 }
2574 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS);
2575 }
2576
2577 if (gintsts & GINTSTS_INCOMPL_SOOUT) {
2578 u32 idx, epctl_reg;
2579 struct dwc2_hsotg_ep *hs_ep;
2580
2581 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
2582 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
2583 hs_ep = hsotg->eps_out[idx];
2584
2585 if (!hs_ep->isochronous || hs_ep->has_correct_parity)
2586 continue;
2587
2588 epctl_reg = DOEPCTL(idx);
2589 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
2590 }
2591 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS);
2592 }
2593
2594 /*
2595 * if we've had fifo events, we should try and go around the
2596 * loop again to see if there's any point in returning yet.
2597 */
2598
2599 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2600 goto irq_retry;
2601
2602 spin_unlock(&hsotg->lock);
2603
2604 return IRQ_HANDLED;
2605}
2606
2607/**
2608 * dwc2_hsotg_ep_enable - enable the given endpoint
2609 * @ep: The USB endpint to configure
2610 * @desc: The USB endpoint descriptor to configure with.
2611 *
2612 * This is called from the USB gadget code's usb_ep_enable().
2613 */
2614static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
2615 const struct usb_endpoint_descriptor *desc)
2616{
2617 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2618 struct dwc2_hsotg *hsotg = hs_ep->parent;
2619 unsigned long flags;
2620 unsigned int index = hs_ep->index;
2621 u32 epctrl_reg;
2622 u32 epctrl;
2623 u32 mps;
2624 unsigned int dir_in;
2625 unsigned int i, val, size;
2626 int ret = 0;
2627
2628 dev_dbg(hsotg->dev,
2629 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2630 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2631 desc->wMaxPacketSize, desc->bInterval);
2632
2633 /* not to be called for EP0 */
2634 WARN_ON(index == 0);
2635
2636 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2637 if (dir_in != hs_ep->dir_in) {
2638 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2639 return -EINVAL;
2640 }
2641
2642 mps = usb_endpoint_maxp(desc);
2643
2644 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
2645
2646 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2647 epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2648
2649 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2650 __func__, epctrl, epctrl_reg);
2651
2652 spin_lock_irqsave(&hsotg->lock, flags);
2653
2654 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
2655 epctrl |= DXEPCTL_MPS(mps);
2656
2657 /*
2658 * mark the endpoint as active, otherwise the core may ignore
2659 * transactions entirely for this endpoint
2660 */
2661 epctrl |= DXEPCTL_USBACTEP;
2662
2663 /*
2664 * set the NAK status on the endpoint, otherwise we might try and
2665 * do something with data that we've yet got a request to process
2666 * since the RXFIFO will take data for an endpoint even if the
2667 * size register hasn't been set.
2668 */
2669
2670 epctrl |= DXEPCTL_SNAK;
2671
2672 /* update the endpoint state */
2673 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in);
2674
2675 /* default, set to non-periodic */
2676 hs_ep->isochronous = 0;
2677 hs_ep->periodic = 0;
2678 hs_ep->halted = 0;
2679 hs_ep->interval = desc->bInterval;
2680 hs_ep->has_correct_parity = 0;
2681
2682 if (hs_ep->interval > 1 && hs_ep->mc > 1)
2683 dev_err(hsotg->dev, "MC > 1 when interval is not 1\n");
2684
2685 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2686 case USB_ENDPOINT_XFER_ISOC:
2687 epctrl |= DXEPCTL_EPTYPE_ISO;
2688 epctrl |= DXEPCTL_SETEVENFR;
2689 hs_ep->isochronous = 1;
2690 if (dir_in)
2691 hs_ep->periodic = 1;
2692 break;
2693
2694 case USB_ENDPOINT_XFER_BULK:
2695 epctrl |= DXEPCTL_EPTYPE_BULK;
2696 break;
2697
2698 case USB_ENDPOINT_XFER_INT:
2699 if (dir_in)
2700 hs_ep->periodic = 1;
2701
2702 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
2703 break;
2704
2705 case USB_ENDPOINT_XFER_CONTROL:
2706 epctrl |= DXEPCTL_EPTYPE_CONTROL;
2707 break;
2708 }
2709
2710 /* If fifo is already allocated for this ep */
2711 if (hs_ep->fifo_index) {
2712 size = hs_ep->ep.maxpacket * hs_ep->mc;
2713 /* If bigger fifo is required deallocate current one */
2714 if (size > hs_ep->fifo_size) {
2715 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
2716 hs_ep->fifo_index = 0;
2717 hs_ep->fifo_size = 0;
2718 }
2719 }
2720
2721 /*
2722 * if the hardware has dedicated fifos, we must give each IN EP
2723 * a unique tx-fifo even if it is non-periodic.
2724 */
2725 if (dir_in && hsotg->dedicated_fifos && !hs_ep->fifo_index) {
2726 u32 fifo_index = 0;
2727 u32 fifo_size = UINT_MAX;
2728 size = hs_ep->ep.maxpacket*hs_ep->mc;
2729 for (i = 1; i < hsotg->num_of_eps; ++i) {
2730 if (hsotg->fifo_map & (1<<i))
2731 continue;
2732 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
2733 val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
2734 if (val < size)
2735 continue;
2736 /* Search for smallest acceptable fifo */
2737 if (val < fifo_size) {
2738 fifo_size = val;
2739 fifo_index = i;
2740 }
2741 }
2742 if (!fifo_index) {
2743 dev_err(hsotg->dev,
2744 "%s: No suitable fifo found\n", __func__);
2745 ret = -ENOMEM;
2746 goto error;
2747 }
2748 hsotg->fifo_map |= 1 << fifo_index;
2749 epctrl |= DXEPCTL_TXFNUM(fifo_index);
2750 hs_ep->fifo_index = fifo_index;
2751 hs_ep->fifo_size = fifo_size;
2752 }
2753
2754 /* for non control endpoints, set PID to D0 */
2755 if (index)
2756 epctrl |= DXEPCTL_SETD0PID;
2757
2758 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2759 __func__, epctrl);
2760
2761 dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
2762 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2763 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
2764
2765 /* enable the endpoint interrupt */
2766 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2767
2768error:
2769 spin_unlock_irqrestore(&hsotg->lock, flags);
2770 return ret;
2771}
2772
2773/**
2774 * dwc2_hsotg_ep_disable - disable given endpoint
2775 * @ep: The endpoint to disable.
2776 */
2777static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
2778{
2779 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2780 struct dwc2_hsotg *hsotg = hs_ep->parent;
2781 int dir_in = hs_ep->dir_in;
2782 int index = hs_ep->index;
2783 unsigned long flags;
2784 u32 epctrl_reg;
2785 u32 ctrl;
2786
2787 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2788
2789 if (ep == &hsotg->eps_out[0]->ep) {
2790 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2791 return -EINVAL;
2792 }
2793
2794 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2795
2796 spin_lock_irqsave(&hsotg->lock, flags);
2797
2798 hsotg->fifo_map &= ~(1<<hs_ep->fifo_index);
2799 hs_ep->fifo_index = 0;
2800 hs_ep->fifo_size = 0;
2801
2802 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2803 ctrl &= ~DXEPCTL_EPENA;
2804 ctrl &= ~DXEPCTL_USBACTEP;
2805 ctrl |= DXEPCTL_SNAK;
2806
2807 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2808 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
2809
2810 /* disable endpoint interrupts */
2811 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2812
2813 /* terminate all requests with shutdown */
2814 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
2815
2816 spin_unlock_irqrestore(&hsotg->lock, flags);
2817 return 0;
2818}
2819
2820/**
2821 * on_list - check request is on the given endpoint
2822 * @ep: The endpoint to check.
2823 * @test: The request to test if it is on the endpoint.
2824 */
2825static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
2826{
2827 struct dwc2_hsotg_req *req, *treq;
2828
2829 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2830 if (req == test)
2831 return true;
2832 }
2833
2834 return false;
2835}
2836
2837static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg,
2838 u32 bit, u32 timeout)
2839{
2840 u32 i;
2841
2842 for (i = 0; i < timeout; i++) {
2843 if (dwc2_readl(hs_otg->regs + reg) & bit)
2844 return 0;
2845 udelay(1);
2846 }
2847
2848 return -ETIMEDOUT;
2849}
2850
2851static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2852 struct dwc2_hsotg_ep *hs_ep)
2853{
2854 u32 epctrl_reg;
2855 u32 epint_reg;
2856
2857 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
2858 DOEPCTL(hs_ep->index);
2859 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
2860 DOEPINT(hs_ep->index);
2861
2862 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
2863 hs_ep->name);
2864 if (hs_ep->dir_in) {
2865 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
2866 /* Wait for Nak effect */
2867 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
2868 DXEPINT_INEPNAKEFF, 100))
2869 dev_warn(hsotg->dev,
2870 "%s: timeout DIEPINT.NAKEFF\n", __func__);
2871 } else {
2872 /* Clear any pending nak effect interrupt */
2873 dwc2_writel(GINTSTS_GOUTNAKEFF, hsotg->regs + GINTSTS);
2874
2875 __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
2876
2877 /* Wait for global nak to take effect */
2878 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
2879 GINTSTS_GOUTNAKEFF, 100))
2880 dev_warn(hsotg->dev,
2881 "%s: timeout GINTSTS.GOUTNAKEFF\n", __func__);
2882 }
2883
2884 /* Disable ep */
2885 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
2886
2887 /* Wait for ep to be disabled */
2888 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
2889 dev_warn(hsotg->dev,
2890 "%s: timeout DOEPCTL.EPDisable\n", __func__);
2891
2892 if (hs_ep->dir_in) {
2893 if (hsotg->dedicated_fifos) {
2894 dwc2_writel(GRSTCTL_TXFNUM(hs_ep->fifo_index) |
2895 GRSTCTL_TXFFLSH, hsotg->regs + GRSTCTL);
2896 /* Wait for fifo flush */
2897 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
2898 GRSTCTL_TXFFLSH, 100))
2899 dev_warn(hsotg->dev,
2900 "%s: timeout flushing fifos\n",
2901 __func__);
2902 }
2903 /* TODO: Flush shared tx fifo */
2904 } else {
2905 /* Remove global NAKs */
2906 __bic32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
2907 }
2908}
2909
2910/**
2911 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
2912 * @ep: The endpoint to dequeue.
2913 * @req: The request to be removed from a queue.
2914 */
2915static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2916{
2917 struct dwc2_hsotg_req *hs_req = our_req(req);
2918 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2919 struct dwc2_hsotg *hs = hs_ep->parent;
2920 unsigned long flags;
2921
2922 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2923
2924 spin_lock_irqsave(&hs->lock, flags);
2925
2926 if (!on_list(hs_ep, hs_req)) {
2927 spin_unlock_irqrestore(&hs->lock, flags);
2928 return -EINVAL;
2929 }
2930
2931 /* Dequeue already started request */
2932 if (req == &hs_ep->req->req)
2933 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
2934
2935 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2936 spin_unlock_irqrestore(&hs->lock, flags);
2937
2938 return 0;
2939}
2940
2941/**
2942 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
2943 * @ep: The endpoint to set halt.
2944 * @value: Set or unset the halt.
2945 */
2946static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2947{
2948 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2949 struct dwc2_hsotg *hs = hs_ep->parent;
2950 int index = hs_ep->index;
2951 u32 epreg;
2952 u32 epctl;
2953 u32 xfertype;
2954
2955 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2956
2957 if (index == 0) {
2958 if (value)
2959 dwc2_hsotg_stall_ep0(hs);
2960 else
2961 dev_warn(hs->dev,
2962 "%s: can't clear halt on ep0\n", __func__);
2963 return 0;
2964 }
2965
2966 if (hs_ep->dir_in) {
2967 epreg = DIEPCTL(index);
2968 epctl = dwc2_readl(hs->regs + epreg);
2969
2970 if (value) {
2971 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
2972 if (epctl & DXEPCTL_EPENA)
2973 epctl |= DXEPCTL_EPDIS;
2974 } else {
2975 epctl &= ~DXEPCTL_STALL;
2976 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2977 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2978 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2979 epctl |= DXEPCTL_SETD0PID;
2980 }
2981 dwc2_writel(epctl, hs->regs + epreg);
2982 } else {
2983
2984 epreg = DOEPCTL(index);
2985 epctl = dwc2_readl(hs->regs + epreg);
2986
2987 if (value)
2988 epctl |= DXEPCTL_STALL;
2989 else {
2990 epctl &= ~DXEPCTL_STALL;
2991 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2992 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2993 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2994 epctl |= DXEPCTL_SETD0PID;
2995 }
2996 dwc2_writel(epctl, hs->regs + epreg);
2997 }
2998
2999 hs_ep->halted = value;
3000
3001 return 0;
3002}
3003
3004/**
3005 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
3006 * @ep: The endpoint to set halt.
3007 * @value: Set or unset the halt.
3008 */
3009static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
3010{
3011 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3012 struct dwc2_hsotg *hs = hs_ep->parent;
3013 unsigned long flags = 0;
3014 int ret = 0;
3015
3016 spin_lock_irqsave(&hs->lock, flags);
3017 ret = dwc2_hsotg_ep_sethalt(ep, value);
3018 spin_unlock_irqrestore(&hs->lock, flags);
3019
3020 return ret;
3021}
3022
3023static struct usb_ep_ops dwc2_hsotg_ep_ops = {
3024 .enable = dwc2_hsotg_ep_enable,
3025 .disable = dwc2_hsotg_ep_disable,
3026 .alloc_request = dwc2_hsotg_ep_alloc_request,
3027 .free_request = dwc2_hsotg_ep_free_request,
3028 .queue = dwc2_hsotg_ep_queue_lock,
3029 .dequeue = dwc2_hsotg_ep_dequeue,
3030 .set_halt = dwc2_hsotg_ep_sethalt_lock,
3031 /* note, don't believe we have any call for the fifo routines */
3032};
3033
3034/**
3035 * dwc2_hsotg_init - initalize the usb core
3036 * @hsotg: The driver state
3037 */
3038static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
3039{
3040 u32 trdtim;
3041 u32 usbcfg;
3042 /* unmask subset of endpoint interrupts */
3043
3044 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
3045 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
3046 hsotg->regs + DIEPMSK);
3047
3048 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
3049 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
3050 hsotg->regs + DOEPMSK);
3051
3052 dwc2_writel(0, hsotg->regs + DAINTMSK);
3053
3054 /* Be in disconnected state until gadget is registered */
3055 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3056
3057 /* setup fifos */
3058
3059 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3060 dwc2_readl(hsotg->regs + GRXFSIZ),
3061 dwc2_readl(hsotg->regs + GNPTXFSIZ));
3062
3063 dwc2_hsotg_init_fifo(hsotg);
3064
3065 /* keep other bits untouched (so e.g. forced modes are not lost) */
3066 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3067 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3068 GUSBCFG_HNPCAP);
3069
3070 /* set the PLL on, remove the HNP/SRP and set the PHY */
3071 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3072 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3073 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
3074 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
3075
3076 if (using_dma(hsotg))
3077 __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
3078}
3079
3080/**
3081 * dwc2_hsotg_udc_start - prepare the udc for work
3082 * @gadget: The usb gadget state
3083 * @driver: The usb gadget driver
3084 *
3085 * Perform initialization to prepare udc device and driver
3086 * to work.
3087 */
3088static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
3089 struct usb_gadget_driver *driver)
3090{
3091 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3092 unsigned long flags;
3093 int ret;
3094
3095 if (!hsotg) {
3096 pr_err("%s: called with no device\n", __func__);
3097 return -ENODEV;
3098 }
3099
3100 if (!driver) {
3101 dev_err(hsotg->dev, "%s: no driver\n", __func__);
3102 return -EINVAL;
3103 }
3104
3105 if (driver->max_speed < USB_SPEED_FULL)
3106 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
3107
3108 if (!driver->setup) {
3109 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
3110 return -EINVAL;
3111 }
3112
3113 WARN_ON(hsotg->driver);
3114
3115 driver->driver.bus = NULL;
3116 hsotg->driver = driver;
3117 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
3118 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3119
3120 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
3121 ret = dwc2_lowlevel_hw_enable(hsotg);
3122 if (ret)
3123 goto err;
3124 }
3125
3126 if (!IS_ERR_OR_NULL(hsotg->uphy))
3127 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
3128
3129 spin_lock_irqsave(&hsotg->lock, flags);
3130 dwc2_hsotg_init(hsotg);
3131 dwc2_hsotg_core_init_disconnected(hsotg, false);
3132 hsotg->enabled = 0;
3133 spin_unlock_irqrestore(&hsotg->lock, flags);
3134
3135 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
3136
3137 return 0;
3138
3139err:
3140 hsotg->driver = NULL;
3141 return ret;
3142}
3143
3144/**
3145 * dwc2_hsotg_udc_stop - stop the udc
3146 * @gadget: The usb gadget state
3147 * @driver: The usb gadget driver
3148 *
3149 * Stop udc hw block and stay tunned for future transmissions
3150 */
3151static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
3152{
3153 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3154 unsigned long flags = 0;
3155 int ep;
3156
3157 if (!hsotg)
3158 return -ENODEV;
3159
3160 /* all endpoints should be shutdown */
3161 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3162 if (hsotg->eps_in[ep])
3163 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3164 if (hsotg->eps_out[ep])
3165 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3166 }
3167
3168 spin_lock_irqsave(&hsotg->lock, flags);
3169
3170 hsotg->driver = NULL;
3171 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3172 hsotg->enabled = 0;
3173
3174 spin_unlock_irqrestore(&hsotg->lock, flags);
3175
3176 if (!IS_ERR_OR_NULL(hsotg->uphy))
3177 otg_set_peripheral(hsotg->uphy->otg, NULL);
3178
3179 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3180 dwc2_lowlevel_hw_disable(hsotg);
3181
3182 return 0;
3183}
3184
3185/**
3186 * dwc2_hsotg_gadget_getframe - read the frame number
3187 * @gadget: The usb gadget state
3188 *
3189 * Read the {micro} frame number
3190 */
3191static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
3192{
3193 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
3194}
3195
3196/**
3197 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
3198 * @gadget: The usb gadget state
3199 * @is_on: Current state of the USB PHY
3200 *
3201 * Connect/Disconnect the USB PHY pullup
3202 */
3203static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
3204{
3205 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3206 unsigned long flags = 0;
3207
3208 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
3209 hsotg->op_state);
3210
3211 /* Don't modify pullup state while in host mode */
3212 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
3213 hsotg->enabled = is_on;
3214 return 0;
3215 }
3216
3217 spin_lock_irqsave(&hsotg->lock, flags);
3218 if (is_on) {
3219 hsotg->enabled = 1;
3220 dwc2_hsotg_core_init_disconnected(hsotg, false);
3221 dwc2_hsotg_core_connect(hsotg);
3222 } else {
3223 dwc2_hsotg_core_disconnect(hsotg);
3224 dwc2_hsotg_disconnect(hsotg);
3225 hsotg->enabled = 0;
3226 }
3227
3228 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3229 spin_unlock_irqrestore(&hsotg->lock, flags);
3230
3231 return 0;
3232}
3233
3234static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
3235{
3236 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3237 unsigned long flags;
3238
3239 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
3240 spin_lock_irqsave(&hsotg->lock, flags);
3241
3242 /*
3243 * If controller is hibernated, it must exit from hibernation
3244 * before being initialized / de-initialized
3245 */
3246 if (hsotg->lx_state == DWC2_L2)
3247 dwc2_exit_hibernation(hsotg, false);
3248
3249 if (is_active) {
3250 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3251
3252 dwc2_hsotg_core_init_disconnected(hsotg, false);
3253 if (hsotg->enabled)
3254 dwc2_hsotg_core_connect(hsotg);
3255 } else {
3256 dwc2_hsotg_core_disconnect(hsotg);
3257 dwc2_hsotg_disconnect(hsotg);
3258 }
3259
3260 spin_unlock_irqrestore(&hsotg->lock, flags);
3261 return 0;
3262}
3263
3264/**
3265 * dwc2_hsotg_vbus_draw - report bMaxPower field
3266 * @gadget: The usb gadget state
3267 * @mA: Amount of current
3268 *
3269 * Report how much power the device may consume to the phy.
3270 */
3271static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA)
3272{
3273 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3274
3275 if (IS_ERR_OR_NULL(hsotg->uphy))
3276 return -ENOTSUPP;
3277 return usb_phy_set_power(hsotg->uphy, mA);
3278}
3279
3280static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
3281 .get_frame = dwc2_hsotg_gadget_getframe,
3282 .udc_start = dwc2_hsotg_udc_start,
3283 .udc_stop = dwc2_hsotg_udc_stop,
3284 .pullup = dwc2_hsotg_pullup,
3285 .vbus_session = dwc2_hsotg_vbus_session,
3286 .vbus_draw = dwc2_hsotg_vbus_draw,
3287};
3288
3289/**
3290 * dwc2_hsotg_initep - initialise a single endpoint
3291 * @hsotg: The device state.
3292 * @hs_ep: The endpoint to be initialised.
3293 * @epnum: The endpoint number
3294 *
3295 * Initialise the given endpoint (as part of the probe and device state
3296 * creation) to give to the gadget driver. Setup the endpoint name, any
3297 * direction information and other state that may be required.
3298 */
3299static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
3300 struct dwc2_hsotg_ep *hs_ep,
3301 int epnum,
3302 bool dir_in)
3303{
3304 char *dir;
3305
3306 if (epnum == 0)
3307 dir = "";
3308 else if (dir_in)
3309 dir = "in";
3310 else
3311 dir = "out";
3312
3313 hs_ep->dir_in = dir_in;
3314 hs_ep->index = epnum;
3315
3316 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3317
3318 INIT_LIST_HEAD(&hs_ep->queue);
3319 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3320
3321 /* add to the list of endpoints known by the gadget driver */
3322 if (epnum)
3323 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3324
3325 hs_ep->parent = hsotg;
3326 hs_ep->ep.name = hs_ep->name;
3327 usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT);
3328 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
3329
3330 if (epnum == 0) {
3331 hs_ep->ep.caps.type_control = true;
3332 } else {
3333 hs_ep->ep.caps.type_iso = true;
3334 hs_ep->ep.caps.type_bulk = true;
3335 hs_ep->ep.caps.type_int = true;
3336 }
3337
3338 if (dir_in)
3339 hs_ep->ep.caps.dir_in = true;
3340 else
3341 hs_ep->ep.caps.dir_out = true;
3342
3343 /*
3344 * if we're using dma, we need to set the next-endpoint pointer
3345 * to be something valid.
3346 */
3347
3348 if (using_dma(hsotg)) {
3349 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
3350 if (dir_in)
3351 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
3352 else
3353 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
3354 }
3355}
3356
3357/**
3358 * dwc2_hsotg_hw_cfg - read HW configuration registers
3359 * @param: The device state
3360 *
3361 * Read the USB core HW configuration registers
3362 */
3363static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
3364{
3365 u32 cfg;
3366 u32 ep_type;
3367 u32 i;
3368
3369 /* check hardware configuration */
3370
3371 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
3372
3373 /* Add ep0 */
3374 hsotg->num_of_eps++;
3375
3376 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct dwc2_hsotg_ep),
3377 GFP_KERNEL);
3378 if (!hsotg->eps_in[0])
3379 return -ENOMEM;
3380 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
3381 hsotg->eps_out[0] = hsotg->eps_in[0];
3382
3383 cfg = hsotg->hw_params.dev_ep_dirs;
3384 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
3385 ep_type = cfg & 3;
3386 /* Direction in or both */
3387 if (!(ep_type & 2)) {
3388 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
3389 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
3390 if (!hsotg->eps_in[i])
3391 return -ENOMEM;
3392 }
3393 /* Direction out or both */
3394 if (!(ep_type & 1)) {
3395 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
3396 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
3397 if (!hsotg->eps_out[i])
3398 return -ENOMEM;
3399 }
3400 }
3401
3402 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
3403 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
3404
3405 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3406 hsotg->num_of_eps,
3407 hsotg->dedicated_fifos ? "dedicated" : "shared",
3408 hsotg->fifo_mem);
3409 return 0;
3410}
3411
3412/**
3413 * dwc2_hsotg_dump - dump state of the udc
3414 * @param: The device state
3415 */
3416static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
3417{
3418#ifdef DEBUG
3419 struct device *dev = hsotg->dev;
3420 void __iomem *regs = hsotg->regs;
3421 u32 val;
3422 int idx;
3423
3424 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3425 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
3426 dwc2_readl(regs + DIEPMSK));
3427
3428 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
3429 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
3430
3431 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3432 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
3433
3434 /* show periodic fifo settings */
3435
3436 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3437 val = dwc2_readl(regs + DPTXFSIZN(idx));
3438 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3439 val >> FIFOSIZE_DEPTH_SHIFT,
3440 val & FIFOSIZE_STARTADDR_MASK);
3441 }
3442
3443 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
3444 dev_info(dev,
3445 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3446 dwc2_readl(regs + DIEPCTL(idx)),
3447 dwc2_readl(regs + DIEPTSIZ(idx)),
3448 dwc2_readl(regs + DIEPDMA(idx)));
3449
3450 val = dwc2_readl(regs + DOEPCTL(idx));
3451 dev_info(dev,
3452 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3453 idx, dwc2_readl(regs + DOEPCTL(idx)),
3454 dwc2_readl(regs + DOEPTSIZ(idx)),
3455 dwc2_readl(regs + DOEPDMA(idx)));
3456
3457 }
3458
3459 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3460 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
3461#endif
3462}
3463
3464#ifdef CONFIG_OF
3465static void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg)
3466{
3467 struct device_node *np = hsotg->dev->of_node;
3468 u32 len = 0;
3469 u32 i = 0;
3470
3471 /* Enable dma if requested in device tree */
3472 hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma");
3473
3474 /*
3475 * Register TX periodic fifo size per endpoint.
3476 * EP0 is excluded since it has no fifo configuration.
3477 */
3478 if (!of_find_property(np, "g-tx-fifo-size", &len))
3479 goto rx_fifo;
3480
3481 len /= sizeof(u32);
3482
3483 /* Read tx fifo sizes other than ep0 */
3484 if (of_property_read_u32_array(np, "g-tx-fifo-size",
3485 &hsotg->g_tx_fifo_sz[1], len))
3486 goto rx_fifo;
3487
3488 /* Add ep0 */
3489 len++;
3490
3491 /* Make remaining TX fifos unavailable */
3492 if (len < MAX_EPS_CHANNELS) {
3493 for (i = len; i < MAX_EPS_CHANNELS; i++)
3494 hsotg->g_tx_fifo_sz[i] = 0;
3495 }
3496
3497rx_fifo:
3498 /* Register RX fifo size */
3499 of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz);
3500
3501 /* Register NPTX fifo size */
3502 of_property_read_u32(np, "g-np-tx-fifo-size",
3503 &hsotg->g_np_g_tx_fifo_sz);
3504}
3505#else
3506static inline void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) { }
3507#endif
3508
3509/**
3510 * dwc2_gadget_init - init function for gadget
3511 * @dwc2: The data structure for the DWC2 driver.
3512 * @irq: The IRQ number for the controller.
3513 */
3514int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
3515{
3516 struct device *dev = hsotg->dev;
3517 int epnum;
3518 int ret;
3519 int i;
3520 u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE;
3521
3522 /* Initialize to legacy fifo configuration values */
3523 hsotg->g_rx_fifo_sz = 2048;
3524 hsotg->g_np_g_tx_fifo_sz = 1024;
3525 memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo));
3526 /* Device tree specific probe */
3527 dwc2_hsotg_of_probe(hsotg);
3528
3529 /* Check against largest possible value. */
3530 if (hsotg->g_np_g_tx_fifo_sz >
3531 hsotg->hw_params.dev_nperio_tx_fifo_size) {
3532 dev_warn(dev, "Specified GNPTXFDEP=%d > %d\n",
3533 hsotg->g_np_g_tx_fifo_sz,
3534 hsotg->hw_params.dev_nperio_tx_fifo_size);
3535 hsotg->g_np_g_tx_fifo_sz =
3536 hsotg->hw_params.dev_nperio_tx_fifo_size;
3537 }
3538
3539 /* Dump fifo information */
3540 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
3541 hsotg->g_np_g_tx_fifo_sz);
3542 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz);
3543 for (i = 0; i < MAX_EPS_CHANNELS; i++)
3544 dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i,
3545 hsotg->g_tx_fifo_sz[i]);
3546
3547 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3548 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
3549 hsotg->gadget.name = dev_name(dev);
3550 if (hsotg->dr_mode == USB_DR_MODE_OTG)
3551 hsotg->gadget.is_otg = 1;
3552 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3553 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3554
3555 ret = dwc2_hsotg_hw_cfg(hsotg);
3556 if (ret) {
3557 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
3558 return ret;
3559 }
3560
3561 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
3562 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3563 if (!hsotg->ctrl_buff) {
3564 dev_err(dev, "failed to allocate ctrl request buff\n");
3565 return -ENOMEM;
3566 }
3567
3568 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
3569 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3570 if (!hsotg->ep0_buff) {
3571 dev_err(dev, "failed to allocate ctrl reply buff\n");
3572 return -ENOMEM;
3573 }
3574
3575 ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED,
3576 dev_name(hsotg->dev), hsotg);
3577 if (ret < 0) {
3578 dev_err(dev, "cannot claim IRQ for gadget\n");
3579 return ret;
3580 }
3581
3582 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3583
3584 if (hsotg->num_of_eps == 0) {
3585 dev_err(dev, "wrong number of EPs (zero)\n");
3586 return -EINVAL;
3587 }
3588
3589 /* setup endpoint information */
3590
3591 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3592 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
3593
3594 /* allocate EP0 request */
3595
3596 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
3597 GFP_KERNEL);
3598 if (!hsotg->ctrl_req) {
3599 dev_err(dev, "failed to allocate ctrl req\n");
3600 return -ENOMEM;
3601 }
3602
3603 /* initialise the endpoints now the core has been initialised */
3604 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
3605 if (hsotg->eps_in[epnum])
3606 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
3607 epnum, 1);
3608 if (hsotg->eps_out[epnum])
3609 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
3610 epnum, 0);
3611 }
3612
3613 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
3614 if (ret)
3615 return ret;
3616
3617 dwc2_hsotg_dump(hsotg);
3618
3619 return 0;
3620}
3621
3622/**
3623 * dwc2_hsotg_remove - remove function for hsotg driver
3624 * @pdev: The platform information for the driver
3625 */
3626int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
3627{
3628 usb_del_gadget_udc(&hsotg->gadget);
3629
3630 return 0;
3631}
3632
3633int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
3634{
3635 unsigned long flags;
3636
3637 if (hsotg->lx_state != DWC2_L0)
3638 return 0;
3639
3640 if (hsotg->driver) {
3641 int ep;
3642
3643 dev_info(hsotg->dev, "suspending usb gadget %s\n",
3644 hsotg->driver->driver.name);
3645
3646 spin_lock_irqsave(&hsotg->lock, flags);
3647 if (hsotg->enabled)
3648 dwc2_hsotg_core_disconnect(hsotg);
3649 dwc2_hsotg_disconnect(hsotg);
3650 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3651 spin_unlock_irqrestore(&hsotg->lock, flags);
3652
3653 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3654 if (hsotg->eps_in[ep])
3655 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3656 if (hsotg->eps_out[ep])
3657 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3658 }
3659 }
3660
3661 return 0;
3662}
3663
3664int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
3665{
3666 unsigned long flags;
3667
3668 if (hsotg->lx_state == DWC2_L2)
3669 return 0;
3670
3671 if (hsotg->driver) {
3672 dev_info(hsotg->dev, "resuming usb gadget %s\n",
3673 hsotg->driver->driver.name);
3674
3675 spin_lock_irqsave(&hsotg->lock, flags);
3676 dwc2_hsotg_core_init_disconnected(hsotg, false);
3677 if (hsotg->enabled)
3678 dwc2_hsotg_core_connect(hsotg);
3679 spin_unlock_irqrestore(&hsotg->lock, flags);
3680 }
3681
3682 return 0;
3683}
3684
3685/**
3686 * dwc2_backup_device_registers() - Backup controller device registers.
3687 * When suspending usb bus, registers needs to be backuped
3688 * if controller power is disabled once suspended.
3689 *
3690 * @hsotg: Programming view of the DWC_otg controller
3691 */
3692int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
3693{
3694 struct dwc2_dregs_backup *dr;
3695 int i;
3696
3697 dev_dbg(hsotg->dev, "%s\n", __func__);
3698
3699 /* Backup dev regs */
3700 dr = &hsotg->dr_backup;
3701
3702 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
3703 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
3704 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3705 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
3706 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
3707
3708 for (i = 0; i < hsotg->num_of_eps; i++) {
3709 /* Backup IN EPs */
3710 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
3711
3712 /* Ensure DATA PID is correctly configured */
3713 if (dr->diepctl[i] & DXEPCTL_DPID)
3714 dr->diepctl[i] |= DXEPCTL_SETD1PID;
3715 else
3716 dr->diepctl[i] |= DXEPCTL_SETD0PID;
3717
3718 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
3719 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
3720
3721 /* Backup OUT EPs */
3722 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
3723
3724 /* Ensure DATA PID is correctly configured */
3725 if (dr->doepctl[i] & DXEPCTL_DPID)
3726 dr->doepctl[i] |= DXEPCTL_SETD1PID;
3727 else
3728 dr->doepctl[i] |= DXEPCTL_SETD0PID;
3729
3730 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
3731 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
3732 }
3733 dr->valid = true;
3734 return 0;
3735}
3736
3737/**
3738 * dwc2_restore_device_registers() - Restore controller device registers.
3739 * When resuming usb bus, device registers needs to be restored
3740 * if controller power were disabled.
3741 *
3742 * @hsotg: Programming view of the DWC_otg controller
3743 */
3744int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
3745{
3746 struct dwc2_dregs_backup *dr;
3747 u32 dctl;
3748 int i;
3749
3750 dev_dbg(hsotg->dev, "%s\n", __func__);
3751
3752 /* Restore dev regs */
3753 dr = &hsotg->dr_backup;
3754 if (!dr->valid) {
3755 dev_err(hsotg->dev, "%s: no device registers to restore\n",
3756 __func__);
3757 return -EINVAL;
3758 }
3759 dr->valid = false;
3760
3761 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
3762 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
3763 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
3764 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
3765 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
3766
3767 for (i = 0; i < hsotg->num_of_eps; i++) {
3768 /* Restore IN EPs */
3769 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
3770 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
3771 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
3772
3773 /* Restore OUT EPs */
3774 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
3775 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
3776 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
3777 }
3778
3779 /* Set the Power-On Programming done bit */
3780 dctl = dwc2_readl(hsotg->regs + DCTL);
3781 dctl |= DCTL_PWRONPRGDONE;
3782 dwc2_writel(dctl, hsotg->regs + DCTL);
3783
3784 return 0;
3785}
1// SPDX-License-Identifier: GPL-2.0
2/**
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * S3C USB2.0 High-speed / OtG driver
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/spinlock.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
20#include <linux/mutex.h>
21#include <linux/seq_file.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25#include <linux/of_platform.h>
26
27#include <linux/usb/ch9.h>
28#include <linux/usb/gadget.h>
29#include <linux/usb/phy.h>
30
31#include "core.h"
32#include "hw.h"
33
34/* conversion functions */
35static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
36{
37 return container_of(req, struct dwc2_hsotg_req, req);
38}
39
40static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
41{
42 return container_of(ep, struct dwc2_hsotg_ep, ep);
43}
44
45static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
46{
47 return container_of(gadget, struct dwc2_hsotg, gadget);
48}
49
50static inline void dwc2_set_bit(void __iomem *ptr, u32 val)
51{
52 dwc2_writel(dwc2_readl(ptr) | val, ptr);
53}
54
55static inline void dwc2_clear_bit(void __iomem *ptr, u32 val)
56{
57 dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
58}
59
60static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
61 u32 ep_index, u32 dir_in)
62{
63 if (dir_in)
64 return hsotg->eps_in[ep_index];
65 else
66 return hsotg->eps_out[ep_index];
67}
68
69/* forward declaration of functions */
70static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
71
72/**
73 * using_dma - return the DMA status of the driver.
74 * @hsotg: The driver state.
75 *
76 * Return true if we're using DMA.
77 *
78 * Currently, we have the DMA support code worked into everywhere
79 * that needs it, but the AMBA DMA implementation in the hardware can
80 * only DMA from 32bit aligned addresses. This means that gadgets such
81 * as the CDC Ethernet cannot work as they often pass packets which are
82 * not 32bit aligned.
83 *
84 * Unfortunately the choice to use DMA or not is global to the controller
85 * and seems to be only settable when the controller is being put through
86 * a core reset. This means we either need to fix the gadgets to take
87 * account of DMA alignment, or add bounce buffers (yuerk).
88 *
89 * g_using_dma is set depending on dts flag.
90 */
91static inline bool using_dma(struct dwc2_hsotg *hsotg)
92{
93 return hsotg->params.g_dma;
94}
95
96/*
97 * using_desc_dma - return the descriptor DMA status of the driver.
98 * @hsotg: The driver state.
99 *
100 * Return true if we're using descriptor DMA.
101 */
102static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
103{
104 return hsotg->params.g_dma_desc;
105}
106
107/**
108 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
109 * @hs_ep: The endpoint
110 * @increment: The value to increment by
111 *
112 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
113 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
114 */
115static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
116{
117 hs_ep->target_frame += hs_ep->interval;
118 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
119 hs_ep->frame_overrun = true;
120 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
121 } else {
122 hs_ep->frame_overrun = false;
123 }
124}
125
126/**
127 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
128 * @hsotg: The device state
129 * @ints: A bitmask of the interrupts to enable
130 */
131static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
132{
133 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
134 u32 new_gsintmsk;
135
136 new_gsintmsk = gsintmsk | ints;
137
138 if (new_gsintmsk != gsintmsk) {
139 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
140 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
141 }
142}
143
144/**
145 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
146 * @hsotg: The device state
147 * @ints: A bitmask of the interrupts to enable
148 */
149static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
150{
151 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
152 u32 new_gsintmsk;
153
154 new_gsintmsk = gsintmsk & ~ints;
155
156 if (new_gsintmsk != gsintmsk)
157 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
158}
159
160/**
161 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
162 * @hsotg: The device state
163 * @ep: The endpoint index
164 * @dir_in: True if direction is in.
165 * @en: The enable value, true to enable
166 *
167 * Set or clear the mask for an individual endpoint's interrupt
168 * request.
169 */
170static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
171 unsigned int ep, unsigned int dir_in,
172 unsigned int en)
173{
174 unsigned long flags;
175 u32 bit = 1 << ep;
176 u32 daint;
177
178 if (!dir_in)
179 bit <<= 16;
180
181 local_irq_save(flags);
182 daint = dwc2_readl(hsotg->regs + DAINTMSK);
183 if (en)
184 daint |= bit;
185 else
186 daint &= ~bit;
187 dwc2_writel(daint, hsotg->regs + DAINTMSK);
188 local_irq_restore(flags);
189}
190
191/**
192 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
193 */
194int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
195{
196 if (hsotg->hw_params.en_multiple_tx_fifo)
197 /* In dedicated FIFO mode we need count of IN EPs */
198 return hsotg->hw_params.num_dev_in_eps;
199 else
200 /* In shared FIFO mode we need count of Periodic IN EPs */
201 return hsotg->hw_params.num_dev_perio_in_ep;
202}
203
204/**
205 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
206 * device mode TX FIFOs
207 */
208int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
209{
210 int addr;
211 int tx_addr_max;
212 u32 np_tx_fifo_size;
213
214 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
215 hsotg->params.g_np_tx_fifo_size);
216
217 /* Get Endpoint Info Control block size in DWORDs. */
218 tx_addr_max = hsotg->hw_params.total_fifo_size;
219
220 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
221 if (tx_addr_max <= addr)
222 return 0;
223
224 return tx_addr_max - addr;
225}
226
227/**
228 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
229 * TX FIFOs
230 */
231int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
232{
233 int tx_fifo_count;
234 int tx_fifo_depth;
235
236 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
237
238 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
239
240 if (!tx_fifo_count)
241 return tx_fifo_depth;
242 else
243 return tx_fifo_depth / tx_fifo_count;
244}
245
246/**
247 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
248 * @hsotg: The device instance.
249 */
250static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
251{
252 unsigned int ep;
253 unsigned int addr;
254 int timeout;
255
256 u32 val;
257 u32 *txfsz = hsotg->params.g_tx_fifo_size;
258
259 /* Reset fifo map if not correctly cleared during previous session */
260 WARN_ON(hsotg->fifo_map);
261 hsotg->fifo_map = 0;
262
263 /* set RX/NPTX FIFO sizes */
264 dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ);
265 dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) |
266 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
267 hsotg->regs + GNPTXFSIZ);
268
269 /*
270 * arange all the rest of the TX FIFOs, as some versions of this
271 * block have overlapping default addresses. This also ensures
272 * that if the settings have been changed, then they are set to
273 * known values.
274 */
275
276 /* start at the end of the GNPTXFSIZ, rounded up */
277 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
278
279 /*
280 * Configure fifos sizes from provided configuration and assign
281 * them to endpoints dynamically according to maxpacket size value of
282 * given endpoint.
283 */
284 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
285 if (!txfsz[ep])
286 continue;
287 val = addr;
288 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
289 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
290 "insufficient fifo memory");
291 addr += txfsz[ep];
292
293 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
294 val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep));
295 }
296
297 dwc2_writel(hsotg->hw_params.total_fifo_size |
298 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
299 hsotg->regs + GDFIFOCFG);
300 /*
301 * according to p428 of the design guide, we need to ensure that
302 * all fifos are flushed before continuing
303 */
304
305 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
306 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
307
308 /* wait until the fifos are both flushed */
309 timeout = 100;
310 while (1) {
311 val = dwc2_readl(hsotg->regs + GRSTCTL);
312
313 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
314 break;
315
316 if (--timeout == 0) {
317 dev_err(hsotg->dev,
318 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
319 __func__, val);
320 break;
321 }
322
323 udelay(1);
324 }
325
326 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
327}
328
329/**
330 * @ep: USB endpoint to allocate request for.
331 * @flags: Allocation flags
332 *
333 * Allocate a new USB request structure appropriate for the specified endpoint
334 */
335static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
336 gfp_t flags)
337{
338 struct dwc2_hsotg_req *req;
339
340 req = kzalloc(sizeof(*req), flags);
341 if (!req)
342 return NULL;
343
344 INIT_LIST_HEAD(&req->queue);
345
346 return &req->req;
347}
348
349/**
350 * is_ep_periodic - return true if the endpoint is in periodic mode.
351 * @hs_ep: The endpoint to query.
352 *
353 * Returns true if the endpoint is in periodic mode, meaning it is being
354 * used for an Interrupt or ISO transfer.
355 */
356static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
357{
358 return hs_ep->periodic;
359}
360
361/**
362 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
363 * @hsotg: The device state.
364 * @hs_ep: The endpoint for the request
365 * @hs_req: The request being processed.
366 *
367 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
368 * of a request to ensure the buffer is ready for access by the caller.
369 */
370static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
371 struct dwc2_hsotg_ep *hs_ep,
372 struct dwc2_hsotg_req *hs_req)
373{
374 struct usb_request *req = &hs_req->req;
375
376 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
377}
378
379/*
380 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
381 * for Control endpoint
382 * @hsotg: The device state.
383 *
384 * This function will allocate 4 descriptor chains for EP 0: 2 for
385 * Setup stage, per one for IN and OUT data/status transactions.
386 */
387static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
388{
389 hsotg->setup_desc[0] =
390 dmam_alloc_coherent(hsotg->dev,
391 sizeof(struct dwc2_dma_desc),
392 &hsotg->setup_desc_dma[0],
393 GFP_KERNEL);
394 if (!hsotg->setup_desc[0])
395 goto fail;
396
397 hsotg->setup_desc[1] =
398 dmam_alloc_coherent(hsotg->dev,
399 sizeof(struct dwc2_dma_desc),
400 &hsotg->setup_desc_dma[1],
401 GFP_KERNEL);
402 if (!hsotg->setup_desc[1])
403 goto fail;
404
405 hsotg->ctrl_in_desc =
406 dmam_alloc_coherent(hsotg->dev,
407 sizeof(struct dwc2_dma_desc),
408 &hsotg->ctrl_in_desc_dma,
409 GFP_KERNEL);
410 if (!hsotg->ctrl_in_desc)
411 goto fail;
412
413 hsotg->ctrl_out_desc =
414 dmam_alloc_coherent(hsotg->dev,
415 sizeof(struct dwc2_dma_desc),
416 &hsotg->ctrl_out_desc_dma,
417 GFP_KERNEL);
418 if (!hsotg->ctrl_out_desc)
419 goto fail;
420
421 return 0;
422
423fail:
424 return -ENOMEM;
425}
426
427/**
428 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
429 * @hsotg: The controller state.
430 * @hs_ep: The endpoint we're going to write for.
431 * @hs_req: The request to write data for.
432 *
433 * This is called when the TxFIFO has some space in it to hold a new
434 * transmission and we have something to give it. The actual setup of
435 * the data size is done elsewhere, so all we have to do is to actually
436 * write the data.
437 *
438 * The return value is zero if there is more space (or nothing was done)
439 * otherwise -ENOSPC is returned if the FIFO space was used up.
440 *
441 * This routine is only needed for PIO
442 */
443static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
444 struct dwc2_hsotg_ep *hs_ep,
445 struct dwc2_hsotg_req *hs_req)
446{
447 bool periodic = is_ep_periodic(hs_ep);
448 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
449 int buf_pos = hs_req->req.actual;
450 int to_write = hs_ep->size_loaded;
451 void *data;
452 int can_write;
453 int pkt_round;
454 int max_transfer;
455
456 to_write -= (buf_pos - hs_ep->last_load);
457
458 /* if there's nothing to write, get out early */
459 if (to_write == 0)
460 return 0;
461
462 if (periodic && !hsotg->dedicated_fifos) {
463 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
464 int size_left;
465 int size_done;
466
467 /*
468 * work out how much data was loaded so we can calculate
469 * how much data is left in the fifo.
470 */
471
472 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
473
474 /*
475 * if shared fifo, we cannot write anything until the
476 * previous data has been completely sent.
477 */
478 if (hs_ep->fifo_load != 0) {
479 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
480 return -ENOSPC;
481 }
482
483 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
484 __func__, size_left,
485 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
486
487 /* how much of the data has moved */
488 size_done = hs_ep->size_loaded - size_left;
489
490 /* how much data is left in the fifo */
491 can_write = hs_ep->fifo_load - size_done;
492 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
493 __func__, can_write);
494
495 can_write = hs_ep->fifo_size - can_write;
496 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
497 __func__, can_write);
498
499 if (can_write <= 0) {
500 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
501 return -ENOSPC;
502 }
503 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
504 can_write = dwc2_readl(hsotg->regs +
505 DTXFSTS(hs_ep->fifo_index));
506
507 can_write &= 0xffff;
508 can_write *= 4;
509 } else {
510 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
511 dev_dbg(hsotg->dev,
512 "%s: no queue slots available (0x%08x)\n",
513 __func__, gnptxsts);
514
515 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
516 return -ENOSPC;
517 }
518
519 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
520 can_write *= 4; /* fifo size is in 32bit quantities. */
521 }
522
523 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
524
525 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
526 __func__, gnptxsts, can_write, to_write, max_transfer);
527
528 /*
529 * limit to 512 bytes of data, it seems at least on the non-periodic
530 * FIFO, requests of >512 cause the endpoint to get stuck with a
531 * fragment of the end of the transfer in it.
532 */
533 if (can_write > 512 && !periodic)
534 can_write = 512;
535
536 /*
537 * limit the write to one max-packet size worth of data, but allow
538 * the transfer to return that it did not run out of fifo space
539 * doing it.
540 */
541 if (to_write > max_transfer) {
542 to_write = max_transfer;
543
544 /* it's needed only when we do not use dedicated fifos */
545 if (!hsotg->dedicated_fifos)
546 dwc2_hsotg_en_gsint(hsotg,
547 periodic ? GINTSTS_PTXFEMP :
548 GINTSTS_NPTXFEMP);
549 }
550
551 /* see if we can write data */
552
553 if (to_write > can_write) {
554 to_write = can_write;
555 pkt_round = to_write % max_transfer;
556
557 /*
558 * Round the write down to an
559 * exact number of packets.
560 *
561 * Note, we do not currently check to see if we can ever
562 * write a full packet or not to the FIFO.
563 */
564
565 if (pkt_round)
566 to_write -= pkt_round;
567
568 /*
569 * enable correct FIFO interrupt to alert us when there
570 * is more room left.
571 */
572
573 /* it's needed only when we do not use dedicated fifos */
574 if (!hsotg->dedicated_fifos)
575 dwc2_hsotg_en_gsint(hsotg,
576 periodic ? GINTSTS_PTXFEMP :
577 GINTSTS_NPTXFEMP);
578 }
579
580 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
581 to_write, hs_req->req.length, can_write, buf_pos);
582
583 if (to_write <= 0)
584 return -ENOSPC;
585
586 hs_req->req.actual = buf_pos + to_write;
587 hs_ep->total_data += to_write;
588
589 if (periodic)
590 hs_ep->fifo_load += to_write;
591
592 to_write = DIV_ROUND_UP(to_write, 4);
593 data = hs_req->req.buf + buf_pos;
594
595 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
596
597 return (to_write >= can_write) ? -ENOSPC : 0;
598}
599
600/**
601 * get_ep_limit - get the maximum data legnth for this endpoint
602 * @hs_ep: The endpoint
603 *
604 * Return the maximum data that can be queued in one go on a given endpoint
605 * so that transfers that are too long can be split.
606 */
607static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
608{
609 int index = hs_ep->index;
610 unsigned int maxsize;
611 unsigned int maxpkt;
612
613 if (index != 0) {
614 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
615 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
616 } else {
617 maxsize = 64 + 64;
618 if (hs_ep->dir_in)
619 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
620 else
621 maxpkt = 2;
622 }
623
624 /* we made the constant loading easier above by using +1 */
625 maxpkt--;
626 maxsize--;
627
628 /*
629 * constrain by packet count if maxpkts*pktsize is greater
630 * than the length register size.
631 */
632
633 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
634 maxsize = maxpkt * hs_ep->ep.maxpacket;
635
636 return maxsize;
637}
638
639/**
640 * dwc2_hsotg_read_frameno - read current frame number
641 * @hsotg: The device instance
642 *
643 * Return the current frame number
644 */
645static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
646{
647 u32 dsts;
648
649 dsts = dwc2_readl(hsotg->regs + DSTS);
650 dsts &= DSTS_SOFFN_MASK;
651 dsts >>= DSTS_SOFFN_SHIFT;
652
653 return dsts;
654}
655
656/**
657 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
658 * DMA descriptor chain prepared for specific endpoint
659 * @hs_ep: The endpoint
660 *
661 * Return the maximum data that can be queued in one go on a given endpoint
662 * depending on its descriptor chain capacity so that transfers that
663 * are too long can be split.
664 */
665static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
666{
667 int is_isoc = hs_ep->isochronous;
668 unsigned int maxsize;
669
670 if (is_isoc)
671 maxsize = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
672 DEV_DMA_ISOC_RX_NBYTES_LIMIT;
673 else
674 maxsize = DEV_DMA_NBYTES_LIMIT;
675
676 /* Above size of one descriptor was chosen, multiple it */
677 maxsize *= MAX_DMA_DESC_NUM_GENERIC;
678
679 return maxsize;
680}
681
682/*
683 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
684 * @hs_ep: The endpoint
685 * @mask: RX/TX bytes mask to be defined
686 *
687 * Returns maximum data payload for one descriptor after analyzing endpoint
688 * characteristics.
689 * DMA descriptor transfer bytes limit depends on EP type:
690 * Control out - MPS,
691 * Isochronous - descriptor rx/tx bytes bitfield limit,
692 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
693 * have concatenations from various descriptors within one packet.
694 *
695 * Selects corresponding mask for RX/TX bytes as well.
696 */
697static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
698{
699 u32 mps = hs_ep->ep.maxpacket;
700 int dir_in = hs_ep->dir_in;
701 u32 desc_size = 0;
702
703 if (!hs_ep->index && !dir_in) {
704 desc_size = mps;
705 *mask = DEV_DMA_NBYTES_MASK;
706 } else if (hs_ep->isochronous) {
707 if (dir_in) {
708 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
709 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
710 } else {
711 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
712 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
713 }
714 } else {
715 desc_size = DEV_DMA_NBYTES_LIMIT;
716 *mask = DEV_DMA_NBYTES_MASK;
717
718 /* Round down desc_size to be mps multiple */
719 desc_size -= desc_size % mps;
720 }
721
722 return desc_size;
723}
724
725/*
726 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
727 * @hs_ep: The endpoint
728 * @dma_buff: DMA address to use
729 * @len: Length of the transfer
730 *
731 * This function will iterate over descriptor chain and fill its entries
732 * with corresponding information based on transfer data.
733 */
734static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
735 dma_addr_t dma_buff,
736 unsigned int len)
737{
738 struct dwc2_hsotg *hsotg = hs_ep->parent;
739 int dir_in = hs_ep->dir_in;
740 struct dwc2_dma_desc *desc = hs_ep->desc_list;
741 u32 mps = hs_ep->ep.maxpacket;
742 u32 maxsize = 0;
743 u32 offset = 0;
744 u32 mask = 0;
745 int i;
746
747 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
748
749 hs_ep->desc_count = (len / maxsize) +
750 ((len % maxsize) ? 1 : 0);
751 if (len == 0)
752 hs_ep->desc_count = 1;
753
754 for (i = 0; i < hs_ep->desc_count; ++i) {
755 desc->status = 0;
756 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
757 << DEV_DMA_BUFF_STS_SHIFT);
758
759 if (len > maxsize) {
760 if (!hs_ep->index && !dir_in)
761 desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
762
763 desc->status |= (maxsize <<
764 DEV_DMA_NBYTES_SHIFT & mask);
765 desc->buf = dma_buff + offset;
766
767 len -= maxsize;
768 offset += maxsize;
769 } else {
770 desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
771
772 if (dir_in)
773 desc->status |= (len % mps) ? DEV_DMA_SHORT :
774 ((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0);
775 if (len > maxsize)
776 dev_err(hsotg->dev, "wrong len %d\n", len);
777
778 desc->status |=
779 len << DEV_DMA_NBYTES_SHIFT & mask;
780 desc->buf = dma_buff + offset;
781 }
782
783 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
784 desc->status |= (DEV_DMA_BUFF_STS_HREADY
785 << DEV_DMA_BUFF_STS_SHIFT);
786 desc++;
787 }
788}
789
790/*
791 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
792 * @hs_ep: The isochronous endpoint.
793 * @dma_buff: usb requests dma buffer.
794 * @len: usb request transfer length.
795 *
796 * Finds out index of first free entry either in the bottom or up half of
797 * descriptor chain depend on which is under SW control and not processed
798 * by HW. Then fills that descriptor with the data of the arrived usb request,
799 * frame info, sets Last and IOC bits increments next_desc. If filled
800 * descriptor is not the first one, removes L bit from the previous descriptor
801 * status.
802 */
803static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
804 dma_addr_t dma_buff, unsigned int len)
805{
806 struct dwc2_dma_desc *desc;
807 struct dwc2_hsotg *hsotg = hs_ep->parent;
808 u32 index;
809 u32 maxsize = 0;
810 u32 mask = 0;
811
812 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
813 if (len > maxsize) {
814 dev_err(hsotg->dev, "wrong len %d\n", len);
815 return -EINVAL;
816 }
817
818 /*
819 * If SW has already filled half of chain, then return and wait for
820 * the other chain to be processed by HW.
821 */
822 if (hs_ep->next_desc == MAX_DMA_DESC_NUM_GENERIC / 2)
823 return -EBUSY;
824
825 /* Increment frame number by interval for IN */
826 if (hs_ep->dir_in)
827 dwc2_gadget_incr_frame_num(hs_ep);
828
829 index = (MAX_DMA_DESC_NUM_GENERIC / 2) * hs_ep->isoc_chain_num +
830 hs_ep->next_desc;
831
832 /* Sanity check of calculated index */
833 if ((hs_ep->isoc_chain_num && index > MAX_DMA_DESC_NUM_GENERIC) ||
834 (!hs_ep->isoc_chain_num && index > MAX_DMA_DESC_NUM_GENERIC / 2)) {
835 dev_err(hsotg->dev, "wrong index %d for iso chain\n", index);
836 return -EINVAL;
837 }
838
839 desc = &hs_ep->desc_list[index];
840
841 /* Clear L bit of previous desc if more than one entries in the chain */
842 if (hs_ep->next_desc)
843 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
844
845 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
846 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
847
848 desc->status = 0;
849 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
850
851 desc->buf = dma_buff;
852 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
853 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
854
855 if (hs_ep->dir_in) {
856 desc->status |= ((hs_ep->mc << DEV_DMA_ISOC_PID_SHIFT) &
857 DEV_DMA_ISOC_PID_MASK) |
858 ((len % hs_ep->ep.maxpacket) ?
859 DEV_DMA_SHORT : 0) |
860 ((hs_ep->target_frame <<
861 DEV_DMA_ISOC_FRNUM_SHIFT) &
862 DEV_DMA_ISOC_FRNUM_MASK);
863 }
864
865 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
866 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
867
868 /* Update index of last configured entry in the chain */
869 hs_ep->next_desc++;
870
871 return 0;
872}
873
874/*
875 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
876 * @hs_ep: The isochronous endpoint.
877 *
878 * Prepare first descriptor chain for isochronous endpoints. Afterwards
879 * write DMA address to HW and enable the endpoint.
880 *
881 * Switch between descriptor chains via isoc_chain_num to give SW opportunity
882 * to prepare second descriptor chain while first one is being processed by HW.
883 */
884static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
885{
886 struct dwc2_hsotg *hsotg = hs_ep->parent;
887 struct dwc2_hsotg_req *hs_req, *treq;
888 int index = hs_ep->index;
889 int ret;
890 u32 dma_reg;
891 u32 depctl;
892 u32 ctrl;
893
894 if (list_empty(&hs_ep->queue)) {
895 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
896 return;
897 }
898
899 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
900 ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
901 hs_req->req.length);
902 if (ret) {
903 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
904 break;
905 }
906 }
907
908 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
909 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
910
911 /* write descriptor chain address to control register */
912 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg);
913
914 ctrl = dwc2_readl(hsotg->regs + depctl);
915 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
916 dwc2_writel(ctrl, hsotg->regs + depctl);
917
918 /* Switch ISOC descriptor chain number being processed by SW*/
919 hs_ep->isoc_chain_num = (hs_ep->isoc_chain_num ^ 1) & 0x1;
920 hs_ep->next_desc = 0;
921}
922
923/**
924 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
925 * @hsotg: The controller state.
926 * @hs_ep: The endpoint to process a request for
927 * @hs_req: The request to start.
928 * @continuing: True if we are doing more for the current request.
929 *
930 * Start the given request running by setting the endpoint registers
931 * appropriately, and writing any data to the FIFOs.
932 */
933static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
934 struct dwc2_hsotg_ep *hs_ep,
935 struct dwc2_hsotg_req *hs_req,
936 bool continuing)
937{
938 struct usb_request *ureq = &hs_req->req;
939 int index = hs_ep->index;
940 int dir_in = hs_ep->dir_in;
941 u32 epctrl_reg;
942 u32 epsize_reg;
943 u32 epsize;
944 u32 ctrl;
945 unsigned int length;
946 unsigned int packets;
947 unsigned int maxreq;
948 unsigned int dma_reg;
949
950 if (index != 0) {
951 if (hs_ep->req && !continuing) {
952 dev_err(hsotg->dev, "%s: active request\n", __func__);
953 WARN_ON(1);
954 return;
955 } else if (hs_ep->req != hs_req && continuing) {
956 dev_err(hsotg->dev,
957 "%s: continue different req\n", __func__);
958 WARN_ON(1);
959 return;
960 }
961 }
962
963 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
964 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
965 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
966
967 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
968 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
969 hs_ep->dir_in ? "in" : "out");
970
971 /* If endpoint is stalled, we will restart request later */
972 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
973
974 if (index && ctrl & DXEPCTL_STALL) {
975 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
976 return;
977 }
978
979 length = ureq->length - ureq->actual;
980 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
981 ureq->length, ureq->actual);
982
983 if (!using_desc_dma(hsotg))
984 maxreq = get_ep_limit(hs_ep);
985 else
986 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
987
988 if (length > maxreq) {
989 int round = maxreq % hs_ep->ep.maxpacket;
990
991 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
992 __func__, length, maxreq, round);
993
994 /* round down to multiple of packets */
995 if (round)
996 maxreq -= round;
997
998 length = maxreq;
999 }
1000
1001 if (length)
1002 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1003 else
1004 packets = 1; /* send one packet if length is zero. */
1005
1006 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1007 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
1008 return;
1009 }
1010
1011 if (dir_in && index != 0)
1012 if (hs_ep->isochronous)
1013 epsize = DXEPTSIZ_MC(packets);
1014 else
1015 epsize = DXEPTSIZ_MC(1);
1016 else
1017 epsize = 0;
1018
1019 /*
1020 * zero length packet should be programmed on its own and should not
1021 * be counted in DIEPTSIZ.PktCnt with other packets.
1022 */
1023 if (dir_in && ureq->zero && !continuing) {
1024 /* Test if zlp is actually required. */
1025 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1026 !(ureq->length % hs_ep->ep.maxpacket))
1027 hs_ep->send_zlp = 1;
1028 }
1029
1030 epsize |= DXEPTSIZ_PKTCNT(packets);
1031 epsize |= DXEPTSIZ_XFERSIZE(length);
1032
1033 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1034 __func__, packets, length, ureq->length, epsize, epsize_reg);
1035
1036 /* store the request as the current one we're doing */
1037 hs_ep->req = hs_req;
1038
1039 if (using_desc_dma(hsotg)) {
1040 u32 offset = 0;
1041 u32 mps = hs_ep->ep.maxpacket;
1042
1043 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1044 if (!dir_in) {
1045 if (!index)
1046 length = mps;
1047 else if (length % mps)
1048 length += (mps - (length % mps));
1049 }
1050
1051 /*
1052 * If more data to send, adjust DMA for EP0 out data stage.
1053 * ureq->dma stays unchanged, hence increment it by already
1054 * passed passed data count before starting new transaction.
1055 */
1056 if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT &&
1057 continuing)
1058 offset = ureq->actual;
1059
1060 /* Fill DDMA chain entries */
1061 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1062 length);
1063
1064 /* write descriptor chain address to control register */
1065 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg);
1066
1067 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1068 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1069 } else {
1070 /* write size / packets */
1071 dwc2_writel(epsize, hsotg->regs + epsize_reg);
1072
1073 if (using_dma(hsotg) && !continuing && (length != 0)) {
1074 /*
1075 * write DMA address to control register, buffer
1076 * already synced by dwc2_hsotg_ep_queue().
1077 */
1078
1079 dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
1080
1081 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1082 __func__, &ureq->dma, dma_reg);
1083 }
1084 }
1085
1086 if (hs_ep->isochronous && hs_ep->interval == 1) {
1087 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
1088 dwc2_gadget_incr_frame_num(hs_ep);
1089
1090 if (hs_ep->target_frame & 0x1)
1091 ctrl |= DXEPCTL_SETODDFR;
1092 else
1093 ctrl |= DXEPCTL_SETEVENFR;
1094 }
1095
1096 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1097
1098 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1099
1100 /* For Setup request do not clear NAK */
1101 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1102 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1103
1104 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1105 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
1106
1107 /*
1108 * set these, it seems that DMA support increments past the end
1109 * of the packet buffer so we need to calculate the length from
1110 * this information.
1111 */
1112 hs_ep->size_loaded = length;
1113 hs_ep->last_load = ureq->actual;
1114
1115 if (dir_in && !using_dma(hsotg)) {
1116 /* set these anyway, we may need them for non-periodic in */
1117 hs_ep->fifo_load = 0;
1118
1119 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1120 }
1121
1122 /*
1123 * Note, trying to clear the NAK here causes problems with transmit
1124 * on the S3C6400 ending up with the TXFIFO becoming full.
1125 */
1126
1127 /* check ep is enabled */
1128 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
1129 dev_dbg(hsotg->dev,
1130 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1131 index, dwc2_readl(hsotg->regs + epctrl_reg));
1132
1133 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1134 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
1135
1136 /* enable ep interrupts */
1137 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1138}
1139
1140/**
1141 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1142 * @hsotg: The device state.
1143 * @hs_ep: The endpoint the request is on.
1144 * @req: The request being processed.
1145 *
1146 * We've been asked to queue a request, so ensure that the memory buffer
1147 * is correctly setup for DMA. If we've been passed an extant DMA address
1148 * then ensure the buffer has been synced to memory. If our buffer has no
1149 * DMA memory, then we map the memory and mark our request to allow us to
1150 * cleanup on completion.
1151 */
1152static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1153 struct dwc2_hsotg_ep *hs_ep,
1154 struct usb_request *req)
1155{
1156 int ret;
1157
1158 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1159 if (ret)
1160 goto dma_error;
1161
1162 return 0;
1163
1164dma_error:
1165 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1166 __func__, req->buf, req->length);
1167
1168 return -EIO;
1169}
1170
1171static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1172 struct dwc2_hsotg_ep *hs_ep,
1173 struct dwc2_hsotg_req *hs_req)
1174{
1175 void *req_buf = hs_req->req.buf;
1176
1177 /* If dma is not being used or buffer is aligned */
1178 if (!using_dma(hsotg) || !((long)req_buf & 3))
1179 return 0;
1180
1181 WARN_ON(hs_req->saved_req_buf);
1182
1183 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1184 hs_ep->ep.name, req_buf, hs_req->req.length);
1185
1186 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1187 if (!hs_req->req.buf) {
1188 hs_req->req.buf = req_buf;
1189 dev_err(hsotg->dev,
1190 "%s: unable to allocate memory for bounce buffer\n",
1191 __func__);
1192 return -ENOMEM;
1193 }
1194
1195 /* Save actual buffer */
1196 hs_req->saved_req_buf = req_buf;
1197
1198 if (hs_ep->dir_in)
1199 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1200 return 0;
1201}
1202
1203static void
1204dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1205 struct dwc2_hsotg_ep *hs_ep,
1206 struct dwc2_hsotg_req *hs_req)
1207{
1208 /* If dma is not being used or buffer was aligned */
1209 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1210 return;
1211
1212 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1213 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1214
1215 /* Copy data from bounce buffer on successful out transfer */
1216 if (!hs_ep->dir_in && !hs_req->req.status)
1217 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1218 hs_req->req.actual);
1219
1220 /* Free bounce buffer */
1221 kfree(hs_req->req.buf);
1222
1223 hs_req->req.buf = hs_req->saved_req_buf;
1224 hs_req->saved_req_buf = NULL;
1225}
1226
1227/**
1228 * dwc2_gadget_target_frame_elapsed - Checks target frame
1229 * @hs_ep: The driver endpoint to check
1230 *
1231 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1232 * corresponding transfer.
1233 */
1234static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1235{
1236 struct dwc2_hsotg *hsotg = hs_ep->parent;
1237 u32 target_frame = hs_ep->target_frame;
1238 u32 current_frame = dwc2_hsotg_read_frameno(hsotg);
1239 bool frame_overrun = hs_ep->frame_overrun;
1240
1241 if (!frame_overrun && current_frame >= target_frame)
1242 return true;
1243
1244 if (frame_overrun && current_frame >= target_frame &&
1245 ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
1246 return true;
1247
1248 return false;
1249}
1250
1251/*
1252 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1253 * @hsotg: The driver state
1254 * @hs_ep: the ep descriptor chain is for
1255 *
1256 * Called to update EP0 structure's pointers depend on stage of
1257 * control transfer.
1258 */
1259static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1260 struct dwc2_hsotg_ep *hs_ep)
1261{
1262 switch (hsotg->ep0_state) {
1263 case DWC2_EP0_SETUP:
1264 case DWC2_EP0_STATUS_OUT:
1265 hs_ep->desc_list = hsotg->setup_desc[0];
1266 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1267 break;
1268 case DWC2_EP0_DATA_IN:
1269 case DWC2_EP0_STATUS_IN:
1270 hs_ep->desc_list = hsotg->ctrl_in_desc;
1271 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1272 break;
1273 case DWC2_EP0_DATA_OUT:
1274 hs_ep->desc_list = hsotg->ctrl_out_desc;
1275 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1276 break;
1277 default:
1278 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1279 hsotg->ep0_state);
1280 return -EINVAL;
1281 }
1282
1283 return 0;
1284}
1285
1286static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1287 gfp_t gfp_flags)
1288{
1289 struct dwc2_hsotg_req *hs_req = our_req(req);
1290 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1291 struct dwc2_hsotg *hs = hs_ep->parent;
1292 bool first;
1293 int ret;
1294
1295 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1296 ep->name, req, req->length, req->buf, req->no_interrupt,
1297 req->zero, req->short_not_ok);
1298
1299 /* Prevent new request submission when controller is suspended */
1300 if (hs->lx_state != DWC2_L0) {
1301 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1302 __func__);
1303 return -EAGAIN;
1304 }
1305
1306 /* initialise status of the request */
1307 INIT_LIST_HEAD(&hs_req->queue);
1308 req->actual = 0;
1309 req->status = -EINPROGRESS;
1310
1311 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1312 if (ret)
1313 return ret;
1314
1315 /* if we're using DMA, sync the buffers as necessary */
1316 if (using_dma(hs)) {
1317 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1318 if (ret)
1319 return ret;
1320 }
1321 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1322 if (using_desc_dma(hs) && !hs_ep->index) {
1323 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1324 if (ret)
1325 return ret;
1326 }
1327
1328 first = list_empty(&hs_ep->queue);
1329 list_add_tail(&hs_req->queue, &hs_ep->queue);
1330
1331 /*
1332 * Handle DDMA isochronous transfers separately - just add new entry
1333 * to the half of descriptor chain that is not processed by HW.
1334 * Transfer will be started once SW gets either one of NAK or
1335 * OutTknEpDis interrupts.
1336 */
1337 if (using_desc_dma(hs) && hs_ep->isochronous &&
1338 hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1339 ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
1340 hs_req->req.length);
1341 if (ret)
1342 dev_dbg(hs->dev, "%s: ISO desc chain full\n", __func__);
1343
1344 return 0;
1345 }
1346
1347 if (first) {
1348 if (!hs_ep->isochronous) {
1349 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1350 return 0;
1351 }
1352
1353 while (dwc2_gadget_target_frame_elapsed(hs_ep))
1354 dwc2_gadget_incr_frame_num(hs_ep);
1355
1356 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1357 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1358 }
1359 return 0;
1360}
1361
1362static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1363 gfp_t gfp_flags)
1364{
1365 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1366 struct dwc2_hsotg *hs = hs_ep->parent;
1367 unsigned long flags = 0;
1368 int ret = 0;
1369
1370 spin_lock_irqsave(&hs->lock, flags);
1371 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1372 spin_unlock_irqrestore(&hs->lock, flags);
1373
1374 return ret;
1375}
1376
1377static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1378 struct usb_request *req)
1379{
1380 struct dwc2_hsotg_req *hs_req = our_req(req);
1381
1382 kfree(hs_req);
1383}
1384
1385/**
1386 * dwc2_hsotg_complete_oursetup - setup completion callback
1387 * @ep: The endpoint the request was on.
1388 * @req: The request completed.
1389 *
1390 * Called on completion of any requests the driver itself
1391 * submitted that need cleaning up.
1392 */
1393static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1394 struct usb_request *req)
1395{
1396 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1397 struct dwc2_hsotg *hsotg = hs_ep->parent;
1398
1399 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1400
1401 dwc2_hsotg_ep_free_request(ep, req);
1402}
1403
1404/**
1405 * ep_from_windex - convert control wIndex value to endpoint
1406 * @hsotg: The driver state.
1407 * @windex: The control request wIndex field (in host order).
1408 *
1409 * Convert the given wIndex into a pointer to an driver endpoint
1410 * structure, or return NULL if it is not a valid endpoint.
1411 */
1412static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1413 u32 windex)
1414{
1415 struct dwc2_hsotg_ep *ep;
1416 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1417 int idx = windex & 0x7F;
1418
1419 if (windex >= 0x100)
1420 return NULL;
1421
1422 if (idx > hsotg->num_of_eps)
1423 return NULL;
1424
1425 ep = index_to_ep(hsotg, idx, dir);
1426
1427 if (idx && ep->dir_in != dir)
1428 return NULL;
1429
1430 return ep;
1431}
1432
1433/**
1434 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1435 * @hsotg: The driver state.
1436 * @testmode: requested usb test mode
1437 * Enable usb Test Mode requested by the Host.
1438 */
1439int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1440{
1441 int dctl = dwc2_readl(hsotg->regs + DCTL);
1442
1443 dctl &= ~DCTL_TSTCTL_MASK;
1444 switch (testmode) {
1445 case TEST_J:
1446 case TEST_K:
1447 case TEST_SE0_NAK:
1448 case TEST_PACKET:
1449 case TEST_FORCE_EN:
1450 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1451 break;
1452 default:
1453 return -EINVAL;
1454 }
1455 dwc2_writel(dctl, hsotg->regs + DCTL);
1456 return 0;
1457}
1458
1459/**
1460 * dwc2_hsotg_send_reply - send reply to control request
1461 * @hsotg: The device state
1462 * @ep: Endpoint 0
1463 * @buff: Buffer for request
1464 * @length: Length of reply.
1465 *
1466 * Create a request and queue it on the given endpoint. This is useful as
1467 * an internal method of sending replies to certain control requests, etc.
1468 */
1469static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1470 struct dwc2_hsotg_ep *ep,
1471 void *buff,
1472 int length)
1473{
1474 struct usb_request *req;
1475 int ret;
1476
1477 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1478
1479 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1480 hsotg->ep0_reply = req;
1481 if (!req) {
1482 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1483 return -ENOMEM;
1484 }
1485
1486 req->buf = hsotg->ep0_buff;
1487 req->length = length;
1488 /*
1489 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1490 * STATUS stage.
1491 */
1492 req->zero = 0;
1493 req->complete = dwc2_hsotg_complete_oursetup;
1494
1495 if (length)
1496 memcpy(req->buf, buff, length);
1497
1498 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1499 if (ret) {
1500 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1501 return ret;
1502 }
1503
1504 return 0;
1505}
1506
1507/**
1508 * dwc2_hsotg_process_req_status - process request GET_STATUS
1509 * @hsotg: The device state
1510 * @ctrl: USB control request
1511 */
1512static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1513 struct usb_ctrlrequest *ctrl)
1514{
1515 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1516 struct dwc2_hsotg_ep *ep;
1517 __le16 reply;
1518 int ret;
1519
1520 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1521
1522 if (!ep0->dir_in) {
1523 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1524 return -EINVAL;
1525 }
1526
1527 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1528 case USB_RECIP_DEVICE:
1529 /*
1530 * bit 0 => self powered
1531 * bit 1 => remote wakeup
1532 */
1533 reply = cpu_to_le16(0);
1534 break;
1535
1536 case USB_RECIP_INTERFACE:
1537 /* currently, the data result should be zero */
1538 reply = cpu_to_le16(0);
1539 break;
1540
1541 case USB_RECIP_ENDPOINT:
1542 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1543 if (!ep)
1544 return -ENOENT;
1545
1546 reply = cpu_to_le16(ep->halted ? 1 : 0);
1547 break;
1548
1549 default:
1550 return 0;
1551 }
1552
1553 if (le16_to_cpu(ctrl->wLength) != 2)
1554 return -EINVAL;
1555
1556 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1557 if (ret) {
1558 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1559 return ret;
1560 }
1561
1562 return 1;
1563}
1564
1565static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1566
1567/**
1568 * get_ep_head - return the first request on the endpoint
1569 * @hs_ep: The controller endpoint to get
1570 *
1571 * Get the first request on the endpoint.
1572 */
1573static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1574{
1575 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1576 queue);
1577}
1578
1579/**
1580 * dwc2_gadget_start_next_request - Starts next request from ep queue
1581 * @hs_ep: Endpoint structure
1582 *
1583 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1584 * in its handler. Hence we need to unmask it here to be able to do
1585 * resynchronization.
1586 */
1587static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1588{
1589 u32 mask;
1590 struct dwc2_hsotg *hsotg = hs_ep->parent;
1591 int dir_in = hs_ep->dir_in;
1592 struct dwc2_hsotg_req *hs_req;
1593 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1594
1595 if (!list_empty(&hs_ep->queue)) {
1596 hs_req = get_ep_head(hs_ep);
1597 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1598 return;
1599 }
1600 if (!hs_ep->isochronous)
1601 return;
1602
1603 if (dir_in) {
1604 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1605 __func__);
1606 } else {
1607 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1608 __func__);
1609 mask = dwc2_readl(hsotg->regs + epmsk_reg);
1610 mask |= DOEPMSK_OUTTKNEPDISMSK;
1611 dwc2_writel(mask, hsotg->regs + epmsk_reg);
1612 }
1613}
1614
1615/**
1616 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1617 * @hsotg: The device state
1618 * @ctrl: USB control request
1619 */
1620static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1621 struct usb_ctrlrequest *ctrl)
1622{
1623 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1624 struct dwc2_hsotg_req *hs_req;
1625 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1626 struct dwc2_hsotg_ep *ep;
1627 int ret;
1628 bool halted;
1629 u32 recip;
1630 u32 wValue;
1631 u32 wIndex;
1632
1633 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1634 __func__, set ? "SET" : "CLEAR");
1635
1636 wValue = le16_to_cpu(ctrl->wValue);
1637 wIndex = le16_to_cpu(ctrl->wIndex);
1638 recip = ctrl->bRequestType & USB_RECIP_MASK;
1639
1640 switch (recip) {
1641 case USB_RECIP_DEVICE:
1642 switch (wValue) {
1643 case USB_DEVICE_REMOTE_WAKEUP:
1644 hsotg->remote_wakeup_allowed = 1;
1645 break;
1646
1647 case USB_DEVICE_TEST_MODE:
1648 if ((wIndex & 0xff) != 0)
1649 return -EINVAL;
1650 if (!set)
1651 return -EINVAL;
1652
1653 hsotg->test_mode = wIndex >> 8;
1654 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1655 if (ret) {
1656 dev_err(hsotg->dev,
1657 "%s: failed to send reply\n", __func__);
1658 return ret;
1659 }
1660 break;
1661 default:
1662 return -ENOENT;
1663 }
1664 break;
1665
1666 case USB_RECIP_ENDPOINT:
1667 ep = ep_from_windex(hsotg, wIndex);
1668 if (!ep) {
1669 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1670 __func__, wIndex);
1671 return -ENOENT;
1672 }
1673
1674 switch (wValue) {
1675 case USB_ENDPOINT_HALT:
1676 halted = ep->halted;
1677
1678 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1679
1680 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1681 if (ret) {
1682 dev_err(hsotg->dev,
1683 "%s: failed to send reply\n", __func__);
1684 return ret;
1685 }
1686
1687 /*
1688 * we have to complete all requests for ep if it was
1689 * halted, and the halt was cleared by CLEAR_FEATURE
1690 */
1691
1692 if (!set && halted) {
1693 /*
1694 * If we have request in progress,
1695 * then complete it
1696 */
1697 if (ep->req) {
1698 hs_req = ep->req;
1699 ep->req = NULL;
1700 list_del_init(&hs_req->queue);
1701 if (hs_req->req.complete) {
1702 spin_unlock(&hsotg->lock);
1703 usb_gadget_giveback_request(
1704 &ep->ep, &hs_req->req);
1705 spin_lock(&hsotg->lock);
1706 }
1707 }
1708
1709 /* If we have pending request, then start it */
1710 if (!ep->req)
1711 dwc2_gadget_start_next_request(ep);
1712 }
1713
1714 break;
1715
1716 default:
1717 return -ENOENT;
1718 }
1719 break;
1720 default:
1721 return -ENOENT;
1722 }
1723 return 1;
1724}
1725
1726static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1727
1728/**
1729 * dwc2_hsotg_stall_ep0 - stall ep0
1730 * @hsotg: The device state
1731 *
1732 * Set stall for ep0 as response for setup request.
1733 */
1734static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1735{
1736 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1737 u32 reg;
1738 u32 ctrl;
1739
1740 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1741 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1742
1743 /*
1744 * DxEPCTL_Stall will be cleared by EP once it has
1745 * taken effect, so no need to clear later.
1746 */
1747
1748 ctrl = dwc2_readl(hsotg->regs + reg);
1749 ctrl |= DXEPCTL_STALL;
1750 ctrl |= DXEPCTL_CNAK;
1751 dwc2_writel(ctrl, hsotg->regs + reg);
1752
1753 dev_dbg(hsotg->dev,
1754 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1755 ctrl, reg, dwc2_readl(hsotg->regs + reg));
1756
1757 /*
1758 * complete won't be called, so we enqueue
1759 * setup request here
1760 */
1761 dwc2_hsotg_enqueue_setup(hsotg);
1762}
1763
1764/**
1765 * dwc2_hsotg_process_control - process a control request
1766 * @hsotg: The device state
1767 * @ctrl: The control request received
1768 *
1769 * The controller has received the SETUP phase of a control request, and
1770 * needs to work out what to do next (and whether to pass it on to the
1771 * gadget driver).
1772 */
1773static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1774 struct usb_ctrlrequest *ctrl)
1775{
1776 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1777 int ret = 0;
1778 u32 dcfg;
1779
1780 dev_dbg(hsotg->dev,
1781 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1782 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1783 ctrl->wIndex, ctrl->wLength);
1784
1785 if (ctrl->wLength == 0) {
1786 ep0->dir_in = 1;
1787 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1788 } else if (ctrl->bRequestType & USB_DIR_IN) {
1789 ep0->dir_in = 1;
1790 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1791 } else {
1792 ep0->dir_in = 0;
1793 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1794 }
1795
1796 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1797 switch (ctrl->bRequest) {
1798 case USB_REQ_SET_ADDRESS:
1799 hsotg->connected = 1;
1800 dcfg = dwc2_readl(hsotg->regs + DCFG);
1801 dcfg &= ~DCFG_DEVADDR_MASK;
1802 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1803 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1804 dwc2_writel(dcfg, hsotg->regs + DCFG);
1805
1806 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1807
1808 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1809 return;
1810
1811 case USB_REQ_GET_STATUS:
1812 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1813 break;
1814
1815 case USB_REQ_CLEAR_FEATURE:
1816 case USB_REQ_SET_FEATURE:
1817 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1818 break;
1819 }
1820 }
1821
1822 /* as a fallback, try delivering it to the driver to deal with */
1823
1824 if (ret == 0 && hsotg->driver) {
1825 spin_unlock(&hsotg->lock);
1826 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1827 spin_lock(&hsotg->lock);
1828 if (ret < 0)
1829 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1830 }
1831
1832 /*
1833 * the request is either unhandlable, or is not formatted correctly
1834 * so respond with a STALL for the status stage to indicate failure.
1835 */
1836
1837 if (ret < 0)
1838 dwc2_hsotg_stall_ep0(hsotg);
1839}
1840
1841/**
1842 * dwc2_hsotg_complete_setup - completion of a setup transfer
1843 * @ep: The endpoint the request was on.
1844 * @req: The request completed.
1845 *
1846 * Called on completion of any requests the driver itself submitted for
1847 * EP0 setup packets
1848 */
1849static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1850 struct usb_request *req)
1851{
1852 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1853 struct dwc2_hsotg *hsotg = hs_ep->parent;
1854
1855 if (req->status < 0) {
1856 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1857 return;
1858 }
1859
1860 spin_lock(&hsotg->lock);
1861 if (req->actual == 0)
1862 dwc2_hsotg_enqueue_setup(hsotg);
1863 else
1864 dwc2_hsotg_process_control(hsotg, req->buf);
1865 spin_unlock(&hsotg->lock);
1866}
1867
1868/**
1869 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1870 * @hsotg: The device state.
1871 *
1872 * Enqueue a request on EP0 if necessary to received any SETUP packets
1873 * received from the host.
1874 */
1875static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1876{
1877 struct usb_request *req = hsotg->ctrl_req;
1878 struct dwc2_hsotg_req *hs_req = our_req(req);
1879 int ret;
1880
1881 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1882
1883 req->zero = 0;
1884 req->length = 8;
1885 req->buf = hsotg->ctrl_buff;
1886 req->complete = dwc2_hsotg_complete_setup;
1887
1888 if (!list_empty(&hs_req->queue)) {
1889 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1890 return;
1891 }
1892
1893 hsotg->eps_out[0]->dir_in = 0;
1894 hsotg->eps_out[0]->send_zlp = 0;
1895 hsotg->ep0_state = DWC2_EP0_SETUP;
1896
1897 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1898 if (ret < 0) {
1899 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1900 /*
1901 * Don't think there's much we can do other than watch the
1902 * driver fail.
1903 */
1904 }
1905}
1906
1907static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1908 struct dwc2_hsotg_ep *hs_ep)
1909{
1910 u32 ctrl;
1911 u8 index = hs_ep->index;
1912 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1913 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1914
1915 if (hs_ep->dir_in)
1916 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
1917 index);
1918 else
1919 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1920 index);
1921 if (using_desc_dma(hsotg)) {
1922 /* Not specific buffer needed for ep0 ZLP */
1923 dma_addr_t dma = hs_ep->desc_list_dma;
1924
1925 if (!index)
1926 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
1927
1928 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
1929 } else {
1930 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1931 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1932 epsiz_reg);
1933 }
1934
1935 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1936 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1937 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1938 ctrl |= DXEPCTL_USBACTEP;
1939 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1940}
1941
1942/**
1943 * dwc2_hsotg_complete_request - complete a request given to us
1944 * @hsotg: The device state.
1945 * @hs_ep: The endpoint the request was on.
1946 * @hs_req: The request to complete.
1947 * @result: The result code (0 => Ok, otherwise errno)
1948 *
1949 * The given request has finished, so call the necessary completion
1950 * if it has one and then look to see if we can start a new request
1951 * on the endpoint.
1952 *
1953 * Note, expects the ep to already be locked as appropriate.
1954 */
1955static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1956 struct dwc2_hsotg_ep *hs_ep,
1957 struct dwc2_hsotg_req *hs_req,
1958 int result)
1959{
1960 if (!hs_req) {
1961 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1962 return;
1963 }
1964
1965 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1966 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1967
1968 /*
1969 * only replace the status if we've not already set an error
1970 * from a previous transaction
1971 */
1972
1973 if (hs_req->req.status == -EINPROGRESS)
1974 hs_req->req.status = result;
1975
1976 if (using_dma(hsotg))
1977 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1978
1979 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
1980
1981 hs_ep->req = NULL;
1982 list_del_init(&hs_req->queue);
1983
1984 /*
1985 * call the complete request with the locks off, just in case the
1986 * request tries to queue more work for this endpoint.
1987 */
1988
1989 if (hs_req->req.complete) {
1990 spin_unlock(&hsotg->lock);
1991 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
1992 spin_lock(&hsotg->lock);
1993 }
1994
1995 /* In DDMA don't need to proceed to starting of next ISOC request */
1996 if (using_desc_dma(hsotg) && hs_ep->isochronous)
1997 return;
1998
1999 /*
2000 * Look to see if there is anything else to do. Note, the completion
2001 * of the previous request may have caused a new request to be started
2002 * so be careful when doing this.
2003 */
2004
2005 if (!hs_ep->req && result >= 0)
2006 dwc2_gadget_start_next_request(hs_ep);
2007}
2008
2009/*
2010 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2011 * @hs_ep: The endpoint the request was on.
2012 *
2013 * Get first request from the ep queue, determine descriptor on which complete
2014 * happened. SW based on isoc_chain_num discovers which half of the descriptor
2015 * chain is currently in use by HW, adjusts dma_address and calculates index
2016 * of completed descriptor based on the value of DEPDMA register. Update actual
2017 * length of request, giveback to gadget.
2018 */
2019static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2020{
2021 struct dwc2_hsotg *hsotg = hs_ep->parent;
2022 struct dwc2_hsotg_req *hs_req;
2023 struct usb_request *ureq;
2024 int index;
2025 dma_addr_t dma_addr;
2026 u32 dma_reg;
2027 u32 depdma;
2028 u32 desc_sts;
2029 u32 mask;
2030
2031 hs_req = get_ep_head(hs_ep);
2032 if (!hs_req) {
2033 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2034 return;
2035 }
2036 ureq = &hs_req->req;
2037
2038 dma_addr = hs_ep->desc_list_dma;
2039
2040 /*
2041 * If lower half of descriptor chain is currently use by SW,
2042 * that means higher half is being processed by HW, so shift
2043 * DMA address to higher half of descriptor chain.
2044 */
2045 if (!hs_ep->isoc_chain_num)
2046 dma_addr += sizeof(struct dwc2_dma_desc) *
2047 (MAX_DMA_DESC_NUM_GENERIC / 2);
2048
2049 dma_reg = hs_ep->dir_in ? DIEPDMA(hs_ep->index) : DOEPDMA(hs_ep->index);
2050 depdma = dwc2_readl(hsotg->regs + dma_reg);
2051
2052 index = (depdma - dma_addr) / sizeof(struct dwc2_dma_desc) - 1;
2053 desc_sts = hs_ep->desc_list[index].status;
2054
2055 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2056 DEV_DMA_ISOC_RX_NBYTES_MASK;
2057 ureq->actual = ureq->length -
2058 ((desc_sts & mask) >> DEV_DMA_ISOC_NBYTES_SHIFT);
2059
2060 /* Adjust actual length for ISOC Out if length is not align of 4 */
2061 if (!hs_ep->dir_in && ureq->length & 0x3)
2062 ureq->actual += 4 - (ureq->length & 0x3);
2063
2064 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2065}
2066
2067/*
2068 * dwc2_gadget_start_next_isoc_ddma - start next isoc request, if any.
2069 * @hs_ep: The isochronous endpoint to be re-enabled.
2070 *
2071 * If ep has been disabled due to last descriptor servicing (IN endpoint) or
2072 * BNA (OUT endpoint) check the status of other half of descriptor chain that
2073 * was under SW control till HW was busy and restart the endpoint if needed.
2074 */
2075static void dwc2_gadget_start_next_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
2076{
2077 struct dwc2_hsotg *hsotg = hs_ep->parent;
2078 u32 depctl;
2079 u32 dma_reg;
2080 u32 ctrl;
2081 u32 dma_addr = hs_ep->desc_list_dma;
2082 unsigned char index = hs_ep->index;
2083
2084 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
2085 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2086
2087 ctrl = dwc2_readl(hsotg->regs + depctl);
2088
2089 /*
2090 * EP was disabled if HW has processed last descriptor or BNA was set.
2091 * So restart ep if SW has prepared new descriptor chain in ep_queue
2092 * routine while HW was busy.
2093 */
2094 if (!(ctrl & DXEPCTL_EPENA)) {
2095 if (!hs_ep->next_desc) {
2096 dev_dbg(hsotg->dev, "%s: No more ISOC requests\n",
2097 __func__);
2098 return;
2099 }
2100
2101 dma_addr += sizeof(struct dwc2_dma_desc) *
2102 (MAX_DMA_DESC_NUM_GENERIC / 2) *
2103 hs_ep->isoc_chain_num;
2104 dwc2_writel(dma_addr, hsotg->regs + dma_reg);
2105
2106 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
2107 dwc2_writel(ctrl, hsotg->regs + depctl);
2108
2109 /* Switch ISOC descriptor chain number being processed by SW*/
2110 hs_ep->isoc_chain_num = (hs_ep->isoc_chain_num ^ 1) & 0x1;
2111 hs_ep->next_desc = 0;
2112
2113 dev_dbg(hsotg->dev, "%s: Restarted isochronous endpoint\n",
2114 __func__);
2115 }
2116}
2117
2118/**
2119 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2120 * @hsotg: The device state.
2121 * @ep_idx: The endpoint index for the data
2122 * @size: The size of data in the fifo, in bytes
2123 *
2124 * The FIFO status shows there is data to read from the FIFO for a given
2125 * endpoint, so sort out whether we need to read the data into a request
2126 * that has been made for that endpoint.
2127 */
2128static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2129{
2130 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2131 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2132 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
2133 int to_read;
2134 int max_req;
2135 int read_ptr;
2136
2137 if (!hs_req) {
2138 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
2139 int ptr;
2140
2141 dev_dbg(hsotg->dev,
2142 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2143 __func__, size, ep_idx, epctl);
2144
2145 /* dump the data from the FIFO, we've nothing we can do */
2146 for (ptr = 0; ptr < size; ptr += 4)
2147 (void)dwc2_readl(fifo);
2148
2149 return;
2150 }
2151
2152 to_read = size;
2153 read_ptr = hs_req->req.actual;
2154 max_req = hs_req->req.length - read_ptr;
2155
2156 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2157 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2158
2159 if (to_read > max_req) {
2160 /*
2161 * more data appeared than we where willing
2162 * to deal with in this request.
2163 */
2164
2165 /* currently we don't deal this */
2166 WARN_ON_ONCE(1);
2167 }
2168
2169 hs_ep->total_data += to_read;
2170 hs_req->req.actual += to_read;
2171 to_read = DIV_ROUND_UP(to_read, 4);
2172
2173 /*
2174 * note, we might over-write the buffer end by 3 bytes depending on
2175 * alignment of the data.
2176 */
2177 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
2178}
2179
2180/**
2181 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2182 * @hsotg: The device instance
2183 * @dir_in: If IN zlp
2184 *
2185 * Generate a zero-length IN packet request for terminating a SETUP
2186 * transaction.
2187 *
2188 * Note, since we don't write any data to the TxFIFO, then it is
2189 * currently believed that we do not need to wait for any space in
2190 * the TxFIFO.
2191 */
2192static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2193{
2194 /* eps_out[0] is used in both directions */
2195 hsotg->eps_out[0]->dir_in = dir_in;
2196 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2197
2198 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2199}
2200
2201static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
2202 u32 epctl_reg)
2203{
2204 u32 ctrl;
2205
2206 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
2207 if (ctrl & DXEPCTL_EOFRNUM)
2208 ctrl |= DXEPCTL_SETEVENFR;
2209 else
2210 ctrl |= DXEPCTL_SETODDFR;
2211 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
2212}
2213
2214/*
2215 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2216 * @hs_ep - The endpoint on which transfer went
2217 *
2218 * Iterate over endpoints descriptor chain and get info on bytes remained
2219 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2220 */
2221static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2222{
2223 struct dwc2_hsotg *hsotg = hs_ep->parent;
2224 unsigned int bytes_rem = 0;
2225 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2226 int i;
2227 u32 status;
2228
2229 if (!desc)
2230 return -EINVAL;
2231
2232 for (i = 0; i < hs_ep->desc_count; ++i) {
2233 status = desc->status;
2234 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2235
2236 if (status & DEV_DMA_STS_MASK)
2237 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2238 i, status & DEV_DMA_STS_MASK);
2239 }
2240
2241 return bytes_rem;
2242}
2243
2244/**
2245 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2246 * @hsotg: The device instance
2247 * @epnum: The endpoint received from
2248 *
2249 * The RXFIFO has delivered an OutDone event, which means that the data
2250 * transfer for an OUT endpoint has been completed, either by a short
2251 * packet or by the finish of a transfer.
2252 */
2253static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2254{
2255 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
2256 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2257 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2258 struct usb_request *req = &hs_req->req;
2259 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2260 int result = 0;
2261
2262 if (!hs_req) {
2263 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2264 return;
2265 }
2266
2267 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2268 dev_dbg(hsotg->dev, "zlp packet received\n");
2269 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2270 dwc2_hsotg_enqueue_setup(hsotg);
2271 return;
2272 }
2273
2274 if (using_desc_dma(hsotg))
2275 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2276
2277 if (using_dma(hsotg)) {
2278 unsigned int size_done;
2279
2280 /*
2281 * Calculate the size of the transfer by checking how much
2282 * is left in the endpoint size register and then working it
2283 * out from the amount we loaded for the transfer.
2284 *
2285 * We need to do this as DMA pointers are always 32bit aligned
2286 * so may overshoot/undershoot the transfer.
2287 */
2288
2289 size_done = hs_ep->size_loaded - size_left;
2290 size_done += hs_ep->last_load;
2291
2292 req->actual = size_done;
2293 }
2294
2295 /* if there is more request to do, schedule new transfer */
2296 if (req->actual < req->length && size_left == 0) {
2297 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2298 return;
2299 }
2300
2301 if (req->actual < req->length && req->short_not_ok) {
2302 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2303 __func__, req->actual, req->length);
2304
2305 /*
2306 * todo - what should we return here? there's no one else
2307 * even bothering to check the status.
2308 */
2309 }
2310
2311 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2312 if (!using_desc_dma(hsotg) && epnum == 0 &&
2313 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2314 /* Move to STATUS IN */
2315 dwc2_hsotg_ep0_zlp(hsotg, true);
2316 return;
2317 }
2318
2319 /*
2320 * Slave mode OUT transfers do not go through XferComplete so
2321 * adjust the ISOC parity here.
2322 */
2323 if (!using_dma(hsotg)) {
2324 if (hs_ep->isochronous && hs_ep->interval == 1)
2325 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
2326 else if (hs_ep->isochronous && hs_ep->interval > 1)
2327 dwc2_gadget_incr_frame_num(hs_ep);
2328 }
2329
2330 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2331}
2332
2333/**
2334 * dwc2_hsotg_handle_rx - RX FIFO has data
2335 * @hsotg: The device instance
2336 *
2337 * The IRQ handler has detected that the RX FIFO has some data in it
2338 * that requires processing, so find out what is in there and do the
2339 * appropriate read.
2340 *
2341 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2342 * chunks, so if you have x packets received on an endpoint you'll get x
2343 * FIFO events delivered, each with a packet's worth of data in it.
2344 *
2345 * When using DMA, we should not be processing events from the RXFIFO
2346 * as the actual data should be sent to the memory directly and we turn
2347 * on the completion interrupts to get notifications of transfer completion.
2348 */
2349static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2350{
2351 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
2352 u32 epnum, status, size;
2353
2354 WARN_ON(using_dma(hsotg));
2355
2356 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2357 status = grxstsr & GRXSTS_PKTSTS_MASK;
2358
2359 size = grxstsr & GRXSTS_BYTECNT_MASK;
2360 size >>= GRXSTS_BYTECNT_SHIFT;
2361
2362 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2363 __func__, grxstsr, size, epnum);
2364
2365 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2366 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2367 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2368 break;
2369
2370 case GRXSTS_PKTSTS_OUTDONE:
2371 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2372 dwc2_hsotg_read_frameno(hsotg));
2373
2374 if (!using_dma(hsotg))
2375 dwc2_hsotg_handle_outdone(hsotg, epnum);
2376 break;
2377
2378 case GRXSTS_PKTSTS_SETUPDONE:
2379 dev_dbg(hsotg->dev,
2380 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2381 dwc2_hsotg_read_frameno(hsotg),
2382 dwc2_readl(hsotg->regs + DOEPCTL(0)));
2383 /*
2384 * Call dwc2_hsotg_handle_outdone here if it was not called from
2385 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2386 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2387 */
2388 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2389 dwc2_hsotg_handle_outdone(hsotg, epnum);
2390 break;
2391
2392 case GRXSTS_PKTSTS_OUTRX:
2393 dwc2_hsotg_rx_data(hsotg, epnum, size);
2394 break;
2395
2396 case GRXSTS_PKTSTS_SETUPRX:
2397 dev_dbg(hsotg->dev,
2398 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2399 dwc2_hsotg_read_frameno(hsotg),
2400 dwc2_readl(hsotg->regs + DOEPCTL(0)));
2401
2402 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2403
2404 dwc2_hsotg_rx_data(hsotg, epnum, size);
2405 break;
2406
2407 default:
2408 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2409 __func__, grxstsr);
2410
2411 dwc2_hsotg_dump(hsotg);
2412 break;
2413 }
2414}
2415
2416/**
2417 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2418 * @mps: The maximum packet size in bytes.
2419 */
2420static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2421{
2422 switch (mps) {
2423 case 64:
2424 return D0EPCTL_MPS_64;
2425 case 32:
2426 return D0EPCTL_MPS_32;
2427 case 16:
2428 return D0EPCTL_MPS_16;
2429 case 8:
2430 return D0EPCTL_MPS_8;
2431 }
2432
2433 /* bad max packet size, warn and return invalid result */
2434 WARN_ON(1);
2435 return (u32)-1;
2436}
2437
2438/**
2439 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2440 * @hsotg: The driver state.
2441 * @ep: The index number of the endpoint
2442 * @mps: The maximum packet size in bytes
2443 * @mc: The multicount value
2444 *
2445 * Configure the maximum packet size for the given endpoint, updating
2446 * the hardware control registers to reflect this.
2447 */
2448static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2449 unsigned int ep, unsigned int mps,
2450 unsigned int mc, unsigned int dir_in)
2451{
2452 struct dwc2_hsotg_ep *hs_ep;
2453 void __iomem *regs = hsotg->regs;
2454 u32 reg;
2455
2456 hs_ep = index_to_ep(hsotg, ep, dir_in);
2457 if (!hs_ep)
2458 return;
2459
2460 if (ep == 0) {
2461 u32 mps_bytes = mps;
2462
2463 /* EP0 is a special case */
2464 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2465 if (mps > 3)
2466 goto bad_mps;
2467 hs_ep->ep.maxpacket = mps_bytes;
2468 hs_ep->mc = 1;
2469 } else {
2470 if (mps > 1024)
2471 goto bad_mps;
2472 hs_ep->mc = mc;
2473 if (mc > 3)
2474 goto bad_mps;
2475 hs_ep->ep.maxpacket = mps;
2476 }
2477
2478 if (dir_in) {
2479 reg = dwc2_readl(regs + DIEPCTL(ep));
2480 reg &= ~DXEPCTL_MPS_MASK;
2481 reg |= mps;
2482 dwc2_writel(reg, regs + DIEPCTL(ep));
2483 } else {
2484 reg = dwc2_readl(regs + DOEPCTL(ep));
2485 reg &= ~DXEPCTL_MPS_MASK;
2486 reg |= mps;
2487 dwc2_writel(reg, regs + DOEPCTL(ep));
2488 }
2489
2490 return;
2491
2492bad_mps:
2493 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2494}
2495
2496/**
2497 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2498 * @hsotg: The driver state
2499 * @idx: The index for the endpoint (0..15)
2500 */
2501static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2502{
2503 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2504 hsotg->regs + GRSTCTL);
2505
2506 /* wait until the fifo is flushed */
2507 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2508 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2509 __func__);
2510}
2511
2512/**
2513 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2514 * @hsotg: The driver state
2515 * @hs_ep: The driver endpoint to check.
2516 *
2517 * Check to see if there is a request that has data to send, and if so
2518 * make an attempt to write data into the FIFO.
2519 */
2520static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2521 struct dwc2_hsotg_ep *hs_ep)
2522{
2523 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2524
2525 if (!hs_ep->dir_in || !hs_req) {
2526 /**
2527 * if request is not enqueued, we disable interrupts
2528 * for endpoints, excepting ep0
2529 */
2530 if (hs_ep->index != 0)
2531 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2532 hs_ep->dir_in, 0);
2533 return 0;
2534 }
2535
2536 if (hs_req->req.actual < hs_req->req.length) {
2537 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2538 hs_ep->index);
2539 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2540 }
2541
2542 return 0;
2543}
2544
2545/**
2546 * dwc2_hsotg_complete_in - complete IN transfer
2547 * @hsotg: The device state.
2548 * @hs_ep: The endpoint that has just completed.
2549 *
2550 * An IN transfer has been completed, update the transfer's state and then
2551 * call the relevant completion routines.
2552 */
2553static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2554 struct dwc2_hsotg_ep *hs_ep)
2555{
2556 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2557 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
2558 int size_left, size_done;
2559
2560 if (!hs_req) {
2561 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2562 return;
2563 }
2564
2565 /* Finish ZLP handling for IN EP0 transactions */
2566 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2567 dev_dbg(hsotg->dev, "zlp packet sent\n");
2568
2569 /*
2570 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2571 * changed to IN. Change back to complete OUT transfer request
2572 */
2573 hs_ep->dir_in = 0;
2574
2575 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2576 if (hsotg->test_mode) {
2577 int ret;
2578
2579 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2580 if (ret < 0) {
2581 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2582 hsotg->test_mode);
2583 dwc2_hsotg_stall_ep0(hsotg);
2584 return;
2585 }
2586 }
2587 dwc2_hsotg_enqueue_setup(hsotg);
2588 return;
2589 }
2590
2591 /*
2592 * Calculate the size of the transfer by checking how much is left
2593 * in the endpoint size register and then working it out from
2594 * the amount we loaded for the transfer.
2595 *
2596 * We do this even for DMA, as the transfer may have incremented
2597 * past the end of the buffer (DMA transfers are always 32bit
2598 * aligned).
2599 */
2600 if (using_desc_dma(hsotg)) {
2601 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2602 if (size_left < 0)
2603 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2604 size_left);
2605 } else {
2606 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2607 }
2608
2609 size_done = hs_ep->size_loaded - size_left;
2610 size_done += hs_ep->last_load;
2611
2612 if (hs_req->req.actual != size_done)
2613 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2614 __func__, hs_req->req.actual, size_done);
2615
2616 hs_req->req.actual = size_done;
2617 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2618 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2619
2620 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2621 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2622 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2623 return;
2624 }
2625
2626 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
2627 if (hs_ep->send_zlp) {
2628 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2629 hs_ep->send_zlp = 0;
2630 /* transfer will be completed on next complete interrupt */
2631 return;
2632 }
2633
2634 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2635 /* Move to STATUS OUT */
2636 dwc2_hsotg_ep0_zlp(hsotg, false);
2637 return;
2638 }
2639
2640 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2641}
2642
2643/**
2644 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2645 * @hsotg: The device state.
2646 * @idx: Index of ep.
2647 * @dir_in: Endpoint direction 1-in 0-out.
2648 *
2649 * Reads for endpoint with given index and direction, by masking
2650 * epint_reg with coresponding mask.
2651 */
2652static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2653 unsigned int idx, int dir_in)
2654{
2655 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2656 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2657 u32 ints;
2658 u32 mask;
2659 u32 diepempmsk;
2660
2661 mask = dwc2_readl(hsotg->regs + epmsk_reg);
2662 diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK);
2663 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2664 mask |= DXEPINT_SETUP_RCVD;
2665
2666 ints = dwc2_readl(hsotg->regs + epint_reg);
2667 ints &= mask;
2668 return ints;
2669}
2670
2671/**
2672 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2673 * @hs_ep: The endpoint on which interrupt is asserted.
2674 *
2675 * This interrupt indicates that the endpoint has been disabled per the
2676 * application's request.
2677 *
2678 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2679 * in case of ISOC completes current request.
2680 *
2681 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2682 * request starts it.
2683 */
2684static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2685{
2686 struct dwc2_hsotg *hsotg = hs_ep->parent;
2687 struct dwc2_hsotg_req *hs_req;
2688 unsigned char idx = hs_ep->index;
2689 int dir_in = hs_ep->dir_in;
2690 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2691 int dctl = dwc2_readl(hsotg->regs + DCTL);
2692
2693 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2694
2695 if (dir_in) {
2696 int epctl = dwc2_readl(hsotg->regs + epctl_reg);
2697
2698 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2699
2700 if (hs_ep->isochronous) {
2701 dwc2_hsotg_complete_in(hsotg, hs_ep);
2702 return;
2703 }
2704
2705 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2706 int dctl = dwc2_readl(hsotg->regs + DCTL);
2707
2708 dctl |= DCTL_CGNPINNAK;
2709 dwc2_writel(dctl, hsotg->regs + DCTL);
2710 }
2711 return;
2712 }
2713
2714 if (dctl & DCTL_GOUTNAKSTS) {
2715 dctl |= DCTL_CGOUTNAK;
2716 dwc2_writel(dctl, hsotg->regs + DCTL);
2717 }
2718
2719 if (!hs_ep->isochronous)
2720 return;
2721
2722 if (list_empty(&hs_ep->queue)) {
2723 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2724 __func__, hs_ep);
2725 return;
2726 }
2727
2728 do {
2729 hs_req = get_ep_head(hs_ep);
2730 if (hs_req)
2731 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2732 -ENODATA);
2733 dwc2_gadget_incr_frame_num(hs_ep);
2734 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2735
2736 dwc2_gadget_start_next_request(hs_ep);
2737}
2738
2739/**
2740 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2741 * @hs_ep: The endpoint on which interrupt is asserted.
2742 *
2743 * This is starting point for ISOC-OUT transfer, synchronization done with
2744 * first out token received from host while corresponding EP is disabled.
2745 *
2746 * Device does not know initial frame in which out token will come. For this
2747 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2748 * getting this interrupt SW starts calculation for next transfer frame.
2749 */
2750static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2751{
2752 struct dwc2_hsotg *hsotg = ep->parent;
2753 int dir_in = ep->dir_in;
2754 u32 doepmsk;
2755 u32 tmp;
2756
2757 if (dir_in || !ep->isochronous)
2758 return;
2759
2760 /*
2761 * Store frame in which irq was asserted here, as
2762 * it can change while completing request below.
2763 */
2764 tmp = dwc2_hsotg_read_frameno(hsotg);
2765
2766 dwc2_hsotg_complete_request(hsotg, ep, get_ep_head(ep), -ENODATA);
2767
2768 if (using_desc_dma(hsotg)) {
2769 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2770 /* Start first ISO Out */
2771 ep->target_frame = tmp;
2772 dwc2_gadget_start_isoc_ddma(ep);
2773 }
2774 return;
2775 }
2776
2777 if (ep->interval > 1 &&
2778 ep->target_frame == TARGET_FRAME_INITIAL) {
2779 u32 dsts;
2780 u32 ctrl;
2781
2782 dsts = dwc2_readl(hsotg->regs + DSTS);
2783 ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2784 dwc2_gadget_incr_frame_num(ep);
2785
2786 ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index));
2787 if (ep->target_frame & 0x1)
2788 ctrl |= DXEPCTL_SETODDFR;
2789 else
2790 ctrl |= DXEPCTL_SETEVENFR;
2791
2792 dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index));
2793 }
2794
2795 dwc2_gadget_start_next_request(ep);
2796 doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
2797 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2798 dwc2_writel(doepmsk, hsotg->regs + DOEPMSK);
2799}
2800
2801/**
2802 * dwc2_gadget_handle_nak - handle NAK interrupt
2803 * @hs_ep: The endpoint on which interrupt is asserted.
2804 *
2805 * This is starting point for ISOC-IN transfer, synchronization done with
2806 * first IN token received from host while corresponding EP is disabled.
2807 *
2808 * Device does not know when first one token will arrive from host. On first
2809 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2810 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2811 * sent in response to that as there was no data in FIFO. SW is basing on this
2812 * interrupt to obtain frame in which token has come and then based on the
2813 * interval calculates next frame for transfer.
2814 */
2815static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2816{
2817 struct dwc2_hsotg *hsotg = hs_ep->parent;
2818 int dir_in = hs_ep->dir_in;
2819
2820 if (!dir_in || !hs_ep->isochronous)
2821 return;
2822
2823 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2824 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2825
2826 if (using_desc_dma(hsotg)) {
2827 dwc2_gadget_start_isoc_ddma(hs_ep);
2828 return;
2829 }
2830
2831 if (hs_ep->interval > 1) {
2832 u32 ctrl = dwc2_readl(hsotg->regs +
2833 DIEPCTL(hs_ep->index));
2834 if (hs_ep->target_frame & 0x1)
2835 ctrl |= DXEPCTL_SETODDFR;
2836 else
2837 ctrl |= DXEPCTL_SETEVENFR;
2838
2839 dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index));
2840 }
2841
2842 dwc2_hsotg_complete_request(hsotg, hs_ep,
2843 get_ep_head(hs_ep), 0);
2844 }
2845
2846 dwc2_gadget_incr_frame_num(hs_ep);
2847}
2848
2849/**
2850 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2851 * @hsotg: The driver state
2852 * @idx: The index for the endpoint (0..15)
2853 * @dir_in: Set if this is an IN endpoint
2854 *
2855 * Process and clear any interrupt pending for an individual endpoint
2856 */
2857static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2858 int dir_in)
2859{
2860 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
2861 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2862 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2863 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
2864 u32 ints;
2865 u32 ctrl;
2866
2867 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
2868 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
2869
2870 /* Clear endpoint interrupts */
2871 dwc2_writel(ints, hsotg->regs + epint_reg);
2872
2873 if (!hs_ep) {
2874 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
2875 __func__, idx, dir_in ? "in" : "out");
2876 return;
2877 }
2878
2879 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2880 __func__, idx, dir_in ? "in" : "out", ints);
2881
2882 /* Don't process XferCompl interrupt if it is a setup packet */
2883 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
2884 ints &= ~DXEPINT_XFERCOMPL;
2885
2886 /*
2887 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
2888 * stage and xfercomplete was generated without SETUP phase done
2889 * interrupt. SW should parse received setup packet only after host's
2890 * exit from setup phase of control transfer.
2891 */
2892 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
2893 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
2894 ints &= ~DXEPINT_XFERCOMPL;
2895
2896 if (ints & DXEPINT_XFERCOMPL) {
2897 dev_dbg(hsotg->dev,
2898 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
2899 __func__, dwc2_readl(hsotg->regs + epctl_reg),
2900 dwc2_readl(hsotg->regs + epsiz_reg));
2901
2902 /* In DDMA handle isochronous requests separately */
2903 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
2904 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
2905 /* Try to start next isoc request */
2906 dwc2_gadget_start_next_isoc_ddma(hs_ep);
2907 } else if (dir_in) {
2908 /*
2909 * We get OutDone from the FIFO, so we only
2910 * need to look at completing IN requests here
2911 * if operating slave mode
2912 */
2913 if (hs_ep->isochronous && hs_ep->interval > 1)
2914 dwc2_gadget_incr_frame_num(hs_ep);
2915
2916 dwc2_hsotg_complete_in(hsotg, hs_ep);
2917 if (ints & DXEPINT_NAKINTRPT)
2918 ints &= ~DXEPINT_NAKINTRPT;
2919
2920 if (idx == 0 && !hs_ep->req)
2921 dwc2_hsotg_enqueue_setup(hsotg);
2922 } else if (using_dma(hsotg)) {
2923 /*
2924 * We're using DMA, we need to fire an OutDone here
2925 * as we ignore the RXFIFO.
2926 */
2927 if (hs_ep->isochronous && hs_ep->interval > 1)
2928 dwc2_gadget_incr_frame_num(hs_ep);
2929
2930 dwc2_hsotg_handle_outdone(hsotg, idx);
2931 }
2932 }
2933
2934 if (ints & DXEPINT_EPDISBLD)
2935 dwc2_gadget_handle_ep_disabled(hs_ep);
2936
2937 if (ints & DXEPINT_OUTTKNEPDIS)
2938 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
2939
2940 if (ints & DXEPINT_NAKINTRPT)
2941 dwc2_gadget_handle_nak(hs_ep);
2942
2943 if (ints & DXEPINT_AHBERR)
2944 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2945
2946 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
2947 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2948
2949 if (using_dma(hsotg) && idx == 0) {
2950 /*
2951 * this is the notification we've received a
2952 * setup packet. In non-DMA mode we'd get this
2953 * from the RXFIFO, instead we need to process
2954 * the setup here.
2955 */
2956
2957 if (dir_in)
2958 WARN_ON_ONCE(1);
2959 else
2960 dwc2_hsotg_handle_outdone(hsotg, 0);
2961 }
2962 }
2963
2964 if (ints & DXEPINT_STSPHSERCVD) {
2965 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
2966
2967 /* Safety check EP0 state when STSPHSERCVD asserted */
2968 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2969 /* Move to STATUS IN for DDMA */
2970 if (using_desc_dma(hsotg))
2971 dwc2_hsotg_ep0_zlp(hsotg, true);
2972 }
2973
2974 }
2975
2976 if (ints & DXEPINT_BACK2BACKSETUP)
2977 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2978
2979 if (ints & DXEPINT_BNAINTR) {
2980 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
2981
2982 /*
2983 * Try to start next isoc request, if any.
2984 * Sometimes the endpoint remains enabled after BNA interrupt
2985 * assertion, which is not expected, hence we can enter here
2986 * couple of times.
2987 */
2988 if (hs_ep->isochronous)
2989 dwc2_gadget_start_next_isoc_ddma(hs_ep);
2990 }
2991
2992 if (dir_in && !hs_ep->isochronous) {
2993 /* not sure if this is important, but we'll clear it anyway */
2994 if (ints & DXEPINT_INTKNTXFEMP) {
2995 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2996 __func__, idx);
2997 }
2998
2999 /* this probably means something bad is happening */
3000 if (ints & DXEPINT_INTKNEPMIS) {
3001 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3002 __func__, idx);
3003 }
3004
3005 /* FIFO has space or is empty (see GAHBCFG) */
3006 if (hsotg->dedicated_fifos &&
3007 ints & DXEPINT_TXFEMP) {
3008 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3009 __func__, idx);
3010 if (!using_dma(hsotg))
3011 dwc2_hsotg_trytx(hsotg, hs_ep);
3012 }
3013 }
3014}
3015
3016/**
3017 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3018 * @hsotg: The device state.
3019 *
3020 * Handle updating the device settings after the enumeration phase has
3021 * been completed.
3022 */
3023static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3024{
3025 u32 dsts = dwc2_readl(hsotg->regs + DSTS);
3026 int ep0_mps = 0, ep_mps = 8;
3027
3028 /*
3029 * This should signal the finish of the enumeration phase
3030 * of the USB handshaking, so we should now know what rate
3031 * we connected at.
3032 */
3033
3034 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3035
3036 /*
3037 * note, since we're limited by the size of transfer on EP0, and
3038 * it seems IN transfers must be a even number of packets we do
3039 * not advertise a 64byte MPS on EP0.
3040 */
3041
3042 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3043 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3044 case DSTS_ENUMSPD_FS:
3045 case DSTS_ENUMSPD_FS48:
3046 hsotg->gadget.speed = USB_SPEED_FULL;
3047 ep0_mps = EP0_MPS_LIMIT;
3048 ep_mps = 1023;
3049 break;
3050
3051 case DSTS_ENUMSPD_HS:
3052 hsotg->gadget.speed = USB_SPEED_HIGH;
3053 ep0_mps = EP0_MPS_LIMIT;
3054 ep_mps = 1024;
3055 break;
3056
3057 case DSTS_ENUMSPD_LS:
3058 hsotg->gadget.speed = USB_SPEED_LOW;
3059 ep0_mps = 8;
3060 ep_mps = 8;
3061 /*
3062 * note, we don't actually support LS in this driver at the
3063 * moment, and the documentation seems to imply that it isn't
3064 * supported by the PHYs on some of the devices.
3065 */
3066 break;
3067 }
3068 dev_info(hsotg->dev, "new device is %s\n",
3069 usb_speed_string(hsotg->gadget.speed));
3070
3071 /*
3072 * we should now know the maximum packet size for an
3073 * endpoint, so set the endpoints to a default value.
3074 */
3075
3076 if (ep0_mps) {
3077 int i;
3078 /* Initialize ep0 for both in and out directions */
3079 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3080 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3081 for (i = 1; i < hsotg->num_of_eps; i++) {
3082 if (hsotg->eps_in[i])
3083 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3084 0, 1);
3085 if (hsotg->eps_out[i])
3086 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3087 0, 0);
3088 }
3089 }
3090
3091 /* ensure after enumeration our EP0 is active */
3092
3093 dwc2_hsotg_enqueue_setup(hsotg);
3094
3095 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3096 dwc2_readl(hsotg->regs + DIEPCTL0),
3097 dwc2_readl(hsotg->regs + DOEPCTL0));
3098}
3099
3100/**
3101 * kill_all_requests - remove all requests from the endpoint's queue
3102 * @hsotg: The device state.
3103 * @ep: The endpoint the requests may be on.
3104 * @result: The result code to use.
3105 *
3106 * Go through the requests on the given endpoint and mark them
3107 * completed with the given result code.
3108 */
3109static void kill_all_requests(struct dwc2_hsotg *hsotg,
3110 struct dwc2_hsotg_ep *ep,
3111 int result)
3112{
3113 struct dwc2_hsotg_req *req, *treq;
3114 unsigned int size;
3115
3116 ep->req = NULL;
3117
3118 list_for_each_entry_safe(req, treq, &ep->queue, queue)
3119 dwc2_hsotg_complete_request(hsotg, ep, req,
3120 result);
3121
3122 if (!hsotg->dedicated_fifos)
3123 return;
3124 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3125 if (size < ep->fifo_size)
3126 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3127}
3128
3129/**
3130 * dwc2_hsotg_disconnect - disconnect service
3131 * @hsotg: The device state.
3132 *
3133 * The device has been disconnected. Remove all current
3134 * transactions and signal the gadget driver that this
3135 * has happened.
3136 */
3137void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3138{
3139 unsigned int ep;
3140
3141 if (!hsotg->connected)
3142 return;
3143
3144 hsotg->connected = 0;
3145 hsotg->test_mode = 0;
3146
3147 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3148 if (hsotg->eps_in[ep])
3149 kill_all_requests(hsotg, hsotg->eps_in[ep],
3150 -ESHUTDOWN);
3151 if (hsotg->eps_out[ep])
3152 kill_all_requests(hsotg, hsotg->eps_out[ep],
3153 -ESHUTDOWN);
3154 }
3155
3156 call_gadget(hsotg, disconnect);
3157 hsotg->lx_state = DWC2_L3;
3158
3159 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3160}
3161
3162/**
3163 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3164 * @hsotg: The device state:
3165 * @periodic: True if this is a periodic FIFO interrupt
3166 */
3167static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3168{
3169 struct dwc2_hsotg_ep *ep;
3170 int epno, ret;
3171
3172 /* look through for any more data to transmit */
3173 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3174 ep = index_to_ep(hsotg, epno, 1);
3175
3176 if (!ep)
3177 continue;
3178
3179 if (!ep->dir_in)
3180 continue;
3181
3182 if ((periodic && !ep->periodic) ||
3183 (!periodic && ep->periodic))
3184 continue;
3185
3186 ret = dwc2_hsotg_trytx(hsotg, ep);
3187 if (ret < 0)
3188 break;
3189 }
3190}
3191
3192/* IRQ flags which will trigger a retry around the IRQ loop */
3193#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3194 GINTSTS_PTXFEMP | \
3195 GINTSTS_RXFLVL)
3196
3197/**
3198 * dwc2_hsotg_core_init - issue softreset to the core
3199 * @hsotg: The device state
3200 *
3201 * Issue a soft reset to the core, and await the core finishing it.
3202 */
3203void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3204 bool is_usb_reset)
3205{
3206 u32 intmsk;
3207 u32 val;
3208 u32 usbcfg;
3209 u32 dcfg = 0;
3210
3211 /* Kill any ep0 requests as controller will be reinitialized */
3212 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3213
3214 if (!is_usb_reset)
3215 if (dwc2_core_reset(hsotg, true))
3216 return;
3217
3218 /*
3219 * we must now enable ep0 ready for host detection and then
3220 * set configuration.
3221 */
3222
3223 /* keep other bits untouched (so e.g. forced modes are not lost) */
3224 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3225 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3226 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
3227
3228 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
3229 (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
3230 hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) {
3231 /* FS/LS Dedicated Transceiver Interface */
3232 usbcfg |= GUSBCFG_PHYSEL;
3233 } else {
3234 /* set the PLL on, remove the HNP/SRP and set the PHY */
3235 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3236 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3237 (val << GUSBCFG_USBTRDTIM_SHIFT);
3238 }
3239 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
3240
3241 dwc2_hsotg_init_fifo(hsotg);
3242
3243 if (!is_usb_reset)
3244 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON);
3245
3246 dcfg |= DCFG_EPMISCNT(1);
3247
3248 switch (hsotg->params.speed) {
3249 case DWC2_SPEED_PARAM_LOW:
3250 dcfg |= DCFG_DEVSPD_LS;
3251 break;
3252 case DWC2_SPEED_PARAM_FULL:
3253 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3254 dcfg |= DCFG_DEVSPD_FS48;
3255 else
3256 dcfg |= DCFG_DEVSPD_FS;
3257 break;
3258 default:
3259 dcfg |= DCFG_DEVSPD_HS;
3260 }
3261
3262 dwc2_writel(dcfg, hsotg->regs + DCFG);
3263
3264 /* Clear any pending OTG interrupts */
3265 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
3266
3267 /* Clear any pending interrupts */
3268 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
3269 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3270 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3271 GINTSTS_USBRST | GINTSTS_RESETDET |
3272 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3273 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3274 GINTSTS_LPMTRANRCVD;
3275
3276 if (!using_desc_dma(hsotg))
3277 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3278
3279 if (!hsotg->params.external_id_pin_ctl)
3280 intmsk |= GINTSTS_CONIDSTSCHNG;
3281
3282 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
3283
3284 if (using_dma(hsotg)) {
3285 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3286 hsotg->params.ahbcfg,
3287 hsotg->regs + GAHBCFG);
3288
3289 /* Set DDMA mode support in the core if needed */
3290 if (using_desc_dma(hsotg))
3291 dwc2_set_bit(hsotg->regs + DCFG, DCFG_DESCDMA_EN);
3292
3293 } else {
3294 dwc2_writel(((hsotg->dedicated_fifos) ?
3295 (GAHBCFG_NP_TXF_EMP_LVL |
3296 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3297 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
3298 }
3299
3300 /*
3301 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3302 * when we have no data to transfer. Otherwise we get being flooded by
3303 * interrupts.
3304 */
3305
3306 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3307 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3308 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3309 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3310 hsotg->regs + DIEPMSK);
3311
3312 /*
3313 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3314 * DMA mode we may need this and StsPhseRcvd.
3315 */
3316 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3317 DOEPMSK_STSPHSERCVDMSK) : 0) |
3318 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3319 DOEPMSK_SETUPMSK,
3320 hsotg->regs + DOEPMSK);
3321
3322 /* Enable BNA interrupt for DDMA */
3323 if (using_desc_dma(hsotg))
3324 dwc2_set_bit(hsotg->regs + DOEPMSK, DOEPMSK_BNAMSK);
3325
3326 dwc2_writel(0, hsotg->regs + DAINTMSK);
3327
3328 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3329 dwc2_readl(hsotg->regs + DIEPCTL0),
3330 dwc2_readl(hsotg->regs + DOEPCTL0));
3331
3332 /* enable in and out endpoint interrupts */
3333 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3334
3335 /*
3336 * Enable the RXFIFO when in slave mode, as this is how we collect
3337 * the data. In DMA mode, we get events from the FIFO but also
3338 * things we cannot process, so do not use it.
3339 */
3340 if (!using_dma(hsotg))
3341 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3342
3343 /* Enable interrupts for EP0 in and out */
3344 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3345 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3346
3347 if (!is_usb_reset) {
3348 dwc2_set_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
3349 udelay(10); /* see openiboot */
3350 dwc2_clear_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
3351 }
3352
3353 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
3354
3355 /*
3356 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3357 * writing to the EPCTL register..
3358 */
3359
3360 /* set to read 1 8byte packet */
3361 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3362 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
3363
3364 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3365 DXEPCTL_CNAK | DXEPCTL_EPENA |
3366 DXEPCTL_USBACTEP,
3367 hsotg->regs + DOEPCTL0);
3368
3369 /* enable, but don't activate EP0in */
3370 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3371 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
3372
3373 /* clear global NAKs */
3374 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3375 if (!is_usb_reset)
3376 val |= DCTL_SFTDISCON;
3377 dwc2_set_bit(hsotg->regs + DCTL, val);
3378
3379 /* configure the core to support LPM */
3380 dwc2_gadget_init_lpm(hsotg);
3381
3382 /* must be at-least 3ms to allow bus to see disconnect */
3383 mdelay(3);
3384
3385 hsotg->lx_state = DWC2_L0;
3386
3387 dwc2_hsotg_enqueue_setup(hsotg);
3388
3389 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3390 dwc2_readl(hsotg->regs + DIEPCTL0),
3391 dwc2_readl(hsotg->regs + DOEPCTL0));
3392}
3393
3394static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3395{
3396 /* set the soft-disconnect bit */
3397 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON);
3398}
3399
3400void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3401{
3402 /* remove the soft-disconnect and let's go */
3403 dwc2_clear_bit(hsotg->regs + DCTL, DCTL_SFTDISCON);
3404}
3405
3406/**
3407 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3408 * @hsotg: The device state:
3409 *
3410 * This interrupt indicates one of the following conditions occurred while
3411 * transmitting an ISOC transaction.
3412 * - Corrupted IN Token for ISOC EP.
3413 * - Packet not complete in FIFO.
3414 *
3415 * The following actions will be taken:
3416 * - Determine the EP
3417 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3418 */
3419static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3420{
3421 struct dwc2_hsotg_ep *hs_ep;
3422 u32 epctrl;
3423 u32 daintmsk;
3424 u32 idx;
3425
3426 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3427
3428 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3429
3430 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3431 hs_ep = hsotg->eps_in[idx];
3432 /* Proceed only unmasked ISOC EPs */
3433 if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk))
3434 continue;
3435
3436 epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx));
3437 if ((epctrl & DXEPCTL_EPENA) &&
3438 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3439 epctrl |= DXEPCTL_SNAK;
3440 epctrl |= DXEPCTL_EPDIS;
3441 dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx));
3442 }
3443 }
3444
3445 /* Clear interrupt */
3446 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS);
3447}
3448
3449/**
3450 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3451 * @hsotg: The device state:
3452 *
3453 * This interrupt indicates one of the following conditions occurred while
3454 * transmitting an ISOC transaction.
3455 * - Corrupted OUT Token for ISOC EP.
3456 * - Packet not complete in FIFO.
3457 *
3458 * The following actions will be taken:
3459 * - Determine the EP
3460 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3461 */
3462static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3463{
3464 u32 gintsts;
3465 u32 gintmsk;
3466 u32 daintmsk;
3467 u32 epctrl;
3468 struct dwc2_hsotg_ep *hs_ep;
3469 int idx;
3470
3471 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3472
3473 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3474 daintmsk >>= DAINT_OUTEP_SHIFT;
3475
3476 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3477 hs_ep = hsotg->eps_out[idx];
3478 /* Proceed only unmasked ISOC EPs */
3479 if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk))
3480 continue;
3481
3482 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
3483 if ((epctrl & DXEPCTL_EPENA) &&
3484 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3485 /* Unmask GOUTNAKEFF interrupt */
3486 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3487 gintmsk |= GINTSTS_GOUTNAKEFF;
3488 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3489
3490 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
3491 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3492 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK);
3493 break;
3494 }
3495 }
3496 }
3497
3498 /* Clear interrupt */
3499 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS);
3500}
3501
3502/**
3503 * dwc2_hsotg_irq - handle device interrupt
3504 * @irq: The IRQ number triggered
3505 * @pw: The pw value when registered the handler.
3506 */
3507static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3508{
3509 struct dwc2_hsotg *hsotg = pw;
3510 int retry_count = 8;
3511 u32 gintsts;
3512 u32 gintmsk;
3513
3514 if (!dwc2_is_device_mode(hsotg))
3515 return IRQ_NONE;
3516
3517 spin_lock(&hsotg->lock);
3518irq_retry:
3519 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
3520 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3521
3522 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3523 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3524
3525 gintsts &= gintmsk;
3526
3527 if (gintsts & GINTSTS_RESETDET) {
3528 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3529
3530 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
3531
3532 /* This event must be used only if controller is suspended */
3533 if (hsotg->lx_state == DWC2_L2) {
3534 dwc2_exit_partial_power_down(hsotg, true);
3535 hsotg->lx_state = DWC2_L0;
3536 }
3537 }
3538
3539 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3540 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
3541 u32 connected = hsotg->connected;
3542
3543 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3544 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3545 dwc2_readl(hsotg->regs + GNPTXSTS));
3546
3547 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
3548
3549 /* Report disconnection if it is not already done. */
3550 dwc2_hsotg_disconnect(hsotg);
3551
3552 /* Reset device address to zero */
3553 dwc2_clear_bit(hsotg->regs + DCFG, DCFG_DEVADDR_MASK);
3554
3555 if (usb_status & GOTGCTL_BSESVLD && connected)
3556 dwc2_hsotg_core_init_disconnected(hsotg, true);
3557 }
3558
3559 if (gintsts & GINTSTS_ENUMDONE) {
3560 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
3561
3562 dwc2_hsotg_irq_enumdone(hsotg);
3563 }
3564
3565 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3566 u32 daint = dwc2_readl(hsotg->regs + DAINT);
3567 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3568 u32 daint_out, daint_in;
3569 int ep;
3570
3571 daint &= daintmsk;
3572 daint_out = daint >> DAINT_OUTEP_SHIFT;
3573 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3574
3575 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3576
3577 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3578 ep++, daint_out >>= 1) {
3579 if (daint_out & 1)
3580 dwc2_hsotg_epint(hsotg, ep, 0);
3581 }
3582
3583 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3584 ep++, daint_in >>= 1) {
3585 if (daint_in & 1)
3586 dwc2_hsotg_epint(hsotg, ep, 1);
3587 }
3588 }
3589
3590 /* check both FIFOs */
3591
3592 if (gintsts & GINTSTS_NPTXFEMP) {
3593 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3594
3595 /*
3596 * Disable the interrupt to stop it happening again
3597 * unless one of these endpoint routines decides that
3598 * it needs re-enabling
3599 */
3600
3601 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3602 dwc2_hsotg_irq_fifoempty(hsotg, false);
3603 }
3604
3605 if (gintsts & GINTSTS_PTXFEMP) {
3606 dev_dbg(hsotg->dev, "PTxFEmp\n");
3607
3608 /* See note in GINTSTS_NPTxFEmp */
3609
3610 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3611 dwc2_hsotg_irq_fifoempty(hsotg, true);
3612 }
3613
3614 if (gintsts & GINTSTS_RXFLVL) {
3615 /*
3616 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3617 * we need to retry dwc2_hsotg_handle_rx if this is still
3618 * set.
3619 */
3620
3621 dwc2_hsotg_handle_rx(hsotg);
3622 }
3623
3624 if (gintsts & GINTSTS_ERLYSUSP) {
3625 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3626 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
3627 }
3628
3629 /*
3630 * these next two seem to crop-up occasionally causing the core
3631 * to shutdown the USB transfer, so try clearing them and logging
3632 * the occurrence.
3633 */
3634
3635 if (gintsts & GINTSTS_GOUTNAKEFF) {
3636 u8 idx;
3637 u32 epctrl;
3638 u32 gintmsk;
3639 u32 daintmsk;
3640 struct dwc2_hsotg_ep *hs_ep;
3641
3642 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3643 daintmsk >>= DAINT_OUTEP_SHIFT;
3644 /* Mask this interrupt */
3645 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3646 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3647 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3648
3649 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3650 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3651 hs_ep = hsotg->eps_out[idx];
3652 /* Proceed only unmasked ISOC EPs */
3653 if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk))
3654 continue;
3655
3656 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
3657
3658 if (epctrl & DXEPCTL_EPENA) {
3659 epctrl |= DXEPCTL_SNAK;
3660 epctrl |= DXEPCTL_EPDIS;
3661 dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx));
3662 }
3663 }
3664
3665 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3666 }
3667
3668 if (gintsts & GINTSTS_GINNAKEFF) {
3669 dev_info(hsotg->dev, "GINNakEff triggered\n");
3670
3671 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK);
3672
3673 dwc2_hsotg_dump(hsotg);
3674 }
3675
3676 if (gintsts & GINTSTS_INCOMPL_SOIN)
3677 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3678
3679 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3680 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3681
3682 /*
3683 * if we've had fifo events, we should try and go around the
3684 * loop again to see if there's any point in returning yet.
3685 */
3686
3687 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3688 goto irq_retry;
3689
3690 spin_unlock(&hsotg->lock);
3691
3692 return IRQ_HANDLED;
3693}
3694
3695static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3696 struct dwc2_hsotg_ep *hs_ep)
3697{
3698 u32 epctrl_reg;
3699 u32 epint_reg;
3700
3701 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3702 DOEPCTL(hs_ep->index);
3703 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3704 DOEPINT(hs_ep->index);
3705
3706 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3707 hs_ep->name);
3708
3709 if (hs_ep->dir_in) {
3710 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3711 dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
3712 /* Wait for Nak effect */
3713 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3714 DXEPINT_INEPNAKEFF, 100))
3715 dev_warn(hsotg->dev,
3716 "%s: timeout DIEPINT.NAKEFF\n",
3717 __func__);
3718 } else {
3719 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGNPINNAK);
3720 /* Wait for Nak effect */
3721 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3722 GINTSTS_GINNAKEFF, 100))
3723 dev_warn(hsotg->dev,
3724 "%s: timeout GINTSTS.GINNAKEFF\n",
3725 __func__);
3726 }
3727 } else {
3728 if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF))
3729 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK);
3730
3731 /* Wait for global nak to take effect */
3732 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3733 GINTSTS_GOUTNAKEFF, 100))
3734 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3735 __func__);
3736 }
3737
3738 /* Disable ep */
3739 dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3740
3741 /* Wait for ep to be disabled */
3742 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3743 dev_warn(hsotg->dev,
3744 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3745
3746 /* Clear EPDISBLD interrupt */
3747 dwc2_set_bit(hsotg->regs + epint_reg, DXEPINT_EPDISBLD);
3748
3749 if (hs_ep->dir_in) {
3750 unsigned short fifo_index;
3751
3752 if (hsotg->dedicated_fifos || hs_ep->periodic)
3753 fifo_index = hs_ep->fifo_index;
3754 else
3755 fifo_index = 0;
3756
3757 /* Flush TX FIFO */
3758 dwc2_flush_tx_fifo(hsotg, fifo_index);
3759
3760 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3761 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3762 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK);
3763
3764 } else {
3765 /* Remove global NAKs */
3766 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGOUTNAK);
3767 }
3768}
3769
3770/**
3771 * dwc2_hsotg_ep_enable - enable the given endpoint
3772 * @ep: The USB endpint to configure
3773 * @desc: The USB endpoint descriptor to configure with.
3774 *
3775 * This is called from the USB gadget code's usb_ep_enable().
3776 */
3777static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3778 const struct usb_endpoint_descriptor *desc)
3779{
3780 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3781 struct dwc2_hsotg *hsotg = hs_ep->parent;
3782 unsigned long flags;
3783 unsigned int index = hs_ep->index;
3784 u32 epctrl_reg;
3785 u32 epctrl;
3786 u32 mps;
3787 u32 mc;
3788 u32 mask;
3789 unsigned int dir_in;
3790 unsigned int i, val, size;
3791 int ret = 0;
3792
3793 dev_dbg(hsotg->dev,
3794 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3795 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
3796 desc->wMaxPacketSize, desc->bInterval);
3797
3798 /* not to be called for EP0 */
3799 if (index == 0) {
3800 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
3801 return -EINVAL;
3802 }
3803
3804 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
3805 if (dir_in != hs_ep->dir_in) {
3806 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
3807 return -EINVAL;
3808 }
3809
3810 mps = usb_endpoint_maxp(desc);
3811 mc = usb_endpoint_maxp_mult(desc);
3812
3813 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
3814
3815 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
3816 epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
3817
3818 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
3819 __func__, epctrl, epctrl_reg);
3820
3821 /* Allocate DMA descriptor chain for non-ctrl endpoints */
3822 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
3823 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
3824 MAX_DMA_DESC_NUM_GENERIC *
3825 sizeof(struct dwc2_dma_desc),
3826 &hs_ep->desc_list_dma, GFP_ATOMIC);
3827 if (!hs_ep->desc_list) {
3828 ret = -ENOMEM;
3829 goto error2;
3830 }
3831 }
3832
3833 spin_lock_irqsave(&hsotg->lock, flags);
3834
3835 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
3836 epctrl |= DXEPCTL_MPS(mps);
3837
3838 /*
3839 * mark the endpoint as active, otherwise the core may ignore
3840 * transactions entirely for this endpoint
3841 */
3842 epctrl |= DXEPCTL_USBACTEP;
3843
3844 /* update the endpoint state */
3845 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
3846
3847 /* default, set to non-periodic */
3848 hs_ep->isochronous = 0;
3849 hs_ep->periodic = 0;
3850 hs_ep->halted = 0;
3851 hs_ep->interval = desc->bInterval;
3852
3853 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
3854 case USB_ENDPOINT_XFER_ISOC:
3855 epctrl |= DXEPCTL_EPTYPE_ISO;
3856 epctrl |= DXEPCTL_SETEVENFR;
3857 hs_ep->isochronous = 1;
3858 hs_ep->interval = 1 << (desc->bInterval - 1);
3859 hs_ep->target_frame = TARGET_FRAME_INITIAL;
3860 hs_ep->isoc_chain_num = 0;
3861 hs_ep->next_desc = 0;
3862 if (dir_in) {
3863 hs_ep->periodic = 1;
3864 mask = dwc2_readl(hsotg->regs + DIEPMSK);
3865 mask |= DIEPMSK_NAKMSK;
3866 dwc2_writel(mask, hsotg->regs + DIEPMSK);
3867 } else {
3868 mask = dwc2_readl(hsotg->regs + DOEPMSK);
3869 mask |= DOEPMSK_OUTTKNEPDISMSK;
3870 dwc2_writel(mask, hsotg->regs + DOEPMSK);
3871 }
3872 break;
3873
3874 case USB_ENDPOINT_XFER_BULK:
3875 epctrl |= DXEPCTL_EPTYPE_BULK;
3876 break;
3877
3878 case USB_ENDPOINT_XFER_INT:
3879 if (dir_in)
3880 hs_ep->periodic = 1;
3881
3882 if (hsotg->gadget.speed == USB_SPEED_HIGH)
3883 hs_ep->interval = 1 << (desc->bInterval - 1);
3884
3885 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
3886 break;
3887
3888 case USB_ENDPOINT_XFER_CONTROL:
3889 epctrl |= DXEPCTL_EPTYPE_CONTROL;
3890 break;
3891 }
3892
3893 /*
3894 * if the hardware has dedicated fifos, we must give each IN EP
3895 * a unique tx-fifo even if it is non-periodic.
3896 */
3897 if (dir_in && hsotg->dedicated_fifos) {
3898 u32 fifo_index = 0;
3899 u32 fifo_size = UINT_MAX;
3900
3901 size = hs_ep->ep.maxpacket * hs_ep->mc;
3902 for (i = 1; i < hsotg->num_of_eps; ++i) {
3903 if (hsotg->fifo_map & (1 << i))
3904 continue;
3905 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
3906 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
3907 if (val < size)
3908 continue;
3909 /* Search for smallest acceptable fifo */
3910 if (val < fifo_size) {
3911 fifo_size = val;
3912 fifo_index = i;
3913 }
3914 }
3915 if (!fifo_index) {
3916 dev_err(hsotg->dev,
3917 "%s: No suitable fifo found\n", __func__);
3918 ret = -ENOMEM;
3919 goto error1;
3920 }
3921 hsotg->fifo_map |= 1 << fifo_index;
3922 epctrl |= DXEPCTL_TXFNUM(fifo_index);
3923 hs_ep->fifo_index = fifo_index;
3924 hs_ep->fifo_size = fifo_size;
3925 }
3926
3927 /* for non control endpoints, set PID to D0 */
3928 if (index && !hs_ep->isochronous)
3929 epctrl |= DXEPCTL_SETD0PID;
3930
3931 /* WA for Full speed ISOC IN in DDMA mode.
3932 * By Clear NAK status of EP, core will send ZLP
3933 * to IN token and assert NAK interrupt relying
3934 * on TxFIFO status only
3935 */
3936
3937 if (hsotg->gadget.speed == USB_SPEED_FULL &&
3938 hs_ep->isochronous && dir_in) {
3939 /* The WA applies only to core versions from 2.72a
3940 * to 4.00a (including both). Also for FS_IOT_1.00a
3941 * and HS_IOT_1.00a.
3942 */
3943 u32 gsnpsid = dwc2_readl(hsotg->regs + GSNPSID);
3944
3945 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
3946 gsnpsid <= DWC2_CORE_REV_4_00a) ||
3947 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
3948 gsnpsid == DWC2_HS_IOT_REV_1_00a)
3949 epctrl |= DXEPCTL_CNAK;
3950 }
3951
3952 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
3953 __func__, epctrl);
3954
3955 dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
3956 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
3957 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
3958
3959 /* enable the endpoint interrupt */
3960 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
3961
3962error1:
3963 spin_unlock_irqrestore(&hsotg->lock, flags);
3964
3965error2:
3966 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
3967 dmam_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC *
3968 sizeof(struct dwc2_dma_desc),
3969 hs_ep->desc_list, hs_ep->desc_list_dma);
3970 hs_ep->desc_list = NULL;
3971 }
3972
3973 return ret;
3974}
3975
3976/**
3977 * dwc2_hsotg_ep_disable - disable given endpoint
3978 * @ep: The endpoint to disable.
3979 */
3980static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
3981{
3982 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3983 struct dwc2_hsotg *hsotg = hs_ep->parent;
3984 int dir_in = hs_ep->dir_in;
3985 int index = hs_ep->index;
3986 unsigned long flags;
3987 u32 epctrl_reg;
3988 u32 ctrl;
3989
3990 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
3991
3992 if (ep == &hsotg->eps_out[0]->ep) {
3993 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
3994 return -EINVAL;
3995 }
3996
3997 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
3998 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
3999 return -EINVAL;
4000 }
4001
4002 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4003
4004 spin_lock_irqsave(&hsotg->lock, flags);
4005
4006 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
4007
4008 if (ctrl & DXEPCTL_EPENA)
4009 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4010
4011 ctrl &= ~DXEPCTL_EPENA;
4012 ctrl &= ~DXEPCTL_USBACTEP;
4013 ctrl |= DXEPCTL_SNAK;
4014
4015 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4016 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
4017
4018 /* disable endpoint interrupts */
4019 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4020
4021 /* terminate all requests with shutdown */
4022 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4023
4024 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4025 hs_ep->fifo_index = 0;
4026 hs_ep->fifo_size = 0;
4027
4028 spin_unlock_irqrestore(&hsotg->lock, flags);
4029 return 0;
4030}
4031
4032/**
4033 * on_list - check request is on the given endpoint
4034 * @ep: The endpoint to check.
4035 * @test: The request to test if it is on the endpoint.
4036 */
4037static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4038{
4039 struct dwc2_hsotg_req *req, *treq;
4040
4041 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4042 if (req == test)
4043 return true;
4044 }
4045
4046 return false;
4047}
4048
4049/**
4050 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4051 * @ep: The endpoint to dequeue.
4052 * @req: The request to be removed from a queue.
4053 */
4054static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4055{
4056 struct dwc2_hsotg_req *hs_req = our_req(req);
4057 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4058 struct dwc2_hsotg *hs = hs_ep->parent;
4059 unsigned long flags;
4060
4061 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4062
4063 spin_lock_irqsave(&hs->lock, flags);
4064
4065 if (!on_list(hs_ep, hs_req)) {
4066 spin_unlock_irqrestore(&hs->lock, flags);
4067 return -EINVAL;
4068 }
4069
4070 /* Dequeue already started request */
4071 if (req == &hs_ep->req->req)
4072 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4073
4074 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4075 spin_unlock_irqrestore(&hs->lock, flags);
4076
4077 return 0;
4078}
4079
4080/**
4081 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4082 * @ep: The endpoint to set halt.
4083 * @value: Set or unset the halt.
4084 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4085 * the endpoint is busy processing requests.
4086 *
4087 * We need to stall the endpoint immediately if request comes from set_feature
4088 * protocol command handler.
4089 */
4090static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4091{
4092 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4093 struct dwc2_hsotg *hs = hs_ep->parent;
4094 int index = hs_ep->index;
4095 u32 epreg;
4096 u32 epctl;
4097 u32 xfertype;
4098
4099 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4100
4101 if (index == 0) {
4102 if (value)
4103 dwc2_hsotg_stall_ep0(hs);
4104 else
4105 dev_warn(hs->dev,
4106 "%s: can't clear halt on ep0\n", __func__);
4107 return 0;
4108 }
4109
4110 if (hs_ep->isochronous) {
4111 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4112 return -EINVAL;
4113 }
4114
4115 if (!now && value && !list_empty(&hs_ep->queue)) {
4116 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4117 ep->name);
4118 return -EAGAIN;
4119 }
4120
4121 if (hs_ep->dir_in) {
4122 epreg = DIEPCTL(index);
4123 epctl = dwc2_readl(hs->regs + epreg);
4124
4125 if (value) {
4126 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4127 if (epctl & DXEPCTL_EPENA)
4128 epctl |= DXEPCTL_EPDIS;
4129 } else {
4130 epctl &= ~DXEPCTL_STALL;
4131 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4132 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4133 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4134 epctl |= DXEPCTL_SETD0PID;
4135 }
4136 dwc2_writel(epctl, hs->regs + epreg);
4137 } else {
4138 epreg = DOEPCTL(index);
4139 epctl = dwc2_readl(hs->regs + epreg);
4140
4141 if (value) {
4142 epctl |= DXEPCTL_STALL;
4143 } else {
4144 epctl &= ~DXEPCTL_STALL;
4145 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4146 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4147 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4148 epctl |= DXEPCTL_SETD0PID;
4149 }
4150 dwc2_writel(epctl, hs->regs + epreg);
4151 }
4152
4153 hs_ep->halted = value;
4154
4155 return 0;
4156}
4157
4158/**
4159 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4160 * @ep: The endpoint to set halt.
4161 * @value: Set or unset the halt.
4162 */
4163static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4164{
4165 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4166 struct dwc2_hsotg *hs = hs_ep->parent;
4167 unsigned long flags = 0;
4168 int ret = 0;
4169
4170 spin_lock_irqsave(&hs->lock, flags);
4171 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4172 spin_unlock_irqrestore(&hs->lock, flags);
4173
4174 return ret;
4175}
4176
4177static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4178 .enable = dwc2_hsotg_ep_enable,
4179 .disable = dwc2_hsotg_ep_disable,
4180 .alloc_request = dwc2_hsotg_ep_alloc_request,
4181 .free_request = dwc2_hsotg_ep_free_request,
4182 .queue = dwc2_hsotg_ep_queue_lock,
4183 .dequeue = dwc2_hsotg_ep_dequeue,
4184 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4185 /* note, don't believe we have any call for the fifo routines */
4186};
4187
4188/**
4189 * dwc2_hsotg_init - initialize the usb core
4190 * @hsotg: The driver state
4191 */
4192static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4193{
4194 u32 trdtim;
4195 u32 usbcfg;
4196 /* unmask subset of endpoint interrupts */
4197
4198 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4199 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4200 hsotg->regs + DIEPMSK);
4201
4202 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4203 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4204 hsotg->regs + DOEPMSK);
4205
4206 dwc2_writel(0, hsotg->regs + DAINTMSK);
4207
4208 /* Be in disconnected state until gadget is registered */
4209 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON);
4210
4211 /* setup fifos */
4212
4213 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4214 dwc2_readl(hsotg->regs + GRXFSIZ),
4215 dwc2_readl(hsotg->regs + GNPTXFSIZ));
4216
4217 dwc2_hsotg_init_fifo(hsotg);
4218
4219 /* keep other bits untouched (so e.g. forced modes are not lost) */
4220 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
4221 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
4222 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
4223
4224 /* set the PLL on, remove the HNP/SRP and set the PHY */
4225 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
4226 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
4227 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
4228 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
4229
4230 if (using_dma(hsotg))
4231 dwc2_set_bit(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
4232}
4233
4234/**
4235 * dwc2_hsotg_udc_start - prepare the udc for work
4236 * @gadget: The usb gadget state
4237 * @driver: The usb gadget driver
4238 *
4239 * Perform initialization to prepare udc device and driver
4240 * to work.
4241 */
4242static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4243 struct usb_gadget_driver *driver)
4244{
4245 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4246 unsigned long flags;
4247 int ret;
4248
4249 if (!hsotg) {
4250 pr_err("%s: called with no device\n", __func__);
4251 return -ENODEV;
4252 }
4253
4254 if (!driver) {
4255 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4256 return -EINVAL;
4257 }
4258
4259 if (driver->max_speed < USB_SPEED_FULL)
4260 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4261
4262 if (!driver->setup) {
4263 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4264 return -EINVAL;
4265 }
4266
4267 WARN_ON(hsotg->driver);
4268
4269 driver->driver.bus = NULL;
4270 hsotg->driver = driver;
4271 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4272 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4273
4274 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4275 ret = dwc2_lowlevel_hw_enable(hsotg);
4276 if (ret)
4277 goto err;
4278 }
4279
4280 if (!IS_ERR_OR_NULL(hsotg->uphy))
4281 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4282
4283 spin_lock_irqsave(&hsotg->lock, flags);
4284 if (dwc2_hw_is_device(hsotg)) {
4285 dwc2_hsotg_init(hsotg);
4286 dwc2_hsotg_core_init_disconnected(hsotg, false);
4287 }
4288
4289 hsotg->enabled = 0;
4290 spin_unlock_irqrestore(&hsotg->lock, flags);
4291
4292 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4293
4294 return 0;
4295
4296err:
4297 hsotg->driver = NULL;
4298 return ret;
4299}
4300
4301/**
4302 * dwc2_hsotg_udc_stop - stop the udc
4303 * @gadget: The usb gadget state
4304 * @driver: The usb gadget driver
4305 *
4306 * Stop udc hw block and stay tunned for future transmissions
4307 */
4308static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4309{
4310 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4311 unsigned long flags = 0;
4312 int ep;
4313
4314 if (!hsotg)
4315 return -ENODEV;
4316
4317 /* all endpoints should be shutdown */
4318 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4319 if (hsotg->eps_in[ep])
4320 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
4321 if (hsotg->eps_out[ep])
4322 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
4323 }
4324
4325 spin_lock_irqsave(&hsotg->lock, flags);
4326
4327 hsotg->driver = NULL;
4328 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4329 hsotg->enabled = 0;
4330
4331 spin_unlock_irqrestore(&hsotg->lock, flags);
4332
4333 if (!IS_ERR_OR_NULL(hsotg->uphy))
4334 otg_set_peripheral(hsotg->uphy->otg, NULL);
4335
4336 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4337 dwc2_lowlevel_hw_disable(hsotg);
4338
4339 return 0;
4340}
4341
4342/**
4343 * dwc2_hsotg_gadget_getframe - read the frame number
4344 * @gadget: The usb gadget state
4345 *
4346 * Read the {micro} frame number
4347 */
4348static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4349{
4350 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4351}
4352
4353/**
4354 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4355 * @gadget: The usb gadget state
4356 * @is_on: Current state of the USB PHY
4357 *
4358 * Connect/Disconnect the USB PHY pullup
4359 */
4360static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4361{
4362 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4363 unsigned long flags = 0;
4364
4365 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4366 hsotg->op_state);
4367
4368 /* Don't modify pullup state while in host mode */
4369 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4370 hsotg->enabled = is_on;
4371 return 0;
4372 }
4373
4374 spin_lock_irqsave(&hsotg->lock, flags);
4375 if (is_on) {
4376 hsotg->enabled = 1;
4377 dwc2_hsotg_core_init_disconnected(hsotg, false);
4378 /* Enable ACG feature in device mode,if supported */
4379 dwc2_enable_acg(hsotg);
4380 dwc2_hsotg_core_connect(hsotg);
4381 } else {
4382 dwc2_hsotg_core_disconnect(hsotg);
4383 dwc2_hsotg_disconnect(hsotg);
4384 hsotg->enabled = 0;
4385 }
4386
4387 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4388 spin_unlock_irqrestore(&hsotg->lock, flags);
4389
4390 return 0;
4391}
4392
4393static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4394{
4395 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4396 unsigned long flags;
4397
4398 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4399 spin_lock_irqsave(&hsotg->lock, flags);
4400
4401 /*
4402 * If controller is hibernated, it must exit from power_down
4403 * before being initialized / de-initialized
4404 */
4405 if (hsotg->lx_state == DWC2_L2)
4406 dwc2_exit_partial_power_down(hsotg, false);
4407
4408 if (is_active) {
4409 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4410
4411 dwc2_hsotg_core_init_disconnected(hsotg, false);
4412 if (hsotg->enabled) {
4413 /* Enable ACG feature in device mode,if supported */
4414 dwc2_enable_acg(hsotg);
4415 dwc2_hsotg_core_connect(hsotg);
4416 }
4417 } else {
4418 dwc2_hsotg_core_disconnect(hsotg);
4419 dwc2_hsotg_disconnect(hsotg);
4420 }
4421
4422 spin_unlock_irqrestore(&hsotg->lock, flags);
4423 return 0;
4424}
4425
4426/**
4427 * dwc2_hsotg_vbus_draw - report bMaxPower field
4428 * @gadget: The usb gadget state
4429 * @mA: Amount of current
4430 *
4431 * Report how much power the device may consume to the phy.
4432 */
4433static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4434{
4435 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4436
4437 if (IS_ERR_OR_NULL(hsotg->uphy))
4438 return -ENOTSUPP;
4439 return usb_phy_set_power(hsotg->uphy, mA);
4440}
4441
4442static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4443 .get_frame = dwc2_hsotg_gadget_getframe,
4444 .udc_start = dwc2_hsotg_udc_start,
4445 .udc_stop = dwc2_hsotg_udc_stop,
4446 .pullup = dwc2_hsotg_pullup,
4447 .vbus_session = dwc2_hsotg_vbus_session,
4448 .vbus_draw = dwc2_hsotg_vbus_draw,
4449};
4450
4451/**
4452 * dwc2_hsotg_initep - initialise a single endpoint
4453 * @hsotg: The device state.
4454 * @hs_ep: The endpoint to be initialised.
4455 * @epnum: The endpoint number
4456 *
4457 * Initialise the given endpoint (as part of the probe and device state
4458 * creation) to give to the gadget driver. Setup the endpoint name, any
4459 * direction information and other state that may be required.
4460 */
4461static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4462 struct dwc2_hsotg_ep *hs_ep,
4463 int epnum,
4464 bool dir_in)
4465{
4466 char *dir;
4467
4468 if (epnum == 0)
4469 dir = "";
4470 else if (dir_in)
4471 dir = "in";
4472 else
4473 dir = "out";
4474
4475 hs_ep->dir_in = dir_in;
4476 hs_ep->index = epnum;
4477
4478 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4479
4480 INIT_LIST_HEAD(&hs_ep->queue);
4481 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4482
4483 /* add to the list of endpoints known by the gadget driver */
4484 if (epnum)
4485 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4486
4487 hs_ep->parent = hsotg;
4488 hs_ep->ep.name = hs_ep->name;
4489
4490 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4491 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4492 else
4493 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4494 epnum ? 1024 : EP0_MPS_LIMIT);
4495 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4496
4497 if (epnum == 0) {
4498 hs_ep->ep.caps.type_control = true;
4499 } else {
4500 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4501 hs_ep->ep.caps.type_iso = true;
4502 hs_ep->ep.caps.type_bulk = true;
4503 }
4504 hs_ep->ep.caps.type_int = true;
4505 }
4506
4507 if (dir_in)
4508 hs_ep->ep.caps.dir_in = true;
4509 else
4510 hs_ep->ep.caps.dir_out = true;
4511
4512 /*
4513 * if we're using dma, we need to set the next-endpoint pointer
4514 * to be something valid.
4515 */
4516
4517 if (using_dma(hsotg)) {
4518 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4519
4520 if (dir_in)
4521 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
4522 else
4523 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
4524 }
4525}
4526
4527/**
4528 * dwc2_hsotg_hw_cfg - read HW configuration registers
4529 * @param: The device state
4530 *
4531 * Read the USB core HW configuration registers
4532 */
4533static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4534{
4535 u32 cfg;
4536 u32 ep_type;
4537 u32 i;
4538
4539 /* check hardware configuration */
4540
4541 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4542
4543 /* Add ep0 */
4544 hsotg->num_of_eps++;
4545
4546 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4547 sizeof(struct dwc2_hsotg_ep),
4548 GFP_KERNEL);
4549 if (!hsotg->eps_in[0])
4550 return -ENOMEM;
4551 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4552 hsotg->eps_out[0] = hsotg->eps_in[0];
4553
4554 cfg = hsotg->hw_params.dev_ep_dirs;
4555 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4556 ep_type = cfg & 3;
4557 /* Direction in or both */
4558 if (!(ep_type & 2)) {
4559 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4560 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4561 if (!hsotg->eps_in[i])
4562 return -ENOMEM;
4563 }
4564 /* Direction out or both */
4565 if (!(ep_type & 1)) {
4566 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4567 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4568 if (!hsotg->eps_out[i])
4569 return -ENOMEM;
4570 }
4571 }
4572
4573 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4574 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4575
4576 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4577 hsotg->num_of_eps,
4578 hsotg->dedicated_fifos ? "dedicated" : "shared",
4579 hsotg->fifo_mem);
4580 return 0;
4581}
4582
4583/**
4584 * dwc2_hsotg_dump - dump state of the udc
4585 * @param: The device state
4586 */
4587static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4588{
4589#ifdef DEBUG
4590 struct device *dev = hsotg->dev;
4591 void __iomem *regs = hsotg->regs;
4592 u32 val;
4593 int idx;
4594
4595 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4596 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
4597 dwc2_readl(regs + DIEPMSK));
4598
4599 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4600 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
4601
4602 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4603 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
4604
4605 /* show periodic fifo settings */
4606
4607 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4608 val = dwc2_readl(regs + DPTXFSIZN(idx));
4609 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4610 val >> FIFOSIZE_DEPTH_SHIFT,
4611 val & FIFOSIZE_STARTADDR_MASK);
4612 }
4613
4614 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4615 dev_info(dev,
4616 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4617 dwc2_readl(regs + DIEPCTL(idx)),
4618 dwc2_readl(regs + DIEPTSIZ(idx)),
4619 dwc2_readl(regs + DIEPDMA(idx)));
4620
4621 val = dwc2_readl(regs + DOEPCTL(idx));
4622 dev_info(dev,
4623 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4624 idx, dwc2_readl(regs + DOEPCTL(idx)),
4625 dwc2_readl(regs + DOEPTSIZ(idx)),
4626 dwc2_readl(regs + DOEPDMA(idx)));
4627 }
4628
4629 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4630 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
4631#endif
4632}
4633
4634/**
4635 * dwc2_gadget_init - init function for gadget
4636 * @dwc2: The data structure for the DWC2 driver.
4637 */
4638int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4639{
4640 struct device *dev = hsotg->dev;
4641 int epnum;
4642 int ret;
4643
4644 /* Dump fifo information */
4645 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4646 hsotg->params.g_np_tx_fifo_size);
4647 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4648
4649 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4650 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4651 hsotg->gadget.name = dev_name(dev);
4652 hsotg->remote_wakeup_allowed = 0;
4653
4654 if (hsotg->params.lpm)
4655 hsotg->gadget.lpm_capable = true;
4656
4657 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4658 hsotg->gadget.is_otg = 1;
4659 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4660 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4661
4662 ret = dwc2_hsotg_hw_cfg(hsotg);
4663 if (ret) {
4664 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4665 return ret;
4666 }
4667
4668 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4669 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4670 if (!hsotg->ctrl_buff)
4671 return -ENOMEM;
4672
4673 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4674 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4675 if (!hsotg->ep0_buff)
4676 return -ENOMEM;
4677
4678 if (using_desc_dma(hsotg)) {
4679 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4680 if (ret < 0)
4681 return ret;
4682 }
4683
4684 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
4685 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
4686 if (ret < 0) {
4687 dev_err(dev, "cannot claim IRQ for gadget\n");
4688 return ret;
4689 }
4690
4691 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4692
4693 if (hsotg->num_of_eps == 0) {
4694 dev_err(dev, "wrong number of EPs (zero)\n");
4695 return -EINVAL;
4696 }
4697
4698 /* setup endpoint information */
4699
4700 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4701 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4702
4703 /* allocate EP0 request */
4704
4705 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
4706 GFP_KERNEL);
4707 if (!hsotg->ctrl_req) {
4708 dev_err(dev, "failed to allocate ctrl req\n");
4709 return -ENOMEM;
4710 }
4711
4712 /* initialise the endpoints now the core has been initialised */
4713 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4714 if (hsotg->eps_in[epnum])
4715 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4716 epnum, 1);
4717 if (hsotg->eps_out[epnum])
4718 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
4719 epnum, 0);
4720 }
4721
4722 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
4723 if (ret)
4724 return ret;
4725
4726 dwc2_hsotg_dump(hsotg);
4727
4728 return 0;
4729}
4730
4731/**
4732 * dwc2_hsotg_remove - remove function for hsotg driver
4733 * @pdev: The platform information for the driver
4734 */
4735int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
4736{
4737 usb_del_gadget_udc(&hsotg->gadget);
4738
4739 return 0;
4740}
4741
4742int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
4743{
4744 unsigned long flags;
4745
4746 if (hsotg->lx_state != DWC2_L0)
4747 return 0;
4748
4749 if (hsotg->driver) {
4750 int ep;
4751
4752 dev_info(hsotg->dev, "suspending usb gadget %s\n",
4753 hsotg->driver->driver.name);
4754
4755 spin_lock_irqsave(&hsotg->lock, flags);
4756 if (hsotg->enabled)
4757 dwc2_hsotg_core_disconnect(hsotg);
4758 dwc2_hsotg_disconnect(hsotg);
4759 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4760 spin_unlock_irqrestore(&hsotg->lock, flags);
4761
4762 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
4763 if (hsotg->eps_in[ep])
4764 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
4765 if (hsotg->eps_out[ep])
4766 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
4767 }
4768 }
4769
4770 return 0;
4771}
4772
4773int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
4774{
4775 unsigned long flags;
4776
4777 if (hsotg->lx_state == DWC2_L2)
4778 return 0;
4779
4780 if (hsotg->driver) {
4781 dev_info(hsotg->dev, "resuming usb gadget %s\n",
4782 hsotg->driver->driver.name);
4783
4784 spin_lock_irqsave(&hsotg->lock, flags);
4785 dwc2_hsotg_core_init_disconnected(hsotg, false);
4786 if (hsotg->enabled) {
4787 /* Enable ACG feature in device mode,if supported */
4788 dwc2_enable_acg(hsotg);
4789 dwc2_hsotg_core_connect(hsotg);
4790 }
4791 spin_unlock_irqrestore(&hsotg->lock, flags);
4792 }
4793
4794 return 0;
4795}
4796
4797/**
4798 * dwc2_backup_device_registers() - Backup controller device registers.
4799 * When suspending usb bus, registers needs to be backuped
4800 * if controller power is disabled once suspended.
4801 *
4802 * @hsotg: Programming view of the DWC_otg controller
4803 */
4804int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
4805{
4806 struct dwc2_dregs_backup *dr;
4807 int i;
4808
4809 dev_dbg(hsotg->dev, "%s\n", __func__);
4810
4811 /* Backup dev regs */
4812 dr = &hsotg->dr_backup;
4813
4814 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
4815 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
4816 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
4817 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
4818 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
4819
4820 for (i = 0; i < hsotg->num_of_eps; i++) {
4821 /* Backup IN EPs */
4822 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
4823
4824 /* Ensure DATA PID is correctly configured */
4825 if (dr->diepctl[i] & DXEPCTL_DPID)
4826 dr->diepctl[i] |= DXEPCTL_SETD1PID;
4827 else
4828 dr->diepctl[i] |= DXEPCTL_SETD0PID;
4829
4830 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
4831 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
4832
4833 /* Backup OUT EPs */
4834 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
4835
4836 /* Ensure DATA PID is correctly configured */
4837 if (dr->doepctl[i] & DXEPCTL_DPID)
4838 dr->doepctl[i] |= DXEPCTL_SETD1PID;
4839 else
4840 dr->doepctl[i] |= DXEPCTL_SETD0PID;
4841
4842 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
4843 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
4844 dr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
4845 }
4846 dr->valid = true;
4847 return 0;
4848}
4849
4850/**
4851 * dwc2_restore_device_registers() - Restore controller device registers.
4852 * When resuming usb bus, device registers needs to be restored
4853 * if controller power were disabled.
4854 *
4855 * @hsotg: Programming view of the DWC_otg controller
4856 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
4857 *
4858 * Return: 0 if successful, negative error code otherwise
4859 */
4860int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
4861{
4862 struct dwc2_dregs_backup *dr;
4863 int i;
4864
4865 dev_dbg(hsotg->dev, "%s\n", __func__);
4866
4867 /* Restore dev regs */
4868 dr = &hsotg->dr_backup;
4869 if (!dr->valid) {
4870 dev_err(hsotg->dev, "%s: no device registers to restore\n",
4871 __func__);
4872 return -EINVAL;
4873 }
4874 dr->valid = false;
4875
4876 if (!remote_wakeup)
4877 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
4878
4879 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
4880 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
4881 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
4882
4883 for (i = 0; i < hsotg->num_of_eps; i++) {
4884 /* Restore IN EPs */
4885 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
4886 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
4887 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
4888 /** WA for enabled EPx's IN in DDMA mode. On entering to
4889 * hibernation wrong value read and saved from DIEPDMAx,
4890 * as result BNA interrupt asserted on hibernation exit
4891 * by restoring from saved area.
4892 */
4893 if (hsotg->params.g_dma_desc &&
4894 (dr->diepctl[i] & DXEPCTL_EPENA))
4895 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
4896 dwc2_writel(dr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i));
4897 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
4898 /* Restore OUT EPs */
4899 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
4900 /* WA for enabled EPx's OUT in DDMA mode. On entering to
4901 * hibernation wrong value read and saved from DOEPDMAx,
4902 * as result BNA interrupt asserted on hibernation exit
4903 * by restoring from saved area.
4904 */
4905 if (hsotg->params.g_dma_desc &&
4906 (dr->doepctl[i] & DXEPCTL_EPENA))
4907 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
4908 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
4909 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
4910 }
4911
4912 return 0;
4913}
4914
4915/**
4916 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
4917 *
4918 * @hsotg: Programming view of DWC_otg controller
4919 *
4920 */
4921void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
4922{
4923 u32 val;
4924
4925 if (!hsotg->params.lpm)
4926 return;
4927
4928 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
4929 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
4930 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
4931 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
4932 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
4933 dwc2_writel(val, hsotg->regs + GLPMCFG);
4934 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg->regs
4935 + GLPMCFG));
4936}
4937
4938/**
4939 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
4940 *
4941 * @hsotg: Programming view of the DWC_otg controller
4942 *
4943 * Return non-zero if failed to enter to hibernation.
4944 */
4945int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
4946{
4947 u32 gpwrdn;
4948 int ret = 0;
4949
4950 /* Change to L2(suspend) state */
4951 hsotg->lx_state = DWC2_L2;
4952 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
4953 ret = dwc2_backup_global_registers(hsotg);
4954 if (ret) {
4955 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
4956 __func__);
4957 return ret;
4958 }
4959 ret = dwc2_backup_device_registers(hsotg);
4960 if (ret) {
4961 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
4962 __func__);
4963 return ret;
4964 }
4965
4966 gpwrdn = GPWRDN_PWRDNRSTN;
4967 gpwrdn |= GPWRDN_PMUACTV;
4968 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
4969 udelay(10);
4970
4971 /* Set flag to indicate that we are in hibernation */
4972 hsotg->hibernated = 1;
4973
4974 /* Enable interrupts from wake up logic */
4975 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
4976 gpwrdn |= GPWRDN_PMUINTSEL;
4977 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
4978 udelay(10);
4979
4980 /* Unmask device mode interrupts in GPWRDN */
4981 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
4982 gpwrdn |= GPWRDN_RST_DET_MSK;
4983 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
4984 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
4985 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
4986 udelay(10);
4987
4988 /* Enable Power Down Clamp */
4989 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
4990 gpwrdn |= GPWRDN_PWRDNCLMP;
4991 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
4992 udelay(10);
4993
4994 /* Switch off VDD */
4995 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
4996 gpwrdn |= GPWRDN_PWRDNSWTCH;
4997 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
4998 udelay(10);
4999
5000 /* Save gpwrdn register for further usage if stschng interrupt */
5001 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5002 dev_dbg(hsotg->dev, "Hibernation completed\n");
5003
5004 return ret;
5005}
5006
5007/**
5008 * dwc2_gadget_exit_hibernation()
5009 * This function is for exiting from Device mode hibernation by host initiated
5010 * resume/reset and device initiated remote-wakeup.
5011 *
5012 * @hsotg: Programming view of the DWC_otg controller
5013 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5014 * @param reset: indicates whether resume is initiated by Reset.
5015 *
5016 * Return non-zero if failed to exit from hibernation.
5017 */
5018int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5019 int rem_wakeup, int reset)
5020{
5021 u32 pcgcctl;
5022 u32 gpwrdn;
5023 u32 dctl;
5024 int ret = 0;
5025 struct dwc2_gregs_backup *gr;
5026 struct dwc2_dregs_backup *dr;
5027
5028 gr = &hsotg->gr_backup;
5029 dr = &hsotg->dr_backup;
5030
5031 if (!hsotg->hibernated) {
5032 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5033 return 1;
5034 }
5035 dev_dbg(hsotg->dev,
5036 "%s: called with rem_wakeup = %d reset = %d\n",
5037 __func__, rem_wakeup, reset);
5038
5039 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5040
5041 if (!reset) {
5042 /* Clear all pending interupts */
5043 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
5044 }
5045
5046 /* De-assert Restore */
5047 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5048 gpwrdn &= ~GPWRDN_RESTORE;
5049 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5050 udelay(10);
5051
5052 if (!rem_wakeup) {
5053 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
5054 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5055 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
5056 }
5057
5058 /* Restore GUSBCFG, DCFG and DCTL */
5059 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
5060 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
5061 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
5062
5063 /* De-assert Wakeup Logic */
5064 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5065 gpwrdn &= ~GPWRDN_PMUACTV;
5066 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5067
5068 if (rem_wakeup) {
5069 udelay(10);
5070 /* Start Remote Wakeup Signaling */
5071 dwc2_writel(dr->dctl | DCTL_RMTWKUPSIG, hsotg->regs + DCTL);
5072 } else {
5073 udelay(50);
5074 /* Set Device programming done bit */
5075 dctl = dwc2_readl(hsotg->regs + DCTL);
5076 dctl |= DCTL_PWRONPRGDONE;
5077 dwc2_writel(dctl, hsotg->regs + DCTL);
5078 }
5079 /* Wait for interrupts which must be cleared */
5080 mdelay(2);
5081 /* Clear all pending interupts */
5082 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
5083
5084 /* Restore global registers */
5085 ret = dwc2_restore_global_registers(hsotg);
5086 if (ret) {
5087 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5088 __func__);
5089 return ret;
5090 }
5091
5092 /* Restore device registers */
5093 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5094 if (ret) {
5095 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5096 __func__);
5097 return ret;
5098 }
5099
5100 if (rem_wakeup) {
5101 mdelay(10);
5102 dctl = dwc2_readl(hsotg->regs + DCTL);
5103 dctl &= ~DCTL_RMTWKUPSIG;
5104 dwc2_writel(dctl, hsotg->regs + DCTL);
5105 }
5106
5107 hsotg->hibernated = 0;
5108 hsotg->lx_state = DWC2_L0;
5109 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
5110
5111 return ret;
5112}