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1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/pci.h>
24#include <linux/irq.h>
25#include <linux/log2.h>
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/slab.h>
29#include <linux/dmi.h>
30#include <linux/dma-mapping.h>
31
32#include "xhci.h"
33#include "xhci-trace.h"
34#include "xhci-mtk.h"
35
36#define DRIVER_AUTHOR "Sarah Sharp"
37#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
38
39#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
40
41/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
42static int link_quirk;
43module_param(link_quirk, int, S_IRUGO | S_IWUSR);
44MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
45
46static unsigned int quirks;
47module_param(quirks, uint, S_IRUGO);
48MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
49
50/* TODO: copied from ehci-hcd.c - can this be refactored? */
51/*
52 * xhci_handshake - spin reading hc until handshake completes or fails
53 * @ptr: address of hc register to be read
54 * @mask: bits to look at in result of read
55 * @done: value of those bits when handshake succeeds
56 * @usec: timeout in microseconds
57 *
58 * Returns negative errno, or zero on success
59 *
60 * Success happens when the "mask" bits have the specified value (hardware
61 * handshake done). There are two failure modes: "usec" have passed (major
62 * hardware flakeout), or the register reads as all-ones (hardware removed).
63 */
64int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
65{
66 u32 result;
67
68 do {
69 result = readl(ptr);
70 if (result == ~(u32)0) /* card removed */
71 return -ENODEV;
72 result &= mask;
73 if (result == done)
74 return 0;
75 udelay(1);
76 usec--;
77 } while (usec > 0);
78 return -ETIMEDOUT;
79}
80
81/*
82 * Disable interrupts and begin the xHCI halting process.
83 */
84void xhci_quiesce(struct xhci_hcd *xhci)
85{
86 u32 halted;
87 u32 cmd;
88 u32 mask;
89
90 mask = ~(XHCI_IRQS);
91 halted = readl(&xhci->op_regs->status) & STS_HALT;
92 if (!halted)
93 mask &= ~CMD_RUN;
94
95 cmd = readl(&xhci->op_regs->command);
96 cmd &= mask;
97 writel(cmd, &xhci->op_regs->command);
98}
99
100/*
101 * Force HC into halt state.
102 *
103 * Disable any IRQs and clear the run/stop bit.
104 * HC will complete any current and actively pipelined transactions, and
105 * should halt within 16 ms of the run/stop bit being cleared.
106 * Read HC Halted bit in the status register to see when the HC is finished.
107 */
108int xhci_halt(struct xhci_hcd *xhci)
109{
110 int ret;
111 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
112 xhci_quiesce(xhci);
113
114 ret = xhci_handshake(&xhci->op_regs->status,
115 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
116 if (!ret) {
117 xhci->xhc_state |= XHCI_STATE_HALTED;
118 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
119 } else
120 xhci_warn(xhci, "Host not halted after %u microseconds.\n",
121 XHCI_MAX_HALT_USEC);
122 return ret;
123}
124
125/*
126 * Set the run bit and wait for the host to be running.
127 */
128static int xhci_start(struct xhci_hcd *xhci)
129{
130 u32 temp;
131 int ret;
132
133 temp = readl(&xhci->op_regs->command);
134 temp |= (CMD_RUN);
135 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
136 temp);
137 writel(temp, &xhci->op_regs->command);
138
139 /*
140 * Wait for the HCHalted Status bit to be 0 to indicate the host is
141 * running.
142 */
143 ret = xhci_handshake(&xhci->op_regs->status,
144 STS_HALT, 0, XHCI_MAX_HALT_USEC);
145 if (ret == -ETIMEDOUT)
146 xhci_err(xhci, "Host took too long to start, "
147 "waited %u microseconds.\n",
148 XHCI_MAX_HALT_USEC);
149 if (!ret)
150 /* clear state flags. Including dying, halted or removing */
151 xhci->xhc_state = 0;
152
153 return ret;
154}
155
156/*
157 * Reset a halted HC.
158 *
159 * This resets pipelines, timers, counters, state machines, etc.
160 * Transactions will be terminated immediately, and operational registers
161 * will be set to their defaults.
162 */
163int xhci_reset(struct xhci_hcd *xhci)
164{
165 u32 command;
166 u32 state;
167 int ret, i;
168
169 state = readl(&xhci->op_regs->status);
170 if ((state & STS_HALT) == 0) {
171 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
172 return 0;
173 }
174
175 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
176 command = readl(&xhci->op_regs->command);
177 command |= CMD_RESET;
178 writel(command, &xhci->op_regs->command);
179
180 /* Existing Intel xHCI controllers require a delay of 1 mS,
181 * after setting the CMD_RESET bit, and before accessing any
182 * HC registers. This allows the HC to complete the
183 * reset operation and be ready for HC register access.
184 * Without this delay, the subsequent HC register access,
185 * may result in a system hang very rarely.
186 */
187 if (xhci->quirks & XHCI_INTEL_HOST)
188 udelay(1000);
189
190 ret = xhci_handshake(&xhci->op_regs->command,
191 CMD_RESET, 0, 10 * 1000 * 1000);
192 if (ret)
193 return ret;
194
195 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
196 "Wait for controller to be ready for doorbell rings");
197 /*
198 * xHCI cannot write to any doorbells or operational registers other
199 * than status until the "Controller Not Ready" flag is cleared.
200 */
201 ret = xhci_handshake(&xhci->op_regs->status,
202 STS_CNR, 0, 10 * 1000 * 1000);
203
204 for (i = 0; i < 2; ++i) {
205 xhci->bus_state[i].port_c_suspend = 0;
206 xhci->bus_state[i].suspended_ports = 0;
207 xhci->bus_state[i].resuming_ports = 0;
208 }
209
210 return ret;
211}
212
213#ifdef CONFIG_PCI
214static int xhci_free_msi(struct xhci_hcd *xhci)
215{
216 int i;
217
218 if (!xhci->msix_entries)
219 return -EINVAL;
220
221 for (i = 0; i < xhci->msix_count; i++)
222 if (xhci->msix_entries[i].vector)
223 free_irq(xhci->msix_entries[i].vector,
224 xhci_to_hcd(xhci));
225 return 0;
226}
227
228/*
229 * Set up MSI
230 */
231static int xhci_setup_msi(struct xhci_hcd *xhci)
232{
233 int ret;
234 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
235
236 ret = pci_enable_msi(pdev);
237 if (ret) {
238 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
239 "failed to allocate MSI entry");
240 return ret;
241 }
242
243 ret = request_irq(pdev->irq, xhci_msi_irq,
244 0, "xhci_hcd", xhci_to_hcd(xhci));
245 if (ret) {
246 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
247 "disable MSI interrupt");
248 pci_disable_msi(pdev);
249 }
250
251 return ret;
252}
253
254/*
255 * Free IRQs
256 * free all IRQs request
257 */
258static void xhci_free_irq(struct xhci_hcd *xhci)
259{
260 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
261 int ret;
262
263 /* return if using legacy interrupt */
264 if (xhci_to_hcd(xhci)->irq > 0)
265 return;
266
267 ret = xhci_free_msi(xhci);
268 if (!ret)
269 return;
270 if (pdev->irq > 0)
271 free_irq(pdev->irq, xhci_to_hcd(xhci));
272
273 return;
274}
275
276/*
277 * Set up MSI-X
278 */
279static int xhci_setup_msix(struct xhci_hcd *xhci)
280{
281 int i, ret = 0;
282 struct usb_hcd *hcd = xhci_to_hcd(xhci);
283 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
284
285 /*
286 * calculate number of msi-x vectors supported.
287 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
288 * with max number of interrupters based on the xhci HCSPARAMS1.
289 * - num_online_cpus: maximum msi-x vectors per CPUs core.
290 * Add additional 1 vector to ensure always available interrupt.
291 */
292 xhci->msix_count = min(num_online_cpus() + 1,
293 HCS_MAX_INTRS(xhci->hcs_params1));
294
295 xhci->msix_entries =
296 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
297 GFP_KERNEL);
298 if (!xhci->msix_entries) {
299 xhci_err(xhci, "Failed to allocate MSI-X entries\n");
300 return -ENOMEM;
301 }
302
303 for (i = 0; i < xhci->msix_count; i++) {
304 xhci->msix_entries[i].entry = i;
305 xhci->msix_entries[i].vector = 0;
306 }
307
308 ret = pci_enable_msix_exact(pdev, xhci->msix_entries, xhci->msix_count);
309 if (ret) {
310 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
311 "Failed to enable MSI-X");
312 goto free_entries;
313 }
314
315 for (i = 0; i < xhci->msix_count; i++) {
316 ret = request_irq(xhci->msix_entries[i].vector,
317 xhci_msi_irq,
318 0, "xhci_hcd", xhci_to_hcd(xhci));
319 if (ret)
320 goto disable_msix;
321 }
322
323 hcd->msix_enabled = 1;
324 return ret;
325
326disable_msix:
327 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
328 xhci_free_irq(xhci);
329 pci_disable_msix(pdev);
330free_entries:
331 kfree(xhci->msix_entries);
332 xhci->msix_entries = NULL;
333 return ret;
334}
335
336/* Free any IRQs and disable MSI-X */
337static void xhci_cleanup_msix(struct xhci_hcd *xhci)
338{
339 struct usb_hcd *hcd = xhci_to_hcd(xhci);
340 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
341
342 if (xhci->quirks & XHCI_PLAT)
343 return;
344
345 xhci_free_irq(xhci);
346
347 if (xhci->msix_entries) {
348 pci_disable_msix(pdev);
349 kfree(xhci->msix_entries);
350 xhci->msix_entries = NULL;
351 } else {
352 pci_disable_msi(pdev);
353 }
354
355 hcd->msix_enabled = 0;
356 return;
357}
358
359static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
360{
361 int i;
362
363 if (xhci->msix_entries) {
364 for (i = 0; i < xhci->msix_count; i++)
365 synchronize_irq(xhci->msix_entries[i].vector);
366 }
367}
368
369static int xhci_try_enable_msi(struct usb_hcd *hcd)
370{
371 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
372 struct pci_dev *pdev;
373 int ret;
374
375 /* The xhci platform device has set up IRQs through usb_add_hcd. */
376 if (xhci->quirks & XHCI_PLAT)
377 return 0;
378
379 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
380 /*
381 * Some Fresco Logic host controllers advertise MSI, but fail to
382 * generate interrupts. Don't even try to enable MSI.
383 */
384 if (xhci->quirks & XHCI_BROKEN_MSI)
385 goto legacy_irq;
386
387 /* unregister the legacy interrupt */
388 if (hcd->irq)
389 free_irq(hcd->irq, hcd);
390 hcd->irq = 0;
391
392 ret = xhci_setup_msix(xhci);
393 if (ret)
394 /* fall back to msi*/
395 ret = xhci_setup_msi(xhci);
396
397 if (!ret)
398 /* hcd->irq is 0, we have MSI */
399 return 0;
400
401 if (!pdev->irq) {
402 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
403 return -EINVAL;
404 }
405
406 legacy_irq:
407 if (!strlen(hcd->irq_descr))
408 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
409 hcd->driver->description, hcd->self.busnum);
410
411 /* fall back to legacy interrupt*/
412 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
413 hcd->irq_descr, hcd);
414 if (ret) {
415 xhci_err(xhci, "request interrupt %d failed\n",
416 pdev->irq);
417 return ret;
418 }
419 hcd->irq = pdev->irq;
420 return 0;
421}
422
423#else
424
425static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
426{
427 return 0;
428}
429
430static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
431{
432}
433
434static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
435{
436}
437
438#endif
439
440static void compliance_mode_recovery(unsigned long arg)
441{
442 struct xhci_hcd *xhci;
443 struct usb_hcd *hcd;
444 u32 temp;
445 int i;
446
447 xhci = (struct xhci_hcd *)arg;
448
449 for (i = 0; i < xhci->num_usb3_ports; i++) {
450 temp = readl(xhci->usb3_ports[i]);
451 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
452 /*
453 * Compliance Mode Detected. Letting USB Core
454 * handle the Warm Reset
455 */
456 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
457 "Compliance mode detected->port %d",
458 i + 1);
459 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
460 "Attempting compliance mode recovery");
461 hcd = xhci->shared_hcd;
462
463 if (hcd->state == HC_STATE_SUSPENDED)
464 usb_hcd_resume_root_hub(hcd);
465
466 usb_hcd_poll_rh_status(hcd);
467 }
468 }
469
470 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
471 mod_timer(&xhci->comp_mode_recovery_timer,
472 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
473}
474
475/*
476 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
477 * that causes ports behind that hardware to enter compliance mode sometimes.
478 * The quirk creates a timer that polls every 2 seconds the link state of
479 * each host controller's port and recovers it by issuing a Warm reset
480 * if Compliance mode is detected, otherwise the port will become "dead" (no
481 * device connections or disconnections will be detected anymore). Becasue no
482 * status event is generated when entering compliance mode (per xhci spec),
483 * this quirk is needed on systems that have the failing hardware installed.
484 */
485static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
486{
487 xhci->port_status_u0 = 0;
488 setup_timer(&xhci->comp_mode_recovery_timer,
489 compliance_mode_recovery, (unsigned long)xhci);
490 xhci->comp_mode_recovery_timer.expires = jiffies +
491 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
492
493 set_timer_slack(&xhci->comp_mode_recovery_timer,
494 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
495 add_timer(&xhci->comp_mode_recovery_timer);
496 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
497 "Compliance mode recovery timer initialized");
498}
499
500/*
501 * This function identifies the systems that have installed the SN65LVPE502CP
502 * USB3.0 re-driver and that need the Compliance Mode Quirk.
503 * Systems:
504 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
505 */
506static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
507{
508 const char *dmi_product_name, *dmi_sys_vendor;
509
510 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
511 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
512 if (!dmi_product_name || !dmi_sys_vendor)
513 return false;
514
515 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
516 return false;
517
518 if (strstr(dmi_product_name, "Z420") ||
519 strstr(dmi_product_name, "Z620") ||
520 strstr(dmi_product_name, "Z820") ||
521 strstr(dmi_product_name, "Z1 Workstation"))
522 return true;
523
524 return false;
525}
526
527static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
528{
529 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
530}
531
532
533/*
534 * Initialize memory for HCD and xHC (one-time init).
535 *
536 * Program the PAGESIZE register, initialize the device context array, create
537 * device contexts (?), set up a command ring segment (or two?), create event
538 * ring (one for now).
539 */
540int xhci_init(struct usb_hcd *hcd)
541{
542 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
543 int retval = 0;
544
545 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
546 spin_lock_init(&xhci->lock);
547 if (xhci->hci_version == 0x95 && link_quirk) {
548 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
549 "QUIRK: Not clearing Link TRB chain bits.");
550 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
551 } else {
552 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
553 "xHCI doesn't need link TRB QUIRK");
554 }
555 retval = xhci_mem_init(xhci, GFP_KERNEL);
556 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
557
558 /* Initializing Compliance Mode Recovery Data If Needed */
559 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
560 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
561 compliance_mode_recovery_timer_init(xhci);
562 }
563
564 return retval;
565}
566
567/*-------------------------------------------------------------------------*/
568
569
570static int xhci_run_finished(struct xhci_hcd *xhci)
571{
572 if (xhci_start(xhci)) {
573 xhci_halt(xhci);
574 return -ENODEV;
575 }
576 xhci->shared_hcd->state = HC_STATE_RUNNING;
577 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
578
579 if (xhci->quirks & XHCI_NEC_HOST)
580 xhci_ring_cmd_db(xhci);
581
582 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
583 "Finished xhci_run for USB3 roothub");
584 return 0;
585}
586
587/*
588 * Start the HC after it was halted.
589 *
590 * This function is called by the USB core when the HC driver is added.
591 * Its opposite is xhci_stop().
592 *
593 * xhci_init() must be called once before this function can be called.
594 * Reset the HC, enable device slot contexts, program DCBAAP, and
595 * set command ring pointer and event ring pointer.
596 *
597 * Setup MSI-X vectors and enable interrupts.
598 */
599int xhci_run(struct usb_hcd *hcd)
600{
601 u32 temp;
602 u64 temp_64;
603 int ret;
604 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
605
606 /* Start the xHCI host controller running only after the USB 2.0 roothub
607 * is setup.
608 */
609
610 hcd->uses_new_polling = 1;
611 if (!usb_hcd_is_primary_hcd(hcd))
612 return xhci_run_finished(xhci);
613
614 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
615
616 ret = xhci_try_enable_msi(hcd);
617 if (ret)
618 return ret;
619
620 xhci_dbg(xhci, "Command ring memory map follows:\n");
621 xhci_debug_ring(xhci, xhci->cmd_ring);
622 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
623 xhci_dbg_cmd_ptrs(xhci);
624
625 xhci_dbg(xhci, "ERST memory map follows:\n");
626 xhci_dbg_erst(xhci, &xhci->erst);
627 xhci_dbg(xhci, "Event ring:\n");
628 xhci_debug_ring(xhci, xhci->event_ring);
629 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
630 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
631 temp_64 &= ~ERST_PTR_MASK;
632 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
633 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
634
635 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
636 "// Set the interrupt modulation register");
637 temp = readl(&xhci->ir_set->irq_control);
638 temp &= ~ER_IRQ_INTERVAL_MASK;
639 /*
640 * the increment interval is 8 times as much as that defined
641 * in xHCI spec on MTK's controller
642 */
643 temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
644 writel(temp, &xhci->ir_set->irq_control);
645
646 /* Set the HCD state before we enable the irqs */
647 temp = readl(&xhci->op_regs->command);
648 temp |= (CMD_EIE);
649 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
650 "// Enable interrupts, cmd = 0x%x.", temp);
651 writel(temp, &xhci->op_regs->command);
652
653 temp = readl(&xhci->ir_set->irq_pending);
654 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
655 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
656 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
657 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
658 xhci_print_ir_set(xhci, 0);
659
660 if (xhci->quirks & XHCI_NEC_HOST) {
661 struct xhci_command *command;
662 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
663 if (!command)
664 return -ENOMEM;
665 xhci_queue_vendor_command(xhci, command, 0, 0, 0,
666 TRB_TYPE(TRB_NEC_GET_FW));
667 }
668 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
669 "Finished xhci_run for USB2 roothub");
670 return 0;
671}
672EXPORT_SYMBOL_GPL(xhci_run);
673
674/*
675 * Stop xHCI driver.
676 *
677 * This function is called by the USB core when the HC driver is removed.
678 * Its opposite is xhci_run().
679 *
680 * Disable device contexts, disable IRQs, and quiesce the HC.
681 * Reset the HC, finish any completed transactions, and cleanup memory.
682 */
683void xhci_stop(struct usb_hcd *hcd)
684{
685 u32 temp;
686 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
687
688 if (xhci->xhc_state & XHCI_STATE_HALTED)
689 return;
690
691 mutex_lock(&xhci->mutex);
692 spin_lock_irq(&xhci->lock);
693 xhci->xhc_state |= XHCI_STATE_HALTED;
694 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
695
696 /* Make sure the xHC is halted for a USB3 roothub
697 * (xhci_stop() could be called as part of failed init).
698 */
699 xhci_halt(xhci);
700 xhci_reset(xhci);
701 spin_unlock_irq(&xhci->lock);
702
703 xhci_cleanup_msix(xhci);
704
705 /* Deleting Compliance Mode Recovery Timer */
706 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
707 (!(xhci_all_ports_seen_u0(xhci)))) {
708 del_timer_sync(&xhci->comp_mode_recovery_timer);
709 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
710 "%s: compliance mode recovery timer deleted",
711 __func__);
712 }
713
714 if (xhci->quirks & XHCI_AMD_PLL_FIX)
715 usb_amd_dev_put();
716
717 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
718 "// Disabling event ring interrupts");
719 temp = readl(&xhci->op_regs->status);
720 writel(temp & ~STS_EINT, &xhci->op_regs->status);
721 temp = readl(&xhci->ir_set->irq_pending);
722 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
723 xhci_print_ir_set(xhci, 0);
724
725 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
726 xhci_mem_cleanup(xhci);
727 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
728 "xhci_stop completed - status = %x",
729 readl(&xhci->op_regs->status));
730 mutex_unlock(&xhci->mutex);
731}
732
733/*
734 * Shutdown HC (not bus-specific)
735 *
736 * This is called when the machine is rebooting or halting. We assume that the
737 * machine will be powered off, and the HC's internal state will be reset.
738 * Don't bother to free memory.
739 *
740 * This will only ever be called with the main usb_hcd (the USB3 roothub).
741 */
742void xhci_shutdown(struct usb_hcd *hcd)
743{
744 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
745
746 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
747 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
748
749 spin_lock_irq(&xhci->lock);
750 xhci_halt(xhci);
751 /* Workaround for spurious wakeups at shutdown with HSW */
752 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
753 xhci_reset(xhci);
754 spin_unlock_irq(&xhci->lock);
755
756 xhci_cleanup_msix(xhci);
757
758 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
759 "xhci_shutdown completed - status = %x",
760 readl(&xhci->op_regs->status));
761
762 /* Yet another workaround for spurious wakeups at shutdown with HSW */
763 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
764 pci_set_power_state(to_pci_dev(hcd->self.controller), PCI_D3hot);
765}
766
767#ifdef CONFIG_PM
768static void xhci_save_registers(struct xhci_hcd *xhci)
769{
770 xhci->s3.command = readl(&xhci->op_regs->command);
771 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
772 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
773 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
774 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
775 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
776 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
777 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
778 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
779}
780
781static void xhci_restore_registers(struct xhci_hcd *xhci)
782{
783 writel(xhci->s3.command, &xhci->op_regs->command);
784 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
785 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
786 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
787 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
788 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
789 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
790 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
791 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
792}
793
794static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
795{
796 u64 val_64;
797
798 /* step 2: initialize command ring buffer */
799 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
800 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
801 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
802 xhci->cmd_ring->dequeue) &
803 (u64) ~CMD_RING_RSVD_BITS) |
804 xhci->cmd_ring->cycle_state;
805 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
806 "// Setting command ring address to 0x%llx",
807 (long unsigned long) val_64);
808 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
809}
810
811/*
812 * The whole command ring must be cleared to zero when we suspend the host.
813 *
814 * The host doesn't save the command ring pointer in the suspend well, so we
815 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
816 * aligned, because of the reserved bits in the command ring dequeue pointer
817 * register. Therefore, we can't just set the dequeue pointer back in the
818 * middle of the ring (TRBs are 16-byte aligned).
819 */
820static void xhci_clear_command_ring(struct xhci_hcd *xhci)
821{
822 struct xhci_ring *ring;
823 struct xhci_segment *seg;
824
825 ring = xhci->cmd_ring;
826 seg = ring->deq_seg;
827 do {
828 memset(seg->trbs, 0,
829 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
830 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
831 cpu_to_le32(~TRB_CYCLE);
832 seg = seg->next;
833 } while (seg != ring->deq_seg);
834
835 /* Reset the software enqueue and dequeue pointers */
836 ring->deq_seg = ring->first_seg;
837 ring->dequeue = ring->first_seg->trbs;
838 ring->enq_seg = ring->deq_seg;
839 ring->enqueue = ring->dequeue;
840
841 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
842 /*
843 * Ring is now zeroed, so the HW should look for change of ownership
844 * when the cycle bit is set to 1.
845 */
846 ring->cycle_state = 1;
847
848 /*
849 * Reset the hardware dequeue pointer.
850 * Yes, this will need to be re-written after resume, but we're paranoid
851 * and want to make sure the hardware doesn't access bogus memory
852 * because, say, the BIOS or an SMI started the host without changing
853 * the command ring pointers.
854 */
855 xhci_set_cmd_ring_deq(xhci);
856}
857
858static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
859{
860 int port_index;
861 __le32 __iomem **port_array;
862 unsigned long flags;
863 u32 t1, t2;
864
865 spin_lock_irqsave(&xhci->lock, flags);
866
867 /* disble usb3 ports Wake bits*/
868 port_index = xhci->num_usb3_ports;
869 port_array = xhci->usb3_ports;
870 while (port_index--) {
871 t1 = readl(port_array[port_index]);
872 t1 = xhci_port_state_to_neutral(t1);
873 t2 = t1 & ~PORT_WAKE_BITS;
874 if (t1 != t2)
875 writel(t2, port_array[port_index]);
876 }
877
878 /* disble usb2 ports Wake bits*/
879 port_index = xhci->num_usb2_ports;
880 port_array = xhci->usb2_ports;
881 while (port_index--) {
882 t1 = readl(port_array[port_index]);
883 t1 = xhci_port_state_to_neutral(t1);
884 t2 = t1 & ~PORT_WAKE_BITS;
885 if (t1 != t2)
886 writel(t2, port_array[port_index]);
887 }
888
889 spin_unlock_irqrestore(&xhci->lock, flags);
890}
891
892/*
893 * Stop HC (not bus-specific)
894 *
895 * This is called when the machine transition into S3/S4 mode.
896 *
897 */
898int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
899{
900 int rc = 0;
901 unsigned int delay = XHCI_MAX_HALT_USEC;
902 struct usb_hcd *hcd = xhci_to_hcd(xhci);
903 u32 command;
904
905 if (!hcd->state)
906 return 0;
907
908 if (hcd->state != HC_STATE_SUSPENDED ||
909 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
910 return -EINVAL;
911
912 /* Clear root port wake on bits if wakeup not allowed. */
913 if (!do_wakeup)
914 xhci_disable_port_wake_on_bits(xhci);
915
916 /* Don't poll the roothubs on bus suspend. */
917 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
918 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
919 del_timer_sync(&hcd->rh_timer);
920 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
921 del_timer_sync(&xhci->shared_hcd->rh_timer);
922
923 spin_lock_irq(&xhci->lock);
924 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
925 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
926 /* step 1: stop endpoint */
927 /* skipped assuming that port suspend has done */
928
929 /* step 2: clear Run/Stop bit */
930 command = readl(&xhci->op_regs->command);
931 command &= ~CMD_RUN;
932 writel(command, &xhci->op_regs->command);
933
934 /* Some chips from Fresco Logic need an extraordinary delay */
935 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
936
937 if (xhci_handshake(&xhci->op_regs->status,
938 STS_HALT, STS_HALT, delay)) {
939 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
940 spin_unlock_irq(&xhci->lock);
941 return -ETIMEDOUT;
942 }
943 xhci_clear_command_ring(xhci);
944
945 /* step 3: save registers */
946 xhci_save_registers(xhci);
947
948 /* step 4: set CSS flag */
949 command = readl(&xhci->op_regs->command);
950 command |= CMD_CSS;
951 writel(command, &xhci->op_regs->command);
952 if (xhci_handshake(&xhci->op_regs->status,
953 STS_SAVE, 0, 10 * 1000)) {
954 xhci_warn(xhci, "WARN: xHC save state timeout\n");
955 spin_unlock_irq(&xhci->lock);
956 return -ETIMEDOUT;
957 }
958 spin_unlock_irq(&xhci->lock);
959
960 /*
961 * Deleting Compliance Mode Recovery Timer because the xHCI Host
962 * is about to be suspended.
963 */
964 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
965 (!(xhci_all_ports_seen_u0(xhci)))) {
966 del_timer_sync(&xhci->comp_mode_recovery_timer);
967 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
968 "%s: compliance mode recovery timer deleted",
969 __func__);
970 }
971
972 /* step 5: remove core well power */
973 /* synchronize irq when using MSI-X */
974 xhci_msix_sync_irqs(xhci);
975
976 return rc;
977}
978EXPORT_SYMBOL_GPL(xhci_suspend);
979
980/*
981 * start xHC (not bus-specific)
982 *
983 * This is called when the machine transition from S3/S4 mode.
984 *
985 */
986int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
987{
988 u32 command, temp = 0, status;
989 struct usb_hcd *hcd = xhci_to_hcd(xhci);
990 struct usb_hcd *secondary_hcd;
991 int retval = 0;
992 bool comp_timer_running = false;
993
994 if (!hcd->state)
995 return 0;
996
997 /* Wait a bit if either of the roothubs need to settle from the
998 * transition into bus suspend.
999 */
1000 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
1001 time_before(jiffies,
1002 xhci->bus_state[1].next_statechange))
1003 msleep(100);
1004
1005 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1006 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1007
1008 spin_lock_irq(&xhci->lock);
1009 if (xhci->quirks & XHCI_RESET_ON_RESUME)
1010 hibernated = true;
1011
1012 if (!hibernated) {
1013 /* step 1: restore register */
1014 xhci_restore_registers(xhci);
1015 /* step 2: initialize command ring buffer */
1016 xhci_set_cmd_ring_deq(xhci);
1017 /* step 3: restore state and start state*/
1018 /* step 3: set CRS flag */
1019 command = readl(&xhci->op_regs->command);
1020 command |= CMD_CRS;
1021 writel(command, &xhci->op_regs->command);
1022 if (xhci_handshake(&xhci->op_regs->status,
1023 STS_RESTORE, 0, 10 * 1000)) {
1024 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1025 spin_unlock_irq(&xhci->lock);
1026 return -ETIMEDOUT;
1027 }
1028 temp = readl(&xhci->op_regs->status);
1029 }
1030
1031 /* If restore operation fails, re-initialize the HC during resume */
1032 if ((temp & STS_SRE) || hibernated) {
1033
1034 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1035 !(xhci_all_ports_seen_u0(xhci))) {
1036 del_timer_sync(&xhci->comp_mode_recovery_timer);
1037 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1038 "Compliance Mode Recovery Timer deleted!");
1039 }
1040
1041 /* Let the USB core know _both_ roothubs lost power. */
1042 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1043 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1044
1045 xhci_dbg(xhci, "Stop HCD\n");
1046 xhci_halt(xhci);
1047 xhci_reset(xhci);
1048 spin_unlock_irq(&xhci->lock);
1049 xhci_cleanup_msix(xhci);
1050
1051 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1052 temp = readl(&xhci->op_regs->status);
1053 writel(temp & ~STS_EINT, &xhci->op_regs->status);
1054 temp = readl(&xhci->ir_set->irq_pending);
1055 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1056 xhci_print_ir_set(xhci, 0);
1057
1058 xhci_dbg(xhci, "cleaning up memory\n");
1059 xhci_mem_cleanup(xhci);
1060 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1061 readl(&xhci->op_regs->status));
1062
1063 /* USB core calls the PCI reinit and start functions twice:
1064 * first with the primary HCD, and then with the secondary HCD.
1065 * If we don't do the same, the host will never be started.
1066 */
1067 if (!usb_hcd_is_primary_hcd(hcd))
1068 secondary_hcd = hcd;
1069 else
1070 secondary_hcd = xhci->shared_hcd;
1071
1072 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1073 retval = xhci_init(hcd->primary_hcd);
1074 if (retval)
1075 return retval;
1076 comp_timer_running = true;
1077
1078 xhci_dbg(xhci, "Start the primary HCD\n");
1079 retval = xhci_run(hcd->primary_hcd);
1080 if (!retval) {
1081 xhci_dbg(xhci, "Start the secondary HCD\n");
1082 retval = xhci_run(secondary_hcd);
1083 }
1084 hcd->state = HC_STATE_SUSPENDED;
1085 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1086 goto done;
1087 }
1088
1089 /* step 4: set Run/Stop bit */
1090 command = readl(&xhci->op_regs->command);
1091 command |= CMD_RUN;
1092 writel(command, &xhci->op_regs->command);
1093 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1094 0, 250 * 1000);
1095
1096 /* step 5: walk topology and initialize portsc,
1097 * portpmsc and portli
1098 */
1099 /* this is done in bus_resume */
1100
1101 /* step 6: restart each of the previously
1102 * Running endpoints by ringing their doorbells
1103 */
1104
1105 spin_unlock_irq(&xhci->lock);
1106
1107 done:
1108 if (retval == 0) {
1109 /* Resume root hubs only when have pending events. */
1110 status = readl(&xhci->op_regs->status);
1111 if (status & STS_EINT) {
1112 usb_hcd_resume_root_hub(xhci->shared_hcd);
1113 usb_hcd_resume_root_hub(hcd);
1114 }
1115 }
1116
1117 /*
1118 * If system is subject to the Quirk, Compliance Mode Timer needs to
1119 * be re-initialized Always after a system resume. Ports are subject
1120 * to suffer the Compliance Mode issue again. It doesn't matter if
1121 * ports have entered previously to U0 before system's suspension.
1122 */
1123 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1124 compliance_mode_recovery_timer_init(xhci);
1125
1126 /* Re-enable port polling. */
1127 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1128 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1129 usb_hcd_poll_rh_status(xhci->shared_hcd);
1130 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1131 usb_hcd_poll_rh_status(hcd);
1132
1133 return retval;
1134}
1135EXPORT_SYMBOL_GPL(xhci_resume);
1136#endif /* CONFIG_PM */
1137
1138/*-------------------------------------------------------------------------*/
1139
1140/**
1141 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1142 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1143 * value to right shift 1 for the bitmask.
1144 *
1145 * Index = (epnum * 2) + direction - 1,
1146 * where direction = 0 for OUT, 1 for IN.
1147 * For control endpoints, the IN index is used (OUT index is unused), so
1148 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1149 */
1150unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1151{
1152 unsigned int index;
1153 if (usb_endpoint_xfer_control(desc))
1154 index = (unsigned int) (usb_endpoint_num(desc)*2);
1155 else
1156 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1157 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1158 return index;
1159}
1160
1161/* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1162 * address from the XHCI endpoint index.
1163 */
1164unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1165{
1166 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1167 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1168 return direction | number;
1169}
1170
1171/* Find the flag for this endpoint (for use in the control context). Use the
1172 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1173 * bit 1, etc.
1174 */
1175unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1176{
1177 return 1 << (xhci_get_endpoint_index(desc) + 1);
1178}
1179
1180/* Find the flag for this endpoint (for use in the control context). Use the
1181 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1182 * bit 1, etc.
1183 */
1184unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1185{
1186 return 1 << (ep_index + 1);
1187}
1188
1189/* Compute the last valid endpoint context index. Basically, this is the
1190 * endpoint index plus one. For slot contexts with more than valid endpoint,
1191 * we find the most significant bit set in the added contexts flags.
1192 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1193 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1194 */
1195unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1196{
1197 return fls(added_ctxs) - 1;
1198}
1199
1200/* Returns 1 if the arguments are OK;
1201 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1202 */
1203static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1204 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1205 const char *func) {
1206 struct xhci_hcd *xhci;
1207 struct xhci_virt_device *virt_dev;
1208
1209 if (!hcd || (check_ep && !ep) || !udev) {
1210 pr_debug("xHCI %s called with invalid args\n", func);
1211 return -EINVAL;
1212 }
1213 if (!udev->parent) {
1214 pr_debug("xHCI %s called for root hub\n", func);
1215 return 0;
1216 }
1217
1218 xhci = hcd_to_xhci(hcd);
1219 if (check_virt_dev) {
1220 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1221 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1222 func);
1223 return -EINVAL;
1224 }
1225
1226 virt_dev = xhci->devs[udev->slot_id];
1227 if (virt_dev->udev != udev) {
1228 xhci_dbg(xhci, "xHCI %s called with udev and "
1229 "virt_dev does not match\n", func);
1230 return -EINVAL;
1231 }
1232 }
1233
1234 if (xhci->xhc_state & XHCI_STATE_HALTED)
1235 return -ENODEV;
1236
1237 return 1;
1238}
1239
1240static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1241 struct usb_device *udev, struct xhci_command *command,
1242 bool ctx_change, bool must_succeed);
1243
1244/*
1245 * Full speed devices may have a max packet size greater than 8 bytes, but the
1246 * USB core doesn't know that until it reads the first 8 bytes of the
1247 * descriptor. If the usb_device's max packet size changes after that point,
1248 * we need to issue an evaluate context command and wait on it.
1249 */
1250static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1251 unsigned int ep_index, struct urb *urb)
1252{
1253 struct xhci_container_ctx *out_ctx;
1254 struct xhci_input_control_ctx *ctrl_ctx;
1255 struct xhci_ep_ctx *ep_ctx;
1256 struct xhci_command *command;
1257 int max_packet_size;
1258 int hw_max_packet_size;
1259 int ret = 0;
1260
1261 out_ctx = xhci->devs[slot_id]->out_ctx;
1262 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1263 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1264 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1265 if (hw_max_packet_size != max_packet_size) {
1266 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1267 "Max Packet Size for ep 0 changed.");
1268 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1269 "Max packet size in usb_device = %d",
1270 max_packet_size);
1271 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1272 "Max packet size in xHCI HW = %d",
1273 hw_max_packet_size);
1274 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1275 "Issuing evaluate context command.");
1276
1277 /* Set up the input context flags for the command */
1278 /* FIXME: This won't work if a non-default control endpoint
1279 * changes max packet sizes.
1280 */
1281
1282 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
1283 if (!command)
1284 return -ENOMEM;
1285
1286 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1287 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1288 if (!ctrl_ctx) {
1289 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1290 __func__);
1291 ret = -ENOMEM;
1292 goto command_cleanup;
1293 }
1294 /* Set up the modified control endpoint 0 */
1295 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1296 xhci->devs[slot_id]->out_ctx, ep_index);
1297
1298 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1299 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1300 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1301
1302 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1303 ctrl_ctx->drop_flags = 0;
1304
1305 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1306 xhci_dbg_ctx(xhci, command->in_ctx, ep_index);
1307 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1308 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1309
1310 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1311 true, false);
1312
1313 /* Clean up the input context for later use by bandwidth
1314 * functions.
1315 */
1316 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1317command_cleanup:
1318 kfree(command->completion);
1319 kfree(command);
1320 }
1321 return ret;
1322}
1323
1324/*
1325 * non-error returns are a promise to giveback() the urb later
1326 * we drop ownership so next owner (or urb unlink) can get it
1327 */
1328int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1329{
1330 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1331 struct xhci_td *buffer;
1332 unsigned long flags;
1333 int ret = 0;
1334 unsigned int slot_id, ep_index;
1335 struct urb_priv *urb_priv;
1336 int size, i;
1337
1338 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1339 true, true, __func__) <= 0)
1340 return -EINVAL;
1341
1342 slot_id = urb->dev->slot_id;
1343 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1344
1345 if (!HCD_HW_ACCESSIBLE(hcd)) {
1346 if (!in_interrupt())
1347 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1348 ret = -ESHUTDOWN;
1349 goto exit;
1350 }
1351
1352 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1353 size = urb->number_of_packets;
1354 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1355 urb->transfer_buffer_length > 0 &&
1356 urb->transfer_flags & URB_ZERO_PACKET &&
1357 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1358 size = 2;
1359 else
1360 size = 1;
1361
1362 urb_priv = kzalloc(sizeof(struct urb_priv) +
1363 size * sizeof(struct xhci_td *), mem_flags);
1364 if (!urb_priv)
1365 return -ENOMEM;
1366
1367 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1368 if (!buffer) {
1369 kfree(urb_priv);
1370 return -ENOMEM;
1371 }
1372
1373 for (i = 0; i < size; i++) {
1374 urb_priv->td[i] = buffer;
1375 buffer++;
1376 }
1377
1378 urb_priv->length = size;
1379 urb_priv->td_cnt = 0;
1380 urb->hcpriv = urb_priv;
1381
1382 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1383 /* Check to see if the max packet size for the default control
1384 * endpoint changed during FS device enumeration
1385 */
1386 if (urb->dev->speed == USB_SPEED_FULL) {
1387 ret = xhci_check_maxpacket(xhci, slot_id,
1388 ep_index, urb);
1389 if (ret < 0) {
1390 xhci_urb_free_priv(urb_priv);
1391 urb->hcpriv = NULL;
1392 return ret;
1393 }
1394 }
1395
1396 /* We have a spinlock and interrupts disabled, so we must pass
1397 * atomic context to this function, which may allocate memory.
1398 */
1399 spin_lock_irqsave(&xhci->lock, flags);
1400 if (xhci->xhc_state & XHCI_STATE_DYING)
1401 goto dying;
1402 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1403 slot_id, ep_index);
1404 if (ret)
1405 goto free_priv;
1406 spin_unlock_irqrestore(&xhci->lock, flags);
1407 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1408 spin_lock_irqsave(&xhci->lock, flags);
1409 if (xhci->xhc_state & XHCI_STATE_DYING)
1410 goto dying;
1411 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1412 EP_GETTING_STREAMS) {
1413 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1414 "is transitioning to using streams.\n");
1415 ret = -EINVAL;
1416 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1417 EP_GETTING_NO_STREAMS) {
1418 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1419 "is transitioning to "
1420 "not having streams.\n");
1421 ret = -EINVAL;
1422 } else {
1423 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1424 slot_id, ep_index);
1425 }
1426 if (ret)
1427 goto free_priv;
1428 spin_unlock_irqrestore(&xhci->lock, flags);
1429 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1430 spin_lock_irqsave(&xhci->lock, flags);
1431 if (xhci->xhc_state & XHCI_STATE_DYING)
1432 goto dying;
1433 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1434 slot_id, ep_index);
1435 if (ret)
1436 goto free_priv;
1437 spin_unlock_irqrestore(&xhci->lock, flags);
1438 } else {
1439 spin_lock_irqsave(&xhci->lock, flags);
1440 if (xhci->xhc_state & XHCI_STATE_DYING)
1441 goto dying;
1442 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1443 slot_id, ep_index);
1444 if (ret)
1445 goto free_priv;
1446 spin_unlock_irqrestore(&xhci->lock, flags);
1447 }
1448exit:
1449 return ret;
1450dying:
1451 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1452 "non-responsive xHCI host.\n",
1453 urb->ep->desc.bEndpointAddress, urb);
1454 ret = -ESHUTDOWN;
1455free_priv:
1456 xhci_urb_free_priv(urb_priv);
1457 urb->hcpriv = NULL;
1458 spin_unlock_irqrestore(&xhci->lock, flags);
1459 return ret;
1460}
1461
1462/* Get the right ring for the given URB.
1463 * If the endpoint supports streams, boundary check the URB's stream ID.
1464 * If the endpoint doesn't support streams, return the singular endpoint ring.
1465 */
1466static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1467 struct urb *urb)
1468{
1469 unsigned int slot_id;
1470 unsigned int ep_index;
1471 unsigned int stream_id;
1472 struct xhci_virt_ep *ep;
1473
1474 slot_id = urb->dev->slot_id;
1475 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1476 stream_id = urb->stream_id;
1477 ep = &xhci->devs[slot_id]->eps[ep_index];
1478 /* Common case: no streams */
1479 if (!(ep->ep_state & EP_HAS_STREAMS))
1480 return ep->ring;
1481
1482 if (stream_id == 0) {
1483 xhci_warn(xhci,
1484 "WARN: Slot ID %u, ep index %u has streams, "
1485 "but URB has no stream ID.\n",
1486 slot_id, ep_index);
1487 return NULL;
1488 }
1489
1490 if (stream_id < ep->stream_info->num_streams)
1491 return ep->stream_info->stream_rings[stream_id];
1492
1493 xhci_warn(xhci,
1494 "WARN: Slot ID %u, ep index %u has "
1495 "stream IDs 1 to %u allocated, "
1496 "but stream ID %u is requested.\n",
1497 slot_id, ep_index,
1498 ep->stream_info->num_streams - 1,
1499 stream_id);
1500 return NULL;
1501}
1502
1503/*
1504 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1505 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1506 * should pick up where it left off in the TD, unless a Set Transfer Ring
1507 * Dequeue Pointer is issued.
1508 *
1509 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1510 * the ring. Since the ring is a contiguous structure, they can't be physically
1511 * removed. Instead, there are two options:
1512 *
1513 * 1) If the HC is in the middle of processing the URB to be canceled, we
1514 * simply move the ring's dequeue pointer past those TRBs using the Set
1515 * Transfer Ring Dequeue Pointer command. This will be the common case,
1516 * when drivers timeout on the last submitted URB and attempt to cancel.
1517 *
1518 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1519 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1520 * HC will need to invalidate the any TRBs it has cached after the stop
1521 * endpoint command, as noted in the xHCI 0.95 errata.
1522 *
1523 * 3) The TD may have completed by the time the Stop Endpoint Command
1524 * completes, so software needs to handle that case too.
1525 *
1526 * This function should protect against the TD enqueueing code ringing the
1527 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1528 * It also needs to account for multiple cancellations on happening at the same
1529 * time for the same endpoint.
1530 *
1531 * Note that this function can be called in any context, or so says
1532 * usb_hcd_unlink_urb()
1533 */
1534int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1535{
1536 unsigned long flags;
1537 int ret, i;
1538 u32 temp;
1539 struct xhci_hcd *xhci;
1540 struct urb_priv *urb_priv;
1541 struct xhci_td *td;
1542 unsigned int ep_index;
1543 struct xhci_ring *ep_ring;
1544 struct xhci_virt_ep *ep;
1545 struct xhci_command *command;
1546
1547 xhci = hcd_to_xhci(hcd);
1548 spin_lock_irqsave(&xhci->lock, flags);
1549 /* Make sure the URB hasn't completed or been unlinked already */
1550 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1551 if (ret || !urb->hcpriv)
1552 goto done;
1553 temp = readl(&xhci->op_regs->status);
1554 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1555 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1556 "HW died, freeing TD.");
1557 urb_priv = urb->hcpriv;
1558 for (i = urb_priv->td_cnt;
1559 i < urb_priv->length && xhci->devs[urb->dev->slot_id];
1560 i++) {
1561 td = urb_priv->td[i];
1562 if (!list_empty(&td->td_list))
1563 list_del_init(&td->td_list);
1564 if (!list_empty(&td->cancelled_td_list))
1565 list_del_init(&td->cancelled_td_list);
1566 }
1567
1568 usb_hcd_unlink_urb_from_ep(hcd, urb);
1569 spin_unlock_irqrestore(&xhci->lock, flags);
1570 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1571 xhci_urb_free_priv(urb_priv);
1572 return ret;
1573 }
1574 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
1575 (xhci->xhc_state & XHCI_STATE_HALTED)) {
1576 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1577 "Ep 0x%x: URB %p to be canceled on "
1578 "non-responsive xHCI host.",
1579 urb->ep->desc.bEndpointAddress, urb);
1580 /* Let the stop endpoint command watchdog timer (which set this
1581 * state) finish cleaning up the endpoint TD lists. We must
1582 * have caught it in the middle of dropping a lock and giving
1583 * back an URB.
1584 */
1585 goto done;
1586 }
1587
1588 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1589 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1590 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1591 if (!ep_ring) {
1592 ret = -EINVAL;
1593 goto done;
1594 }
1595
1596 urb_priv = urb->hcpriv;
1597 i = urb_priv->td_cnt;
1598 if (i < urb_priv->length)
1599 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1600 "Cancel URB %p, dev %s, ep 0x%x, "
1601 "starting at offset 0x%llx",
1602 urb, urb->dev->devpath,
1603 urb->ep->desc.bEndpointAddress,
1604 (unsigned long long) xhci_trb_virt_to_dma(
1605 urb_priv->td[i]->start_seg,
1606 urb_priv->td[i]->first_trb));
1607
1608 for (; i < urb_priv->length; i++) {
1609 td = urb_priv->td[i];
1610 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1611 }
1612
1613 /* Queue a stop endpoint command, but only if this is
1614 * the first cancellation to be handled.
1615 */
1616 if (!(ep->ep_state & EP_HALT_PENDING)) {
1617 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1618 if (!command) {
1619 ret = -ENOMEM;
1620 goto done;
1621 }
1622 ep->ep_state |= EP_HALT_PENDING;
1623 ep->stop_cmds_pending++;
1624 ep->stop_cmd_timer.expires = jiffies +
1625 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1626 add_timer(&ep->stop_cmd_timer);
1627 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1628 ep_index, 0);
1629 xhci_ring_cmd_db(xhci);
1630 }
1631done:
1632 spin_unlock_irqrestore(&xhci->lock, flags);
1633 return ret;
1634}
1635
1636/* Drop an endpoint from a new bandwidth configuration for this device.
1637 * Only one call to this function is allowed per endpoint before
1638 * check_bandwidth() or reset_bandwidth() must be called.
1639 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1640 * add the endpoint to the schedule with possibly new parameters denoted by a
1641 * different endpoint descriptor in usb_host_endpoint.
1642 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1643 * not allowed.
1644 *
1645 * The USB core will not allow URBs to be queued to an endpoint that is being
1646 * disabled, so there's no need for mutual exclusion to protect
1647 * the xhci->devs[slot_id] structure.
1648 */
1649int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1650 struct usb_host_endpoint *ep)
1651{
1652 struct xhci_hcd *xhci;
1653 struct xhci_container_ctx *in_ctx, *out_ctx;
1654 struct xhci_input_control_ctx *ctrl_ctx;
1655 unsigned int ep_index;
1656 struct xhci_ep_ctx *ep_ctx;
1657 u32 drop_flag;
1658 u32 new_add_flags, new_drop_flags;
1659 int ret;
1660
1661 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1662 if (ret <= 0)
1663 return ret;
1664 xhci = hcd_to_xhci(hcd);
1665 if (xhci->xhc_state & XHCI_STATE_DYING)
1666 return -ENODEV;
1667
1668 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1669 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1670 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1671 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1672 __func__, drop_flag);
1673 return 0;
1674 }
1675
1676 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1677 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1678 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1679 if (!ctrl_ctx) {
1680 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1681 __func__);
1682 return 0;
1683 }
1684
1685 ep_index = xhci_get_endpoint_index(&ep->desc);
1686 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1687 /* If the HC already knows the endpoint is disabled,
1688 * or the HCD has noted it is disabled, ignore this request
1689 */
1690 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1691 cpu_to_le32(EP_STATE_DISABLED)) ||
1692 le32_to_cpu(ctrl_ctx->drop_flags) &
1693 xhci_get_endpoint_flag(&ep->desc)) {
1694 /* Do not warn when called after a usb_device_reset */
1695 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1696 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1697 __func__, ep);
1698 return 0;
1699 }
1700
1701 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1702 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1703
1704 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1705 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1706
1707 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1708
1709 if (xhci->quirks & XHCI_MTK_HOST)
1710 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1711
1712 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1713 (unsigned int) ep->desc.bEndpointAddress,
1714 udev->slot_id,
1715 (unsigned int) new_drop_flags,
1716 (unsigned int) new_add_flags);
1717 return 0;
1718}
1719
1720/* Add an endpoint to a new possible bandwidth configuration for this device.
1721 * Only one call to this function is allowed per endpoint before
1722 * check_bandwidth() or reset_bandwidth() must be called.
1723 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1724 * add the endpoint to the schedule with possibly new parameters denoted by a
1725 * different endpoint descriptor in usb_host_endpoint.
1726 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1727 * not allowed.
1728 *
1729 * The USB core will not allow URBs to be queued to an endpoint until the
1730 * configuration or alt setting is installed in the device, so there's no need
1731 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1732 */
1733int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1734 struct usb_host_endpoint *ep)
1735{
1736 struct xhci_hcd *xhci;
1737 struct xhci_container_ctx *in_ctx;
1738 unsigned int ep_index;
1739 struct xhci_input_control_ctx *ctrl_ctx;
1740 u32 added_ctxs;
1741 u32 new_add_flags, new_drop_flags;
1742 struct xhci_virt_device *virt_dev;
1743 int ret = 0;
1744
1745 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1746 if (ret <= 0) {
1747 /* So we won't queue a reset ep command for a root hub */
1748 ep->hcpriv = NULL;
1749 return ret;
1750 }
1751 xhci = hcd_to_xhci(hcd);
1752 if (xhci->xhc_state & XHCI_STATE_DYING)
1753 return -ENODEV;
1754
1755 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1756 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1757 /* FIXME when we have to issue an evaluate endpoint command to
1758 * deal with ep0 max packet size changing once we get the
1759 * descriptors
1760 */
1761 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1762 __func__, added_ctxs);
1763 return 0;
1764 }
1765
1766 virt_dev = xhci->devs[udev->slot_id];
1767 in_ctx = virt_dev->in_ctx;
1768 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1769 if (!ctrl_ctx) {
1770 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1771 __func__);
1772 return 0;
1773 }
1774
1775 ep_index = xhci_get_endpoint_index(&ep->desc);
1776 /* If this endpoint is already in use, and the upper layers are trying
1777 * to add it again without dropping it, reject the addition.
1778 */
1779 if (virt_dev->eps[ep_index].ring &&
1780 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1781 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1782 "without dropping it.\n",
1783 (unsigned int) ep->desc.bEndpointAddress);
1784 return -EINVAL;
1785 }
1786
1787 /* If the HCD has already noted the endpoint is enabled,
1788 * ignore this request.
1789 */
1790 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1791 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1792 __func__, ep);
1793 return 0;
1794 }
1795
1796 /*
1797 * Configuration and alternate setting changes must be done in
1798 * process context, not interrupt context (or so documenation
1799 * for usb_set_interface() and usb_set_configuration() claim).
1800 */
1801 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1802 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1803 __func__, ep->desc.bEndpointAddress);
1804 return -ENOMEM;
1805 }
1806
1807 if (xhci->quirks & XHCI_MTK_HOST) {
1808 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1809 if (ret < 0) {
1810 xhci_free_or_cache_endpoint_ring(xhci,
1811 virt_dev, ep_index);
1812 return ret;
1813 }
1814 }
1815
1816 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1817 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1818
1819 /* If xhci_endpoint_disable() was called for this endpoint, but the
1820 * xHC hasn't been notified yet through the check_bandwidth() call,
1821 * this re-adds a new state for the endpoint from the new endpoint
1822 * descriptors. We must drop and re-add this endpoint, so we leave the
1823 * drop flags alone.
1824 */
1825 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1826
1827 /* Store the usb_device pointer for later use */
1828 ep->hcpriv = udev;
1829
1830 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1831 (unsigned int) ep->desc.bEndpointAddress,
1832 udev->slot_id,
1833 (unsigned int) new_drop_flags,
1834 (unsigned int) new_add_flags);
1835 return 0;
1836}
1837
1838static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1839{
1840 struct xhci_input_control_ctx *ctrl_ctx;
1841 struct xhci_ep_ctx *ep_ctx;
1842 struct xhci_slot_ctx *slot_ctx;
1843 int i;
1844
1845 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1846 if (!ctrl_ctx) {
1847 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1848 __func__);
1849 return;
1850 }
1851
1852 /* When a device's add flag and drop flag are zero, any subsequent
1853 * configure endpoint command will leave that endpoint's state
1854 * untouched. Make sure we don't leave any old state in the input
1855 * endpoint contexts.
1856 */
1857 ctrl_ctx->drop_flags = 0;
1858 ctrl_ctx->add_flags = 0;
1859 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1860 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1861 /* Endpoint 0 is always valid */
1862 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1863 for (i = 1; i < 31; ++i) {
1864 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1865 ep_ctx->ep_info = 0;
1866 ep_ctx->ep_info2 = 0;
1867 ep_ctx->deq = 0;
1868 ep_ctx->tx_info = 0;
1869 }
1870}
1871
1872static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1873 struct usb_device *udev, u32 *cmd_status)
1874{
1875 int ret;
1876
1877 switch (*cmd_status) {
1878 case COMP_CMD_ABORT:
1879 case COMP_CMD_STOP:
1880 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1881 ret = -ETIME;
1882 break;
1883 case COMP_ENOMEM:
1884 dev_warn(&udev->dev,
1885 "Not enough host controller resources for new device state.\n");
1886 ret = -ENOMEM;
1887 /* FIXME: can we allocate more resources for the HC? */
1888 break;
1889 case COMP_BW_ERR:
1890 case COMP_2ND_BW_ERR:
1891 dev_warn(&udev->dev,
1892 "Not enough bandwidth for new device state.\n");
1893 ret = -ENOSPC;
1894 /* FIXME: can we go back to the old state? */
1895 break;
1896 case COMP_TRB_ERR:
1897 /* the HCD set up something wrong */
1898 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1899 "add flag = 1, "
1900 "and endpoint is not disabled.\n");
1901 ret = -EINVAL;
1902 break;
1903 case COMP_DEV_ERR:
1904 dev_warn(&udev->dev,
1905 "ERROR: Incompatible device for endpoint configure command.\n");
1906 ret = -ENODEV;
1907 break;
1908 case COMP_SUCCESS:
1909 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1910 "Successful Endpoint Configure command");
1911 ret = 0;
1912 break;
1913 default:
1914 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1915 *cmd_status);
1916 ret = -EINVAL;
1917 break;
1918 }
1919 return ret;
1920}
1921
1922static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1923 struct usb_device *udev, u32 *cmd_status)
1924{
1925 int ret;
1926 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1927
1928 switch (*cmd_status) {
1929 case COMP_CMD_ABORT:
1930 case COMP_CMD_STOP:
1931 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1932 ret = -ETIME;
1933 break;
1934 case COMP_EINVAL:
1935 dev_warn(&udev->dev,
1936 "WARN: xHCI driver setup invalid evaluate context command.\n");
1937 ret = -EINVAL;
1938 break;
1939 case COMP_EBADSLT:
1940 dev_warn(&udev->dev,
1941 "WARN: slot not enabled for evaluate context command.\n");
1942 ret = -EINVAL;
1943 break;
1944 case COMP_CTX_STATE:
1945 dev_warn(&udev->dev,
1946 "WARN: invalid context state for evaluate context command.\n");
1947 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1948 ret = -EINVAL;
1949 break;
1950 case COMP_DEV_ERR:
1951 dev_warn(&udev->dev,
1952 "ERROR: Incompatible device for evaluate context command.\n");
1953 ret = -ENODEV;
1954 break;
1955 case COMP_MEL_ERR:
1956 /* Max Exit Latency too large error */
1957 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1958 ret = -EINVAL;
1959 break;
1960 case COMP_SUCCESS:
1961 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1962 "Successful evaluate context command");
1963 ret = 0;
1964 break;
1965 default:
1966 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1967 *cmd_status);
1968 ret = -EINVAL;
1969 break;
1970 }
1971 return ret;
1972}
1973
1974static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1975 struct xhci_input_control_ctx *ctrl_ctx)
1976{
1977 u32 valid_add_flags;
1978 u32 valid_drop_flags;
1979
1980 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1981 * (bit 1). The default control endpoint is added during the Address
1982 * Device command and is never removed until the slot is disabled.
1983 */
1984 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1985 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1986
1987 /* Use hweight32 to count the number of ones in the add flags, or
1988 * number of endpoints added. Don't count endpoints that are changed
1989 * (both added and dropped).
1990 */
1991 return hweight32(valid_add_flags) -
1992 hweight32(valid_add_flags & valid_drop_flags);
1993}
1994
1995static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1996 struct xhci_input_control_ctx *ctrl_ctx)
1997{
1998 u32 valid_add_flags;
1999 u32 valid_drop_flags;
2000
2001 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2002 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2003
2004 return hweight32(valid_drop_flags) -
2005 hweight32(valid_add_flags & valid_drop_flags);
2006}
2007
2008/*
2009 * We need to reserve the new number of endpoints before the configure endpoint
2010 * command completes. We can't subtract the dropped endpoints from the number
2011 * of active endpoints until the command completes because we can oversubscribe
2012 * the host in this case:
2013 *
2014 * - the first configure endpoint command drops more endpoints than it adds
2015 * - a second configure endpoint command that adds more endpoints is queued
2016 * - the first configure endpoint command fails, so the config is unchanged
2017 * - the second command may succeed, even though there isn't enough resources
2018 *
2019 * Must be called with xhci->lock held.
2020 */
2021static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2022 struct xhci_input_control_ctx *ctrl_ctx)
2023{
2024 u32 added_eps;
2025
2026 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2027 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2028 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2029 "Not enough ep ctxs: "
2030 "%u active, need to add %u, limit is %u.",
2031 xhci->num_active_eps, added_eps,
2032 xhci->limit_active_eps);
2033 return -ENOMEM;
2034 }
2035 xhci->num_active_eps += added_eps;
2036 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2037 "Adding %u ep ctxs, %u now active.", added_eps,
2038 xhci->num_active_eps);
2039 return 0;
2040}
2041
2042/*
2043 * The configure endpoint was failed by the xHC for some other reason, so we
2044 * need to revert the resources that failed configuration would have used.
2045 *
2046 * Must be called with xhci->lock held.
2047 */
2048static void xhci_free_host_resources(struct xhci_hcd *xhci,
2049 struct xhci_input_control_ctx *ctrl_ctx)
2050{
2051 u32 num_failed_eps;
2052
2053 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2054 xhci->num_active_eps -= num_failed_eps;
2055 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2056 "Removing %u failed ep ctxs, %u now active.",
2057 num_failed_eps,
2058 xhci->num_active_eps);
2059}
2060
2061/*
2062 * Now that the command has completed, clean up the active endpoint count by
2063 * subtracting out the endpoints that were dropped (but not changed).
2064 *
2065 * Must be called with xhci->lock held.
2066 */
2067static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2068 struct xhci_input_control_ctx *ctrl_ctx)
2069{
2070 u32 num_dropped_eps;
2071
2072 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2073 xhci->num_active_eps -= num_dropped_eps;
2074 if (num_dropped_eps)
2075 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2076 "Removing %u dropped ep ctxs, %u now active.",
2077 num_dropped_eps,
2078 xhci->num_active_eps);
2079}
2080
2081static unsigned int xhci_get_block_size(struct usb_device *udev)
2082{
2083 switch (udev->speed) {
2084 case USB_SPEED_LOW:
2085 case USB_SPEED_FULL:
2086 return FS_BLOCK;
2087 case USB_SPEED_HIGH:
2088 return HS_BLOCK;
2089 case USB_SPEED_SUPER:
2090 case USB_SPEED_SUPER_PLUS:
2091 return SS_BLOCK;
2092 case USB_SPEED_UNKNOWN:
2093 case USB_SPEED_WIRELESS:
2094 default:
2095 /* Should never happen */
2096 return 1;
2097 }
2098}
2099
2100static unsigned int
2101xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2102{
2103 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2104 return LS_OVERHEAD;
2105 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2106 return FS_OVERHEAD;
2107 return HS_OVERHEAD;
2108}
2109
2110/* If we are changing a LS/FS device under a HS hub,
2111 * make sure (if we are activating a new TT) that the HS bus has enough
2112 * bandwidth for this new TT.
2113 */
2114static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2115 struct xhci_virt_device *virt_dev,
2116 int old_active_eps)
2117{
2118 struct xhci_interval_bw_table *bw_table;
2119 struct xhci_tt_bw_info *tt_info;
2120
2121 /* Find the bandwidth table for the root port this TT is attached to. */
2122 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2123 tt_info = virt_dev->tt_info;
2124 /* If this TT already had active endpoints, the bandwidth for this TT
2125 * has already been added. Removing all periodic endpoints (and thus
2126 * making the TT enactive) will only decrease the bandwidth used.
2127 */
2128 if (old_active_eps)
2129 return 0;
2130 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2131 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2132 return -ENOMEM;
2133 return 0;
2134 }
2135 /* Not sure why we would have no new active endpoints...
2136 *
2137 * Maybe because of an Evaluate Context change for a hub update or a
2138 * control endpoint 0 max packet size change?
2139 * FIXME: skip the bandwidth calculation in that case.
2140 */
2141 return 0;
2142}
2143
2144static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2145 struct xhci_virt_device *virt_dev)
2146{
2147 unsigned int bw_reserved;
2148
2149 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2150 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2151 return -ENOMEM;
2152
2153 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2154 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2155 return -ENOMEM;
2156
2157 return 0;
2158}
2159
2160/*
2161 * This algorithm is a very conservative estimate of the worst-case scheduling
2162 * scenario for any one interval. The hardware dynamically schedules the
2163 * packets, so we can't tell which microframe could be the limiting factor in
2164 * the bandwidth scheduling. This only takes into account periodic endpoints.
2165 *
2166 * Obviously, we can't solve an NP complete problem to find the minimum worst
2167 * case scenario. Instead, we come up with an estimate that is no less than
2168 * the worst case bandwidth used for any one microframe, but may be an
2169 * over-estimate.
2170 *
2171 * We walk the requirements for each endpoint by interval, starting with the
2172 * smallest interval, and place packets in the schedule where there is only one
2173 * possible way to schedule packets for that interval. In order to simplify
2174 * this algorithm, we record the largest max packet size for each interval, and
2175 * assume all packets will be that size.
2176 *
2177 * For interval 0, we obviously must schedule all packets for each interval.
2178 * The bandwidth for interval 0 is just the amount of data to be transmitted
2179 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2180 * the number of packets).
2181 *
2182 * For interval 1, we have two possible microframes to schedule those packets
2183 * in. For this algorithm, if we can schedule the same number of packets for
2184 * each possible scheduling opportunity (each microframe), we will do so. The
2185 * remaining number of packets will be saved to be transmitted in the gaps in
2186 * the next interval's scheduling sequence.
2187 *
2188 * As we move those remaining packets to be scheduled with interval 2 packets,
2189 * we have to double the number of remaining packets to transmit. This is
2190 * because the intervals are actually powers of 2, and we would be transmitting
2191 * the previous interval's packets twice in this interval. We also have to be
2192 * sure that when we look at the largest max packet size for this interval, we
2193 * also look at the largest max packet size for the remaining packets and take
2194 * the greater of the two.
2195 *
2196 * The algorithm continues to evenly distribute packets in each scheduling
2197 * opportunity, and push the remaining packets out, until we get to the last
2198 * interval. Then those packets and their associated overhead are just added
2199 * to the bandwidth used.
2200 */
2201static int xhci_check_bw_table(struct xhci_hcd *xhci,
2202 struct xhci_virt_device *virt_dev,
2203 int old_active_eps)
2204{
2205 unsigned int bw_reserved;
2206 unsigned int max_bandwidth;
2207 unsigned int bw_used;
2208 unsigned int block_size;
2209 struct xhci_interval_bw_table *bw_table;
2210 unsigned int packet_size = 0;
2211 unsigned int overhead = 0;
2212 unsigned int packets_transmitted = 0;
2213 unsigned int packets_remaining = 0;
2214 unsigned int i;
2215
2216 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2217 return xhci_check_ss_bw(xhci, virt_dev);
2218
2219 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2220 max_bandwidth = HS_BW_LIMIT;
2221 /* Convert percent of bus BW reserved to blocks reserved */
2222 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2223 } else {
2224 max_bandwidth = FS_BW_LIMIT;
2225 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2226 }
2227
2228 bw_table = virt_dev->bw_table;
2229 /* We need to translate the max packet size and max ESIT payloads into
2230 * the units the hardware uses.
2231 */
2232 block_size = xhci_get_block_size(virt_dev->udev);
2233
2234 /* If we are manipulating a LS/FS device under a HS hub, double check
2235 * that the HS bus has enough bandwidth if we are activing a new TT.
2236 */
2237 if (virt_dev->tt_info) {
2238 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2239 "Recalculating BW for rootport %u",
2240 virt_dev->real_port);
2241 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2242 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2243 "newly activated TT.\n");
2244 return -ENOMEM;
2245 }
2246 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2247 "Recalculating BW for TT slot %u port %u",
2248 virt_dev->tt_info->slot_id,
2249 virt_dev->tt_info->ttport);
2250 } else {
2251 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2252 "Recalculating BW for rootport %u",
2253 virt_dev->real_port);
2254 }
2255
2256 /* Add in how much bandwidth will be used for interval zero, or the
2257 * rounded max ESIT payload + number of packets * largest overhead.
2258 */
2259 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2260 bw_table->interval_bw[0].num_packets *
2261 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2262
2263 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2264 unsigned int bw_added;
2265 unsigned int largest_mps;
2266 unsigned int interval_overhead;
2267
2268 /*
2269 * How many packets could we transmit in this interval?
2270 * If packets didn't fit in the previous interval, we will need
2271 * to transmit that many packets twice within this interval.
2272 */
2273 packets_remaining = 2 * packets_remaining +
2274 bw_table->interval_bw[i].num_packets;
2275
2276 /* Find the largest max packet size of this or the previous
2277 * interval.
2278 */
2279 if (list_empty(&bw_table->interval_bw[i].endpoints))
2280 largest_mps = 0;
2281 else {
2282 struct xhci_virt_ep *virt_ep;
2283 struct list_head *ep_entry;
2284
2285 ep_entry = bw_table->interval_bw[i].endpoints.next;
2286 virt_ep = list_entry(ep_entry,
2287 struct xhci_virt_ep, bw_endpoint_list);
2288 /* Convert to blocks, rounding up */
2289 largest_mps = DIV_ROUND_UP(
2290 virt_ep->bw_info.max_packet_size,
2291 block_size);
2292 }
2293 if (largest_mps > packet_size)
2294 packet_size = largest_mps;
2295
2296 /* Use the larger overhead of this or the previous interval. */
2297 interval_overhead = xhci_get_largest_overhead(
2298 &bw_table->interval_bw[i]);
2299 if (interval_overhead > overhead)
2300 overhead = interval_overhead;
2301
2302 /* How many packets can we evenly distribute across
2303 * (1 << (i + 1)) possible scheduling opportunities?
2304 */
2305 packets_transmitted = packets_remaining >> (i + 1);
2306
2307 /* Add in the bandwidth used for those scheduled packets */
2308 bw_added = packets_transmitted * (overhead + packet_size);
2309
2310 /* How many packets do we have remaining to transmit? */
2311 packets_remaining = packets_remaining % (1 << (i + 1));
2312
2313 /* What largest max packet size should those packets have? */
2314 /* If we've transmitted all packets, don't carry over the
2315 * largest packet size.
2316 */
2317 if (packets_remaining == 0) {
2318 packet_size = 0;
2319 overhead = 0;
2320 } else if (packets_transmitted > 0) {
2321 /* Otherwise if we do have remaining packets, and we've
2322 * scheduled some packets in this interval, take the
2323 * largest max packet size from endpoints with this
2324 * interval.
2325 */
2326 packet_size = largest_mps;
2327 overhead = interval_overhead;
2328 }
2329 /* Otherwise carry over packet_size and overhead from the last
2330 * time we had a remainder.
2331 */
2332 bw_used += bw_added;
2333 if (bw_used > max_bandwidth) {
2334 xhci_warn(xhci, "Not enough bandwidth. "
2335 "Proposed: %u, Max: %u\n",
2336 bw_used, max_bandwidth);
2337 return -ENOMEM;
2338 }
2339 }
2340 /*
2341 * Ok, we know we have some packets left over after even-handedly
2342 * scheduling interval 15. We don't know which microframes they will
2343 * fit into, so we over-schedule and say they will be scheduled every
2344 * microframe.
2345 */
2346 if (packets_remaining > 0)
2347 bw_used += overhead + packet_size;
2348
2349 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2350 unsigned int port_index = virt_dev->real_port - 1;
2351
2352 /* OK, we're manipulating a HS device attached to a
2353 * root port bandwidth domain. Include the number of active TTs
2354 * in the bandwidth used.
2355 */
2356 bw_used += TT_HS_OVERHEAD *
2357 xhci->rh_bw[port_index].num_active_tts;
2358 }
2359
2360 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2361 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2362 "Available: %u " "percent",
2363 bw_used, max_bandwidth, bw_reserved,
2364 (max_bandwidth - bw_used - bw_reserved) * 100 /
2365 max_bandwidth);
2366
2367 bw_used += bw_reserved;
2368 if (bw_used > max_bandwidth) {
2369 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2370 bw_used, max_bandwidth);
2371 return -ENOMEM;
2372 }
2373
2374 bw_table->bw_used = bw_used;
2375 return 0;
2376}
2377
2378static bool xhci_is_async_ep(unsigned int ep_type)
2379{
2380 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2381 ep_type != ISOC_IN_EP &&
2382 ep_type != INT_IN_EP);
2383}
2384
2385static bool xhci_is_sync_in_ep(unsigned int ep_type)
2386{
2387 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2388}
2389
2390static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2391{
2392 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2393
2394 if (ep_bw->ep_interval == 0)
2395 return SS_OVERHEAD_BURST +
2396 (ep_bw->mult * ep_bw->num_packets *
2397 (SS_OVERHEAD + mps));
2398 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2399 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2400 1 << ep_bw->ep_interval);
2401
2402}
2403
2404void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2405 struct xhci_bw_info *ep_bw,
2406 struct xhci_interval_bw_table *bw_table,
2407 struct usb_device *udev,
2408 struct xhci_virt_ep *virt_ep,
2409 struct xhci_tt_bw_info *tt_info)
2410{
2411 struct xhci_interval_bw *interval_bw;
2412 int normalized_interval;
2413
2414 if (xhci_is_async_ep(ep_bw->type))
2415 return;
2416
2417 if (udev->speed >= USB_SPEED_SUPER) {
2418 if (xhci_is_sync_in_ep(ep_bw->type))
2419 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2420 xhci_get_ss_bw_consumed(ep_bw);
2421 else
2422 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2423 xhci_get_ss_bw_consumed(ep_bw);
2424 return;
2425 }
2426
2427 /* SuperSpeed endpoints never get added to intervals in the table, so
2428 * this check is only valid for HS/FS/LS devices.
2429 */
2430 if (list_empty(&virt_ep->bw_endpoint_list))
2431 return;
2432 /* For LS/FS devices, we need to translate the interval expressed in
2433 * microframes to frames.
2434 */
2435 if (udev->speed == USB_SPEED_HIGH)
2436 normalized_interval = ep_bw->ep_interval;
2437 else
2438 normalized_interval = ep_bw->ep_interval - 3;
2439
2440 if (normalized_interval == 0)
2441 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2442 interval_bw = &bw_table->interval_bw[normalized_interval];
2443 interval_bw->num_packets -= ep_bw->num_packets;
2444 switch (udev->speed) {
2445 case USB_SPEED_LOW:
2446 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2447 break;
2448 case USB_SPEED_FULL:
2449 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2450 break;
2451 case USB_SPEED_HIGH:
2452 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2453 break;
2454 case USB_SPEED_SUPER:
2455 case USB_SPEED_SUPER_PLUS:
2456 case USB_SPEED_UNKNOWN:
2457 case USB_SPEED_WIRELESS:
2458 /* Should never happen because only LS/FS/HS endpoints will get
2459 * added to the endpoint list.
2460 */
2461 return;
2462 }
2463 if (tt_info)
2464 tt_info->active_eps -= 1;
2465 list_del_init(&virt_ep->bw_endpoint_list);
2466}
2467
2468static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2469 struct xhci_bw_info *ep_bw,
2470 struct xhci_interval_bw_table *bw_table,
2471 struct usb_device *udev,
2472 struct xhci_virt_ep *virt_ep,
2473 struct xhci_tt_bw_info *tt_info)
2474{
2475 struct xhci_interval_bw *interval_bw;
2476 struct xhci_virt_ep *smaller_ep;
2477 int normalized_interval;
2478
2479 if (xhci_is_async_ep(ep_bw->type))
2480 return;
2481
2482 if (udev->speed == USB_SPEED_SUPER) {
2483 if (xhci_is_sync_in_ep(ep_bw->type))
2484 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2485 xhci_get_ss_bw_consumed(ep_bw);
2486 else
2487 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2488 xhci_get_ss_bw_consumed(ep_bw);
2489 return;
2490 }
2491
2492 /* For LS/FS devices, we need to translate the interval expressed in
2493 * microframes to frames.
2494 */
2495 if (udev->speed == USB_SPEED_HIGH)
2496 normalized_interval = ep_bw->ep_interval;
2497 else
2498 normalized_interval = ep_bw->ep_interval - 3;
2499
2500 if (normalized_interval == 0)
2501 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2502 interval_bw = &bw_table->interval_bw[normalized_interval];
2503 interval_bw->num_packets += ep_bw->num_packets;
2504 switch (udev->speed) {
2505 case USB_SPEED_LOW:
2506 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2507 break;
2508 case USB_SPEED_FULL:
2509 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2510 break;
2511 case USB_SPEED_HIGH:
2512 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2513 break;
2514 case USB_SPEED_SUPER:
2515 case USB_SPEED_SUPER_PLUS:
2516 case USB_SPEED_UNKNOWN:
2517 case USB_SPEED_WIRELESS:
2518 /* Should never happen because only LS/FS/HS endpoints will get
2519 * added to the endpoint list.
2520 */
2521 return;
2522 }
2523
2524 if (tt_info)
2525 tt_info->active_eps += 1;
2526 /* Insert the endpoint into the list, largest max packet size first. */
2527 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2528 bw_endpoint_list) {
2529 if (ep_bw->max_packet_size >=
2530 smaller_ep->bw_info.max_packet_size) {
2531 /* Add the new ep before the smaller endpoint */
2532 list_add_tail(&virt_ep->bw_endpoint_list,
2533 &smaller_ep->bw_endpoint_list);
2534 return;
2535 }
2536 }
2537 /* Add the new endpoint at the end of the list. */
2538 list_add_tail(&virt_ep->bw_endpoint_list,
2539 &interval_bw->endpoints);
2540}
2541
2542void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2543 struct xhci_virt_device *virt_dev,
2544 int old_active_eps)
2545{
2546 struct xhci_root_port_bw_info *rh_bw_info;
2547 if (!virt_dev->tt_info)
2548 return;
2549
2550 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2551 if (old_active_eps == 0 &&
2552 virt_dev->tt_info->active_eps != 0) {
2553 rh_bw_info->num_active_tts += 1;
2554 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2555 } else if (old_active_eps != 0 &&
2556 virt_dev->tt_info->active_eps == 0) {
2557 rh_bw_info->num_active_tts -= 1;
2558 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2559 }
2560}
2561
2562static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2563 struct xhci_virt_device *virt_dev,
2564 struct xhci_container_ctx *in_ctx)
2565{
2566 struct xhci_bw_info ep_bw_info[31];
2567 int i;
2568 struct xhci_input_control_ctx *ctrl_ctx;
2569 int old_active_eps = 0;
2570
2571 if (virt_dev->tt_info)
2572 old_active_eps = virt_dev->tt_info->active_eps;
2573
2574 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2575 if (!ctrl_ctx) {
2576 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2577 __func__);
2578 return -ENOMEM;
2579 }
2580
2581 for (i = 0; i < 31; i++) {
2582 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2583 continue;
2584
2585 /* Make a copy of the BW info in case we need to revert this */
2586 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2587 sizeof(ep_bw_info[i]));
2588 /* Drop the endpoint from the interval table if the endpoint is
2589 * being dropped or changed.
2590 */
2591 if (EP_IS_DROPPED(ctrl_ctx, i))
2592 xhci_drop_ep_from_interval_table(xhci,
2593 &virt_dev->eps[i].bw_info,
2594 virt_dev->bw_table,
2595 virt_dev->udev,
2596 &virt_dev->eps[i],
2597 virt_dev->tt_info);
2598 }
2599 /* Overwrite the information stored in the endpoints' bw_info */
2600 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2601 for (i = 0; i < 31; i++) {
2602 /* Add any changed or added endpoints to the interval table */
2603 if (EP_IS_ADDED(ctrl_ctx, i))
2604 xhci_add_ep_to_interval_table(xhci,
2605 &virt_dev->eps[i].bw_info,
2606 virt_dev->bw_table,
2607 virt_dev->udev,
2608 &virt_dev->eps[i],
2609 virt_dev->tt_info);
2610 }
2611
2612 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2613 /* Ok, this fits in the bandwidth we have.
2614 * Update the number of active TTs.
2615 */
2616 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2617 return 0;
2618 }
2619
2620 /* We don't have enough bandwidth for this, revert the stored info. */
2621 for (i = 0; i < 31; i++) {
2622 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2623 continue;
2624
2625 /* Drop the new copies of any added or changed endpoints from
2626 * the interval table.
2627 */
2628 if (EP_IS_ADDED(ctrl_ctx, i)) {
2629 xhci_drop_ep_from_interval_table(xhci,
2630 &virt_dev->eps[i].bw_info,
2631 virt_dev->bw_table,
2632 virt_dev->udev,
2633 &virt_dev->eps[i],
2634 virt_dev->tt_info);
2635 }
2636 /* Revert the endpoint back to its old information */
2637 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2638 sizeof(ep_bw_info[i]));
2639 /* Add any changed or dropped endpoints back into the table */
2640 if (EP_IS_DROPPED(ctrl_ctx, i))
2641 xhci_add_ep_to_interval_table(xhci,
2642 &virt_dev->eps[i].bw_info,
2643 virt_dev->bw_table,
2644 virt_dev->udev,
2645 &virt_dev->eps[i],
2646 virt_dev->tt_info);
2647 }
2648 return -ENOMEM;
2649}
2650
2651
2652/* Issue a configure endpoint command or evaluate context command
2653 * and wait for it to finish.
2654 */
2655static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2656 struct usb_device *udev,
2657 struct xhci_command *command,
2658 bool ctx_change, bool must_succeed)
2659{
2660 int ret;
2661 unsigned long flags;
2662 struct xhci_input_control_ctx *ctrl_ctx;
2663 struct xhci_virt_device *virt_dev;
2664
2665 if (!command)
2666 return -EINVAL;
2667
2668 spin_lock_irqsave(&xhci->lock, flags);
2669 virt_dev = xhci->devs[udev->slot_id];
2670
2671 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2672 if (!ctrl_ctx) {
2673 spin_unlock_irqrestore(&xhci->lock, flags);
2674 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2675 __func__);
2676 return -ENOMEM;
2677 }
2678
2679 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2680 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2681 spin_unlock_irqrestore(&xhci->lock, flags);
2682 xhci_warn(xhci, "Not enough host resources, "
2683 "active endpoint contexts = %u\n",
2684 xhci->num_active_eps);
2685 return -ENOMEM;
2686 }
2687 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2688 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2689 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2690 xhci_free_host_resources(xhci, ctrl_ctx);
2691 spin_unlock_irqrestore(&xhci->lock, flags);
2692 xhci_warn(xhci, "Not enough bandwidth\n");
2693 return -ENOMEM;
2694 }
2695
2696 if (!ctx_change)
2697 ret = xhci_queue_configure_endpoint(xhci, command,
2698 command->in_ctx->dma,
2699 udev->slot_id, must_succeed);
2700 else
2701 ret = xhci_queue_evaluate_context(xhci, command,
2702 command->in_ctx->dma,
2703 udev->slot_id, must_succeed);
2704 if (ret < 0) {
2705 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2706 xhci_free_host_resources(xhci, ctrl_ctx);
2707 spin_unlock_irqrestore(&xhci->lock, flags);
2708 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2709 "FIXME allocate a new ring segment");
2710 return -ENOMEM;
2711 }
2712 xhci_ring_cmd_db(xhci);
2713 spin_unlock_irqrestore(&xhci->lock, flags);
2714
2715 /* Wait for the configure endpoint command to complete */
2716 wait_for_completion(command->completion);
2717
2718 if (!ctx_change)
2719 ret = xhci_configure_endpoint_result(xhci, udev,
2720 &command->status);
2721 else
2722 ret = xhci_evaluate_context_result(xhci, udev,
2723 &command->status);
2724
2725 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2726 spin_lock_irqsave(&xhci->lock, flags);
2727 /* If the command failed, remove the reserved resources.
2728 * Otherwise, clean up the estimate to include dropped eps.
2729 */
2730 if (ret)
2731 xhci_free_host_resources(xhci, ctrl_ctx);
2732 else
2733 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2734 spin_unlock_irqrestore(&xhci->lock, flags);
2735 }
2736 return ret;
2737}
2738
2739static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2740 struct xhci_virt_device *vdev, int i)
2741{
2742 struct xhci_virt_ep *ep = &vdev->eps[i];
2743
2744 if (ep->ep_state & EP_HAS_STREAMS) {
2745 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2746 xhci_get_endpoint_address(i));
2747 xhci_free_stream_info(xhci, ep->stream_info);
2748 ep->stream_info = NULL;
2749 ep->ep_state &= ~EP_HAS_STREAMS;
2750 }
2751}
2752
2753/* Called after one or more calls to xhci_add_endpoint() or
2754 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2755 * to call xhci_reset_bandwidth().
2756 *
2757 * Since we are in the middle of changing either configuration or
2758 * installing a new alt setting, the USB core won't allow URBs to be
2759 * enqueued for any endpoint on the old config or interface. Nothing
2760 * else should be touching the xhci->devs[slot_id] structure, so we
2761 * don't need to take the xhci->lock for manipulating that.
2762 */
2763int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2764{
2765 int i;
2766 int ret = 0;
2767 struct xhci_hcd *xhci;
2768 struct xhci_virt_device *virt_dev;
2769 struct xhci_input_control_ctx *ctrl_ctx;
2770 struct xhci_slot_ctx *slot_ctx;
2771 struct xhci_command *command;
2772
2773 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2774 if (ret <= 0)
2775 return ret;
2776 xhci = hcd_to_xhci(hcd);
2777 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2778 (xhci->xhc_state & XHCI_STATE_REMOVING))
2779 return -ENODEV;
2780
2781 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2782 virt_dev = xhci->devs[udev->slot_id];
2783
2784 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
2785 if (!command)
2786 return -ENOMEM;
2787
2788 command->in_ctx = virt_dev->in_ctx;
2789
2790 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2791 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2792 if (!ctrl_ctx) {
2793 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2794 __func__);
2795 ret = -ENOMEM;
2796 goto command_cleanup;
2797 }
2798 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2799 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2800 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2801
2802 /* Don't issue the command if there's no endpoints to update. */
2803 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2804 ctrl_ctx->drop_flags == 0) {
2805 ret = 0;
2806 goto command_cleanup;
2807 }
2808 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2809 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2810 for (i = 31; i >= 1; i--) {
2811 __le32 le32 = cpu_to_le32(BIT(i));
2812
2813 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2814 || (ctrl_ctx->add_flags & le32) || i == 1) {
2815 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2816 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2817 break;
2818 }
2819 }
2820 xhci_dbg(xhci, "New Input Control Context:\n");
2821 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2822 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2823
2824 ret = xhci_configure_endpoint(xhci, udev, command,
2825 false, false);
2826 if (ret)
2827 /* Callee should call reset_bandwidth() */
2828 goto command_cleanup;
2829
2830 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2831 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2832 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2833
2834 /* Free any rings that were dropped, but not changed. */
2835 for (i = 1; i < 31; ++i) {
2836 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2837 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2838 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2839 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2840 }
2841 }
2842 xhci_zero_in_ctx(xhci, virt_dev);
2843 /*
2844 * Install any rings for completely new endpoints or changed endpoints,
2845 * and free or cache any old rings from changed endpoints.
2846 */
2847 for (i = 1; i < 31; ++i) {
2848 if (!virt_dev->eps[i].new_ring)
2849 continue;
2850 /* Only cache or free the old ring if it exists.
2851 * It may not if this is the first add of an endpoint.
2852 */
2853 if (virt_dev->eps[i].ring) {
2854 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2855 }
2856 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2857 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2858 virt_dev->eps[i].new_ring = NULL;
2859 }
2860command_cleanup:
2861 kfree(command->completion);
2862 kfree(command);
2863
2864 return ret;
2865}
2866
2867void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2868{
2869 struct xhci_hcd *xhci;
2870 struct xhci_virt_device *virt_dev;
2871 int i, ret;
2872
2873 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2874 if (ret <= 0)
2875 return;
2876 xhci = hcd_to_xhci(hcd);
2877
2878 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2879 virt_dev = xhci->devs[udev->slot_id];
2880 /* Free any rings allocated for added endpoints */
2881 for (i = 0; i < 31; ++i) {
2882 if (virt_dev->eps[i].new_ring) {
2883 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2884 virt_dev->eps[i].new_ring = NULL;
2885 }
2886 }
2887 xhci_zero_in_ctx(xhci, virt_dev);
2888}
2889
2890static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2891 struct xhci_container_ctx *in_ctx,
2892 struct xhci_container_ctx *out_ctx,
2893 struct xhci_input_control_ctx *ctrl_ctx,
2894 u32 add_flags, u32 drop_flags)
2895{
2896 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2897 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2898 xhci_slot_copy(xhci, in_ctx, out_ctx);
2899 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2900
2901 xhci_dbg(xhci, "Input Context:\n");
2902 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2903}
2904
2905static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2906 unsigned int slot_id, unsigned int ep_index,
2907 struct xhci_dequeue_state *deq_state)
2908{
2909 struct xhci_input_control_ctx *ctrl_ctx;
2910 struct xhci_container_ctx *in_ctx;
2911 struct xhci_ep_ctx *ep_ctx;
2912 u32 added_ctxs;
2913 dma_addr_t addr;
2914
2915 in_ctx = xhci->devs[slot_id]->in_ctx;
2916 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2917 if (!ctrl_ctx) {
2918 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2919 __func__);
2920 return;
2921 }
2922
2923 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2924 xhci->devs[slot_id]->out_ctx, ep_index);
2925 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2926 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2927 deq_state->new_deq_ptr);
2928 if (addr == 0) {
2929 xhci_warn(xhci, "WARN Cannot submit config ep after "
2930 "reset ep command\n");
2931 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2932 deq_state->new_deq_seg,
2933 deq_state->new_deq_ptr);
2934 return;
2935 }
2936 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2937
2938 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2939 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2940 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2941 added_ctxs, added_ctxs);
2942}
2943
2944void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2945 unsigned int ep_index, struct xhci_td *td)
2946{
2947 struct xhci_dequeue_state deq_state;
2948 struct xhci_virt_ep *ep;
2949 struct usb_device *udev = td->urb->dev;
2950
2951 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2952 "Cleaning up stalled endpoint ring");
2953 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2954 /* We need to move the HW's dequeue pointer past this TD,
2955 * or it will attempt to resend it on the next doorbell ring.
2956 */
2957 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2958 ep_index, ep->stopped_stream, td, &deq_state);
2959
2960 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2961 return;
2962
2963 /* HW with the reset endpoint quirk will use the saved dequeue state to
2964 * issue a configure endpoint command later.
2965 */
2966 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2967 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2968 "Queueing new dequeue state");
2969 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2970 ep_index, ep->stopped_stream, &deq_state);
2971 } else {
2972 /* Better hope no one uses the input context between now and the
2973 * reset endpoint completion!
2974 * XXX: No idea how this hardware will react when stream rings
2975 * are enabled.
2976 */
2977 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2978 "Setting up input context for "
2979 "configure endpoint command");
2980 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2981 ep_index, &deq_state);
2982 }
2983}
2984
2985/* Called when clearing halted device. The core should have sent the control
2986 * message to clear the device halt condition. The host side of the halt should
2987 * already be cleared with a reset endpoint command issued when the STALL tx
2988 * event was received.
2989 *
2990 * Context: in_interrupt
2991 */
2992
2993void xhci_endpoint_reset(struct usb_hcd *hcd,
2994 struct usb_host_endpoint *ep)
2995{
2996 struct xhci_hcd *xhci;
2997
2998 xhci = hcd_to_xhci(hcd);
2999
3000 /*
3001 * We might need to implement the config ep cmd in xhci 4.8.1 note:
3002 * The Reset Endpoint Command may only be issued to endpoints in the
3003 * Halted state. If software wishes reset the Data Toggle or Sequence
3004 * Number of an endpoint that isn't in the Halted state, then software
3005 * may issue a Configure Endpoint Command with the Drop and Add bits set
3006 * for the target endpoint. that is in the Stopped state.
3007 */
3008
3009 /* For now just print debug to follow the situation */
3010 xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n",
3011 ep->desc.bEndpointAddress);
3012}
3013
3014static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3015 struct usb_device *udev, struct usb_host_endpoint *ep,
3016 unsigned int slot_id)
3017{
3018 int ret;
3019 unsigned int ep_index;
3020 unsigned int ep_state;
3021
3022 if (!ep)
3023 return -EINVAL;
3024 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3025 if (ret <= 0)
3026 return -EINVAL;
3027 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3028 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3029 " descriptor for ep 0x%x does not support streams\n",
3030 ep->desc.bEndpointAddress);
3031 return -EINVAL;
3032 }
3033
3034 ep_index = xhci_get_endpoint_index(&ep->desc);
3035 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3036 if (ep_state & EP_HAS_STREAMS ||
3037 ep_state & EP_GETTING_STREAMS) {
3038 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3039 "already has streams set up.\n",
3040 ep->desc.bEndpointAddress);
3041 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3042 "dynamic stream context array reallocation.\n");
3043 return -EINVAL;
3044 }
3045 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3046 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3047 "endpoint 0x%x; URBs are pending.\n",
3048 ep->desc.bEndpointAddress);
3049 return -EINVAL;
3050 }
3051 return 0;
3052}
3053
3054static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3055 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3056{
3057 unsigned int max_streams;
3058
3059 /* The stream context array size must be a power of two */
3060 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3061 /*
3062 * Find out how many primary stream array entries the host controller
3063 * supports. Later we may use secondary stream arrays (similar to 2nd
3064 * level page entries), but that's an optional feature for xHCI host
3065 * controllers. xHCs must support at least 4 stream IDs.
3066 */
3067 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3068 if (*num_stream_ctxs > max_streams) {
3069 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3070 max_streams);
3071 *num_stream_ctxs = max_streams;
3072 *num_streams = max_streams;
3073 }
3074}
3075
3076/* Returns an error code if one of the endpoint already has streams.
3077 * This does not change any data structures, it only checks and gathers
3078 * information.
3079 */
3080static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3081 struct usb_device *udev,
3082 struct usb_host_endpoint **eps, unsigned int num_eps,
3083 unsigned int *num_streams, u32 *changed_ep_bitmask)
3084{
3085 unsigned int max_streams;
3086 unsigned int endpoint_flag;
3087 int i;
3088 int ret;
3089
3090 for (i = 0; i < num_eps; i++) {
3091 ret = xhci_check_streams_endpoint(xhci, udev,
3092 eps[i], udev->slot_id);
3093 if (ret < 0)
3094 return ret;
3095
3096 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3097 if (max_streams < (*num_streams - 1)) {
3098 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3099 eps[i]->desc.bEndpointAddress,
3100 max_streams);
3101 *num_streams = max_streams+1;
3102 }
3103
3104 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3105 if (*changed_ep_bitmask & endpoint_flag)
3106 return -EINVAL;
3107 *changed_ep_bitmask |= endpoint_flag;
3108 }
3109 return 0;
3110}
3111
3112static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3113 struct usb_device *udev,
3114 struct usb_host_endpoint **eps, unsigned int num_eps)
3115{
3116 u32 changed_ep_bitmask = 0;
3117 unsigned int slot_id;
3118 unsigned int ep_index;
3119 unsigned int ep_state;
3120 int i;
3121
3122 slot_id = udev->slot_id;
3123 if (!xhci->devs[slot_id])
3124 return 0;
3125
3126 for (i = 0; i < num_eps; i++) {
3127 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3128 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3129 /* Are streams already being freed for the endpoint? */
3130 if (ep_state & EP_GETTING_NO_STREAMS) {
3131 xhci_warn(xhci, "WARN Can't disable streams for "
3132 "endpoint 0x%x, "
3133 "streams are being disabled already\n",
3134 eps[i]->desc.bEndpointAddress);
3135 return 0;
3136 }
3137 /* Are there actually any streams to free? */
3138 if (!(ep_state & EP_HAS_STREAMS) &&
3139 !(ep_state & EP_GETTING_STREAMS)) {
3140 xhci_warn(xhci, "WARN Can't disable streams for "
3141 "endpoint 0x%x, "
3142 "streams are already disabled!\n",
3143 eps[i]->desc.bEndpointAddress);
3144 xhci_warn(xhci, "WARN xhci_free_streams() called "
3145 "with non-streams endpoint\n");
3146 return 0;
3147 }
3148 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3149 }
3150 return changed_ep_bitmask;
3151}
3152
3153/*
3154 * The USB device drivers use this function (through the HCD interface in USB
3155 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3156 * coordinate mass storage command queueing across multiple endpoints (basically
3157 * a stream ID == a task ID).
3158 *
3159 * Setting up streams involves allocating the same size stream context array
3160 * for each endpoint and issuing a configure endpoint command for all endpoints.
3161 *
3162 * Don't allow the call to succeed if one endpoint only supports one stream
3163 * (which means it doesn't support streams at all).
3164 *
3165 * Drivers may get less stream IDs than they asked for, if the host controller
3166 * hardware or endpoints claim they can't support the number of requested
3167 * stream IDs.
3168 */
3169int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3170 struct usb_host_endpoint **eps, unsigned int num_eps,
3171 unsigned int num_streams, gfp_t mem_flags)
3172{
3173 int i, ret;
3174 struct xhci_hcd *xhci;
3175 struct xhci_virt_device *vdev;
3176 struct xhci_command *config_cmd;
3177 struct xhci_input_control_ctx *ctrl_ctx;
3178 unsigned int ep_index;
3179 unsigned int num_stream_ctxs;
3180 unsigned long flags;
3181 u32 changed_ep_bitmask = 0;
3182
3183 if (!eps)
3184 return -EINVAL;
3185
3186 /* Add one to the number of streams requested to account for
3187 * stream 0 that is reserved for xHCI usage.
3188 */
3189 num_streams += 1;
3190 xhci = hcd_to_xhci(hcd);
3191 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3192 num_streams);
3193
3194 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3195 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3196 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3197 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3198 return -ENOSYS;
3199 }
3200
3201 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3202 if (!config_cmd) {
3203 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3204 return -ENOMEM;
3205 }
3206 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3207 if (!ctrl_ctx) {
3208 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3209 __func__);
3210 xhci_free_command(xhci, config_cmd);
3211 return -ENOMEM;
3212 }
3213
3214 /* Check to make sure all endpoints are not already configured for
3215 * streams. While we're at it, find the maximum number of streams that
3216 * all the endpoints will support and check for duplicate endpoints.
3217 */
3218 spin_lock_irqsave(&xhci->lock, flags);
3219 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3220 num_eps, &num_streams, &changed_ep_bitmask);
3221 if (ret < 0) {
3222 xhci_free_command(xhci, config_cmd);
3223 spin_unlock_irqrestore(&xhci->lock, flags);
3224 return ret;
3225 }
3226 if (num_streams <= 1) {
3227 xhci_warn(xhci, "WARN: endpoints can't handle "
3228 "more than one stream.\n");
3229 xhci_free_command(xhci, config_cmd);
3230 spin_unlock_irqrestore(&xhci->lock, flags);
3231 return -EINVAL;
3232 }
3233 vdev = xhci->devs[udev->slot_id];
3234 /* Mark each endpoint as being in transition, so
3235 * xhci_urb_enqueue() will reject all URBs.
3236 */
3237 for (i = 0; i < num_eps; i++) {
3238 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3239 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3240 }
3241 spin_unlock_irqrestore(&xhci->lock, flags);
3242
3243 /* Setup internal data structures and allocate HW data structures for
3244 * streams (but don't install the HW structures in the input context
3245 * until we're sure all memory allocation succeeded).
3246 */
3247 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3248 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3249 num_stream_ctxs, num_streams);
3250
3251 for (i = 0; i < num_eps; i++) {
3252 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3253 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3254 num_stream_ctxs,
3255 num_streams, mem_flags);
3256 if (!vdev->eps[ep_index].stream_info)
3257 goto cleanup;
3258 /* Set maxPstreams in endpoint context and update deq ptr to
3259 * point to stream context array. FIXME
3260 */
3261 }
3262
3263 /* Set up the input context for a configure endpoint command. */
3264 for (i = 0; i < num_eps; i++) {
3265 struct xhci_ep_ctx *ep_ctx;
3266
3267 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3268 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3269
3270 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3271 vdev->out_ctx, ep_index);
3272 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3273 vdev->eps[ep_index].stream_info);
3274 }
3275 /* Tell the HW to drop its old copy of the endpoint context info
3276 * and add the updated copy from the input context.
3277 */
3278 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3279 vdev->out_ctx, ctrl_ctx,
3280 changed_ep_bitmask, changed_ep_bitmask);
3281
3282 /* Issue and wait for the configure endpoint command */
3283 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3284 false, false);
3285
3286 /* xHC rejected the configure endpoint command for some reason, so we
3287 * leave the old ring intact and free our internal streams data
3288 * structure.
3289 */
3290 if (ret < 0)
3291 goto cleanup;
3292
3293 spin_lock_irqsave(&xhci->lock, flags);
3294 for (i = 0; i < num_eps; i++) {
3295 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3296 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3297 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3298 udev->slot_id, ep_index);
3299 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3300 }
3301 xhci_free_command(xhci, config_cmd);
3302 spin_unlock_irqrestore(&xhci->lock, flags);
3303
3304 /* Subtract 1 for stream 0, which drivers can't use */
3305 return num_streams - 1;
3306
3307cleanup:
3308 /* If it didn't work, free the streams! */
3309 for (i = 0; i < num_eps; i++) {
3310 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3311 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3312 vdev->eps[ep_index].stream_info = NULL;
3313 /* FIXME Unset maxPstreams in endpoint context and
3314 * update deq ptr to point to normal string ring.
3315 */
3316 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3317 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3318 xhci_endpoint_zero(xhci, vdev, eps[i]);
3319 }
3320 xhci_free_command(xhci, config_cmd);
3321 return -ENOMEM;
3322}
3323
3324/* Transition the endpoint from using streams to being a "normal" endpoint
3325 * without streams.
3326 *
3327 * Modify the endpoint context state, submit a configure endpoint command,
3328 * and free all endpoint rings for streams if that completes successfully.
3329 */
3330int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3331 struct usb_host_endpoint **eps, unsigned int num_eps,
3332 gfp_t mem_flags)
3333{
3334 int i, ret;
3335 struct xhci_hcd *xhci;
3336 struct xhci_virt_device *vdev;
3337 struct xhci_command *command;
3338 struct xhci_input_control_ctx *ctrl_ctx;
3339 unsigned int ep_index;
3340 unsigned long flags;
3341 u32 changed_ep_bitmask;
3342
3343 xhci = hcd_to_xhci(hcd);
3344 vdev = xhci->devs[udev->slot_id];
3345
3346 /* Set up a configure endpoint command to remove the streams rings */
3347 spin_lock_irqsave(&xhci->lock, flags);
3348 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3349 udev, eps, num_eps);
3350 if (changed_ep_bitmask == 0) {
3351 spin_unlock_irqrestore(&xhci->lock, flags);
3352 return -EINVAL;
3353 }
3354
3355 /* Use the xhci_command structure from the first endpoint. We may have
3356 * allocated too many, but the driver may call xhci_free_streams() for
3357 * each endpoint it grouped into one call to xhci_alloc_streams().
3358 */
3359 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3360 command = vdev->eps[ep_index].stream_info->free_streams_command;
3361 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3362 if (!ctrl_ctx) {
3363 spin_unlock_irqrestore(&xhci->lock, flags);
3364 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3365 __func__);
3366 return -EINVAL;
3367 }
3368
3369 for (i = 0; i < num_eps; i++) {
3370 struct xhci_ep_ctx *ep_ctx;
3371
3372 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3373 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3374 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3375 EP_GETTING_NO_STREAMS;
3376
3377 xhci_endpoint_copy(xhci, command->in_ctx,
3378 vdev->out_ctx, ep_index);
3379 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3380 &vdev->eps[ep_index]);
3381 }
3382 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3383 vdev->out_ctx, ctrl_ctx,
3384 changed_ep_bitmask, changed_ep_bitmask);
3385 spin_unlock_irqrestore(&xhci->lock, flags);
3386
3387 /* Issue and wait for the configure endpoint command,
3388 * which must succeed.
3389 */
3390 ret = xhci_configure_endpoint(xhci, udev, command,
3391 false, true);
3392
3393 /* xHC rejected the configure endpoint command for some reason, so we
3394 * leave the streams rings intact.
3395 */
3396 if (ret < 0)
3397 return ret;
3398
3399 spin_lock_irqsave(&xhci->lock, flags);
3400 for (i = 0; i < num_eps; i++) {
3401 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3402 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3403 vdev->eps[ep_index].stream_info = NULL;
3404 /* FIXME Unset maxPstreams in endpoint context and
3405 * update deq ptr to point to normal string ring.
3406 */
3407 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3408 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3409 }
3410 spin_unlock_irqrestore(&xhci->lock, flags);
3411
3412 return 0;
3413}
3414
3415/*
3416 * Deletes endpoint resources for endpoints that were active before a Reset
3417 * Device command, or a Disable Slot command. The Reset Device command leaves
3418 * the control endpoint intact, whereas the Disable Slot command deletes it.
3419 *
3420 * Must be called with xhci->lock held.
3421 */
3422void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3423 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3424{
3425 int i;
3426 unsigned int num_dropped_eps = 0;
3427 unsigned int drop_flags = 0;
3428
3429 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3430 if (virt_dev->eps[i].ring) {
3431 drop_flags |= 1 << i;
3432 num_dropped_eps++;
3433 }
3434 }
3435 xhci->num_active_eps -= num_dropped_eps;
3436 if (num_dropped_eps)
3437 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3438 "Dropped %u ep ctxs, flags = 0x%x, "
3439 "%u now active.",
3440 num_dropped_eps, drop_flags,
3441 xhci->num_active_eps);
3442}
3443
3444/*
3445 * This submits a Reset Device Command, which will set the device state to 0,
3446 * set the device address to 0, and disable all the endpoints except the default
3447 * control endpoint. The USB core should come back and call
3448 * xhci_address_device(), and then re-set up the configuration. If this is
3449 * called because of a usb_reset_and_verify_device(), then the old alternate
3450 * settings will be re-installed through the normal bandwidth allocation
3451 * functions.
3452 *
3453 * Wait for the Reset Device command to finish. Remove all structures
3454 * associated with the endpoints that were disabled. Clear the input device
3455 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3456 *
3457 * If the virt_dev to be reset does not exist or does not match the udev,
3458 * it means the device is lost, possibly due to the xHC restore error and
3459 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3460 * re-allocate the device.
3461 */
3462int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3463{
3464 int ret, i;
3465 unsigned long flags;
3466 struct xhci_hcd *xhci;
3467 unsigned int slot_id;
3468 struct xhci_virt_device *virt_dev;
3469 struct xhci_command *reset_device_cmd;
3470 int last_freed_endpoint;
3471 struct xhci_slot_ctx *slot_ctx;
3472 int old_active_eps = 0;
3473
3474 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3475 if (ret <= 0)
3476 return ret;
3477 xhci = hcd_to_xhci(hcd);
3478 slot_id = udev->slot_id;
3479 virt_dev = xhci->devs[slot_id];
3480 if (!virt_dev) {
3481 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3482 "not exist. Re-allocate the device\n", slot_id);
3483 ret = xhci_alloc_dev(hcd, udev);
3484 if (ret == 1)
3485 return 0;
3486 else
3487 return -EINVAL;
3488 }
3489
3490 if (virt_dev->tt_info)
3491 old_active_eps = virt_dev->tt_info->active_eps;
3492
3493 if (virt_dev->udev != udev) {
3494 /* If the virt_dev and the udev does not match, this virt_dev
3495 * may belong to another udev.
3496 * Re-allocate the device.
3497 */
3498 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3499 "not match the udev. Re-allocate the device\n",
3500 slot_id);
3501 ret = xhci_alloc_dev(hcd, udev);
3502 if (ret == 1)
3503 return 0;
3504 else
3505 return -EINVAL;
3506 }
3507
3508 /* If device is not setup, there is no point in resetting it */
3509 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3510 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3511 SLOT_STATE_DISABLED)
3512 return 0;
3513
3514 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3515 /* Allocate the command structure that holds the struct completion.
3516 * Assume we're in process context, since the normal device reset
3517 * process has to wait for the device anyway. Storage devices are
3518 * reset as part of error handling, so use GFP_NOIO instead of
3519 * GFP_KERNEL.
3520 */
3521 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3522 if (!reset_device_cmd) {
3523 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3524 return -ENOMEM;
3525 }
3526
3527 /* Attempt to submit the Reset Device command to the command ring */
3528 spin_lock_irqsave(&xhci->lock, flags);
3529
3530 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3531 if (ret) {
3532 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3533 spin_unlock_irqrestore(&xhci->lock, flags);
3534 goto command_cleanup;
3535 }
3536 xhci_ring_cmd_db(xhci);
3537 spin_unlock_irqrestore(&xhci->lock, flags);
3538
3539 /* Wait for the Reset Device command to finish */
3540 wait_for_completion(reset_device_cmd->completion);
3541
3542 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3543 * unless we tried to reset a slot ID that wasn't enabled,
3544 * or the device wasn't in the addressed or configured state.
3545 */
3546 ret = reset_device_cmd->status;
3547 switch (ret) {
3548 case COMP_CMD_ABORT:
3549 case COMP_CMD_STOP:
3550 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3551 ret = -ETIME;
3552 goto command_cleanup;
3553 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3554 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3555 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3556 slot_id,
3557 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3558 xhci_dbg(xhci, "Not freeing device rings.\n");
3559 /* Don't treat this as an error. May change my mind later. */
3560 ret = 0;
3561 goto command_cleanup;
3562 case COMP_SUCCESS:
3563 xhci_dbg(xhci, "Successful reset device command.\n");
3564 break;
3565 default:
3566 if (xhci_is_vendor_info_code(xhci, ret))
3567 break;
3568 xhci_warn(xhci, "Unknown completion code %u for "
3569 "reset device command.\n", ret);
3570 ret = -EINVAL;
3571 goto command_cleanup;
3572 }
3573
3574 /* Free up host controller endpoint resources */
3575 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3576 spin_lock_irqsave(&xhci->lock, flags);
3577 /* Don't delete the default control endpoint resources */
3578 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3579 spin_unlock_irqrestore(&xhci->lock, flags);
3580 }
3581
3582 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3583 last_freed_endpoint = 1;
3584 for (i = 1; i < 31; ++i) {
3585 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3586
3587 if (ep->ep_state & EP_HAS_STREAMS) {
3588 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3589 xhci_get_endpoint_address(i));
3590 xhci_free_stream_info(xhci, ep->stream_info);
3591 ep->stream_info = NULL;
3592 ep->ep_state &= ~EP_HAS_STREAMS;
3593 }
3594
3595 if (ep->ring) {
3596 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3597 last_freed_endpoint = i;
3598 }
3599 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3600 xhci_drop_ep_from_interval_table(xhci,
3601 &virt_dev->eps[i].bw_info,
3602 virt_dev->bw_table,
3603 udev,
3604 &virt_dev->eps[i],
3605 virt_dev->tt_info);
3606 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3607 }
3608 /* If necessary, update the number of active TTs on this root port */
3609 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3610
3611 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3612 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3613 ret = 0;
3614
3615command_cleanup:
3616 xhci_free_command(xhci, reset_device_cmd);
3617 return ret;
3618}
3619
3620/*
3621 * At this point, the struct usb_device is about to go away, the device has
3622 * disconnected, and all traffic has been stopped and the endpoints have been
3623 * disabled. Free any HC data structures associated with that device.
3624 */
3625void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3626{
3627 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3628 struct xhci_virt_device *virt_dev;
3629 unsigned long flags;
3630 u32 state;
3631 int i, ret;
3632 struct xhci_command *command;
3633
3634 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3635 if (!command)
3636 return;
3637
3638#ifndef CONFIG_USB_DEFAULT_PERSIST
3639 /*
3640 * We called pm_runtime_get_noresume when the device was attached.
3641 * Decrement the counter here to allow controller to runtime suspend
3642 * if no devices remain.
3643 */
3644 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3645 pm_runtime_put_noidle(hcd->self.controller);
3646#endif
3647
3648 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3649 /* If the host is halted due to driver unload, we still need to free the
3650 * device.
3651 */
3652 if (ret <= 0 && ret != -ENODEV) {
3653 kfree(command);
3654 return;
3655 }
3656
3657 virt_dev = xhci->devs[udev->slot_id];
3658
3659 /* Stop any wayward timer functions (which may grab the lock) */
3660 for (i = 0; i < 31; ++i) {
3661 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3662 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3663 }
3664
3665 spin_lock_irqsave(&xhci->lock, flags);
3666 /* Don't disable the slot if the host controller is dead. */
3667 state = readl(&xhci->op_regs->status);
3668 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3669 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3670 xhci_free_virt_device(xhci, udev->slot_id);
3671 spin_unlock_irqrestore(&xhci->lock, flags);
3672 kfree(command);
3673 return;
3674 }
3675
3676 if (xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3677 udev->slot_id)) {
3678 spin_unlock_irqrestore(&xhci->lock, flags);
3679 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3680 return;
3681 }
3682 xhci_ring_cmd_db(xhci);
3683 spin_unlock_irqrestore(&xhci->lock, flags);
3684
3685 /*
3686 * Event command completion handler will free any data structures
3687 * associated with the slot. XXX Can free sleep?
3688 */
3689}
3690
3691/*
3692 * Checks if we have enough host controller resources for the default control
3693 * endpoint.
3694 *
3695 * Must be called with xhci->lock held.
3696 */
3697static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3698{
3699 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3700 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3701 "Not enough ep ctxs: "
3702 "%u active, need to add 1, limit is %u.",
3703 xhci->num_active_eps, xhci->limit_active_eps);
3704 return -ENOMEM;
3705 }
3706 xhci->num_active_eps += 1;
3707 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3708 "Adding 1 ep ctx, %u now active.",
3709 xhci->num_active_eps);
3710 return 0;
3711}
3712
3713
3714/*
3715 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3716 * timed out, or allocating memory failed. Returns 1 on success.
3717 */
3718int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3719{
3720 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3721 unsigned long flags;
3722 int ret, slot_id;
3723 struct xhci_command *command;
3724
3725 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3726 if (!command)
3727 return 0;
3728
3729 /* xhci->slot_id and xhci->addr_dev are not thread-safe */
3730 mutex_lock(&xhci->mutex);
3731 spin_lock_irqsave(&xhci->lock, flags);
3732 command->completion = &xhci->addr_dev;
3733 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3734 if (ret) {
3735 spin_unlock_irqrestore(&xhci->lock, flags);
3736 mutex_unlock(&xhci->mutex);
3737 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3738 kfree(command);
3739 return 0;
3740 }
3741 xhci_ring_cmd_db(xhci);
3742 spin_unlock_irqrestore(&xhci->lock, flags);
3743
3744 wait_for_completion(command->completion);
3745 slot_id = xhci->slot_id;
3746 mutex_unlock(&xhci->mutex);
3747
3748 if (!slot_id || command->status != COMP_SUCCESS) {
3749 xhci_err(xhci, "Error while assigning device slot ID\n");
3750 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3751 HCS_MAX_SLOTS(
3752 readl(&xhci->cap_regs->hcs_params1)));
3753 kfree(command);
3754 return 0;
3755 }
3756
3757 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3758 spin_lock_irqsave(&xhci->lock, flags);
3759 ret = xhci_reserve_host_control_ep_resources(xhci);
3760 if (ret) {
3761 spin_unlock_irqrestore(&xhci->lock, flags);
3762 xhci_warn(xhci, "Not enough host resources, "
3763 "active endpoint contexts = %u\n",
3764 xhci->num_active_eps);
3765 goto disable_slot;
3766 }
3767 spin_unlock_irqrestore(&xhci->lock, flags);
3768 }
3769 /* Use GFP_NOIO, since this function can be called from
3770 * xhci_discover_or_reset_device(), which may be called as part of
3771 * mass storage driver error handling.
3772 */
3773 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3774 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3775 goto disable_slot;
3776 }
3777 udev->slot_id = slot_id;
3778
3779#ifndef CONFIG_USB_DEFAULT_PERSIST
3780 /*
3781 * If resetting upon resume, we can't put the controller into runtime
3782 * suspend if there is a device attached.
3783 */
3784 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3785 pm_runtime_get_noresume(hcd->self.controller);
3786#endif
3787
3788
3789 kfree(command);
3790 /* Is this a LS or FS device under a HS hub? */
3791 /* Hub or peripherial? */
3792 return 1;
3793
3794disable_slot:
3795 /* Disable slot, if we can do it without mem alloc */
3796 spin_lock_irqsave(&xhci->lock, flags);
3797 command->completion = NULL;
3798 command->status = 0;
3799 if (!xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3800 udev->slot_id))
3801 xhci_ring_cmd_db(xhci);
3802 spin_unlock_irqrestore(&xhci->lock, flags);
3803 return 0;
3804}
3805
3806/*
3807 * Issue an Address Device command and optionally send a corresponding
3808 * SetAddress request to the device.
3809 */
3810static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3811 enum xhci_setup_dev setup)
3812{
3813 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3814 unsigned long flags;
3815 struct xhci_virt_device *virt_dev;
3816 int ret = 0;
3817 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3818 struct xhci_slot_ctx *slot_ctx;
3819 struct xhci_input_control_ctx *ctrl_ctx;
3820 u64 temp_64;
3821 struct xhci_command *command = NULL;
3822
3823 mutex_lock(&xhci->mutex);
3824
3825 if (xhci->xhc_state) /* dying, removing or halted */
3826 goto out;
3827
3828 if (!udev->slot_id) {
3829 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3830 "Bad Slot ID %d", udev->slot_id);
3831 ret = -EINVAL;
3832 goto out;
3833 }
3834
3835 virt_dev = xhci->devs[udev->slot_id];
3836
3837 if (WARN_ON(!virt_dev)) {
3838 /*
3839 * In plug/unplug torture test with an NEC controller,
3840 * a zero-dereference was observed once due to virt_dev = 0.
3841 * Print useful debug rather than crash if it is observed again!
3842 */
3843 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3844 udev->slot_id);
3845 ret = -EINVAL;
3846 goto out;
3847 }
3848
3849 if (setup == SETUP_CONTEXT_ONLY) {
3850 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3851 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3852 SLOT_STATE_DEFAULT) {
3853 xhci_dbg(xhci, "Slot already in default state\n");
3854 goto out;
3855 }
3856 }
3857
3858 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3859 if (!command) {
3860 ret = -ENOMEM;
3861 goto out;
3862 }
3863
3864 command->in_ctx = virt_dev->in_ctx;
3865 command->completion = &xhci->addr_dev;
3866
3867 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3868 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3869 if (!ctrl_ctx) {
3870 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3871 __func__);
3872 ret = -EINVAL;
3873 goto out;
3874 }
3875 /*
3876 * If this is the first Set Address since device plug-in or
3877 * virt_device realloaction after a resume with an xHCI power loss,
3878 * then set up the slot context.
3879 */
3880 if (!slot_ctx->dev_info)
3881 xhci_setup_addressable_virt_dev(xhci, udev);
3882 /* Otherwise, update the control endpoint ring enqueue pointer. */
3883 else
3884 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3885 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3886 ctrl_ctx->drop_flags = 0;
3887
3888 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3889 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3890 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3891 le32_to_cpu(slot_ctx->dev_info) >> 27);
3892
3893 spin_lock_irqsave(&xhci->lock, flags);
3894 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
3895 udev->slot_id, setup);
3896 if (ret) {
3897 spin_unlock_irqrestore(&xhci->lock, flags);
3898 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3899 "FIXME: allocate a command ring segment");
3900 goto out;
3901 }
3902 xhci_ring_cmd_db(xhci);
3903 spin_unlock_irqrestore(&xhci->lock, flags);
3904
3905 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3906 wait_for_completion(command->completion);
3907
3908 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3909 * the SetAddress() "recovery interval" required by USB and aborting the
3910 * command on a timeout.
3911 */
3912 switch (command->status) {
3913 case COMP_CMD_ABORT:
3914 case COMP_CMD_STOP:
3915 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
3916 ret = -ETIME;
3917 break;
3918 case COMP_CTX_STATE:
3919 case COMP_EBADSLT:
3920 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
3921 act, udev->slot_id);
3922 ret = -EINVAL;
3923 break;
3924 case COMP_TX_ERR:
3925 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
3926 ret = -EPROTO;
3927 break;
3928 case COMP_DEV_ERR:
3929 dev_warn(&udev->dev,
3930 "ERROR: Incompatible device for setup %s command\n", act);
3931 ret = -ENODEV;
3932 break;
3933 case COMP_SUCCESS:
3934 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3935 "Successful setup %s command", act);
3936 break;
3937 default:
3938 xhci_err(xhci,
3939 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3940 act, command->status);
3941 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3942 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3943 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
3944 ret = -EINVAL;
3945 break;
3946 }
3947 if (ret)
3948 goto out;
3949 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3950 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3951 "Op regs DCBAA ptr = %#016llx", temp_64);
3952 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3953 "Slot ID %d dcbaa entry @%p = %#016llx",
3954 udev->slot_id,
3955 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3956 (unsigned long long)
3957 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3958 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3959 "Output Context DMA address = %#08llx",
3960 (unsigned long long)virt_dev->out_ctx->dma);
3961 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3962 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3963 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3964 le32_to_cpu(slot_ctx->dev_info) >> 27);
3965 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3966 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3967 /*
3968 * USB core uses address 1 for the roothubs, so we add one to the
3969 * address given back to us by the HC.
3970 */
3971 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3972 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
3973 le32_to_cpu(slot_ctx->dev_info) >> 27);
3974 /* Zero the input context control for later use */
3975 ctrl_ctx->add_flags = 0;
3976 ctrl_ctx->drop_flags = 0;
3977
3978 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3979 "Internal device address = %d",
3980 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
3981out:
3982 mutex_unlock(&xhci->mutex);
3983 kfree(command);
3984 return ret;
3985}
3986
3987int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3988{
3989 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
3990}
3991
3992int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
3993{
3994 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
3995}
3996
3997/*
3998 * Transfer the port index into real index in the HW port status
3999 * registers. Caculate offset between the port's PORTSC register
4000 * and port status base. Divide the number of per port register
4001 * to get the real index. The raw port number bases 1.
4002 */
4003int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4004{
4005 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4006 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
4007 __le32 __iomem *addr;
4008 int raw_port;
4009
4010 if (hcd->speed < HCD_USB3)
4011 addr = xhci->usb2_ports[port1 - 1];
4012 else
4013 addr = xhci->usb3_ports[port1 - 1];
4014
4015 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
4016 return raw_port;
4017}
4018
4019/*
4020 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4021 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4022 */
4023static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4024 struct usb_device *udev, u16 max_exit_latency)
4025{
4026 struct xhci_virt_device *virt_dev;
4027 struct xhci_command *command;
4028 struct xhci_input_control_ctx *ctrl_ctx;
4029 struct xhci_slot_ctx *slot_ctx;
4030 unsigned long flags;
4031 int ret;
4032
4033 spin_lock_irqsave(&xhci->lock, flags);
4034
4035 virt_dev = xhci->devs[udev->slot_id];
4036
4037 /*
4038 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4039 * xHC was re-initialized. Exit latency will be set later after
4040 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4041 */
4042
4043 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4044 spin_unlock_irqrestore(&xhci->lock, flags);
4045 return 0;
4046 }
4047
4048 /* Attempt to issue an Evaluate Context command to change the MEL. */
4049 command = xhci->lpm_command;
4050 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4051 if (!ctrl_ctx) {
4052 spin_unlock_irqrestore(&xhci->lock, flags);
4053 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4054 __func__);
4055 return -ENOMEM;
4056 }
4057
4058 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4059 spin_unlock_irqrestore(&xhci->lock, flags);
4060
4061 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4062 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4063 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4064 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4065 slot_ctx->dev_state = 0;
4066
4067 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4068 "Set up evaluate context for LPM MEL change.");
4069 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
4070 xhci_dbg_ctx(xhci, command->in_ctx, 0);
4071
4072 /* Issue and wait for the evaluate context command. */
4073 ret = xhci_configure_endpoint(xhci, udev, command,
4074 true, true);
4075 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
4076 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
4077
4078 if (!ret) {
4079 spin_lock_irqsave(&xhci->lock, flags);
4080 virt_dev->current_mel = max_exit_latency;
4081 spin_unlock_irqrestore(&xhci->lock, flags);
4082 }
4083 return ret;
4084}
4085
4086#ifdef CONFIG_PM
4087
4088/* BESL to HIRD Encoding array for USB2 LPM */
4089static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4090 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4091
4092/* Calculate HIRD/BESL for USB2 PORTPMSC*/
4093static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4094 struct usb_device *udev)
4095{
4096 int u2del, besl, besl_host;
4097 int besl_device = 0;
4098 u32 field;
4099
4100 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4101 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4102
4103 if (field & USB_BESL_SUPPORT) {
4104 for (besl_host = 0; besl_host < 16; besl_host++) {
4105 if (xhci_besl_encoding[besl_host] >= u2del)
4106 break;
4107 }
4108 /* Use baseline BESL value as default */
4109 if (field & USB_BESL_BASELINE_VALID)
4110 besl_device = USB_GET_BESL_BASELINE(field);
4111 else if (field & USB_BESL_DEEP_VALID)
4112 besl_device = USB_GET_BESL_DEEP(field);
4113 } else {
4114 if (u2del <= 50)
4115 besl_host = 0;
4116 else
4117 besl_host = (u2del - 51) / 75 + 1;
4118 }
4119
4120 besl = besl_host + besl_device;
4121 if (besl > 15)
4122 besl = 15;
4123
4124 return besl;
4125}
4126
4127/* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4128static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4129{
4130 u32 field;
4131 int l1;
4132 int besld = 0;
4133 int hirdm = 0;
4134
4135 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4136
4137 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4138 l1 = udev->l1_params.timeout / 256;
4139
4140 /* device has preferred BESLD */
4141 if (field & USB_BESL_DEEP_VALID) {
4142 besld = USB_GET_BESL_DEEP(field);
4143 hirdm = 1;
4144 }
4145
4146 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4147}
4148
4149int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4150 struct usb_device *udev, int enable)
4151{
4152 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4153 __le32 __iomem **port_array;
4154 __le32 __iomem *pm_addr, *hlpm_addr;
4155 u32 pm_val, hlpm_val, field;
4156 unsigned int port_num;
4157 unsigned long flags;
4158 int hird, exit_latency;
4159 int ret;
4160
4161 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4162 !udev->lpm_capable)
4163 return -EPERM;
4164
4165 if (!udev->parent || udev->parent->parent ||
4166 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4167 return -EPERM;
4168
4169 if (udev->usb2_hw_lpm_capable != 1)
4170 return -EPERM;
4171
4172 spin_lock_irqsave(&xhci->lock, flags);
4173
4174 port_array = xhci->usb2_ports;
4175 port_num = udev->portnum - 1;
4176 pm_addr = port_array[port_num] + PORTPMSC;
4177 pm_val = readl(pm_addr);
4178 hlpm_addr = port_array[port_num] + PORTHLPMC;
4179 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4180
4181 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4182 enable ? "enable" : "disable", port_num + 1);
4183
4184 if (enable) {
4185 /* Host supports BESL timeout instead of HIRD */
4186 if (udev->usb2_hw_lpm_besl_capable) {
4187 /* if device doesn't have a preferred BESL value use a
4188 * default one which works with mixed HIRD and BESL
4189 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4190 */
4191 if ((field & USB_BESL_SUPPORT) &&
4192 (field & USB_BESL_BASELINE_VALID))
4193 hird = USB_GET_BESL_BASELINE(field);
4194 else
4195 hird = udev->l1_params.besl;
4196
4197 exit_latency = xhci_besl_encoding[hird];
4198 spin_unlock_irqrestore(&xhci->lock, flags);
4199
4200 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4201 * input context for link powermanagement evaluate
4202 * context commands. It is protected by hcd->bandwidth
4203 * mutex and is shared by all devices. We need to set
4204 * the max ext latency in USB 2 BESL LPM as well, so
4205 * use the same mutex and xhci_change_max_exit_latency()
4206 */
4207 mutex_lock(hcd->bandwidth_mutex);
4208 ret = xhci_change_max_exit_latency(xhci, udev,
4209 exit_latency);
4210 mutex_unlock(hcd->bandwidth_mutex);
4211
4212 if (ret < 0)
4213 return ret;
4214 spin_lock_irqsave(&xhci->lock, flags);
4215
4216 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4217 writel(hlpm_val, hlpm_addr);
4218 /* flush write */
4219 readl(hlpm_addr);
4220 } else {
4221 hird = xhci_calculate_hird_besl(xhci, udev);
4222 }
4223
4224 pm_val &= ~PORT_HIRD_MASK;
4225 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4226 writel(pm_val, pm_addr);
4227 pm_val = readl(pm_addr);
4228 pm_val |= PORT_HLE;
4229 writel(pm_val, pm_addr);
4230 /* flush write */
4231 readl(pm_addr);
4232 } else {
4233 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4234 writel(pm_val, pm_addr);
4235 /* flush write */
4236 readl(pm_addr);
4237 if (udev->usb2_hw_lpm_besl_capable) {
4238 spin_unlock_irqrestore(&xhci->lock, flags);
4239 mutex_lock(hcd->bandwidth_mutex);
4240 xhci_change_max_exit_latency(xhci, udev, 0);
4241 mutex_unlock(hcd->bandwidth_mutex);
4242 return 0;
4243 }
4244 }
4245
4246 spin_unlock_irqrestore(&xhci->lock, flags);
4247 return 0;
4248}
4249
4250/* check if a usb2 port supports a given extened capability protocol
4251 * only USB2 ports extended protocol capability values are cached.
4252 * Return 1 if capability is supported
4253 */
4254static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4255 unsigned capability)
4256{
4257 u32 port_offset, port_count;
4258 int i;
4259
4260 for (i = 0; i < xhci->num_ext_caps; i++) {
4261 if (xhci->ext_caps[i] & capability) {
4262 /* port offsets starts at 1 */
4263 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4264 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4265 if (port >= port_offset &&
4266 port < port_offset + port_count)
4267 return 1;
4268 }
4269 }
4270 return 0;
4271}
4272
4273int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4274{
4275 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4276 int portnum = udev->portnum - 1;
4277
4278 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4279 !udev->lpm_capable)
4280 return 0;
4281
4282 /* we only support lpm for non-hub device connected to root hub yet */
4283 if (!udev->parent || udev->parent->parent ||
4284 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4285 return 0;
4286
4287 if (xhci->hw_lpm_support == 1 &&
4288 xhci_check_usb2_port_capability(
4289 xhci, portnum, XHCI_HLC)) {
4290 udev->usb2_hw_lpm_capable = 1;
4291 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4292 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4293 if (xhci_check_usb2_port_capability(xhci, portnum,
4294 XHCI_BLC))
4295 udev->usb2_hw_lpm_besl_capable = 1;
4296 }
4297
4298 return 0;
4299}
4300
4301/*---------------------- USB 3.0 Link PM functions ------------------------*/
4302
4303/* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4304static unsigned long long xhci_service_interval_to_ns(
4305 struct usb_endpoint_descriptor *desc)
4306{
4307 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4308}
4309
4310static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4311 enum usb3_link_state state)
4312{
4313 unsigned long long sel;
4314 unsigned long long pel;
4315 unsigned int max_sel_pel;
4316 char *state_name;
4317
4318 switch (state) {
4319 case USB3_LPM_U1:
4320 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4321 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4322 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4323 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4324 state_name = "U1";
4325 break;
4326 case USB3_LPM_U2:
4327 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4328 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4329 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4330 state_name = "U2";
4331 break;
4332 default:
4333 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4334 __func__);
4335 return USB3_LPM_DISABLED;
4336 }
4337
4338 if (sel <= max_sel_pel && pel <= max_sel_pel)
4339 return USB3_LPM_DEVICE_INITIATED;
4340
4341 if (sel > max_sel_pel)
4342 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4343 "due to long SEL %llu ms\n",
4344 state_name, sel);
4345 else
4346 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4347 "due to long PEL %llu ms\n",
4348 state_name, pel);
4349 return USB3_LPM_DISABLED;
4350}
4351
4352/* The U1 timeout should be the maximum of the following values:
4353 * - For control endpoints, U1 system exit latency (SEL) * 3
4354 * - For bulk endpoints, U1 SEL * 5
4355 * - For interrupt endpoints:
4356 * - Notification EPs, U1 SEL * 3
4357 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4358 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4359 */
4360static unsigned long long xhci_calculate_intel_u1_timeout(
4361 struct usb_device *udev,
4362 struct usb_endpoint_descriptor *desc)
4363{
4364 unsigned long long timeout_ns;
4365 int ep_type;
4366 int intr_type;
4367
4368 ep_type = usb_endpoint_type(desc);
4369 switch (ep_type) {
4370 case USB_ENDPOINT_XFER_CONTROL:
4371 timeout_ns = udev->u1_params.sel * 3;
4372 break;
4373 case USB_ENDPOINT_XFER_BULK:
4374 timeout_ns = udev->u1_params.sel * 5;
4375 break;
4376 case USB_ENDPOINT_XFER_INT:
4377 intr_type = usb_endpoint_interrupt_type(desc);
4378 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4379 timeout_ns = udev->u1_params.sel * 3;
4380 break;
4381 }
4382 /* Otherwise the calculation is the same as isoc eps */
4383 case USB_ENDPOINT_XFER_ISOC:
4384 timeout_ns = xhci_service_interval_to_ns(desc);
4385 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4386 if (timeout_ns < udev->u1_params.sel * 2)
4387 timeout_ns = udev->u1_params.sel * 2;
4388 break;
4389 default:
4390 return 0;
4391 }
4392
4393 return timeout_ns;
4394}
4395
4396/* Returns the hub-encoded U1 timeout value. */
4397static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4398 struct usb_device *udev,
4399 struct usb_endpoint_descriptor *desc)
4400{
4401 unsigned long long timeout_ns;
4402
4403 if (xhci->quirks & XHCI_INTEL_HOST)
4404 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4405 else
4406 timeout_ns = udev->u1_params.sel;
4407
4408 /* The U1 timeout is encoded in 1us intervals.
4409 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4410 */
4411 if (timeout_ns == USB3_LPM_DISABLED)
4412 timeout_ns = 1;
4413 else
4414 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4415
4416 /* If the necessary timeout value is bigger than what we can set in the
4417 * USB 3.0 hub, we have to disable hub-initiated U1.
4418 */
4419 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4420 return timeout_ns;
4421 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4422 "due to long timeout %llu ms\n", timeout_ns);
4423 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4424}
4425
4426/* The U2 timeout should be the maximum of:
4427 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4428 * - largest bInterval of any active periodic endpoint (to avoid going
4429 * into lower power link states between intervals).
4430 * - the U2 Exit Latency of the device
4431 */
4432static unsigned long long xhci_calculate_intel_u2_timeout(
4433 struct usb_device *udev,
4434 struct usb_endpoint_descriptor *desc)
4435{
4436 unsigned long long timeout_ns;
4437 unsigned long long u2_del_ns;
4438
4439 timeout_ns = 10 * 1000 * 1000;
4440
4441 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4442 (xhci_service_interval_to_ns(desc) > timeout_ns))
4443 timeout_ns = xhci_service_interval_to_ns(desc);
4444
4445 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4446 if (u2_del_ns > timeout_ns)
4447 timeout_ns = u2_del_ns;
4448
4449 return timeout_ns;
4450}
4451
4452/* Returns the hub-encoded U2 timeout value. */
4453static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4454 struct usb_device *udev,
4455 struct usb_endpoint_descriptor *desc)
4456{
4457 unsigned long long timeout_ns;
4458
4459 if (xhci->quirks & XHCI_INTEL_HOST)
4460 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4461 else
4462 timeout_ns = udev->u2_params.sel;
4463
4464 /* The U2 timeout is encoded in 256us intervals */
4465 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4466 /* If the necessary timeout value is bigger than what we can set in the
4467 * USB 3.0 hub, we have to disable hub-initiated U2.
4468 */
4469 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4470 return timeout_ns;
4471 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4472 "due to long timeout %llu ms\n", timeout_ns);
4473 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4474}
4475
4476static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4477 struct usb_device *udev,
4478 struct usb_endpoint_descriptor *desc,
4479 enum usb3_link_state state,
4480 u16 *timeout)
4481{
4482 if (state == USB3_LPM_U1)
4483 return xhci_calculate_u1_timeout(xhci, udev, desc);
4484 else if (state == USB3_LPM_U2)
4485 return xhci_calculate_u2_timeout(xhci, udev, desc);
4486
4487 return USB3_LPM_DISABLED;
4488}
4489
4490static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4491 struct usb_device *udev,
4492 struct usb_endpoint_descriptor *desc,
4493 enum usb3_link_state state,
4494 u16 *timeout)
4495{
4496 u16 alt_timeout;
4497
4498 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4499 desc, state, timeout);
4500
4501 /* If we found we can't enable hub-initiated LPM, or
4502 * the U1 or U2 exit latency was too high to allow
4503 * device-initiated LPM as well, just stop searching.
4504 */
4505 if (alt_timeout == USB3_LPM_DISABLED ||
4506 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4507 *timeout = alt_timeout;
4508 return -E2BIG;
4509 }
4510 if (alt_timeout > *timeout)
4511 *timeout = alt_timeout;
4512 return 0;
4513}
4514
4515static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4516 struct usb_device *udev,
4517 struct usb_host_interface *alt,
4518 enum usb3_link_state state,
4519 u16 *timeout)
4520{
4521 int j;
4522
4523 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4524 if (xhci_update_timeout_for_endpoint(xhci, udev,
4525 &alt->endpoint[j].desc, state, timeout))
4526 return -E2BIG;
4527 continue;
4528 }
4529 return 0;
4530}
4531
4532static int xhci_check_intel_tier_policy(struct usb_device *udev,
4533 enum usb3_link_state state)
4534{
4535 struct usb_device *parent;
4536 unsigned int num_hubs;
4537
4538 if (state == USB3_LPM_U2)
4539 return 0;
4540
4541 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4542 for (parent = udev->parent, num_hubs = 0; parent->parent;
4543 parent = parent->parent)
4544 num_hubs++;
4545
4546 if (num_hubs < 2)
4547 return 0;
4548
4549 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4550 " below second-tier hub.\n");
4551 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4552 "to decrease power consumption.\n");
4553 return -E2BIG;
4554}
4555
4556static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4557 struct usb_device *udev,
4558 enum usb3_link_state state)
4559{
4560 if (xhci->quirks & XHCI_INTEL_HOST)
4561 return xhci_check_intel_tier_policy(udev, state);
4562 else
4563 return 0;
4564}
4565
4566/* Returns the U1 or U2 timeout that should be enabled.
4567 * If the tier check or timeout setting functions return with a non-zero exit
4568 * code, that means the timeout value has been finalized and we shouldn't look
4569 * at any more endpoints.
4570 */
4571static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4572 struct usb_device *udev, enum usb3_link_state state)
4573{
4574 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4575 struct usb_host_config *config;
4576 char *state_name;
4577 int i;
4578 u16 timeout = USB3_LPM_DISABLED;
4579
4580 if (state == USB3_LPM_U1)
4581 state_name = "U1";
4582 else if (state == USB3_LPM_U2)
4583 state_name = "U2";
4584 else {
4585 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4586 state);
4587 return timeout;
4588 }
4589
4590 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4591 return timeout;
4592
4593 /* Gather some information about the currently installed configuration
4594 * and alternate interface settings.
4595 */
4596 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4597 state, &timeout))
4598 return timeout;
4599
4600 config = udev->actconfig;
4601 if (!config)
4602 return timeout;
4603
4604 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4605 struct usb_driver *driver;
4606 struct usb_interface *intf = config->interface[i];
4607
4608 if (!intf)
4609 continue;
4610
4611 /* Check if any currently bound drivers want hub-initiated LPM
4612 * disabled.
4613 */
4614 if (intf->dev.driver) {
4615 driver = to_usb_driver(intf->dev.driver);
4616 if (driver && driver->disable_hub_initiated_lpm) {
4617 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4618 "at request of driver %s\n",
4619 state_name, driver->name);
4620 return xhci_get_timeout_no_hub_lpm(udev, state);
4621 }
4622 }
4623
4624 /* Not sure how this could happen... */
4625 if (!intf->cur_altsetting)
4626 continue;
4627
4628 if (xhci_update_timeout_for_interface(xhci, udev,
4629 intf->cur_altsetting,
4630 state, &timeout))
4631 return timeout;
4632 }
4633 return timeout;
4634}
4635
4636static int calculate_max_exit_latency(struct usb_device *udev,
4637 enum usb3_link_state state_changed,
4638 u16 hub_encoded_timeout)
4639{
4640 unsigned long long u1_mel_us = 0;
4641 unsigned long long u2_mel_us = 0;
4642 unsigned long long mel_us = 0;
4643 bool disabling_u1;
4644 bool disabling_u2;
4645 bool enabling_u1;
4646 bool enabling_u2;
4647
4648 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4649 hub_encoded_timeout == USB3_LPM_DISABLED);
4650 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4651 hub_encoded_timeout == USB3_LPM_DISABLED);
4652
4653 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4654 hub_encoded_timeout != USB3_LPM_DISABLED);
4655 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4656 hub_encoded_timeout != USB3_LPM_DISABLED);
4657
4658 /* If U1 was already enabled and we're not disabling it,
4659 * or we're going to enable U1, account for the U1 max exit latency.
4660 */
4661 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4662 enabling_u1)
4663 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4664 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4665 enabling_u2)
4666 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4667
4668 if (u1_mel_us > u2_mel_us)
4669 mel_us = u1_mel_us;
4670 else
4671 mel_us = u2_mel_us;
4672 /* xHCI host controller max exit latency field is only 16 bits wide. */
4673 if (mel_us > MAX_EXIT) {
4674 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4675 "is too big.\n", mel_us);
4676 return -E2BIG;
4677 }
4678 return mel_us;
4679}
4680
4681/* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4682int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4683 struct usb_device *udev, enum usb3_link_state state)
4684{
4685 struct xhci_hcd *xhci;
4686 u16 hub_encoded_timeout;
4687 int mel;
4688 int ret;
4689
4690 xhci = hcd_to_xhci(hcd);
4691 /* The LPM timeout values are pretty host-controller specific, so don't
4692 * enable hub-initiated timeouts unless the vendor has provided
4693 * information about their timeout algorithm.
4694 */
4695 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4696 !xhci->devs[udev->slot_id])
4697 return USB3_LPM_DISABLED;
4698
4699 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4700 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4701 if (mel < 0) {
4702 /* Max Exit Latency is too big, disable LPM. */
4703 hub_encoded_timeout = USB3_LPM_DISABLED;
4704 mel = 0;
4705 }
4706
4707 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4708 if (ret)
4709 return ret;
4710 return hub_encoded_timeout;
4711}
4712
4713int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4714 struct usb_device *udev, enum usb3_link_state state)
4715{
4716 struct xhci_hcd *xhci;
4717 u16 mel;
4718
4719 xhci = hcd_to_xhci(hcd);
4720 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4721 !xhci->devs[udev->slot_id])
4722 return 0;
4723
4724 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4725 return xhci_change_max_exit_latency(xhci, udev, mel);
4726}
4727#else /* CONFIG_PM */
4728
4729int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4730 struct usb_device *udev, int enable)
4731{
4732 return 0;
4733}
4734
4735int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4736{
4737 return 0;
4738}
4739
4740int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4741 struct usb_device *udev, enum usb3_link_state state)
4742{
4743 return USB3_LPM_DISABLED;
4744}
4745
4746int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4747 struct usb_device *udev, enum usb3_link_state state)
4748{
4749 return 0;
4750}
4751#endif /* CONFIG_PM */
4752
4753/*-------------------------------------------------------------------------*/
4754
4755/* Once a hub descriptor is fetched for a device, we need to update the xHC's
4756 * internal data structures for the device.
4757 */
4758int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4759 struct usb_tt *tt, gfp_t mem_flags)
4760{
4761 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4762 struct xhci_virt_device *vdev;
4763 struct xhci_command *config_cmd;
4764 struct xhci_input_control_ctx *ctrl_ctx;
4765 struct xhci_slot_ctx *slot_ctx;
4766 unsigned long flags;
4767 unsigned think_time;
4768 int ret;
4769
4770 /* Ignore root hubs */
4771 if (!hdev->parent)
4772 return 0;
4773
4774 vdev = xhci->devs[hdev->slot_id];
4775 if (!vdev) {
4776 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4777 return -EINVAL;
4778 }
4779 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4780 if (!config_cmd) {
4781 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4782 return -ENOMEM;
4783 }
4784 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4785 if (!ctrl_ctx) {
4786 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4787 __func__);
4788 xhci_free_command(xhci, config_cmd);
4789 return -ENOMEM;
4790 }
4791
4792 spin_lock_irqsave(&xhci->lock, flags);
4793 if (hdev->speed == USB_SPEED_HIGH &&
4794 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4795 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4796 xhci_free_command(xhci, config_cmd);
4797 spin_unlock_irqrestore(&xhci->lock, flags);
4798 return -ENOMEM;
4799 }
4800
4801 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4802 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4803 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4804 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4805 /*
4806 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4807 * but it may be already set to 1 when setup an xHCI virtual
4808 * device, so clear it anyway.
4809 */
4810 if (tt->multi)
4811 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4812 else if (hdev->speed == USB_SPEED_FULL)
4813 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4814
4815 if (xhci->hci_version > 0x95) {
4816 xhci_dbg(xhci, "xHCI version %x needs hub "
4817 "TT think time and number of ports\n",
4818 (unsigned int) xhci->hci_version);
4819 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4820 /* Set TT think time - convert from ns to FS bit times.
4821 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4822 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4823 *
4824 * xHCI 1.0: this field shall be 0 if the device is not a
4825 * High-spped hub.
4826 */
4827 think_time = tt->think_time;
4828 if (think_time != 0)
4829 think_time = (think_time / 666) - 1;
4830 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4831 slot_ctx->tt_info |=
4832 cpu_to_le32(TT_THINK_TIME(think_time));
4833 } else {
4834 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4835 "TT think time or number of ports\n",
4836 (unsigned int) xhci->hci_version);
4837 }
4838 slot_ctx->dev_state = 0;
4839 spin_unlock_irqrestore(&xhci->lock, flags);
4840
4841 xhci_dbg(xhci, "Set up %s for hub device.\n",
4842 (xhci->hci_version > 0x95) ?
4843 "configure endpoint" : "evaluate context");
4844 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4845 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4846
4847 /* Issue and wait for the configure endpoint or
4848 * evaluate context command.
4849 */
4850 if (xhci->hci_version > 0x95)
4851 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4852 false, false);
4853 else
4854 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4855 true, false);
4856
4857 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4858 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4859
4860 xhci_free_command(xhci, config_cmd);
4861 return ret;
4862}
4863
4864int xhci_get_frame(struct usb_hcd *hcd)
4865{
4866 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4867 /* EHCI mods by the periodic size. Why? */
4868 return readl(&xhci->run_regs->microframe_index) >> 3;
4869}
4870
4871int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4872{
4873 struct xhci_hcd *xhci;
4874 struct device *dev = hcd->self.controller;
4875 int retval;
4876
4877 /* Accept arbitrarily long scatter-gather lists */
4878 hcd->self.sg_tablesize = ~0;
4879
4880 /* support to build packet from discontinuous buffers */
4881 hcd->self.no_sg_constraint = 1;
4882
4883 /* XHCI controllers don't stop the ep queue on short packets :| */
4884 hcd->self.no_stop_on_short = 1;
4885
4886 xhci = hcd_to_xhci(hcd);
4887
4888 if (usb_hcd_is_primary_hcd(hcd)) {
4889 xhci->main_hcd = hcd;
4890 /* Mark the first roothub as being USB 2.0.
4891 * The xHCI driver will register the USB 3.0 roothub.
4892 */
4893 hcd->speed = HCD_USB2;
4894 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4895 /*
4896 * USB 2.0 roothub under xHCI has an integrated TT,
4897 * (rate matching hub) as opposed to having an OHCI/UHCI
4898 * companion controller.
4899 */
4900 hcd->has_tt = 1;
4901 } else {
4902 if (xhci->sbrn == 0x31) {
4903 xhci_info(xhci, "Host supports USB 3.1 Enhanced SuperSpeed\n");
4904 hcd->speed = HCD_USB31;
4905 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
4906 }
4907 /* xHCI private pointer was set in xhci_pci_probe for the second
4908 * registered roothub.
4909 */
4910 return 0;
4911 }
4912
4913 mutex_init(&xhci->mutex);
4914 xhci->cap_regs = hcd->regs;
4915 xhci->op_regs = hcd->regs +
4916 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
4917 xhci->run_regs = hcd->regs +
4918 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4919 /* Cache read-only capability registers */
4920 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
4921 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
4922 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
4923 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
4924 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4925 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
4926 if (xhci->hci_version > 0x100)
4927 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
4928 xhci_print_registers(xhci);
4929
4930 xhci->quirks = quirks;
4931
4932 get_quirks(dev, xhci);
4933
4934 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4935 * success event after a short transfer. This quirk will ignore such
4936 * spurious event.
4937 */
4938 if (xhci->hci_version > 0x96)
4939 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4940
4941 /* Make sure the HC is halted. */
4942 retval = xhci_halt(xhci);
4943 if (retval)
4944 return retval;
4945
4946 xhci_dbg(xhci, "Resetting HCD\n");
4947 /* Reset the internal HC memory state and registers. */
4948 retval = xhci_reset(xhci);
4949 if (retval)
4950 return retval;
4951 xhci_dbg(xhci, "Reset complete\n");
4952
4953 /*
4954 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
4955 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
4956 * address memory pointers actually. So, this driver clears the AC64
4957 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
4958 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
4959 */
4960 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
4961 xhci->hcc_params &= ~BIT(0);
4962
4963 /* Set dma_mask and coherent_dma_mask to 64-bits,
4964 * if xHC supports 64-bit addressing */
4965 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
4966 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
4967 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4968 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
4969 } else {
4970 /*
4971 * This is to avoid error in cases where a 32-bit USB
4972 * controller is used on a 64-bit capable system.
4973 */
4974 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
4975 if (retval)
4976 return retval;
4977 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
4978 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
4979 }
4980
4981 xhci_dbg(xhci, "Calling HCD init\n");
4982 /* Initialize HCD and host controller data structures. */
4983 retval = xhci_init(hcd);
4984 if (retval)
4985 return retval;
4986 xhci_dbg(xhci, "Called HCD init\n");
4987
4988 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n",
4989 xhci->hcc_params, xhci->hci_version, xhci->quirks);
4990
4991 return 0;
4992}
4993EXPORT_SYMBOL_GPL(xhci_gen_setup);
4994
4995static const struct hc_driver xhci_hc_driver = {
4996 .description = "xhci-hcd",
4997 .product_desc = "xHCI Host Controller",
4998 .hcd_priv_size = sizeof(struct xhci_hcd),
4999
5000 /*
5001 * generic hardware linkage
5002 */
5003 .irq = xhci_irq,
5004 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
5005
5006 /*
5007 * basic lifecycle operations
5008 */
5009 .reset = NULL, /* set in xhci_init_driver() */
5010 .start = xhci_run,
5011 .stop = xhci_stop,
5012 .shutdown = xhci_shutdown,
5013
5014 /*
5015 * managing i/o requests and associated device resources
5016 */
5017 .urb_enqueue = xhci_urb_enqueue,
5018 .urb_dequeue = xhci_urb_dequeue,
5019 .alloc_dev = xhci_alloc_dev,
5020 .free_dev = xhci_free_dev,
5021 .alloc_streams = xhci_alloc_streams,
5022 .free_streams = xhci_free_streams,
5023 .add_endpoint = xhci_add_endpoint,
5024 .drop_endpoint = xhci_drop_endpoint,
5025 .endpoint_reset = xhci_endpoint_reset,
5026 .check_bandwidth = xhci_check_bandwidth,
5027 .reset_bandwidth = xhci_reset_bandwidth,
5028 .address_device = xhci_address_device,
5029 .enable_device = xhci_enable_device,
5030 .update_hub_device = xhci_update_hub_device,
5031 .reset_device = xhci_discover_or_reset_device,
5032
5033 /*
5034 * scheduling support
5035 */
5036 .get_frame_number = xhci_get_frame,
5037
5038 /*
5039 * root hub support
5040 */
5041 .hub_control = xhci_hub_control,
5042 .hub_status_data = xhci_hub_status_data,
5043 .bus_suspend = xhci_bus_suspend,
5044 .bus_resume = xhci_bus_resume,
5045
5046 /*
5047 * call back when device connected and addressed
5048 */
5049 .update_device = xhci_update_device,
5050 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5051 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5052 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5053 .find_raw_port_number = xhci_find_raw_port_number,
5054};
5055
5056void xhci_init_driver(struct hc_driver *drv,
5057 const struct xhci_driver_overrides *over)
5058{
5059 BUG_ON(!over);
5060
5061 /* Copy the generic table to drv then apply the overrides */
5062 *drv = xhci_hc_driver;
5063
5064 if (over) {
5065 drv->hcd_priv_size += over->extra_priv_size;
5066 if (over->reset)
5067 drv->reset = over->reset;
5068 if (over->start)
5069 drv->start = over->start;
5070 }
5071}
5072EXPORT_SYMBOL_GPL(xhci_init_driver);
5073
5074MODULE_DESCRIPTION(DRIVER_DESC);
5075MODULE_AUTHOR(DRIVER_AUTHOR);
5076MODULE_LICENSE("GPL");
5077
5078static int __init xhci_hcd_init(void)
5079{
5080 /*
5081 * Check the compiler generated sizes of structures that must be laid
5082 * out in specific ways for hardware access.
5083 */
5084 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5085 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5086 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5087 /* xhci_device_control has eight fields, and also
5088 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5089 */
5090 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5091 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5092 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5093 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5094 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5095 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5096 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5097
5098 if (usb_disabled())
5099 return -ENODEV;
5100
5101 return 0;
5102}
5103
5104/*
5105 * If an init function is provided, an exit function must also be provided
5106 * to allow module unload.
5107 */
5108static void __exit xhci_hcd_fini(void) { }
5109
5110module_init(xhci_hcd_init);
5111module_exit(xhci_hcd_fini);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11#include <linux/jiffies.h>
12#include <linux/pci.h>
13#include <linux/iommu.h>
14#include <linux/iopoll.h>
15#include <linux/irq.h>
16#include <linux/log2.h>
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/slab.h>
20#include <linux/dmi.h>
21#include <linux/dma-mapping.h>
22
23#include "xhci.h"
24#include "xhci-trace.h"
25#include "xhci-debugfs.h"
26#include "xhci-dbgcap.h"
27
28#define DRIVER_AUTHOR "Sarah Sharp"
29#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
30
31#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
32
33/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
34static int link_quirk;
35module_param(link_quirk, int, S_IRUGO | S_IWUSR);
36MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
37
38static unsigned long long quirks;
39module_param(quirks, ullong, S_IRUGO);
40MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
41
42static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
43{
44 struct xhci_segment *seg;
45
46 if (!td || !td->start_seg)
47 return false;
48
49 xhci_for_each_ring_seg(ring->first_seg, seg) {
50 if (seg == td->start_seg)
51 return true;
52 }
53
54 return false;
55}
56
57/*
58 * xhci_handshake - spin reading hc until handshake completes or fails
59 * @ptr: address of hc register to be read
60 * @mask: bits to look at in result of read
61 * @done: value of those bits when handshake succeeds
62 * @usec: timeout in microseconds
63 *
64 * Returns negative errno, or zero on success
65 *
66 * Success happens when the "mask" bits have the specified value (hardware
67 * handshake done). There are two failure modes: "usec" have passed (major
68 * hardware flakeout), or the register reads as all-ones (hardware removed).
69 */
70int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
71{
72 u32 result;
73 int ret;
74
75 ret = readl_poll_timeout_atomic(ptr, result,
76 (result & mask) == done ||
77 result == U32_MAX,
78 1, timeout_us);
79 if (result == U32_MAX) /* card removed */
80 return -ENODEV;
81
82 return ret;
83}
84
85/*
86 * xhci_handshake_check_state - same as xhci_handshake but takes an additional
87 * exit_state parameter, and bails out with an error immediately when xhc_state
88 * has exit_state flag set.
89 */
90int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr,
91 u32 mask, u32 done, int usec, unsigned int exit_state)
92{
93 u32 result;
94 int ret;
95
96 ret = readl_poll_timeout_atomic(ptr, result,
97 (result & mask) == done ||
98 result == U32_MAX ||
99 xhci->xhc_state & exit_state,
100 1, usec);
101
102 if (result == U32_MAX || xhci->xhc_state & exit_state)
103 return -ENODEV;
104
105 return ret;
106}
107
108/*
109 * Disable interrupts and begin the xHCI halting process.
110 */
111void xhci_quiesce(struct xhci_hcd *xhci)
112{
113 u32 halted;
114 u32 cmd;
115 u32 mask;
116
117 mask = ~(XHCI_IRQS);
118 halted = readl(&xhci->op_regs->status) & STS_HALT;
119 if (!halted)
120 mask &= ~CMD_RUN;
121
122 cmd = readl(&xhci->op_regs->command);
123 cmd &= mask;
124 writel(cmd, &xhci->op_regs->command);
125}
126
127/*
128 * Force HC into halt state.
129 *
130 * Disable any IRQs and clear the run/stop bit.
131 * HC will complete any current and actively pipelined transactions, and
132 * should halt within 16 ms of the run/stop bit being cleared.
133 * Read HC Halted bit in the status register to see when the HC is finished.
134 */
135int xhci_halt(struct xhci_hcd *xhci)
136{
137 int ret;
138
139 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
140 xhci_quiesce(xhci);
141
142 ret = xhci_handshake(&xhci->op_regs->status,
143 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
144 if (ret) {
145 xhci_warn(xhci, "Host halt failed, %d\n", ret);
146 return ret;
147 }
148
149 xhci->xhc_state |= XHCI_STATE_HALTED;
150 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
151
152 return ret;
153}
154
155/*
156 * Set the run bit and wait for the host to be running.
157 */
158int xhci_start(struct xhci_hcd *xhci)
159{
160 u32 temp;
161 int ret;
162
163 temp = readl(&xhci->op_regs->command);
164 temp |= (CMD_RUN);
165 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
166 temp);
167 writel(temp, &xhci->op_regs->command);
168
169 /*
170 * Wait for the HCHalted Status bit to be 0 to indicate the host is
171 * running.
172 */
173 ret = xhci_handshake(&xhci->op_regs->status,
174 STS_HALT, 0, XHCI_MAX_HALT_USEC);
175 if (ret == -ETIMEDOUT)
176 xhci_err(xhci, "Host took too long to start, "
177 "waited %u microseconds.\n",
178 XHCI_MAX_HALT_USEC);
179 if (!ret) {
180 /* clear state flags. Including dying, halted or removing */
181 xhci->xhc_state = 0;
182 xhci->run_graceperiod = jiffies + msecs_to_jiffies(500);
183 }
184
185 return ret;
186}
187
188/*
189 * Reset a halted HC.
190 *
191 * This resets pipelines, timers, counters, state machines, etc.
192 * Transactions will be terminated immediately, and operational registers
193 * will be set to their defaults.
194 */
195int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
196{
197 u32 command;
198 u32 state;
199 int ret;
200
201 state = readl(&xhci->op_regs->status);
202
203 if (state == ~(u32)0) {
204 xhci_warn(xhci, "Host not accessible, reset failed.\n");
205 return -ENODEV;
206 }
207
208 if ((state & STS_HALT) == 0) {
209 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
210 return 0;
211 }
212
213 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
214 command = readl(&xhci->op_regs->command);
215 command |= CMD_RESET;
216 writel(command, &xhci->op_regs->command);
217
218 /* Existing Intel xHCI controllers require a delay of 1 mS,
219 * after setting the CMD_RESET bit, and before accessing any
220 * HC registers. This allows the HC to complete the
221 * reset operation and be ready for HC register access.
222 * Without this delay, the subsequent HC register access,
223 * may result in a system hang very rarely.
224 */
225 if (xhci->quirks & XHCI_INTEL_HOST)
226 udelay(1000);
227
228 ret = xhci_handshake_check_state(xhci, &xhci->op_regs->command,
229 CMD_RESET, 0, timeout_us, XHCI_STATE_REMOVING);
230 if (ret)
231 return ret;
232
233 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
234 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
235
236 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
237 "Wait for controller to be ready for doorbell rings");
238 /*
239 * xHCI cannot write to any doorbells or operational registers other
240 * than status until the "Controller Not Ready" flag is cleared.
241 */
242 ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
243
244 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
245 xhci->usb2_rhub.bus_state.suspended_ports = 0;
246 xhci->usb2_rhub.bus_state.resuming_ports = 0;
247 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
248 xhci->usb3_rhub.bus_state.suspended_ports = 0;
249 xhci->usb3_rhub.bus_state.resuming_ports = 0;
250
251 return ret;
252}
253
254static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
255{
256 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
257 struct iommu_domain *domain;
258 int err, i;
259 u64 val;
260 u32 intrs;
261
262 /*
263 * Some Renesas controllers get into a weird state if they are
264 * reset while programmed with 64bit addresses (they will preserve
265 * the top half of the address in internal, non visible
266 * registers). You end up with half the address coming from the
267 * kernel, and the other half coming from the firmware. Also,
268 * changing the programming leads to extra accesses even if the
269 * controller is supposed to be halted. The controller ends up with
270 * a fatal fault, and is then ripe for being properly reset.
271 *
272 * Special care is taken to only apply this if the device is behind
273 * an iommu. Doing anything when there is no iommu is definitely
274 * unsafe...
275 */
276 domain = iommu_get_domain_for_dev(dev);
277 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !domain ||
278 domain->type == IOMMU_DOMAIN_IDENTITY)
279 return;
280
281 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
282
283 /* Clear HSEIE so that faults do not get signaled */
284 val = readl(&xhci->op_regs->command);
285 val &= ~CMD_HSEIE;
286 writel(val, &xhci->op_regs->command);
287
288 /* Clear HSE (aka FATAL) */
289 val = readl(&xhci->op_regs->status);
290 val |= STS_FATAL;
291 writel(val, &xhci->op_regs->status);
292
293 /* Now zero the registers, and brace for impact */
294 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
295 if (upper_32_bits(val))
296 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
297 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
298 if (upper_32_bits(val))
299 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
300
301 intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
302 ARRAY_SIZE(xhci->run_regs->ir_set));
303
304 for (i = 0; i < intrs; i++) {
305 struct xhci_intr_reg __iomem *ir;
306
307 ir = &xhci->run_regs->ir_set[i];
308 val = xhci_read_64(xhci, &ir->erst_base);
309 if (upper_32_bits(val))
310 xhci_write_64(xhci, 0, &ir->erst_base);
311 val= xhci_read_64(xhci, &ir->erst_dequeue);
312 if (upper_32_bits(val))
313 xhci_write_64(xhci, 0, &ir->erst_dequeue);
314 }
315
316 /* Wait for the fault to appear. It will be cleared on reset */
317 err = xhci_handshake(&xhci->op_regs->status,
318 STS_FATAL, STS_FATAL,
319 XHCI_MAX_HALT_USEC);
320 if (!err)
321 xhci_info(xhci, "Fault detected\n");
322}
323
324static int xhci_enable_interrupter(struct xhci_interrupter *ir)
325{
326 u32 iman;
327
328 if (!ir || !ir->ir_set)
329 return -EINVAL;
330
331 iman = readl(&ir->ir_set->irq_pending);
332 writel(ER_IRQ_ENABLE(iman), &ir->ir_set->irq_pending);
333
334 return 0;
335}
336
337static int xhci_disable_interrupter(struct xhci_interrupter *ir)
338{
339 u32 iman;
340
341 if (!ir || !ir->ir_set)
342 return -EINVAL;
343
344 iman = readl(&ir->ir_set->irq_pending);
345 writel(ER_IRQ_DISABLE(iman), &ir->ir_set->irq_pending);
346
347 return 0;
348}
349
350/* interrupt moderation interval imod_interval in nanoseconds */
351int xhci_set_interrupter_moderation(struct xhci_interrupter *ir,
352 u32 imod_interval)
353{
354 u32 imod;
355
356 if (!ir || !ir->ir_set || imod_interval > U16_MAX * 250)
357 return -EINVAL;
358
359 imod = readl(&ir->ir_set->irq_control);
360 imod &= ~ER_IRQ_INTERVAL_MASK;
361 imod |= (imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
362 writel(imod, &ir->ir_set->irq_control);
363
364 return 0;
365}
366
367static void compliance_mode_recovery(struct timer_list *t)
368{
369 struct xhci_hcd *xhci;
370 struct usb_hcd *hcd;
371 struct xhci_hub *rhub;
372 u32 temp;
373 int i;
374
375 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
376 rhub = &xhci->usb3_rhub;
377 hcd = rhub->hcd;
378
379 if (!hcd)
380 return;
381
382 for (i = 0; i < rhub->num_ports; i++) {
383 temp = readl(rhub->ports[i]->addr);
384 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
385 /*
386 * Compliance Mode Detected. Letting USB Core
387 * handle the Warm Reset
388 */
389 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
390 "Compliance mode detected->port %d",
391 i + 1);
392 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
393 "Attempting compliance mode recovery");
394
395 if (hcd->state == HC_STATE_SUSPENDED)
396 usb_hcd_resume_root_hub(hcd);
397
398 usb_hcd_poll_rh_status(hcd);
399 }
400 }
401
402 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
403 mod_timer(&xhci->comp_mode_recovery_timer,
404 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
405}
406
407/*
408 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
409 * that causes ports behind that hardware to enter compliance mode sometimes.
410 * The quirk creates a timer that polls every 2 seconds the link state of
411 * each host controller's port and recovers it by issuing a Warm reset
412 * if Compliance mode is detected, otherwise the port will become "dead" (no
413 * device connections or disconnections will be detected anymore). Becasue no
414 * status event is generated when entering compliance mode (per xhci spec),
415 * this quirk is needed on systems that have the failing hardware installed.
416 */
417static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
418{
419 xhci->port_status_u0 = 0;
420 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
421 0);
422 xhci->comp_mode_recovery_timer.expires = jiffies +
423 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
424
425 add_timer(&xhci->comp_mode_recovery_timer);
426 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
427 "Compliance mode recovery timer initialized");
428}
429
430/*
431 * This function identifies the systems that have installed the SN65LVPE502CP
432 * USB3.0 re-driver and that need the Compliance Mode Quirk.
433 * Systems:
434 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
435 */
436static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
437{
438 const char *dmi_product_name, *dmi_sys_vendor;
439
440 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
441 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
442 if (!dmi_product_name || !dmi_sys_vendor)
443 return false;
444
445 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
446 return false;
447
448 if (strstr(dmi_product_name, "Z420") ||
449 strstr(dmi_product_name, "Z620") ||
450 strstr(dmi_product_name, "Z820") ||
451 strstr(dmi_product_name, "Z1 Workstation"))
452 return true;
453
454 return false;
455}
456
457static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
458{
459 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
460}
461
462
463/*
464 * Initialize memory for HCD and xHC (one-time init).
465 *
466 * Program the PAGESIZE register, initialize the device context array, create
467 * device contexts (?), set up a command ring segment (or two?), create event
468 * ring (one for now).
469 */
470static int xhci_init(struct usb_hcd *hcd)
471{
472 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
473 int retval;
474
475 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
476 spin_lock_init(&xhci->lock);
477
478 retval = xhci_mem_init(xhci, GFP_KERNEL);
479 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
480
481 /* Initializing Compliance Mode Recovery Data If Needed */
482 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
483 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
484 compliance_mode_recovery_timer_init(xhci);
485 }
486
487 return retval;
488}
489
490/*-------------------------------------------------------------------------*/
491
492static int xhci_run_finished(struct xhci_hcd *xhci)
493{
494 struct xhci_interrupter *ir = xhci->interrupters[0];
495 unsigned long flags;
496 u32 temp;
497
498 /*
499 * Enable interrupts before starting the host (xhci 4.2 and 5.5.2).
500 * Protect the short window before host is running with a lock
501 */
502 spin_lock_irqsave(&xhci->lock, flags);
503
504 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable interrupts");
505 temp = readl(&xhci->op_regs->command);
506 temp |= (CMD_EIE);
507 writel(temp, &xhci->op_regs->command);
508
509 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable primary interrupter");
510 xhci_enable_interrupter(ir);
511
512 if (xhci_start(xhci)) {
513 xhci_halt(xhci);
514 spin_unlock_irqrestore(&xhci->lock, flags);
515 return -ENODEV;
516 }
517
518 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
519
520 if (xhci->quirks & XHCI_NEC_HOST)
521 xhci_ring_cmd_db(xhci);
522
523 spin_unlock_irqrestore(&xhci->lock, flags);
524
525 return 0;
526}
527
528/*
529 * Start the HC after it was halted.
530 *
531 * This function is called by the USB core when the HC driver is added.
532 * Its opposite is xhci_stop().
533 *
534 * xhci_init() must be called once before this function can be called.
535 * Reset the HC, enable device slot contexts, program DCBAAP, and
536 * set command ring pointer and event ring pointer.
537 *
538 * Setup MSI-X vectors and enable interrupts.
539 */
540int xhci_run(struct usb_hcd *hcd)
541{
542 u64 temp_64;
543 int ret;
544 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
545 struct xhci_interrupter *ir = xhci->interrupters[0];
546 /* Start the xHCI host controller running only after the USB 2.0 roothub
547 * is setup.
548 */
549
550 hcd->uses_new_polling = 1;
551 if (hcd->msi_enabled)
552 ir->ip_autoclear = true;
553
554 if (!usb_hcd_is_primary_hcd(hcd))
555 return xhci_run_finished(xhci);
556
557 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
558
559 temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
560 temp_64 &= ERST_PTR_MASK;
561 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
562 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
563
564 xhci_set_interrupter_moderation(ir, xhci->imod_interval);
565
566 if (xhci->quirks & XHCI_NEC_HOST) {
567 struct xhci_command *command;
568
569 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
570 if (!command)
571 return -ENOMEM;
572
573 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
574 TRB_TYPE(TRB_NEC_GET_FW));
575 if (ret)
576 xhci_free_command(xhci, command);
577 }
578 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
579 "Finished %s for main hcd", __func__);
580
581 xhci_create_dbc_dev(xhci);
582
583 xhci_debugfs_init(xhci);
584
585 if (xhci_has_one_roothub(xhci))
586 return xhci_run_finished(xhci);
587
588 set_bit(HCD_FLAG_DEFER_RH_REGISTER, &hcd->flags);
589
590 return 0;
591}
592EXPORT_SYMBOL_GPL(xhci_run);
593
594/*
595 * Stop xHCI driver.
596 *
597 * This function is called by the USB core when the HC driver is removed.
598 * Its opposite is xhci_run().
599 *
600 * Disable device contexts, disable IRQs, and quiesce the HC.
601 * Reset the HC, finish any completed transactions, and cleanup memory.
602 */
603void xhci_stop(struct usb_hcd *hcd)
604{
605 u32 temp;
606 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
607 struct xhci_interrupter *ir = xhci->interrupters[0];
608
609 mutex_lock(&xhci->mutex);
610
611 /* Only halt host and free memory after both hcds are removed */
612 if (!usb_hcd_is_primary_hcd(hcd)) {
613 mutex_unlock(&xhci->mutex);
614 return;
615 }
616
617 xhci_remove_dbc_dev(xhci);
618
619 spin_lock_irq(&xhci->lock);
620 xhci->xhc_state |= XHCI_STATE_HALTED;
621 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
622 xhci_halt(xhci);
623 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
624 spin_unlock_irq(&xhci->lock);
625
626 /* Deleting Compliance Mode Recovery Timer */
627 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
628 (!(xhci_all_ports_seen_u0(xhci)))) {
629 del_timer_sync(&xhci->comp_mode_recovery_timer);
630 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
631 "%s: compliance mode recovery timer deleted",
632 __func__);
633 }
634
635 if (xhci->quirks & XHCI_AMD_PLL_FIX)
636 usb_amd_dev_put();
637
638 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
639 "// Disabling event ring interrupts");
640 temp = readl(&xhci->op_regs->status);
641 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
642 xhci_disable_interrupter(ir);
643
644 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
645 xhci_mem_cleanup(xhci);
646 xhci_debugfs_exit(xhci);
647 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
648 "xhci_stop completed - status = %x",
649 readl(&xhci->op_regs->status));
650 mutex_unlock(&xhci->mutex);
651}
652EXPORT_SYMBOL_GPL(xhci_stop);
653
654/*
655 * Shutdown HC (not bus-specific)
656 *
657 * This is called when the machine is rebooting or halting. We assume that the
658 * machine will be powered off, and the HC's internal state will be reset.
659 * Don't bother to free memory.
660 *
661 * This will only ever be called with the main usb_hcd (the USB3 roothub).
662 */
663void xhci_shutdown(struct usb_hcd *hcd)
664{
665 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
666
667 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
668 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
669
670 /* Don't poll the roothubs after shutdown. */
671 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
672 __func__, hcd->self.busnum);
673 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
674 del_timer_sync(&hcd->rh_timer);
675
676 if (xhci->shared_hcd) {
677 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
678 del_timer_sync(&xhci->shared_hcd->rh_timer);
679 }
680
681 spin_lock_irq(&xhci->lock);
682 xhci_halt(xhci);
683
684 /*
685 * Workaround for spurious wakeps at shutdown with HSW, and for boot
686 * firmware delay in ADL-P PCH if port are left in U3 at shutdown
687 */
688 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP ||
689 xhci->quirks & XHCI_RESET_TO_DEFAULT)
690 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
691
692 spin_unlock_irq(&xhci->lock);
693
694 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
695 "xhci_shutdown completed - status = %x",
696 readl(&xhci->op_regs->status));
697}
698EXPORT_SYMBOL_GPL(xhci_shutdown);
699
700#ifdef CONFIG_PM
701static void xhci_save_registers(struct xhci_hcd *xhci)
702{
703 struct xhci_interrupter *ir;
704 unsigned int i;
705
706 xhci->s3.command = readl(&xhci->op_regs->command);
707 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
708 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
709 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
710
711 /* save both primary and all secondary interrupters */
712 /* fixme, shold we lock to prevent race with remove secondary interrupter? */
713 for (i = 0; i < xhci->max_interrupters; i++) {
714 ir = xhci->interrupters[i];
715 if (!ir)
716 continue;
717
718 ir->s3_erst_size = readl(&ir->ir_set->erst_size);
719 ir->s3_erst_base = xhci_read_64(xhci, &ir->ir_set->erst_base);
720 ir->s3_erst_dequeue = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
721 ir->s3_irq_pending = readl(&ir->ir_set->irq_pending);
722 ir->s3_irq_control = readl(&ir->ir_set->irq_control);
723 }
724}
725
726static void xhci_restore_registers(struct xhci_hcd *xhci)
727{
728 struct xhci_interrupter *ir;
729 unsigned int i;
730
731 writel(xhci->s3.command, &xhci->op_regs->command);
732 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
733 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
734 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
735
736 /* FIXME should we lock to protect against freeing of interrupters */
737 for (i = 0; i < xhci->max_interrupters; i++) {
738 ir = xhci->interrupters[i];
739 if (!ir)
740 continue;
741
742 writel(ir->s3_erst_size, &ir->ir_set->erst_size);
743 xhci_write_64(xhci, ir->s3_erst_base, &ir->ir_set->erst_base);
744 xhci_write_64(xhci, ir->s3_erst_dequeue, &ir->ir_set->erst_dequeue);
745 writel(ir->s3_irq_pending, &ir->ir_set->irq_pending);
746 writel(ir->s3_irq_control, &ir->ir_set->irq_control);
747 }
748}
749
750static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
751{
752 u64 val_64;
753
754 /* step 2: initialize command ring buffer */
755 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
756 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
757 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
758 xhci->cmd_ring->dequeue) &
759 (u64) ~CMD_RING_RSVD_BITS) |
760 xhci->cmd_ring->cycle_state;
761 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
762 "// Setting command ring address to 0x%llx",
763 (long unsigned long) val_64);
764 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
765}
766
767/*
768 * The whole command ring must be cleared to zero when we suspend the host.
769 *
770 * The host doesn't save the command ring pointer in the suspend well, so we
771 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
772 * aligned, because of the reserved bits in the command ring dequeue pointer
773 * register. Therefore, we can't just set the dequeue pointer back in the
774 * middle of the ring (TRBs are 16-byte aligned).
775 */
776static void xhci_clear_command_ring(struct xhci_hcd *xhci)
777{
778 struct xhci_ring *ring;
779 struct xhci_segment *seg;
780
781 ring = xhci->cmd_ring;
782 xhci_for_each_ring_seg(ring->first_seg, seg) {
783 /* erase all TRBs before the link */
784 memset(seg->trbs, 0, sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
785 /* clear link cycle bit */
786 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &= cpu_to_le32(~TRB_CYCLE);
787 }
788
789 xhci_initialize_ring_info(ring);
790 /*
791 * Reset the hardware dequeue pointer.
792 * Yes, this will need to be re-written after resume, but we're paranoid
793 * and want to make sure the hardware doesn't access bogus memory
794 * because, say, the BIOS or an SMI started the host without changing
795 * the command ring pointers.
796 */
797 xhci_set_cmd_ring_deq(xhci);
798}
799
800/*
801 * Disable port wake bits if do_wakeup is not set.
802 *
803 * Also clear a possible internal port wake state left hanging for ports that
804 * detected termination but never successfully enumerated (trained to 0U).
805 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
806 * at enumeration clears this wake, force one here as well for unconnected ports
807 */
808
809static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
810 struct xhci_hub *rhub,
811 bool do_wakeup)
812{
813 unsigned long flags;
814 u32 t1, t2, portsc;
815 int i;
816
817 spin_lock_irqsave(&xhci->lock, flags);
818
819 for (i = 0; i < rhub->num_ports; i++) {
820 portsc = readl(rhub->ports[i]->addr);
821 t1 = xhci_port_state_to_neutral(portsc);
822 t2 = t1;
823
824 /* clear wake bits if do_wake is not set */
825 if (!do_wakeup)
826 t2 &= ~PORT_WAKE_BITS;
827
828 /* Don't touch csc bit if connected or connect change is set */
829 if (!(portsc & (PORT_CSC | PORT_CONNECT)))
830 t2 |= PORT_CSC;
831
832 if (t1 != t2) {
833 writel(t2, rhub->ports[i]->addr);
834 xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
835 rhub->hcd->self.busnum, i + 1, portsc, t2);
836 }
837 }
838 spin_unlock_irqrestore(&xhci->lock, flags);
839}
840
841static bool xhci_pending_portevent(struct xhci_hcd *xhci)
842{
843 struct xhci_port **ports;
844 int port_index;
845 u32 status;
846 u32 portsc;
847
848 status = readl(&xhci->op_regs->status);
849 if (status & STS_EINT)
850 return true;
851 /*
852 * Checking STS_EINT is not enough as there is a lag between a change
853 * bit being set and the Port Status Change Event that it generated
854 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
855 */
856
857 port_index = xhci->usb2_rhub.num_ports;
858 ports = xhci->usb2_rhub.ports;
859 while (port_index--) {
860 portsc = readl(ports[port_index]->addr);
861 if (portsc & PORT_CHANGE_MASK ||
862 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
863 return true;
864 }
865 port_index = xhci->usb3_rhub.num_ports;
866 ports = xhci->usb3_rhub.ports;
867 while (port_index--) {
868 portsc = readl(ports[port_index]->addr);
869 if (portsc & (PORT_CHANGE_MASK | PORT_CAS) ||
870 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
871 return true;
872 }
873 return false;
874}
875
876/*
877 * Stop HC (not bus-specific)
878 *
879 * This is called when the machine transition into S3/S4 mode.
880 *
881 */
882int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
883{
884 int rc = 0;
885 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
886 struct usb_hcd *hcd = xhci_to_hcd(xhci);
887 u32 command;
888 u32 res;
889
890 if (!hcd->state)
891 return 0;
892
893 if (hcd->state != HC_STATE_SUSPENDED ||
894 (xhci->shared_hcd && xhci->shared_hcd->state != HC_STATE_SUSPENDED))
895 return -EINVAL;
896
897 /* Clear root port wake on bits if wakeup not allowed. */
898 xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
899 xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
900
901 if (!HCD_HW_ACCESSIBLE(hcd))
902 return 0;
903
904 xhci_dbc_suspend(xhci);
905
906 /* Don't poll the roothubs on bus suspend. */
907 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
908 __func__, hcd->self.busnum);
909 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
910 del_timer_sync(&hcd->rh_timer);
911 if (xhci->shared_hcd) {
912 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
913 del_timer_sync(&xhci->shared_hcd->rh_timer);
914 }
915
916 if (xhci->quirks & XHCI_SUSPEND_DELAY)
917 usleep_range(1000, 1500);
918
919 spin_lock_irq(&xhci->lock);
920 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
921 if (xhci->shared_hcd)
922 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
923 /* step 1: stop endpoint */
924 /* skipped assuming that port suspend has done */
925
926 /* step 2: clear Run/Stop bit */
927 command = readl(&xhci->op_regs->command);
928 command &= ~CMD_RUN;
929 writel(command, &xhci->op_regs->command);
930
931 /* Some chips from Fresco Logic need an extraordinary delay */
932 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
933
934 if (xhci_handshake(&xhci->op_regs->status,
935 STS_HALT, STS_HALT, delay)) {
936 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
937 spin_unlock_irq(&xhci->lock);
938 return -ETIMEDOUT;
939 }
940 xhci_clear_command_ring(xhci);
941
942 /* step 3: save registers */
943 xhci_save_registers(xhci);
944
945 /* step 4: set CSS flag */
946 command = readl(&xhci->op_regs->command);
947 command |= CMD_CSS;
948 writel(command, &xhci->op_regs->command);
949 xhci->broken_suspend = 0;
950 if (xhci_handshake(&xhci->op_regs->status,
951 STS_SAVE, 0, 20 * 1000)) {
952 /*
953 * AMD SNPS xHC 3.0 occasionally does not clear the
954 * SSS bit of USBSTS and when driver tries to poll
955 * to see if the xHC clears BIT(8) which never happens
956 * and driver assumes that controller is not responding
957 * and times out. To workaround this, its good to check
958 * if SRE and HCE bits are not set (as per xhci
959 * Section 5.4.2) and bypass the timeout.
960 */
961 res = readl(&xhci->op_regs->status);
962 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
963 (((res & STS_SRE) == 0) &&
964 ((res & STS_HCE) == 0))) {
965 xhci->broken_suspend = 1;
966 } else {
967 xhci_warn(xhci, "WARN: xHC save state timeout\n");
968 spin_unlock_irq(&xhci->lock);
969 return -ETIMEDOUT;
970 }
971 }
972 spin_unlock_irq(&xhci->lock);
973
974 /*
975 * Deleting Compliance Mode Recovery Timer because the xHCI Host
976 * is about to be suspended.
977 */
978 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
979 (!(xhci_all_ports_seen_u0(xhci)))) {
980 del_timer_sync(&xhci->comp_mode_recovery_timer);
981 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
982 "%s: compliance mode recovery timer deleted",
983 __func__);
984 }
985
986 return rc;
987}
988EXPORT_SYMBOL_GPL(xhci_suspend);
989
990/*
991 * start xHC (not bus-specific)
992 *
993 * This is called when the machine transition from S3/S4 mode.
994 *
995 */
996int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg)
997{
998 bool hibernated = (msg.event == PM_EVENT_RESTORE);
999 u32 command, temp = 0;
1000 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1001 int retval = 0;
1002 bool comp_timer_running = false;
1003 bool pending_portevent = false;
1004 bool suspended_usb3_devs = false;
1005 bool reinit_xhc = false;
1006
1007 if (!hcd->state)
1008 return 0;
1009
1010 /* Wait a bit if either of the roothubs need to settle from the
1011 * transition into bus suspend.
1012 */
1013
1014 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1015 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1016 msleep(100);
1017
1018 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1019 if (xhci->shared_hcd)
1020 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1021
1022 spin_lock_irq(&xhci->lock);
1023
1024 if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1025 reinit_xhc = true;
1026
1027 if (!reinit_xhc) {
1028 /*
1029 * Some controllers might lose power during suspend, so wait
1030 * for controller not ready bit to clear, just as in xHC init.
1031 */
1032 retval = xhci_handshake(&xhci->op_regs->status,
1033 STS_CNR, 0, 10 * 1000 * 1000);
1034 if (retval) {
1035 xhci_warn(xhci, "Controller not ready at resume %d\n",
1036 retval);
1037 spin_unlock_irq(&xhci->lock);
1038 return retval;
1039 }
1040 /* step 1: restore register */
1041 xhci_restore_registers(xhci);
1042 /* step 2: initialize command ring buffer */
1043 xhci_set_cmd_ring_deq(xhci);
1044 /* step 3: restore state and start state*/
1045 /* step 3: set CRS flag */
1046 command = readl(&xhci->op_regs->command);
1047 command |= CMD_CRS;
1048 writel(command, &xhci->op_regs->command);
1049 /*
1050 * Some controllers take up to 55+ ms to complete the controller
1051 * restore so setting the timeout to 100ms. Xhci specification
1052 * doesn't mention any timeout value.
1053 */
1054 if (xhci_handshake(&xhci->op_regs->status,
1055 STS_RESTORE, 0, 100 * 1000)) {
1056 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1057 spin_unlock_irq(&xhci->lock);
1058 return -ETIMEDOUT;
1059 }
1060 }
1061
1062 temp = readl(&xhci->op_regs->status);
1063
1064 /* re-initialize the HC on Restore Error, or Host Controller Error */
1065 if ((temp & (STS_SRE | STS_HCE)) &&
1066 !(xhci->xhc_state & XHCI_STATE_REMOVING)) {
1067 reinit_xhc = true;
1068 if (!xhci->broken_suspend)
1069 xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1070 }
1071
1072 if (reinit_xhc) {
1073 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1074 !(xhci_all_ports_seen_u0(xhci))) {
1075 del_timer_sync(&xhci->comp_mode_recovery_timer);
1076 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1077 "Compliance Mode Recovery Timer deleted!");
1078 }
1079
1080 /* Let the USB core know _both_ roothubs lost power. */
1081 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1082 if (xhci->shared_hcd)
1083 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1084
1085 xhci_dbg(xhci, "Stop HCD\n");
1086 xhci_halt(xhci);
1087 xhci_zero_64b_regs(xhci);
1088 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
1089 spin_unlock_irq(&xhci->lock);
1090 if (retval)
1091 return retval;
1092
1093 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1094 temp = readl(&xhci->op_regs->status);
1095 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1096 xhci_disable_interrupter(xhci->interrupters[0]);
1097
1098 xhci_dbg(xhci, "cleaning up memory\n");
1099 xhci_mem_cleanup(xhci);
1100 xhci_debugfs_exit(xhci);
1101 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1102 readl(&xhci->op_regs->status));
1103
1104 /* USB core calls the PCI reinit and start functions twice:
1105 * first with the primary HCD, and then with the secondary HCD.
1106 * If we don't do the same, the host will never be started.
1107 */
1108 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1109 retval = xhci_init(hcd);
1110 if (retval)
1111 return retval;
1112 comp_timer_running = true;
1113
1114 xhci_dbg(xhci, "Start the primary HCD\n");
1115 retval = xhci_run(hcd);
1116 if (!retval && xhci->shared_hcd) {
1117 xhci_dbg(xhci, "Start the secondary HCD\n");
1118 retval = xhci_run(xhci->shared_hcd);
1119 }
1120 if (retval)
1121 return retval;
1122 /*
1123 * Resume roothubs unconditionally as PORTSC change bits are not
1124 * immediately visible after xHC reset
1125 */
1126 hcd->state = HC_STATE_SUSPENDED;
1127
1128 if (xhci->shared_hcd) {
1129 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1130 usb_hcd_resume_root_hub(xhci->shared_hcd);
1131 }
1132 usb_hcd_resume_root_hub(hcd);
1133
1134 goto done;
1135 }
1136
1137 /* step 4: set Run/Stop bit */
1138 command = readl(&xhci->op_regs->command);
1139 command |= CMD_RUN;
1140 writel(command, &xhci->op_regs->command);
1141 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1142 0, 250 * 1000);
1143
1144 /* step 5: walk topology and initialize portsc,
1145 * portpmsc and portli
1146 */
1147 /* this is done in bus_resume */
1148
1149 /* step 6: restart each of the previously
1150 * Running endpoints by ringing their doorbells
1151 */
1152
1153 spin_unlock_irq(&xhci->lock);
1154
1155 xhci_dbc_resume(xhci);
1156
1157 if (retval == 0) {
1158 /*
1159 * Resume roothubs only if there are pending events.
1160 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1161 * the first wake signalling failed, give it that chance if
1162 * there are suspended USB 3 devices.
1163 */
1164 if (xhci->usb3_rhub.bus_state.suspended_ports ||
1165 xhci->usb3_rhub.bus_state.bus_suspended)
1166 suspended_usb3_devs = true;
1167
1168 pending_portevent = xhci_pending_portevent(xhci);
1169
1170 if (suspended_usb3_devs && !pending_portevent &&
1171 msg.event == PM_EVENT_AUTO_RESUME) {
1172 msleep(120);
1173 pending_portevent = xhci_pending_portevent(xhci);
1174 }
1175
1176 if (pending_portevent) {
1177 if (xhci->shared_hcd)
1178 usb_hcd_resume_root_hub(xhci->shared_hcd);
1179 usb_hcd_resume_root_hub(hcd);
1180 }
1181 }
1182done:
1183 /*
1184 * If system is subject to the Quirk, Compliance Mode Timer needs to
1185 * be re-initialized Always after a system resume. Ports are subject
1186 * to suffer the Compliance Mode issue again. It doesn't matter if
1187 * ports have entered previously to U0 before system's suspension.
1188 */
1189 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1190 compliance_mode_recovery_timer_init(xhci);
1191
1192 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1193 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1194
1195 /* Re-enable port polling. */
1196 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
1197 __func__, hcd->self.busnum);
1198 if (xhci->shared_hcd) {
1199 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1200 usb_hcd_poll_rh_status(xhci->shared_hcd);
1201 }
1202 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1203 usb_hcd_poll_rh_status(hcd);
1204
1205 return retval;
1206}
1207EXPORT_SYMBOL_GPL(xhci_resume);
1208#endif /* CONFIG_PM */
1209
1210/*-------------------------------------------------------------------------*/
1211
1212static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1213{
1214 void *temp;
1215 int ret = 0;
1216 unsigned int buf_len;
1217 enum dma_data_direction dir;
1218
1219 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1220 buf_len = urb->transfer_buffer_length;
1221
1222 temp = kzalloc_node(buf_len, GFP_ATOMIC,
1223 dev_to_node(hcd->self.sysdev));
1224 if (!temp)
1225 return -ENOMEM;
1226
1227 if (usb_urb_dir_out(urb))
1228 sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1229 temp, buf_len, 0);
1230
1231 urb->transfer_buffer = temp;
1232 urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1233 urb->transfer_buffer,
1234 urb->transfer_buffer_length,
1235 dir);
1236
1237 if (dma_mapping_error(hcd->self.sysdev,
1238 urb->transfer_dma)) {
1239 ret = -EAGAIN;
1240 kfree(temp);
1241 } else {
1242 urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1243 }
1244
1245 return ret;
1246}
1247
1248static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1249 struct urb *urb)
1250{
1251 bool ret = false;
1252 unsigned int i;
1253 unsigned int len = 0;
1254 unsigned int trb_size;
1255 unsigned int max_pkt;
1256 struct scatterlist *sg;
1257 struct scatterlist *tail_sg;
1258
1259 tail_sg = urb->sg;
1260 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1261
1262 if (!urb->num_sgs)
1263 return ret;
1264
1265 if (urb->dev->speed >= USB_SPEED_SUPER)
1266 trb_size = TRB_CACHE_SIZE_SS;
1267 else
1268 trb_size = TRB_CACHE_SIZE_HS;
1269
1270 if (urb->transfer_buffer_length != 0 &&
1271 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1272 for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1273 len = len + sg->length;
1274 if (i > trb_size - 2) {
1275 len = len - tail_sg->length;
1276 if (len < max_pkt) {
1277 ret = true;
1278 break;
1279 }
1280
1281 tail_sg = sg_next(tail_sg);
1282 }
1283 }
1284 }
1285 return ret;
1286}
1287
1288static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1289{
1290 unsigned int len;
1291 unsigned int buf_len;
1292 enum dma_data_direction dir;
1293
1294 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1295
1296 buf_len = urb->transfer_buffer_length;
1297
1298 if (IS_ENABLED(CONFIG_HAS_DMA) &&
1299 (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1300 dma_unmap_single(hcd->self.sysdev,
1301 urb->transfer_dma,
1302 urb->transfer_buffer_length,
1303 dir);
1304
1305 if (usb_urb_dir_in(urb)) {
1306 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1307 urb->transfer_buffer,
1308 buf_len,
1309 0);
1310 if (len != buf_len) {
1311 xhci_dbg(hcd_to_xhci(hcd),
1312 "Copy from tmp buf to urb sg list failed\n");
1313 urb->actual_length = len;
1314 }
1315 }
1316 urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1317 kfree(urb->transfer_buffer);
1318 urb->transfer_buffer = NULL;
1319}
1320
1321/*
1322 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1323 * we'll copy the actual data into the TRB address register. This is limited to
1324 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1325 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1326 */
1327static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1328 gfp_t mem_flags)
1329{
1330 struct xhci_hcd *xhci;
1331
1332 xhci = hcd_to_xhci(hcd);
1333
1334 if (xhci_urb_suitable_for_idt(urb))
1335 return 0;
1336
1337 if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1338 if (xhci_urb_temp_buffer_required(hcd, urb))
1339 return xhci_map_temp_buffer(hcd, urb);
1340 }
1341 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1342}
1343
1344static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1345{
1346 struct xhci_hcd *xhci;
1347 bool unmap_temp_buf = false;
1348
1349 xhci = hcd_to_xhci(hcd);
1350
1351 if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1352 unmap_temp_buf = true;
1353
1354 if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1355 xhci_unmap_temp_buf(hcd, urb);
1356 else
1357 usb_hcd_unmap_urb_for_dma(hcd, urb);
1358}
1359
1360/**
1361 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1362 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1363 * value to right shift 1 for the bitmask.
1364 *
1365 * Index = (epnum * 2) + direction - 1,
1366 * where direction = 0 for OUT, 1 for IN.
1367 * For control endpoints, the IN index is used (OUT index is unused), so
1368 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1369 */
1370unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1371{
1372 unsigned int index;
1373 if (usb_endpoint_xfer_control(desc))
1374 index = (unsigned int) (usb_endpoint_num(desc)*2);
1375 else
1376 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1377 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1378 return index;
1379}
1380EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
1381
1382/* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1383 * address from the XHCI endpoint index.
1384 */
1385static unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1386{
1387 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1388 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1389 return direction | number;
1390}
1391
1392/* Find the flag for this endpoint (for use in the control context). Use the
1393 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1394 * bit 1, etc.
1395 */
1396static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1397{
1398 return 1 << (xhci_get_endpoint_index(desc) + 1);
1399}
1400
1401/* Compute the last valid endpoint context index. Basically, this is the
1402 * endpoint index plus one. For slot contexts with more than valid endpoint,
1403 * we find the most significant bit set in the added contexts flags.
1404 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1405 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1406 */
1407unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1408{
1409 return fls(added_ctxs) - 1;
1410}
1411
1412/* Returns 1 if the arguments are OK;
1413 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1414 */
1415static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1416 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1417 const char *func) {
1418 struct xhci_hcd *xhci;
1419 struct xhci_virt_device *virt_dev;
1420
1421 if (!hcd || (check_ep && !ep) || !udev) {
1422 pr_debug("xHCI %s called with invalid args\n", func);
1423 return -EINVAL;
1424 }
1425 if (!udev->parent) {
1426 pr_debug("xHCI %s called for root hub\n", func);
1427 return 0;
1428 }
1429
1430 xhci = hcd_to_xhci(hcd);
1431 if (check_virt_dev) {
1432 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1433 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1434 func);
1435 return -EINVAL;
1436 }
1437
1438 virt_dev = xhci->devs[udev->slot_id];
1439 if (virt_dev->udev != udev) {
1440 xhci_dbg(xhci, "xHCI %s called with udev and "
1441 "virt_dev does not match\n", func);
1442 return -EINVAL;
1443 }
1444 }
1445
1446 if (xhci->xhc_state & XHCI_STATE_HALTED)
1447 return -ENODEV;
1448
1449 return 1;
1450}
1451
1452static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1453 struct usb_device *udev, struct xhci_command *command,
1454 bool ctx_change, bool must_succeed);
1455
1456/*
1457 * Full speed devices may have a max packet size greater than 8 bytes, but the
1458 * USB core doesn't know that until it reads the first 8 bytes of the
1459 * descriptor. If the usb_device's max packet size changes after that point,
1460 * we need to issue an evaluate context command and wait on it.
1461 */
1462static int xhci_check_ep0_maxpacket(struct xhci_hcd *xhci, struct xhci_virt_device *vdev)
1463{
1464 struct xhci_input_control_ctx *ctrl_ctx;
1465 struct xhci_ep_ctx *ep_ctx;
1466 struct xhci_command *command;
1467 int max_packet_size;
1468 int hw_max_packet_size;
1469 int ret = 0;
1470
1471 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, 0);
1472 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1473 max_packet_size = usb_endpoint_maxp(&vdev->udev->ep0.desc);
1474
1475 if (hw_max_packet_size == max_packet_size)
1476 return 0;
1477
1478 switch (max_packet_size) {
1479 case 8: case 16: case 32: case 64: case 9:
1480 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1481 "Max Packet Size for ep 0 changed.");
1482 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1483 "Max packet size in usb_device = %d",
1484 max_packet_size);
1485 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1486 "Max packet size in xHCI HW = %d",
1487 hw_max_packet_size);
1488 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1489 "Issuing evaluate context command.");
1490
1491 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
1492 if (!command)
1493 return -ENOMEM;
1494
1495 command->in_ctx = vdev->in_ctx;
1496 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1497 if (!ctrl_ctx) {
1498 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1499 __func__);
1500 ret = -ENOMEM;
1501 break;
1502 }
1503 /* Set up the modified control endpoint 0 */
1504 xhci_endpoint_copy(xhci, vdev->in_ctx, vdev->out_ctx, 0);
1505
1506 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, 0);
1507 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1508 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1509 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1510
1511 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1512 ctrl_ctx->drop_flags = 0;
1513
1514 ret = xhci_configure_endpoint(xhci, vdev->udev, command,
1515 true, false);
1516 /* Clean up the input context for later use by bandwidth functions */
1517 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1518 break;
1519 default:
1520 dev_dbg(&vdev->udev->dev, "incorrect max packet size %d for ep0\n",
1521 max_packet_size);
1522 return -EINVAL;
1523 }
1524
1525 kfree(command->completion);
1526 kfree(command);
1527
1528 return ret;
1529}
1530
1531/*
1532 * non-error returns are a promise to giveback() the urb later
1533 * we drop ownership so next owner (or urb unlink) can get it
1534 */
1535static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1536{
1537 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1538 unsigned long flags;
1539 int ret = 0;
1540 unsigned int slot_id, ep_index;
1541 unsigned int *ep_state;
1542 struct urb_priv *urb_priv;
1543 int num_tds;
1544
1545 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1546
1547 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1548 num_tds = urb->number_of_packets;
1549 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1550 urb->transfer_buffer_length > 0 &&
1551 urb->transfer_flags & URB_ZERO_PACKET &&
1552 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1553 num_tds = 2;
1554 else
1555 num_tds = 1;
1556
1557 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1558 if (!urb_priv)
1559 return -ENOMEM;
1560
1561 urb_priv->num_tds = num_tds;
1562 urb_priv->num_tds_done = 0;
1563 urb->hcpriv = urb_priv;
1564
1565 trace_xhci_urb_enqueue(urb);
1566
1567 spin_lock_irqsave(&xhci->lock, flags);
1568
1569 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1570 true, true, __func__);
1571 if (ret <= 0) {
1572 ret = ret ? ret : -EINVAL;
1573 goto free_priv;
1574 }
1575
1576 slot_id = urb->dev->slot_id;
1577
1578 if (!HCD_HW_ACCESSIBLE(hcd)) {
1579 ret = -ESHUTDOWN;
1580 goto free_priv;
1581 }
1582
1583 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1584 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1585 ret = -ENODEV;
1586 goto free_priv;
1587 }
1588
1589 if (xhci->xhc_state & XHCI_STATE_DYING) {
1590 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1591 urb->ep->desc.bEndpointAddress, urb);
1592 ret = -ESHUTDOWN;
1593 goto free_priv;
1594 }
1595
1596 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1597
1598 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1599 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1600 *ep_state);
1601 ret = -EINVAL;
1602 goto free_priv;
1603 }
1604 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1605 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1606 ret = -EINVAL;
1607 goto free_priv;
1608 }
1609
1610 switch (usb_endpoint_type(&urb->ep->desc)) {
1611
1612 case USB_ENDPOINT_XFER_CONTROL:
1613 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1614 slot_id, ep_index);
1615 break;
1616 case USB_ENDPOINT_XFER_BULK:
1617 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1618 slot_id, ep_index);
1619 break;
1620 case USB_ENDPOINT_XFER_INT:
1621 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1622 slot_id, ep_index);
1623 break;
1624 case USB_ENDPOINT_XFER_ISOC:
1625 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1626 slot_id, ep_index);
1627 }
1628
1629 if (ret) {
1630free_priv:
1631 xhci_urb_free_priv(urb_priv);
1632 urb->hcpriv = NULL;
1633 }
1634 spin_unlock_irqrestore(&xhci->lock, flags);
1635 return ret;
1636}
1637
1638/*
1639 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1640 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1641 * should pick up where it left off in the TD, unless a Set Transfer Ring
1642 * Dequeue Pointer is issued.
1643 *
1644 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1645 * the ring. Since the ring is a contiguous structure, they can't be physically
1646 * removed. Instead, there are two options:
1647 *
1648 * 1) If the HC is in the middle of processing the URB to be canceled, we
1649 * simply move the ring's dequeue pointer past those TRBs using the Set
1650 * Transfer Ring Dequeue Pointer command. This will be the common case,
1651 * when drivers timeout on the last submitted URB and attempt to cancel.
1652 *
1653 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1654 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1655 * HC will need to invalidate the any TRBs it has cached after the stop
1656 * endpoint command, as noted in the xHCI 0.95 errata.
1657 *
1658 * 3) The TD may have completed by the time the Stop Endpoint Command
1659 * completes, so software needs to handle that case too.
1660 *
1661 * This function should protect against the TD enqueueing code ringing the
1662 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1663 * It also needs to account for multiple cancellations on happening at the same
1664 * time for the same endpoint.
1665 *
1666 * Note that this function can be called in any context, or so says
1667 * usb_hcd_unlink_urb()
1668 */
1669static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1670{
1671 unsigned long flags;
1672 int ret, i;
1673 u32 temp;
1674 struct xhci_hcd *xhci;
1675 struct urb_priv *urb_priv;
1676 struct xhci_td *td;
1677 unsigned int ep_index;
1678 struct xhci_ring *ep_ring;
1679 struct xhci_virt_ep *ep;
1680 struct xhci_command *command;
1681 struct xhci_virt_device *vdev;
1682
1683 xhci = hcd_to_xhci(hcd);
1684 spin_lock_irqsave(&xhci->lock, flags);
1685
1686 trace_xhci_urb_dequeue(urb);
1687
1688 /* Make sure the URB hasn't completed or been unlinked already */
1689 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1690 if (ret)
1691 goto done;
1692
1693 /* give back URB now if we can't queue it for cancel */
1694 vdev = xhci->devs[urb->dev->slot_id];
1695 urb_priv = urb->hcpriv;
1696 if (!vdev || !urb_priv)
1697 goto err_giveback;
1698
1699 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1700 ep = &vdev->eps[ep_index];
1701 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1702 if (!ep || !ep_ring)
1703 goto err_giveback;
1704
1705 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1706 temp = readl(&xhci->op_regs->status);
1707 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1708 xhci_hc_died(xhci);
1709 goto done;
1710 }
1711
1712 /*
1713 * check ring is not re-allocated since URB was enqueued. If it is, then
1714 * make sure none of the ring related pointers in this URB private data
1715 * are touched, such as td_list, otherwise we overwrite freed data
1716 */
1717 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1718 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1719 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1720 td = &urb_priv->td[i];
1721 if (!list_empty(&td->cancelled_td_list))
1722 list_del_init(&td->cancelled_td_list);
1723 }
1724 goto err_giveback;
1725 }
1726
1727 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1728 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1729 "HC halted, freeing TD manually.");
1730 for (i = urb_priv->num_tds_done;
1731 i < urb_priv->num_tds;
1732 i++) {
1733 td = &urb_priv->td[i];
1734 if (!list_empty(&td->td_list))
1735 list_del_init(&td->td_list);
1736 if (!list_empty(&td->cancelled_td_list))
1737 list_del_init(&td->cancelled_td_list);
1738 }
1739 goto err_giveback;
1740 }
1741
1742 i = urb_priv->num_tds_done;
1743 if (i < urb_priv->num_tds)
1744 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1745 "Cancel URB %p, dev %s, ep 0x%x, "
1746 "starting at offset 0x%llx",
1747 urb, urb->dev->devpath,
1748 urb->ep->desc.bEndpointAddress,
1749 (unsigned long long) xhci_trb_virt_to_dma(
1750 urb_priv->td[i].start_seg,
1751 urb_priv->td[i].start_trb));
1752
1753 for (; i < urb_priv->num_tds; i++) {
1754 td = &urb_priv->td[i];
1755 /* TD can already be on cancelled list if ep halted on it */
1756 if (list_empty(&td->cancelled_td_list)) {
1757 td->cancel_status = TD_DIRTY;
1758 list_add_tail(&td->cancelled_td_list,
1759 &ep->cancelled_td_list);
1760 }
1761 }
1762
1763 /* These completion handlers will sort out cancelled TDs for us */
1764 if (ep->ep_state & (EP_STOP_CMD_PENDING | EP_HALTED | SET_DEQ_PENDING)) {
1765 xhci_dbg(xhci, "Not queuing Stop Endpoint on slot %d ep %d in state 0x%x\n",
1766 urb->dev->slot_id, ep_index, ep->ep_state);
1767 goto done;
1768 }
1769
1770 /* In this case no commands are pending but the endpoint is stopped */
1771 if (ep->ep_state & EP_CLEARING_TT) {
1772 /* and cancelled TDs can be given back right away */
1773 xhci_dbg(xhci, "Invalidating TDs instantly on slot %d ep %d in state 0x%x\n",
1774 urb->dev->slot_id, ep_index, ep->ep_state);
1775 xhci_process_cancelled_tds(ep);
1776 } else {
1777 /* Otherwise, queue a new Stop Endpoint command */
1778 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1779 if (!command) {
1780 ret = -ENOMEM;
1781 goto done;
1782 }
1783 ep->stop_time = jiffies;
1784 ep->ep_state |= EP_STOP_CMD_PENDING;
1785 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1786 ep_index, 0);
1787 xhci_ring_cmd_db(xhci);
1788 }
1789done:
1790 spin_unlock_irqrestore(&xhci->lock, flags);
1791 return ret;
1792
1793err_giveback:
1794 if (urb_priv)
1795 xhci_urb_free_priv(urb_priv);
1796 usb_hcd_unlink_urb_from_ep(hcd, urb);
1797 spin_unlock_irqrestore(&xhci->lock, flags);
1798 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1799 return ret;
1800}
1801
1802/* Drop an endpoint from a new bandwidth configuration for this device.
1803 * Only one call to this function is allowed per endpoint before
1804 * check_bandwidth() or reset_bandwidth() must be called.
1805 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1806 * add the endpoint to the schedule with possibly new parameters denoted by a
1807 * different endpoint descriptor in usb_host_endpoint.
1808 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1809 * not allowed.
1810 *
1811 * The USB core will not allow URBs to be queued to an endpoint that is being
1812 * disabled, so there's no need for mutual exclusion to protect
1813 * the xhci->devs[slot_id] structure.
1814 */
1815int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1816 struct usb_host_endpoint *ep)
1817{
1818 struct xhci_hcd *xhci;
1819 struct xhci_container_ctx *in_ctx, *out_ctx;
1820 struct xhci_input_control_ctx *ctrl_ctx;
1821 unsigned int ep_index;
1822 struct xhci_ep_ctx *ep_ctx;
1823 u32 drop_flag;
1824 u32 new_add_flags, new_drop_flags;
1825 int ret;
1826
1827 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1828 if (ret <= 0)
1829 return ret;
1830 xhci = hcd_to_xhci(hcd);
1831 if (xhci->xhc_state & XHCI_STATE_DYING)
1832 return -ENODEV;
1833
1834 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1835 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1836 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1837 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1838 __func__, drop_flag);
1839 return 0;
1840 }
1841
1842 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1843 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1844 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1845 if (!ctrl_ctx) {
1846 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1847 __func__);
1848 return 0;
1849 }
1850
1851 ep_index = xhci_get_endpoint_index(&ep->desc);
1852 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1853 /* If the HC already knows the endpoint is disabled,
1854 * or the HCD has noted it is disabled, ignore this request
1855 */
1856 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1857 le32_to_cpu(ctrl_ctx->drop_flags) &
1858 xhci_get_endpoint_flag(&ep->desc)) {
1859 /* Do not warn when called after a usb_device_reset */
1860 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1861 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1862 __func__, ep);
1863 return 0;
1864 }
1865
1866 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1867 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1868
1869 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1870 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1871
1872 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1873
1874 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1875
1876 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1877 (unsigned int) ep->desc.bEndpointAddress,
1878 udev->slot_id,
1879 (unsigned int) new_drop_flags,
1880 (unsigned int) new_add_flags);
1881 return 0;
1882}
1883EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
1884
1885/* Add an endpoint to a new possible bandwidth configuration for this device.
1886 * Only one call to this function is allowed per endpoint before
1887 * check_bandwidth() or reset_bandwidth() must be called.
1888 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1889 * add the endpoint to the schedule with possibly new parameters denoted by a
1890 * different endpoint descriptor in usb_host_endpoint.
1891 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1892 * not allowed.
1893 *
1894 * The USB core will not allow URBs to be queued to an endpoint until the
1895 * configuration or alt setting is installed in the device, so there's no need
1896 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1897 */
1898int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1899 struct usb_host_endpoint *ep)
1900{
1901 struct xhci_hcd *xhci;
1902 struct xhci_container_ctx *in_ctx;
1903 unsigned int ep_index;
1904 struct xhci_input_control_ctx *ctrl_ctx;
1905 struct xhci_ep_ctx *ep_ctx;
1906 u32 added_ctxs;
1907 u32 new_add_flags, new_drop_flags;
1908 struct xhci_virt_device *virt_dev;
1909 int ret = 0;
1910
1911 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1912 if (ret <= 0) {
1913 /* So we won't queue a reset ep command for a root hub */
1914 ep->hcpriv = NULL;
1915 return ret;
1916 }
1917 xhci = hcd_to_xhci(hcd);
1918 if (xhci->xhc_state & XHCI_STATE_DYING)
1919 return -ENODEV;
1920
1921 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1922 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1923 /* FIXME when we have to issue an evaluate endpoint command to
1924 * deal with ep0 max packet size changing once we get the
1925 * descriptors
1926 */
1927 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1928 __func__, added_ctxs);
1929 return 0;
1930 }
1931
1932 virt_dev = xhci->devs[udev->slot_id];
1933 in_ctx = virt_dev->in_ctx;
1934 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1935 if (!ctrl_ctx) {
1936 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1937 __func__);
1938 return 0;
1939 }
1940
1941 ep_index = xhci_get_endpoint_index(&ep->desc);
1942 /* If this endpoint is already in use, and the upper layers are trying
1943 * to add it again without dropping it, reject the addition.
1944 */
1945 if (virt_dev->eps[ep_index].ring &&
1946 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1947 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1948 "without dropping it.\n",
1949 (unsigned int) ep->desc.bEndpointAddress);
1950 return -EINVAL;
1951 }
1952
1953 /* If the HCD has already noted the endpoint is enabled,
1954 * ignore this request.
1955 */
1956 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1957 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1958 __func__, ep);
1959 return 0;
1960 }
1961
1962 /*
1963 * Configuration and alternate setting changes must be done in
1964 * process context, not interrupt context (or so documenation
1965 * for usb_set_interface() and usb_set_configuration() claim).
1966 */
1967 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1968 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1969 __func__, ep->desc.bEndpointAddress);
1970 return -ENOMEM;
1971 }
1972
1973 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1974 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1975
1976 /* If xhci_endpoint_disable() was called for this endpoint, but the
1977 * xHC hasn't been notified yet through the check_bandwidth() call,
1978 * this re-adds a new state for the endpoint from the new endpoint
1979 * descriptors. We must drop and re-add this endpoint, so we leave the
1980 * drop flags alone.
1981 */
1982 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1983
1984 /* Store the usb_device pointer for later use */
1985 ep->hcpriv = udev;
1986
1987 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1988 trace_xhci_add_endpoint(ep_ctx);
1989
1990 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1991 (unsigned int) ep->desc.bEndpointAddress,
1992 udev->slot_id,
1993 (unsigned int) new_drop_flags,
1994 (unsigned int) new_add_flags);
1995 return 0;
1996}
1997EXPORT_SYMBOL_GPL(xhci_add_endpoint);
1998
1999static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
2000{
2001 struct xhci_input_control_ctx *ctrl_ctx;
2002 struct xhci_ep_ctx *ep_ctx;
2003 struct xhci_slot_ctx *slot_ctx;
2004 int i;
2005
2006 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
2007 if (!ctrl_ctx) {
2008 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2009 __func__);
2010 return;
2011 }
2012
2013 /* When a device's add flag and drop flag are zero, any subsequent
2014 * configure endpoint command will leave that endpoint's state
2015 * untouched. Make sure we don't leave any old state in the input
2016 * endpoint contexts.
2017 */
2018 ctrl_ctx->drop_flags = 0;
2019 ctrl_ctx->add_flags = 0;
2020 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2021 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2022 /* Endpoint 0 is always valid */
2023 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2024 for (i = 1; i < 31; i++) {
2025 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2026 ep_ctx->ep_info = 0;
2027 ep_ctx->ep_info2 = 0;
2028 ep_ctx->deq = 0;
2029 ep_ctx->tx_info = 0;
2030 }
2031}
2032
2033static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2034 struct usb_device *udev, u32 *cmd_status)
2035{
2036 int ret;
2037
2038 switch (*cmd_status) {
2039 case COMP_COMMAND_ABORTED:
2040 case COMP_COMMAND_RING_STOPPED:
2041 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2042 ret = -ETIME;
2043 break;
2044 case COMP_RESOURCE_ERROR:
2045 dev_warn(&udev->dev,
2046 "Not enough host controller resources for new device state.\n");
2047 ret = -ENOMEM;
2048 /* FIXME: can we allocate more resources for the HC? */
2049 break;
2050 case COMP_BANDWIDTH_ERROR:
2051 case COMP_SECONDARY_BANDWIDTH_ERROR:
2052 dev_warn(&udev->dev,
2053 "Not enough bandwidth for new device state.\n");
2054 ret = -ENOSPC;
2055 /* FIXME: can we go back to the old state? */
2056 break;
2057 case COMP_TRB_ERROR:
2058 /* the HCD set up something wrong */
2059 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2060 "add flag = 1, "
2061 "and endpoint is not disabled.\n");
2062 ret = -EINVAL;
2063 break;
2064 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2065 dev_warn(&udev->dev,
2066 "ERROR: Incompatible device for endpoint configure command.\n");
2067 ret = -ENODEV;
2068 break;
2069 case COMP_SUCCESS:
2070 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2071 "Successful Endpoint Configure command");
2072 ret = 0;
2073 break;
2074 default:
2075 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2076 *cmd_status);
2077 ret = -EINVAL;
2078 break;
2079 }
2080 return ret;
2081}
2082
2083static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2084 struct usb_device *udev, u32 *cmd_status)
2085{
2086 int ret;
2087
2088 switch (*cmd_status) {
2089 case COMP_COMMAND_ABORTED:
2090 case COMP_COMMAND_RING_STOPPED:
2091 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2092 ret = -ETIME;
2093 break;
2094 case COMP_PARAMETER_ERROR:
2095 dev_warn(&udev->dev,
2096 "WARN: xHCI driver setup invalid evaluate context command.\n");
2097 ret = -EINVAL;
2098 break;
2099 case COMP_SLOT_NOT_ENABLED_ERROR:
2100 dev_warn(&udev->dev,
2101 "WARN: slot not enabled for evaluate context command.\n");
2102 ret = -EINVAL;
2103 break;
2104 case COMP_CONTEXT_STATE_ERROR:
2105 dev_warn(&udev->dev,
2106 "WARN: invalid context state for evaluate context command.\n");
2107 ret = -EINVAL;
2108 break;
2109 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2110 dev_warn(&udev->dev,
2111 "ERROR: Incompatible device for evaluate context command.\n");
2112 ret = -ENODEV;
2113 break;
2114 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2115 /* Max Exit Latency too large error */
2116 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2117 ret = -EINVAL;
2118 break;
2119 case COMP_SUCCESS:
2120 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2121 "Successful evaluate context command");
2122 ret = 0;
2123 break;
2124 default:
2125 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2126 *cmd_status);
2127 ret = -EINVAL;
2128 break;
2129 }
2130 return ret;
2131}
2132
2133static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2134 struct xhci_input_control_ctx *ctrl_ctx)
2135{
2136 u32 valid_add_flags;
2137 u32 valid_drop_flags;
2138
2139 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2140 * (bit 1). The default control endpoint is added during the Address
2141 * Device command and is never removed until the slot is disabled.
2142 */
2143 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2144 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2145
2146 /* Use hweight32 to count the number of ones in the add flags, or
2147 * number of endpoints added. Don't count endpoints that are changed
2148 * (both added and dropped).
2149 */
2150 return hweight32(valid_add_flags) -
2151 hweight32(valid_add_flags & valid_drop_flags);
2152}
2153
2154static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2155 struct xhci_input_control_ctx *ctrl_ctx)
2156{
2157 u32 valid_add_flags;
2158 u32 valid_drop_flags;
2159
2160 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2161 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2162
2163 return hweight32(valid_drop_flags) -
2164 hweight32(valid_add_flags & valid_drop_flags);
2165}
2166
2167/*
2168 * We need to reserve the new number of endpoints before the configure endpoint
2169 * command completes. We can't subtract the dropped endpoints from the number
2170 * of active endpoints until the command completes because we can oversubscribe
2171 * the host in this case:
2172 *
2173 * - the first configure endpoint command drops more endpoints than it adds
2174 * - a second configure endpoint command that adds more endpoints is queued
2175 * - the first configure endpoint command fails, so the config is unchanged
2176 * - the second command may succeed, even though there isn't enough resources
2177 *
2178 * Must be called with xhci->lock held.
2179 */
2180static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2181 struct xhci_input_control_ctx *ctrl_ctx)
2182{
2183 u32 added_eps;
2184
2185 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2186 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2187 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2188 "Not enough ep ctxs: "
2189 "%u active, need to add %u, limit is %u.",
2190 xhci->num_active_eps, added_eps,
2191 xhci->limit_active_eps);
2192 return -ENOMEM;
2193 }
2194 xhci->num_active_eps += added_eps;
2195 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2196 "Adding %u ep ctxs, %u now active.", added_eps,
2197 xhci->num_active_eps);
2198 return 0;
2199}
2200
2201/*
2202 * The configure endpoint was failed by the xHC for some other reason, so we
2203 * need to revert the resources that failed configuration would have used.
2204 *
2205 * Must be called with xhci->lock held.
2206 */
2207static void xhci_free_host_resources(struct xhci_hcd *xhci,
2208 struct xhci_input_control_ctx *ctrl_ctx)
2209{
2210 u32 num_failed_eps;
2211
2212 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2213 xhci->num_active_eps -= num_failed_eps;
2214 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2215 "Removing %u failed ep ctxs, %u now active.",
2216 num_failed_eps,
2217 xhci->num_active_eps);
2218}
2219
2220/*
2221 * Now that the command has completed, clean up the active endpoint count by
2222 * subtracting out the endpoints that were dropped (but not changed).
2223 *
2224 * Must be called with xhci->lock held.
2225 */
2226static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2227 struct xhci_input_control_ctx *ctrl_ctx)
2228{
2229 u32 num_dropped_eps;
2230
2231 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2232 xhci->num_active_eps -= num_dropped_eps;
2233 if (num_dropped_eps)
2234 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2235 "Removing %u dropped ep ctxs, %u now active.",
2236 num_dropped_eps,
2237 xhci->num_active_eps);
2238}
2239
2240static unsigned int xhci_get_block_size(struct usb_device *udev)
2241{
2242 switch (udev->speed) {
2243 case USB_SPEED_LOW:
2244 case USB_SPEED_FULL:
2245 return FS_BLOCK;
2246 case USB_SPEED_HIGH:
2247 return HS_BLOCK;
2248 case USB_SPEED_SUPER:
2249 case USB_SPEED_SUPER_PLUS:
2250 return SS_BLOCK;
2251 case USB_SPEED_UNKNOWN:
2252 default:
2253 /* Should never happen */
2254 return 1;
2255 }
2256}
2257
2258static unsigned int
2259xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2260{
2261 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2262 return LS_OVERHEAD;
2263 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2264 return FS_OVERHEAD;
2265 return HS_OVERHEAD;
2266}
2267
2268/* If we are changing a LS/FS device under a HS hub,
2269 * make sure (if we are activating a new TT) that the HS bus has enough
2270 * bandwidth for this new TT.
2271 */
2272static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2273 struct xhci_virt_device *virt_dev,
2274 int old_active_eps)
2275{
2276 struct xhci_interval_bw_table *bw_table;
2277 struct xhci_tt_bw_info *tt_info;
2278
2279 /* Find the bandwidth table for the root port this TT is attached to. */
2280 bw_table = &xhci->rh_bw[virt_dev->rhub_port->hw_portnum].bw_table;
2281 tt_info = virt_dev->tt_info;
2282 /* If this TT already had active endpoints, the bandwidth for this TT
2283 * has already been added. Removing all periodic endpoints (and thus
2284 * making the TT enactive) will only decrease the bandwidth used.
2285 */
2286 if (old_active_eps)
2287 return 0;
2288 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2289 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2290 return -ENOMEM;
2291 return 0;
2292 }
2293 /* Not sure why we would have no new active endpoints...
2294 *
2295 * Maybe because of an Evaluate Context change for a hub update or a
2296 * control endpoint 0 max packet size change?
2297 * FIXME: skip the bandwidth calculation in that case.
2298 */
2299 return 0;
2300}
2301
2302static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2303 struct xhci_virt_device *virt_dev)
2304{
2305 unsigned int bw_reserved;
2306
2307 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2308 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2309 return -ENOMEM;
2310
2311 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2312 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2313 return -ENOMEM;
2314
2315 return 0;
2316}
2317
2318/*
2319 * This algorithm is a very conservative estimate of the worst-case scheduling
2320 * scenario for any one interval. The hardware dynamically schedules the
2321 * packets, so we can't tell which microframe could be the limiting factor in
2322 * the bandwidth scheduling. This only takes into account periodic endpoints.
2323 *
2324 * Obviously, we can't solve an NP complete problem to find the minimum worst
2325 * case scenario. Instead, we come up with an estimate that is no less than
2326 * the worst case bandwidth used for any one microframe, but may be an
2327 * over-estimate.
2328 *
2329 * We walk the requirements for each endpoint by interval, starting with the
2330 * smallest interval, and place packets in the schedule where there is only one
2331 * possible way to schedule packets for that interval. In order to simplify
2332 * this algorithm, we record the largest max packet size for each interval, and
2333 * assume all packets will be that size.
2334 *
2335 * For interval 0, we obviously must schedule all packets for each interval.
2336 * The bandwidth for interval 0 is just the amount of data to be transmitted
2337 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2338 * the number of packets).
2339 *
2340 * For interval 1, we have two possible microframes to schedule those packets
2341 * in. For this algorithm, if we can schedule the same number of packets for
2342 * each possible scheduling opportunity (each microframe), we will do so. The
2343 * remaining number of packets will be saved to be transmitted in the gaps in
2344 * the next interval's scheduling sequence.
2345 *
2346 * As we move those remaining packets to be scheduled with interval 2 packets,
2347 * we have to double the number of remaining packets to transmit. This is
2348 * because the intervals are actually powers of 2, and we would be transmitting
2349 * the previous interval's packets twice in this interval. We also have to be
2350 * sure that when we look at the largest max packet size for this interval, we
2351 * also look at the largest max packet size for the remaining packets and take
2352 * the greater of the two.
2353 *
2354 * The algorithm continues to evenly distribute packets in each scheduling
2355 * opportunity, and push the remaining packets out, until we get to the last
2356 * interval. Then those packets and their associated overhead are just added
2357 * to the bandwidth used.
2358 */
2359static int xhci_check_bw_table(struct xhci_hcd *xhci,
2360 struct xhci_virt_device *virt_dev,
2361 int old_active_eps)
2362{
2363 unsigned int bw_reserved;
2364 unsigned int max_bandwidth;
2365 unsigned int bw_used;
2366 unsigned int block_size;
2367 struct xhci_interval_bw_table *bw_table;
2368 unsigned int packet_size = 0;
2369 unsigned int overhead = 0;
2370 unsigned int packets_transmitted = 0;
2371 unsigned int packets_remaining = 0;
2372 unsigned int i;
2373
2374 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2375 return xhci_check_ss_bw(xhci, virt_dev);
2376
2377 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2378 max_bandwidth = HS_BW_LIMIT;
2379 /* Convert percent of bus BW reserved to blocks reserved */
2380 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2381 } else {
2382 max_bandwidth = FS_BW_LIMIT;
2383 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2384 }
2385
2386 bw_table = virt_dev->bw_table;
2387 /* We need to translate the max packet size and max ESIT payloads into
2388 * the units the hardware uses.
2389 */
2390 block_size = xhci_get_block_size(virt_dev->udev);
2391
2392 /* If we are manipulating a LS/FS device under a HS hub, double check
2393 * that the HS bus has enough bandwidth if we are activing a new TT.
2394 */
2395 if (virt_dev->tt_info) {
2396 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2397 "Recalculating BW for rootport %u",
2398 virt_dev->rhub_port->hw_portnum + 1);
2399 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2400 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2401 "newly activated TT.\n");
2402 return -ENOMEM;
2403 }
2404 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2405 "Recalculating BW for TT slot %u port %u",
2406 virt_dev->tt_info->slot_id,
2407 virt_dev->tt_info->ttport);
2408 } else {
2409 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2410 "Recalculating BW for rootport %u",
2411 virt_dev->rhub_port->hw_portnum + 1);
2412 }
2413
2414 /* Add in how much bandwidth will be used for interval zero, or the
2415 * rounded max ESIT payload + number of packets * largest overhead.
2416 */
2417 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2418 bw_table->interval_bw[0].num_packets *
2419 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2420
2421 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2422 unsigned int bw_added;
2423 unsigned int largest_mps;
2424 unsigned int interval_overhead;
2425
2426 /*
2427 * How many packets could we transmit in this interval?
2428 * If packets didn't fit in the previous interval, we will need
2429 * to transmit that many packets twice within this interval.
2430 */
2431 packets_remaining = 2 * packets_remaining +
2432 bw_table->interval_bw[i].num_packets;
2433
2434 /* Find the largest max packet size of this or the previous
2435 * interval.
2436 */
2437 if (list_empty(&bw_table->interval_bw[i].endpoints))
2438 largest_mps = 0;
2439 else {
2440 struct xhci_virt_ep *virt_ep;
2441 struct list_head *ep_entry;
2442
2443 ep_entry = bw_table->interval_bw[i].endpoints.next;
2444 virt_ep = list_entry(ep_entry,
2445 struct xhci_virt_ep, bw_endpoint_list);
2446 /* Convert to blocks, rounding up */
2447 largest_mps = DIV_ROUND_UP(
2448 virt_ep->bw_info.max_packet_size,
2449 block_size);
2450 }
2451 if (largest_mps > packet_size)
2452 packet_size = largest_mps;
2453
2454 /* Use the larger overhead of this or the previous interval. */
2455 interval_overhead = xhci_get_largest_overhead(
2456 &bw_table->interval_bw[i]);
2457 if (interval_overhead > overhead)
2458 overhead = interval_overhead;
2459
2460 /* How many packets can we evenly distribute across
2461 * (1 << (i + 1)) possible scheduling opportunities?
2462 */
2463 packets_transmitted = packets_remaining >> (i + 1);
2464
2465 /* Add in the bandwidth used for those scheduled packets */
2466 bw_added = packets_transmitted * (overhead + packet_size);
2467
2468 /* How many packets do we have remaining to transmit? */
2469 packets_remaining = packets_remaining % (1 << (i + 1));
2470
2471 /* What largest max packet size should those packets have? */
2472 /* If we've transmitted all packets, don't carry over the
2473 * largest packet size.
2474 */
2475 if (packets_remaining == 0) {
2476 packet_size = 0;
2477 overhead = 0;
2478 } else if (packets_transmitted > 0) {
2479 /* Otherwise if we do have remaining packets, and we've
2480 * scheduled some packets in this interval, take the
2481 * largest max packet size from endpoints with this
2482 * interval.
2483 */
2484 packet_size = largest_mps;
2485 overhead = interval_overhead;
2486 }
2487 /* Otherwise carry over packet_size and overhead from the last
2488 * time we had a remainder.
2489 */
2490 bw_used += bw_added;
2491 if (bw_used > max_bandwidth) {
2492 xhci_warn(xhci, "Not enough bandwidth. "
2493 "Proposed: %u, Max: %u\n",
2494 bw_used, max_bandwidth);
2495 return -ENOMEM;
2496 }
2497 }
2498 /*
2499 * Ok, we know we have some packets left over after even-handedly
2500 * scheduling interval 15. We don't know which microframes they will
2501 * fit into, so we over-schedule and say they will be scheduled every
2502 * microframe.
2503 */
2504 if (packets_remaining > 0)
2505 bw_used += overhead + packet_size;
2506
2507 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2508 /* OK, we're manipulating a HS device attached to a
2509 * root port bandwidth domain. Include the number of active TTs
2510 * in the bandwidth used.
2511 */
2512 bw_used += TT_HS_OVERHEAD *
2513 xhci->rh_bw[virt_dev->rhub_port->hw_portnum].num_active_tts;
2514 }
2515
2516 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2517 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2518 "Available: %u " "percent",
2519 bw_used, max_bandwidth, bw_reserved,
2520 (max_bandwidth - bw_used - bw_reserved) * 100 /
2521 max_bandwidth);
2522
2523 bw_used += bw_reserved;
2524 if (bw_used > max_bandwidth) {
2525 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2526 bw_used, max_bandwidth);
2527 return -ENOMEM;
2528 }
2529
2530 bw_table->bw_used = bw_used;
2531 return 0;
2532}
2533
2534static bool xhci_is_async_ep(unsigned int ep_type)
2535{
2536 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2537 ep_type != ISOC_IN_EP &&
2538 ep_type != INT_IN_EP);
2539}
2540
2541static bool xhci_is_sync_in_ep(unsigned int ep_type)
2542{
2543 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2544}
2545
2546static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2547{
2548 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2549
2550 if (ep_bw->ep_interval == 0)
2551 return SS_OVERHEAD_BURST +
2552 (ep_bw->mult * ep_bw->num_packets *
2553 (SS_OVERHEAD + mps));
2554 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2555 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2556 1 << ep_bw->ep_interval);
2557
2558}
2559
2560static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2561 struct xhci_bw_info *ep_bw,
2562 struct xhci_interval_bw_table *bw_table,
2563 struct usb_device *udev,
2564 struct xhci_virt_ep *virt_ep,
2565 struct xhci_tt_bw_info *tt_info)
2566{
2567 struct xhci_interval_bw *interval_bw;
2568 int normalized_interval;
2569
2570 if (xhci_is_async_ep(ep_bw->type))
2571 return;
2572
2573 if (udev->speed >= USB_SPEED_SUPER) {
2574 if (xhci_is_sync_in_ep(ep_bw->type))
2575 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2576 xhci_get_ss_bw_consumed(ep_bw);
2577 else
2578 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2579 xhci_get_ss_bw_consumed(ep_bw);
2580 return;
2581 }
2582
2583 /* SuperSpeed endpoints never get added to intervals in the table, so
2584 * this check is only valid for HS/FS/LS devices.
2585 */
2586 if (list_empty(&virt_ep->bw_endpoint_list))
2587 return;
2588 /* For LS/FS devices, we need to translate the interval expressed in
2589 * microframes to frames.
2590 */
2591 if (udev->speed == USB_SPEED_HIGH)
2592 normalized_interval = ep_bw->ep_interval;
2593 else
2594 normalized_interval = ep_bw->ep_interval - 3;
2595
2596 if (normalized_interval == 0)
2597 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2598 interval_bw = &bw_table->interval_bw[normalized_interval];
2599 interval_bw->num_packets -= ep_bw->num_packets;
2600 switch (udev->speed) {
2601 case USB_SPEED_LOW:
2602 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2603 break;
2604 case USB_SPEED_FULL:
2605 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2606 break;
2607 case USB_SPEED_HIGH:
2608 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2609 break;
2610 default:
2611 /* Should never happen because only LS/FS/HS endpoints will get
2612 * added to the endpoint list.
2613 */
2614 return;
2615 }
2616 if (tt_info)
2617 tt_info->active_eps -= 1;
2618 list_del_init(&virt_ep->bw_endpoint_list);
2619}
2620
2621static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2622 struct xhci_bw_info *ep_bw,
2623 struct xhci_interval_bw_table *bw_table,
2624 struct usb_device *udev,
2625 struct xhci_virt_ep *virt_ep,
2626 struct xhci_tt_bw_info *tt_info)
2627{
2628 struct xhci_interval_bw *interval_bw;
2629 struct xhci_virt_ep *smaller_ep;
2630 int normalized_interval;
2631
2632 if (xhci_is_async_ep(ep_bw->type))
2633 return;
2634
2635 if (udev->speed == USB_SPEED_SUPER) {
2636 if (xhci_is_sync_in_ep(ep_bw->type))
2637 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2638 xhci_get_ss_bw_consumed(ep_bw);
2639 else
2640 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2641 xhci_get_ss_bw_consumed(ep_bw);
2642 return;
2643 }
2644
2645 /* For LS/FS devices, we need to translate the interval expressed in
2646 * microframes to frames.
2647 */
2648 if (udev->speed == USB_SPEED_HIGH)
2649 normalized_interval = ep_bw->ep_interval;
2650 else
2651 normalized_interval = ep_bw->ep_interval - 3;
2652
2653 if (normalized_interval == 0)
2654 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2655 interval_bw = &bw_table->interval_bw[normalized_interval];
2656 interval_bw->num_packets += ep_bw->num_packets;
2657 switch (udev->speed) {
2658 case USB_SPEED_LOW:
2659 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2660 break;
2661 case USB_SPEED_FULL:
2662 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2663 break;
2664 case USB_SPEED_HIGH:
2665 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2666 break;
2667 default:
2668 /* Should never happen because only LS/FS/HS endpoints will get
2669 * added to the endpoint list.
2670 */
2671 return;
2672 }
2673
2674 if (tt_info)
2675 tt_info->active_eps += 1;
2676 /* Insert the endpoint into the list, largest max packet size first. */
2677 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2678 bw_endpoint_list) {
2679 if (ep_bw->max_packet_size >=
2680 smaller_ep->bw_info.max_packet_size) {
2681 /* Add the new ep before the smaller endpoint */
2682 list_add_tail(&virt_ep->bw_endpoint_list,
2683 &smaller_ep->bw_endpoint_list);
2684 return;
2685 }
2686 }
2687 /* Add the new endpoint at the end of the list. */
2688 list_add_tail(&virt_ep->bw_endpoint_list,
2689 &interval_bw->endpoints);
2690}
2691
2692void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2693 struct xhci_virt_device *virt_dev,
2694 int old_active_eps)
2695{
2696 struct xhci_root_port_bw_info *rh_bw_info;
2697 if (!virt_dev->tt_info)
2698 return;
2699
2700 rh_bw_info = &xhci->rh_bw[virt_dev->rhub_port->hw_portnum];
2701 if (old_active_eps == 0 &&
2702 virt_dev->tt_info->active_eps != 0) {
2703 rh_bw_info->num_active_tts += 1;
2704 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2705 } else if (old_active_eps != 0 &&
2706 virt_dev->tt_info->active_eps == 0) {
2707 rh_bw_info->num_active_tts -= 1;
2708 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2709 }
2710}
2711
2712static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2713 struct xhci_virt_device *virt_dev,
2714 struct xhci_container_ctx *in_ctx)
2715{
2716 struct xhci_bw_info ep_bw_info[31];
2717 int i;
2718 struct xhci_input_control_ctx *ctrl_ctx;
2719 int old_active_eps = 0;
2720
2721 if (virt_dev->tt_info)
2722 old_active_eps = virt_dev->tt_info->active_eps;
2723
2724 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2725 if (!ctrl_ctx) {
2726 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2727 __func__);
2728 return -ENOMEM;
2729 }
2730
2731 for (i = 0; i < 31; i++) {
2732 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2733 continue;
2734
2735 /* Make a copy of the BW info in case we need to revert this */
2736 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2737 sizeof(ep_bw_info[i]));
2738 /* Drop the endpoint from the interval table if the endpoint is
2739 * being dropped or changed.
2740 */
2741 if (EP_IS_DROPPED(ctrl_ctx, i))
2742 xhci_drop_ep_from_interval_table(xhci,
2743 &virt_dev->eps[i].bw_info,
2744 virt_dev->bw_table,
2745 virt_dev->udev,
2746 &virt_dev->eps[i],
2747 virt_dev->tt_info);
2748 }
2749 /* Overwrite the information stored in the endpoints' bw_info */
2750 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2751 for (i = 0; i < 31; i++) {
2752 /* Add any changed or added endpoints to the interval table */
2753 if (EP_IS_ADDED(ctrl_ctx, i))
2754 xhci_add_ep_to_interval_table(xhci,
2755 &virt_dev->eps[i].bw_info,
2756 virt_dev->bw_table,
2757 virt_dev->udev,
2758 &virt_dev->eps[i],
2759 virt_dev->tt_info);
2760 }
2761
2762 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2763 /* Ok, this fits in the bandwidth we have.
2764 * Update the number of active TTs.
2765 */
2766 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2767 return 0;
2768 }
2769
2770 /* We don't have enough bandwidth for this, revert the stored info. */
2771 for (i = 0; i < 31; i++) {
2772 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2773 continue;
2774
2775 /* Drop the new copies of any added or changed endpoints from
2776 * the interval table.
2777 */
2778 if (EP_IS_ADDED(ctrl_ctx, i)) {
2779 xhci_drop_ep_from_interval_table(xhci,
2780 &virt_dev->eps[i].bw_info,
2781 virt_dev->bw_table,
2782 virt_dev->udev,
2783 &virt_dev->eps[i],
2784 virt_dev->tt_info);
2785 }
2786 /* Revert the endpoint back to its old information */
2787 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2788 sizeof(ep_bw_info[i]));
2789 /* Add any changed or dropped endpoints back into the table */
2790 if (EP_IS_DROPPED(ctrl_ctx, i))
2791 xhci_add_ep_to_interval_table(xhci,
2792 &virt_dev->eps[i].bw_info,
2793 virt_dev->bw_table,
2794 virt_dev->udev,
2795 &virt_dev->eps[i],
2796 virt_dev->tt_info);
2797 }
2798 return -ENOMEM;
2799}
2800
2801/*
2802 * Synchronous XHCI stop endpoint helper. Issues the stop endpoint command and
2803 * waits for the command completion before returning. This does not call
2804 * xhci_handle_cmd_stop_ep(), which has additional handling for 'context error'
2805 * cases, along with transfer ring cleanup.
2806 *
2807 * xhci_stop_endpoint_sync() is intended to be utilized by clients that manage
2808 * their own transfer ring, such as offload situations.
2809 */
2810int xhci_stop_endpoint_sync(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, int suspend,
2811 gfp_t gfp_flags)
2812{
2813 struct xhci_command *command;
2814 unsigned long flags;
2815 int ret;
2816
2817 command = xhci_alloc_command(xhci, true, gfp_flags);
2818 if (!command)
2819 return -ENOMEM;
2820
2821 spin_lock_irqsave(&xhci->lock, flags);
2822 ret = xhci_queue_stop_endpoint(xhci, command, ep->vdev->slot_id,
2823 ep->ep_index, suspend);
2824 if (ret < 0) {
2825 spin_unlock_irqrestore(&xhci->lock, flags);
2826 goto out;
2827 }
2828
2829 xhci_ring_cmd_db(xhci);
2830 spin_unlock_irqrestore(&xhci->lock, flags);
2831
2832 wait_for_completion(command->completion);
2833
2834 /* No handling for COMP_CONTEXT_STATE_ERROR done at command completion*/
2835 if (command->status == COMP_COMMAND_ABORTED ||
2836 command->status == COMP_COMMAND_RING_STOPPED) {
2837 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
2838 ret = -ETIME;
2839 }
2840out:
2841 xhci_free_command(xhci, command);
2842
2843 return ret;
2844}
2845EXPORT_SYMBOL_GPL(xhci_stop_endpoint_sync);
2846
2847/* Issue a configure endpoint command or evaluate context command
2848 * and wait for it to finish.
2849 */
2850static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2851 struct usb_device *udev,
2852 struct xhci_command *command,
2853 bool ctx_change, bool must_succeed)
2854{
2855 int ret;
2856 unsigned long flags;
2857 struct xhci_input_control_ctx *ctrl_ctx;
2858 struct xhci_virt_device *virt_dev;
2859 struct xhci_slot_ctx *slot_ctx;
2860
2861 if (!command)
2862 return -EINVAL;
2863
2864 spin_lock_irqsave(&xhci->lock, flags);
2865
2866 if (xhci->xhc_state & XHCI_STATE_DYING) {
2867 spin_unlock_irqrestore(&xhci->lock, flags);
2868 return -ESHUTDOWN;
2869 }
2870
2871 virt_dev = xhci->devs[udev->slot_id];
2872
2873 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2874 if (!ctrl_ctx) {
2875 spin_unlock_irqrestore(&xhci->lock, flags);
2876 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2877 __func__);
2878 return -ENOMEM;
2879 }
2880
2881 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2882 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2883 spin_unlock_irqrestore(&xhci->lock, flags);
2884 xhci_warn(xhci, "Not enough host resources, "
2885 "active endpoint contexts = %u\n",
2886 xhci->num_active_eps);
2887 return -ENOMEM;
2888 }
2889 if ((xhci->quirks & XHCI_SW_BW_CHECKING) && !ctx_change &&
2890 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2891 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2892 xhci_free_host_resources(xhci, ctrl_ctx);
2893 spin_unlock_irqrestore(&xhci->lock, flags);
2894 xhci_warn(xhci, "Not enough bandwidth\n");
2895 return -ENOMEM;
2896 }
2897
2898 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2899
2900 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2901 trace_xhci_configure_endpoint(slot_ctx);
2902
2903 if (!ctx_change)
2904 ret = xhci_queue_configure_endpoint(xhci, command,
2905 command->in_ctx->dma,
2906 udev->slot_id, must_succeed);
2907 else
2908 ret = xhci_queue_evaluate_context(xhci, command,
2909 command->in_ctx->dma,
2910 udev->slot_id, must_succeed);
2911 if (ret < 0) {
2912 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2913 xhci_free_host_resources(xhci, ctrl_ctx);
2914 spin_unlock_irqrestore(&xhci->lock, flags);
2915 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2916 "FIXME allocate a new ring segment");
2917 return -ENOMEM;
2918 }
2919 xhci_ring_cmd_db(xhci);
2920 spin_unlock_irqrestore(&xhci->lock, flags);
2921
2922 /* Wait for the configure endpoint command to complete */
2923 wait_for_completion(command->completion);
2924
2925 if (!ctx_change)
2926 ret = xhci_configure_endpoint_result(xhci, udev,
2927 &command->status);
2928 else
2929 ret = xhci_evaluate_context_result(xhci, udev,
2930 &command->status);
2931
2932 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2933 spin_lock_irqsave(&xhci->lock, flags);
2934 /* If the command failed, remove the reserved resources.
2935 * Otherwise, clean up the estimate to include dropped eps.
2936 */
2937 if (ret)
2938 xhci_free_host_resources(xhci, ctrl_ctx);
2939 else
2940 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2941 spin_unlock_irqrestore(&xhci->lock, flags);
2942 }
2943 return ret;
2944}
2945
2946static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2947 struct xhci_virt_device *vdev, int i)
2948{
2949 struct xhci_virt_ep *ep = &vdev->eps[i];
2950
2951 if (ep->ep_state & EP_HAS_STREAMS) {
2952 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2953 xhci_get_endpoint_address(i));
2954 xhci_free_stream_info(xhci, ep->stream_info);
2955 ep->stream_info = NULL;
2956 ep->ep_state &= ~EP_HAS_STREAMS;
2957 }
2958}
2959
2960/* Called after one or more calls to xhci_add_endpoint() or
2961 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2962 * to call xhci_reset_bandwidth().
2963 *
2964 * Since we are in the middle of changing either configuration or
2965 * installing a new alt setting, the USB core won't allow URBs to be
2966 * enqueued for any endpoint on the old config or interface. Nothing
2967 * else should be touching the xhci->devs[slot_id] structure, so we
2968 * don't need to take the xhci->lock for manipulating that.
2969 */
2970int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2971{
2972 int i;
2973 int ret = 0;
2974 struct xhci_hcd *xhci;
2975 struct xhci_virt_device *virt_dev;
2976 struct xhci_input_control_ctx *ctrl_ctx;
2977 struct xhci_slot_ctx *slot_ctx;
2978 struct xhci_command *command;
2979
2980 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2981 if (ret <= 0)
2982 return ret;
2983 xhci = hcd_to_xhci(hcd);
2984 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2985 (xhci->xhc_state & XHCI_STATE_REMOVING))
2986 return -ENODEV;
2987
2988 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2989 virt_dev = xhci->devs[udev->slot_id];
2990
2991 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
2992 if (!command)
2993 return -ENOMEM;
2994
2995 command->in_ctx = virt_dev->in_ctx;
2996
2997 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2998 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2999 if (!ctrl_ctx) {
3000 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3001 __func__);
3002 ret = -ENOMEM;
3003 goto command_cleanup;
3004 }
3005 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3006 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
3007 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
3008
3009 /* Don't issue the command if there's no endpoints to update. */
3010 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
3011 ctrl_ctx->drop_flags == 0) {
3012 ret = 0;
3013 goto command_cleanup;
3014 }
3015 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
3016 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3017 for (i = 31; i >= 1; i--) {
3018 __le32 le32 = cpu_to_le32(BIT(i));
3019
3020 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
3021 || (ctrl_ctx->add_flags & le32) || i == 1) {
3022 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
3023 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
3024 break;
3025 }
3026 }
3027
3028 ret = xhci_configure_endpoint(xhci, udev, command,
3029 false, false);
3030 if (ret)
3031 /* Callee should call reset_bandwidth() */
3032 goto command_cleanup;
3033
3034 /* Free any rings that were dropped, but not changed. */
3035 for (i = 1; i < 31; i++) {
3036 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
3037 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
3038 xhci_free_endpoint_ring(xhci, virt_dev, i);
3039 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3040 }
3041 }
3042 xhci_zero_in_ctx(xhci, virt_dev);
3043 /*
3044 * Install any rings for completely new endpoints or changed endpoints,
3045 * and free any old rings from changed endpoints.
3046 */
3047 for (i = 1; i < 31; i++) {
3048 if (!virt_dev->eps[i].new_ring)
3049 continue;
3050 /* Only free the old ring if it exists.
3051 * It may not if this is the first add of an endpoint.
3052 */
3053 if (virt_dev->eps[i].ring) {
3054 xhci_free_endpoint_ring(xhci, virt_dev, i);
3055 }
3056 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3057 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
3058 virt_dev->eps[i].new_ring = NULL;
3059 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
3060 }
3061command_cleanup:
3062 kfree(command->completion);
3063 kfree(command);
3064
3065 return ret;
3066}
3067EXPORT_SYMBOL_GPL(xhci_check_bandwidth);
3068
3069void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3070{
3071 struct xhci_hcd *xhci;
3072 struct xhci_virt_device *virt_dev;
3073 int i, ret;
3074
3075 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3076 if (ret <= 0)
3077 return;
3078 xhci = hcd_to_xhci(hcd);
3079
3080 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3081 virt_dev = xhci->devs[udev->slot_id];
3082 /* Free any rings allocated for added endpoints */
3083 for (i = 0; i < 31; i++) {
3084 if (virt_dev->eps[i].new_ring) {
3085 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3086 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3087 virt_dev->eps[i].new_ring = NULL;
3088 }
3089 }
3090 xhci_zero_in_ctx(xhci, virt_dev);
3091}
3092EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
3093
3094static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3095 struct xhci_container_ctx *in_ctx,
3096 struct xhci_container_ctx *out_ctx,
3097 struct xhci_input_control_ctx *ctrl_ctx,
3098 u32 add_flags, u32 drop_flags)
3099{
3100 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3101 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3102 xhci_slot_copy(xhci, in_ctx, out_ctx);
3103 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3104}
3105
3106static void xhci_endpoint_disable(struct usb_hcd *hcd,
3107 struct usb_host_endpoint *host_ep)
3108{
3109 struct xhci_hcd *xhci;
3110 struct xhci_virt_device *vdev;
3111 struct xhci_virt_ep *ep;
3112 struct usb_device *udev;
3113 unsigned long flags;
3114 unsigned int ep_index;
3115
3116 xhci = hcd_to_xhci(hcd);
3117rescan:
3118 spin_lock_irqsave(&xhci->lock, flags);
3119
3120 udev = (struct usb_device *)host_ep->hcpriv;
3121 if (!udev || !udev->slot_id)
3122 goto done;
3123
3124 vdev = xhci->devs[udev->slot_id];
3125 if (!vdev)
3126 goto done;
3127
3128 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3129 ep = &vdev->eps[ep_index];
3130
3131 /* wait for hub_tt_work to finish clearing hub TT */
3132 if (ep->ep_state & EP_CLEARING_TT) {
3133 spin_unlock_irqrestore(&xhci->lock, flags);
3134 schedule_timeout_uninterruptible(1);
3135 goto rescan;
3136 }
3137
3138 if (ep->ep_state)
3139 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3140 ep->ep_state);
3141done:
3142 host_ep->hcpriv = NULL;
3143 spin_unlock_irqrestore(&xhci->lock, flags);
3144}
3145
3146/*
3147 * Called after usb core issues a clear halt control message.
3148 * The host side of the halt should already be cleared by a reset endpoint
3149 * command issued when the STALL event was received.
3150 *
3151 * The reset endpoint command may only be issued to endpoints in the halted
3152 * state. For software that wishes to reset the data toggle or sequence number
3153 * of an endpoint that isn't in the halted state this function will issue a
3154 * configure endpoint command with the Drop and Add bits set for the target
3155 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3156 *
3157 * vdev may be lost due to xHC restore error and re-initialization during S3/S4
3158 * resume. A new vdev will be allocated later by xhci_discover_or_reset_device()
3159 */
3160
3161static void xhci_endpoint_reset(struct usb_hcd *hcd,
3162 struct usb_host_endpoint *host_ep)
3163{
3164 struct xhci_hcd *xhci;
3165 struct usb_device *udev;
3166 struct xhci_virt_device *vdev;
3167 struct xhci_virt_ep *ep;
3168 struct xhci_input_control_ctx *ctrl_ctx;
3169 struct xhci_command *stop_cmd, *cfg_cmd;
3170 unsigned int ep_index;
3171 unsigned long flags;
3172 u32 ep_flag;
3173 int err;
3174
3175 xhci = hcd_to_xhci(hcd);
3176 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3177
3178 /*
3179 * Usb core assumes a max packet value for ep0 on FS devices until the
3180 * real value is read from the descriptor. Core resets Ep0 if values
3181 * mismatch. Reconfigure the xhci ep0 endpoint context here in that case
3182 */
3183 if (usb_endpoint_xfer_control(&host_ep->desc) && ep_index == 0) {
3184
3185 udev = container_of(host_ep, struct usb_device, ep0);
3186 if (udev->speed != USB_SPEED_FULL || !udev->slot_id)
3187 return;
3188
3189 vdev = xhci->devs[udev->slot_id];
3190 if (!vdev || vdev->udev != udev)
3191 return;
3192
3193 xhci_check_ep0_maxpacket(xhci, vdev);
3194
3195 /* Nothing else should be done here for ep0 during ep reset */
3196 return;
3197 }
3198
3199 if (!host_ep->hcpriv)
3200 return;
3201 udev = (struct usb_device *) host_ep->hcpriv;
3202 vdev = xhci->devs[udev->slot_id];
3203
3204 if (!udev->slot_id || !vdev)
3205 return;
3206
3207 ep = &vdev->eps[ep_index];
3208
3209 /* Bail out if toggle is already being cleared by a endpoint reset */
3210 spin_lock_irqsave(&xhci->lock, flags);
3211 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3212 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3213 spin_unlock_irqrestore(&xhci->lock, flags);
3214 return;
3215 }
3216 spin_unlock_irqrestore(&xhci->lock, flags);
3217 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3218 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3219 usb_endpoint_xfer_isoc(&host_ep->desc))
3220 return;
3221
3222 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3223
3224 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3225 return;
3226
3227 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3228 if (!stop_cmd)
3229 return;
3230
3231 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3232 if (!cfg_cmd)
3233 goto cleanup;
3234
3235 spin_lock_irqsave(&xhci->lock, flags);
3236
3237 /* block queuing new trbs and ringing ep doorbell */
3238 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3239
3240 /*
3241 * Make sure endpoint ring is empty before resetting the toggle/seq.
3242 * Driver is required to synchronously cancel all transfer request.
3243 * Stop the endpoint to force xHC to update the output context
3244 */
3245
3246 if (!list_empty(&ep->ring->td_list)) {
3247 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3248 spin_unlock_irqrestore(&xhci->lock, flags);
3249 xhci_free_command(xhci, cfg_cmd);
3250 goto cleanup;
3251 }
3252
3253 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3254 ep_index, 0);
3255 if (err < 0) {
3256 spin_unlock_irqrestore(&xhci->lock, flags);
3257 xhci_free_command(xhci, cfg_cmd);
3258 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3259 __func__, err);
3260 goto cleanup;
3261 }
3262
3263 xhci_ring_cmd_db(xhci);
3264 spin_unlock_irqrestore(&xhci->lock, flags);
3265
3266 wait_for_completion(stop_cmd->completion);
3267
3268 spin_lock_irqsave(&xhci->lock, flags);
3269
3270 /* config ep command clears toggle if add and drop ep flags are set */
3271 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3272 if (!ctrl_ctx) {
3273 spin_unlock_irqrestore(&xhci->lock, flags);
3274 xhci_free_command(xhci, cfg_cmd);
3275 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3276 __func__);
3277 goto cleanup;
3278 }
3279
3280 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3281 ctrl_ctx, ep_flag, ep_flag);
3282 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3283
3284 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3285 udev->slot_id, false);
3286 if (err < 0) {
3287 spin_unlock_irqrestore(&xhci->lock, flags);
3288 xhci_free_command(xhci, cfg_cmd);
3289 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3290 __func__, err);
3291 goto cleanup;
3292 }
3293
3294 xhci_ring_cmd_db(xhci);
3295 spin_unlock_irqrestore(&xhci->lock, flags);
3296
3297 wait_for_completion(cfg_cmd->completion);
3298
3299 xhci_free_command(xhci, cfg_cmd);
3300cleanup:
3301 xhci_free_command(xhci, stop_cmd);
3302 spin_lock_irqsave(&xhci->lock, flags);
3303 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3304 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3305 spin_unlock_irqrestore(&xhci->lock, flags);
3306}
3307
3308static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3309 struct usb_device *udev, struct usb_host_endpoint *ep,
3310 unsigned int slot_id)
3311{
3312 int ret;
3313 unsigned int ep_index;
3314 unsigned int ep_state;
3315
3316 if (!ep)
3317 return -EINVAL;
3318 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3319 if (ret <= 0)
3320 return ret ? ret : -EINVAL;
3321 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3322 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3323 " descriptor for ep 0x%x does not support streams\n",
3324 ep->desc.bEndpointAddress);
3325 return -EINVAL;
3326 }
3327
3328 ep_index = xhci_get_endpoint_index(&ep->desc);
3329 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3330 if (ep_state & EP_HAS_STREAMS ||
3331 ep_state & EP_GETTING_STREAMS) {
3332 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3333 "already has streams set up.\n",
3334 ep->desc.bEndpointAddress);
3335 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3336 "dynamic stream context array reallocation.\n");
3337 return -EINVAL;
3338 }
3339 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3340 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3341 "endpoint 0x%x; URBs are pending.\n",
3342 ep->desc.bEndpointAddress);
3343 return -EINVAL;
3344 }
3345 return 0;
3346}
3347
3348static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3349 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3350{
3351 unsigned int max_streams;
3352
3353 /* The stream context array size must be a power of two */
3354 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3355 /*
3356 * Find out how many primary stream array entries the host controller
3357 * supports. Later we may use secondary stream arrays (similar to 2nd
3358 * level page entries), but that's an optional feature for xHCI host
3359 * controllers. xHCs must support at least 4 stream IDs.
3360 */
3361 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3362 if (*num_stream_ctxs > max_streams) {
3363 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3364 max_streams);
3365 *num_stream_ctxs = max_streams;
3366 *num_streams = max_streams;
3367 }
3368}
3369
3370/* Returns an error code if one of the endpoint already has streams.
3371 * This does not change any data structures, it only checks and gathers
3372 * information.
3373 */
3374static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3375 struct usb_device *udev,
3376 struct usb_host_endpoint **eps, unsigned int num_eps,
3377 unsigned int *num_streams, u32 *changed_ep_bitmask)
3378{
3379 unsigned int max_streams;
3380 unsigned int endpoint_flag;
3381 int i;
3382 int ret;
3383
3384 for (i = 0; i < num_eps; i++) {
3385 ret = xhci_check_streams_endpoint(xhci, udev,
3386 eps[i], udev->slot_id);
3387 if (ret < 0)
3388 return ret;
3389
3390 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3391 if (max_streams < (*num_streams - 1)) {
3392 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3393 eps[i]->desc.bEndpointAddress,
3394 max_streams);
3395 *num_streams = max_streams+1;
3396 }
3397
3398 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3399 if (*changed_ep_bitmask & endpoint_flag)
3400 return -EINVAL;
3401 *changed_ep_bitmask |= endpoint_flag;
3402 }
3403 return 0;
3404}
3405
3406static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3407 struct usb_device *udev,
3408 struct usb_host_endpoint **eps, unsigned int num_eps)
3409{
3410 u32 changed_ep_bitmask = 0;
3411 unsigned int slot_id;
3412 unsigned int ep_index;
3413 unsigned int ep_state;
3414 int i;
3415
3416 slot_id = udev->slot_id;
3417 if (!xhci->devs[slot_id])
3418 return 0;
3419
3420 for (i = 0; i < num_eps; i++) {
3421 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3422 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3423 /* Are streams already being freed for the endpoint? */
3424 if (ep_state & EP_GETTING_NO_STREAMS) {
3425 xhci_warn(xhci, "WARN Can't disable streams for "
3426 "endpoint 0x%x, "
3427 "streams are being disabled already\n",
3428 eps[i]->desc.bEndpointAddress);
3429 return 0;
3430 }
3431 /* Are there actually any streams to free? */
3432 if (!(ep_state & EP_HAS_STREAMS) &&
3433 !(ep_state & EP_GETTING_STREAMS)) {
3434 xhci_warn(xhci, "WARN Can't disable streams for "
3435 "endpoint 0x%x, "
3436 "streams are already disabled!\n",
3437 eps[i]->desc.bEndpointAddress);
3438 xhci_warn(xhci, "WARN xhci_free_streams() called "
3439 "with non-streams endpoint\n");
3440 return 0;
3441 }
3442 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3443 }
3444 return changed_ep_bitmask;
3445}
3446
3447/*
3448 * The USB device drivers use this function (through the HCD interface in USB
3449 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3450 * coordinate mass storage command queueing across multiple endpoints (basically
3451 * a stream ID == a task ID).
3452 *
3453 * Setting up streams involves allocating the same size stream context array
3454 * for each endpoint and issuing a configure endpoint command for all endpoints.
3455 *
3456 * Don't allow the call to succeed if one endpoint only supports one stream
3457 * (which means it doesn't support streams at all).
3458 *
3459 * Drivers may get less stream IDs than they asked for, if the host controller
3460 * hardware or endpoints claim they can't support the number of requested
3461 * stream IDs.
3462 */
3463static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3464 struct usb_host_endpoint **eps, unsigned int num_eps,
3465 unsigned int num_streams, gfp_t mem_flags)
3466{
3467 int i, ret;
3468 struct xhci_hcd *xhci;
3469 struct xhci_virt_device *vdev;
3470 struct xhci_command *config_cmd;
3471 struct xhci_input_control_ctx *ctrl_ctx;
3472 unsigned int ep_index;
3473 unsigned int num_stream_ctxs;
3474 unsigned int max_packet;
3475 unsigned long flags;
3476 u32 changed_ep_bitmask = 0;
3477
3478 if (!eps)
3479 return -EINVAL;
3480
3481 /* Add one to the number of streams requested to account for
3482 * stream 0 that is reserved for xHCI usage.
3483 */
3484 num_streams += 1;
3485 xhci = hcd_to_xhci(hcd);
3486 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3487 num_streams);
3488
3489 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3490 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3491 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3492 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3493 return -ENOSYS;
3494 }
3495
3496 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3497 if (!config_cmd)
3498 return -ENOMEM;
3499
3500 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3501 if (!ctrl_ctx) {
3502 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3503 __func__);
3504 xhci_free_command(xhci, config_cmd);
3505 return -ENOMEM;
3506 }
3507
3508 /* Check to make sure all endpoints are not already configured for
3509 * streams. While we're at it, find the maximum number of streams that
3510 * all the endpoints will support and check for duplicate endpoints.
3511 */
3512 spin_lock_irqsave(&xhci->lock, flags);
3513 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3514 num_eps, &num_streams, &changed_ep_bitmask);
3515 if (ret < 0) {
3516 xhci_free_command(xhci, config_cmd);
3517 spin_unlock_irqrestore(&xhci->lock, flags);
3518 return ret;
3519 }
3520 if (num_streams <= 1) {
3521 xhci_warn(xhci, "WARN: endpoints can't handle "
3522 "more than one stream.\n");
3523 xhci_free_command(xhci, config_cmd);
3524 spin_unlock_irqrestore(&xhci->lock, flags);
3525 return -EINVAL;
3526 }
3527 vdev = xhci->devs[udev->slot_id];
3528 /* Mark each endpoint as being in transition, so
3529 * xhci_urb_enqueue() will reject all URBs.
3530 */
3531 for (i = 0; i < num_eps; i++) {
3532 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3533 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3534 }
3535 spin_unlock_irqrestore(&xhci->lock, flags);
3536
3537 /* Setup internal data structures and allocate HW data structures for
3538 * streams (but don't install the HW structures in the input context
3539 * until we're sure all memory allocation succeeded).
3540 */
3541 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3542 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3543 num_stream_ctxs, num_streams);
3544
3545 for (i = 0; i < num_eps; i++) {
3546 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3547 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3548 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3549 num_stream_ctxs,
3550 num_streams,
3551 max_packet, mem_flags);
3552 if (!vdev->eps[ep_index].stream_info)
3553 goto cleanup;
3554 /* Set maxPstreams in endpoint context and update deq ptr to
3555 * point to stream context array. FIXME
3556 */
3557 }
3558
3559 /* Set up the input context for a configure endpoint command. */
3560 for (i = 0; i < num_eps; i++) {
3561 struct xhci_ep_ctx *ep_ctx;
3562
3563 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3564 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3565
3566 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3567 vdev->out_ctx, ep_index);
3568 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3569 vdev->eps[ep_index].stream_info);
3570 }
3571 /* Tell the HW to drop its old copy of the endpoint context info
3572 * and add the updated copy from the input context.
3573 */
3574 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3575 vdev->out_ctx, ctrl_ctx,
3576 changed_ep_bitmask, changed_ep_bitmask);
3577
3578 /* Issue and wait for the configure endpoint command */
3579 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3580 false, false);
3581
3582 /* xHC rejected the configure endpoint command for some reason, so we
3583 * leave the old ring intact and free our internal streams data
3584 * structure.
3585 */
3586 if (ret < 0)
3587 goto cleanup;
3588
3589 spin_lock_irqsave(&xhci->lock, flags);
3590 for (i = 0; i < num_eps; i++) {
3591 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3592 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3593 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3594 udev->slot_id, ep_index);
3595 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3596 }
3597 xhci_free_command(xhci, config_cmd);
3598 spin_unlock_irqrestore(&xhci->lock, flags);
3599
3600 for (i = 0; i < num_eps; i++) {
3601 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3602 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3603 }
3604 /* Subtract 1 for stream 0, which drivers can't use */
3605 return num_streams - 1;
3606
3607cleanup:
3608 /* If it didn't work, free the streams! */
3609 for (i = 0; i < num_eps; i++) {
3610 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3611 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3612 vdev->eps[ep_index].stream_info = NULL;
3613 /* FIXME Unset maxPstreams in endpoint context and
3614 * update deq ptr to point to normal string ring.
3615 */
3616 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3617 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3618 xhci_endpoint_zero(xhci, vdev, eps[i]);
3619 }
3620 xhci_free_command(xhci, config_cmd);
3621 return -ENOMEM;
3622}
3623
3624/* Transition the endpoint from using streams to being a "normal" endpoint
3625 * without streams.
3626 *
3627 * Modify the endpoint context state, submit a configure endpoint command,
3628 * and free all endpoint rings for streams if that completes successfully.
3629 */
3630static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3631 struct usb_host_endpoint **eps, unsigned int num_eps,
3632 gfp_t mem_flags)
3633{
3634 int i, ret;
3635 struct xhci_hcd *xhci;
3636 struct xhci_virt_device *vdev;
3637 struct xhci_command *command;
3638 struct xhci_input_control_ctx *ctrl_ctx;
3639 unsigned int ep_index;
3640 unsigned long flags;
3641 u32 changed_ep_bitmask;
3642
3643 xhci = hcd_to_xhci(hcd);
3644 vdev = xhci->devs[udev->slot_id];
3645
3646 /* Set up a configure endpoint command to remove the streams rings */
3647 spin_lock_irqsave(&xhci->lock, flags);
3648 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3649 udev, eps, num_eps);
3650 if (changed_ep_bitmask == 0) {
3651 spin_unlock_irqrestore(&xhci->lock, flags);
3652 return -EINVAL;
3653 }
3654
3655 /* Use the xhci_command structure from the first endpoint. We may have
3656 * allocated too many, but the driver may call xhci_free_streams() for
3657 * each endpoint it grouped into one call to xhci_alloc_streams().
3658 */
3659 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3660 command = vdev->eps[ep_index].stream_info->free_streams_command;
3661 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3662 if (!ctrl_ctx) {
3663 spin_unlock_irqrestore(&xhci->lock, flags);
3664 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3665 __func__);
3666 return -EINVAL;
3667 }
3668
3669 for (i = 0; i < num_eps; i++) {
3670 struct xhci_ep_ctx *ep_ctx;
3671
3672 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3673 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3674 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3675 EP_GETTING_NO_STREAMS;
3676
3677 xhci_endpoint_copy(xhci, command->in_ctx,
3678 vdev->out_ctx, ep_index);
3679 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3680 &vdev->eps[ep_index]);
3681 }
3682 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3683 vdev->out_ctx, ctrl_ctx,
3684 changed_ep_bitmask, changed_ep_bitmask);
3685 spin_unlock_irqrestore(&xhci->lock, flags);
3686
3687 /* Issue and wait for the configure endpoint command,
3688 * which must succeed.
3689 */
3690 ret = xhci_configure_endpoint(xhci, udev, command,
3691 false, true);
3692
3693 /* xHC rejected the configure endpoint command for some reason, so we
3694 * leave the streams rings intact.
3695 */
3696 if (ret < 0)
3697 return ret;
3698
3699 spin_lock_irqsave(&xhci->lock, flags);
3700 for (i = 0; i < num_eps; i++) {
3701 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3702 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3703 vdev->eps[ep_index].stream_info = NULL;
3704 /* FIXME Unset maxPstreams in endpoint context and
3705 * update deq ptr to point to normal string ring.
3706 */
3707 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3708 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3709 }
3710 spin_unlock_irqrestore(&xhci->lock, flags);
3711
3712 return 0;
3713}
3714
3715/*
3716 * Deletes endpoint resources for endpoints that were active before a Reset
3717 * Device command, or a Disable Slot command. The Reset Device command leaves
3718 * the control endpoint intact, whereas the Disable Slot command deletes it.
3719 *
3720 * Must be called with xhci->lock held.
3721 */
3722void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3723 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3724{
3725 int i;
3726 unsigned int num_dropped_eps = 0;
3727 unsigned int drop_flags = 0;
3728
3729 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3730 if (virt_dev->eps[i].ring) {
3731 drop_flags |= 1 << i;
3732 num_dropped_eps++;
3733 }
3734 }
3735 xhci->num_active_eps -= num_dropped_eps;
3736 if (num_dropped_eps)
3737 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3738 "Dropped %u ep ctxs, flags = 0x%x, "
3739 "%u now active.",
3740 num_dropped_eps, drop_flags,
3741 xhci->num_active_eps);
3742}
3743
3744static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
3745
3746/*
3747 * This submits a Reset Device Command, which will set the device state to 0,
3748 * set the device address to 0, and disable all the endpoints except the default
3749 * control endpoint. The USB core should come back and call
3750 * xhci_address_device(), and then re-set up the configuration. If this is
3751 * called because of a usb_reset_and_verify_device(), then the old alternate
3752 * settings will be re-installed through the normal bandwidth allocation
3753 * functions.
3754 *
3755 * Wait for the Reset Device command to finish. Remove all structures
3756 * associated with the endpoints that were disabled. Clear the input device
3757 * structure? Reset the control endpoint 0 max packet size?
3758 *
3759 * If the virt_dev to be reset does not exist or does not match the udev,
3760 * it means the device is lost, possibly due to the xHC restore error and
3761 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3762 * re-allocate the device.
3763 */
3764static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3765 struct usb_device *udev)
3766{
3767 int ret, i;
3768 unsigned long flags;
3769 struct xhci_hcd *xhci;
3770 unsigned int slot_id;
3771 struct xhci_virt_device *virt_dev;
3772 struct xhci_command *reset_device_cmd;
3773 struct xhci_slot_ctx *slot_ctx;
3774 int old_active_eps = 0;
3775
3776 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3777 if (ret <= 0)
3778 return ret;
3779 xhci = hcd_to_xhci(hcd);
3780 slot_id = udev->slot_id;
3781 virt_dev = xhci->devs[slot_id];
3782 if (!virt_dev) {
3783 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3784 "not exist. Re-allocate the device\n", slot_id);
3785 ret = xhci_alloc_dev(hcd, udev);
3786 if (ret == 1)
3787 return 0;
3788 else
3789 return -EINVAL;
3790 }
3791
3792 if (virt_dev->tt_info)
3793 old_active_eps = virt_dev->tt_info->active_eps;
3794
3795 if (virt_dev->udev != udev) {
3796 /* If the virt_dev and the udev does not match, this virt_dev
3797 * may belong to another udev.
3798 * Re-allocate the device.
3799 */
3800 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3801 "not match the udev. Re-allocate the device\n",
3802 slot_id);
3803 ret = xhci_alloc_dev(hcd, udev);
3804 if (ret == 1)
3805 return 0;
3806 else
3807 return -EINVAL;
3808 }
3809
3810 /* If device is not setup, there is no point in resetting it */
3811 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3812 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3813 SLOT_STATE_DISABLED)
3814 return 0;
3815
3816 if (xhci->quirks & XHCI_ETRON_HOST) {
3817 /*
3818 * Obtaining a new device slot to inform the xHCI host that
3819 * the USB device has been reset.
3820 */
3821 ret = xhci_disable_slot(xhci, udev->slot_id);
3822 xhci_free_virt_device(xhci, udev->slot_id);
3823 if (!ret) {
3824 ret = xhci_alloc_dev(hcd, udev);
3825 if (ret == 1)
3826 ret = 0;
3827 else
3828 ret = -EINVAL;
3829 }
3830 return ret;
3831 }
3832
3833 trace_xhci_discover_or_reset_device(slot_ctx);
3834
3835 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3836 /* Allocate the command structure that holds the struct completion.
3837 * Assume we're in process context, since the normal device reset
3838 * process has to wait for the device anyway. Storage devices are
3839 * reset as part of error handling, so use GFP_NOIO instead of
3840 * GFP_KERNEL.
3841 */
3842 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3843 if (!reset_device_cmd) {
3844 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3845 return -ENOMEM;
3846 }
3847
3848 /* Attempt to submit the Reset Device command to the command ring */
3849 spin_lock_irqsave(&xhci->lock, flags);
3850
3851 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3852 if (ret) {
3853 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3854 spin_unlock_irqrestore(&xhci->lock, flags);
3855 goto command_cleanup;
3856 }
3857 xhci_ring_cmd_db(xhci);
3858 spin_unlock_irqrestore(&xhci->lock, flags);
3859
3860 /* Wait for the Reset Device command to finish */
3861 wait_for_completion(reset_device_cmd->completion);
3862
3863 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3864 * unless we tried to reset a slot ID that wasn't enabled,
3865 * or the device wasn't in the addressed or configured state.
3866 */
3867 ret = reset_device_cmd->status;
3868 switch (ret) {
3869 case COMP_COMMAND_ABORTED:
3870 case COMP_COMMAND_RING_STOPPED:
3871 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3872 ret = -ETIME;
3873 goto command_cleanup;
3874 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3875 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3876 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3877 slot_id,
3878 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3879 xhci_dbg(xhci, "Not freeing device rings.\n");
3880 /* Don't treat this as an error. May change my mind later. */
3881 ret = 0;
3882 goto command_cleanup;
3883 case COMP_SUCCESS:
3884 xhci_dbg(xhci, "Successful reset device command.\n");
3885 break;
3886 default:
3887 if (xhci_is_vendor_info_code(xhci, ret))
3888 break;
3889 xhci_warn(xhci, "Unknown completion code %u for "
3890 "reset device command.\n", ret);
3891 ret = -EINVAL;
3892 goto command_cleanup;
3893 }
3894
3895 /* Free up host controller endpoint resources */
3896 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3897 spin_lock_irqsave(&xhci->lock, flags);
3898 /* Don't delete the default control endpoint resources */
3899 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3900 spin_unlock_irqrestore(&xhci->lock, flags);
3901 }
3902
3903 /* Everything but endpoint 0 is disabled, so free the rings. */
3904 for (i = 1; i < 31; i++) {
3905 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3906
3907 if (ep->ep_state & EP_HAS_STREAMS) {
3908 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3909 xhci_get_endpoint_address(i));
3910 xhci_free_stream_info(xhci, ep->stream_info);
3911 ep->stream_info = NULL;
3912 ep->ep_state &= ~EP_HAS_STREAMS;
3913 }
3914
3915 if (ep->ring) {
3916 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3917 xhci_free_endpoint_ring(xhci, virt_dev, i);
3918 }
3919 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3920 xhci_drop_ep_from_interval_table(xhci,
3921 &virt_dev->eps[i].bw_info,
3922 virt_dev->bw_table,
3923 udev,
3924 &virt_dev->eps[i],
3925 virt_dev->tt_info);
3926 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3927 }
3928 /* If necessary, update the number of active TTs on this root port */
3929 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3930 virt_dev->flags = 0;
3931 ret = 0;
3932
3933command_cleanup:
3934 xhci_free_command(xhci, reset_device_cmd);
3935 return ret;
3936}
3937
3938/*
3939 * At this point, the struct usb_device is about to go away, the device has
3940 * disconnected, and all traffic has been stopped and the endpoints have been
3941 * disabled. Free any HC data structures associated with that device.
3942 */
3943static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3944{
3945 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3946 struct xhci_virt_device *virt_dev;
3947 struct xhci_slot_ctx *slot_ctx;
3948 unsigned long flags;
3949 int i, ret;
3950
3951 /*
3952 * We called pm_runtime_get_noresume when the device was attached.
3953 * Decrement the counter here to allow controller to runtime suspend
3954 * if no devices remain.
3955 */
3956 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3957 pm_runtime_put_noidle(hcd->self.controller);
3958
3959 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3960 /* If the host is halted due to driver unload, we still need to free the
3961 * device.
3962 */
3963 if (ret <= 0 && ret != -ENODEV)
3964 return;
3965
3966 virt_dev = xhci->devs[udev->slot_id];
3967 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3968 trace_xhci_free_dev(slot_ctx);
3969
3970 /* Stop any wayward timer functions (which may grab the lock) */
3971 for (i = 0; i < 31; i++)
3972 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3973 virt_dev->udev = NULL;
3974 xhci_disable_slot(xhci, udev->slot_id);
3975
3976 spin_lock_irqsave(&xhci->lock, flags);
3977 xhci_free_virt_device(xhci, udev->slot_id);
3978 spin_unlock_irqrestore(&xhci->lock, flags);
3979
3980}
3981
3982int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3983{
3984 struct xhci_command *command;
3985 unsigned long flags;
3986 u32 state;
3987 int ret;
3988
3989 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3990 if (!command)
3991 return -ENOMEM;
3992
3993 xhci_debugfs_remove_slot(xhci, slot_id);
3994
3995 spin_lock_irqsave(&xhci->lock, flags);
3996 /* Don't disable the slot if the host controller is dead. */
3997 state = readl(&xhci->op_regs->status);
3998 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3999 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4000 spin_unlock_irqrestore(&xhci->lock, flags);
4001 kfree(command);
4002 return -ENODEV;
4003 }
4004
4005 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
4006 slot_id);
4007 if (ret) {
4008 spin_unlock_irqrestore(&xhci->lock, flags);
4009 kfree(command);
4010 return ret;
4011 }
4012 xhci_ring_cmd_db(xhci);
4013 spin_unlock_irqrestore(&xhci->lock, flags);
4014
4015 wait_for_completion(command->completion);
4016
4017 if (command->status != COMP_SUCCESS)
4018 xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
4019 slot_id, command->status);
4020
4021 xhci_free_command(xhci, command);
4022
4023 return 0;
4024}
4025
4026/*
4027 * Checks if we have enough host controller resources for the default control
4028 * endpoint.
4029 *
4030 * Must be called with xhci->lock held.
4031 */
4032static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
4033{
4034 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
4035 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4036 "Not enough ep ctxs: "
4037 "%u active, need to add 1, limit is %u.",
4038 xhci->num_active_eps, xhci->limit_active_eps);
4039 return -ENOMEM;
4040 }
4041 xhci->num_active_eps += 1;
4042 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4043 "Adding 1 ep ctx, %u now active.",
4044 xhci->num_active_eps);
4045 return 0;
4046}
4047
4048
4049/*
4050 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
4051 * timed out, or allocating memory failed. Returns 1 on success.
4052 */
4053int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4054{
4055 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4056 struct xhci_virt_device *vdev;
4057 struct xhci_slot_ctx *slot_ctx;
4058 unsigned long flags;
4059 int ret, slot_id;
4060 struct xhci_command *command;
4061
4062 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4063 if (!command)
4064 return 0;
4065
4066 spin_lock_irqsave(&xhci->lock, flags);
4067 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
4068 if (ret) {
4069 spin_unlock_irqrestore(&xhci->lock, flags);
4070 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
4071 xhci_free_command(xhci, command);
4072 return 0;
4073 }
4074 xhci_ring_cmd_db(xhci);
4075 spin_unlock_irqrestore(&xhci->lock, flags);
4076
4077 wait_for_completion(command->completion);
4078 slot_id = command->slot_id;
4079
4080 if (!slot_id || command->status != COMP_SUCCESS) {
4081 xhci_err(xhci, "Error while assigning device slot ID: %s\n",
4082 xhci_trb_comp_code_string(command->status));
4083 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4084 HCS_MAX_SLOTS(
4085 readl(&xhci->cap_regs->hcs_params1)));
4086 xhci_free_command(xhci, command);
4087 return 0;
4088 }
4089
4090 xhci_free_command(xhci, command);
4091
4092 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4093 spin_lock_irqsave(&xhci->lock, flags);
4094 ret = xhci_reserve_host_control_ep_resources(xhci);
4095 if (ret) {
4096 spin_unlock_irqrestore(&xhci->lock, flags);
4097 xhci_warn(xhci, "Not enough host resources, "
4098 "active endpoint contexts = %u\n",
4099 xhci->num_active_eps);
4100 goto disable_slot;
4101 }
4102 spin_unlock_irqrestore(&xhci->lock, flags);
4103 }
4104 /* Use GFP_NOIO, since this function can be called from
4105 * xhci_discover_or_reset_device(), which may be called as part of
4106 * mass storage driver error handling.
4107 */
4108 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4109 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4110 goto disable_slot;
4111 }
4112 vdev = xhci->devs[slot_id];
4113 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4114 trace_xhci_alloc_dev(slot_ctx);
4115
4116 udev->slot_id = slot_id;
4117
4118 xhci_debugfs_create_slot(xhci, slot_id);
4119
4120 /*
4121 * If resetting upon resume, we can't put the controller into runtime
4122 * suspend if there is a device attached.
4123 */
4124 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4125 pm_runtime_get_noresume(hcd->self.controller);
4126
4127 /* Is this a LS or FS device under a HS hub? */
4128 /* Hub or peripherial? */
4129 return 1;
4130
4131disable_slot:
4132 xhci_disable_slot(xhci, udev->slot_id);
4133 xhci_free_virt_device(xhci, udev->slot_id);
4134
4135 return 0;
4136}
4137
4138/**
4139 * xhci_setup_device - issues an Address Device command to assign a unique
4140 * USB bus address.
4141 * @hcd: USB host controller data structure.
4142 * @udev: USB dev structure representing the connected device.
4143 * @setup: Enum specifying setup mode: address only or with context.
4144 * @timeout_ms: Max wait time (ms) for the command operation to complete.
4145 *
4146 * Return: 0 if successful; otherwise, negative error code.
4147 */
4148static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4149 enum xhci_setup_dev setup, unsigned int timeout_ms)
4150{
4151 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4152 unsigned long flags;
4153 struct xhci_virt_device *virt_dev;
4154 int ret = 0;
4155 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4156 struct xhci_slot_ctx *slot_ctx;
4157 struct xhci_input_control_ctx *ctrl_ctx;
4158 u64 temp_64;
4159 struct xhci_command *command = NULL;
4160
4161 mutex_lock(&xhci->mutex);
4162
4163 if (xhci->xhc_state) { /* dying, removing or halted */
4164 ret = -ESHUTDOWN;
4165 goto out;
4166 }
4167
4168 if (!udev->slot_id) {
4169 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4170 "Bad Slot ID %d", udev->slot_id);
4171 ret = -EINVAL;
4172 goto out;
4173 }
4174
4175 virt_dev = xhci->devs[udev->slot_id];
4176
4177 if (WARN_ON(!virt_dev)) {
4178 /*
4179 * In plug/unplug torture test with an NEC controller,
4180 * a zero-dereference was observed once due to virt_dev = 0.
4181 * Print useful debug rather than crash if it is observed again!
4182 */
4183 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4184 udev->slot_id);
4185 ret = -EINVAL;
4186 goto out;
4187 }
4188 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4189 trace_xhci_setup_device_slot(slot_ctx);
4190
4191 if (setup == SETUP_CONTEXT_ONLY) {
4192 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4193 SLOT_STATE_DEFAULT) {
4194 xhci_dbg(xhci, "Slot already in default state\n");
4195 goto out;
4196 }
4197 }
4198
4199 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4200 if (!command) {
4201 ret = -ENOMEM;
4202 goto out;
4203 }
4204
4205 command->in_ctx = virt_dev->in_ctx;
4206 command->timeout_ms = timeout_ms;
4207
4208 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4209 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4210 if (!ctrl_ctx) {
4211 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4212 __func__);
4213 ret = -EINVAL;
4214 goto out;
4215 }
4216 /*
4217 * If this is the first Set Address since device plug-in or
4218 * virt_device realloaction after a resume with an xHCI power loss,
4219 * then set up the slot context.
4220 */
4221 if (!slot_ctx->dev_info)
4222 xhci_setup_addressable_virt_dev(xhci, udev);
4223 /* Otherwise, update the control endpoint ring enqueue pointer. */
4224 else
4225 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4226 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4227 ctrl_ctx->drop_flags = 0;
4228
4229 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4230 le32_to_cpu(slot_ctx->dev_info) >> 27);
4231
4232 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4233 spin_lock_irqsave(&xhci->lock, flags);
4234 trace_xhci_setup_device(virt_dev);
4235 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4236 udev->slot_id, setup);
4237 if (ret) {
4238 spin_unlock_irqrestore(&xhci->lock, flags);
4239 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4240 "FIXME: allocate a command ring segment");
4241 goto out;
4242 }
4243 xhci_ring_cmd_db(xhci);
4244 spin_unlock_irqrestore(&xhci->lock, flags);
4245
4246 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4247 wait_for_completion(command->completion);
4248
4249 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4250 * the SetAddress() "recovery interval" required by USB and aborting the
4251 * command on a timeout.
4252 */
4253 switch (command->status) {
4254 case COMP_COMMAND_ABORTED:
4255 case COMP_COMMAND_RING_STOPPED:
4256 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4257 ret = -ETIME;
4258 break;
4259 case COMP_CONTEXT_STATE_ERROR:
4260 case COMP_SLOT_NOT_ENABLED_ERROR:
4261 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4262 act, udev->slot_id);
4263 ret = -EINVAL;
4264 break;
4265 case COMP_USB_TRANSACTION_ERROR:
4266 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4267
4268 mutex_unlock(&xhci->mutex);
4269 ret = xhci_disable_slot(xhci, udev->slot_id);
4270 xhci_free_virt_device(xhci, udev->slot_id);
4271 if (!ret) {
4272 if (xhci_alloc_dev(hcd, udev) == 1)
4273 xhci_setup_addressable_virt_dev(xhci, udev);
4274 }
4275 kfree(command->completion);
4276 kfree(command);
4277 return -EPROTO;
4278 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4279 dev_warn(&udev->dev,
4280 "ERROR: Incompatible device for setup %s command\n", act);
4281 ret = -ENODEV;
4282 break;
4283 case COMP_SUCCESS:
4284 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4285 "Successful setup %s command", act);
4286 break;
4287 default:
4288 xhci_err(xhci,
4289 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4290 act, command->status);
4291 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4292 ret = -EINVAL;
4293 break;
4294 }
4295 if (ret)
4296 goto out;
4297 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4298 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4299 "Op regs DCBAA ptr = %#016llx", temp_64);
4300 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4301 "Slot ID %d dcbaa entry @%p = %#016llx",
4302 udev->slot_id,
4303 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4304 (unsigned long long)
4305 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4306 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4307 "Output Context DMA address = %#08llx",
4308 (unsigned long long)virt_dev->out_ctx->dma);
4309 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4310 le32_to_cpu(slot_ctx->dev_info) >> 27);
4311 /*
4312 * USB core uses address 1 for the roothubs, so we add one to the
4313 * address given back to us by the HC.
4314 */
4315 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4316 le32_to_cpu(slot_ctx->dev_info) >> 27);
4317 /* Zero the input context control for later use */
4318 ctrl_ctx->add_flags = 0;
4319 ctrl_ctx->drop_flags = 0;
4320 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4321 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4322
4323 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4324 "Internal device address = %d",
4325 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4326out:
4327 mutex_unlock(&xhci->mutex);
4328 if (command) {
4329 kfree(command->completion);
4330 kfree(command);
4331 }
4332 return ret;
4333}
4334
4335static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev,
4336 unsigned int timeout_ms)
4337{
4338 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS, timeout_ms);
4339}
4340
4341static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4342{
4343 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY,
4344 XHCI_CMD_DEFAULT_TIMEOUT);
4345}
4346
4347/*
4348 * Transfer the port index into real index in the HW port status
4349 * registers. Caculate offset between the port's PORTSC register
4350 * and port status base. Divide the number of per port register
4351 * to get the real index. The raw port number bases 1.
4352 */
4353int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4354{
4355 struct xhci_hub *rhub;
4356
4357 rhub = xhci_get_rhub(hcd);
4358 return rhub->ports[port1 - 1]->hw_portnum + 1;
4359}
4360
4361/*
4362 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4363 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4364 */
4365static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4366 struct usb_device *udev, u16 max_exit_latency)
4367{
4368 struct xhci_virt_device *virt_dev;
4369 struct xhci_command *command;
4370 struct xhci_input_control_ctx *ctrl_ctx;
4371 struct xhci_slot_ctx *slot_ctx;
4372 unsigned long flags;
4373 int ret;
4374
4375 command = xhci_alloc_command_with_ctx(xhci, true, GFP_KERNEL);
4376 if (!command)
4377 return -ENOMEM;
4378
4379 spin_lock_irqsave(&xhci->lock, flags);
4380
4381 virt_dev = xhci->devs[udev->slot_id];
4382
4383 /*
4384 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4385 * xHC was re-initialized. Exit latency will be set later after
4386 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4387 */
4388
4389 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4390 spin_unlock_irqrestore(&xhci->lock, flags);
4391 xhci_free_command(xhci, command);
4392 return 0;
4393 }
4394
4395 /* Attempt to issue an Evaluate Context command to change the MEL. */
4396 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4397 if (!ctrl_ctx) {
4398 spin_unlock_irqrestore(&xhci->lock, flags);
4399 xhci_free_command(xhci, command);
4400 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4401 __func__);
4402 return -ENOMEM;
4403 }
4404
4405 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4406 spin_unlock_irqrestore(&xhci->lock, flags);
4407
4408 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4409 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4410 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4411 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4412 slot_ctx->dev_state = 0;
4413
4414 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4415 "Set up evaluate context for LPM MEL change.");
4416
4417 /* Issue and wait for the evaluate context command. */
4418 ret = xhci_configure_endpoint(xhci, udev, command,
4419 true, true);
4420
4421 if (!ret) {
4422 spin_lock_irqsave(&xhci->lock, flags);
4423 virt_dev->current_mel = max_exit_latency;
4424 spin_unlock_irqrestore(&xhci->lock, flags);
4425 }
4426
4427 xhci_free_command(xhci, command);
4428
4429 return ret;
4430}
4431
4432#ifdef CONFIG_PM
4433
4434/* BESL to HIRD Encoding array for USB2 LPM */
4435static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4436 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4437
4438/* Calculate HIRD/BESL for USB2 PORTPMSC*/
4439static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4440 struct usb_device *udev)
4441{
4442 int u2del, besl, besl_host;
4443 int besl_device = 0;
4444 u32 field;
4445
4446 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4447 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4448
4449 if (field & USB_BESL_SUPPORT) {
4450 for (besl_host = 0; besl_host < 16; besl_host++) {
4451 if (xhci_besl_encoding[besl_host] >= u2del)
4452 break;
4453 }
4454 /* Use baseline BESL value as default */
4455 if (field & USB_BESL_BASELINE_VALID)
4456 besl_device = USB_GET_BESL_BASELINE(field);
4457 else if (field & USB_BESL_DEEP_VALID)
4458 besl_device = USB_GET_BESL_DEEP(field);
4459 } else {
4460 if (u2del <= 50)
4461 besl_host = 0;
4462 else
4463 besl_host = (u2del - 51) / 75 + 1;
4464 }
4465
4466 besl = besl_host + besl_device;
4467 if (besl > 15)
4468 besl = 15;
4469
4470 return besl;
4471}
4472
4473/* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4474static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4475{
4476 u32 field;
4477 int l1;
4478 int besld = 0;
4479 int hirdm = 0;
4480
4481 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4482
4483 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4484 l1 = udev->l1_params.timeout / 256;
4485
4486 /* device has preferred BESLD */
4487 if (field & USB_BESL_DEEP_VALID) {
4488 besld = USB_GET_BESL_DEEP(field);
4489 hirdm = 1;
4490 }
4491
4492 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4493}
4494
4495static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4496 struct usb_device *udev, int enable)
4497{
4498 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4499 struct xhci_port **ports;
4500 __le32 __iomem *pm_addr, *hlpm_addr;
4501 u32 pm_val, hlpm_val, field;
4502 unsigned int port_num;
4503 unsigned long flags;
4504 int hird, exit_latency;
4505 int ret;
4506
4507 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4508 return -EPERM;
4509
4510 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4511 !udev->lpm_capable)
4512 return -EPERM;
4513
4514 if (!udev->parent || udev->parent->parent ||
4515 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4516 return -EPERM;
4517
4518 if (udev->usb2_hw_lpm_capable != 1)
4519 return -EPERM;
4520
4521 spin_lock_irqsave(&xhci->lock, flags);
4522
4523 ports = xhci->usb2_rhub.ports;
4524 port_num = udev->portnum - 1;
4525 pm_addr = ports[port_num]->addr + PORTPMSC;
4526 pm_val = readl(pm_addr);
4527 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4528
4529 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4530 enable ? "enable" : "disable", port_num + 1);
4531
4532 if (enable) {
4533 /* Host supports BESL timeout instead of HIRD */
4534 if (udev->usb2_hw_lpm_besl_capable) {
4535 /* if device doesn't have a preferred BESL value use a
4536 * default one which works with mixed HIRD and BESL
4537 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4538 */
4539 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4540 if ((field & USB_BESL_SUPPORT) &&
4541 (field & USB_BESL_BASELINE_VALID))
4542 hird = USB_GET_BESL_BASELINE(field);
4543 else
4544 hird = udev->l1_params.besl;
4545
4546 exit_latency = xhci_besl_encoding[hird];
4547 spin_unlock_irqrestore(&xhci->lock, flags);
4548
4549 ret = xhci_change_max_exit_latency(xhci, udev,
4550 exit_latency);
4551 if (ret < 0)
4552 return ret;
4553 spin_lock_irqsave(&xhci->lock, flags);
4554
4555 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4556 writel(hlpm_val, hlpm_addr);
4557 /* flush write */
4558 readl(hlpm_addr);
4559 } else {
4560 hird = xhci_calculate_hird_besl(xhci, udev);
4561 }
4562
4563 pm_val &= ~PORT_HIRD_MASK;
4564 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4565 writel(pm_val, pm_addr);
4566 pm_val = readl(pm_addr);
4567 pm_val |= PORT_HLE;
4568 writel(pm_val, pm_addr);
4569 /* flush write */
4570 readl(pm_addr);
4571 } else {
4572 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4573 writel(pm_val, pm_addr);
4574 /* flush write */
4575 readl(pm_addr);
4576 if (udev->usb2_hw_lpm_besl_capable) {
4577 spin_unlock_irqrestore(&xhci->lock, flags);
4578 xhci_change_max_exit_latency(xhci, udev, 0);
4579 readl_poll_timeout(ports[port_num]->addr, pm_val,
4580 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4581 100, 10000);
4582 return 0;
4583 }
4584 }
4585
4586 spin_unlock_irqrestore(&xhci->lock, flags);
4587 return 0;
4588}
4589
4590static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4591{
4592 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4593 struct xhci_port *port;
4594 u32 capability;
4595
4596 /* Check if USB3 device at root port is tunneled over USB4 */
4597 if (hcd->speed >= HCD_USB3 && !udev->parent->parent) {
4598 port = xhci->usb3_rhub.ports[udev->portnum - 1];
4599
4600 udev->tunnel_mode = xhci_port_is_tunneled(xhci, port);
4601 if (udev->tunnel_mode == USB_LINK_UNKNOWN)
4602 dev_dbg(&udev->dev, "link tunnel state unknown\n");
4603 else if (udev->tunnel_mode == USB_LINK_TUNNELED)
4604 dev_dbg(&udev->dev, "tunneled over USB4 link\n");
4605 else if (udev->tunnel_mode == USB_LINK_NATIVE)
4606 dev_dbg(&udev->dev, "native USB 3.x link\n");
4607 return 0;
4608 }
4609
4610 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable || !xhci->hw_lpm_support)
4611 return 0;
4612
4613 /* we only support lpm for non-hub device connected to root hub yet */
4614 if (!udev->parent || udev->parent->parent ||
4615 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4616 return 0;
4617
4618 port = xhci->usb2_rhub.ports[udev->portnum - 1];
4619 capability = port->port_cap->protocol_caps;
4620
4621 if (capability & XHCI_HLC) {
4622 udev->usb2_hw_lpm_capable = 1;
4623 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4624 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4625 if (capability & XHCI_BLC)
4626 udev->usb2_hw_lpm_besl_capable = 1;
4627 }
4628
4629 return 0;
4630}
4631
4632/*---------------------- USB 3.0 Link PM functions ------------------------*/
4633
4634/* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4635static unsigned long long xhci_service_interval_to_ns(
4636 struct usb_endpoint_descriptor *desc)
4637{
4638 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4639}
4640
4641static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4642 enum usb3_link_state state)
4643{
4644 unsigned long long sel;
4645 unsigned long long pel;
4646 unsigned int max_sel_pel;
4647 char *state_name;
4648
4649 switch (state) {
4650 case USB3_LPM_U1:
4651 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4652 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4653 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4654 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4655 state_name = "U1";
4656 break;
4657 case USB3_LPM_U2:
4658 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4659 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4660 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4661 state_name = "U2";
4662 break;
4663 default:
4664 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4665 __func__);
4666 return USB3_LPM_DISABLED;
4667 }
4668
4669 if (sel <= max_sel_pel && pel <= max_sel_pel)
4670 return USB3_LPM_DEVICE_INITIATED;
4671
4672 if (sel > max_sel_pel)
4673 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4674 "due to long SEL %llu ms\n",
4675 state_name, sel);
4676 else
4677 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4678 "due to long PEL %llu ms\n",
4679 state_name, pel);
4680 return USB3_LPM_DISABLED;
4681}
4682
4683/* The U1 timeout should be the maximum of the following values:
4684 * - For control endpoints, U1 system exit latency (SEL) * 3
4685 * - For bulk endpoints, U1 SEL * 5
4686 * - For interrupt endpoints:
4687 * - Notification EPs, U1 SEL * 3
4688 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4689 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4690 */
4691static unsigned long long xhci_calculate_intel_u1_timeout(
4692 struct usb_device *udev,
4693 struct usb_endpoint_descriptor *desc)
4694{
4695 unsigned long long timeout_ns;
4696 int ep_type;
4697 int intr_type;
4698
4699 ep_type = usb_endpoint_type(desc);
4700 switch (ep_type) {
4701 case USB_ENDPOINT_XFER_CONTROL:
4702 timeout_ns = udev->u1_params.sel * 3;
4703 break;
4704 case USB_ENDPOINT_XFER_BULK:
4705 timeout_ns = udev->u1_params.sel * 5;
4706 break;
4707 case USB_ENDPOINT_XFER_INT:
4708 intr_type = usb_endpoint_interrupt_type(desc);
4709 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4710 timeout_ns = udev->u1_params.sel * 3;
4711 break;
4712 }
4713 /* Otherwise the calculation is the same as isoc eps */
4714 fallthrough;
4715 case USB_ENDPOINT_XFER_ISOC:
4716 timeout_ns = xhci_service_interval_to_ns(desc);
4717 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4718 if (timeout_ns < udev->u1_params.sel * 2)
4719 timeout_ns = udev->u1_params.sel * 2;
4720 break;
4721 default:
4722 return 0;
4723 }
4724
4725 return timeout_ns;
4726}
4727
4728/* Returns the hub-encoded U1 timeout value. */
4729static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4730 struct usb_device *udev,
4731 struct usb_endpoint_descriptor *desc)
4732{
4733 unsigned long long timeout_ns;
4734
4735 /* Prevent U1 if service interval is shorter than U1 exit latency */
4736 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4737 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4738 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4739 return USB3_LPM_DISABLED;
4740 }
4741 }
4742
4743 if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_ZHAOXIN_HOST))
4744 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4745 else
4746 timeout_ns = udev->u1_params.sel;
4747
4748 /* The U1 timeout is encoded in 1us intervals.
4749 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4750 */
4751 if (timeout_ns == USB3_LPM_DISABLED)
4752 timeout_ns = 1;
4753 else
4754 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4755
4756 /* If the necessary timeout value is bigger than what we can set in the
4757 * USB 3.0 hub, we have to disable hub-initiated U1.
4758 */
4759 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4760 return timeout_ns;
4761 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4762 "due to long timeout %llu ms\n", timeout_ns);
4763 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4764}
4765
4766/* The U2 timeout should be the maximum of:
4767 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4768 * - largest bInterval of any active periodic endpoint (to avoid going
4769 * into lower power link states between intervals).
4770 * - the U2 Exit Latency of the device
4771 */
4772static unsigned long long xhci_calculate_intel_u2_timeout(
4773 struct usb_device *udev,
4774 struct usb_endpoint_descriptor *desc)
4775{
4776 unsigned long long timeout_ns;
4777 unsigned long long u2_del_ns;
4778
4779 timeout_ns = 10 * 1000 * 1000;
4780
4781 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4782 (xhci_service_interval_to_ns(desc) > timeout_ns))
4783 timeout_ns = xhci_service_interval_to_ns(desc);
4784
4785 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4786 if (u2_del_ns > timeout_ns)
4787 timeout_ns = u2_del_ns;
4788
4789 return timeout_ns;
4790}
4791
4792/* Returns the hub-encoded U2 timeout value. */
4793static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4794 struct usb_device *udev,
4795 struct usb_endpoint_descriptor *desc)
4796{
4797 unsigned long long timeout_ns;
4798
4799 /* Prevent U2 if service interval is shorter than U2 exit latency */
4800 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4801 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4802 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4803 return USB3_LPM_DISABLED;
4804 }
4805 }
4806
4807 if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_ZHAOXIN_HOST))
4808 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4809 else
4810 timeout_ns = udev->u2_params.sel;
4811
4812 /* The U2 timeout is encoded in 256us intervals */
4813 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4814 /* If the necessary timeout value is bigger than what we can set in the
4815 * USB 3.0 hub, we have to disable hub-initiated U2.
4816 */
4817 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4818 return timeout_ns;
4819 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4820 "due to long timeout %llu ms\n", timeout_ns);
4821 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4822}
4823
4824static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4825 struct usb_device *udev,
4826 struct usb_endpoint_descriptor *desc,
4827 enum usb3_link_state state,
4828 u16 *timeout)
4829{
4830 if (state == USB3_LPM_U1)
4831 return xhci_calculate_u1_timeout(xhci, udev, desc);
4832 else if (state == USB3_LPM_U2)
4833 return xhci_calculate_u2_timeout(xhci, udev, desc);
4834
4835 return USB3_LPM_DISABLED;
4836}
4837
4838static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4839 struct usb_device *udev,
4840 struct usb_endpoint_descriptor *desc,
4841 enum usb3_link_state state,
4842 u16 *timeout)
4843{
4844 u16 alt_timeout;
4845
4846 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4847 desc, state, timeout);
4848
4849 /* If we found we can't enable hub-initiated LPM, and
4850 * the U1 or U2 exit latency was too high to allow
4851 * device-initiated LPM as well, then we will disable LPM
4852 * for this device, so stop searching any further.
4853 */
4854 if (alt_timeout == USB3_LPM_DISABLED) {
4855 *timeout = alt_timeout;
4856 return -E2BIG;
4857 }
4858 if (alt_timeout > *timeout)
4859 *timeout = alt_timeout;
4860 return 0;
4861}
4862
4863static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4864 struct usb_device *udev,
4865 struct usb_host_interface *alt,
4866 enum usb3_link_state state,
4867 u16 *timeout)
4868{
4869 int j;
4870
4871 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4872 if (xhci_update_timeout_for_endpoint(xhci, udev,
4873 &alt->endpoint[j].desc, state, timeout))
4874 return -E2BIG;
4875 }
4876 return 0;
4877}
4878
4879static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4880 struct usb_device *udev,
4881 enum usb3_link_state state)
4882{
4883 struct usb_device *parent = udev->parent;
4884 int tier = 1; /* roothub is tier1 */
4885
4886 while (parent) {
4887 parent = parent->parent;
4888 tier++;
4889 }
4890
4891 if (xhci->quirks & XHCI_INTEL_HOST && tier > 3)
4892 goto fail;
4893 if (xhci->quirks & XHCI_ZHAOXIN_HOST && tier > 2)
4894 goto fail;
4895
4896 return 0;
4897fail:
4898 dev_dbg(&udev->dev, "Tier policy prevents U1/U2 LPM states for devices at tier %d\n",
4899 tier);
4900 return -E2BIG;
4901}
4902
4903/* Returns the U1 or U2 timeout that should be enabled.
4904 * If the tier check or timeout setting functions return with a non-zero exit
4905 * code, that means the timeout value has been finalized and we shouldn't look
4906 * at any more endpoints.
4907 */
4908static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4909 struct usb_device *udev, enum usb3_link_state state)
4910{
4911 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4912 struct usb_host_config *config;
4913 char *state_name;
4914 int i;
4915 u16 timeout = USB3_LPM_DISABLED;
4916
4917 if (state == USB3_LPM_U1)
4918 state_name = "U1";
4919 else if (state == USB3_LPM_U2)
4920 state_name = "U2";
4921 else {
4922 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4923 state);
4924 return timeout;
4925 }
4926
4927 /* Gather some information about the currently installed configuration
4928 * and alternate interface settings.
4929 */
4930 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4931 state, &timeout))
4932 return timeout;
4933
4934 config = udev->actconfig;
4935 if (!config)
4936 return timeout;
4937
4938 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4939 struct usb_driver *driver;
4940 struct usb_interface *intf = config->interface[i];
4941
4942 if (!intf)
4943 continue;
4944
4945 /* Check if any currently bound drivers want hub-initiated LPM
4946 * disabled.
4947 */
4948 if (intf->dev.driver) {
4949 driver = to_usb_driver(intf->dev.driver);
4950 if (driver && driver->disable_hub_initiated_lpm) {
4951 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4952 state_name, driver->name);
4953 timeout = xhci_get_timeout_no_hub_lpm(udev,
4954 state);
4955 if (timeout == USB3_LPM_DISABLED)
4956 return timeout;
4957 }
4958 }
4959
4960 /* Not sure how this could happen... */
4961 if (!intf->cur_altsetting)
4962 continue;
4963
4964 if (xhci_update_timeout_for_interface(xhci, udev,
4965 intf->cur_altsetting,
4966 state, &timeout))
4967 return timeout;
4968 }
4969 return timeout;
4970}
4971
4972static int calculate_max_exit_latency(struct usb_device *udev,
4973 enum usb3_link_state state_changed,
4974 u16 hub_encoded_timeout)
4975{
4976 unsigned long long u1_mel_us = 0;
4977 unsigned long long u2_mel_us = 0;
4978 unsigned long long mel_us = 0;
4979 bool disabling_u1;
4980 bool disabling_u2;
4981 bool enabling_u1;
4982 bool enabling_u2;
4983
4984 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4985 hub_encoded_timeout == USB3_LPM_DISABLED);
4986 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4987 hub_encoded_timeout == USB3_LPM_DISABLED);
4988
4989 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4990 hub_encoded_timeout != USB3_LPM_DISABLED);
4991 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4992 hub_encoded_timeout != USB3_LPM_DISABLED);
4993
4994 /* If U1 was already enabled and we're not disabling it,
4995 * or we're going to enable U1, account for the U1 max exit latency.
4996 */
4997 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4998 enabling_u1)
4999 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
5000 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
5001 enabling_u2)
5002 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
5003
5004 mel_us = max(u1_mel_us, u2_mel_us);
5005
5006 /* xHCI host controller max exit latency field is only 16 bits wide. */
5007 if (mel_us > MAX_EXIT) {
5008 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
5009 "is too big.\n", mel_us);
5010 return -E2BIG;
5011 }
5012 return mel_us;
5013}
5014
5015/* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
5016static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5017 struct usb_device *udev, enum usb3_link_state state)
5018{
5019 struct xhci_hcd *xhci;
5020 struct xhci_port *port;
5021 u16 hub_encoded_timeout;
5022 int mel;
5023 int ret;
5024
5025 xhci = hcd_to_xhci(hcd);
5026 /* The LPM timeout values are pretty host-controller specific, so don't
5027 * enable hub-initiated timeouts unless the vendor has provided
5028 * information about their timeout algorithm.
5029 */
5030 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5031 !xhci->devs[udev->slot_id])
5032 return USB3_LPM_DISABLED;
5033
5034 if (xhci_check_tier_policy(xhci, udev, state) < 0)
5035 return USB3_LPM_DISABLED;
5036
5037 /* If connected to root port then check port can handle lpm */
5038 if (udev->parent && !udev->parent->parent) {
5039 port = xhci->usb3_rhub.ports[udev->portnum - 1];
5040 if (port->lpm_incapable)
5041 return USB3_LPM_DISABLED;
5042 }
5043
5044 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
5045 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
5046 if (mel < 0) {
5047 /* Max Exit Latency is too big, disable LPM. */
5048 hub_encoded_timeout = USB3_LPM_DISABLED;
5049 mel = 0;
5050 }
5051
5052 ret = xhci_change_max_exit_latency(xhci, udev, mel);
5053 if (ret)
5054 return ret;
5055 return hub_encoded_timeout;
5056}
5057
5058static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5059 struct usb_device *udev, enum usb3_link_state state)
5060{
5061 struct xhci_hcd *xhci;
5062 u16 mel;
5063
5064 xhci = hcd_to_xhci(hcd);
5065 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5066 !xhci->devs[udev->slot_id])
5067 return 0;
5068
5069 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
5070 return xhci_change_max_exit_latency(xhci, udev, mel);
5071}
5072#else /* CONFIG_PM */
5073
5074static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5075 struct usb_device *udev, int enable)
5076{
5077 return 0;
5078}
5079
5080static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5081{
5082 return 0;
5083}
5084
5085static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5086 struct usb_device *udev, enum usb3_link_state state)
5087{
5088 return USB3_LPM_DISABLED;
5089}
5090
5091static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5092 struct usb_device *udev, enum usb3_link_state state)
5093{
5094 return 0;
5095}
5096#endif /* CONFIG_PM */
5097
5098/*-------------------------------------------------------------------------*/
5099
5100/* Once a hub descriptor is fetched for a device, we need to update the xHC's
5101 * internal data structures for the device.
5102 */
5103int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5104 struct usb_tt *tt, gfp_t mem_flags)
5105{
5106 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5107 struct xhci_virt_device *vdev;
5108 struct xhci_command *config_cmd;
5109 struct xhci_input_control_ctx *ctrl_ctx;
5110 struct xhci_slot_ctx *slot_ctx;
5111 unsigned long flags;
5112 unsigned think_time;
5113 int ret;
5114
5115 /* Ignore root hubs */
5116 if (!hdev->parent)
5117 return 0;
5118
5119 vdev = xhci->devs[hdev->slot_id];
5120 if (!vdev) {
5121 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5122 return -EINVAL;
5123 }
5124
5125 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5126 if (!config_cmd)
5127 return -ENOMEM;
5128
5129 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5130 if (!ctrl_ctx) {
5131 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5132 __func__);
5133 xhci_free_command(xhci, config_cmd);
5134 return -ENOMEM;
5135 }
5136
5137 spin_lock_irqsave(&xhci->lock, flags);
5138 if (hdev->speed == USB_SPEED_HIGH &&
5139 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5140 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5141 xhci_free_command(xhci, config_cmd);
5142 spin_unlock_irqrestore(&xhci->lock, flags);
5143 return -ENOMEM;
5144 }
5145
5146 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5147 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5148 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5149 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5150 /*
5151 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5152 * but it may be already set to 1 when setup an xHCI virtual
5153 * device, so clear it anyway.
5154 */
5155 if (tt->multi)
5156 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5157 else if (hdev->speed == USB_SPEED_FULL)
5158 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5159
5160 if (xhci->hci_version > 0x95) {
5161 xhci_dbg(xhci, "xHCI version %x needs hub "
5162 "TT think time and number of ports\n",
5163 (unsigned int) xhci->hci_version);
5164 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5165 /* Set TT think time - convert from ns to FS bit times.
5166 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5167 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5168 *
5169 * xHCI 1.0: this field shall be 0 if the device is not a
5170 * High-spped hub.
5171 */
5172 think_time = tt->think_time;
5173 if (think_time != 0)
5174 think_time = (think_time / 666) - 1;
5175 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5176 slot_ctx->tt_info |=
5177 cpu_to_le32(TT_THINK_TIME(think_time));
5178 } else {
5179 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5180 "TT think time or number of ports\n",
5181 (unsigned int) xhci->hci_version);
5182 }
5183 slot_ctx->dev_state = 0;
5184 spin_unlock_irqrestore(&xhci->lock, flags);
5185
5186 xhci_dbg(xhci, "Set up %s for hub device.\n",
5187 (xhci->hci_version > 0x95) ?
5188 "configure endpoint" : "evaluate context");
5189
5190 /* Issue and wait for the configure endpoint or
5191 * evaluate context command.
5192 */
5193 if (xhci->hci_version > 0x95)
5194 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5195 false, false);
5196 else
5197 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5198 true, false);
5199
5200 xhci_free_command(xhci, config_cmd);
5201 return ret;
5202}
5203EXPORT_SYMBOL_GPL(xhci_update_hub_device);
5204
5205static int xhci_get_frame(struct usb_hcd *hcd)
5206{
5207 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5208 /* EHCI mods by the periodic size. Why? */
5209 return readl(&xhci->run_regs->microframe_index) >> 3;
5210}
5211
5212static void xhci_hcd_init_usb2_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5213{
5214 xhci->usb2_rhub.hcd = hcd;
5215 hcd->speed = HCD_USB2;
5216 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5217 /*
5218 * USB 2.0 roothub under xHCI has an integrated TT,
5219 * (rate matching hub) as opposed to having an OHCI/UHCI
5220 * companion controller.
5221 */
5222 hcd->has_tt = 1;
5223}
5224
5225static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5226{
5227 unsigned int minor_rev;
5228
5229 /*
5230 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5231 * should return 0x31 for sbrn, or that the minor revision
5232 * is a two digit BCD containig minor and sub-minor numbers.
5233 * This was later clarified in xHCI 1.2.
5234 *
5235 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5236 * minor revision set to 0x1 instead of 0x10.
5237 */
5238 if (xhci->usb3_rhub.min_rev == 0x1)
5239 minor_rev = 1;
5240 else
5241 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5242
5243 switch (minor_rev) {
5244 case 2:
5245 hcd->speed = HCD_USB32;
5246 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5247 hcd->self.root_hub->rx_lanes = 2;
5248 hcd->self.root_hub->tx_lanes = 2;
5249 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x2;
5250 break;
5251 case 1:
5252 hcd->speed = HCD_USB31;
5253 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5254 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
5255 break;
5256 }
5257 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5258 minor_rev, minor_rev ? "Enhanced " : "");
5259
5260 xhci->usb3_rhub.hcd = hcd;
5261}
5262
5263int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5264{
5265 struct xhci_hcd *xhci;
5266 /*
5267 * TODO: Check with DWC3 clients for sysdev according to
5268 * quirks
5269 */
5270 struct device *dev = hcd->self.sysdev;
5271 int retval;
5272
5273 /* Accept arbitrarily long scatter-gather lists */
5274 hcd->self.sg_tablesize = ~0;
5275
5276 /* support to build packet from discontinuous buffers */
5277 hcd->self.no_sg_constraint = 1;
5278
5279 /* XHCI controllers don't stop the ep queue on short packets :| */
5280 hcd->self.no_stop_on_short = 1;
5281
5282 xhci = hcd_to_xhci(hcd);
5283
5284 if (!usb_hcd_is_primary_hcd(hcd)) {
5285 xhci_hcd_init_usb3_data(xhci, hcd);
5286 return 0;
5287 }
5288
5289 mutex_init(&xhci->mutex);
5290 xhci->main_hcd = hcd;
5291 xhci->cap_regs = hcd->regs;
5292 xhci->op_regs = hcd->regs +
5293 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5294 xhci->run_regs = hcd->regs +
5295 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5296 /* Cache read-only capability registers */
5297 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5298 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5299 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5300 xhci->hci_version = HC_VERSION(readl(&xhci->cap_regs->hc_capbase));
5301 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5302 if (xhci->hci_version > 0x100)
5303 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5304
5305 /* xhci-plat or xhci-pci might have set max_interrupters already */
5306 if ((!xhci->max_interrupters) ||
5307 xhci->max_interrupters > HCS_MAX_INTRS(xhci->hcs_params1))
5308 xhci->max_interrupters = HCS_MAX_INTRS(xhci->hcs_params1);
5309
5310 xhci->quirks |= quirks;
5311
5312 if (get_quirks)
5313 get_quirks(dev, xhci);
5314
5315 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5316 * success event after a short transfer. This quirk will ignore such
5317 * spurious event.
5318 */
5319 if (xhci->hci_version > 0x96)
5320 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5321
5322 if (xhci->hci_version == 0x95 && link_quirk) {
5323 xhci_dbg(xhci, "QUIRK: Not clearing Link TRB chain bits");
5324 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
5325 }
5326
5327 /* Make sure the HC is halted. */
5328 retval = xhci_halt(xhci);
5329 if (retval)
5330 return retval;
5331
5332 xhci_zero_64b_regs(xhci);
5333
5334 xhci_dbg(xhci, "Resetting HCD\n");
5335 /* Reset the internal HC memory state and registers. */
5336 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
5337 if (retval)
5338 return retval;
5339 xhci_dbg(xhci, "Reset complete\n");
5340
5341 /*
5342 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5343 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5344 * address memory pointers actually. So, this driver clears the AC64
5345 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5346 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5347 */
5348 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5349 xhci->hcc_params &= ~BIT(0);
5350
5351 /* Set dma_mask and coherent_dma_mask to 64-bits,
5352 * if xHC supports 64-bit addressing */
5353 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5354 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5355 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5356 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5357 } else {
5358 /*
5359 * This is to avoid error in cases where a 32-bit USB
5360 * controller is used on a 64-bit capable system.
5361 */
5362 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5363 if (retval)
5364 return retval;
5365 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5366 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5367 }
5368
5369 xhci_dbg(xhci, "Calling HCD init\n");
5370 /* Initialize HCD and host controller data structures. */
5371 retval = xhci_init(hcd);
5372 if (retval)
5373 return retval;
5374 xhci_dbg(xhci, "Called HCD init\n");
5375
5376 if (xhci_hcd_is_usb3(hcd))
5377 xhci_hcd_init_usb3_data(xhci, hcd);
5378 else
5379 xhci_hcd_init_usb2_data(xhci, hcd);
5380
5381 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5382 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5383
5384 return 0;
5385}
5386EXPORT_SYMBOL_GPL(xhci_gen_setup);
5387
5388static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5389 struct usb_host_endpoint *ep)
5390{
5391 struct xhci_hcd *xhci;
5392 struct usb_device *udev;
5393 unsigned int slot_id;
5394 unsigned int ep_index;
5395 unsigned long flags;
5396
5397 xhci = hcd_to_xhci(hcd);
5398
5399 spin_lock_irqsave(&xhci->lock, flags);
5400 udev = (struct usb_device *)ep->hcpriv;
5401 slot_id = udev->slot_id;
5402 ep_index = xhci_get_endpoint_index(&ep->desc);
5403
5404 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5405 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5406 spin_unlock_irqrestore(&xhci->lock, flags);
5407}
5408
5409static const struct hc_driver xhci_hc_driver = {
5410 .description = "xhci-hcd",
5411 .product_desc = "xHCI Host Controller",
5412 .hcd_priv_size = sizeof(struct xhci_hcd),
5413
5414 /*
5415 * generic hardware linkage
5416 */
5417 .irq = xhci_irq,
5418 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5419 HCD_BH,
5420
5421 /*
5422 * basic lifecycle operations
5423 */
5424 .reset = NULL, /* set in xhci_init_driver() */
5425 .start = xhci_run,
5426 .stop = xhci_stop,
5427 .shutdown = xhci_shutdown,
5428
5429 /*
5430 * managing i/o requests and associated device resources
5431 */
5432 .map_urb_for_dma = xhci_map_urb_for_dma,
5433 .unmap_urb_for_dma = xhci_unmap_urb_for_dma,
5434 .urb_enqueue = xhci_urb_enqueue,
5435 .urb_dequeue = xhci_urb_dequeue,
5436 .alloc_dev = xhci_alloc_dev,
5437 .free_dev = xhci_free_dev,
5438 .alloc_streams = xhci_alloc_streams,
5439 .free_streams = xhci_free_streams,
5440 .add_endpoint = xhci_add_endpoint,
5441 .drop_endpoint = xhci_drop_endpoint,
5442 .endpoint_disable = xhci_endpoint_disable,
5443 .endpoint_reset = xhci_endpoint_reset,
5444 .check_bandwidth = xhci_check_bandwidth,
5445 .reset_bandwidth = xhci_reset_bandwidth,
5446 .address_device = xhci_address_device,
5447 .enable_device = xhci_enable_device,
5448 .update_hub_device = xhci_update_hub_device,
5449 .reset_device = xhci_discover_or_reset_device,
5450
5451 /*
5452 * scheduling support
5453 */
5454 .get_frame_number = xhci_get_frame,
5455
5456 /*
5457 * root hub support
5458 */
5459 .hub_control = xhci_hub_control,
5460 .hub_status_data = xhci_hub_status_data,
5461 .bus_suspend = xhci_bus_suspend,
5462 .bus_resume = xhci_bus_resume,
5463 .get_resuming_ports = xhci_get_resuming_ports,
5464
5465 /*
5466 * call back when device connected and addressed
5467 */
5468 .update_device = xhci_update_device,
5469 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5470 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5471 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5472 .find_raw_port_number = xhci_find_raw_port_number,
5473 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5474};
5475
5476void xhci_init_driver(struct hc_driver *drv,
5477 const struct xhci_driver_overrides *over)
5478{
5479 BUG_ON(!over);
5480
5481 /* Copy the generic table to drv then apply the overrides */
5482 *drv = xhci_hc_driver;
5483
5484 if (over) {
5485 drv->hcd_priv_size += over->extra_priv_size;
5486 if (over->reset)
5487 drv->reset = over->reset;
5488 if (over->start)
5489 drv->start = over->start;
5490 if (over->add_endpoint)
5491 drv->add_endpoint = over->add_endpoint;
5492 if (over->drop_endpoint)
5493 drv->drop_endpoint = over->drop_endpoint;
5494 if (over->check_bandwidth)
5495 drv->check_bandwidth = over->check_bandwidth;
5496 if (over->reset_bandwidth)
5497 drv->reset_bandwidth = over->reset_bandwidth;
5498 if (over->update_hub_device)
5499 drv->update_hub_device = over->update_hub_device;
5500 if (over->hub_control)
5501 drv->hub_control = over->hub_control;
5502 }
5503}
5504EXPORT_SYMBOL_GPL(xhci_init_driver);
5505
5506MODULE_DESCRIPTION(DRIVER_DESC);
5507MODULE_AUTHOR(DRIVER_AUTHOR);
5508MODULE_LICENSE("GPL");
5509
5510static int __init xhci_hcd_init(void)
5511{
5512 /*
5513 * Check the compiler generated sizes of structures that must be laid
5514 * out in specific ways for hardware access.
5515 */
5516 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5517 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5518 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5519 /* xhci_device_control has eight fields, and also
5520 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5521 */
5522 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5523 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5524 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5525 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5526 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5527 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5528 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5529
5530 if (usb_disabled())
5531 return -ENODEV;
5532
5533 xhci_debugfs_create_root();
5534 xhci_dbc_init();
5535
5536 return 0;
5537}
5538
5539/*
5540 * If an init function is provided, an exit function must also be provided
5541 * to allow module unload.
5542 */
5543static void __exit xhci_hcd_fini(void)
5544{
5545 xhci_debugfs_remove_root();
5546 xhci_dbc_exit();
5547}
5548
5549module_init(xhci_hcd_init);
5550module_exit(xhci_hcd_fini);