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1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include <linux/prefetch.h>
28#include <net/busy_poll.h>
29#include "i40e.h"
30#include "i40e_prototype.h"
31
32static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
33 u32 td_tag)
34{
35 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
36 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
37 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
38 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
39 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
40}
41
42#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
43#define I40E_FD_CLEAN_DELAY 10
44/**
45 * i40e_program_fdir_filter - Program a Flow Director filter
46 * @fdir_data: Packet data that will be filter parameters
47 * @raw_packet: the pre-allocated packet buffer for FDir
48 * @pf: The PF pointer
49 * @add: True for add/update, False for remove
50 **/
51int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet,
52 struct i40e_pf *pf, bool add)
53{
54 struct i40e_filter_program_desc *fdir_desc;
55 struct i40e_tx_buffer *tx_buf, *first;
56 struct i40e_tx_desc *tx_desc;
57 struct i40e_ring *tx_ring;
58 unsigned int fpt, dcc;
59 struct i40e_vsi *vsi;
60 struct device *dev;
61 dma_addr_t dma;
62 u32 td_cmd = 0;
63 u16 delay = 0;
64 u16 i;
65
66 /* find existing FDIR VSI */
67 vsi = NULL;
68 for (i = 0; i < pf->num_alloc_vsi; i++)
69 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
70 vsi = pf->vsi[i];
71 if (!vsi)
72 return -ENOENT;
73
74 tx_ring = vsi->tx_rings[0];
75 dev = tx_ring->dev;
76
77 /* we need two descriptors to add/del a filter and we can wait */
78 do {
79 if (I40E_DESC_UNUSED(tx_ring) > 1)
80 break;
81 msleep_interruptible(1);
82 delay++;
83 } while (delay < I40E_FD_CLEAN_DELAY);
84
85 if (!(I40E_DESC_UNUSED(tx_ring) > 1))
86 return -EAGAIN;
87
88 dma = dma_map_single(dev, raw_packet,
89 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
90 if (dma_mapping_error(dev, dma))
91 goto dma_fail;
92
93 /* grab the next descriptor */
94 i = tx_ring->next_to_use;
95 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
96 first = &tx_ring->tx_bi[i];
97 memset(first, 0, sizeof(struct i40e_tx_buffer));
98
99 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
100
101 fpt = (fdir_data->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
102 I40E_TXD_FLTR_QW0_QINDEX_MASK;
103
104 fpt |= (fdir_data->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
105 I40E_TXD_FLTR_QW0_FLEXOFF_MASK;
106
107 fpt |= (fdir_data->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
108 I40E_TXD_FLTR_QW0_PCTYPE_MASK;
109
110 /* Use LAN VSI Id if not programmed by user */
111 if (fdir_data->dest_vsi == 0)
112 fpt |= (pf->vsi[pf->lan_vsi]->id) <<
113 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
114 else
115 fpt |= ((u32)fdir_data->dest_vsi <<
116 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
117 I40E_TXD_FLTR_QW0_DEST_VSI_MASK;
118
119 dcc = I40E_TX_DESC_DTYPE_FILTER_PROG;
120
121 if (add)
122 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
123 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
124 else
125 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
126 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
127
128 dcc |= (fdir_data->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT) &
129 I40E_TXD_FLTR_QW1_DEST_MASK;
130
131 dcc |= (fdir_data->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
132 I40E_TXD_FLTR_QW1_FD_STATUS_MASK;
133
134 if (fdir_data->cnt_index != 0) {
135 dcc |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
136 dcc |= ((u32)fdir_data->cnt_index <<
137 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
138 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
139 }
140
141 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(fpt);
142 fdir_desc->rsvd = cpu_to_le32(0);
143 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dcc);
144 fdir_desc->fd_id = cpu_to_le32(fdir_data->fd_id);
145
146 /* Now program a dummy descriptor */
147 i = tx_ring->next_to_use;
148 tx_desc = I40E_TX_DESC(tx_ring, i);
149 tx_buf = &tx_ring->tx_bi[i];
150
151 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
152
153 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
154
155 /* record length, and DMA address */
156 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
157 dma_unmap_addr_set(tx_buf, dma, dma);
158
159 tx_desc->buffer_addr = cpu_to_le64(dma);
160 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
161
162 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
163 tx_buf->raw_buf = (void *)raw_packet;
164
165 tx_desc->cmd_type_offset_bsz =
166 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
167
168 /* Force memory writes to complete before letting h/w
169 * know there are new descriptors to fetch.
170 */
171 wmb();
172
173 /* Mark the data descriptor to be watched */
174 first->next_to_watch = tx_desc;
175
176 writel(tx_ring->next_to_use, tx_ring->tail);
177 return 0;
178
179dma_fail:
180 return -1;
181}
182
183#define IP_HEADER_OFFSET 14
184#define I40E_UDPIP_DUMMY_PACKET_LEN 42
185/**
186 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters
187 * @vsi: pointer to the targeted VSI
188 * @fd_data: the flow director data required for the FDir descriptor
189 * @add: true adds a filter, false removes it
190 *
191 * Returns 0 if the filters were successfully added or removed
192 **/
193static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi,
194 struct i40e_fdir_filter *fd_data,
195 bool add)
196{
197 struct i40e_pf *pf = vsi->back;
198 struct udphdr *udp;
199 struct iphdr *ip;
200 bool err = false;
201 u8 *raw_packet;
202 int ret;
203 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
204 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0,
205 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
206
207 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
208 if (!raw_packet)
209 return -ENOMEM;
210 memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN);
211
212 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
213 udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET
214 + sizeof(struct iphdr));
215
216 ip->daddr = fd_data->dst_ip[0];
217 udp->dest = fd_data->dst_port;
218 ip->saddr = fd_data->src_ip[0];
219 udp->source = fd_data->src_port;
220
221 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
222 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
223 if (ret) {
224 dev_info(&pf->pdev->dev,
225 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
226 fd_data->pctype, fd_data->fd_id, ret);
227 err = true;
228 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
229 if (add)
230 dev_info(&pf->pdev->dev,
231 "Filter OK for PCTYPE %d loc = %d\n",
232 fd_data->pctype, fd_data->fd_id);
233 else
234 dev_info(&pf->pdev->dev,
235 "Filter deleted for PCTYPE %d loc = %d\n",
236 fd_data->pctype, fd_data->fd_id);
237 }
238 if (err)
239 kfree(raw_packet);
240
241 return err ? -EOPNOTSUPP : 0;
242}
243
244#define I40E_TCPIP_DUMMY_PACKET_LEN 54
245/**
246 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters
247 * @vsi: pointer to the targeted VSI
248 * @fd_data: the flow director data required for the FDir descriptor
249 * @add: true adds a filter, false removes it
250 *
251 * Returns 0 if the filters were successfully added or removed
252 **/
253static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
254 struct i40e_fdir_filter *fd_data,
255 bool add)
256{
257 struct i40e_pf *pf = vsi->back;
258 struct tcphdr *tcp;
259 struct iphdr *ip;
260 bool err = false;
261 u8 *raw_packet;
262 int ret;
263 /* Dummy packet */
264 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
265 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0,
266 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11,
267 0x0, 0x72, 0, 0, 0, 0};
268
269 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
270 if (!raw_packet)
271 return -ENOMEM;
272 memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN);
273
274 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
275 tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET
276 + sizeof(struct iphdr));
277
278 ip->daddr = fd_data->dst_ip[0];
279 tcp->dest = fd_data->dst_port;
280 ip->saddr = fd_data->src_ip[0];
281 tcp->source = fd_data->src_port;
282
283 if (add) {
284 pf->fd_tcp_rule++;
285 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) {
286 if (I40E_DEBUG_FD & pf->hw.debug_mask)
287 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
288 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
289 }
290 } else {
291 pf->fd_tcp_rule = (pf->fd_tcp_rule > 0) ?
292 (pf->fd_tcp_rule - 1) : 0;
293 if (pf->fd_tcp_rule == 0) {
294 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
295 if (I40E_DEBUG_FD & pf->hw.debug_mask)
296 dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n");
297 }
298 }
299
300 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
301 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
302
303 if (ret) {
304 dev_info(&pf->pdev->dev,
305 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
306 fd_data->pctype, fd_data->fd_id, ret);
307 err = true;
308 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
309 if (add)
310 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n",
311 fd_data->pctype, fd_data->fd_id);
312 else
313 dev_info(&pf->pdev->dev,
314 "Filter deleted for PCTYPE %d loc = %d\n",
315 fd_data->pctype, fd_data->fd_id);
316 }
317
318 if (err)
319 kfree(raw_packet);
320
321 return err ? -EOPNOTSUPP : 0;
322}
323
324/**
325 * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for
326 * a specific flow spec
327 * @vsi: pointer to the targeted VSI
328 * @fd_data: the flow director data required for the FDir descriptor
329 * @add: true adds a filter, false removes it
330 *
331 * Returns 0 if the filters were successfully added or removed
332 **/
333static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi,
334 struct i40e_fdir_filter *fd_data,
335 bool add)
336{
337 return -EOPNOTSUPP;
338}
339
340#define I40E_IP_DUMMY_PACKET_LEN 34
341/**
342 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for
343 * a specific flow spec
344 * @vsi: pointer to the targeted VSI
345 * @fd_data: the flow director data required for the FDir descriptor
346 * @add: true adds a filter, false removes it
347 *
348 * Returns 0 if the filters were successfully added or removed
349 **/
350static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi,
351 struct i40e_fdir_filter *fd_data,
352 bool add)
353{
354 struct i40e_pf *pf = vsi->back;
355 struct iphdr *ip;
356 bool err = false;
357 u8 *raw_packet;
358 int ret;
359 int i;
360 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
361 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0,
362 0, 0, 0, 0};
363
364 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
365 i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) {
366 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
367 if (!raw_packet)
368 return -ENOMEM;
369 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN);
370 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
371
372 ip->saddr = fd_data->src_ip[0];
373 ip->daddr = fd_data->dst_ip[0];
374 ip->protocol = 0;
375
376 fd_data->pctype = i;
377 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
378
379 if (ret) {
380 dev_info(&pf->pdev->dev,
381 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
382 fd_data->pctype, fd_data->fd_id, ret);
383 err = true;
384 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
385 if (add)
386 dev_info(&pf->pdev->dev,
387 "Filter OK for PCTYPE %d loc = %d\n",
388 fd_data->pctype, fd_data->fd_id);
389 else
390 dev_info(&pf->pdev->dev,
391 "Filter deleted for PCTYPE %d loc = %d\n",
392 fd_data->pctype, fd_data->fd_id);
393 }
394 }
395
396 if (err)
397 kfree(raw_packet);
398
399 return err ? -EOPNOTSUPP : 0;
400}
401
402/**
403 * i40e_add_del_fdir - Build raw packets to add/del fdir filter
404 * @vsi: pointer to the targeted VSI
405 * @cmd: command to get or set RX flow classification rules
406 * @add: true adds a filter, false removes it
407 *
408 **/
409int i40e_add_del_fdir(struct i40e_vsi *vsi,
410 struct i40e_fdir_filter *input, bool add)
411{
412 struct i40e_pf *pf = vsi->back;
413 int ret;
414
415 switch (input->flow_type & ~FLOW_EXT) {
416 case TCP_V4_FLOW:
417 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
418 break;
419 case UDP_V4_FLOW:
420 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
421 break;
422 case SCTP_V4_FLOW:
423 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
424 break;
425 case IPV4_FLOW:
426 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
427 break;
428 case IP_USER_FLOW:
429 switch (input->ip4_proto) {
430 case IPPROTO_TCP:
431 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
432 break;
433 case IPPROTO_UDP:
434 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
435 break;
436 case IPPROTO_SCTP:
437 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
438 break;
439 default:
440 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
441 break;
442 }
443 break;
444 default:
445 dev_info(&pf->pdev->dev, "Could not specify spec type %d\n",
446 input->flow_type);
447 ret = -EINVAL;
448 }
449
450 /* The buffer allocated here is freed by the i40e_clean_tx_ring() */
451 return ret;
452}
453
454/**
455 * i40e_fd_handle_status - check the Programming Status for FD
456 * @rx_ring: the Rx ring for this descriptor
457 * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor.
458 * @prog_id: the id originally used for programming
459 *
460 * This is used to verify if the FD programming or invalidation
461 * requested by SW to the HW is successful or not and take actions accordingly.
462 **/
463static void i40e_fd_handle_status(struct i40e_ring *rx_ring,
464 union i40e_rx_desc *rx_desc, u8 prog_id)
465{
466 struct i40e_pf *pf = rx_ring->vsi->back;
467 struct pci_dev *pdev = pf->pdev;
468 u32 fcnt_prog, fcnt_avail;
469 u32 error;
470 u64 qw;
471
472 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
473 error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
474 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
475
476 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
477 pf->fd_inv = le32_to_cpu(rx_desc->wb.qword0.hi_dword.fd_id);
478 if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) ||
479 (I40E_DEBUG_FD & pf->hw.debug_mask))
480 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
481 pf->fd_inv);
482
483 /* Check if the programming error is for ATR.
484 * If so, auto disable ATR and set a state for
485 * flush in progress. Next time we come here if flush is in
486 * progress do nothing, once flush is complete the state will
487 * be cleared.
488 */
489 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
490 return;
491
492 pf->fd_add_err++;
493 /* store the current atr filter count */
494 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
495
496 if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) &&
497 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
498 pf->auto_disable_flags |= I40E_FLAG_FD_ATR_ENABLED;
499 set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
500 }
501
502 /* filter programming failed most likely due to table full */
503 fcnt_prog = i40e_get_global_fd_count(pf);
504 fcnt_avail = pf->fdir_pf_filter_count;
505 /* If ATR is running fcnt_prog can quickly change,
506 * if we are very close to full, it makes sense to disable
507 * FD ATR/SB and then re-enable it when there is room.
508 */
509 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
510 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
511 !(pf->auto_disable_flags &
512 I40E_FLAG_FD_SB_ENABLED)) {
513 if (I40E_DEBUG_FD & pf->hw.debug_mask)
514 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
515 pf->auto_disable_flags |=
516 I40E_FLAG_FD_SB_ENABLED;
517 }
518 }
519 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
520 if (I40E_DEBUG_FD & pf->hw.debug_mask)
521 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
522 rx_desc->wb.qword0.hi_dword.fd_id);
523 }
524}
525
526/**
527 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
528 * @ring: the ring that owns the buffer
529 * @tx_buffer: the buffer to free
530 **/
531static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
532 struct i40e_tx_buffer *tx_buffer)
533{
534 if (tx_buffer->skb) {
535 dev_kfree_skb_any(tx_buffer->skb);
536 if (dma_unmap_len(tx_buffer, len))
537 dma_unmap_single(ring->dev,
538 dma_unmap_addr(tx_buffer, dma),
539 dma_unmap_len(tx_buffer, len),
540 DMA_TO_DEVICE);
541 } else if (dma_unmap_len(tx_buffer, len)) {
542 dma_unmap_page(ring->dev,
543 dma_unmap_addr(tx_buffer, dma),
544 dma_unmap_len(tx_buffer, len),
545 DMA_TO_DEVICE);
546 }
547
548 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
549 kfree(tx_buffer->raw_buf);
550
551 tx_buffer->next_to_watch = NULL;
552 tx_buffer->skb = NULL;
553 dma_unmap_len_set(tx_buffer, len, 0);
554 /* tx_buffer must be completely set up in the transmit path */
555}
556
557/**
558 * i40e_clean_tx_ring - Free any empty Tx buffers
559 * @tx_ring: ring to be cleaned
560 **/
561void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
562{
563 unsigned long bi_size;
564 u16 i;
565
566 /* ring already cleared, nothing to do */
567 if (!tx_ring->tx_bi)
568 return;
569
570 /* Free all the Tx ring sk_buffs */
571 for (i = 0; i < tx_ring->count; i++)
572 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
573
574 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
575 memset(tx_ring->tx_bi, 0, bi_size);
576
577 /* Zero out the descriptor ring */
578 memset(tx_ring->desc, 0, tx_ring->size);
579
580 tx_ring->next_to_use = 0;
581 tx_ring->next_to_clean = 0;
582
583 if (!tx_ring->netdev)
584 return;
585
586 /* cleanup Tx queue statistics */
587 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
588 tx_ring->queue_index));
589}
590
591/**
592 * i40e_free_tx_resources - Free Tx resources per queue
593 * @tx_ring: Tx descriptor ring for a specific queue
594 *
595 * Free all transmit software resources
596 **/
597void i40e_free_tx_resources(struct i40e_ring *tx_ring)
598{
599 i40e_clean_tx_ring(tx_ring);
600 kfree(tx_ring->tx_bi);
601 tx_ring->tx_bi = NULL;
602
603 if (tx_ring->desc) {
604 dma_free_coherent(tx_ring->dev, tx_ring->size,
605 tx_ring->desc, tx_ring->dma);
606 tx_ring->desc = NULL;
607 }
608}
609
610/**
611 * i40e_get_tx_pending - how many tx descriptors not processed
612 * @tx_ring: the ring of descriptors
613 * @in_sw: is tx_pending being checked in SW or HW
614 *
615 * Since there is no access to the ring head register
616 * in XL710, we need to use our local copies
617 **/
618u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw)
619{
620 u32 head, tail;
621
622 if (!in_sw)
623 head = i40e_get_head(ring);
624 else
625 head = ring->next_to_clean;
626 tail = readl(ring->tail);
627
628 if (head != tail)
629 return (head < tail) ?
630 tail - head : (tail + ring->count - head);
631
632 return 0;
633}
634
635#define WB_STRIDE 0x3
636
637/**
638 * i40e_clean_tx_irq - Reclaim resources after transmit completes
639 * @tx_ring: tx ring to clean
640 * @budget: how many cleans we're allowed
641 *
642 * Returns true if there's any budget left (e.g. the clean is finished)
643 **/
644static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
645{
646 u16 i = tx_ring->next_to_clean;
647 struct i40e_tx_buffer *tx_buf;
648 struct i40e_tx_desc *tx_head;
649 struct i40e_tx_desc *tx_desc;
650 unsigned int total_packets = 0;
651 unsigned int total_bytes = 0;
652
653 tx_buf = &tx_ring->tx_bi[i];
654 tx_desc = I40E_TX_DESC(tx_ring, i);
655 i -= tx_ring->count;
656
657 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
658
659 do {
660 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
661
662 /* if next_to_watch is not set then there is no work pending */
663 if (!eop_desc)
664 break;
665
666 /* prevent any other reads prior to eop_desc */
667 read_barrier_depends();
668
669 /* we have caught up to head, no work left to do */
670 if (tx_head == tx_desc)
671 break;
672
673 /* clear next_to_watch to prevent false hangs */
674 tx_buf->next_to_watch = NULL;
675
676 /* update the statistics for this packet */
677 total_bytes += tx_buf->bytecount;
678 total_packets += tx_buf->gso_segs;
679
680 /* free the skb */
681 dev_consume_skb_any(tx_buf->skb);
682
683 /* unmap skb header data */
684 dma_unmap_single(tx_ring->dev,
685 dma_unmap_addr(tx_buf, dma),
686 dma_unmap_len(tx_buf, len),
687 DMA_TO_DEVICE);
688
689 /* clear tx_buffer data */
690 tx_buf->skb = NULL;
691 dma_unmap_len_set(tx_buf, len, 0);
692
693 /* unmap remaining buffers */
694 while (tx_desc != eop_desc) {
695
696 tx_buf++;
697 tx_desc++;
698 i++;
699 if (unlikely(!i)) {
700 i -= tx_ring->count;
701 tx_buf = tx_ring->tx_bi;
702 tx_desc = I40E_TX_DESC(tx_ring, 0);
703 }
704
705 /* unmap any remaining paged data */
706 if (dma_unmap_len(tx_buf, len)) {
707 dma_unmap_page(tx_ring->dev,
708 dma_unmap_addr(tx_buf, dma),
709 dma_unmap_len(tx_buf, len),
710 DMA_TO_DEVICE);
711 dma_unmap_len_set(tx_buf, len, 0);
712 }
713 }
714
715 /* move us one more past the eop_desc for start of next pkt */
716 tx_buf++;
717 tx_desc++;
718 i++;
719 if (unlikely(!i)) {
720 i -= tx_ring->count;
721 tx_buf = tx_ring->tx_bi;
722 tx_desc = I40E_TX_DESC(tx_ring, 0);
723 }
724
725 prefetch(tx_desc);
726
727 /* update budget accounting */
728 budget--;
729 } while (likely(budget));
730
731 i += tx_ring->count;
732 tx_ring->next_to_clean = i;
733 u64_stats_update_begin(&tx_ring->syncp);
734 tx_ring->stats.bytes += total_bytes;
735 tx_ring->stats.packets += total_packets;
736 u64_stats_update_end(&tx_ring->syncp);
737 tx_ring->q_vector->tx.total_bytes += total_bytes;
738 tx_ring->q_vector->tx.total_packets += total_packets;
739
740 if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
741 unsigned int j = 0;
742
743 /* check to see if there are < 4 descriptors
744 * waiting to be written back, then kick the hardware to force
745 * them to be written back in case we stay in NAPI.
746 * In this mode on X722 we do not enable Interrupt.
747 */
748 j = i40e_get_tx_pending(tx_ring, false);
749
750 if (budget &&
751 ((j / (WB_STRIDE + 1)) == 0) && (j != 0) &&
752 !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
753 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
754 tx_ring->arm_wb = true;
755 }
756
757 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
758 tx_ring->queue_index),
759 total_packets, total_bytes);
760
761#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
762 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
763 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
764 /* Make sure that anybody stopping the queue after this
765 * sees the new next_to_clean.
766 */
767 smp_mb();
768 if (__netif_subqueue_stopped(tx_ring->netdev,
769 tx_ring->queue_index) &&
770 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
771 netif_wake_subqueue(tx_ring->netdev,
772 tx_ring->queue_index);
773 ++tx_ring->tx_stats.restart_queue;
774 }
775 }
776
777 return !!budget;
778}
779
780/**
781 * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
782 * @vsi: the VSI we care about
783 * @q_vector: the vector on which to enable writeback
784 *
785 **/
786static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
787 struct i40e_q_vector *q_vector)
788{
789 u16 flags = q_vector->tx.ring[0].flags;
790 u32 val;
791
792 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
793 return;
794
795 if (q_vector->arm_wb_state)
796 return;
797
798 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
799 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK |
800 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */
801
802 wr32(&vsi->back->hw,
803 I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1),
804 val);
805 } else {
806 val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK |
807 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */
808
809 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
810 }
811 q_vector->arm_wb_state = true;
812}
813
814/**
815 * i40e_force_wb - Issue SW Interrupt so HW does a wb
816 * @vsi: the VSI we care about
817 * @q_vector: the vector on which to force writeback
818 *
819 **/
820void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
821{
822 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
823 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
824 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
825 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
826 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
827 /* allow 00 to be written to the index */
828
829 wr32(&vsi->back->hw,
830 I40E_PFINT_DYN_CTLN(q_vector->v_idx +
831 vsi->base_vector - 1), val);
832 } else {
833 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
834 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
835 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
836 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK;
837 /* allow 00 to be written to the index */
838
839 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
840 }
841}
842
843/**
844 * i40e_set_new_dynamic_itr - Find new ITR level
845 * @rc: structure containing ring performance data
846 *
847 * Returns true if ITR changed, false if not
848 *
849 * Stores a new ITR value based on packets and byte counts during
850 * the last interrupt. The advantage of per interrupt computation
851 * is faster updates and more accurate ITR for the current traffic
852 * pattern. Constants in this function were computed based on
853 * theoretical maximum wire speed and thresholds were set based on
854 * testing data as well as attempting to minimize response time
855 * while increasing bulk throughput.
856 **/
857static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
858{
859 enum i40e_latency_range new_latency_range = rc->latency_range;
860 struct i40e_q_vector *qv = rc->ring->q_vector;
861 u32 new_itr = rc->itr;
862 int bytes_per_int;
863 int usecs;
864
865 if (rc->total_packets == 0 || !rc->itr)
866 return false;
867
868 /* simple throttlerate management
869 * 0-10MB/s lowest (50000 ints/s)
870 * 10-20MB/s low (20000 ints/s)
871 * 20-1249MB/s bulk (18000 ints/s)
872 * > 40000 Rx packets per second (8000 ints/s)
873 *
874 * The math works out because the divisor is in 10^(-6) which
875 * turns the bytes/us input value into MB/s values, but
876 * make sure to use usecs, as the register values written
877 * are in 2 usec increments in the ITR registers, and make sure
878 * to use the smoothed values that the countdown timer gives us.
879 */
880 usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
881 bytes_per_int = rc->total_bytes / usecs;
882
883 switch (new_latency_range) {
884 case I40E_LOWEST_LATENCY:
885 if (bytes_per_int > 10)
886 new_latency_range = I40E_LOW_LATENCY;
887 break;
888 case I40E_LOW_LATENCY:
889 if (bytes_per_int > 20)
890 new_latency_range = I40E_BULK_LATENCY;
891 else if (bytes_per_int <= 10)
892 new_latency_range = I40E_LOWEST_LATENCY;
893 break;
894 case I40E_BULK_LATENCY:
895 case I40E_ULTRA_LATENCY:
896 default:
897 if (bytes_per_int <= 20)
898 new_latency_range = I40E_LOW_LATENCY;
899 break;
900 }
901
902 /* this is to adjust RX more aggressively when streaming small
903 * packets. The value of 40000 was picked as it is just beyond
904 * what the hardware can receive per second if in low latency
905 * mode.
906 */
907#define RX_ULTRA_PACKET_RATE 40000
908
909 if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
910 (&qv->rx == rc))
911 new_latency_range = I40E_ULTRA_LATENCY;
912
913 rc->latency_range = new_latency_range;
914
915 switch (new_latency_range) {
916 case I40E_LOWEST_LATENCY:
917 new_itr = I40E_ITR_50K;
918 break;
919 case I40E_LOW_LATENCY:
920 new_itr = I40E_ITR_20K;
921 break;
922 case I40E_BULK_LATENCY:
923 new_itr = I40E_ITR_18K;
924 break;
925 case I40E_ULTRA_LATENCY:
926 new_itr = I40E_ITR_8K;
927 break;
928 default:
929 break;
930 }
931
932 rc->total_bytes = 0;
933 rc->total_packets = 0;
934
935 if (new_itr != rc->itr) {
936 rc->itr = new_itr;
937 return true;
938 }
939
940 return false;
941}
942
943/**
944 * i40e_clean_programming_status - clean the programming status descriptor
945 * @rx_ring: the rx ring that has this descriptor
946 * @rx_desc: the rx descriptor written back by HW
947 *
948 * Flow director should handle FD_FILTER_STATUS to check its filter programming
949 * status being successful or not and take actions accordingly. FCoE should
950 * handle its context/filter programming/invalidation status and take actions.
951 *
952 **/
953static void i40e_clean_programming_status(struct i40e_ring *rx_ring,
954 union i40e_rx_desc *rx_desc)
955{
956 u64 qw;
957 u8 id;
958
959 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
960 id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
961 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
962
963 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
964 i40e_fd_handle_status(rx_ring, rx_desc, id);
965#ifdef I40E_FCOE
966 else if ((id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS) ||
967 (id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS))
968 i40e_fcoe_handle_status(rx_ring, rx_desc, id);
969#endif
970}
971
972/**
973 * i40e_setup_tx_descriptors - Allocate the Tx descriptors
974 * @tx_ring: the tx ring to set up
975 *
976 * Return 0 on success, negative on error
977 **/
978int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
979{
980 struct device *dev = tx_ring->dev;
981 int bi_size;
982
983 if (!dev)
984 return -ENOMEM;
985
986 /* warn if we are about to overwrite the pointer */
987 WARN_ON(tx_ring->tx_bi);
988 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
989 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
990 if (!tx_ring->tx_bi)
991 goto err;
992
993 /* round up to nearest 4K */
994 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
995 /* add u32 for head writeback, align after this takes care of
996 * guaranteeing this is at least one cache line in size
997 */
998 tx_ring->size += sizeof(u32);
999 tx_ring->size = ALIGN(tx_ring->size, 4096);
1000 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1001 &tx_ring->dma, GFP_KERNEL);
1002 if (!tx_ring->desc) {
1003 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
1004 tx_ring->size);
1005 goto err;
1006 }
1007
1008 tx_ring->next_to_use = 0;
1009 tx_ring->next_to_clean = 0;
1010 return 0;
1011
1012err:
1013 kfree(tx_ring->tx_bi);
1014 tx_ring->tx_bi = NULL;
1015 return -ENOMEM;
1016}
1017
1018/**
1019 * i40e_clean_rx_ring - Free Rx buffers
1020 * @rx_ring: ring to be cleaned
1021 **/
1022void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
1023{
1024 struct device *dev = rx_ring->dev;
1025 struct i40e_rx_buffer *rx_bi;
1026 unsigned long bi_size;
1027 u16 i;
1028
1029 /* ring already cleared, nothing to do */
1030 if (!rx_ring->rx_bi)
1031 return;
1032
1033 if (ring_is_ps_enabled(rx_ring)) {
1034 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
1035
1036 rx_bi = &rx_ring->rx_bi[0];
1037 if (rx_bi->hdr_buf) {
1038 dma_free_coherent(dev,
1039 bufsz,
1040 rx_bi->hdr_buf,
1041 rx_bi->dma);
1042 for (i = 0; i < rx_ring->count; i++) {
1043 rx_bi = &rx_ring->rx_bi[i];
1044 rx_bi->dma = 0;
1045 rx_bi->hdr_buf = NULL;
1046 }
1047 }
1048 }
1049 /* Free all the Rx ring sk_buffs */
1050 for (i = 0; i < rx_ring->count; i++) {
1051 rx_bi = &rx_ring->rx_bi[i];
1052 if (rx_bi->dma) {
1053 dma_unmap_single(dev,
1054 rx_bi->dma,
1055 rx_ring->rx_buf_len,
1056 DMA_FROM_DEVICE);
1057 rx_bi->dma = 0;
1058 }
1059 if (rx_bi->skb) {
1060 dev_kfree_skb(rx_bi->skb);
1061 rx_bi->skb = NULL;
1062 }
1063 if (rx_bi->page) {
1064 if (rx_bi->page_dma) {
1065 dma_unmap_page(dev,
1066 rx_bi->page_dma,
1067 PAGE_SIZE,
1068 DMA_FROM_DEVICE);
1069 rx_bi->page_dma = 0;
1070 }
1071 __free_page(rx_bi->page);
1072 rx_bi->page = NULL;
1073 rx_bi->page_offset = 0;
1074 }
1075 }
1076
1077 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1078 memset(rx_ring->rx_bi, 0, bi_size);
1079
1080 /* Zero out the descriptor ring */
1081 memset(rx_ring->desc, 0, rx_ring->size);
1082
1083 rx_ring->next_to_clean = 0;
1084 rx_ring->next_to_use = 0;
1085}
1086
1087/**
1088 * i40e_free_rx_resources - Free Rx resources
1089 * @rx_ring: ring to clean the resources from
1090 *
1091 * Free all receive software resources
1092 **/
1093void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1094{
1095 i40e_clean_rx_ring(rx_ring);
1096 kfree(rx_ring->rx_bi);
1097 rx_ring->rx_bi = NULL;
1098
1099 if (rx_ring->desc) {
1100 dma_free_coherent(rx_ring->dev, rx_ring->size,
1101 rx_ring->desc, rx_ring->dma);
1102 rx_ring->desc = NULL;
1103 }
1104}
1105
1106/**
1107 * i40e_alloc_rx_headers - allocate rx header buffers
1108 * @rx_ring: ring to alloc buffers
1109 *
1110 * Allocate rx header buffers for the entire ring. As these are static,
1111 * this is only called when setting up a new ring.
1112 **/
1113void i40e_alloc_rx_headers(struct i40e_ring *rx_ring)
1114{
1115 struct device *dev = rx_ring->dev;
1116 struct i40e_rx_buffer *rx_bi;
1117 dma_addr_t dma;
1118 void *buffer;
1119 int buf_size;
1120 int i;
1121
1122 if (rx_ring->rx_bi[0].hdr_buf)
1123 return;
1124 /* Make sure the buffers don't cross cache line boundaries. */
1125 buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
1126 buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
1127 &dma, GFP_KERNEL);
1128 if (!buffer)
1129 return;
1130 for (i = 0; i < rx_ring->count; i++) {
1131 rx_bi = &rx_ring->rx_bi[i];
1132 rx_bi->dma = dma + (i * buf_size);
1133 rx_bi->hdr_buf = buffer + (i * buf_size);
1134 }
1135}
1136
1137/**
1138 * i40e_setup_rx_descriptors - Allocate Rx descriptors
1139 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1140 *
1141 * Returns 0 on success, negative on failure
1142 **/
1143int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1144{
1145 struct device *dev = rx_ring->dev;
1146 int bi_size;
1147
1148 /* warn if we are about to overwrite the pointer */
1149 WARN_ON(rx_ring->rx_bi);
1150 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1151 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
1152 if (!rx_ring->rx_bi)
1153 goto err;
1154
1155 u64_stats_init(&rx_ring->syncp);
1156
1157 /* Round up to nearest 4K */
1158 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
1159 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
1160 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
1161 rx_ring->size = ALIGN(rx_ring->size, 4096);
1162 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1163 &rx_ring->dma, GFP_KERNEL);
1164
1165 if (!rx_ring->desc) {
1166 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1167 rx_ring->size);
1168 goto err;
1169 }
1170
1171 rx_ring->next_to_clean = 0;
1172 rx_ring->next_to_use = 0;
1173
1174 return 0;
1175err:
1176 kfree(rx_ring->rx_bi);
1177 rx_ring->rx_bi = NULL;
1178 return -ENOMEM;
1179}
1180
1181/**
1182 * i40e_release_rx_desc - Store the new tail and head values
1183 * @rx_ring: ring to bump
1184 * @val: new head index
1185 **/
1186static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1187{
1188 rx_ring->next_to_use = val;
1189 /* Force memory writes to complete before letting h/w
1190 * know there are new descriptors to fetch. (Only
1191 * applicable for weak-ordered memory model archs,
1192 * such as IA-64).
1193 */
1194 wmb();
1195 writel(val, rx_ring->tail);
1196}
1197
1198/**
1199 * i40e_alloc_rx_buffers_ps - Replace used receive buffers; packet split
1200 * @rx_ring: ring to place buffers on
1201 * @cleaned_count: number of buffers to replace
1202 *
1203 * Returns true if any errors on allocation
1204 **/
1205bool i40e_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
1206{
1207 u16 i = rx_ring->next_to_use;
1208 union i40e_rx_desc *rx_desc;
1209 struct i40e_rx_buffer *bi;
1210 const int current_node = numa_node_id();
1211
1212 /* do nothing if no valid netdev defined */
1213 if (!rx_ring->netdev || !cleaned_count)
1214 return false;
1215
1216 while (cleaned_count--) {
1217 rx_desc = I40E_RX_DESC(rx_ring, i);
1218 bi = &rx_ring->rx_bi[i];
1219
1220 if (bi->skb) /* desc is in use */
1221 goto no_buffers;
1222
1223 /* If we've been moved to a different NUMA node, release the
1224 * page so we can get a new one on the current node.
1225 */
1226 if (bi->page && page_to_nid(bi->page) != current_node) {
1227 dma_unmap_page(rx_ring->dev,
1228 bi->page_dma,
1229 PAGE_SIZE,
1230 DMA_FROM_DEVICE);
1231 __free_page(bi->page);
1232 bi->page = NULL;
1233 bi->page_dma = 0;
1234 rx_ring->rx_stats.realloc_count++;
1235 } else if (bi->page) {
1236 rx_ring->rx_stats.page_reuse_count++;
1237 }
1238
1239 if (!bi->page) {
1240 bi->page = alloc_page(GFP_ATOMIC);
1241 if (!bi->page) {
1242 rx_ring->rx_stats.alloc_page_failed++;
1243 goto no_buffers;
1244 }
1245 bi->page_dma = dma_map_page(rx_ring->dev,
1246 bi->page,
1247 0,
1248 PAGE_SIZE,
1249 DMA_FROM_DEVICE);
1250 if (dma_mapping_error(rx_ring->dev, bi->page_dma)) {
1251 rx_ring->rx_stats.alloc_page_failed++;
1252 __free_page(bi->page);
1253 bi->page = NULL;
1254 bi->page_dma = 0;
1255 bi->page_offset = 0;
1256 goto no_buffers;
1257 }
1258 bi->page_offset = 0;
1259 }
1260
1261 /* Refresh the desc even if buffer_addrs didn't change
1262 * because each write-back erases this info.
1263 */
1264 rx_desc->read.pkt_addr =
1265 cpu_to_le64(bi->page_dma + bi->page_offset);
1266 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1267 i++;
1268 if (i == rx_ring->count)
1269 i = 0;
1270 }
1271
1272 if (rx_ring->next_to_use != i)
1273 i40e_release_rx_desc(rx_ring, i);
1274
1275 return false;
1276
1277no_buffers:
1278 if (rx_ring->next_to_use != i)
1279 i40e_release_rx_desc(rx_ring, i);
1280
1281 /* make sure to come back via polling to try again after
1282 * allocation failure
1283 */
1284 return true;
1285}
1286
1287/**
1288 * i40e_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
1289 * @rx_ring: ring to place buffers on
1290 * @cleaned_count: number of buffers to replace
1291 *
1292 * Returns true if any errors on allocation
1293 **/
1294bool i40e_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
1295{
1296 u16 i = rx_ring->next_to_use;
1297 union i40e_rx_desc *rx_desc;
1298 struct i40e_rx_buffer *bi;
1299 struct sk_buff *skb;
1300
1301 /* do nothing if no valid netdev defined */
1302 if (!rx_ring->netdev || !cleaned_count)
1303 return false;
1304
1305 while (cleaned_count--) {
1306 rx_desc = I40E_RX_DESC(rx_ring, i);
1307 bi = &rx_ring->rx_bi[i];
1308 skb = bi->skb;
1309
1310 if (!skb) {
1311 skb = __netdev_alloc_skb_ip_align(rx_ring->netdev,
1312 rx_ring->rx_buf_len,
1313 GFP_ATOMIC |
1314 __GFP_NOWARN);
1315 if (!skb) {
1316 rx_ring->rx_stats.alloc_buff_failed++;
1317 goto no_buffers;
1318 }
1319 /* initialize queue mapping */
1320 skb_record_rx_queue(skb, rx_ring->queue_index);
1321 bi->skb = skb;
1322 }
1323
1324 if (!bi->dma) {
1325 bi->dma = dma_map_single(rx_ring->dev,
1326 skb->data,
1327 rx_ring->rx_buf_len,
1328 DMA_FROM_DEVICE);
1329 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1330 rx_ring->rx_stats.alloc_buff_failed++;
1331 bi->dma = 0;
1332 dev_kfree_skb(bi->skb);
1333 bi->skb = NULL;
1334 goto no_buffers;
1335 }
1336 }
1337
1338 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1339 rx_desc->read.hdr_addr = 0;
1340 i++;
1341 if (i == rx_ring->count)
1342 i = 0;
1343 }
1344
1345 if (rx_ring->next_to_use != i)
1346 i40e_release_rx_desc(rx_ring, i);
1347
1348 return false;
1349
1350no_buffers:
1351 if (rx_ring->next_to_use != i)
1352 i40e_release_rx_desc(rx_ring, i);
1353
1354 /* make sure to come back via polling to try again after
1355 * allocation failure
1356 */
1357 return true;
1358}
1359
1360/**
1361 * i40e_receive_skb - Send a completed packet up the stack
1362 * @rx_ring: rx ring in play
1363 * @skb: packet to send up
1364 * @vlan_tag: vlan tag for packet
1365 **/
1366static void i40e_receive_skb(struct i40e_ring *rx_ring,
1367 struct sk_buff *skb, u16 vlan_tag)
1368{
1369 struct i40e_q_vector *q_vector = rx_ring->q_vector;
1370
1371 if (vlan_tag & VLAN_VID_MASK)
1372 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
1373
1374 napi_gro_receive(&q_vector->napi, skb);
1375}
1376
1377/**
1378 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1379 * @vsi: the VSI we care about
1380 * @skb: skb currently being received and modified
1381 * @rx_status: status value of last descriptor in packet
1382 * @rx_error: error value of last descriptor in packet
1383 * @rx_ptype: ptype value of last descriptor in packet
1384 **/
1385static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1386 struct sk_buff *skb,
1387 u32 rx_status,
1388 u32 rx_error,
1389 u16 rx_ptype)
1390{
1391 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
1392 bool ipv4, ipv6, ipv4_tunnel, ipv6_tunnel;
1393
1394 skb->ip_summed = CHECKSUM_NONE;
1395
1396 /* Rx csum enabled and ip headers found? */
1397 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
1398 return;
1399
1400 /* did the hardware decode the packet and checksum? */
1401 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
1402 return;
1403
1404 /* both known and outer_ip must be set for the below code to work */
1405 if (!(decoded.known && decoded.outer_ip))
1406 return;
1407
1408 ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1409 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4);
1410 ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1411 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6);
1412
1413 if (ipv4 &&
1414 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
1415 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
1416 goto checksum_fail;
1417
1418 /* likely incorrect csum if alternate IP extension headers found */
1419 if (ipv6 &&
1420 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
1421 /* don't increment checksum err here, non-fatal err */
1422 return;
1423
1424 /* there was some L4 error, count error and punt packet to the stack */
1425 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
1426 goto checksum_fail;
1427
1428 /* handle packets that were not able to be checksummed due
1429 * to arrival speed, in this case the stack can compute
1430 * the csum.
1431 */
1432 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
1433 return;
1434
1435 /* The hardware supported by this driver does not validate outer
1436 * checksums for tunneled VXLAN or GENEVE frames. I don't agree
1437 * with it but the specification states that you "MAY validate", it
1438 * doesn't make it a hard requirement so if we have validated the
1439 * inner checksum report CHECKSUM_UNNECESSARY.
1440 */
1441
1442 ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
1443 (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
1444 ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
1445 (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
1446
1447 skb->ip_summed = CHECKSUM_UNNECESSARY;
1448 skb->csum_level = ipv4_tunnel || ipv6_tunnel;
1449
1450 return;
1451
1452checksum_fail:
1453 vsi->back->hw_csum_rx_error++;
1454}
1455
1456/**
1457 * i40e_ptype_to_htype - get a hash type
1458 * @ptype: the ptype value from the descriptor
1459 *
1460 * Returns a hash type to be used by skb_set_hash
1461 **/
1462static inline enum pkt_hash_types i40e_ptype_to_htype(u8 ptype)
1463{
1464 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1465
1466 if (!decoded.known)
1467 return PKT_HASH_TYPE_NONE;
1468
1469 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1470 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1471 return PKT_HASH_TYPE_L4;
1472 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1473 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1474 return PKT_HASH_TYPE_L3;
1475 else
1476 return PKT_HASH_TYPE_L2;
1477}
1478
1479/**
1480 * i40e_rx_hash - set the hash value in the skb
1481 * @ring: descriptor ring
1482 * @rx_desc: specific descriptor
1483 **/
1484static inline void i40e_rx_hash(struct i40e_ring *ring,
1485 union i40e_rx_desc *rx_desc,
1486 struct sk_buff *skb,
1487 u8 rx_ptype)
1488{
1489 u32 hash;
1490 const __le64 rss_mask =
1491 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1492 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1493
1494 if (ring->netdev->features & NETIF_F_RXHASH)
1495 return;
1496
1497 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
1498 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1499 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
1500 }
1501}
1502
1503/**
1504 * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
1505 * @rx_ring: rx ring to clean
1506 * @budget: how many cleans we're allowed
1507 *
1508 * Returns true if there's any budget left (e.g. the clean is finished)
1509 **/
1510static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, const int budget)
1511{
1512 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1513 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
1514 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1515 struct i40e_vsi *vsi = rx_ring->vsi;
1516 u16 i = rx_ring->next_to_clean;
1517 union i40e_rx_desc *rx_desc;
1518 u32 rx_error, rx_status;
1519 bool failure = false;
1520 u8 rx_ptype;
1521 u64 qword;
1522 u32 copysize;
1523
1524 if (budget <= 0)
1525 return 0;
1526
1527 do {
1528 struct i40e_rx_buffer *rx_bi;
1529 struct sk_buff *skb;
1530 u16 vlan_tag;
1531 /* return some buffers to hardware, one at a time is too slow */
1532 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1533 failure = failure ||
1534 i40e_alloc_rx_buffers_ps(rx_ring,
1535 cleaned_count);
1536 cleaned_count = 0;
1537 }
1538
1539 i = rx_ring->next_to_clean;
1540 rx_desc = I40E_RX_DESC(rx_ring, i);
1541 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1542 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1543 I40E_RXD_QW1_STATUS_SHIFT;
1544
1545 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1546 break;
1547
1548 /* This memory barrier is needed to keep us from reading
1549 * any other fields out of the rx_desc until we know the
1550 * DD bit is set.
1551 */
1552 dma_rmb();
1553 /* sync header buffer for reading */
1554 dma_sync_single_range_for_cpu(rx_ring->dev,
1555 rx_ring->rx_bi[0].dma,
1556 i * rx_ring->rx_hdr_len,
1557 rx_ring->rx_hdr_len,
1558 DMA_FROM_DEVICE);
1559 if (i40e_rx_is_programming_status(qword)) {
1560 i40e_clean_programming_status(rx_ring, rx_desc);
1561 I40E_RX_INCREMENT(rx_ring, i);
1562 continue;
1563 }
1564 rx_bi = &rx_ring->rx_bi[i];
1565 skb = rx_bi->skb;
1566 if (likely(!skb)) {
1567 skb = __netdev_alloc_skb_ip_align(rx_ring->netdev,
1568 rx_ring->rx_hdr_len,
1569 GFP_ATOMIC |
1570 __GFP_NOWARN);
1571 if (!skb) {
1572 rx_ring->rx_stats.alloc_buff_failed++;
1573 failure = true;
1574 break;
1575 }
1576
1577 /* initialize queue mapping */
1578 skb_record_rx_queue(skb, rx_ring->queue_index);
1579 /* we are reusing so sync this buffer for CPU use */
1580 dma_sync_single_range_for_cpu(rx_ring->dev,
1581 rx_ring->rx_bi[0].dma,
1582 i * rx_ring->rx_hdr_len,
1583 rx_ring->rx_hdr_len,
1584 DMA_FROM_DEVICE);
1585 }
1586 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1587 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1588 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1589 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1590 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1591 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1592
1593 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1594 I40E_RXD_QW1_ERROR_SHIFT;
1595 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1596 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1597
1598 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1599 I40E_RXD_QW1_PTYPE_SHIFT;
1600 /* sync half-page for reading */
1601 dma_sync_single_range_for_cpu(rx_ring->dev,
1602 rx_bi->page_dma,
1603 rx_bi->page_offset,
1604 PAGE_SIZE / 2,
1605 DMA_FROM_DEVICE);
1606 prefetch(page_address(rx_bi->page) + rx_bi->page_offset);
1607 rx_bi->skb = NULL;
1608 cleaned_count++;
1609 copysize = 0;
1610 if (rx_hbo || rx_sph) {
1611 int len;
1612
1613 if (rx_hbo)
1614 len = I40E_RX_HDR_SIZE;
1615 else
1616 len = rx_header_len;
1617 memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1618 } else if (skb->len == 0) {
1619 int len;
1620 unsigned char *va = page_address(rx_bi->page) +
1621 rx_bi->page_offset;
1622
1623 len = min(rx_packet_len, rx_ring->rx_hdr_len);
1624 memcpy(__skb_put(skb, len), va, len);
1625 copysize = len;
1626 rx_packet_len -= len;
1627 }
1628 /* Get the rest of the data if this was a header split */
1629 if (rx_packet_len) {
1630 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1631 rx_bi->page,
1632 rx_bi->page_offset + copysize,
1633 rx_packet_len, I40E_RXBUFFER_2048);
1634
1635 /* If the page count is more than 2, then both halves
1636 * of the page are used and we need to free it. Do it
1637 * here instead of in the alloc code. Otherwise one
1638 * of the half-pages might be released between now and
1639 * then, and we wouldn't know which one to use.
1640 * Don't call get_page and free_page since those are
1641 * both expensive atomic operations that just change
1642 * the refcount in opposite directions. Just give the
1643 * page to the stack; he can have our refcount.
1644 */
1645 if (page_count(rx_bi->page) > 2) {
1646 dma_unmap_page(rx_ring->dev,
1647 rx_bi->page_dma,
1648 PAGE_SIZE,
1649 DMA_FROM_DEVICE);
1650 rx_bi->page = NULL;
1651 rx_bi->page_dma = 0;
1652 rx_ring->rx_stats.realloc_count++;
1653 } else {
1654 get_page(rx_bi->page);
1655 /* switch to the other half-page here; the
1656 * allocation code programs the right addr
1657 * into HW. If we haven't used this half-page,
1658 * the address won't be changed, and HW can
1659 * just use it next time through.
1660 */
1661 rx_bi->page_offset ^= PAGE_SIZE / 2;
1662 }
1663
1664 }
1665 I40E_RX_INCREMENT(rx_ring, i);
1666
1667 if (unlikely(
1668 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1669 struct i40e_rx_buffer *next_buffer;
1670
1671 next_buffer = &rx_ring->rx_bi[i];
1672 next_buffer->skb = skb;
1673 rx_ring->rx_stats.non_eop_descs++;
1674 continue;
1675 }
1676
1677 /* ERR_MASK will only have valid bits if EOP set */
1678 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1679 dev_kfree_skb_any(skb);
1680 continue;
1681 }
1682
1683 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1684
1685 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1686 i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1687 I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1688 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1689 rx_ring->last_rx_timestamp = jiffies;
1690 }
1691
1692 /* probably a little skewed due to removing CRC */
1693 total_rx_bytes += skb->len;
1694 total_rx_packets++;
1695
1696 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1697
1698 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1699
1700 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1701 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1702 : 0;
1703#ifdef I40E_FCOE
1704 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1705 dev_kfree_skb_any(skb);
1706 continue;
1707 }
1708#endif
1709 i40e_receive_skb(rx_ring, skb, vlan_tag);
1710
1711 rx_desc->wb.qword1.status_error_len = 0;
1712
1713 } while (likely(total_rx_packets < budget));
1714
1715 u64_stats_update_begin(&rx_ring->syncp);
1716 rx_ring->stats.packets += total_rx_packets;
1717 rx_ring->stats.bytes += total_rx_bytes;
1718 u64_stats_update_end(&rx_ring->syncp);
1719 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1720 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1721
1722 return failure ? budget : total_rx_packets;
1723}
1724
1725/**
1726 * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1727 * @rx_ring: rx ring to clean
1728 * @budget: how many cleans we're allowed
1729 *
1730 * Returns number of packets cleaned
1731 **/
1732static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1733{
1734 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1735 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1736 struct i40e_vsi *vsi = rx_ring->vsi;
1737 union i40e_rx_desc *rx_desc;
1738 u32 rx_error, rx_status;
1739 u16 rx_packet_len;
1740 bool failure = false;
1741 u8 rx_ptype;
1742 u64 qword;
1743 u16 i;
1744
1745 do {
1746 struct i40e_rx_buffer *rx_bi;
1747 struct sk_buff *skb;
1748 u16 vlan_tag;
1749 /* return some buffers to hardware, one at a time is too slow */
1750 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1751 failure = failure ||
1752 i40e_alloc_rx_buffers_1buf(rx_ring,
1753 cleaned_count);
1754 cleaned_count = 0;
1755 }
1756
1757 i = rx_ring->next_to_clean;
1758 rx_desc = I40E_RX_DESC(rx_ring, i);
1759 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1760 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1761 I40E_RXD_QW1_STATUS_SHIFT;
1762
1763 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1764 break;
1765
1766 /* This memory barrier is needed to keep us from reading
1767 * any other fields out of the rx_desc until we know the
1768 * DD bit is set.
1769 */
1770 dma_rmb();
1771
1772 if (i40e_rx_is_programming_status(qword)) {
1773 i40e_clean_programming_status(rx_ring, rx_desc);
1774 I40E_RX_INCREMENT(rx_ring, i);
1775 continue;
1776 }
1777 rx_bi = &rx_ring->rx_bi[i];
1778 skb = rx_bi->skb;
1779 prefetch(skb->data);
1780
1781 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1782 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1783
1784 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1785 I40E_RXD_QW1_ERROR_SHIFT;
1786 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1787
1788 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1789 I40E_RXD_QW1_PTYPE_SHIFT;
1790 rx_bi->skb = NULL;
1791 cleaned_count++;
1792
1793 /* Get the header and possibly the whole packet
1794 * If this is an skb from previous receive dma will be 0
1795 */
1796 skb_put(skb, rx_packet_len);
1797 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1798 DMA_FROM_DEVICE);
1799 rx_bi->dma = 0;
1800
1801 I40E_RX_INCREMENT(rx_ring, i);
1802
1803 if (unlikely(
1804 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1805 rx_ring->rx_stats.non_eop_descs++;
1806 continue;
1807 }
1808
1809 /* ERR_MASK will only have valid bits if EOP set */
1810 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1811 dev_kfree_skb_any(skb);
1812 continue;
1813 }
1814
1815 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1816 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1817 i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1818 I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1819 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1820 rx_ring->last_rx_timestamp = jiffies;
1821 }
1822
1823 /* probably a little skewed due to removing CRC */
1824 total_rx_bytes += skb->len;
1825 total_rx_packets++;
1826
1827 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1828
1829 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1830
1831 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1832 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1833 : 0;
1834#ifdef I40E_FCOE
1835 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1836 dev_kfree_skb_any(skb);
1837 continue;
1838 }
1839#endif
1840 i40e_receive_skb(rx_ring, skb, vlan_tag);
1841
1842 rx_desc->wb.qword1.status_error_len = 0;
1843 } while (likely(total_rx_packets < budget));
1844
1845 u64_stats_update_begin(&rx_ring->syncp);
1846 rx_ring->stats.packets += total_rx_packets;
1847 rx_ring->stats.bytes += total_rx_bytes;
1848 u64_stats_update_end(&rx_ring->syncp);
1849 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1850 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1851
1852 return failure ? budget : total_rx_packets;
1853}
1854
1855static u32 i40e_buildreg_itr(const int type, const u16 itr)
1856{
1857 u32 val;
1858
1859 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1860 /* Don't clear PBA because that can cause lost interrupts that
1861 * came in while we were cleaning/polling
1862 */
1863 (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1864 (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);
1865
1866 return val;
1867}
1868
1869/* a small macro to shorten up some long lines */
1870#define INTREG I40E_PFINT_DYN_CTLN
1871
1872/**
1873 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1874 * @vsi: the VSI we care about
1875 * @q_vector: q_vector for which itr is being updated and interrupt enabled
1876 *
1877 **/
1878static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1879 struct i40e_q_vector *q_vector)
1880{
1881 struct i40e_hw *hw = &vsi->back->hw;
1882 bool rx = false, tx = false;
1883 u32 rxval, txval;
1884 int vector;
1885 int idx = q_vector->v_idx;
1886
1887 vector = (q_vector->v_idx + vsi->base_vector);
1888
1889 /* avoid dynamic calculation if in countdown mode OR if
1890 * all dynamic is disabled
1891 */
1892 rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1893
1894 if (q_vector->itr_countdown > 0 ||
1895 (!ITR_IS_DYNAMIC(vsi->rx_rings[idx]->rx_itr_setting) &&
1896 !ITR_IS_DYNAMIC(vsi->tx_rings[idx]->tx_itr_setting))) {
1897 goto enable_int;
1898 }
1899
1900 if (ITR_IS_DYNAMIC(vsi->rx_rings[idx]->rx_itr_setting)) {
1901 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1902 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
1903 }
1904
1905 if (ITR_IS_DYNAMIC(vsi->tx_rings[idx]->tx_itr_setting)) {
1906 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1907 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1908 }
1909
1910 if (rx || tx) {
1911 /* get the higher of the two ITR adjustments and
1912 * use the same value for both ITR registers
1913 * when in adaptive mode (Rx and/or Tx)
1914 */
1915 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1916
1917 q_vector->tx.itr = q_vector->rx.itr = itr;
1918 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1919 tx = true;
1920 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1921 rx = true;
1922 }
1923
1924 /* only need to enable the interrupt once, but need
1925 * to possibly update both ITR values
1926 */
1927 if (rx) {
1928 /* set the INTENA_MSK_MASK so that this first write
1929 * won't actually enable the interrupt, instead just
1930 * updating the ITR (it's bit 31 PF and VF)
1931 */
1932 rxval |= BIT(31);
1933 /* don't check _DOWN because interrupt isn't being enabled */
1934 wr32(hw, INTREG(vector - 1), rxval);
1935 }
1936
1937enable_int:
1938 if (!test_bit(__I40E_DOWN, &vsi->state))
1939 wr32(hw, INTREG(vector - 1), txval);
1940
1941 if (q_vector->itr_countdown)
1942 q_vector->itr_countdown--;
1943 else
1944 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1945}
1946
1947/**
1948 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
1949 * @napi: napi struct with our devices info in it
1950 * @budget: amount of work driver is allowed to do this pass, in packets
1951 *
1952 * This function will clean all queues associated with a q_vector.
1953 *
1954 * Returns the amount of work done
1955 **/
1956int i40e_napi_poll(struct napi_struct *napi, int budget)
1957{
1958 struct i40e_q_vector *q_vector =
1959 container_of(napi, struct i40e_q_vector, napi);
1960 struct i40e_vsi *vsi = q_vector->vsi;
1961 struct i40e_ring *ring;
1962 bool clean_complete = true;
1963 bool arm_wb = false;
1964 int budget_per_ring;
1965 int work_done = 0;
1966
1967 if (test_bit(__I40E_DOWN, &vsi->state)) {
1968 napi_complete(napi);
1969 return 0;
1970 }
1971
1972 /* Clear hung_detected bit */
1973 clear_bit(I40E_Q_VECTOR_HUNG_DETECT, &q_vector->hung_detected);
1974 /* Since the actual Tx work is minimal, we can give the Tx a larger
1975 * budget and be more aggressive about cleaning up the Tx descriptors.
1976 */
1977 i40e_for_each_ring(ring, q_vector->tx) {
1978 clean_complete = clean_complete &&
1979 i40e_clean_tx_irq(ring, vsi->work_limit);
1980 arm_wb = arm_wb || ring->arm_wb;
1981 ring->arm_wb = false;
1982 }
1983
1984 /* Handle case where we are called by netpoll with a budget of 0 */
1985 if (budget <= 0)
1986 goto tx_only;
1987
1988 /* We attempt to distribute budget to each Rx queue fairly, but don't
1989 * allow the budget to go below 1 because that would exit polling early.
1990 */
1991 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1992
1993 i40e_for_each_ring(ring, q_vector->rx) {
1994 int cleaned;
1995
1996 if (ring_is_ps_enabled(ring))
1997 cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1998 else
1999 cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
2000
2001 work_done += cleaned;
2002 /* if we didn't clean as many as budgeted, we must be done */
2003 clean_complete = clean_complete && (budget_per_ring > cleaned);
2004 }
2005
2006 /* If work not completed, return budget and polling will return */
2007 if (!clean_complete) {
2008tx_only:
2009 if (arm_wb) {
2010 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
2011 i40e_enable_wb_on_itr(vsi, q_vector);
2012 }
2013 return budget;
2014 }
2015
2016 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
2017 q_vector->arm_wb_state = false;
2018
2019 /* Work is done so exit the polling mode and re-enable the interrupt */
2020 napi_complete_done(napi, work_done);
2021 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
2022 i40e_update_enable_itr(vsi, q_vector);
2023 } else { /* Legacy mode */
2024 i40e_irq_dynamic_enable_icr0(vsi->back, false);
2025 }
2026 return 0;
2027}
2028
2029/**
2030 * i40e_atr - Add a Flow Director ATR filter
2031 * @tx_ring: ring to add programming descriptor to
2032 * @skb: send buffer
2033 * @tx_flags: send tx flags
2034 **/
2035static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
2036 u32 tx_flags)
2037{
2038 struct i40e_filter_program_desc *fdir_desc;
2039 struct i40e_pf *pf = tx_ring->vsi->back;
2040 union {
2041 unsigned char *network;
2042 struct iphdr *ipv4;
2043 struct ipv6hdr *ipv6;
2044 } hdr;
2045 struct tcphdr *th;
2046 unsigned int hlen;
2047 u32 flex_ptype, dtype_cmd;
2048 int l4_proto;
2049 u16 i;
2050
2051 /* make sure ATR is enabled */
2052 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
2053 return;
2054
2055 if ((pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
2056 return;
2057
2058 /* if sampling is disabled do nothing */
2059 if (!tx_ring->atr_sample_rate)
2060 return;
2061
2062 /* Currently only IPv4/IPv6 with TCP is supported */
2063 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6)))
2064 return;
2065
2066 /* snag network header to get L4 type and address */
2067 hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ?
2068 skb_inner_network_header(skb) : skb_network_header(skb);
2069
2070 /* Note: tx_flags gets modified to reflect inner protocols in
2071 * tx_enable_csum function if encap is enabled.
2072 */
2073 if (tx_flags & I40E_TX_FLAGS_IPV4) {
2074 /* access ihl as u8 to avoid unaligned access on ia64 */
2075 hlen = (hdr.network[0] & 0x0F) << 2;
2076 l4_proto = hdr.ipv4->protocol;
2077 } else {
2078 hlen = hdr.network - skb->data;
2079 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL);
2080 hlen -= hdr.network - skb->data;
2081 }
2082
2083 if (l4_proto != IPPROTO_TCP)
2084 return;
2085
2086 th = (struct tcphdr *)(hdr.network + hlen);
2087
2088 /* Due to lack of space, no more new filters can be programmed */
2089 if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
2090 return;
2091 if ((pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) &&
2092 (!(pf->auto_disable_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE))) {
2093 /* HW ATR eviction will take care of removing filters on FIN
2094 * and RST packets.
2095 */
2096 if (th->fin || th->rst)
2097 return;
2098 }
2099
2100 tx_ring->atr_count++;
2101
2102 /* sample on all syn/fin/rst packets or once every atr sample rate */
2103 if (!th->fin &&
2104 !th->syn &&
2105 !th->rst &&
2106 (tx_ring->atr_count < tx_ring->atr_sample_rate))
2107 return;
2108
2109 tx_ring->atr_count = 0;
2110
2111 /* grab the next descriptor */
2112 i = tx_ring->next_to_use;
2113 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
2114
2115 i++;
2116 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2117
2118 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
2119 I40E_TXD_FLTR_QW0_QINDEX_MASK;
2120 flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ?
2121 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
2122 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
2123 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
2124 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
2125
2126 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
2127
2128 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
2129
2130 dtype_cmd |= (th->fin || th->rst) ?
2131 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2132 I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
2133 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2134 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2135
2136 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
2137 I40E_TXD_FLTR_QW1_DEST_SHIFT;
2138
2139 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
2140 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
2141
2142 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
2143 if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL))
2144 dtype_cmd |=
2145 ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) <<
2146 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2147 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2148 else
2149 dtype_cmd |=
2150 ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) <<
2151 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2152 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2153
2154 if ((pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) &&
2155 (!(pf->auto_disable_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE)))
2156 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;
2157
2158 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
2159 fdir_desc->rsvd = cpu_to_le32(0);
2160 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
2161 fdir_desc->fd_id = cpu_to_le32(0);
2162}
2163
2164/**
2165 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2166 * @skb: send buffer
2167 * @tx_ring: ring to send buffer on
2168 * @flags: the tx flags to be set
2169 *
2170 * Checks the skb and set up correspondingly several generic transmit flags
2171 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2172 *
2173 * Returns error code indicate the frame should be dropped upon error and the
2174 * otherwise returns 0 to indicate the flags has been set properly.
2175 **/
2176#ifdef I40E_FCOE
2177inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2178 struct i40e_ring *tx_ring,
2179 u32 *flags)
2180#else
2181static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2182 struct i40e_ring *tx_ring,
2183 u32 *flags)
2184#endif
2185{
2186 __be16 protocol = skb->protocol;
2187 u32 tx_flags = 0;
2188
2189 if (protocol == htons(ETH_P_8021Q) &&
2190 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
2191 /* When HW VLAN acceleration is turned off by the user the
2192 * stack sets the protocol to 8021q so that the driver
2193 * can take any steps required to support the SW only
2194 * VLAN handling. In our case the driver doesn't need
2195 * to take any further steps so just set the protocol
2196 * to the encapsulated ethertype.
2197 */
2198 skb->protocol = vlan_get_protocol(skb);
2199 goto out;
2200 }
2201
2202 /* if we have a HW VLAN tag being added, default to the HW one */
2203 if (skb_vlan_tag_present(skb)) {
2204 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
2205 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2206 /* else if it is a SW VLAN, check the next protocol and store the tag */
2207 } else if (protocol == htons(ETH_P_8021Q)) {
2208 struct vlan_hdr *vhdr, _vhdr;
2209
2210 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
2211 if (!vhdr)
2212 return -EINVAL;
2213
2214 protocol = vhdr->h_vlan_encapsulated_proto;
2215 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
2216 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
2217 }
2218
2219 if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2220 goto out;
2221
2222 /* Insert 802.1p priority into VLAN header */
2223 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
2224 (skb->priority != TC_PRIO_CONTROL)) {
2225 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
2226 tx_flags |= (skb->priority & 0x7) <<
2227 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
2228 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
2229 struct vlan_ethhdr *vhdr;
2230 int rc;
2231
2232 rc = skb_cow_head(skb, 0);
2233 if (rc < 0)
2234 return rc;
2235 vhdr = (struct vlan_ethhdr *)skb->data;
2236 vhdr->h_vlan_TCI = htons(tx_flags >>
2237 I40E_TX_FLAGS_VLAN_SHIFT);
2238 } else {
2239 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2240 }
2241 }
2242
2243out:
2244 *flags = tx_flags;
2245 return 0;
2246}
2247
2248/**
2249 * i40e_tso - set up the tso context descriptor
2250 * @tx_ring: ptr to the ring to send
2251 * @skb: ptr to the skb we're sending
2252 * @hdr_len: ptr to the size of the packet header
2253 * @cd_type_cmd_tso_mss: Quad Word 1
2254 *
2255 * Returns 0 if no TSO can happen, 1 if tso is going, or error
2256 **/
2257static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
2258 u8 *hdr_len, u64 *cd_type_cmd_tso_mss)
2259{
2260 u64 cd_cmd, cd_tso_len, cd_mss;
2261 union {
2262 struct iphdr *v4;
2263 struct ipv6hdr *v6;
2264 unsigned char *hdr;
2265 } ip;
2266 union {
2267 struct tcphdr *tcp;
2268 struct udphdr *udp;
2269 unsigned char *hdr;
2270 } l4;
2271 u32 paylen, l4_offset;
2272 int err;
2273
2274 if (skb->ip_summed != CHECKSUM_PARTIAL)
2275 return 0;
2276
2277 if (!skb_is_gso(skb))
2278 return 0;
2279
2280 err = skb_cow_head(skb, 0);
2281 if (err < 0)
2282 return err;
2283
2284 ip.hdr = skb_network_header(skb);
2285 l4.hdr = skb_transport_header(skb);
2286
2287 /* initialize outer IP header fields */
2288 if (ip.v4->version == 4) {
2289 ip.v4->tot_len = 0;
2290 ip.v4->check = 0;
2291 } else {
2292 ip.v6->payload_len = 0;
2293 }
2294
2295 if (skb_shinfo(skb)->gso_type & (SKB_GSO_UDP_TUNNEL | SKB_GSO_GRE |
2296 SKB_GSO_UDP_TUNNEL_CSUM)) {
2297 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM) {
2298 /* determine offset of outer transport header */
2299 l4_offset = l4.hdr - skb->data;
2300
2301 /* remove payload length from outer checksum */
2302 paylen = (__force u16)l4.udp->check;
2303 paylen += ntohs(1) * (u16)~(skb->len - l4_offset);
2304 l4.udp->check = ~csum_fold((__force __wsum)paylen);
2305 }
2306
2307 /* reset pointers to inner headers */
2308 ip.hdr = skb_inner_network_header(skb);
2309 l4.hdr = skb_inner_transport_header(skb);
2310
2311 /* initialize inner IP header fields */
2312 if (ip.v4->version == 4) {
2313 ip.v4->tot_len = 0;
2314 ip.v4->check = 0;
2315 } else {
2316 ip.v6->payload_len = 0;
2317 }
2318 }
2319
2320 /* determine offset of inner transport header */
2321 l4_offset = l4.hdr - skb->data;
2322
2323 /* remove payload length from inner checksum */
2324 paylen = (__force u16)l4.tcp->check;
2325 paylen += ntohs(1) * (u16)~(skb->len - l4_offset);
2326 l4.tcp->check = ~csum_fold((__force __wsum)paylen);
2327
2328 /* compute length of segmentation header */
2329 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
2330
2331 /* find the field values */
2332 cd_cmd = I40E_TX_CTX_DESC_TSO;
2333 cd_tso_len = skb->len - *hdr_len;
2334 cd_mss = skb_shinfo(skb)->gso_size;
2335 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
2336 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2337 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
2338 return 1;
2339}
2340
2341/**
2342 * i40e_tsyn - set up the tsyn context descriptor
2343 * @tx_ring: ptr to the ring to send
2344 * @skb: ptr to the skb we're sending
2345 * @tx_flags: the collected send information
2346 * @cd_type_cmd_tso_mss: Quad Word 1
2347 *
2348 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
2349 **/
2350static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
2351 u32 tx_flags, u64 *cd_type_cmd_tso_mss)
2352{
2353 struct i40e_pf *pf;
2354
2355 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
2356 return 0;
2357
2358 /* Tx timestamps cannot be sampled when doing TSO */
2359 if (tx_flags & I40E_TX_FLAGS_TSO)
2360 return 0;
2361
2362 /* only timestamp the outbound packet if the user has requested it and
2363 * we are not already transmitting a packet to be timestamped
2364 */
2365 pf = i40e_netdev_to_pf(tx_ring->netdev);
2366 if (!(pf->flags & I40E_FLAG_PTP))
2367 return 0;
2368
2369 if (pf->ptp_tx &&
2370 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, &pf->state)) {
2371 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2372 pf->ptp_tx_skb = skb_get(skb);
2373 } else {
2374 return 0;
2375 }
2376
2377 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
2378 I40E_TXD_CTX_QW1_CMD_SHIFT;
2379
2380 return 1;
2381}
2382
2383/**
2384 * i40e_tx_enable_csum - Enable Tx checksum offloads
2385 * @skb: send buffer
2386 * @tx_flags: pointer to Tx flags currently set
2387 * @td_cmd: Tx descriptor command bits to set
2388 * @td_offset: Tx descriptor header offsets to set
2389 * @tx_ring: Tx descriptor ring
2390 * @cd_tunneling: ptr to context desc bits
2391 **/
2392static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
2393 u32 *td_cmd, u32 *td_offset,
2394 struct i40e_ring *tx_ring,
2395 u32 *cd_tunneling)
2396{
2397 union {
2398 struct iphdr *v4;
2399 struct ipv6hdr *v6;
2400 unsigned char *hdr;
2401 } ip;
2402 union {
2403 struct tcphdr *tcp;
2404 struct udphdr *udp;
2405 unsigned char *hdr;
2406 } l4;
2407 unsigned char *exthdr;
2408 u32 offset, cmd = 0, tunnel = 0;
2409 __be16 frag_off;
2410 u8 l4_proto = 0;
2411
2412 if (skb->ip_summed != CHECKSUM_PARTIAL)
2413 return 0;
2414
2415 ip.hdr = skb_network_header(skb);
2416 l4.hdr = skb_transport_header(skb);
2417
2418 /* compute outer L2 header size */
2419 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
2420
2421 if (skb->encapsulation) {
2422 /* define outer network header type */
2423 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
2424 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
2425 I40E_TX_CTX_EXT_IP_IPV4 :
2426 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
2427
2428 l4_proto = ip.v4->protocol;
2429 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
2430 tunnel |= I40E_TX_CTX_EXT_IP_IPV6;
2431
2432 exthdr = ip.hdr + sizeof(*ip.v6);
2433 l4_proto = ip.v6->nexthdr;
2434 if (l4.hdr != exthdr)
2435 ipv6_skip_exthdr(skb, exthdr - skb->data,
2436 &l4_proto, &frag_off);
2437 }
2438
2439 /* compute outer L3 header size */
2440 tunnel |= ((l4.hdr - ip.hdr) / 4) <<
2441 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
2442
2443 /* switch IP header pointer from outer to inner header */
2444 ip.hdr = skb_inner_network_header(skb);
2445
2446 /* define outer transport */
2447 switch (l4_proto) {
2448 case IPPROTO_UDP:
2449 tunnel |= I40E_TXD_CTX_UDP_TUNNELING;
2450 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
2451 break;
2452 case IPPROTO_GRE:
2453 tunnel |= I40E_TXD_CTX_GRE_TUNNELING;
2454 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
2455 break;
2456 default:
2457 if (*tx_flags & I40E_TX_FLAGS_TSO)
2458 return -1;
2459
2460 skb_checksum_help(skb);
2461 return 0;
2462 }
2463
2464 /* compute tunnel header size */
2465 tunnel |= ((ip.hdr - l4.hdr) / 2) <<
2466 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
2467
2468 /* indicate if we need to offload outer UDP header */
2469 if ((*tx_flags & I40E_TX_FLAGS_TSO) &&
2470 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
2471 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
2472
2473 /* record tunnel offload values */
2474 *cd_tunneling |= tunnel;
2475
2476 /* switch L4 header pointer from outer to inner */
2477 l4.hdr = skb_inner_transport_header(skb);
2478 l4_proto = 0;
2479
2480 /* reset type as we transition from outer to inner headers */
2481 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6);
2482 if (ip.v4->version == 4)
2483 *tx_flags |= I40E_TX_FLAGS_IPV4;
2484 if (ip.v6->version == 6)
2485 *tx_flags |= I40E_TX_FLAGS_IPV6;
2486 }
2487
2488 /* Enable IP checksum offloads */
2489 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
2490 l4_proto = ip.v4->protocol;
2491 /* the stack computes the IP header already, the only time we
2492 * need the hardware to recompute it is in the case of TSO.
2493 */
2494 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
2495 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM :
2496 I40E_TX_DESC_CMD_IIPT_IPV4;
2497 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
2498 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
2499
2500 exthdr = ip.hdr + sizeof(*ip.v6);
2501 l4_proto = ip.v6->nexthdr;
2502 if (l4.hdr != exthdr)
2503 ipv6_skip_exthdr(skb, exthdr - skb->data,
2504 &l4_proto, &frag_off);
2505 }
2506
2507 /* compute inner L3 header size */
2508 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
2509
2510 /* Enable L4 checksum offloads */
2511 switch (l4_proto) {
2512 case IPPROTO_TCP:
2513 /* enable checksum offloads */
2514 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
2515 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2516 break;
2517 case IPPROTO_SCTP:
2518 /* enable SCTP checksum offload */
2519 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
2520 offset |= (sizeof(struct sctphdr) >> 2) <<
2521 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2522 break;
2523 case IPPROTO_UDP:
2524 /* enable UDP checksum offload */
2525 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
2526 offset |= (sizeof(struct udphdr) >> 2) <<
2527 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2528 break;
2529 default:
2530 if (*tx_flags & I40E_TX_FLAGS_TSO)
2531 return -1;
2532 skb_checksum_help(skb);
2533 return 0;
2534 }
2535
2536 *td_cmd |= cmd;
2537 *td_offset |= offset;
2538
2539 return 1;
2540}
2541
2542/**
2543 * i40e_create_tx_ctx Build the Tx context descriptor
2544 * @tx_ring: ring to create the descriptor on
2545 * @cd_type_cmd_tso_mss: Quad Word 1
2546 * @cd_tunneling: Quad Word 0 - bits 0-31
2547 * @cd_l2tag2: Quad Word 0 - bits 32-63
2548 **/
2549static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
2550 const u64 cd_type_cmd_tso_mss,
2551 const u32 cd_tunneling, const u32 cd_l2tag2)
2552{
2553 struct i40e_tx_context_desc *context_desc;
2554 int i = tx_ring->next_to_use;
2555
2556 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
2557 !cd_tunneling && !cd_l2tag2)
2558 return;
2559
2560 /* grab the next descriptor */
2561 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
2562
2563 i++;
2564 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2565
2566 /* cpu_to_le32 and assign to struct fields */
2567 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
2568 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
2569 context_desc->rsvd = cpu_to_le16(0);
2570 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
2571}
2572
2573/**
2574 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
2575 * @tx_ring: the ring to be checked
2576 * @size: the size buffer we want to assure is available
2577 *
2578 * Returns -EBUSY if a stop is needed, else 0
2579 **/
2580int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2581{
2582 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
2583 /* Memory barrier before checking head and tail */
2584 smp_mb();
2585
2586 /* Check again in a case another CPU has just made room available. */
2587 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
2588 return -EBUSY;
2589
2590 /* A reprieve! - use start_queue because it doesn't call schedule */
2591 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
2592 ++tx_ring->tx_stats.restart_queue;
2593 return 0;
2594}
2595
2596/**
2597 * __i40e_chk_linearize - Check if there are more than 8 buffers per packet
2598 * @skb: send buffer
2599 *
2600 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
2601 * and so we need to figure out the cases where we need to linearize the skb.
2602 *
2603 * For TSO we need to count the TSO header and segment payload separately.
2604 * As such we need to check cases where we have 7 fragments or more as we
2605 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
2606 * the segment payload in the first descriptor, and another 7 for the
2607 * fragments.
2608 **/
2609bool __i40e_chk_linearize(struct sk_buff *skb)
2610{
2611 const struct skb_frag_struct *frag, *stale;
2612 int nr_frags, sum;
2613
2614 /* no need to check if number of frags is less than 7 */
2615 nr_frags = skb_shinfo(skb)->nr_frags;
2616 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1))
2617 return false;
2618
2619 /* We need to walk through the list and validate that each group
2620 * of 6 fragments totals at least gso_size. However we don't need
2621 * to perform such validation on the last 6 since the last 6 cannot
2622 * inherit any data from a descriptor after them.
2623 */
2624 nr_frags -= I40E_MAX_BUFFER_TXD - 2;
2625 frag = &skb_shinfo(skb)->frags[0];
2626
2627 /* Initialize size to the negative value of gso_size minus 1. We
2628 * use this as the worst case scenerio in which the frag ahead
2629 * of us only provides one byte which is why we are limited to 6
2630 * descriptors for a single transmit as the header and previous
2631 * fragment are already consuming 2 descriptors.
2632 */
2633 sum = 1 - skb_shinfo(skb)->gso_size;
2634
2635 /* Add size of frags 0 through 4 to create our initial sum */
2636 sum += skb_frag_size(frag++);
2637 sum += skb_frag_size(frag++);
2638 sum += skb_frag_size(frag++);
2639 sum += skb_frag_size(frag++);
2640 sum += skb_frag_size(frag++);
2641
2642 /* Walk through fragments adding latest fragment, testing it, and
2643 * then removing stale fragments from the sum.
2644 */
2645 stale = &skb_shinfo(skb)->frags[0];
2646 for (;;) {
2647 sum += skb_frag_size(frag++);
2648
2649 /* if sum is negative we failed to make sufficient progress */
2650 if (sum < 0)
2651 return true;
2652
2653 /* use pre-decrement to avoid processing last fragment */
2654 if (!--nr_frags)
2655 break;
2656
2657 sum -= skb_frag_size(stale++);
2658 }
2659
2660 return false;
2661}
2662
2663/**
2664 * i40e_tx_map - Build the Tx descriptor
2665 * @tx_ring: ring to send buffer on
2666 * @skb: send buffer
2667 * @first: first buffer info buffer to use
2668 * @tx_flags: collected send information
2669 * @hdr_len: size of the packet header
2670 * @td_cmd: the command field in the descriptor
2671 * @td_offset: offset for checksum or crc
2672 **/
2673#ifdef I40E_FCOE
2674inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
2675 struct i40e_tx_buffer *first, u32 tx_flags,
2676 const u8 hdr_len, u32 td_cmd, u32 td_offset)
2677#else
2678static inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
2679 struct i40e_tx_buffer *first, u32 tx_flags,
2680 const u8 hdr_len, u32 td_cmd, u32 td_offset)
2681#endif
2682{
2683 unsigned int data_len = skb->data_len;
2684 unsigned int size = skb_headlen(skb);
2685 struct skb_frag_struct *frag;
2686 struct i40e_tx_buffer *tx_bi;
2687 struct i40e_tx_desc *tx_desc;
2688 u16 i = tx_ring->next_to_use;
2689 u32 td_tag = 0;
2690 dma_addr_t dma;
2691 u16 gso_segs;
2692 u16 desc_count = 0;
2693 bool tail_bump = true;
2694 bool do_rs = false;
2695
2696 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
2697 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
2698 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
2699 I40E_TX_FLAGS_VLAN_SHIFT;
2700 }
2701
2702 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
2703 gso_segs = skb_shinfo(skb)->gso_segs;
2704 else
2705 gso_segs = 1;
2706
2707 /* multiply data chunks by size of headers */
2708 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
2709 first->gso_segs = gso_segs;
2710 first->skb = skb;
2711 first->tx_flags = tx_flags;
2712
2713 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
2714
2715 tx_desc = I40E_TX_DESC(tx_ring, i);
2716 tx_bi = first;
2717
2718 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
2719 if (dma_mapping_error(tx_ring->dev, dma))
2720 goto dma_error;
2721
2722 /* record length, and DMA address */
2723 dma_unmap_len_set(tx_bi, len, size);
2724 dma_unmap_addr_set(tx_bi, dma, dma);
2725
2726 tx_desc->buffer_addr = cpu_to_le64(dma);
2727
2728 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
2729 tx_desc->cmd_type_offset_bsz =
2730 build_ctob(td_cmd, td_offset,
2731 I40E_MAX_DATA_PER_TXD, td_tag);
2732
2733 tx_desc++;
2734 i++;
2735 desc_count++;
2736
2737 if (i == tx_ring->count) {
2738 tx_desc = I40E_TX_DESC(tx_ring, 0);
2739 i = 0;
2740 }
2741
2742 dma += I40E_MAX_DATA_PER_TXD;
2743 size -= I40E_MAX_DATA_PER_TXD;
2744
2745 tx_desc->buffer_addr = cpu_to_le64(dma);
2746 }
2747
2748 if (likely(!data_len))
2749 break;
2750
2751 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
2752 size, td_tag);
2753
2754 tx_desc++;
2755 i++;
2756 desc_count++;
2757
2758 if (i == tx_ring->count) {
2759 tx_desc = I40E_TX_DESC(tx_ring, 0);
2760 i = 0;
2761 }
2762
2763 size = skb_frag_size(frag);
2764 data_len -= size;
2765
2766 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
2767 DMA_TO_DEVICE);
2768
2769 tx_bi = &tx_ring->tx_bi[i];
2770 }
2771
2772 /* set next_to_watch value indicating a packet is present */
2773 first->next_to_watch = tx_desc;
2774
2775 i++;
2776 if (i == tx_ring->count)
2777 i = 0;
2778
2779 tx_ring->next_to_use = i;
2780
2781 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
2782 tx_ring->queue_index),
2783 first->bytecount);
2784 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
2785
2786 /* Algorithm to optimize tail and RS bit setting:
2787 * if xmit_more is supported
2788 * if xmit_more is true
2789 * do not update tail and do not mark RS bit.
2790 * if xmit_more is false and last xmit_more was false
2791 * if every packet spanned less than 4 desc
2792 * then set RS bit on 4th packet and update tail
2793 * on every packet
2794 * else
2795 * update tail and set RS bit on every packet.
2796 * if xmit_more is false and last_xmit_more was true
2797 * update tail and set RS bit.
2798 *
2799 * Optimization: wmb to be issued only in case of tail update.
2800 * Also optimize the Descriptor WB path for RS bit with the same
2801 * algorithm.
2802 *
2803 * Note: If there are less than 4 packets
2804 * pending and interrupts were disabled the service task will
2805 * trigger a force WB.
2806 */
2807 if (skb->xmit_more &&
2808 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2809 tx_ring->queue_index))) {
2810 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2811 tail_bump = false;
2812 } else if (!skb->xmit_more &&
2813 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2814 tx_ring->queue_index)) &&
2815 (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&
2816 (tx_ring->packet_stride < WB_STRIDE) &&
2817 (desc_count < WB_STRIDE)) {
2818 tx_ring->packet_stride++;
2819 } else {
2820 tx_ring->packet_stride = 0;
2821 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2822 do_rs = true;
2823 }
2824 if (do_rs)
2825 tx_ring->packet_stride = 0;
2826
2827 tx_desc->cmd_type_offset_bsz =
2828 build_ctob(td_cmd, td_offset, size, td_tag) |
2829 cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :
2830 I40E_TX_DESC_CMD_EOP) <<
2831 I40E_TXD_QW1_CMD_SHIFT);
2832
2833 /* notify HW of packet */
2834 if (!tail_bump)
2835 prefetchw(tx_desc + 1);
2836
2837 if (tail_bump) {
2838 /* Force memory writes to complete before letting h/w
2839 * know there are new descriptors to fetch. (Only
2840 * applicable for weak-ordered memory model archs,
2841 * such as IA-64).
2842 */
2843 wmb();
2844 writel(i, tx_ring->tail);
2845 }
2846
2847 return;
2848
2849dma_error:
2850 dev_info(tx_ring->dev, "TX DMA map failed\n");
2851
2852 /* clear dma mappings for failed tx_bi map */
2853 for (;;) {
2854 tx_bi = &tx_ring->tx_bi[i];
2855 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
2856 if (tx_bi == first)
2857 break;
2858 if (i == 0)
2859 i = tx_ring->count;
2860 i--;
2861 }
2862
2863 tx_ring->next_to_use = i;
2864}
2865
2866/**
2867 * i40e_xmit_frame_ring - Sends buffer on Tx ring
2868 * @skb: send buffer
2869 * @tx_ring: ring to send buffer on
2870 *
2871 * Returns NETDEV_TX_OK if sent, else an error code
2872 **/
2873static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2874 struct i40e_ring *tx_ring)
2875{
2876 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2877 u32 cd_tunneling = 0, cd_l2tag2 = 0;
2878 struct i40e_tx_buffer *first;
2879 u32 td_offset = 0;
2880 u32 tx_flags = 0;
2881 __be16 protocol;
2882 u32 td_cmd = 0;
2883 u8 hdr_len = 0;
2884 int tso, count;
2885 int tsyn;
2886
2887 /* prefetch the data, we'll need it later */
2888 prefetch(skb->data);
2889
2890 count = i40e_xmit_descriptor_count(skb);
2891 if (i40e_chk_linearize(skb, count)) {
2892 if (__skb_linearize(skb))
2893 goto out_drop;
2894 count = TXD_USE_COUNT(skb->len);
2895 tx_ring->tx_stats.tx_linearize++;
2896 }
2897
2898 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2899 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
2900 * + 4 desc gap to avoid the cache line where head is,
2901 * + 1 desc for context descriptor,
2902 * otherwise try next time
2903 */
2904 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
2905 tx_ring->tx_stats.tx_busy++;
2906 return NETDEV_TX_BUSY;
2907 }
2908
2909 /* prepare the xmit flags */
2910 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2911 goto out_drop;
2912
2913 /* obtain protocol of skb */
2914 protocol = vlan_get_protocol(skb);
2915
2916 /* record the location of the first descriptor for this packet */
2917 first = &tx_ring->tx_bi[tx_ring->next_to_use];
2918
2919 /* setup IPv4/IPv6 offloads */
2920 if (protocol == htons(ETH_P_IP))
2921 tx_flags |= I40E_TX_FLAGS_IPV4;
2922 else if (protocol == htons(ETH_P_IPV6))
2923 tx_flags |= I40E_TX_FLAGS_IPV6;
2924
2925 tso = i40e_tso(tx_ring, skb, &hdr_len, &cd_type_cmd_tso_mss);
2926
2927 if (tso < 0)
2928 goto out_drop;
2929 else if (tso)
2930 tx_flags |= I40E_TX_FLAGS_TSO;
2931
2932 /* Always offload the checksum, since it's in the data descriptor */
2933 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2934 tx_ring, &cd_tunneling);
2935 if (tso < 0)
2936 goto out_drop;
2937
2938 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
2939
2940 if (tsyn)
2941 tx_flags |= I40E_TX_FLAGS_TSYN;
2942
2943 skb_tx_timestamp(skb);
2944
2945 /* always enable CRC insertion offload */
2946 td_cmd |= I40E_TX_DESC_CMD_ICRC;
2947
2948 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2949 cd_tunneling, cd_l2tag2);
2950
2951 /* Add Flow Director ATR if it's enabled.
2952 *
2953 * NOTE: this must always be directly before the data descriptor.
2954 */
2955 i40e_atr(tx_ring, skb, tx_flags);
2956
2957 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2958 td_cmd, td_offset);
2959
2960 return NETDEV_TX_OK;
2961
2962out_drop:
2963 dev_kfree_skb_any(skb);
2964 return NETDEV_TX_OK;
2965}
2966
2967/**
2968 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2969 * @skb: send buffer
2970 * @netdev: network interface device structure
2971 *
2972 * Returns NETDEV_TX_OK if sent, else an error code
2973 **/
2974netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2975{
2976 struct i40e_netdev_priv *np = netdev_priv(netdev);
2977 struct i40e_vsi *vsi = np->vsi;
2978 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
2979
2980 /* hardware can't handle really short frames, hardware padding works
2981 * beyond this point
2982 */
2983 if (skb_put_padto(skb, I40E_MIN_TX_LEN))
2984 return NETDEV_TX_OK;
2985
2986 return i40e_xmit_frame_ring(skb, tx_ring);
2987}
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4#include <linux/prefetch.h>
5#include <linux/bpf_trace.h>
6#include <net/xdp.h>
7#include "i40e.h"
8#include "i40e_trace.h"
9#include "i40e_prototype.h"
10#include "i40e_txrx_common.h"
11#include "i40e_xsk.h"
12
13#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
14/**
15 * i40e_fdir - Generate a Flow Director descriptor based on fdata
16 * @tx_ring: Tx ring to send buffer on
17 * @fdata: Flow director filter data
18 * @add: Indicate if we are adding a rule or deleting one
19 *
20 **/
21static void i40e_fdir(struct i40e_ring *tx_ring,
22 struct i40e_fdir_filter *fdata, bool add)
23{
24 struct i40e_filter_program_desc *fdir_desc;
25 struct i40e_pf *pf = tx_ring->vsi->back;
26 u32 flex_ptype, dtype_cmd;
27 u16 i;
28
29 /* grab the next descriptor */
30 i = tx_ring->next_to_use;
31 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
32
33 i++;
34 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
35
36 flex_ptype = I40E_TXD_FLTR_QW0_QINDEX_MASK &
37 (fdata->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT);
38
39 flex_ptype |= I40E_TXD_FLTR_QW0_FLEXOFF_MASK &
40 (fdata->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT);
41
42 flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK &
43 (fdata->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
44
45 flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK &
46 (fdata->flex_offset << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT);
47
48 /* Use LAN VSI Id if not programmed by user */
49 flex_ptype |= I40E_TXD_FLTR_QW0_DEST_VSI_MASK &
50 ((u32)(fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id) <<
51 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT);
52
53 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
54
55 dtype_cmd |= add ?
56 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
57 I40E_TXD_FLTR_QW1_PCMD_SHIFT :
58 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
59 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
60
61 dtype_cmd |= I40E_TXD_FLTR_QW1_DEST_MASK &
62 (fdata->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT);
63
64 dtype_cmd |= I40E_TXD_FLTR_QW1_FD_STATUS_MASK &
65 (fdata->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT);
66
67 if (fdata->cnt_index) {
68 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
69 dtype_cmd |= I40E_TXD_FLTR_QW1_CNTINDEX_MASK &
70 ((u32)fdata->cnt_index <<
71 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT);
72 }
73
74 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
75 fdir_desc->rsvd = cpu_to_le32(0);
76 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
77 fdir_desc->fd_id = cpu_to_le32(fdata->fd_id);
78}
79
80#define I40E_FD_CLEAN_DELAY 10
81/**
82 * i40e_program_fdir_filter - Program a Flow Director filter
83 * @fdir_data: Packet data that will be filter parameters
84 * @raw_packet: the pre-allocated packet buffer for FDir
85 * @pf: The PF pointer
86 * @add: True for add/update, False for remove
87 **/
88static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data,
89 u8 *raw_packet, struct i40e_pf *pf,
90 bool add)
91{
92 struct i40e_tx_buffer *tx_buf, *first;
93 struct i40e_tx_desc *tx_desc;
94 struct i40e_ring *tx_ring;
95 struct i40e_vsi *vsi;
96 struct device *dev;
97 dma_addr_t dma;
98 u32 td_cmd = 0;
99 u16 i;
100
101 /* find existing FDIR VSI */
102 vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR);
103 if (!vsi)
104 return -ENOENT;
105
106 tx_ring = vsi->tx_rings[0];
107 dev = tx_ring->dev;
108
109 /* we need two descriptors to add/del a filter and we can wait */
110 for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) {
111 if (!i)
112 return -EAGAIN;
113 msleep_interruptible(1);
114 }
115
116 dma = dma_map_single(dev, raw_packet,
117 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
118 if (dma_mapping_error(dev, dma))
119 goto dma_fail;
120
121 /* grab the next descriptor */
122 i = tx_ring->next_to_use;
123 first = &tx_ring->tx_bi[i];
124 i40e_fdir(tx_ring, fdir_data, add);
125
126 /* Now program a dummy descriptor */
127 i = tx_ring->next_to_use;
128 tx_desc = I40E_TX_DESC(tx_ring, i);
129 tx_buf = &tx_ring->tx_bi[i];
130
131 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
132
133 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
134
135 /* record length, and DMA address */
136 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
137 dma_unmap_addr_set(tx_buf, dma, dma);
138
139 tx_desc->buffer_addr = cpu_to_le64(dma);
140 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
141
142 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
143 tx_buf->raw_buf = (void *)raw_packet;
144
145 tx_desc->cmd_type_offset_bsz =
146 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
147
148 /* Force memory writes to complete before letting h/w
149 * know there are new descriptors to fetch.
150 */
151 wmb();
152
153 /* Mark the data descriptor to be watched */
154 first->next_to_watch = tx_desc;
155
156 writel(tx_ring->next_to_use, tx_ring->tail);
157 return 0;
158
159dma_fail:
160 return -1;
161}
162
163#define IP_HEADER_OFFSET 14
164#define I40E_UDPIP_DUMMY_PACKET_LEN 42
165/**
166 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters
167 * @vsi: pointer to the targeted VSI
168 * @fd_data: the flow director data required for the FDir descriptor
169 * @add: true adds a filter, false removes it
170 *
171 * Returns 0 if the filters were successfully added or removed
172 **/
173static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi,
174 struct i40e_fdir_filter *fd_data,
175 bool add)
176{
177 struct i40e_pf *pf = vsi->back;
178 struct udphdr *udp;
179 struct iphdr *ip;
180 u8 *raw_packet;
181 int ret;
182 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
183 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0,
184 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
185
186 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
187 if (!raw_packet)
188 return -ENOMEM;
189 memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN);
190
191 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
192 udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET
193 + sizeof(struct iphdr));
194
195 ip->daddr = fd_data->dst_ip;
196 udp->dest = fd_data->dst_port;
197 ip->saddr = fd_data->src_ip;
198 udp->source = fd_data->src_port;
199
200 if (fd_data->flex_filter) {
201 u8 *payload = raw_packet + I40E_UDPIP_DUMMY_PACKET_LEN;
202 __be16 pattern = fd_data->flex_word;
203 u16 off = fd_data->flex_offset;
204
205 *((__force __be16 *)(payload + off)) = pattern;
206 }
207
208 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
209 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
210 if (ret) {
211 dev_info(&pf->pdev->dev,
212 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
213 fd_data->pctype, fd_data->fd_id, ret);
214 /* Free the packet buffer since it wasn't added to the ring */
215 kfree(raw_packet);
216 return -EOPNOTSUPP;
217 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
218 if (add)
219 dev_info(&pf->pdev->dev,
220 "Filter OK for PCTYPE %d loc = %d\n",
221 fd_data->pctype, fd_data->fd_id);
222 else
223 dev_info(&pf->pdev->dev,
224 "Filter deleted for PCTYPE %d loc = %d\n",
225 fd_data->pctype, fd_data->fd_id);
226 }
227
228 if (add)
229 pf->fd_udp4_filter_cnt++;
230 else
231 pf->fd_udp4_filter_cnt--;
232
233 return 0;
234}
235
236#define I40E_TCPIP_DUMMY_PACKET_LEN 54
237/**
238 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters
239 * @vsi: pointer to the targeted VSI
240 * @fd_data: the flow director data required for the FDir descriptor
241 * @add: true adds a filter, false removes it
242 *
243 * Returns 0 if the filters were successfully added or removed
244 **/
245static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
246 struct i40e_fdir_filter *fd_data,
247 bool add)
248{
249 struct i40e_pf *pf = vsi->back;
250 struct tcphdr *tcp;
251 struct iphdr *ip;
252 u8 *raw_packet;
253 int ret;
254 /* Dummy packet */
255 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
256 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0,
257 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11,
258 0x0, 0x72, 0, 0, 0, 0};
259
260 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
261 if (!raw_packet)
262 return -ENOMEM;
263 memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN);
264
265 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
266 tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET
267 + sizeof(struct iphdr));
268
269 ip->daddr = fd_data->dst_ip;
270 tcp->dest = fd_data->dst_port;
271 ip->saddr = fd_data->src_ip;
272 tcp->source = fd_data->src_port;
273
274 if (fd_data->flex_filter) {
275 u8 *payload = raw_packet + I40E_TCPIP_DUMMY_PACKET_LEN;
276 __be16 pattern = fd_data->flex_word;
277 u16 off = fd_data->flex_offset;
278
279 *((__force __be16 *)(payload + off)) = pattern;
280 }
281
282 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
283 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
284 if (ret) {
285 dev_info(&pf->pdev->dev,
286 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
287 fd_data->pctype, fd_data->fd_id, ret);
288 /* Free the packet buffer since it wasn't added to the ring */
289 kfree(raw_packet);
290 return -EOPNOTSUPP;
291 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
292 if (add)
293 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n",
294 fd_data->pctype, fd_data->fd_id);
295 else
296 dev_info(&pf->pdev->dev,
297 "Filter deleted for PCTYPE %d loc = %d\n",
298 fd_data->pctype, fd_data->fd_id);
299 }
300
301 if (add) {
302 pf->fd_tcp4_filter_cnt++;
303 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
304 I40E_DEBUG_FD & pf->hw.debug_mask)
305 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
306 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
307 } else {
308 pf->fd_tcp4_filter_cnt--;
309 }
310
311 return 0;
312}
313
314#define I40E_SCTPIP_DUMMY_PACKET_LEN 46
315/**
316 * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for
317 * a specific flow spec
318 * @vsi: pointer to the targeted VSI
319 * @fd_data: the flow director data required for the FDir descriptor
320 * @add: true adds a filter, false removes it
321 *
322 * Returns 0 if the filters were successfully added or removed
323 **/
324static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi,
325 struct i40e_fdir_filter *fd_data,
326 bool add)
327{
328 struct i40e_pf *pf = vsi->back;
329 struct sctphdr *sctp;
330 struct iphdr *ip;
331 u8 *raw_packet;
332 int ret;
333 /* Dummy packet */
334 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
335 0x45, 0, 0, 0x20, 0, 0, 0x40, 0, 0x40, 0x84, 0, 0, 0, 0, 0, 0,
336 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
337
338 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
339 if (!raw_packet)
340 return -ENOMEM;
341 memcpy(raw_packet, packet, I40E_SCTPIP_DUMMY_PACKET_LEN);
342
343 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
344 sctp = (struct sctphdr *)(raw_packet + IP_HEADER_OFFSET
345 + sizeof(struct iphdr));
346
347 ip->daddr = fd_data->dst_ip;
348 sctp->dest = fd_data->dst_port;
349 ip->saddr = fd_data->src_ip;
350 sctp->source = fd_data->src_port;
351
352 if (fd_data->flex_filter) {
353 u8 *payload = raw_packet + I40E_SCTPIP_DUMMY_PACKET_LEN;
354 __be16 pattern = fd_data->flex_word;
355 u16 off = fd_data->flex_offset;
356
357 *((__force __be16 *)(payload + off)) = pattern;
358 }
359
360 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
361 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
362 if (ret) {
363 dev_info(&pf->pdev->dev,
364 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
365 fd_data->pctype, fd_data->fd_id, ret);
366 /* Free the packet buffer since it wasn't added to the ring */
367 kfree(raw_packet);
368 return -EOPNOTSUPP;
369 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
370 if (add)
371 dev_info(&pf->pdev->dev,
372 "Filter OK for PCTYPE %d loc = %d\n",
373 fd_data->pctype, fd_data->fd_id);
374 else
375 dev_info(&pf->pdev->dev,
376 "Filter deleted for PCTYPE %d loc = %d\n",
377 fd_data->pctype, fd_data->fd_id);
378 }
379
380 if (add)
381 pf->fd_sctp4_filter_cnt++;
382 else
383 pf->fd_sctp4_filter_cnt--;
384
385 return 0;
386}
387
388#define I40E_IP_DUMMY_PACKET_LEN 34
389/**
390 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for
391 * a specific flow spec
392 * @vsi: pointer to the targeted VSI
393 * @fd_data: the flow director data required for the FDir descriptor
394 * @add: true adds a filter, false removes it
395 *
396 * Returns 0 if the filters were successfully added or removed
397 **/
398static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi,
399 struct i40e_fdir_filter *fd_data,
400 bool add)
401{
402 struct i40e_pf *pf = vsi->back;
403 struct iphdr *ip;
404 u8 *raw_packet;
405 int ret;
406 int i;
407 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
408 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0,
409 0, 0, 0, 0};
410
411 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
412 i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) {
413 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
414 if (!raw_packet)
415 return -ENOMEM;
416 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN);
417 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
418
419 ip->saddr = fd_data->src_ip;
420 ip->daddr = fd_data->dst_ip;
421 ip->protocol = 0;
422
423 if (fd_data->flex_filter) {
424 u8 *payload = raw_packet + I40E_IP_DUMMY_PACKET_LEN;
425 __be16 pattern = fd_data->flex_word;
426 u16 off = fd_data->flex_offset;
427
428 *((__force __be16 *)(payload + off)) = pattern;
429 }
430
431 fd_data->pctype = i;
432 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
433 if (ret) {
434 dev_info(&pf->pdev->dev,
435 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
436 fd_data->pctype, fd_data->fd_id, ret);
437 /* The packet buffer wasn't added to the ring so we
438 * need to free it now.
439 */
440 kfree(raw_packet);
441 return -EOPNOTSUPP;
442 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
443 if (add)
444 dev_info(&pf->pdev->dev,
445 "Filter OK for PCTYPE %d loc = %d\n",
446 fd_data->pctype, fd_data->fd_id);
447 else
448 dev_info(&pf->pdev->dev,
449 "Filter deleted for PCTYPE %d loc = %d\n",
450 fd_data->pctype, fd_data->fd_id);
451 }
452 }
453
454 if (add)
455 pf->fd_ip4_filter_cnt++;
456 else
457 pf->fd_ip4_filter_cnt--;
458
459 return 0;
460}
461
462/**
463 * i40e_add_del_fdir - Build raw packets to add/del fdir filter
464 * @vsi: pointer to the targeted VSI
465 * @input: filter to add or delete
466 * @add: true adds a filter, false removes it
467 *
468 **/
469int i40e_add_del_fdir(struct i40e_vsi *vsi,
470 struct i40e_fdir_filter *input, bool add)
471{
472 struct i40e_pf *pf = vsi->back;
473 int ret;
474
475 switch (input->flow_type & ~FLOW_EXT) {
476 case TCP_V4_FLOW:
477 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
478 break;
479 case UDP_V4_FLOW:
480 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
481 break;
482 case SCTP_V4_FLOW:
483 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
484 break;
485 case IP_USER_FLOW:
486 switch (input->ip4_proto) {
487 case IPPROTO_TCP:
488 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
489 break;
490 case IPPROTO_UDP:
491 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
492 break;
493 case IPPROTO_SCTP:
494 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
495 break;
496 case IPPROTO_IP:
497 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
498 break;
499 default:
500 /* We cannot support masking based on protocol */
501 dev_info(&pf->pdev->dev, "Unsupported IPv4 protocol 0x%02x\n",
502 input->ip4_proto);
503 return -EINVAL;
504 }
505 break;
506 default:
507 dev_info(&pf->pdev->dev, "Unsupported flow type 0x%02x\n",
508 input->flow_type);
509 return -EINVAL;
510 }
511
512 /* The buffer allocated here will be normally be freed by
513 * i40e_clean_fdir_tx_irq() as it reclaims resources after transmit
514 * completion. In the event of an error adding the buffer to the FDIR
515 * ring, it will immediately be freed. It may also be freed by
516 * i40e_clean_tx_ring() when closing the VSI.
517 */
518 return ret;
519}
520
521/**
522 * i40e_fd_handle_status - check the Programming Status for FD
523 * @rx_ring: the Rx ring for this descriptor
524 * @qword0_raw: qword0
525 * @qword1: qword1 after le_to_cpu
526 * @prog_id: the id originally used for programming
527 *
528 * This is used to verify if the FD programming or invalidation
529 * requested by SW to the HW is successful or not and take actions accordingly.
530 **/
531static void i40e_fd_handle_status(struct i40e_ring *rx_ring, u64 qword0_raw,
532 u64 qword1, u8 prog_id)
533{
534 struct i40e_pf *pf = rx_ring->vsi->back;
535 struct pci_dev *pdev = pf->pdev;
536 struct i40e_32b_rx_wb_qw0 *qw0;
537 u32 fcnt_prog, fcnt_avail;
538 u32 error;
539
540 qw0 = (struct i40e_32b_rx_wb_qw0 *)&qword0_raw;
541 error = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
542 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
543
544 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
545 pf->fd_inv = le32_to_cpu(qw0->hi_dword.fd_id);
546 if (qw0->hi_dword.fd_id != 0 ||
547 (I40E_DEBUG_FD & pf->hw.debug_mask))
548 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
549 pf->fd_inv);
550
551 /* Check if the programming error is for ATR.
552 * If so, auto disable ATR and set a state for
553 * flush in progress. Next time we come here if flush is in
554 * progress do nothing, once flush is complete the state will
555 * be cleared.
556 */
557 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
558 return;
559
560 pf->fd_add_err++;
561 /* store the current atr filter count */
562 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
563
564 if (qw0->hi_dword.fd_id == 0 &&
565 test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state)) {
566 /* These set_bit() calls aren't atomic with the
567 * test_bit() here, but worse case we potentially
568 * disable ATR and queue a flush right after SB
569 * support is re-enabled. That shouldn't cause an
570 * issue in practice
571 */
572 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
573 set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state);
574 }
575
576 /* filter programming failed most likely due to table full */
577 fcnt_prog = i40e_get_global_fd_count(pf);
578 fcnt_avail = pf->fdir_pf_filter_count;
579 /* If ATR is running fcnt_prog can quickly change,
580 * if we are very close to full, it makes sense to disable
581 * FD ATR/SB and then re-enable it when there is room.
582 */
583 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
584 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
585 !test_and_set_bit(__I40E_FD_SB_AUTO_DISABLED,
586 pf->state))
587 if (I40E_DEBUG_FD & pf->hw.debug_mask)
588 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
589 }
590 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
591 if (I40E_DEBUG_FD & pf->hw.debug_mask)
592 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
593 qw0->hi_dword.fd_id);
594 }
595}
596
597/**
598 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
599 * @ring: the ring that owns the buffer
600 * @tx_buffer: the buffer to free
601 **/
602static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
603 struct i40e_tx_buffer *tx_buffer)
604{
605 if (tx_buffer->skb) {
606 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
607 kfree(tx_buffer->raw_buf);
608 else if (ring_is_xdp(ring))
609 xdp_return_frame(tx_buffer->xdpf);
610 else
611 dev_kfree_skb_any(tx_buffer->skb);
612 if (dma_unmap_len(tx_buffer, len))
613 dma_unmap_single(ring->dev,
614 dma_unmap_addr(tx_buffer, dma),
615 dma_unmap_len(tx_buffer, len),
616 DMA_TO_DEVICE);
617 } else if (dma_unmap_len(tx_buffer, len)) {
618 dma_unmap_page(ring->dev,
619 dma_unmap_addr(tx_buffer, dma),
620 dma_unmap_len(tx_buffer, len),
621 DMA_TO_DEVICE);
622 }
623
624 tx_buffer->next_to_watch = NULL;
625 tx_buffer->skb = NULL;
626 dma_unmap_len_set(tx_buffer, len, 0);
627 /* tx_buffer must be completely set up in the transmit path */
628}
629
630/**
631 * i40e_clean_tx_ring - Free any empty Tx buffers
632 * @tx_ring: ring to be cleaned
633 **/
634void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
635{
636 unsigned long bi_size;
637 u16 i;
638
639 if (ring_is_xdp(tx_ring) && tx_ring->xsk_umem) {
640 i40e_xsk_clean_tx_ring(tx_ring);
641 } else {
642 /* ring already cleared, nothing to do */
643 if (!tx_ring->tx_bi)
644 return;
645
646 /* Free all the Tx ring sk_buffs */
647 for (i = 0; i < tx_ring->count; i++)
648 i40e_unmap_and_free_tx_resource(tx_ring,
649 &tx_ring->tx_bi[i]);
650 }
651
652 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
653 memset(tx_ring->tx_bi, 0, bi_size);
654
655 /* Zero out the descriptor ring */
656 memset(tx_ring->desc, 0, tx_ring->size);
657
658 tx_ring->next_to_use = 0;
659 tx_ring->next_to_clean = 0;
660
661 if (!tx_ring->netdev)
662 return;
663
664 /* cleanup Tx queue statistics */
665 netdev_tx_reset_queue(txring_txq(tx_ring));
666}
667
668/**
669 * i40e_free_tx_resources - Free Tx resources per queue
670 * @tx_ring: Tx descriptor ring for a specific queue
671 *
672 * Free all transmit software resources
673 **/
674void i40e_free_tx_resources(struct i40e_ring *tx_ring)
675{
676 i40e_clean_tx_ring(tx_ring);
677 kfree(tx_ring->tx_bi);
678 tx_ring->tx_bi = NULL;
679
680 if (tx_ring->desc) {
681 dma_free_coherent(tx_ring->dev, tx_ring->size,
682 tx_ring->desc, tx_ring->dma);
683 tx_ring->desc = NULL;
684 }
685}
686
687/**
688 * i40e_get_tx_pending - how many tx descriptors not processed
689 * @ring: the ring of descriptors
690 * @in_sw: use SW variables
691 *
692 * Since there is no access to the ring head register
693 * in XL710, we need to use our local copies
694 **/
695u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw)
696{
697 u32 head, tail;
698
699 if (!in_sw) {
700 head = i40e_get_head(ring);
701 tail = readl(ring->tail);
702 } else {
703 head = ring->next_to_clean;
704 tail = ring->next_to_use;
705 }
706
707 if (head != tail)
708 return (head < tail) ?
709 tail - head : (tail + ring->count - head);
710
711 return 0;
712}
713
714/**
715 * i40e_detect_recover_hung - Function to detect and recover hung_queues
716 * @vsi: pointer to vsi struct with tx queues
717 *
718 * VSI has netdev and netdev has TX queues. This function is to check each of
719 * those TX queues if they are hung, trigger recovery by issuing SW interrupt.
720 **/
721void i40e_detect_recover_hung(struct i40e_vsi *vsi)
722{
723 struct i40e_ring *tx_ring = NULL;
724 struct net_device *netdev;
725 unsigned int i;
726 int packets;
727
728 if (!vsi)
729 return;
730
731 if (test_bit(__I40E_VSI_DOWN, vsi->state))
732 return;
733
734 netdev = vsi->netdev;
735 if (!netdev)
736 return;
737
738 if (!netif_carrier_ok(netdev))
739 return;
740
741 for (i = 0; i < vsi->num_queue_pairs; i++) {
742 tx_ring = vsi->tx_rings[i];
743 if (tx_ring && tx_ring->desc) {
744 /* If packet counter has not changed the queue is
745 * likely stalled, so force an interrupt for this
746 * queue.
747 *
748 * prev_pkt_ctr would be negative if there was no
749 * pending work.
750 */
751 packets = tx_ring->stats.packets & INT_MAX;
752 if (tx_ring->tx_stats.prev_pkt_ctr == packets) {
753 i40e_force_wb(vsi, tx_ring->q_vector);
754 continue;
755 }
756
757 /* Memory barrier between read of packet count and call
758 * to i40e_get_tx_pending()
759 */
760 smp_rmb();
761 tx_ring->tx_stats.prev_pkt_ctr =
762 i40e_get_tx_pending(tx_ring, true) ? packets : -1;
763 }
764 }
765}
766
767/**
768 * i40e_clean_tx_irq - Reclaim resources after transmit completes
769 * @vsi: the VSI we care about
770 * @tx_ring: Tx ring to clean
771 * @napi_budget: Used to determine if we are in netpoll
772 *
773 * Returns true if there's any budget left (e.g. the clean is finished)
774 **/
775static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
776 struct i40e_ring *tx_ring, int napi_budget)
777{
778 int i = tx_ring->next_to_clean;
779 struct i40e_tx_buffer *tx_buf;
780 struct i40e_tx_desc *tx_head;
781 struct i40e_tx_desc *tx_desc;
782 unsigned int total_bytes = 0, total_packets = 0;
783 unsigned int budget = vsi->work_limit;
784
785 tx_buf = &tx_ring->tx_bi[i];
786 tx_desc = I40E_TX_DESC(tx_ring, i);
787 i -= tx_ring->count;
788
789 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
790
791 do {
792 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
793
794 /* if next_to_watch is not set then there is no work pending */
795 if (!eop_desc)
796 break;
797
798 /* prevent any other reads prior to eop_desc */
799 smp_rmb();
800
801 i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf);
802 /* we have caught up to head, no work left to do */
803 if (tx_head == tx_desc)
804 break;
805
806 /* clear next_to_watch to prevent false hangs */
807 tx_buf->next_to_watch = NULL;
808
809 /* update the statistics for this packet */
810 total_bytes += tx_buf->bytecount;
811 total_packets += tx_buf->gso_segs;
812
813 /* free the skb/XDP data */
814 if (ring_is_xdp(tx_ring))
815 xdp_return_frame(tx_buf->xdpf);
816 else
817 napi_consume_skb(tx_buf->skb, napi_budget);
818
819 /* unmap skb header data */
820 dma_unmap_single(tx_ring->dev,
821 dma_unmap_addr(tx_buf, dma),
822 dma_unmap_len(tx_buf, len),
823 DMA_TO_DEVICE);
824
825 /* clear tx_buffer data */
826 tx_buf->skb = NULL;
827 dma_unmap_len_set(tx_buf, len, 0);
828
829 /* unmap remaining buffers */
830 while (tx_desc != eop_desc) {
831 i40e_trace(clean_tx_irq_unmap,
832 tx_ring, tx_desc, tx_buf);
833
834 tx_buf++;
835 tx_desc++;
836 i++;
837 if (unlikely(!i)) {
838 i -= tx_ring->count;
839 tx_buf = tx_ring->tx_bi;
840 tx_desc = I40E_TX_DESC(tx_ring, 0);
841 }
842
843 /* unmap any remaining paged data */
844 if (dma_unmap_len(tx_buf, len)) {
845 dma_unmap_page(tx_ring->dev,
846 dma_unmap_addr(tx_buf, dma),
847 dma_unmap_len(tx_buf, len),
848 DMA_TO_DEVICE);
849 dma_unmap_len_set(tx_buf, len, 0);
850 }
851 }
852
853 /* move us one more past the eop_desc for start of next pkt */
854 tx_buf++;
855 tx_desc++;
856 i++;
857 if (unlikely(!i)) {
858 i -= tx_ring->count;
859 tx_buf = tx_ring->tx_bi;
860 tx_desc = I40E_TX_DESC(tx_ring, 0);
861 }
862
863 prefetch(tx_desc);
864
865 /* update budget accounting */
866 budget--;
867 } while (likely(budget));
868
869 i += tx_ring->count;
870 tx_ring->next_to_clean = i;
871 i40e_update_tx_stats(tx_ring, total_packets, total_bytes);
872 i40e_arm_wb(tx_ring, vsi, budget);
873
874 if (ring_is_xdp(tx_ring))
875 return !!budget;
876
877 /* notify netdev of completed buffers */
878 netdev_tx_completed_queue(txring_txq(tx_ring),
879 total_packets, total_bytes);
880
881#define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2))
882 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
883 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
884 /* Make sure that anybody stopping the queue after this
885 * sees the new next_to_clean.
886 */
887 smp_mb();
888 if (__netif_subqueue_stopped(tx_ring->netdev,
889 tx_ring->queue_index) &&
890 !test_bit(__I40E_VSI_DOWN, vsi->state)) {
891 netif_wake_subqueue(tx_ring->netdev,
892 tx_ring->queue_index);
893 ++tx_ring->tx_stats.restart_queue;
894 }
895 }
896
897 return !!budget;
898}
899
900/**
901 * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
902 * @vsi: the VSI we care about
903 * @q_vector: the vector on which to enable writeback
904 *
905 **/
906static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
907 struct i40e_q_vector *q_vector)
908{
909 u16 flags = q_vector->tx.ring[0].flags;
910 u32 val;
911
912 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
913 return;
914
915 if (q_vector->arm_wb_state)
916 return;
917
918 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
919 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK |
920 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */
921
922 wr32(&vsi->back->hw,
923 I40E_PFINT_DYN_CTLN(q_vector->reg_idx),
924 val);
925 } else {
926 val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK |
927 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */
928
929 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
930 }
931 q_vector->arm_wb_state = true;
932}
933
934/**
935 * i40e_force_wb - Issue SW Interrupt so HW does a wb
936 * @vsi: the VSI we care about
937 * @q_vector: the vector on which to force writeback
938 *
939 **/
940void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
941{
942 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
943 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
944 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
945 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
946 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
947 /* allow 00 to be written to the index */
948
949 wr32(&vsi->back->hw,
950 I40E_PFINT_DYN_CTLN(q_vector->reg_idx), val);
951 } else {
952 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
953 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
954 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
955 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK;
956 /* allow 00 to be written to the index */
957
958 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
959 }
960}
961
962static inline bool i40e_container_is_rx(struct i40e_q_vector *q_vector,
963 struct i40e_ring_container *rc)
964{
965 return &q_vector->rx == rc;
966}
967
968static inline unsigned int i40e_itr_divisor(struct i40e_q_vector *q_vector)
969{
970 unsigned int divisor;
971
972 switch (q_vector->vsi->back->hw.phy.link_info.link_speed) {
973 case I40E_LINK_SPEED_40GB:
974 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 1024;
975 break;
976 case I40E_LINK_SPEED_25GB:
977 case I40E_LINK_SPEED_20GB:
978 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 512;
979 break;
980 default:
981 case I40E_LINK_SPEED_10GB:
982 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 256;
983 break;
984 case I40E_LINK_SPEED_1GB:
985 case I40E_LINK_SPEED_100MB:
986 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 32;
987 break;
988 }
989
990 return divisor;
991}
992
993/**
994 * i40e_update_itr - update the dynamic ITR value based on statistics
995 * @q_vector: structure containing interrupt and ring information
996 * @rc: structure containing ring performance data
997 *
998 * Stores a new ITR value based on packets and byte
999 * counts during the last interrupt. The advantage of per interrupt
1000 * computation is faster updates and more accurate ITR for the current
1001 * traffic pattern. Constants in this function were computed
1002 * based on theoretical maximum wire speed and thresholds were set based
1003 * on testing data as well as attempting to minimize response time
1004 * while increasing bulk throughput.
1005 **/
1006static void i40e_update_itr(struct i40e_q_vector *q_vector,
1007 struct i40e_ring_container *rc)
1008{
1009 unsigned int avg_wire_size, packets, bytes, itr;
1010 unsigned long next_update = jiffies;
1011
1012 /* If we don't have any rings just leave ourselves set for maximum
1013 * possible latency so we take ourselves out of the equation.
1014 */
1015 if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting))
1016 return;
1017
1018 /* For Rx we want to push the delay up and default to low latency.
1019 * for Tx we want to pull the delay down and default to high latency.
1020 */
1021 itr = i40e_container_is_rx(q_vector, rc) ?
1022 I40E_ITR_ADAPTIVE_MIN_USECS | I40E_ITR_ADAPTIVE_LATENCY :
1023 I40E_ITR_ADAPTIVE_MAX_USECS | I40E_ITR_ADAPTIVE_LATENCY;
1024
1025 /* If we didn't update within up to 1 - 2 jiffies we can assume
1026 * that either packets are coming in so slow there hasn't been
1027 * any work, or that there is so much work that NAPI is dealing
1028 * with interrupt moderation and we don't need to do anything.
1029 */
1030 if (time_after(next_update, rc->next_update))
1031 goto clear_counts;
1032
1033 /* If itr_countdown is set it means we programmed an ITR within
1034 * the last 4 interrupt cycles. This has a side effect of us
1035 * potentially firing an early interrupt. In order to work around
1036 * this we need to throw out any data received for a few
1037 * interrupts following the update.
1038 */
1039 if (q_vector->itr_countdown) {
1040 itr = rc->target_itr;
1041 goto clear_counts;
1042 }
1043
1044 packets = rc->total_packets;
1045 bytes = rc->total_bytes;
1046
1047 if (i40e_container_is_rx(q_vector, rc)) {
1048 /* If Rx there are 1 to 4 packets and bytes are less than
1049 * 9000 assume insufficient data to use bulk rate limiting
1050 * approach unless Tx is already in bulk rate limiting. We
1051 * are likely latency driven.
1052 */
1053 if (packets && packets < 4 && bytes < 9000 &&
1054 (q_vector->tx.target_itr & I40E_ITR_ADAPTIVE_LATENCY)) {
1055 itr = I40E_ITR_ADAPTIVE_LATENCY;
1056 goto adjust_by_size;
1057 }
1058 } else if (packets < 4) {
1059 /* If we have Tx and Rx ITR maxed and Tx ITR is running in
1060 * bulk mode and we are receiving 4 or fewer packets just
1061 * reset the ITR_ADAPTIVE_LATENCY bit for latency mode so
1062 * that the Rx can relax.
1063 */
1064 if (rc->target_itr == I40E_ITR_ADAPTIVE_MAX_USECS &&
1065 (q_vector->rx.target_itr & I40E_ITR_MASK) ==
1066 I40E_ITR_ADAPTIVE_MAX_USECS)
1067 goto clear_counts;
1068 } else if (packets > 32) {
1069 /* If we have processed over 32 packets in a single interrupt
1070 * for Tx assume we need to switch over to "bulk" mode.
1071 */
1072 rc->target_itr &= ~I40E_ITR_ADAPTIVE_LATENCY;
1073 }
1074
1075 /* We have no packets to actually measure against. This means
1076 * either one of the other queues on this vector is active or
1077 * we are a Tx queue doing TSO with too high of an interrupt rate.
1078 *
1079 * Between 4 and 56 we can assume that our current interrupt delay
1080 * is only slightly too low. As such we should increase it by a small
1081 * fixed amount.
1082 */
1083 if (packets < 56) {
1084 itr = rc->target_itr + I40E_ITR_ADAPTIVE_MIN_INC;
1085 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) {
1086 itr &= I40E_ITR_ADAPTIVE_LATENCY;
1087 itr += I40E_ITR_ADAPTIVE_MAX_USECS;
1088 }
1089 goto clear_counts;
1090 }
1091
1092 if (packets <= 256) {
1093 itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr);
1094 itr &= I40E_ITR_MASK;
1095
1096 /* Between 56 and 112 is our "goldilocks" zone where we are
1097 * working out "just right". Just report that our current
1098 * ITR is good for us.
1099 */
1100 if (packets <= 112)
1101 goto clear_counts;
1102
1103 /* If packet count is 128 or greater we are likely looking
1104 * at a slight overrun of the delay we want. Try halving
1105 * our delay to see if that will cut the number of packets
1106 * in half per interrupt.
1107 */
1108 itr /= 2;
1109 itr &= I40E_ITR_MASK;
1110 if (itr < I40E_ITR_ADAPTIVE_MIN_USECS)
1111 itr = I40E_ITR_ADAPTIVE_MIN_USECS;
1112
1113 goto clear_counts;
1114 }
1115
1116 /* The paths below assume we are dealing with a bulk ITR since
1117 * number of packets is greater than 256. We are just going to have
1118 * to compute a value and try to bring the count under control,
1119 * though for smaller packet sizes there isn't much we can do as
1120 * NAPI polling will likely be kicking in sooner rather than later.
1121 */
1122 itr = I40E_ITR_ADAPTIVE_BULK;
1123
1124adjust_by_size:
1125 /* If packet counts are 256 or greater we can assume we have a gross
1126 * overestimation of what the rate should be. Instead of trying to fine
1127 * tune it just use the formula below to try and dial in an exact value
1128 * give the current packet size of the frame.
1129 */
1130 avg_wire_size = bytes / packets;
1131
1132 /* The following is a crude approximation of:
1133 * wmem_default / (size + overhead) = desired_pkts_per_int
1134 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
1135 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
1136 *
1137 * Assuming wmem_default is 212992 and overhead is 640 bytes per
1138 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
1139 * formula down to
1140 *
1141 * (170 * (size + 24)) / (size + 640) = ITR
1142 *
1143 * We first do some math on the packet size and then finally bitshift
1144 * by 8 after rounding up. We also have to account for PCIe link speed
1145 * difference as ITR scales based on this.
1146 */
1147 if (avg_wire_size <= 60) {
1148 /* Start at 250k ints/sec */
1149 avg_wire_size = 4096;
1150 } else if (avg_wire_size <= 380) {
1151 /* 250K ints/sec to 60K ints/sec */
1152 avg_wire_size *= 40;
1153 avg_wire_size += 1696;
1154 } else if (avg_wire_size <= 1084) {
1155 /* 60K ints/sec to 36K ints/sec */
1156 avg_wire_size *= 15;
1157 avg_wire_size += 11452;
1158 } else if (avg_wire_size <= 1980) {
1159 /* 36K ints/sec to 30K ints/sec */
1160 avg_wire_size *= 5;
1161 avg_wire_size += 22420;
1162 } else {
1163 /* plateau at a limit of 30K ints/sec */
1164 avg_wire_size = 32256;
1165 }
1166
1167 /* If we are in low latency mode halve our delay which doubles the
1168 * rate to somewhere between 100K to 16K ints/sec
1169 */
1170 if (itr & I40E_ITR_ADAPTIVE_LATENCY)
1171 avg_wire_size /= 2;
1172
1173 /* Resultant value is 256 times larger than it needs to be. This
1174 * gives us room to adjust the value as needed to either increase
1175 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
1176 *
1177 * Use addition as we have already recorded the new latency flag
1178 * for the ITR value.
1179 */
1180 itr += DIV_ROUND_UP(avg_wire_size, i40e_itr_divisor(q_vector)) *
1181 I40E_ITR_ADAPTIVE_MIN_INC;
1182
1183 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) {
1184 itr &= I40E_ITR_ADAPTIVE_LATENCY;
1185 itr += I40E_ITR_ADAPTIVE_MAX_USECS;
1186 }
1187
1188clear_counts:
1189 /* write back value */
1190 rc->target_itr = itr;
1191
1192 /* next update should occur within next jiffy */
1193 rc->next_update = next_update + 1;
1194
1195 rc->total_bytes = 0;
1196 rc->total_packets = 0;
1197}
1198
1199static struct i40e_rx_buffer *i40e_rx_bi(struct i40e_ring *rx_ring, u32 idx)
1200{
1201 return &rx_ring->rx_bi[idx];
1202}
1203
1204/**
1205 * i40e_reuse_rx_page - page flip buffer and store it back on the ring
1206 * @rx_ring: rx descriptor ring to store buffers on
1207 * @old_buff: donor buffer to have page reused
1208 *
1209 * Synchronizes page for reuse by the adapter
1210 **/
1211static void i40e_reuse_rx_page(struct i40e_ring *rx_ring,
1212 struct i40e_rx_buffer *old_buff)
1213{
1214 struct i40e_rx_buffer *new_buff;
1215 u16 nta = rx_ring->next_to_alloc;
1216
1217 new_buff = i40e_rx_bi(rx_ring, nta);
1218
1219 /* update, and store next to alloc */
1220 nta++;
1221 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1222
1223 /* transfer page from old buffer to new buffer */
1224 new_buff->dma = old_buff->dma;
1225 new_buff->page = old_buff->page;
1226 new_buff->page_offset = old_buff->page_offset;
1227 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
1228
1229 rx_ring->rx_stats.page_reuse_count++;
1230
1231 /* clear contents of buffer_info */
1232 old_buff->page = NULL;
1233}
1234
1235/**
1236 * i40e_clean_programming_status - clean the programming status descriptor
1237 * @rx_ring: the rx ring that has this descriptor
1238 * @qword0_raw: qword0
1239 * @qword1: qword1 representing status_error_len in CPU ordering
1240 *
1241 * Flow director should handle FD_FILTER_STATUS to check its filter programming
1242 * status being successful or not and take actions accordingly. FCoE should
1243 * handle its context/filter programming/invalidation status and take actions.
1244 *
1245 * Returns an i40e_rx_buffer to reuse if the cleanup occurred, otherwise NULL.
1246 **/
1247void i40e_clean_programming_status(struct i40e_ring *rx_ring, u64 qword0_raw,
1248 u64 qword1)
1249{
1250 u8 id;
1251
1252 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
1253 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
1254
1255 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
1256 i40e_fd_handle_status(rx_ring, qword0_raw, qword1, id);
1257}
1258
1259/**
1260 * i40e_setup_tx_descriptors - Allocate the Tx descriptors
1261 * @tx_ring: the tx ring to set up
1262 *
1263 * Return 0 on success, negative on error
1264 **/
1265int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
1266{
1267 struct device *dev = tx_ring->dev;
1268 int bi_size;
1269
1270 if (!dev)
1271 return -ENOMEM;
1272
1273 /* warn if we are about to overwrite the pointer */
1274 WARN_ON(tx_ring->tx_bi);
1275 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
1276 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
1277 if (!tx_ring->tx_bi)
1278 goto err;
1279
1280 u64_stats_init(&tx_ring->syncp);
1281
1282 /* round up to nearest 4K */
1283 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1284 /* add u32 for head writeback, align after this takes care of
1285 * guaranteeing this is at least one cache line in size
1286 */
1287 tx_ring->size += sizeof(u32);
1288 tx_ring->size = ALIGN(tx_ring->size, 4096);
1289 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1290 &tx_ring->dma, GFP_KERNEL);
1291 if (!tx_ring->desc) {
1292 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
1293 tx_ring->size);
1294 goto err;
1295 }
1296
1297 tx_ring->next_to_use = 0;
1298 tx_ring->next_to_clean = 0;
1299 tx_ring->tx_stats.prev_pkt_ctr = -1;
1300 return 0;
1301
1302err:
1303 kfree(tx_ring->tx_bi);
1304 tx_ring->tx_bi = NULL;
1305 return -ENOMEM;
1306}
1307
1308int i40e_alloc_rx_bi(struct i40e_ring *rx_ring)
1309{
1310 unsigned long sz = sizeof(*rx_ring->rx_bi) * rx_ring->count;
1311
1312 rx_ring->rx_bi = kzalloc(sz, GFP_KERNEL);
1313 return rx_ring->rx_bi ? 0 : -ENOMEM;
1314}
1315
1316static void i40e_clear_rx_bi(struct i40e_ring *rx_ring)
1317{
1318 memset(rx_ring->rx_bi, 0, sizeof(*rx_ring->rx_bi) * rx_ring->count);
1319}
1320
1321/**
1322 * i40e_clean_rx_ring - Free Rx buffers
1323 * @rx_ring: ring to be cleaned
1324 **/
1325void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
1326{
1327 u16 i;
1328
1329 /* ring already cleared, nothing to do */
1330 if (!rx_ring->rx_bi)
1331 return;
1332
1333 if (rx_ring->skb) {
1334 dev_kfree_skb(rx_ring->skb);
1335 rx_ring->skb = NULL;
1336 }
1337
1338 if (rx_ring->xsk_umem) {
1339 i40e_xsk_clean_rx_ring(rx_ring);
1340 goto skip_free;
1341 }
1342
1343 /* Free all the Rx ring sk_buffs */
1344 for (i = 0; i < rx_ring->count; i++) {
1345 struct i40e_rx_buffer *rx_bi = i40e_rx_bi(rx_ring, i);
1346
1347 if (!rx_bi->page)
1348 continue;
1349
1350 /* Invalidate cache lines that may have been written to by
1351 * device so that we avoid corrupting memory.
1352 */
1353 dma_sync_single_range_for_cpu(rx_ring->dev,
1354 rx_bi->dma,
1355 rx_bi->page_offset,
1356 rx_ring->rx_buf_len,
1357 DMA_FROM_DEVICE);
1358
1359 /* free resources associated with mapping */
1360 dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma,
1361 i40e_rx_pg_size(rx_ring),
1362 DMA_FROM_DEVICE,
1363 I40E_RX_DMA_ATTR);
1364
1365 __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias);
1366
1367 rx_bi->page = NULL;
1368 rx_bi->page_offset = 0;
1369 }
1370
1371skip_free:
1372 if (rx_ring->xsk_umem)
1373 i40e_clear_rx_bi_zc(rx_ring);
1374 else
1375 i40e_clear_rx_bi(rx_ring);
1376
1377 /* Zero out the descriptor ring */
1378 memset(rx_ring->desc, 0, rx_ring->size);
1379
1380 rx_ring->next_to_alloc = 0;
1381 rx_ring->next_to_clean = 0;
1382 rx_ring->next_to_use = 0;
1383}
1384
1385/**
1386 * i40e_free_rx_resources - Free Rx resources
1387 * @rx_ring: ring to clean the resources from
1388 *
1389 * Free all receive software resources
1390 **/
1391void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1392{
1393 i40e_clean_rx_ring(rx_ring);
1394 if (rx_ring->vsi->type == I40E_VSI_MAIN)
1395 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
1396 rx_ring->xdp_prog = NULL;
1397 kfree(rx_ring->rx_bi);
1398 rx_ring->rx_bi = NULL;
1399
1400 if (rx_ring->desc) {
1401 dma_free_coherent(rx_ring->dev, rx_ring->size,
1402 rx_ring->desc, rx_ring->dma);
1403 rx_ring->desc = NULL;
1404 }
1405}
1406
1407/**
1408 * i40e_setup_rx_descriptors - Allocate Rx descriptors
1409 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1410 *
1411 * Returns 0 on success, negative on failure
1412 **/
1413int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1414{
1415 struct device *dev = rx_ring->dev;
1416 int err;
1417
1418 u64_stats_init(&rx_ring->syncp);
1419
1420 /* Round up to nearest 4K */
1421 rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc);
1422 rx_ring->size = ALIGN(rx_ring->size, 4096);
1423 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1424 &rx_ring->dma, GFP_KERNEL);
1425
1426 if (!rx_ring->desc) {
1427 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1428 rx_ring->size);
1429 return -ENOMEM;
1430 }
1431
1432 rx_ring->next_to_alloc = 0;
1433 rx_ring->next_to_clean = 0;
1434 rx_ring->next_to_use = 0;
1435
1436 /* XDP RX-queue info only needed for RX rings exposed to XDP */
1437 if (rx_ring->vsi->type == I40E_VSI_MAIN) {
1438 err = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev,
1439 rx_ring->queue_index);
1440 if (err < 0)
1441 return err;
1442 }
1443
1444 rx_ring->xdp_prog = rx_ring->vsi->xdp_prog;
1445
1446 return 0;
1447}
1448
1449/**
1450 * i40e_release_rx_desc - Store the new tail and head values
1451 * @rx_ring: ring to bump
1452 * @val: new head index
1453 **/
1454void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1455{
1456 rx_ring->next_to_use = val;
1457
1458 /* update next to alloc since we have filled the ring */
1459 rx_ring->next_to_alloc = val;
1460
1461 /* Force memory writes to complete before letting h/w
1462 * know there are new descriptors to fetch. (Only
1463 * applicable for weak-ordered memory model archs,
1464 * such as IA-64).
1465 */
1466 wmb();
1467 writel(val, rx_ring->tail);
1468}
1469
1470/**
1471 * i40e_rx_offset - Return expected offset into page to access data
1472 * @rx_ring: Ring we are requesting offset of
1473 *
1474 * Returns the offset value for ring into the data buffer.
1475 */
1476static inline unsigned int i40e_rx_offset(struct i40e_ring *rx_ring)
1477{
1478 return ring_uses_build_skb(rx_ring) ? I40E_SKB_PAD : 0;
1479}
1480
1481static unsigned int i40e_rx_frame_truesize(struct i40e_ring *rx_ring,
1482 unsigned int size)
1483{
1484 unsigned int truesize;
1485
1486#if (PAGE_SIZE < 8192)
1487 truesize = i40e_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
1488#else
1489 truesize = i40e_rx_offset(rx_ring) ?
1490 SKB_DATA_ALIGN(size + i40e_rx_offset(rx_ring)) +
1491 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
1492 SKB_DATA_ALIGN(size);
1493#endif
1494 return truesize;
1495}
1496
1497/**
1498 * i40e_alloc_mapped_page - recycle or make a new page
1499 * @rx_ring: ring to use
1500 * @bi: rx_buffer struct to modify
1501 *
1502 * Returns true if the page was successfully allocated or
1503 * reused.
1504 **/
1505static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring,
1506 struct i40e_rx_buffer *bi)
1507{
1508 struct page *page = bi->page;
1509 dma_addr_t dma;
1510
1511 /* since we are recycling buffers we should seldom need to alloc */
1512 if (likely(page)) {
1513 rx_ring->rx_stats.page_reuse_count++;
1514 return true;
1515 }
1516
1517 /* alloc new page for storage */
1518 page = dev_alloc_pages(i40e_rx_pg_order(rx_ring));
1519 if (unlikely(!page)) {
1520 rx_ring->rx_stats.alloc_page_failed++;
1521 return false;
1522 }
1523
1524 /* map page for use */
1525 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1526 i40e_rx_pg_size(rx_ring),
1527 DMA_FROM_DEVICE,
1528 I40E_RX_DMA_ATTR);
1529
1530 /* if mapping failed free memory back to system since
1531 * there isn't much point in holding memory we can't use
1532 */
1533 if (dma_mapping_error(rx_ring->dev, dma)) {
1534 __free_pages(page, i40e_rx_pg_order(rx_ring));
1535 rx_ring->rx_stats.alloc_page_failed++;
1536 return false;
1537 }
1538
1539 bi->dma = dma;
1540 bi->page = page;
1541 bi->page_offset = i40e_rx_offset(rx_ring);
1542 page_ref_add(page, USHRT_MAX - 1);
1543 bi->pagecnt_bias = USHRT_MAX;
1544
1545 return true;
1546}
1547
1548/**
1549 * i40e_alloc_rx_buffers - Replace used receive buffers
1550 * @rx_ring: ring to place buffers on
1551 * @cleaned_count: number of buffers to replace
1552 *
1553 * Returns false if all allocations were successful, true if any fail
1554 **/
1555bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
1556{
1557 u16 ntu = rx_ring->next_to_use;
1558 union i40e_rx_desc *rx_desc;
1559 struct i40e_rx_buffer *bi;
1560
1561 /* do nothing if no valid netdev defined */
1562 if (!rx_ring->netdev || !cleaned_count)
1563 return false;
1564
1565 rx_desc = I40E_RX_DESC(rx_ring, ntu);
1566 bi = i40e_rx_bi(rx_ring, ntu);
1567
1568 do {
1569 if (!i40e_alloc_mapped_page(rx_ring, bi))
1570 goto no_buffers;
1571
1572 /* sync the buffer for use by the device */
1573 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1574 bi->page_offset,
1575 rx_ring->rx_buf_len,
1576 DMA_FROM_DEVICE);
1577
1578 /* Refresh the desc even if buffer_addrs didn't change
1579 * because each write-back erases this info.
1580 */
1581 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1582
1583 rx_desc++;
1584 bi++;
1585 ntu++;
1586 if (unlikely(ntu == rx_ring->count)) {
1587 rx_desc = I40E_RX_DESC(rx_ring, 0);
1588 bi = i40e_rx_bi(rx_ring, 0);
1589 ntu = 0;
1590 }
1591
1592 /* clear the status bits for the next_to_use descriptor */
1593 rx_desc->wb.qword1.status_error_len = 0;
1594
1595 cleaned_count--;
1596 } while (cleaned_count);
1597
1598 if (rx_ring->next_to_use != ntu)
1599 i40e_release_rx_desc(rx_ring, ntu);
1600
1601 return false;
1602
1603no_buffers:
1604 if (rx_ring->next_to_use != ntu)
1605 i40e_release_rx_desc(rx_ring, ntu);
1606
1607 /* make sure to come back via polling to try again after
1608 * allocation failure
1609 */
1610 return true;
1611}
1612
1613/**
1614 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1615 * @vsi: the VSI we care about
1616 * @skb: skb currently being received and modified
1617 * @rx_desc: the receive descriptor
1618 **/
1619static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1620 struct sk_buff *skb,
1621 union i40e_rx_desc *rx_desc)
1622{
1623 struct i40e_rx_ptype_decoded decoded;
1624 u32 rx_error, rx_status;
1625 bool ipv4, ipv6;
1626 u8 ptype;
1627 u64 qword;
1628
1629 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1630 ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT;
1631 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1632 I40E_RXD_QW1_ERROR_SHIFT;
1633 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1634 I40E_RXD_QW1_STATUS_SHIFT;
1635 decoded = decode_rx_desc_ptype(ptype);
1636
1637 skb->ip_summed = CHECKSUM_NONE;
1638
1639 skb_checksum_none_assert(skb);
1640
1641 /* Rx csum enabled and ip headers found? */
1642 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
1643 return;
1644
1645 /* did the hardware decode the packet and checksum? */
1646 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
1647 return;
1648
1649 /* both known and outer_ip must be set for the below code to work */
1650 if (!(decoded.known && decoded.outer_ip))
1651 return;
1652
1653 ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1654 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4);
1655 ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1656 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6);
1657
1658 if (ipv4 &&
1659 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
1660 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
1661 goto checksum_fail;
1662
1663 /* likely incorrect csum if alternate IP extension headers found */
1664 if (ipv6 &&
1665 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
1666 /* don't increment checksum err here, non-fatal err */
1667 return;
1668
1669 /* there was some L4 error, count error and punt packet to the stack */
1670 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
1671 goto checksum_fail;
1672
1673 /* handle packets that were not able to be checksummed due
1674 * to arrival speed, in this case the stack can compute
1675 * the csum.
1676 */
1677 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
1678 return;
1679
1680 /* If there is an outer header present that might contain a checksum
1681 * we need to bump the checksum level by 1 to reflect the fact that
1682 * we are indicating we validated the inner checksum.
1683 */
1684 if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT)
1685 skb->csum_level = 1;
1686
1687 /* Only report checksum unnecessary for TCP, UDP, or SCTP */
1688 switch (decoded.inner_prot) {
1689 case I40E_RX_PTYPE_INNER_PROT_TCP:
1690 case I40E_RX_PTYPE_INNER_PROT_UDP:
1691 case I40E_RX_PTYPE_INNER_PROT_SCTP:
1692 skb->ip_summed = CHECKSUM_UNNECESSARY;
1693 fallthrough;
1694 default:
1695 break;
1696 }
1697
1698 return;
1699
1700checksum_fail:
1701 vsi->back->hw_csum_rx_error++;
1702}
1703
1704/**
1705 * i40e_ptype_to_htype - get a hash type
1706 * @ptype: the ptype value from the descriptor
1707 *
1708 * Returns a hash type to be used by skb_set_hash
1709 **/
1710static inline int i40e_ptype_to_htype(u8 ptype)
1711{
1712 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1713
1714 if (!decoded.known)
1715 return PKT_HASH_TYPE_NONE;
1716
1717 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1718 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1719 return PKT_HASH_TYPE_L4;
1720 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1721 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1722 return PKT_HASH_TYPE_L3;
1723 else
1724 return PKT_HASH_TYPE_L2;
1725}
1726
1727/**
1728 * i40e_rx_hash - set the hash value in the skb
1729 * @ring: descriptor ring
1730 * @rx_desc: specific descriptor
1731 * @skb: skb currently being received and modified
1732 * @rx_ptype: Rx packet type
1733 **/
1734static inline void i40e_rx_hash(struct i40e_ring *ring,
1735 union i40e_rx_desc *rx_desc,
1736 struct sk_buff *skb,
1737 u8 rx_ptype)
1738{
1739 u32 hash;
1740 const __le64 rss_mask =
1741 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1742 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1743
1744 if (!(ring->netdev->features & NETIF_F_RXHASH))
1745 return;
1746
1747 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
1748 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1749 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
1750 }
1751}
1752
1753/**
1754 * i40e_process_skb_fields - Populate skb header fields from Rx descriptor
1755 * @rx_ring: rx descriptor ring packet is being transacted on
1756 * @rx_desc: pointer to the EOP Rx descriptor
1757 * @skb: pointer to current skb being populated
1758 * @rx_ptype: the packet type decoded by hardware
1759 *
1760 * This function checks the ring, descriptor, and packet information in
1761 * order to populate the hash, checksum, VLAN, protocol, and
1762 * other fields within the skb.
1763 **/
1764void i40e_process_skb_fields(struct i40e_ring *rx_ring,
1765 union i40e_rx_desc *rx_desc, struct sk_buff *skb)
1766{
1767 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1768 u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1769 I40E_RXD_QW1_STATUS_SHIFT;
1770 u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK;
1771 u32 tsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1772 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT;
1773 u8 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1774 I40E_RXD_QW1_PTYPE_SHIFT;
1775
1776 if (unlikely(tsynvalid))
1777 i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn);
1778
1779 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1780
1781 i40e_rx_checksum(rx_ring->vsi, skb, rx_desc);
1782
1783 skb_record_rx_queue(skb, rx_ring->queue_index);
1784
1785 if (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1786 u16 vlan_tag = rx_desc->wb.qword0.lo_dword.l2tag1;
1787
1788 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1789 le16_to_cpu(vlan_tag));
1790 }
1791
1792 /* modifies the skb - consumes the enet header */
1793 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1794}
1795
1796/**
1797 * i40e_cleanup_headers - Correct empty headers
1798 * @rx_ring: rx descriptor ring packet is being transacted on
1799 * @skb: pointer to current skb being fixed
1800 * @rx_desc: pointer to the EOP Rx descriptor
1801 *
1802 * Also address the case where we are pulling data in on pages only
1803 * and as such no data is present in the skb header.
1804 *
1805 * In addition if skb is not at least 60 bytes we need to pad it so that
1806 * it is large enough to qualify as a valid Ethernet frame.
1807 *
1808 * Returns true if an error was encountered and skb was freed.
1809 **/
1810static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb,
1811 union i40e_rx_desc *rx_desc)
1812
1813{
1814 /* XDP packets use error pointer so abort at this point */
1815 if (IS_ERR(skb))
1816 return true;
1817
1818 /* ERR_MASK will only have valid bits if EOP set, and
1819 * what we are doing here is actually checking
1820 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in
1821 * the error field
1822 */
1823 if (unlikely(i40e_test_staterr(rx_desc,
1824 BIT(I40E_RXD_QW1_ERROR_SHIFT)))) {
1825 dev_kfree_skb_any(skb);
1826 return true;
1827 }
1828
1829 /* if eth_skb_pad returns an error the skb was freed */
1830 if (eth_skb_pad(skb))
1831 return true;
1832
1833 return false;
1834}
1835
1836/**
1837 * i40e_page_is_reusable - check if any reuse is possible
1838 * @page: page struct to check
1839 *
1840 * A page is not reusable if it was allocated under low memory
1841 * conditions, or it's not in the same NUMA node as this CPU.
1842 */
1843static inline bool i40e_page_is_reusable(struct page *page)
1844{
1845 return (page_to_nid(page) == numa_mem_id()) &&
1846 !page_is_pfmemalloc(page);
1847}
1848
1849/**
1850 * i40e_can_reuse_rx_page - Determine if this page can be reused by
1851 * the adapter for another receive
1852 *
1853 * @rx_buffer: buffer containing the page
1854 *
1855 * If page is reusable, rx_buffer->page_offset is adjusted to point to
1856 * an unused region in the page.
1857 *
1858 * For small pages, @truesize will be a constant value, half the size
1859 * of the memory at page. We'll attempt to alternate between high and
1860 * low halves of the page, with one half ready for use by the hardware
1861 * and the other half being consumed by the stack. We use the page
1862 * ref count to determine whether the stack has finished consuming the
1863 * portion of this page that was passed up with a previous packet. If
1864 * the page ref count is >1, we'll assume the "other" half page is
1865 * still busy, and this page cannot be reused.
1866 *
1867 * For larger pages, @truesize will be the actual space used by the
1868 * received packet (adjusted upward to an even multiple of the cache
1869 * line size). This will advance through the page by the amount
1870 * actually consumed by the received packets while there is still
1871 * space for a buffer. Each region of larger pages will be used at
1872 * most once, after which the page will not be reused.
1873 *
1874 * In either case, if the page is reusable its refcount is increased.
1875 **/
1876static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer)
1877{
1878 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1879 struct page *page = rx_buffer->page;
1880
1881 /* Is any reuse possible? */
1882 if (unlikely(!i40e_page_is_reusable(page)))
1883 return false;
1884
1885#if (PAGE_SIZE < 8192)
1886 /* if we are only owner of page we can reuse it */
1887 if (unlikely((page_count(page) - pagecnt_bias) > 1))
1888 return false;
1889#else
1890#define I40E_LAST_OFFSET \
1891 (SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048)
1892 if (rx_buffer->page_offset > I40E_LAST_OFFSET)
1893 return false;
1894#endif
1895
1896 /* If we have drained the page fragment pool we need to update
1897 * the pagecnt_bias and page count so that we fully restock the
1898 * number of references the driver holds.
1899 */
1900 if (unlikely(pagecnt_bias == 1)) {
1901 page_ref_add(page, USHRT_MAX - 1);
1902 rx_buffer->pagecnt_bias = USHRT_MAX;
1903 }
1904
1905 return true;
1906}
1907
1908/**
1909 * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff
1910 * @rx_ring: rx descriptor ring to transact packets on
1911 * @rx_buffer: buffer containing page to add
1912 * @skb: sk_buff to place the data into
1913 * @size: packet length from rx_desc
1914 *
1915 * This function will add the data contained in rx_buffer->page to the skb.
1916 * It will just attach the page as a frag to the skb.
1917 *
1918 * The function will then update the page offset.
1919 **/
1920static void i40e_add_rx_frag(struct i40e_ring *rx_ring,
1921 struct i40e_rx_buffer *rx_buffer,
1922 struct sk_buff *skb,
1923 unsigned int size)
1924{
1925#if (PAGE_SIZE < 8192)
1926 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
1927#else
1928 unsigned int truesize = SKB_DATA_ALIGN(size + i40e_rx_offset(rx_ring));
1929#endif
1930
1931 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
1932 rx_buffer->page_offset, size, truesize);
1933
1934 /* page is being used so we must update the page offset */
1935#if (PAGE_SIZE < 8192)
1936 rx_buffer->page_offset ^= truesize;
1937#else
1938 rx_buffer->page_offset += truesize;
1939#endif
1940}
1941
1942/**
1943 * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use
1944 * @rx_ring: rx descriptor ring to transact packets on
1945 * @size: size of buffer to add to skb
1946 *
1947 * This function will pull an Rx buffer from the ring and synchronize it
1948 * for use by the CPU.
1949 */
1950static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring,
1951 const unsigned int size)
1952{
1953 struct i40e_rx_buffer *rx_buffer;
1954
1955 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean);
1956 prefetchw(rx_buffer->page);
1957
1958 /* we are reusing so sync this buffer for CPU use */
1959 dma_sync_single_range_for_cpu(rx_ring->dev,
1960 rx_buffer->dma,
1961 rx_buffer->page_offset,
1962 size,
1963 DMA_FROM_DEVICE);
1964
1965 /* We have pulled a buffer for use, so decrement pagecnt_bias */
1966 rx_buffer->pagecnt_bias--;
1967
1968 return rx_buffer;
1969}
1970
1971/**
1972 * i40e_construct_skb - Allocate skb and populate it
1973 * @rx_ring: rx descriptor ring to transact packets on
1974 * @rx_buffer: rx buffer to pull data from
1975 * @xdp: xdp_buff pointing to the data
1976 *
1977 * This function allocates an skb. It then populates it with the page
1978 * data from the current receive descriptor, taking care to set up the
1979 * skb correctly.
1980 */
1981static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring,
1982 struct i40e_rx_buffer *rx_buffer,
1983 struct xdp_buff *xdp)
1984{
1985 unsigned int size = xdp->data_end - xdp->data;
1986#if (PAGE_SIZE < 8192)
1987 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
1988#else
1989 unsigned int truesize = SKB_DATA_ALIGN(size);
1990#endif
1991 unsigned int headlen;
1992 struct sk_buff *skb;
1993
1994 /* prefetch first cache line of first page */
1995 prefetch(xdp->data);
1996#if L1_CACHE_BYTES < 128
1997 prefetch(xdp->data + L1_CACHE_BYTES);
1998#endif
1999 /* Note, we get here by enabling legacy-rx via:
2000 *
2001 * ethtool --set-priv-flags <dev> legacy-rx on
2002 *
2003 * In this mode, we currently get 0 extra XDP headroom as
2004 * opposed to having legacy-rx off, where we process XDP
2005 * packets going to stack via i40e_build_skb(). The latter
2006 * provides us currently with 192 bytes of headroom.
2007 *
2008 * For i40e_construct_skb() mode it means that the
2009 * xdp->data_meta will always point to xdp->data, since
2010 * the helper cannot expand the head. Should this ever
2011 * change in future for legacy-rx mode on, then lets also
2012 * add xdp->data_meta handling here.
2013 */
2014
2015 /* allocate a skb to store the frags */
2016 skb = __napi_alloc_skb(&rx_ring->q_vector->napi,
2017 I40E_RX_HDR_SIZE,
2018 GFP_ATOMIC | __GFP_NOWARN);
2019 if (unlikely(!skb))
2020 return NULL;
2021
2022 /* Determine available headroom for copy */
2023 headlen = size;
2024 if (headlen > I40E_RX_HDR_SIZE)
2025 headlen = eth_get_headlen(skb->dev, xdp->data,
2026 I40E_RX_HDR_SIZE);
2027
2028 /* align pull length to size of long to optimize memcpy performance */
2029 memcpy(__skb_put(skb, headlen), xdp->data,
2030 ALIGN(headlen, sizeof(long)));
2031
2032 /* update all of the pointers */
2033 size -= headlen;
2034 if (size) {
2035 skb_add_rx_frag(skb, 0, rx_buffer->page,
2036 rx_buffer->page_offset + headlen,
2037 size, truesize);
2038
2039 /* buffer is used by skb, update page_offset */
2040#if (PAGE_SIZE < 8192)
2041 rx_buffer->page_offset ^= truesize;
2042#else
2043 rx_buffer->page_offset += truesize;
2044#endif
2045 } else {
2046 /* buffer is unused, reset bias back to rx_buffer */
2047 rx_buffer->pagecnt_bias++;
2048 }
2049
2050 return skb;
2051}
2052
2053/**
2054 * i40e_build_skb - Build skb around an existing buffer
2055 * @rx_ring: Rx descriptor ring to transact packets on
2056 * @rx_buffer: Rx buffer to pull data from
2057 * @xdp: xdp_buff pointing to the data
2058 *
2059 * This function builds an skb around an existing Rx buffer, taking care
2060 * to set up the skb correctly and avoid any memcpy overhead.
2061 */
2062static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring,
2063 struct i40e_rx_buffer *rx_buffer,
2064 struct xdp_buff *xdp)
2065{
2066 unsigned int metasize = xdp->data - xdp->data_meta;
2067#if (PAGE_SIZE < 8192)
2068 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
2069#else
2070 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
2071 SKB_DATA_ALIGN(xdp->data_end -
2072 xdp->data_hard_start);
2073#endif
2074 struct sk_buff *skb;
2075
2076 /* Prefetch first cache line of first page. If xdp->data_meta
2077 * is unused, this points exactly as xdp->data, otherwise we
2078 * likely have a consumer accessing first few bytes of meta
2079 * data, and then actual data.
2080 */
2081 prefetch(xdp->data_meta);
2082#if L1_CACHE_BYTES < 128
2083 prefetch(xdp->data_meta + L1_CACHE_BYTES);
2084#endif
2085 /* build an skb around the page buffer */
2086 skb = build_skb(xdp->data_hard_start, truesize);
2087 if (unlikely(!skb))
2088 return NULL;
2089
2090 /* update pointers within the skb to store the data */
2091 skb_reserve(skb, xdp->data - xdp->data_hard_start);
2092 __skb_put(skb, xdp->data_end - xdp->data);
2093 if (metasize)
2094 skb_metadata_set(skb, metasize);
2095
2096 /* buffer is used by skb, update page_offset */
2097#if (PAGE_SIZE < 8192)
2098 rx_buffer->page_offset ^= truesize;
2099#else
2100 rx_buffer->page_offset += truesize;
2101#endif
2102
2103 return skb;
2104}
2105
2106/**
2107 * i40e_put_rx_buffer - Clean up used buffer and either recycle or free
2108 * @rx_ring: rx descriptor ring to transact packets on
2109 * @rx_buffer: rx buffer to pull data from
2110 *
2111 * This function will clean up the contents of the rx_buffer. It will
2112 * either recycle the buffer or unmap it and free the associated resources.
2113 */
2114static void i40e_put_rx_buffer(struct i40e_ring *rx_ring,
2115 struct i40e_rx_buffer *rx_buffer)
2116{
2117 if (i40e_can_reuse_rx_page(rx_buffer)) {
2118 /* hand second half of page back to the ring */
2119 i40e_reuse_rx_page(rx_ring, rx_buffer);
2120 } else {
2121 /* we are not reusing the buffer so unmap it */
2122 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2123 i40e_rx_pg_size(rx_ring),
2124 DMA_FROM_DEVICE, I40E_RX_DMA_ATTR);
2125 __page_frag_cache_drain(rx_buffer->page,
2126 rx_buffer->pagecnt_bias);
2127 /* clear contents of buffer_info */
2128 rx_buffer->page = NULL;
2129 }
2130}
2131
2132/**
2133 * i40e_is_non_eop - process handling of non-EOP buffers
2134 * @rx_ring: Rx ring being processed
2135 * @rx_desc: Rx descriptor for current buffer
2136 * @skb: Current socket buffer containing buffer in progress
2137 *
2138 * This function updates next to clean. If the buffer is an EOP buffer
2139 * this function exits returning false, otherwise it will place the
2140 * sk_buff in the next buffer to be chained and return true indicating
2141 * that this is in fact a non-EOP buffer.
2142 **/
2143static bool i40e_is_non_eop(struct i40e_ring *rx_ring,
2144 union i40e_rx_desc *rx_desc,
2145 struct sk_buff *skb)
2146{
2147 u32 ntc = rx_ring->next_to_clean + 1;
2148
2149 /* fetch, update, and store next to clean */
2150 ntc = (ntc < rx_ring->count) ? ntc : 0;
2151 rx_ring->next_to_clean = ntc;
2152
2153 prefetch(I40E_RX_DESC(rx_ring, ntc));
2154
2155 /* if we are the last buffer then there is nothing else to do */
2156#define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)
2157 if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF)))
2158 return false;
2159
2160 rx_ring->rx_stats.non_eop_descs++;
2161
2162 return true;
2163}
2164
2165static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf,
2166 struct i40e_ring *xdp_ring);
2167
2168int i40e_xmit_xdp_tx_ring(struct xdp_buff *xdp, struct i40e_ring *xdp_ring)
2169{
2170 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2171
2172 if (unlikely(!xdpf))
2173 return I40E_XDP_CONSUMED;
2174
2175 return i40e_xmit_xdp_ring(xdpf, xdp_ring);
2176}
2177
2178/**
2179 * i40e_run_xdp - run an XDP program
2180 * @rx_ring: Rx ring being processed
2181 * @xdp: XDP buffer containing the frame
2182 **/
2183static struct sk_buff *i40e_run_xdp(struct i40e_ring *rx_ring,
2184 struct xdp_buff *xdp)
2185{
2186 int err, result = I40E_XDP_PASS;
2187 struct i40e_ring *xdp_ring;
2188 struct bpf_prog *xdp_prog;
2189 u32 act;
2190
2191 rcu_read_lock();
2192 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
2193
2194 if (!xdp_prog)
2195 goto xdp_out;
2196
2197 prefetchw(xdp->data_hard_start); /* xdp_frame write */
2198
2199 act = bpf_prog_run_xdp(xdp_prog, xdp);
2200 switch (act) {
2201 case XDP_PASS:
2202 break;
2203 case XDP_TX:
2204 xdp_ring = rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2205 result = i40e_xmit_xdp_tx_ring(xdp, xdp_ring);
2206 break;
2207 case XDP_REDIRECT:
2208 err = xdp_do_redirect(rx_ring->netdev, xdp, xdp_prog);
2209 result = !err ? I40E_XDP_REDIR : I40E_XDP_CONSUMED;
2210 break;
2211 default:
2212 bpf_warn_invalid_xdp_action(act);
2213 fallthrough;
2214 case XDP_ABORTED:
2215 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
2216 fallthrough; /* handle aborts by dropping packet */
2217 case XDP_DROP:
2218 result = I40E_XDP_CONSUMED;
2219 break;
2220 }
2221xdp_out:
2222 rcu_read_unlock();
2223 return ERR_PTR(-result);
2224}
2225
2226/**
2227 * i40e_rx_buffer_flip - adjusted rx_buffer to point to an unused region
2228 * @rx_ring: Rx ring
2229 * @rx_buffer: Rx buffer to adjust
2230 * @size: Size of adjustment
2231 **/
2232static void i40e_rx_buffer_flip(struct i40e_ring *rx_ring,
2233 struct i40e_rx_buffer *rx_buffer,
2234 unsigned int size)
2235{
2236 unsigned int truesize = i40e_rx_frame_truesize(rx_ring, size);
2237
2238#if (PAGE_SIZE < 8192)
2239 rx_buffer->page_offset ^= truesize;
2240#else
2241 rx_buffer->page_offset += truesize;
2242#endif
2243}
2244
2245/**
2246 * i40e_xdp_ring_update_tail - Updates the XDP Tx ring tail register
2247 * @xdp_ring: XDP Tx ring
2248 *
2249 * This function updates the XDP Tx ring tail register.
2250 **/
2251void i40e_xdp_ring_update_tail(struct i40e_ring *xdp_ring)
2252{
2253 /* Force memory writes to complete before letting h/w
2254 * know there are new descriptors to fetch.
2255 */
2256 wmb();
2257 writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail);
2258}
2259
2260/**
2261 * i40e_update_rx_stats - Update Rx ring statistics
2262 * @rx_ring: rx descriptor ring
2263 * @total_rx_bytes: number of bytes received
2264 * @total_rx_packets: number of packets received
2265 *
2266 * This function updates the Rx ring statistics.
2267 **/
2268void i40e_update_rx_stats(struct i40e_ring *rx_ring,
2269 unsigned int total_rx_bytes,
2270 unsigned int total_rx_packets)
2271{
2272 u64_stats_update_begin(&rx_ring->syncp);
2273 rx_ring->stats.packets += total_rx_packets;
2274 rx_ring->stats.bytes += total_rx_bytes;
2275 u64_stats_update_end(&rx_ring->syncp);
2276 rx_ring->q_vector->rx.total_packets += total_rx_packets;
2277 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
2278}
2279
2280/**
2281 * i40e_finalize_xdp_rx - Bump XDP Tx tail and/or flush redirect map
2282 * @rx_ring: Rx ring
2283 * @xdp_res: Result of the receive batch
2284 *
2285 * This function bumps XDP Tx tail and/or flush redirect map, and
2286 * should be called when a batch of packets has been processed in the
2287 * napi loop.
2288 **/
2289void i40e_finalize_xdp_rx(struct i40e_ring *rx_ring, unsigned int xdp_res)
2290{
2291 if (xdp_res & I40E_XDP_REDIR)
2292 xdp_do_flush_map();
2293
2294 if (xdp_res & I40E_XDP_TX) {
2295 struct i40e_ring *xdp_ring =
2296 rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2297
2298 i40e_xdp_ring_update_tail(xdp_ring);
2299 }
2300}
2301
2302/**
2303 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2304 * @rx_ring: rx descriptor ring to transact packets on
2305 * @budget: Total limit on number of packets to process
2306 *
2307 * This function provides a "bounce buffer" approach to Rx interrupt
2308 * processing. The advantage to this is that on systems that have
2309 * expensive overhead for IOMMU access this provides a means of avoiding
2310 * it by maintaining the mapping of the page to the system.
2311 *
2312 * Returns amount of work completed
2313 **/
2314static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
2315{
2316 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2317 struct sk_buff *skb = rx_ring->skb;
2318 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
2319 unsigned int xdp_xmit = 0;
2320 bool failure = false;
2321 struct xdp_buff xdp;
2322
2323#if (PAGE_SIZE < 8192)
2324 xdp.frame_sz = i40e_rx_frame_truesize(rx_ring, 0);
2325#endif
2326 xdp.rxq = &rx_ring->xdp_rxq;
2327
2328 while (likely(total_rx_packets < (unsigned int)budget)) {
2329 struct i40e_rx_buffer *rx_buffer;
2330 union i40e_rx_desc *rx_desc;
2331 unsigned int size;
2332 u64 qword;
2333
2334 /* return some buffers to hardware, one at a time is too slow */
2335 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
2336 failure = failure ||
2337 i40e_alloc_rx_buffers(rx_ring, cleaned_count);
2338 cleaned_count = 0;
2339 }
2340
2341 rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean);
2342
2343 /* status_error_len will always be zero for unused descriptors
2344 * because it's cleared in cleanup, and overlaps with hdr_addr
2345 * which is always zero because packet split isn't used, if the
2346 * hardware wrote DD then the length will be non-zero
2347 */
2348 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
2349
2350 /* This memory barrier is needed to keep us from reading
2351 * any other fields out of the rx_desc until we have
2352 * verified the descriptor has been written back.
2353 */
2354 dma_rmb();
2355
2356 if (i40e_rx_is_programming_status(qword)) {
2357 i40e_clean_programming_status(rx_ring,
2358 rx_desc->raw.qword[0],
2359 qword);
2360 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean);
2361 i40e_inc_ntc(rx_ring);
2362 i40e_reuse_rx_page(rx_ring, rx_buffer);
2363 cleaned_count++;
2364 continue;
2365 }
2366
2367 size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
2368 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
2369 if (!size)
2370 break;
2371
2372 i40e_trace(clean_rx_irq, rx_ring, rx_desc, skb);
2373 rx_buffer = i40e_get_rx_buffer(rx_ring, size);
2374
2375 /* retrieve a buffer from the ring */
2376 if (!skb) {
2377 xdp.data = page_address(rx_buffer->page) +
2378 rx_buffer->page_offset;
2379 xdp.data_meta = xdp.data;
2380 xdp.data_hard_start = xdp.data -
2381 i40e_rx_offset(rx_ring);
2382 xdp.data_end = xdp.data + size;
2383#if (PAGE_SIZE > 4096)
2384 /* At larger PAGE_SIZE, frame_sz depend on len size */
2385 xdp.frame_sz = i40e_rx_frame_truesize(rx_ring, size);
2386#endif
2387 skb = i40e_run_xdp(rx_ring, &xdp);
2388 }
2389
2390 if (IS_ERR(skb)) {
2391 unsigned int xdp_res = -PTR_ERR(skb);
2392
2393 if (xdp_res & (I40E_XDP_TX | I40E_XDP_REDIR)) {
2394 xdp_xmit |= xdp_res;
2395 i40e_rx_buffer_flip(rx_ring, rx_buffer, size);
2396 } else {
2397 rx_buffer->pagecnt_bias++;
2398 }
2399 total_rx_bytes += size;
2400 total_rx_packets++;
2401 } else if (skb) {
2402 i40e_add_rx_frag(rx_ring, rx_buffer, skb, size);
2403 } else if (ring_uses_build_skb(rx_ring)) {
2404 skb = i40e_build_skb(rx_ring, rx_buffer, &xdp);
2405 } else {
2406 skb = i40e_construct_skb(rx_ring, rx_buffer, &xdp);
2407 }
2408
2409 /* exit if we failed to retrieve a buffer */
2410 if (!skb) {
2411 rx_ring->rx_stats.alloc_buff_failed++;
2412 rx_buffer->pagecnt_bias++;
2413 break;
2414 }
2415
2416 i40e_put_rx_buffer(rx_ring, rx_buffer);
2417 cleaned_count++;
2418
2419 if (i40e_is_non_eop(rx_ring, rx_desc, skb))
2420 continue;
2421
2422 if (i40e_cleanup_headers(rx_ring, skb, rx_desc)) {
2423 skb = NULL;
2424 continue;
2425 }
2426
2427 /* probably a little skewed due to removing CRC */
2428 total_rx_bytes += skb->len;
2429
2430 /* populate checksum, VLAN, and protocol */
2431 i40e_process_skb_fields(rx_ring, rx_desc, skb);
2432
2433 i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb);
2434 napi_gro_receive(&rx_ring->q_vector->napi, skb);
2435 skb = NULL;
2436
2437 /* update budget accounting */
2438 total_rx_packets++;
2439 }
2440
2441 i40e_finalize_xdp_rx(rx_ring, xdp_xmit);
2442 rx_ring->skb = skb;
2443
2444 i40e_update_rx_stats(rx_ring, total_rx_bytes, total_rx_packets);
2445
2446 /* guarantee a trip back through this routine if there was a failure */
2447 return failure ? budget : (int)total_rx_packets;
2448}
2449
2450static inline u32 i40e_buildreg_itr(const int type, u16 itr)
2451{
2452 u32 val;
2453
2454 /* We don't bother with setting the CLEARPBA bit as the data sheet
2455 * points out doing so is "meaningless since it was already
2456 * auto-cleared". The auto-clearing happens when the interrupt is
2457 * asserted.
2458 *
2459 * Hardware errata 28 for also indicates that writing to a
2460 * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear
2461 * an event in the PBA anyway so we need to rely on the automask
2462 * to hold pending events for us until the interrupt is re-enabled
2463 *
2464 * The itr value is reported in microseconds, and the register
2465 * value is recorded in 2 microsecond units. For this reason we
2466 * only need to shift by the interval shift - 1 instead of the
2467 * full value.
2468 */
2469 itr &= I40E_ITR_MASK;
2470
2471 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2472 (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
2473 (itr << (I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT - 1));
2474
2475 return val;
2476}
2477
2478/* a small macro to shorten up some long lines */
2479#define INTREG I40E_PFINT_DYN_CTLN
2480
2481/* The act of updating the ITR will cause it to immediately trigger. In order
2482 * to prevent this from throwing off adaptive update statistics we defer the
2483 * update so that it can only happen so often. So after either Tx or Rx are
2484 * updated we make the adaptive scheme wait until either the ITR completely
2485 * expires via the next_update expiration or we have been through at least
2486 * 3 interrupts.
2487 */
2488#define ITR_COUNTDOWN_START 3
2489
2490/**
2491 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
2492 * @vsi: the VSI we care about
2493 * @q_vector: q_vector for which itr is being updated and interrupt enabled
2494 *
2495 **/
2496static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
2497 struct i40e_q_vector *q_vector)
2498{
2499 struct i40e_hw *hw = &vsi->back->hw;
2500 u32 intval;
2501
2502 /* If we don't have MSIX, then we only need to re-enable icr0 */
2503 if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) {
2504 i40e_irq_dynamic_enable_icr0(vsi->back);
2505 return;
2506 }
2507
2508 /* These will do nothing if dynamic updates are not enabled */
2509 i40e_update_itr(q_vector, &q_vector->tx);
2510 i40e_update_itr(q_vector, &q_vector->rx);
2511
2512 /* This block of logic allows us to get away with only updating
2513 * one ITR value with each interrupt. The idea is to perform a
2514 * pseudo-lazy update with the following criteria.
2515 *
2516 * 1. Rx is given higher priority than Tx if both are in same state
2517 * 2. If we must reduce an ITR that is given highest priority.
2518 * 3. We then give priority to increasing ITR based on amount.
2519 */
2520 if (q_vector->rx.target_itr < q_vector->rx.current_itr) {
2521 /* Rx ITR needs to be reduced, this is highest priority */
2522 intval = i40e_buildreg_itr(I40E_RX_ITR,
2523 q_vector->rx.target_itr);
2524 q_vector->rx.current_itr = q_vector->rx.target_itr;
2525 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2526 } else if ((q_vector->tx.target_itr < q_vector->tx.current_itr) ||
2527 ((q_vector->rx.target_itr - q_vector->rx.current_itr) <
2528 (q_vector->tx.target_itr - q_vector->tx.current_itr))) {
2529 /* Tx ITR needs to be reduced, this is second priority
2530 * Tx ITR needs to be increased more than Rx, fourth priority
2531 */
2532 intval = i40e_buildreg_itr(I40E_TX_ITR,
2533 q_vector->tx.target_itr);
2534 q_vector->tx.current_itr = q_vector->tx.target_itr;
2535 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2536 } else if (q_vector->rx.current_itr != q_vector->rx.target_itr) {
2537 /* Rx ITR needs to be increased, third priority */
2538 intval = i40e_buildreg_itr(I40E_RX_ITR,
2539 q_vector->rx.target_itr);
2540 q_vector->rx.current_itr = q_vector->rx.target_itr;
2541 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2542 } else {
2543 /* No ITR update, lowest priority */
2544 intval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
2545 if (q_vector->itr_countdown)
2546 q_vector->itr_countdown--;
2547 }
2548
2549 if (!test_bit(__I40E_VSI_DOWN, vsi->state))
2550 wr32(hw, INTREG(q_vector->reg_idx), intval);
2551}
2552
2553/**
2554 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
2555 * @napi: napi struct with our devices info in it
2556 * @budget: amount of work driver is allowed to do this pass, in packets
2557 *
2558 * This function will clean all queues associated with a q_vector.
2559 *
2560 * Returns the amount of work done
2561 **/
2562int i40e_napi_poll(struct napi_struct *napi, int budget)
2563{
2564 struct i40e_q_vector *q_vector =
2565 container_of(napi, struct i40e_q_vector, napi);
2566 struct i40e_vsi *vsi = q_vector->vsi;
2567 struct i40e_ring *ring;
2568 bool clean_complete = true;
2569 bool arm_wb = false;
2570 int budget_per_ring;
2571 int work_done = 0;
2572
2573 if (test_bit(__I40E_VSI_DOWN, vsi->state)) {
2574 napi_complete(napi);
2575 return 0;
2576 }
2577
2578 /* Since the actual Tx work is minimal, we can give the Tx a larger
2579 * budget and be more aggressive about cleaning up the Tx descriptors.
2580 */
2581 i40e_for_each_ring(ring, q_vector->tx) {
2582 bool wd = ring->xsk_umem ?
2583 i40e_clean_xdp_tx_irq(vsi, ring) :
2584 i40e_clean_tx_irq(vsi, ring, budget);
2585
2586 if (!wd) {
2587 clean_complete = false;
2588 continue;
2589 }
2590 arm_wb |= ring->arm_wb;
2591 ring->arm_wb = false;
2592 }
2593
2594 /* Handle case where we are called by netpoll with a budget of 0 */
2595 if (budget <= 0)
2596 goto tx_only;
2597
2598 /* normally we have 1 Rx ring per q_vector */
2599 if (unlikely(q_vector->num_ringpairs > 1))
2600 /* We attempt to distribute budget to each Rx queue fairly, but
2601 * don't allow the budget to go below 1 because that would exit
2602 * polling early.
2603 */
2604 budget_per_ring = max_t(int, budget / q_vector->num_ringpairs, 1);
2605 else
2606 /* Max of 1 Rx ring in this q_vector so give it the budget */
2607 budget_per_ring = budget;
2608
2609 i40e_for_each_ring(ring, q_vector->rx) {
2610 int cleaned = ring->xsk_umem ?
2611 i40e_clean_rx_irq_zc(ring, budget_per_ring) :
2612 i40e_clean_rx_irq(ring, budget_per_ring);
2613
2614 work_done += cleaned;
2615 /* if we clean as many as budgeted, we must not be done */
2616 if (cleaned >= budget_per_ring)
2617 clean_complete = false;
2618 }
2619
2620 /* If work not completed, return budget and polling will return */
2621 if (!clean_complete) {
2622 int cpu_id = smp_processor_id();
2623
2624 /* It is possible that the interrupt affinity has changed but,
2625 * if the cpu is pegged at 100%, polling will never exit while
2626 * traffic continues and the interrupt will be stuck on this
2627 * cpu. We check to make sure affinity is correct before we
2628 * continue to poll, otherwise we must stop polling so the
2629 * interrupt can move to the correct cpu.
2630 */
2631 if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) {
2632 /* Tell napi that we are done polling */
2633 napi_complete_done(napi, work_done);
2634
2635 /* Force an interrupt */
2636 i40e_force_wb(vsi, q_vector);
2637
2638 /* Return budget-1 so that polling stops */
2639 return budget - 1;
2640 }
2641tx_only:
2642 if (arm_wb) {
2643 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
2644 i40e_enable_wb_on_itr(vsi, q_vector);
2645 }
2646 return budget;
2647 }
2648
2649 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
2650 q_vector->arm_wb_state = false;
2651
2652 /* Exit the polling mode, but don't re-enable interrupts if stack might
2653 * poll us due to busy-polling
2654 */
2655 if (likely(napi_complete_done(napi, work_done)))
2656 i40e_update_enable_itr(vsi, q_vector);
2657
2658 return min(work_done, budget - 1);
2659}
2660
2661/**
2662 * i40e_atr - Add a Flow Director ATR filter
2663 * @tx_ring: ring to add programming descriptor to
2664 * @skb: send buffer
2665 * @tx_flags: send tx flags
2666 **/
2667static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
2668 u32 tx_flags)
2669{
2670 struct i40e_filter_program_desc *fdir_desc;
2671 struct i40e_pf *pf = tx_ring->vsi->back;
2672 union {
2673 unsigned char *network;
2674 struct iphdr *ipv4;
2675 struct ipv6hdr *ipv6;
2676 } hdr;
2677 struct tcphdr *th;
2678 unsigned int hlen;
2679 u32 flex_ptype, dtype_cmd;
2680 int l4_proto;
2681 u16 i;
2682
2683 /* make sure ATR is enabled */
2684 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
2685 return;
2686
2687 if (test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
2688 return;
2689
2690 /* if sampling is disabled do nothing */
2691 if (!tx_ring->atr_sample_rate)
2692 return;
2693
2694 /* Currently only IPv4/IPv6 with TCP is supported */
2695 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6)))
2696 return;
2697
2698 /* snag network header to get L4 type and address */
2699 hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ?
2700 skb_inner_network_header(skb) : skb_network_header(skb);
2701
2702 /* Note: tx_flags gets modified to reflect inner protocols in
2703 * tx_enable_csum function if encap is enabled.
2704 */
2705 if (tx_flags & I40E_TX_FLAGS_IPV4) {
2706 /* access ihl as u8 to avoid unaligned access on ia64 */
2707 hlen = (hdr.network[0] & 0x0F) << 2;
2708 l4_proto = hdr.ipv4->protocol;
2709 } else {
2710 /* find the start of the innermost ipv6 header */
2711 unsigned int inner_hlen = hdr.network - skb->data;
2712 unsigned int h_offset = inner_hlen;
2713
2714 /* this function updates h_offset to the end of the header */
2715 l4_proto =
2716 ipv6_find_hdr(skb, &h_offset, IPPROTO_TCP, NULL, NULL);
2717 /* hlen will contain our best estimate of the tcp header */
2718 hlen = h_offset - inner_hlen;
2719 }
2720
2721 if (l4_proto != IPPROTO_TCP)
2722 return;
2723
2724 th = (struct tcphdr *)(hdr.network + hlen);
2725
2726 /* Due to lack of space, no more new filters can be programmed */
2727 if (th->syn && test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
2728 return;
2729 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) {
2730 /* HW ATR eviction will take care of removing filters on FIN
2731 * and RST packets.
2732 */
2733 if (th->fin || th->rst)
2734 return;
2735 }
2736
2737 tx_ring->atr_count++;
2738
2739 /* sample on all syn/fin/rst packets or once every atr sample rate */
2740 if (!th->fin &&
2741 !th->syn &&
2742 !th->rst &&
2743 (tx_ring->atr_count < tx_ring->atr_sample_rate))
2744 return;
2745
2746 tx_ring->atr_count = 0;
2747
2748 /* grab the next descriptor */
2749 i = tx_ring->next_to_use;
2750 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
2751
2752 i++;
2753 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2754
2755 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
2756 I40E_TXD_FLTR_QW0_QINDEX_MASK;
2757 flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ?
2758 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
2759 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
2760 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
2761 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
2762
2763 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
2764
2765 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
2766
2767 dtype_cmd |= (th->fin || th->rst) ?
2768 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2769 I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
2770 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2771 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2772
2773 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
2774 I40E_TXD_FLTR_QW1_DEST_SHIFT;
2775
2776 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
2777 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
2778
2779 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
2780 if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL))
2781 dtype_cmd |=
2782 ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) <<
2783 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2784 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2785 else
2786 dtype_cmd |=
2787 ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) <<
2788 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2789 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2790
2791 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED)
2792 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;
2793
2794 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
2795 fdir_desc->rsvd = cpu_to_le32(0);
2796 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
2797 fdir_desc->fd_id = cpu_to_le32(0);
2798}
2799
2800/**
2801 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2802 * @skb: send buffer
2803 * @tx_ring: ring to send buffer on
2804 * @flags: the tx flags to be set
2805 *
2806 * Checks the skb and set up correspondingly several generic transmit flags
2807 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2808 *
2809 * Returns error code indicate the frame should be dropped upon error and the
2810 * otherwise returns 0 to indicate the flags has been set properly.
2811 **/
2812static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2813 struct i40e_ring *tx_ring,
2814 u32 *flags)
2815{
2816 __be16 protocol = skb->protocol;
2817 u32 tx_flags = 0;
2818
2819 if (protocol == htons(ETH_P_8021Q) &&
2820 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
2821 /* When HW VLAN acceleration is turned off by the user the
2822 * stack sets the protocol to 8021q so that the driver
2823 * can take any steps required to support the SW only
2824 * VLAN handling. In our case the driver doesn't need
2825 * to take any further steps so just set the protocol
2826 * to the encapsulated ethertype.
2827 */
2828 skb->protocol = vlan_get_protocol(skb);
2829 goto out;
2830 }
2831
2832 /* if we have a HW VLAN tag being added, default to the HW one */
2833 if (skb_vlan_tag_present(skb)) {
2834 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
2835 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2836 /* else if it is a SW VLAN, check the next protocol and store the tag */
2837 } else if (protocol == htons(ETH_P_8021Q)) {
2838 struct vlan_hdr *vhdr, _vhdr;
2839
2840 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
2841 if (!vhdr)
2842 return -EINVAL;
2843
2844 protocol = vhdr->h_vlan_encapsulated_proto;
2845 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
2846 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
2847 }
2848
2849 if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2850 goto out;
2851
2852 /* Insert 802.1p priority into VLAN header */
2853 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
2854 (skb->priority != TC_PRIO_CONTROL)) {
2855 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
2856 tx_flags |= (skb->priority & 0x7) <<
2857 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
2858 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
2859 struct vlan_ethhdr *vhdr;
2860 int rc;
2861
2862 rc = skb_cow_head(skb, 0);
2863 if (rc < 0)
2864 return rc;
2865 vhdr = (struct vlan_ethhdr *)skb->data;
2866 vhdr->h_vlan_TCI = htons(tx_flags >>
2867 I40E_TX_FLAGS_VLAN_SHIFT);
2868 } else {
2869 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2870 }
2871 }
2872
2873out:
2874 *flags = tx_flags;
2875 return 0;
2876}
2877
2878/**
2879 * i40e_tso - set up the tso context descriptor
2880 * @first: pointer to first Tx buffer for xmit
2881 * @hdr_len: ptr to the size of the packet header
2882 * @cd_type_cmd_tso_mss: Quad Word 1
2883 *
2884 * Returns 0 if no TSO can happen, 1 if tso is going, or error
2885 **/
2886static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len,
2887 u64 *cd_type_cmd_tso_mss)
2888{
2889 struct sk_buff *skb = first->skb;
2890 u64 cd_cmd, cd_tso_len, cd_mss;
2891 union {
2892 struct iphdr *v4;
2893 struct ipv6hdr *v6;
2894 unsigned char *hdr;
2895 } ip;
2896 union {
2897 struct tcphdr *tcp;
2898 struct udphdr *udp;
2899 unsigned char *hdr;
2900 } l4;
2901 u32 paylen, l4_offset;
2902 u16 gso_segs, gso_size;
2903 int err;
2904
2905 if (skb->ip_summed != CHECKSUM_PARTIAL)
2906 return 0;
2907
2908 if (!skb_is_gso(skb))
2909 return 0;
2910
2911 err = skb_cow_head(skb, 0);
2912 if (err < 0)
2913 return err;
2914
2915 ip.hdr = skb_network_header(skb);
2916 l4.hdr = skb_transport_header(skb);
2917
2918 /* initialize outer IP header fields */
2919 if (ip.v4->version == 4) {
2920 ip.v4->tot_len = 0;
2921 ip.v4->check = 0;
2922 } else {
2923 ip.v6->payload_len = 0;
2924 }
2925
2926 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
2927 SKB_GSO_GRE_CSUM |
2928 SKB_GSO_IPXIP4 |
2929 SKB_GSO_IPXIP6 |
2930 SKB_GSO_UDP_TUNNEL |
2931 SKB_GSO_UDP_TUNNEL_CSUM)) {
2932 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
2933 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) {
2934 l4.udp->len = 0;
2935
2936 /* determine offset of outer transport header */
2937 l4_offset = l4.hdr - skb->data;
2938
2939 /* remove payload length from outer checksum */
2940 paylen = skb->len - l4_offset;
2941 csum_replace_by_diff(&l4.udp->check,
2942 (__force __wsum)htonl(paylen));
2943 }
2944
2945 /* reset pointers to inner headers */
2946 ip.hdr = skb_inner_network_header(skb);
2947 l4.hdr = skb_inner_transport_header(skb);
2948
2949 /* initialize inner IP header fields */
2950 if (ip.v4->version == 4) {
2951 ip.v4->tot_len = 0;
2952 ip.v4->check = 0;
2953 } else {
2954 ip.v6->payload_len = 0;
2955 }
2956 }
2957
2958 /* determine offset of inner transport header */
2959 l4_offset = l4.hdr - skb->data;
2960
2961 /* remove payload length from inner checksum */
2962 paylen = skb->len - l4_offset;
2963
2964 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
2965 csum_replace_by_diff(&l4.udp->check, (__force __wsum)htonl(paylen));
2966 /* compute length of segmentation header */
2967 *hdr_len = sizeof(*l4.udp) + l4_offset;
2968 } else {
2969 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen));
2970 /* compute length of segmentation header */
2971 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
2972 }
2973
2974 /* pull values out of skb_shinfo */
2975 gso_size = skb_shinfo(skb)->gso_size;
2976 gso_segs = skb_shinfo(skb)->gso_segs;
2977
2978 /* update GSO size and bytecount with header size */
2979 first->gso_segs = gso_segs;
2980 first->bytecount += (first->gso_segs - 1) * *hdr_len;
2981
2982 /* find the field values */
2983 cd_cmd = I40E_TX_CTX_DESC_TSO;
2984 cd_tso_len = skb->len - *hdr_len;
2985 cd_mss = gso_size;
2986 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
2987 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2988 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
2989 return 1;
2990}
2991
2992/**
2993 * i40e_tsyn - set up the tsyn context descriptor
2994 * @tx_ring: ptr to the ring to send
2995 * @skb: ptr to the skb we're sending
2996 * @tx_flags: the collected send information
2997 * @cd_type_cmd_tso_mss: Quad Word 1
2998 *
2999 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
3000 **/
3001static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
3002 u32 tx_flags, u64 *cd_type_cmd_tso_mss)
3003{
3004 struct i40e_pf *pf;
3005
3006 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
3007 return 0;
3008
3009 /* Tx timestamps cannot be sampled when doing TSO */
3010 if (tx_flags & I40E_TX_FLAGS_TSO)
3011 return 0;
3012
3013 /* only timestamp the outbound packet if the user has requested it and
3014 * we are not already transmitting a packet to be timestamped
3015 */
3016 pf = i40e_netdev_to_pf(tx_ring->netdev);
3017 if (!(pf->flags & I40E_FLAG_PTP))
3018 return 0;
3019
3020 if (pf->ptp_tx &&
3021 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, pf->state)) {
3022 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3023 pf->ptp_tx_start = jiffies;
3024 pf->ptp_tx_skb = skb_get(skb);
3025 } else {
3026 pf->tx_hwtstamp_skipped++;
3027 return 0;
3028 }
3029
3030 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
3031 I40E_TXD_CTX_QW1_CMD_SHIFT;
3032
3033 return 1;
3034}
3035
3036/**
3037 * i40e_tx_enable_csum - Enable Tx checksum offloads
3038 * @skb: send buffer
3039 * @tx_flags: pointer to Tx flags currently set
3040 * @td_cmd: Tx descriptor command bits to set
3041 * @td_offset: Tx descriptor header offsets to set
3042 * @tx_ring: Tx descriptor ring
3043 * @cd_tunneling: ptr to context desc bits
3044 **/
3045static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
3046 u32 *td_cmd, u32 *td_offset,
3047 struct i40e_ring *tx_ring,
3048 u32 *cd_tunneling)
3049{
3050 union {
3051 struct iphdr *v4;
3052 struct ipv6hdr *v6;
3053 unsigned char *hdr;
3054 } ip;
3055 union {
3056 struct tcphdr *tcp;
3057 struct udphdr *udp;
3058 unsigned char *hdr;
3059 } l4;
3060 unsigned char *exthdr;
3061 u32 offset, cmd = 0;
3062 __be16 frag_off;
3063 u8 l4_proto = 0;
3064
3065 if (skb->ip_summed != CHECKSUM_PARTIAL)
3066 return 0;
3067
3068 ip.hdr = skb_network_header(skb);
3069 l4.hdr = skb_transport_header(skb);
3070
3071 /* compute outer L2 header size */
3072 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
3073
3074 if (skb->encapsulation) {
3075 u32 tunnel = 0;
3076 /* define outer network header type */
3077 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
3078 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
3079 I40E_TX_CTX_EXT_IP_IPV4 :
3080 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
3081
3082 l4_proto = ip.v4->protocol;
3083 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
3084 tunnel |= I40E_TX_CTX_EXT_IP_IPV6;
3085
3086 exthdr = ip.hdr + sizeof(*ip.v6);
3087 l4_proto = ip.v6->nexthdr;
3088 if (l4.hdr != exthdr)
3089 ipv6_skip_exthdr(skb, exthdr - skb->data,
3090 &l4_proto, &frag_off);
3091 }
3092
3093 /* define outer transport */
3094 switch (l4_proto) {
3095 case IPPROTO_UDP:
3096 tunnel |= I40E_TXD_CTX_UDP_TUNNELING;
3097 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3098 break;
3099 case IPPROTO_GRE:
3100 tunnel |= I40E_TXD_CTX_GRE_TUNNELING;
3101 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3102 break;
3103 case IPPROTO_IPIP:
3104 case IPPROTO_IPV6:
3105 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3106 l4.hdr = skb_inner_network_header(skb);
3107 break;
3108 default:
3109 if (*tx_flags & I40E_TX_FLAGS_TSO)
3110 return -1;
3111
3112 skb_checksum_help(skb);
3113 return 0;
3114 }
3115
3116 /* compute outer L3 header size */
3117 tunnel |= ((l4.hdr - ip.hdr) / 4) <<
3118 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
3119
3120 /* switch IP header pointer from outer to inner header */
3121 ip.hdr = skb_inner_network_header(skb);
3122
3123 /* compute tunnel header size */
3124 tunnel |= ((ip.hdr - l4.hdr) / 2) <<
3125 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
3126
3127 /* indicate if we need to offload outer UDP header */
3128 if ((*tx_flags & I40E_TX_FLAGS_TSO) &&
3129 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
3130 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
3131 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
3132
3133 /* record tunnel offload values */
3134 *cd_tunneling |= tunnel;
3135
3136 /* switch L4 header pointer from outer to inner */
3137 l4.hdr = skb_inner_transport_header(skb);
3138 l4_proto = 0;
3139
3140 /* reset type as we transition from outer to inner headers */
3141 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6);
3142 if (ip.v4->version == 4)
3143 *tx_flags |= I40E_TX_FLAGS_IPV4;
3144 if (ip.v6->version == 6)
3145 *tx_flags |= I40E_TX_FLAGS_IPV6;
3146 }
3147
3148 /* Enable IP checksum offloads */
3149 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
3150 l4_proto = ip.v4->protocol;
3151 /* the stack computes the IP header already, the only time we
3152 * need the hardware to recompute it is in the case of TSO.
3153 */
3154 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
3155 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM :
3156 I40E_TX_DESC_CMD_IIPT_IPV4;
3157 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
3158 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
3159
3160 exthdr = ip.hdr + sizeof(*ip.v6);
3161 l4_proto = ip.v6->nexthdr;
3162 if (l4.hdr != exthdr)
3163 ipv6_skip_exthdr(skb, exthdr - skb->data,
3164 &l4_proto, &frag_off);
3165 }
3166
3167 /* compute inner L3 header size */
3168 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
3169
3170 /* Enable L4 checksum offloads */
3171 switch (l4_proto) {
3172 case IPPROTO_TCP:
3173 /* enable checksum offloads */
3174 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
3175 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3176 break;
3177 case IPPROTO_SCTP:
3178 /* enable SCTP checksum offload */
3179 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
3180 offset |= (sizeof(struct sctphdr) >> 2) <<
3181 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3182 break;
3183 case IPPROTO_UDP:
3184 /* enable UDP checksum offload */
3185 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
3186 offset |= (sizeof(struct udphdr) >> 2) <<
3187 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3188 break;
3189 default:
3190 if (*tx_flags & I40E_TX_FLAGS_TSO)
3191 return -1;
3192 skb_checksum_help(skb);
3193 return 0;
3194 }
3195
3196 *td_cmd |= cmd;
3197 *td_offset |= offset;
3198
3199 return 1;
3200}
3201
3202/**
3203 * i40e_create_tx_ctx Build the Tx context descriptor
3204 * @tx_ring: ring to create the descriptor on
3205 * @cd_type_cmd_tso_mss: Quad Word 1
3206 * @cd_tunneling: Quad Word 0 - bits 0-31
3207 * @cd_l2tag2: Quad Word 0 - bits 32-63
3208 **/
3209static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
3210 const u64 cd_type_cmd_tso_mss,
3211 const u32 cd_tunneling, const u32 cd_l2tag2)
3212{
3213 struct i40e_tx_context_desc *context_desc;
3214 int i = tx_ring->next_to_use;
3215
3216 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
3217 !cd_tunneling && !cd_l2tag2)
3218 return;
3219
3220 /* grab the next descriptor */
3221 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
3222
3223 i++;
3224 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3225
3226 /* cpu_to_le32 and assign to struct fields */
3227 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
3228 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
3229 context_desc->rsvd = cpu_to_le16(0);
3230 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
3231}
3232
3233/**
3234 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
3235 * @tx_ring: the ring to be checked
3236 * @size: the size buffer we want to assure is available
3237 *
3238 * Returns -EBUSY if a stop is needed, else 0
3239 **/
3240int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
3241{
3242 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
3243 /* Memory barrier before checking head and tail */
3244 smp_mb();
3245
3246 /* Check again in a case another CPU has just made room available. */
3247 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
3248 return -EBUSY;
3249
3250 /* A reprieve! - use start_queue because it doesn't call schedule */
3251 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
3252 ++tx_ring->tx_stats.restart_queue;
3253 return 0;
3254}
3255
3256/**
3257 * __i40e_chk_linearize - Check if there are more than 8 buffers per packet
3258 * @skb: send buffer
3259 *
3260 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
3261 * and so we need to figure out the cases where we need to linearize the skb.
3262 *
3263 * For TSO we need to count the TSO header and segment payload separately.
3264 * As such we need to check cases where we have 7 fragments or more as we
3265 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
3266 * the segment payload in the first descriptor, and another 7 for the
3267 * fragments.
3268 **/
3269bool __i40e_chk_linearize(struct sk_buff *skb)
3270{
3271 const skb_frag_t *frag, *stale;
3272 int nr_frags, sum;
3273
3274 /* no need to check if number of frags is less than 7 */
3275 nr_frags = skb_shinfo(skb)->nr_frags;
3276 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1))
3277 return false;
3278
3279 /* We need to walk through the list and validate that each group
3280 * of 6 fragments totals at least gso_size.
3281 */
3282 nr_frags -= I40E_MAX_BUFFER_TXD - 2;
3283 frag = &skb_shinfo(skb)->frags[0];
3284
3285 /* Initialize size to the negative value of gso_size minus 1. We
3286 * use this as the worst case scenerio in which the frag ahead
3287 * of us only provides one byte which is why we are limited to 6
3288 * descriptors for a single transmit as the header and previous
3289 * fragment are already consuming 2 descriptors.
3290 */
3291 sum = 1 - skb_shinfo(skb)->gso_size;
3292
3293 /* Add size of frags 0 through 4 to create our initial sum */
3294 sum += skb_frag_size(frag++);
3295 sum += skb_frag_size(frag++);
3296 sum += skb_frag_size(frag++);
3297 sum += skb_frag_size(frag++);
3298 sum += skb_frag_size(frag++);
3299
3300 /* Walk through fragments adding latest fragment, testing it, and
3301 * then removing stale fragments from the sum.
3302 */
3303 for (stale = &skb_shinfo(skb)->frags[0];; stale++) {
3304 int stale_size = skb_frag_size(stale);
3305
3306 sum += skb_frag_size(frag++);
3307
3308 /* The stale fragment may present us with a smaller
3309 * descriptor than the actual fragment size. To account
3310 * for that we need to remove all the data on the front and
3311 * figure out what the remainder would be in the last
3312 * descriptor associated with the fragment.
3313 */
3314 if (stale_size > I40E_MAX_DATA_PER_TXD) {
3315 int align_pad = -(skb_frag_off(stale)) &
3316 (I40E_MAX_READ_REQ_SIZE - 1);
3317
3318 sum -= align_pad;
3319 stale_size -= align_pad;
3320
3321 do {
3322 sum -= I40E_MAX_DATA_PER_TXD_ALIGNED;
3323 stale_size -= I40E_MAX_DATA_PER_TXD_ALIGNED;
3324 } while (stale_size > I40E_MAX_DATA_PER_TXD);
3325 }
3326
3327 /* if sum is negative we failed to make sufficient progress */
3328 if (sum < 0)
3329 return true;
3330
3331 if (!nr_frags--)
3332 break;
3333
3334 sum -= stale_size;
3335 }
3336
3337 return false;
3338}
3339
3340/**
3341 * i40e_tx_map - Build the Tx descriptor
3342 * @tx_ring: ring to send buffer on
3343 * @skb: send buffer
3344 * @first: first buffer info buffer to use
3345 * @tx_flags: collected send information
3346 * @hdr_len: size of the packet header
3347 * @td_cmd: the command field in the descriptor
3348 * @td_offset: offset for checksum or crc
3349 *
3350 * Returns 0 on success, -1 on failure to DMA
3351 **/
3352static inline int i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
3353 struct i40e_tx_buffer *first, u32 tx_flags,
3354 const u8 hdr_len, u32 td_cmd, u32 td_offset)
3355{
3356 unsigned int data_len = skb->data_len;
3357 unsigned int size = skb_headlen(skb);
3358 skb_frag_t *frag;
3359 struct i40e_tx_buffer *tx_bi;
3360 struct i40e_tx_desc *tx_desc;
3361 u16 i = tx_ring->next_to_use;
3362 u32 td_tag = 0;
3363 dma_addr_t dma;
3364 u16 desc_count = 1;
3365
3366 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
3367 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
3368 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
3369 I40E_TX_FLAGS_VLAN_SHIFT;
3370 }
3371
3372 first->tx_flags = tx_flags;
3373
3374 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
3375
3376 tx_desc = I40E_TX_DESC(tx_ring, i);
3377 tx_bi = first;
3378
3379 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
3380 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
3381
3382 if (dma_mapping_error(tx_ring->dev, dma))
3383 goto dma_error;
3384
3385 /* record length, and DMA address */
3386 dma_unmap_len_set(tx_bi, len, size);
3387 dma_unmap_addr_set(tx_bi, dma, dma);
3388
3389 /* align size to end of page */
3390 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1);
3391 tx_desc->buffer_addr = cpu_to_le64(dma);
3392
3393 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
3394 tx_desc->cmd_type_offset_bsz =
3395 build_ctob(td_cmd, td_offset,
3396 max_data, td_tag);
3397
3398 tx_desc++;
3399 i++;
3400 desc_count++;
3401
3402 if (i == tx_ring->count) {
3403 tx_desc = I40E_TX_DESC(tx_ring, 0);
3404 i = 0;
3405 }
3406
3407 dma += max_data;
3408 size -= max_data;
3409
3410 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
3411 tx_desc->buffer_addr = cpu_to_le64(dma);
3412 }
3413
3414 if (likely(!data_len))
3415 break;
3416
3417 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
3418 size, td_tag);
3419
3420 tx_desc++;
3421 i++;
3422 desc_count++;
3423
3424 if (i == tx_ring->count) {
3425 tx_desc = I40E_TX_DESC(tx_ring, 0);
3426 i = 0;
3427 }
3428
3429 size = skb_frag_size(frag);
3430 data_len -= size;
3431
3432 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
3433 DMA_TO_DEVICE);
3434
3435 tx_bi = &tx_ring->tx_bi[i];
3436 }
3437
3438 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
3439
3440 i++;
3441 if (i == tx_ring->count)
3442 i = 0;
3443
3444 tx_ring->next_to_use = i;
3445
3446 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
3447
3448 /* write last descriptor with EOP bit */
3449 td_cmd |= I40E_TX_DESC_CMD_EOP;
3450
3451 /* We OR these values together to check both against 4 (WB_STRIDE)
3452 * below. This is safe since we don't re-use desc_count afterwards.
3453 */
3454 desc_count |= ++tx_ring->packet_stride;
3455
3456 if (desc_count >= WB_STRIDE) {
3457 /* write last descriptor with RS bit set */
3458 td_cmd |= I40E_TX_DESC_CMD_RS;
3459 tx_ring->packet_stride = 0;
3460 }
3461
3462 tx_desc->cmd_type_offset_bsz =
3463 build_ctob(td_cmd, td_offset, size, td_tag);
3464
3465 skb_tx_timestamp(skb);
3466
3467 /* Force memory writes to complete before letting h/w know there
3468 * are new descriptors to fetch.
3469 *
3470 * We also use this memory barrier to make certain all of the
3471 * status bits have been updated before next_to_watch is written.
3472 */
3473 wmb();
3474
3475 /* set next_to_watch value indicating a packet is present */
3476 first->next_to_watch = tx_desc;
3477
3478 /* notify HW of packet */
3479 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
3480 writel(i, tx_ring->tail);
3481 }
3482
3483 return 0;
3484
3485dma_error:
3486 dev_info(tx_ring->dev, "TX DMA map failed\n");
3487
3488 /* clear dma mappings for failed tx_bi map */
3489 for (;;) {
3490 tx_bi = &tx_ring->tx_bi[i];
3491 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
3492 if (tx_bi == first)
3493 break;
3494 if (i == 0)
3495 i = tx_ring->count;
3496 i--;
3497 }
3498
3499 tx_ring->next_to_use = i;
3500
3501 return -1;
3502}
3503
3504/**
3505 * i40e_xmit_xdp_ring - transmits an XDP buffer to an XDP Tx ring
3506 * @xdp: data to transmit
3507 * @xdp_ring: XDP Tx ring
3508 **/
3509static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf,
3510 struct i40e_ring *xdp_ring)
3511{
3512 u16 i = xdp_ring->next_to_use;
3513 struct i40e_tx_buffer *tx_bi;
3514 struct i40e_tx_desc *tx_desc;
3515 void *data = xdpf->data;
3516 u32 size = xdpf->len;
3517 dma_addr_t dma;
3518
3519 if (!unlikely(I40E_DESC_UNUSED(xdp_ring))) {
3520 xdp_ring->tx_stats.tx_busy++;
3521 return I40E_XDP_CONSUMED;
3522 }
3523 dma = dma_map_single(xdp_ring->dev, data, size, DMA_TO_DEVICE);
3524 if (dma_mapping_error(xdp_ring->dev, dma))
3525 return I40E_XDP_CONSUMED;
3526
3527 tx_bi = &xdp_ring->tx_bi[i];
3528 tx_bi->bytecount = size;
3529 tx_bi->gso_segs = 1;
3530 tx_bi->xdpf = xdpf;
3531
3532 /* record length, and DMA address */
3533 dma_unmap_len_set(tx_bi, len, size);
3534 dma_unmap_addr_set(tx_bi, dma, dma);
3535
3536 tx_desc = I40E_TX_DESC(xdp_ring, i);
3537 tx_desc->buffer_addr = cpu_to_le64(dma);
3538 tx_desc->cmd_type_offset_bsz = build_ctob(I40E_TX_DESC_CMD_ICRC
3539 | I40E_TXD_CMD,
3540 0, size, 0);
3541
3542 /* Make certain all of the status bits have been updated
3543 * before next_to_watch is written.
3544 */
3545 smp_wmb();
3546
3547 xdp_ring->xdp_tx_active++;
3548 i++;
3549 if (i == xdp_ring->count)
3550 i = 0;
3551
3552 tx_bi->next_to_watch = tx_desc;
3553 xdp_ring->next_to_use = i;
3554
3555 return I40E_XDP_TX;
3556}
3557
3558/**
3559 * i40e_xmit_frame_ring - Sends buffer on Tx ring
3560 * @skb: send buffer
3561 * @tx_ring: ring to send buffer on
3562 *
3563 * Returns NETDEV_TX_OK if sent, else an error code
3564 **/
3565static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
3566 struct i40e_ring *tx_ring)
3567{
3568 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
3569 u32 cd_tunneling = 0, cd_l2tag2 = 0;
3570 struct i40e_tx_buffer *first;
3571 u32 td_offset = 0;
3572 u32 tx_flags = 0;
3573 __be16 protocol;
3574 u32 td_cmd = 0;
3575 u8 hdr_len = 0;
3576 int tso, count;
3577 int tsyn;
3578
3579 /* prefetch the data, we'll need it later */
3580 prefetch(skb->data);
3581
3582 i40e_trace(xmit_frame_ring, skb, tx_ring);
3583
3584 count = i40e_xmit_descriptor_count(skb);
3585 if (i40e_chk_linearize(skb, count)) {
3586 if (__skb_linearize(skb)) {
3587 dev_kfree_skb_any(skb);
3588 return NETDEV_TX_OK;
3589 }
3590 count = i40e_txd_use_count(skb->len);
3591 tx_ring->tx_stats.tx_linearize++;
3592 }
3593
3594 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
3595 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
3596 * + 4 desc gap to avoid the cache line where head is,
3597 * + 1 desc for context descriptor,
3598 * otherwise try next time
3599 */
3600 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
3601 tx_ring->tx_stats.tx_busy++;
3602 return NETDEV_TX_BUSY;
3603 }
3604
3605 /* record the location of the first descriptor for this packet */
3606 first = &tx_ring->tx_bi[tx_ring->next_to_use];
3607 first->skb = skb;
3608 first->bytecount = skb->len;
3609 first->gso_segs = 1;
3610
3611 /* prepare the xmit flags */
3612 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
3613 goto out_drop;
3614
3615 /* obtain protocol of skb */
3616 protocol = vlan_get_protocol(skb);
3617
3618 /* setup IPv4/IPv6 offloads */
3619 if (protocol == htons(ETH_P_IP))
3620 tx_flags |= I40E_TX_FLAGS_IPV4;
3621 else if (protocol == htons(ETH_P_IPV6))
3622 tx_flags |= I40E_TX_FLAGS_IPV6;
3623
3624 tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss);
3625
3626 if (tso < 0)
3627 goto out_drop;
3628 else if (tso)
3629 tx_flags |= I40E_TX_FLAGS_TSO;
3630
3631 /* Always offload the checksum, since it's in the data descriptor */
3632 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
3633 tx_ring, &cd_tunneling);
3634 if (tso < 0)
3635 goto out_drop;
3636
3637 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
3638
3639 if (tsyn)
3640 tx_flags |= I40E_TX_FLAGS_TSYN;
3641
3642 /* always enable CRC insertion offload */
3643 td_cmd |= I40E_TX_DESC_CMD_ICRC;
3644
3645 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
3646 cd_tunneling, cd_l2tag2);
3647
3648 /* Add Flow Director ATR if it's enabled.
3649 *
3650 * NOTE: this must always be directly before the data descriptor.
3651 */
3652 i40e_atr(tx_ring, skb, tx_flags);
3653
3654 if (i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
3655 td_cmd, td_offset))
3656 goto cleanup_tx_tstamp;
3657
3658 return NETDEV_TX_OK;
3659
3660out_drop:
3661 i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring);
3662 dev_kfree_skb_any(first->skb);
3663 first->skb = NULL;
3664cleanup_tx_tstamp:
3665 if (unlikely(tx_flags & I40E_TX_FLAGS_TSYN)) {
3666 struct i40e_pf *pf = i40e_netdev_to_pf(tx_ring->netdev);
3667
3668 dev_kfree_skb_any(pf->ptp_tx_skb);
3669 pf->ptp_tx_skb = NULL;
3670 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
3671 }
3672
3673 return NETDEV_TX_OK;
3674}
3675
3676/**
3677 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
3678 * @skb: send buffer
3679 * @netdev: network interface device structure
3680 *
3681 * Returns NETDEV_TX_OK if sent, else an error code
3682 **/
3683netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3684{
3685 struct i40e_netdev_priv *np = netdev_priv(netdev);
3686 struct i40e_vsi *vsi = np->vsi;
3687 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
3688
3689 /* hardware can't handle really short frames, hardware padding works
3690 * beyond this point
3691 */
3692 if (skb_put_padto(skb, I40E_MIN_TX_LEN))
3693 return NETDEV_TX_OK;
3694
3695 return i40e_xmit_frame_ring(skb, tx_ring);
3696}
3697
3698/**
3699 * i40e_xdp_xmit - Implements ndo_xdp_xmit
3700 * @dev: netdev
3701 * @xdp: XDP buffer
3702 *
3703 * Returns number of frames successfully sent. Frames that fail are
3704 * free'ed via XDP return API.
3705 *
3706 * For error cases, a negative errno code is returned and no-frames
3707 * are transmitted (caller must handle freeing frames).
3708 **/
3709int i40e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
3710 u32 flags)
3711{
3712 struct i40e_netdev_priv *np = netdev_priv(dev);
3713 unsigned int queue_index = smp_processor_id();
3714 struct i40e_vsi *vsi = np->vsi;
3715 struct i40e_pf *pf = vsi->back;
3716 struct i40e_ring *xdp_ring;
3717 int drops = 0;
3718 int i;
3719
3720 if (test_bit(__I40E_VSI_DOWN, vsi->state))
3721 return -ENETDOWN;
3722
3723 if (!i40e_enabled_xdp_vsi(vsi) || queue_index >= vsi->num_queue_pairs ||
3724 test_bit(__I40E_CONFIG_BUSY, pf->state))
3725 return -ENXIO;
3726
3727 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
3728 return -EINVAL;
3729
3730 xdp_ring = vsi->xdp_rings[queue_index];
3731
3732 for (i = 0; i < n; i++) {
3733 struct xdp_frame *xdpf = frames[i];
3734 int err;
3735
3736 err = i40e_xmit_xdp_ring(xdpf, xdp_ring);
3737 if (err != I40E_XDP_TX) {
3738 xdp_return_frame_rx_napi(xdpf);
3739 drops++;
3740 }
3741 }
3742
3743 if (unlikely(flags & XDP_XMIT_FLUSH))
3744 i40e_xdp_ring_update_tail(xdp_ring);
3745
3746 return n - drops;
3747}