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1/*
2 * arch/arm/include/asm/io.h
3 *
4 * Copyright (C) 1996-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Modifications:
11 * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
12 * constant addresses and variable addresses.
13 * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
14 * specific IO header files.
15 * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
16 * 04-Apr-1999 PJB Added check_signature.
17 * 12-Dec-1999 RMK More cleanups
18 * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
19 * 05-Oct-2004 BJD Moved memory string functions to use void __iomem
20 */
21#ifndef __ASM_ARM_IO_H
22#define __ASM_ARM_IO_H
23
24#ifdef __KERNEL__
25
26#include <linux/string.h>
27#include <linux/types.h>
28#include <linux/blk_types.h>
29#include <asm/byteorder.h>
30#include <asm/memory.h>
31#include <asm-generic/pci_iomap.h>
32#include <xen/xen.h>
33
34/*
35 * ISA I/O bus memory addresses are 1:1 with the physical address.
36 */
37#define isa_virt_to_bus virt_to_phys
38#define isa_page_to_bus page_to_phys
39#define isa_bus_to_virt phys_to_virt
40
41/*
42 * Atomic MMIO-wide IO modify
43 */
44extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set);
45extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set);
46
47/*
48 * Generic IO read/write. These perform native-endian accesses. Note
49 * that some architectures will want to re-define __raw_{read,write}w.
50 */
51void __raw_writesb(volatile void __iomem *addr, const void *data, int bytelen);
52void __raw_writesw(volatile void __iomem *addr, const void *data, int wordlen);
53void __raw_writesl(volatile void __iomem *addr, const void *data, int longlen);
54
55void __raw_readsb(const volatile void __iomem *addr, void *data, int bytelen);
56void __raw_readsw(const volatile void __iomem *addr, void *data, int wordlen);
57void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen);
58
59#if __LINUX_ARM_ARCH__ < 6
60/*
61 * Half-word accesses are problematic with RiscPC due to limitations of
62 * the bus. Rather than special-case the machine, just let the compiler
63 * generate the access for CPUs prior to ARMv6.
64 */
65#define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
66#define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
67#else
68/*
69 * When running under a hypervisor, we want to avoid I/O accesses with
70 * writeback addressing modes as these incur a significant performance
71 * overhead (the address generation must be emulated in software).
72 */
73#define __raw_writew __raw_writew
74static inline void __raw_writew(u16 val, volatile void __iomem *addr)
75{
76 asm volatile("strh %1, %0"
77 : : "Q" (*(volatile u16 __force *)addr), "r" (val));
78}
79
80#define __raw_readw __raw_readw
81static inline u16 __raw_readw(const volatile void __iomem *addr)
82{
83 u16 val;
84 asm volatile("ldrh %0, %1"
85 : "=r" (val)
86 : "Q" (*(volatile u16 __force *)addr));
87 return val;
88}
89#endif
90
91#define __raw_writeb __raw_writeb
92static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
93{
94 asm volatile("strb %1, %0"
95 : : "Qo" (*(volatile u8 __force *)addr), "r" (val));
96}
97
98#define __raw_writel __raw_writel
99static inline void __raw_writel(u32 val, volatile void __iomem *addr)
100{
101 asm volatile("str %1, %0"
102 : : "Qo" (*(volatile u32 __force *)addr), "r" (val));
103}
104
105#define __raw_readb __raw_readb
106static inline u8 __raw_readb(const volatile void __iomem *addr)
107{
108 u8 val;
109 asm volatile("ldrb %0, %1"
110 : "=r" (val)
111 : "Qo" (*(volatile u8 __force *)addr));
112 return val;
113}
114
115#define __raw_readl __raw_readl
116static inline u32 __raw_readl(const volatile void __iomem *addr)
117{
118 u32 val;
119 asm volatile("ldr %0, %1"
120 : "=r" (val)
121 : "Qo" (*(volatile u32 __force *)addr));
122 return val;
123}
124
125/*
126 * Architecture ioremap implementation.
127 */
128#define MT_DEVICE 0
129#define MT_DEVICE_NONSHARED 1
130#define MT_DEVICE_CACHED 2
131#define MT_DEVICE_WC 3
132/*
133 * types 4 onwards can be found in asm/mach/map.h and are undefined
134 * for ioremap
135 */
136
137/*
138 * __arm_ioremap takes CPU physical address.
139 * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
140 * The _caller variety takes a __builtin_return_address(0) value for
141 * /proc/vmalloc to use - and should only be used in non-inline functions.
142 */
143extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int,
144 void *);
145extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
146extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
147extern void __iounmap(volatile void __iomem *addr);
148
149extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
150 unsigned int, void *);
151extern void (*arch_iounmap)(volatile void __iomem *);
152
153/*
154 * Bad read/write accesses...
155 */
156extern void __readwrite_bug(const char *fn);
157
158/*
159 * A typesafe __io() helper
160 */
161static inline void __iomem *__typesafe_io(unsigned long addr)
162{
163 return (void __iomem *)addr;
164}
165
166#define IOMEM(x) ((void __force __iomem *)(x))
167
168/* IO barriers */
169#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
170#include <asm/barrier.h>
171#define __iormb() rmb()
172#define __iowmb() wmb()
173#else
174#define __iormb() do { } while (0)
175#define __iowmb() do { } while (0)
176#endif
177
178/* PCI fixed i/o mapping */
179#define PCI_IO_VIRT_BASE 0xfee00000
180#define PCI_IOBASE ((void __iomem *)PCI_IO_VIRT_BASE)
181
182#if defined(CONFIG_PCI)
183void pci_ioremap_set_mem_type(int mem_type);
184#else
185static inline void pci_ioremap_set_mem_type(int mem_type) {}
186#endif
187
188extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
189
190/*
191 * Now, pick up the machine-defined IO definitions
192 */
193#ifdef CONFIG_NEED_MACH_IO_H
194#include <mach/io.h>
195#elif defined(CONFIG_PCI)
196#define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
197#define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
198#else
199#define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT)
200#endif
201
202/*
203 * This is the limit of PC card/PCI/ISA IO space, which is by default
204 * 64K if we have PC card, PCI or ISA support. Otherwise, default to
205 * zero to prevent ISA/PCI drivers claiming IO space (and potentially
206 * oopsing.)
207 *
208 * Only set this larger if you really need inb() et.al. to operate over
209 * a larger address space. Note that SOC_COMMON ioremaps each sockets
210 * IO space area, and so inb() et.al. must be defined to operate as per
211 * readb() et.al. on such platforms.
212 */
213#ifndef IO_SPACE_LIMIT
214#if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE)
215#define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
216#elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD)
217#define IO_SPACE_LIMIT ((resource_size_t)0xffff)
218#else
219#define IO_SPACE_LIMIT ((resource_size_t)0)
220#endif
221#endif
222
223/*
224 * IO port access primitives
225 * -------------------------
226 *
227 * The ARM doesn't have special IO access instructions; all IO is memory
228 * mapped. Note that these are defined to perform little endian accesses
229 * only. Their primary purpose is to access PCI and ISA peripherals.
230 *
231 * Note that for a big endian machine, this implies that the following
232 * big endian mode connectivity is in place, as described by numerous
233 * ARM documents:
234 *
235 * PCI: D0-D7 D8-D15 D16-D23 D24-D31
236 * ARM: D24-D31 D16-D23 D8-D15 D0-D7
237 *
238 * The machine specific io.h include defines __io to translate an "IO"
239 * address to a memory address.
240 *
241 * Note that we prevent GCC re-ordering or caching values in expressions
242 * by introducing sequence points into the in*() definitions. Note that
243 * __raw_* do not guarantee this behaviour.
244 *
245 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
246 */
247#ifdef __io
248#define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
249#define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
250 cpu_to_le16(v),__io(p)); })
251#define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
252 cpu_to_le32(v),__io(p)); })
253
254#define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
255#define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
256 __raw_readw(__io(p))); __iormb(); __v; })
257#define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
258 __raw_readl(__io(p))); __iormb(); __v; })
259
260#define outsb(p,d,l) __raw_writesb(__io(p),d,l)
261#define outsw(p,d,l) __raw_writesw(__io(p),d,l)
262#define outsl(p,d,l) __raw_writesl(__io(p),d,l)
263
264#define insb(p,d,l) __raw_readsb(__io(p),d,l)
265#define insw(p,d,l) __raw_readsw(__io(p),d,l)
266#define insl(p,d,l) __raw_readsl(__io(p),d,l)
267#endif
268
269/*
270 * String version of IO memory access ops:
271 */
272extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
273extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
274extern void _memset_io(volatile void __iomem *, int, size_t);
275
276#define mmiowb()
277
278/*
279 * Memory access primitives
280 * ------------------------
281 *
282 * These perform PCI memory accesses via an ioremap region. They don't
283 * take an address as such, but a cookie.
284 *
285 * Again, this are defined to perform little endian accesses. See the
286 * IO port primitives for more information.
287 */
288#ifndef readl
289#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
290#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
291 __raw_readw(c)); __r; })
292#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
293 __raw_readl(c)); __r; })
294
295#define writeb_relaxed(v,c) __raw_writeb(v,c)
296#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
297#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
298
299#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
300#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
301#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
302
303#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
304#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
305#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
306
307#define readsb(p,d,l) __raw_readsb(p,d,l)
308#define readsw(p,d,l) __raw_readsw(p,d,l)
309#define readsl(p,d,l) __raw_readsl(p,d,l)
310
311#define writesb(p,d,l) __raw_writesb(p,d,l)
312#define writesw(p,d,l) __raw_writesw(p,d,l)
313#define writesl(p,d,l) __raw_writesl(p,d,l)
314
315#ifndef __ARMBE__
316static inline void memset_io(volatile void __iomem *dst, unsigned c,
317 size_t count)
318{
319 extern void mmioset(void *, unsigned int, size_t);
320 mmioset((void __force *)dst, c, count);
321}
322#define memset_io(dst,c,count) memset_io(dst,c,count)
323
324static inline void memcpy_fromio(void *to, const volatile void __iomem *from,
325 size_t count)
326{
327 extern void mmiocpy(void *, const void *, size_t);
328 mmiocpy(to, (const void __force *)from, count);
329}
330#define memcpy_fromio(to,from,count) memcpy_fromio(to,from,count)
331
332static inline void memcpy_toio(volatile void __iomem *to, const void *from,
333 size_t count)
334{
335 extern void mmiocpy(void *, const void *, size_t);
336 mmiocpy((void __force *)to, from, count);
337}
338#define memcpy_toio(to,from,count) memcpy_toio(to,from,count)
339
340#else
341#define memset_io(c,v,l) _memset_io(c,(v),(l))
342#define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l))
343#define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l))
344#endif
345
346#endif /* readl */
347
348/*
349 * ioremap() and friends.
350 *
351 * ioremap() takes a resource address, and size. Due to the ARM memory
352 * types, it is important to use the correct ioremap() function as each
353 * mapping has specific properties.
354 *
355 * Function Memory type Cacheability Cache hint
356 * ioremap() Device n/a n/a
357 * ioremap_nocache() Device n/a n/a
358 * ioremap_cache() Normal Writeback Read allocate
359 * ioremap_wc() Normal Non-cacheable n/a
360 * ioremap_wt() Normal Non-cacheable n/a
361 *
362 * All device mappings have the following properties:
363 * - no access speculation
364 * - no repetition (eg, on return from an exception)
365 * - number, order and size of accesses are maintained
366 * - unaligned accesses are "unpredictable"
367 * - writes may be delayed before they hit the endpoint device
368 *
369 * ioremap_nocache() is the same as ioremap() as there are too many device
370 * drivers using this for device registers, and documentation which tells
371 * people to use it for such for this to be any different. This is not a
372 * safe fallback for memory-like mappings, or memory regions where the
373 * compiler may generate unaligned accesses - eg, via inlining its own
374 * memcpy.
375 *
376 * All normal memory mappings have the following properties:
377 * - reads can be repeated with no side effects
378 * - repeated reads return the last value written
379 * - reads can fetch additional locations without side effects
380 * - writes can be repeated (in certain cases) with no side effects
381 * - writes can be merged before accessing the target
382 * - unaligned accesses can be supported
383 * - ordering is not guaranteed without explicit dependencies or barrier
384 * instructions
385 * - writes may be delayed before they hit the endpoint memory
386 *
387 * The cache hint is only a performance hint: CPUs may alias these hints.
388 * Eg, a CPU not implementing read allocate but implementing write allocate
389 * will provide a write allocate mapping instead.
390 */
391void __iomem *ioremap(resource_size_t res_cookie, size_t size);
392#define ioremap ioremap
393#define ioremap_nocache ioremap
394
395void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size);
396#define ioremap_cache ioremap_cache
397
398void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size);
399#define ioremap_wc ioremap_wc
400#define ioremap_wt ioremap_wc
401
402void iounmap(volatile void __iomem *iomem_cookie);
403#define iounmap iounmap
404
405/*
406 * io{read,write}{16,32}be() macros
407 */
408#define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
409#define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
410
411#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
412#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
413
414#ifndef ioport_map
415#define ioport_map ioport_map
416extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
417#endif
418#ifndef ioport_unmap
419#define ioport_unmap ioport_unmap
420extern void ioport_unmap(void __iomem *addr);
421#endif
422
423struct pci_dev;
424
425#define pci_iounmap pci_iounmap
426extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
427
428/*
429 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
430 * access
431 */
432#define xlate_dev_mem_ptr(p) __va(p)
433
434/*
435 * Convert a virtual cached pointer to an uncached pointer
436 */
437#define xlate_dev_kmem_ptr(p) p
438
439#include <asm-generic/io.h>
440
441/*
442 * can the hardware map this into one segment or not, given no other
443 * constraints.
444 */
445#define BIOVEC_MERGEABLE(vec1, vec2) \
446 ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
447
448struct bio_vec;
449extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
450 const struct bio_vec *vec2);
451#define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \
452 (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \
453 (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
454
455#ifdef CONFIG_MMU
456#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
457extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
458extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
459extern int devmem_is_allowed(unsigned long pfn);
460#endif
461
462/*
463 * Register ISA memory and port locations for glibc iopl/inb/outb
464 * emulation.
465 */
466extern void register_isa_ports(unsigned int mmio, unsigned int io,
467 unsigned int io_shift);
468
469#endif /* __KERNEL__ */
470#endif /* __ASM_ARM_IO_H */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * arch/arm/include/asm/io.h
4 *
5 * Copyright (C) 1996-2000 Russell King
6 *
7 * Modifications:
8 * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
9 * constant addresses and variable addresses.
10 * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
11 * specific IO header files.
12 * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
13 * 04-Apr-1999 PJB Added check_signature.
14 * 12-Dec-1999 RMK More cleanups
15 * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
16 * 05-Oct-2004 BJD Moved memory string functions to use void __iomem
17 */
18#ifndef __ASM_ARM_IO_H
19#define __ASM_ARM_IO_H
20
21#ifdef __KERNEL__
22
23#include <linux/string.h>
24#include <linux/types.h>
25#include <asm/byteorder.h>
26#include <asm/memory.h>
27#include <asm-generic/pci_iomap.h>
28
29/*
30 * ISA I/O bus memory addresses are 1:1 with the physical address.
31 */
32#define isa_virt_to_bus virt_to_phys
33#define isa_bus_to_virt phys_to_virt
34
35/*
36 * Atomic MMIO-wide IO modify
37 */
38extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set);
39extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set);
40
41/*
42 * Generic IO read/write. These perform native-endian accesses. Note
43 * that some architectures will want to re-define __raw_{read,write}w.
44 */
45void __raw_writesb(volatile void __iomem *addr, const void *data, int bytelen);
46void __raw_writesw(volatile void __iomem *addr, const void *data, int wordlen);
47void __raw_writesl(volatile void __iomem *addr, const void *data, int longlen);
48
49void __raw_readsb(const volatile void __iomem *addr, void *data, int bytelen);
50void __raw_readsw(const volatile void __iomem *addr, void *data, int wordlen);
51void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen);
52
53#if __LINUX_ARM_ARCH__ < 6
54/*
55 * Half-word accesses are problematic with RiscPC due to limitations of
56 * the bus. Rather than special-case the machine, just let the compiler
57 * generate the access for CPUs prior to ARMv6.
58 */
59#define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
60#define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
61#else
62/*
63 * When running under a hypervisor, we want to avoid I/O accesses with
64 * writeback addressing modes as these incur a significant performance
65 * overhead (the address generation must be emulated in software).
66 */
67#define __raw_writew __raw_writew
68static inline void __raw_writew(u16 val, volatile void __iomem *addr)
69{
70 asm volatile("strh %1, %0"
71 : : "Q" (*(volatile u16 __force *)addr), "r" (val));
72}
73
74#define __raw_readw __raw_readw
75static inline u16 __raw_readw(const volatile void __iomem *addr)
76{
77 u16 val;
78 asm volatile("ldrh %0, %1"
79 : "=r" (val)
80 : "Q" (*(volatile u16 __force *)addr));
81 return val;
82}
83#endif
84
85#define __raw_writeb __raw_writeb
86static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
87{
88 asm volatile("strb %1, %0"
89 : : "Qo" (*(volatile u8 __force *)addr), "r" (val));
90}
91
92#define __raw_writel __raw_writel
93static inline void __raw_writel(u32 val, volatile void __iomem *addr)
94{
95 asm volatile("str %1, %0"
96 : : "Qo" (*(volatile u32 __force *)addr), "r" (val));
97}
98
99#define __raw_readb __raw_readb
100static inline u8 __raw_readb(const volatile void __iomem *addr)
101{
102 u8 val;
103 asm volatile("ldrb %0, %1"
104 : "=r" (val)
105 : "Qo" (*(volatile u8 __force *)addr));
106 return val;
107}
108
109#define __raw_readl __raw_readl
110static inline u32 __raw_readl(const volatile void __iomem *addr)
111{
112 u32 val;
113 asm volatile("ldr %0, %1"
114 : "=r" (val)
115 : "Qo" (*(volatile u32 __force *)addr));
116 return val;
117}
118
119/*
120 * Architecture ioremap implementation.
121 */
122#define MT_DEVICE 0
123#define MT_DEVICE_NONSHARED 1
124#define MT_DEVICE_CACHED 2
125#define MT_DEVICE_WC 3
126/*
127 * types 4 onwards can be found in asm/mach/map.h and are undefined
128 * for ioremap
129 */
130
131/*
132 * __arm_ioremap takes CPU physical address.
133 * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
134 * The _caller variety takes a __builtin_return_address(0) value for
135 * /proc/vmalloc to use - and should only be used in non-inline functions.
136 */
137extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int,
138 void *);
139extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
140extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
141extern void __iounmap(volatile void __iomem *addr);
142
143extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
144 unsigned int, void *);
145extern void (*arch_iounmap)(volatile void __iomem *);
146
147/*
148 * Bad read/write accesses...
149 */
150extern void __readwrite_bug(const char *fn);
151
152/*
153 * A typesafe __io() helper
154 */
155static inline void __iomem *__typesafe_io(unsigned long addr)
156{
157 return (void __iomem *)addr;
158}
159
160#define IOMEM(x) ((void __force __iomem *)(x))
161
162/* IO barriers */
163#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
164#include <asm/barrier.h>
165#define __iormb() rmb()
166#define __iowmb() wmb()
167#else
168#define __iormb() do { } while (0)
169#define __iowmb() do { } while (0)
170#endif
171
172/* PCI fixed i/o mapping */
173#define PCI_IO_VIRT_BASE 0xfee00000
174#define PCI_IOBASE ((void __iomem *)PCI_IO_VIRT_BASE)
175
176#if defined(CONFIG_PCI)
177void pci_ioremap_set_mem_type(int mem_type);
178#else
179static inline void pci_ioremap_set_mem_type(int mem_type) {}
180#endif
181
182extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
183
184/*
185 * PCI configuration space mapping function.
186 *
187 * The PCI specification does not allow configuration write
188 * transactions to be posted. Add an arch specific
189 * pci_remap_cfgspace() definition that is implemented
190 * through strongly ordered memory mappings.
191 */
192#define pci_remap_cfgspace pci_remap_cfgspace
193void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size);
194/*
195 * Now, pick up the machine-defined IO definitions
196 */
197#ifdef CONFIG_NEED_MACH_IO_H
198#include <mach/io.h>
199#elif defined(CONFIG_PCI)
200#define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
201#define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
202#else
203#define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT)
204#endif
205
206/*
207 * This is the limit of PC card/PCI/ISA IO space, which is by default
208 * 64K if we have PC card, PCI or ISA support. Otherwise, default to
209 * zero to prevent ISA/PCI drivers claiming IO space (and potentially
210 * oopsing.)
211 *
212 * Only set this larger if you really need inb() et.al. to operate over
213 * a larger address space. Note that SOC_COMMON ioremaps each sockets
214 * IO space area, and so inb() et.al. must be defined to operate as per
215 * readb() et.al. on such platforms.
216 */
217#ifndef IO_SPACE_LIMIT
218#if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE)
219#define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
220#elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD)
221#define IO_SPACE_LIMIT ((resource_size_t)0xffff)
222#else
223#define IO_SPACE_LIMIT ((resource_size_t)0)
224#endif
225#endif
226
227/*
228 * IO port access primitives
229 * -------------------------
230 *
231 * The ARM doesn't have special IO access instructions; all IO is memory
232 * mapped. Note that these are defined to perform little endian accesses
233 * only. Their primary purpose is to access PCI and ISA peripherals.
234 *
235 * Note that for a big endian machine, this implies that the following
236 * big endian mode connectivity is in place, as described by numerous
237 * ARM documents:
238 *
239 * PCI: D0-D7 D8-D15 D16-D23 D24-D31
240 * ARM: D24-D31 D16-D23 D8-D15 D0-D7
241 *
242 * The machine specific io.h include defines __io to translate an "IO"
243 * address to a memory address.
244 *
245 * Note that we prevent GCC re-ordering or caching values in expressions
246 * by introducing sequence points into the in*() definitions. Note that
247 * __raw_* do not guarantee this behaviour.
248 *
249 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
250 */
251#ifdef __io
252#define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
253#define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
254 cpu_to_le16(v),__io(p)); })
255#define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
256 cpu_to_le32(v),__io(p)); })
257
258#define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
259#define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
260 __raw_readw(__io(p))); __iormb(); __v; })
261#define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
262 __raw_readl(__io(p))); __iormb(); __v; })
263
264#define outsb(p,d,l) __raw_writesb(__io(p),d,l)
265#define outsw(p,d,l) __raw_writesw(__io(p),d,l)
266#define outsl(p,d,l) __raw_writesl(__io(p),d,l)
267
268#define insb(p,d,l) __raw_readsb(__io(p),d,l)
269#define insw(p,d,l) __raw_readsw(__io(p),d,l)
270#define insl(p,d,l) __raw_readsl(__io(p),d,l)
271#endif
272
273/*
274 * String version of IO memory access ops:
275 */
276extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
277extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
278extern void _memset_io(volatile void __iomem *, int, size_t);
279
280/*
281 * Memory access primitives
282 * ------------------------
283 *
284 * These perform PCI memory accesses via an ioremap region. They don't
285 * take an address as such, but a cookie.
286 *
287 * Again, these are defined to perform little endian accesses. See the
288 * IO port primitives for more information.
289 */
290#ifndef readl
291#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
292#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
293 __raw_readw(c)); __r; })
294#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
295 __raw_readl(c)); __r; })
296
297#define writeb_relaxed(v,c) __raw_writeb(v,c)
298#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
299#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
300
301#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
302#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
303#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
304
305#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
306#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
307#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
308
309#define readsb(p,d,l) __raw_readsb(p,d,l)
310#define readsw(p,d,l) __raw_readsw(p,d,l)
311#define readsl(p,d,l) __raw_readsl(p,d,l)
312
313#define writesb(p,d,l) __raw_writesb(p,d,l)
314#define writesw(p,d,l) __raw_writesw(p,d,l)
315#define writesl(p,d,l) __raw_writesl(p,d,l)
316
317#ifndef __ARMBE__
318static inline void memset_io(volatile void __iomem *dst, unsigned c,
319 size_t count)
320{
321 extern void mmioset(void *, unsigned int, size_t);
322 mmioset((void __force *)dst, c, count);
323}
324#define memset_io(dst,c,count) memset_io(dst,c,count)
325
326static inline void memcpy_fromio(void *to, const volatile void __iomem *from,
327 size_t count)
328{
329 extern void mmiocpy(void *, const void *, size_t);
330 mmiocpy(to, (const void __force *)from, count);
331}
332#define memcpy_fromio(to,from,count) memcpy_fromio(to,from,count)
333
334static inline void memcpy_toio(volatile void __iomem *to, const void *from,
335 size_t count)
336{
337 extern void mmiocpy(void *, const void *, size_t);
338 mmiocpy((void __force *)to, from, count);
339}
340#define memcpy_toio(to,from,count) memcpy_toio(to,from,count)
341
342#else
343#define memset_io(c,v,l) _memset_io(c,(v),(l))
344#define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l))
345#define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l))
346#endif
347
348#endif /* readl */
349
350/*
351 * ioremap() and friends.
352 *
353 * ioremap() takes a resource address, and size. Due to the ARM memory
354 * types, it is important to use the correct ioremap() function as each
355 * mapping has specific properties.
356 *
357 * Function Memory type Cacheability Cache hint
358 * ioremap() Device n/a n/a
359 * ioremap_cache() Normal Writeback Read allocate
360 * ioremap_wc() Normal Non-cacheable n/a
361 * ioremap_wt() Normal Non-cacheable n/a
362 *
363 * All device mappings have the following properties:
364 * - no access speculation
365 * - no repetition (eg, on return from an exception)
366 * - number, order and size of accesses are maintained
367 * - unaligned accesses are "unpredictable"
368 * - writes may be delayed before they hit the endpoint device
369 *
370 * All normal memory mappings have the following properties:
371 * - reads can be repeated with no side effects
372 * - repeated reads return the last value written
373 * - reads can fetch additional locations without side effects
374 * - writes can be repeated (in certain cases) with no side effects
375 * - writes can be merged before accessing the target
376 * - unaligned accesses can be supported
377 * - ordering is not guaranteed without explicit dependencies or barrier
378 * instructions
379 * - writes may be delayed before they hit the endpoint memory
380 *
381 * The cache hint is only a performance hint: CPUs may alias these hints.
382 * Eg, a CPU not implementing read allocate but implementing write allocate
383 * will provide a write allocate mapping instead.
384 */
385void __iomem *ioremap(resource_size_t res_cookie, size_t size);
386#define ioremap ioremap
387
388/*
389 * Do not use ioremap_cache for mapping memory. Use memremap instead.
390 */
391void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size);
392#define ioremap_cache ioremap_cache
393
394void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size);
395#define ioremap_wc ioremap_wc
396#define ioremap_wt ioremap_wc
397
398void iounmap(volatile void __iomem *iomem_cookie);
399#define iounmap iounmap
400
401void *arch_memremap_wb(phys_addr_t phys_addr, size_t size);
402#define arch_memremap_wb arch_memremap_wb
403
404/*
405 * io{read,write}{16,32}be() macros
406 */
407#define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
408#define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
409
410#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
411#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
412
413#ifndef ioport_map
414#define ioport_map ioport_map
415extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
416#endif
417#ifndef ioport_unmap
418#define ioport_unmap ioport_unmap
419extern void ioport_unmap(void __iomem *addr);
420#endif
421
422struct pci_dev;
423
424#define pci_iounmap pci_iounmap
425extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
426
427/*
428 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
429 * access
430 */
431#define xlate_dev_mem_ptr(p) __va(p)
432
433/*
434 * Convert a virtual cached pointer to an uncached pointer
435 */
436#define xlate_dev_kmem_ptr(p) p
437
438#include <asm-generic/io.h>
439
440#ifdef CONFIG_MMU
441#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
442extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
443extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
444extern int devmem_is_allowed(unsigned long pfn);
445#endif
446
447/*
448 * Register ISA memory and port locations for glibc iopl/inb/outb
449 * emulation.
450 */
451extern void register_isa_ports(unsigned int mmio, unsigned int io,
452 unsigned int io_shift);
453
454#endif /* __KERNEL__ */
455#endif /* __ASM_ARM_IO_H */