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1/*
2 * An SPI driver for the Philips PCF2123 RTC
3 * Copyright 2009 Cyber Switching, Inc.
4 *
5 * Author: Chris Verges <chrisv@cyberswitching.com>
6 * Maintainers: http://www.cyberswitching.com
7 *
8 * based on the RS5C348 driver in this same directory.
9 *
10 * Thanks to Christian Pellegrin <chripell@fsfe.org> for
11 * the sysfs contributions to this driver.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 *
17 * Please note that the CS is active high, so platform data
18 * should look something like:
19 *
20 * static struct spi_board_info ek_spi_devices[] = {
21 * ...
22 * {
23 * .modalias = "rtc-pcf2123",
24 * .chip_select = 1,
25 * .controller_data = (void *)AT91_PIN_PA10,
26 * .max_speed_hz = 1000 * 1000,
27 * .mode = SPI_CS_HIGH,
28 * .bus_num = 0,
29 * },
30 * ...
31 *};
32 *
33 */
34
35#include <linux/bcd.h>
36#include <linux/delay.h>
37#include <linux/device.h>
38#include <linux/errno.h>
39#include <linux/init.h>
40#include <linux/kernel.h>
41#include <linux/of.h>
42#include <linux/string.h>
43#include <linux/slab.h>
44#include <linux/rtc.h>
45#include <linux/spi/spi.h>
46#include <linux/module.h>
47#include <linux/sysfs.h>
48
49#define DRV_VERSION "0.6"
50
51/* REGISTERS */
52#define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */
53#define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */
54#define PCF2123_REG_SC (0x02) /* datetime */
55#define PCF2123_REG_MN (0x03)
56#define PCF2123_REG_HR (0x04)
57#define PCF2123_REG_DM (0x05)
58#define PCF2123_REG_DW (0x06)
59#define PCF2123_REG_MO (0x07)
60#define PCF2123_REG_YR (0x08)
61#define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */
62#define PCF2123_REG_ALRM_HR (0x0a)
63#define PCF2123_REG_ALRM_DM (0x0b)
64#define PCF2123_REG_ALRM_DW (0x0c)
65#define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */
66#define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */
67#define PCF2123_REG_CTDWN_TMR (0x0f)
68
69/* PCF2123_REG_CTRL1 BITS */
70#define CTRL1_CLEAR (0) /* Clear */
71#define CTRL1_CORR_INT BIT(1) /* Correction irq enable */
72#define CTRL1_12_HOUR BIT(2) /* 12 hour time */
73#define CTRL1_SW_RESET (BIT(3) | BIT(4) | BIT(6)) /* Software reset */
74#define CTRL1_STOP BIT(5) /* Stop the clock */
75#define CTRL1_EXT_TEST BIT(7) /* External clock test mode */
76
77/* PCF2123_REG_CTRL2 BITS */
78#define CTRL2_TIE BIT(0) /* Countdown timer irq enable */
79#define CTRL2_AIE BIT(1) /* Alarm irq enable */
80#define CTRL2_TF BIT(2) /* Countdown timer flag */
81#define CTRL2_AF BIT(3) /* Alarm flag */
82#define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */
83#define CTRL2_MSF BIT(5) /* Minute or second irq flag */
84#define CTRL2_SI BIT(6) /* Second irq enable */
85#define CTRL2_MI BIT(7) /* Minute irq enable */
86
87/* PCF2123_REG_SC BITS */
88#define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */
89
90/* PCF2123_REG_ALRM_XX BITS */
91#define ALRM_ENABLE BIT(7) /* MN, HR, DM, or DW alarm enable */
92
93/* PCF2123_REG_TMR_CLKOUT BITS */
94#define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */
95#define CD_TMR_64HZ (1) /* 64 Hz countdown timer */
96#define CD_TMR_1HZ (2) /* 1 Hz countdown timer */
97#define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */
98#define CD_TMR_TE BIT(3) /* Countdown timer enable */
99
100/* PCF2123_REG_OFFSET BITS */
101#define OFFSET_SIGN_BIT BIT(6) /* 2's complement sign bit */
102#define OFFSET_COARSE BIT(7) /* Coarse mode offset */
103#define OFFSET_STEP (2170) /* Offset step in parts per billion */
104
105/* READ/WRITE ADDRESS BITS */
106#define PCF2123_WRITE BIT(4)
107#define PCF2123_READ (BIT(4) | BIT(7))
108
109
110static struct spi_driver pcf2123_driver;
111
112struct pcf2123_sysfs_reg {
113 struct device_attribute attr;
114 char name[2];
115};
116
117struct pcf2123_plat_data {
118 struct rtc_device *rtc;
119 struct pcf2123_sysfs_reg regs[16];
120};
121
122/*
123 * Causes a 30 nanosecond delay to ensure that the PCF2123 chip select
124 * is released properly after an SPI write. This function should be
125 * called after EVERY read/write call over SPI.
126 */
127static inline void pcf2123_delay_trec(void)
128{
129 ndelay(30);
130}
131
132static int pcf2123_read(struct device *dev, u8 reg, u8 *rxbuf, size_t size)
133{
134 struct spi_device *spi = to_spi_device(dev);
135 int ret;
136
137 reg |= PCF2123_READ;
138 ret = spi_write_then_read(spi, ®, 1, rxbuf, size);
139 pcf2123_delay_trec();
140
141 return ret;
142}
143
144static int pcf2123_write(struct device *dev, u8 *txbuf, size_t size)
145{
146 struct spi_device *spi = to_spi_device(dev);
147 int ret;
148
149 txbuf[0] |= PCF2123_WRITE;
150 ret = spi_write(spi, txbuf, size);
151 pcf2123_delay_trec();
152
153 return ret;
154}
155
156static int pcf2123_write_reg(struct device *dev, u8 reg, u8 val)
157{
158 u8 txbuf[2];
159
160 txbuf[0] = reg;
161 txbuf[1] = val;
162 return pcf2123_write(dev, txbuf, sizeof(txbuf));
163}
164
165static ssize_t pcf2123_show(struct device *dev, struct device_attribute *attr,
166 char *buffer)
167{
168 struct pcf2123_sysfs_reg *r;
169 u8 rxbuf[1];
170 unsigned long reg;
171 int ret;
172
173 r = container_of(attr, struct pcf2123_sysfs_reg, attr);
174
175 ret = kstrtoul(r->name, 16, ®);
176 if (ret)
177 return ret;
178
179 ret = pcf2123_read(dev, reg, rxbuf, 1);
180 if (ret < 0)
181 return -EIO;
182
183 return sprintf(buffer, "0x%x\n", rxbuf[0]);
184}
185
186static ssize_t pcf2123_store(struct device *dev, struct device_attribute *attr,
187 const char *buffer, size_t count) {
188 struct pcf2123_sysfs_reg *r;
189 unsigned long reg;
190 unsigned long val;
191
192 int ret;
193
194 r = container_of(attr, struct pcf2123_sysfs_reg, attr);
195
196 ret = kstrtoul(r->name, 16, ®);
197 if (ret)
198 return ret;
199
200 ret = kstrtoul(buffer, 10, &val);
201 if (ret)
202 return ret;
203
204 pcf2123_write_reg(dev, reg, val);
205 if (ret < 0)
206 return -EIO;
207 return count;
208}
209
210static int pcf2123_read_offset(struct device *dev, long *offset)
211{
212 int ret;
213 s8 reg;
214
215 ret = pcf2123_read(dev, PCF2123_REG_OFFSET, ®, 1);
216 if (ret < 0)
217 return ret;
218
219 if (reg & OFFSET_COARSE)
220 reg <<= 1; /* multiply by 2 and sign extend */
221 else
222 reg |= (reg & OFFSET_SIGN_BIT) << 1; /* sign extend only */
223
224 *offset = ((long)reg) * OFFSET_STEP;
225
226 return 0;
227}
228
229/*
230 * The offset register is a 7 bit signed value with a coarse bit in bit 7.
231 * The main difference between the two is normal offset adjusts the first
232 * second of n minutes every other hour, with 61, 62 and 63 being shoved
233 * into the 60th minute.
234 * The coarse adjustment does the same, but every hour.
235 * the two overlap, with every even normal offset value corresponding
236 * to a coarse offset. Based on this algorithm, it seems that despite the
237 * name, coarse offset is a better fit for overlapping values.
238 */
239static int pcf2123_set_offset(struct device *dev, long offset)
240{
241 s8 reg;
242
243 if (offset > OFFSET_STEP * 127)
244 reg = 127;
245 else if (offset < OFFSET_STEP * -128)
246 reg = -128;
247 else
248 reg = (s8)((offset + (OFFSET_STEP >> 1)) / OFFSET_STEP);
249
250 /* choose fine offset only for odd values in the normal range */
251 if (reg & 1 && reg <= 63 && reg >= -64) {
252 /* Normal offset. Clear the coarse bit */
253 reg &= ~OFFSET_COARSE;
254 } else {
255 /* Coarse offset. Divide by 2 and set the coarse bit */
256 reg >>= 1;
257 reg |= OFFSET_COARSE;
258 }
259
260 return pcf2123_write_reg(dev, PCF2123_REG_OFFSET, reg);
261}
262
263static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm)
264{
265 u8 rxbuf[7];
266 int ret;
267
268 ret = pcf2123_read(dev, PCF2123_REG_SC, rxbuf, sizeof(rxbuf));
269 if (ret < 0)
270 return ret;
271
272 if (rxbuf[0] & OSC_HAS_STOPPED) {
273 dev_info(dev, "clock was stopped. Time is not valid\n");
274 return -EINVAL;
275 }
276
277 tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
278 tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
279 tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
280 tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
281 tm->tm_wday = rxbuf[4] & 0x07;
282 tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
283 tm->tm_year = bcd2bin(rxbuf[6]);
284 if (tm->tm_year < 70)
285 tm->tm_year += 100; /* assume we are in 1970...2069 */
286
287 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
288 "mday=%d, mon=%d, year=%d, wday=%d\n",
289 __func__,
290 tm->tm_sec, tm->tm_min, tm->tm_hour,
291 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
292
293 return rtc_valid_tm(tm);
294}
295
296static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm)
297{
298 u8 txbuf[8];
299 int ret;
300
301 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
302 "mday=%d, mon=%d, year=%d, wday=%d\n",
303 __func__,
304 tm->tm_sec, tm->tm_min, tm->tm_hour,
305 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
306
307 /* Stop the counter first */
308 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
309 if (ret < 0)
310 return ret;
311
312 /* Set the new time */
313 txbuf[0] = PCF2123_REG_SC;
314 txbuf[1] = bin2bcd(tm->tm_sec & 0x7F);
315 txbuf[2] = bin2bcd(tm->tm_min & 0x7F);
316 txbuf[3] = bin2bcd(tm->tm_hour & 0x3F);
317 txbuf[4] = bin2bcd(tm->tm_mday & 0x3F);
318 txbuf[5] = tm->tm_wday & 0x07;
319 txbuf[6] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
320 txbuf[7] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100);
321
322 ret = pcf2123_write(dev, txbuf, sizeof(txbuf));
323 if (ret < 0)
324 return ret;
325
326 /* Start the counter */
327 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
328 if (ret < 0)
329 return ret;
330
331 return 0;
332}
333
334static int pcf2123_reset(struct device *dev)
335{
336 int ret;
337 u8 rxbuf[2];
338
339 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
340 if (ret < 0)
341 return ret;
342
343 /* Stop the counter */
344 dev_dbg(dev, "stopping RTC\n");
345 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
346 if (ret < 0)
347 return ret;
348
349 /* See if the counter was actually stopped */
350 dev_dbg(dev, "checking for presence of RTC\n");
351 ret = pcf2123_read(dev, PCF2123_REG_CTRL1, rxbuf, sizeof(rxbuf));
352 if (ret < 0)
353 return ret;
354
355 dev_dbg(dev, "received data from RTC (0x%02X 0x%02X)\n",
356 rxbuf[0], rxbuf[1]);
357 if (!(rxbuf[0] & CTRL1_STOP))
358 return -ENODEV;
359
360 /* Start the counter */
361 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
362 if (ret < 0)
363 return ret;
364
365 return 0;
366}
367
368static const struct rtc_class_ops pcf2123_rtc_ops = {
369 .read_time = pcf2123_rtc_read_time,
370 .set_time = pcf2123_rtc_set_time,
371 .read_offset = pcf2123_read_offset,
372 .set_offset = pcf2123_set_offset,
373
374};
375
376static int pcf2123_probe(struct spi_device *spi)
377{
378 struct rtc_device *rtc;
379 struct rtc_time tm;
380 struct pcf2123_plat_data *pdata;
381 int ret, i;
382
383 pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data),
384 GFP_KERNEL);
385 if (!pdata)
386 return -ENOMEM;
387 spi->dev.platform_data = pdata;
388
389 ret = pcf2123_rtc_read_time(&spi->dev, &tm);
390 if (ret < 0) {
391 ret = pcf2123_reset(&spi->dev);
392 if (ret < 0) {
393 dev_err(&spi->dev, "chip not found\n");
394 goto kfree_exit;
395 }
396 }
397
398 dev_info(&spi->dev, "chip found, driver version " DRV_VERSION "\n");
399 dev_info(&spi->dev, "spiclk %u KHz.\n",
400 (spi->max_speed_hz + 500) / 1000);
401
402 /* Finalize the initialization */
403 rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name,
404 &pcf2123_rtc_ops, THIS_MODULE);
405
406 if (IS_ERR(rtc)) {
407 dev_err(&spi->dev, "failed to register.\n");
408 ret = PTR_ERR(rtc);
409 goto kfree_exit;
410 }
411
412 pdata->rtc = rtc;
413
414 for (i = 0; i < 16; i++) {
415 sysfs_attr_init(&pdata->regs[i].attr.attr);
416 sprintf(pdata->regs[i].name, "%1x", i);
417 pdata->regs[i].attr.attr.mode = S_IRUGO | S_IWUSR;
418 pdata->regs[i].attr.attr.name = pdata->regs[i].name;
419 pdata->regs[i].attr.show = pcf2123_show;
420 pdata->regs[i].attr.store = pcf2123_store;
421 ret = device_create_file(&spi->dev, &pdata->regs[i].attr);
422 if (ret) {
423 dev_err(&spi->dev, "Unable to create sysfs %s\n",
424 pdata->regs[i].name);
425 goto sysfs_exit;
426 }
427 }
428
429 return 0;
430
431sysfs_exit:
432 for (i--; i >= 0; i--)
433 device_remove_file(&spi->dev, &pdata->regs[i].attr);
434
435kfree_exit:
436 spi->dev.platform_data = NULL;
437 return ret;
438}
439
440static int pcf2123_remove(struct spi_device *spi)
441{
442 struct pcf2123_plat_data *pdata = dev_get_platdata(&spi->dev);
443 int i;
444
445 if (pdata) {
446 for (i = 0; i < 16; i++)
447 if (pdata->regs[i].name[0])
448 device_remove_file(&spi->dev,
449 &pdata->regs[i].attr);
450 }
451
452 return 0;
453}
454
455#ifdef CONFIG_OF
456static const struct of_device_id pcf2123_dt_ids[] = {
457 { .compatible = "nxp,rtc-pcf2123", },
458 { /* sentinel */ }
459};
460MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
461#endif
462
463static struct spi_driver pcf2123_driver = {
464 .driver = {
465 .name = "rtc-pcf2123",
466 .of_match_table = of_match_ptr(pcf2123_dt_ids),
467 },
468 .probe = pcf2123_probe,
469 .remove = pcf2123_remove,
470};
471
472module_spi_driver(pcf2123_driver);
473
474MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
475MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
476MODULE_LICENSE("GPL");
477MODULE_VERSION(DRV_VERSION);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * An SPI driver for the Philips PCF2123 RTC
4 * Copyright 2009 Cyber Switching, Inc.
5 *
6 * Author: Chris Verges <chrisv@cyberswitching.com>
7 * Maintainers: http://www.cyberswitching.com
8 *
9 * based on the RS5C348 driver in this same directory.
10 *
11 * Thanks to Christian Pellegrin <chripell@fsfe.org> for
12 * the sysfs contributions to this driver.
13 *
14 * Please note that the CS is active high, so platform data
15 * should look something like:
16 *
17 * static struct spi_board_info ek_spi_devices[] = {
18 * ...
19 * {
20 * .modalias = "rtc-pcf2123",
21 * .chip_select = 1,
22 * .controller_data = (void *)AT91_PIN_PA10,
23 * .max_speed_hz = 1000 * 1000,
24 * .mode = SPI_CS_HIGH,
25 * .bus_num = 0,
26 * },
27 * ...
28 *};
29 */
30
31#include <linux/bcd.h>
32#include <linux/delay.h>
33#include <linux/device.h>
34#include <linux/errno.h>
35#include <linux/init.h>
36#include <linux/kernel.h>
37#include <linux/of.h>
38#include <linux/string.h>
39#include <linux/slab.h>
40#include <linux/rtc.h>
41#include <linux/spi/spi.h>
42#include <linux/module.h>
43#include <linux/regmap.h>
44
45/* REGISTERS */
46#define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */
47#define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */
48#define PCF2123_REG_SC (0x02) /* datetime */
49#define PCF2123_REG_MN (0x03)
50#define PCF2123_REG_HR (0x04)
51#define PCF2123_REG_DM (0x05)
52#define PCF2123_REG_DW (0x06)
53#define PCF2123_REG_MO (0x07)
54#define PCF2123_REG_YR (0x08)
55#define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */
56#define PCF2123_REG_ALRM_HR (0x0a)
57#define PCF2123_REG_ALRM_DM (0x0b)
58#define PCF2123_REG_ALRM_DW (0x0c)
59#define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */
60#define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */
61#define PCF2123_REG_CTDWN_TMR (0x0f)
62
63/* PCF2123_REG_CTRL1 BITS */
64#define CTRL1_CLEAR (0) /* Clear */
65#define CTRL1_CORR_INT BIT(1) /* Correction irq enable */
66#define CTRL1_12_HOUR BIT(2) /* 12 hour time */
67#define CTRL1_SW_RESET (BIT(3) | BIT(4) | BIT(6)) /* Software reset */
68#define CTRL1_STOP BIT(5) /* Stop the clock */
69#define CTRL1_EXT_TEST BIT(7) /* External clock test mode */
70
71/* PCF2123_REG_CTRL2 BITS */
72#define CTRL2_TIE BIT(0) /* Countdown timer irq enable */
73#define CTRL2_AIE BIT(1) /* Alarm irq enable */
74#define CTRL2_TF BIT(2) /* Countdown timer flag */
75#define CTRL2_AF BIT(3) /* Alarm flag */
76#define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */
77#define CTRL2_MSF BIT(5) /* Minute or second irq flag */
78#define CTRL2_SI BIT(6) /* Second irq enable */
79#define CTRL2_MI BIT(7) /* Minute irq enable */
80
81/* PCF2123_REG_SC BITS */
82#define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */
83
84/* PCF2123_REG_ALRM_XX BITS */
85#define ALRM_DISABLE BIT(7) /* MN, HR, DM, or DW alarm matching */
86
87/* PCF2123_REG_TMR_CLKOUT BITS */
88#define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */
89#define CD_TMR_64HZ (1) /* 64 Hz countdown timer */
90#define CD_TMR_1HZ (2) /* 1 Hz countdown timer */
91#define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */
92#define CD_TMR_TE BIT(3) /* Countdown timer enable */
93
94/* PCF2123_REG_OFFSET BITS */
95#define OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
96#define OFFSET_COARSE BIT(7) /* Coarse mode offset */
97#define OFFSET_STEP (2170) /* Offset step in parts per billion */
98#define OFFSET_MASK GENMASK(6, 0) /* Offset value */
99
100/* READ/WRITE ADDRESS BITS */
101#define PCF2123_WRITE BIT(4)
102#define PCF2123_READ (BIT(4) | BIT(7))
103
104
105static struct spi_driver pcf2123_driver;
106
107struct pcf2123_data {
108 struct rtc_device *rtc;
109 struct regmap *map;
110};
111
112static const struct regmap_config pcf2123_regmap_config = {
113 .reg_bits = 8,
114 .val_bits = 8,
115 .read_flag_mask = PCF2123_READ,
116 .write_flag_mask = PCF2123_WRITE,
117 .max_register = PCF2123_REG_CTDWN_TMR,
118};
119
120static int pcf2123_read_offset(struct device *dev, long *offset)
121{
122 struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
123 int ret, val;
124 unsigned int reg;
125
126 ret = regmap_read(pcf2123->map, PCF2123_REG_OFFSET, ®);
127 if (ret)
128 return ret;
129
130 val = sign_extend32((reg & OFFSET_MASK), OFFSET_SIGN_BIT);
131
132 if (reg & OFFSET_COARSE)
133 val *= 2;
134
135 *offset = ((long)val) * OFFSET_STEP;
136
137 return 0;
138}
139
140/*
141 * The offset register is a 7 bit signed value with a coarse bit in bit 7.
142 * The main difference between the two is normal offset adjusts the first
143 * second of n minutes every other hour, with 61, 62 and 63 being shoved
144 * into the 60th minute.
145 * The coarse adjustment does the same, but every hour.
146 * the two overlap, with every even normal offset value corresponding
147 * to a coarse offset. Based on this algorithm, it seems that despite the
148 * name, coarse offset is a better fit for overlapping values.
149 */
150static int pcf2123_set_offset(struct device *dev, long offset)
151{
152 struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
153 s8 reg;
154
155 if (offset > OFFSET_STEP * 127)
156 reg = 127;
157 else if (offset < OFFSET_STEP * -128)
158 reg = -128;
159 else
160 reg = DIV_ROUND_CLOSEST(offset, OFFSET_STEP);
161
162 /* choose fine offset only for odd values in the normal range */
163 if (reg & 1 && reg <= 63 && reg >= -64) {
164 /* Normal offset. Clear the coarse bit */
165 reg &= ~OFFSET_COARSE;
166 } else {
167 /* Coarse offset. Divide by 2 and set the coarse bit */
168 reg >>= 1;
169 reg |= OFFSET_COARSE;
170 }
171
172 return regmap_write(pcf2123->map, PCF2123_REG_OFFSET, (unsigned int)reg);
173}
174
175static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm)
176{
177 struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
178 u8 rxbuf[7];
179 int ret;
180
181 ret = regmap_bulk_read(pcf2123->map, PCF2123_REG_SC, rxbuf,
182 sizeof(rxbuf));
183 if (ret)
184 return ret;
185
186 if (rxbuf[0] & OSC_HAS_STOPPED) {
187 dev_info(dev, "clock was stopped. Time is not valid\n");
188 return -EINVAL;
189 }
190
191 tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
192 tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
193 tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
194 tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
195 tm->tm_wday = rxbuf[4] & 0x07;
196 tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
197 tm->tm_year = bcd2bin(rxbuf[6]) + 100;
198
199 dev_dbg(dev, "%s: tm is %ptR\n", __func__, tm);
200
201 return 0;
202}
203
204static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm)
205{
206 struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
207 u8 txbuf[7];
208 int ret;
209
210 dev_dbg(dev, "%s: tm is %ptR\n", __func__, tm);
211
212 /* Stop the counter first */
213 ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_STOP);
214 if (ret)
215 return ret;
216
217 /* Set the new time */
218 txbuf[0] = bin2bcd(tm->tm_sec & 0x7F);
219 txbuf[1] = bin2bcd(tm->tm_min & 0x7F);
220 txbuf[2] = bin2bcd(tm->tm_hour & 0x3F);
221 txbuf[3] = bin2bcd(tm->tm_mday & 0x3F);
222 txbuf[4] = tm->tm_wday & 0x07;
223 txbuf[5] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
224 txbuf[6] = bin2bcd(tm->tm_year - 100);
225
226 ret = regmap_bulk_write(pcf2123->map, PCF2123_REG_SC, txbuf,
227 sizeof(txbuf));
228 if (ret)
229 return ret;
230
231 /* Start the counter */
232 ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_CLEAR);
233 if (ret)
234 return ret;
235
236 return 0;
237}
238
239static int pcf2123_rtc_alarm_irq_enable(struct device *dev, unsigned int en)
240{
241 struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
242
243 return regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AIE,
244 en ? CTRL2_AIE : 0);
245}
246
247static int pcf2123_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
248{
249 struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
250 u8 rxbuf[4];
251 int ret;
252 unsigned int val = 0;
253
254 ret = regmap_bulk_read(pcf2123->map, PCF2123_REG_ALRM_MN, rxbuf,
255 sizeof(rxbuf));
256 if (ret)
257 return ret;
258
259 alm->time.tm_min = bcd2bin(rxbuf[0] & 0x7F);
260 alm->time.tm_hour = bcd2bin(rxbuf[1] & 0x3F);
261 alm->time.tm_mday = bcd2bin(rxbuf[2] & 0x3F);
262 alm->time.tm_wday = bcd2bin(rxbuf[3] & 0x07);
263
264 dev_dbg(dev, "%s: alm is %ptR\n", __func__, &alm->time);
265
266 ret = regmap_read(pcf2123->map, PCF2123_REG_CTRL2, &val);
267 if (ret)
268 return ret;
269
270 alm->enabled = !!(val & CTRL2_AIE);
271
272 return 0;
273}
274
275static int pcf2123_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
276{
277 struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
278 u8 txbuf[4];
279 int ret;
280
281 dev_dbg(dev, "%s: alm is %ptR\n", __func__, &alm->time);
282
283 /* Disable alarm interrupt */
284 ret = regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AIE, 0);
285 if (ret)
286 return ret;
287
288 /* Ensure alarm flag is clear */
289 ret = regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AF, 0);
290 if (ret)
291 return ret;
292
293 /* Set new alarm */
294 txbuf[0] = bin2bcd(alm->time.tm_min & 0x7F);
295 txbuf[1] = bin2bcd(alm->time.tm_hour & 0x3F);
296 txbuf[2] = bin2bcd(alm->time.tm_mday & 0x3F);
297 txbuf[3] = ALRM_DISABLE;
298
299 ret = regmap_bulk_write(pcf2123->map, PCF2123_REG_ALRM_MN, txbuf,
300 sizeof(txbuf));
301 if (ret)
302 return ret;
303
304 return pcf2123_rtc_alarm_irq_enable(dev, alm->enabled);
305}
306
307static irqreturn_t pcf2123_rtc_irq(int irq, void *dev)
308{
309 struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
310 struct mutex *lock = &pcf2123->rtc->ops_lock;
311 unsigned int val = 0;
312 int ret = IRQ_NONE;
313
314 mutex_lock(lock);
315 regmap_read(pcf2123->map, PCF2123_REG_CTRL2, &val);
316
317 /* Alarm? */
318 if (val & CTRL2_AF) {
319 ret = IRQ_HANDLED;
320
321 /* Clear alarm flag */
322 regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AF, 0);
323
324 rtc_update_irq(pcf2123->rtc, 1, RTC_IRQF | RTC_AF);
325 }
326
327 mutex_unlock(lock);
328
329 return ret;
330}
331
332static int pcf2123_reset(struct device *dev)
333{
334 struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
335 int ret;
336 unsigned int val = 0;
337
338 ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
339 if (ret)
340 return ret;
341
342 /* Stop the counter */
343 dev_dbg(dev, "stopping RTC\n");
344 ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_STOP);
345 if (ret)
346 return ret;
347
348 /* See if the counter was actually stopped */
349 dev_dbg(dev, "checking for presence of RTC\n");
350 ret = regmap_read(pcf2123->map, PCF2123_REG_CTRL1, &val);
351 if (ret)
352 return ret;
353
354 dev_dbg(dev, "received data from RTC (0x%08X)\n", val);
355 if (!(val & CTRL1_STOP))
356 return -ENODEV;
357
358 /* Start the counter */
359 ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_CLEAR);
360 if (ret)
361 return ret;
362
363 return 0;
364}
365
366static const struct rtc_class_ops pcf2123_rtc_ops = {
367 .read_time = pcf2123_rtc_read_time,
368 .set_time = pcf2123_rtc_set_time,
369 .read_offset = pcf2123_read_offset,
370 .set_offset = pcf2123_set_offset,
371 .read_alarm = pcf2123_rtc_read_alarm,
372 .set_alarm = pcf2123_rtc_set_alarm,
373 .alarm_irq_enable = pcf2123_rtc_alarm_irq_enable,
374};
375
376static int pcf2123_probe(struct spi_device *spi)
377{
378 struct rtc_device *rtc;
379 struct rtc_time tm;
380 struct pcf2123_data *pcf2123;
381 int ret = 0;
382
383 pcf2123 = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_data),
384 GFP_KERNEL);
385 if (!pcf2123)
386 return -ENOMEM;
387
388 dev_set_drvdata(&spi->dev, pcf2123);
389
390 pcf2123->map = devm_regmap_init_spi(spi, &pcf2123_regmap_config);
391 if (IS_ERR(pcf2123->map)) {
392 dev_err(&spi->dev, "regmap init failed.\n");
393 return PTR_ERR(pcf2123->map);
394 }
395
396 ret = pcf2123_rtc_read_time(&spi->dev, &tm);
397 if (ret < 0) {
398 ret = pcf2123_reset(&spi->dev);
399 if (ret < 0) {
400 dev_err(&spi->dev, "chip not found\n");
401 return ret;
402 }
403 }
404
405 dev_info(&spi->dev, "spiclk %u KHz.\n",
406 (spi->max_speed_hz + 500) / 1000);
407
408 /* Finalize the initialization */
409 rtc = devm_rtc_allocate_device(&spi->dev);
410 if (IS_ERR(rtc))
411 return PTR_ERR(rtc);
412
413 pcf2123->rtc = rtc;
414
415 /* Register alarm irq */
416 if (spi->irq > 0) {
417 ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
418 pcf2123_rtc_irq,
419 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
420 pcf2123_driver.driver.name, &spi->dev);
421 if (!ret)
422 device_init_wakeup(&spi->dev, true);
423 else
424 dev_err(&spi->dev, "could not request irq.\n");
425 }
426
427 /* The PCF2123's alarm only has minute accuracy. Must add timer
428 * support to this driver to generate interrupts more than once
429 * per minute.
430 */
431 rtc->uie_unsupported = 1;
432 rtc->ops = &pcf2123_rtc_ops;
433 rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
434 rtc->range_max = RTC_TIMESTAMP_END_2099;
435 rtc->set_start_time = true;
436
437 ret = rtc_register_device(rtc);
438 if (ret)
439 return ret;
440
441 return 0;
442}
443
444#ifdef CONFIG_OF
445static const struct of_device_id pcf2123_dt_ids[] = {
446 { .compatible = "nxp,pcf2123", },
447 { .compatible = "microcrystal,rv2123", },
448 /* Deprecated, do not use */
449 { .compatible = "nxp,rtc-pcf2123", },
450 { /* sentinel */ }
451};
452MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
453#endif
454
455static struct spi_driver pcf2123_driver = {
456 .driver = {
457 .name = "rtc-pcf2123",
458 .of_match_table = of_match_ptr(pcf2123_dt_ids),
459 },
460 .probe = pcf2123_probe,
461};
462
463module_spi_driver(pcf2123_driver);
464
465MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
466MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
467MODULE_LICENSE("GPL");