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1/*
2 * An SPI driver for the Philips PCF2123 RTC
3 * Copyright 2009 Cyber Switching, Inc.
4 *
5 * Author: Chris Verges <chrisv@cyberswitching.com>
6 * Maintainers: http://www.cyberswitching.com
7 *
8 * based on the RS5C348 driver in this same directory.
9 *
10 * Thanks to Christian Pellegrin <chripell@fsfe.org> for
11 * the sysfs contributions to this driver.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 *
17 * Please note that the CS is active high, so platform data
18 * should look something like:
19 *
20 * static struct spi_board_info ek_spi_devices[] = {
21 * ...
22 * {
23 * .modalias = "rtc-pcf2123",
24 * .chip_select = 1,
25 * .controller_data = (void *)AT91_PIN_PA10,
26 * .max_speed_hz = 1000 * 1000,
27 * .mode = SPI_CS_HIGH,
28 * .bus_num = 0,
29 * },
30 * ...
31 *};
32 *
33 */
34
35#include <linux/bcd.h>
36#include <linux/delay.h>
37#include <linux/device.h>
38#include <linux/errno.h>
39#include <linux/init.h>
40#include <linux/kernel.h>
41#include <linux/of.h>
42#include <linux/string.h>
43#include <linux/slab.h>
44#include <linux/rtc.h>
45#include <linux/spi/spi.h>
46#include <linux/module.h>
47#include <linux/sysfs.h>
48
49#define DRV_VERSION "0.6"
50
51/* REGISTERS */
52#define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */
53#define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */
54#define PCF2123_REG_SC (0x02) /* datetime */
55#define PCF2123_REG_MN (0x03)
56#define PCF2123_REG_HR (0x04)
57#define PCF2123_REG_DM (0x05)
58#define PCF2123_REG_DW (0x06)
59#define PCF2123_REG_MO (0x07)
60#define PCF2123_REG_YR (0x08)
61#define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */
62#define PCF2123_REG_ALRM_HR (0x0a)
63#define PCF2123_REG_ALRM_DM (0x0b)
64#define PCF2123_REG_ALRM_DW (0x0c)
65#define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */
66#define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */
67#define PCF2123_REG_CTDWN_TMR (0x0f)
68
69/* PCF2123_REG_CTRL1 BITS */
70#define CTRL1_CLEAR (0) /* Clear */
71#define CTRL1_CORR_INT BIT(1) /* Correction irq enable */
72#define CTRL1_12_HOUR BIT(2) /* 12 hour time */
73#define CTRL1_SW_RESET (BIT(3) | BIT(4) | BIT(6)) /* Software reset */
74#define CTRL1_STOP BIT(5) /* Stop the clock */
75#define CTRL1_EXT_TEST BIT(7) /* External clock test mode */
76
77/* PCF2123_REG_CTRL2 BITS */
78#define CTRL2_TIE BIT(0) /* Countdown timer irq enable */
79#define CTRL2_AIE BIT(1) /* Alarm irq enable */
80#define CTRL2_TF BIT(2) /* Countdown timer flag */
81#define CTRL2_AF BIT(3) /* Alarm flag */
82#define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */
83#define CTRL2_MSF BIT(5) /* Minute or second irq flag */
84#define CTRL2_SI BIT(6) /* Second irq enable */
85#define CTRL2_MI BIT(7) /* Minute irq enable */
86
87/* PCF2123_REG_SC BITS */
88#define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */
89
90/* PCF2123_REG_ALRM_XX BITS */
91#define ALRM_ENABLE BIT(7) /* MN, HR, DM, or DW alarm enable */
92
93/* PCF2123_REG_TMR_CLKOUT BITS */
94#define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */
95#define CD_TMR_64HZ (1) /* 64 Hz countdown timer */
96#define CD_TMR_1HZ (2) /* 1 Hz countdown timer */
97#define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */
98#define CD_TMR_TE BIT(3) /* Countdown timer enable */
99
100/* PCF2123_REG_OFFSET BITS */
101#define OFFSET_SIGN_BIT BIT(6) /* 2's complement sign bit */
102#define OFFSET_COARSE BIT(7) /* Coarse mode offset */
103#define OFFSET_STEP (2170) /* Offset step in parts per billion */
104
105/* READ/WRITE ADDRESS BITS */
106#define PCF2123_WRITE BIT(4)
107#define PCF2123_READ (BIT(4) | BIT(7))
108
109
110static struct spi_driver pcf2123_driver;
111
112struct pcf2123_sysfs_reg {
113 struct device_attribute attr;
114 char name[2];
115};
116
117struct pcf2123_plat_data {
118 struct rtc_device *rtc;
119 struct pcf2123_sysfs_reg regs[16];
120};
121
122/*
123 * Causes a 30 nanosecond delay to ensure that the PCF2123 chip select
124 * is released properly after an SPI write. This function should be
125 * called after EVERY read/write call over SPI.
126 */
127static inline void pcf2123_delay_trec(void)
128{
129 ndelay(30);
130}
131
132static int pcf2123_read(struct device *dev, u8 reg, u8 *rxbuf, size_t size)
133{
134 struct spi_device *spi = to_spi_device(dev);
135 int ret;
136
137 reg |= PCF2123_READ;
138 ret = spi_write_then_read(spi, ®, 1, rxbuf, size);
139 pcf2123_delay_trec();
140
141 return ret;
142}
143
144static int pcf2123_write(struct device *dev, u8 *txbuf, size_t size)
145{
146 struct spi_device *spi = to_spi_device(dev);
147 int ret;
148
149 txbuf[0] |= PCF2123_WRITE;
150 ret = spi_write(spi, txbuf, size);
151 pcf2123_delay_trec();
152
153 return ret;
154}
155
156static int pcf2123_write_reg(struct device *dev, u8 reg, u8 val)
157{
158 u8 txbuf[2];
159
160 txbuf[0] = reg;
161 txbuf[1] = val;
162 return pcf2123_write(dev, txbuf, sizeof(txbuf));
163}
164
165static ssize_t pcf2123_show(struct device *dev, struct device_attribute *attr,
166 char *buffer)
167{
168 struct pcf2123_sysfs_reg *r;
169 u8 rxbuf[1];
170 unsigned long reg;
171 int ret;
172
173 r = container_of(attr, struct pcf2123_sysfs_reg, attr);
174
175 ret = kstrtoul(r->name, 16, ®);
176 if (ret)
177 return ret;
178
179 ret = pcf2123_read(dev, reg, rxbuf, 1);
180 if (ret < 0)
181 return -EIO;
182
183 return sprintf(buffer, "0x%x\n", rxbuf[0]);
184}
185
186static ssize_t pcf2123_store(struct device *dev, struct device_attribute *attr,
187 const char *buffer, size_t count) {
188 struct pcf2123_sysfs_reg *r;
189 unsigned long reg;
190 unsigned long val;
191
192 int ret;
193
194 r = container_of(attr, struct pcf2123_sysfs_reg, attr);
195
196 ret = kstrtoul(r->name, 16, ®);
197 if (ret)
198 return ret;
199
200 ret = kstrtoul(buffer, 10, &val);
201 if (ret)
202 return ret;
203
204 pcf2123_write_reg(dev, reg, val);
205 if (ret < 0)
206 return -EIO;
207 return count;
208}
209
210static int pcf2123_read_offset(struct device *dev, long *offset)
211{
212 int ret;
213 s8 reg;
214
215 ret = pcf2123_read(dev, PCF2123_REG_OFFSET, ®, 1);
216 if (ret < 0)
217 return ret;
218
219 if (reg & OFFSET_COARSE)
220 reg <<= 1; /* multiply by 2 and sign extend */
221 else
222 reg |= (reg & OFFSET_SIGN_BIT) << 1; /* sign extend only */
223
224 *offset = ((long)reg) * OFFSET_STEP;
225
226 return 0;
227}
228
229/*
230 * The offset register is a 7 bit signed value with a coarse bit in bit 7.
231 * The main difference between the two is normal offset adjusts the first
232 * second of n minutes every other hour, with 61, 62 and 63 being shoved
233 * into the 60th minute.
234 * The coarse adjustment does the same, but every hour.
235 * the two overlap, with every even normal offset value corresponding
236 * to a coarse offset. Based on this algorithm, it seems that despite the
237 * name, coarse offset is a better fit for overlapping values.
238 */
239static int pcf2123_set_offset(struct device *dev, long offset)
240{
241 s8 reg;
242
243 if (offset > OFFSET_STEP * 127)
244 reg = 127;
245 else if (offset < OFFSET_STEP * -128)
246 reg = -128;
247 else
248 reg = (s8)((offset + (OFFSET_STEP >> 1)) / OFFSET_STEP);
249
250 /* choose fine offset only for odd values in the normal range */
251 if (reg & 1 && reg <= 63 && reg >= -64) {
252 /* Normal offset. Clear the coarse bit */
253 reg &= ~OFFSET_COARSE;
254 } else {
255 /* Coarse offset. Divide by 2 and set the coarse bit */
256 reg >>= 1;
257 reg |= OFFSET_COARSE;
258 }
259
260 return pcf2123_write_reg(dev, PCF2123_REG_OFFSET, reg);
261}
262
263static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm)
264{
265 u8 rxbuf[7];
266 int ret;
267
268 ret = pcf2123_read(dev, PCF2123_REG_SC, rxbuf, sizeof(rxbuf));
269 if (ret < 0)
270 return ret;
271
272 if (rxbuf[0] & OSC_HAS_STOPPED) {
273 dev_info(dev, "clock was stopped. Time is not valid\n");
274 return -EINVAL;
275 }
276
277 tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
278 tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
279 tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
280 tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
281 tm->tm_wday = rxbuf[4] & 0x07;
282 tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
283 tm->tm_year = bcd2bin(rxbuf[6]);
284 if (tm->tm_year < 70)
285 tm->tm_year += 100; /* assume we are in 1970...2069 */
286
287 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
288 "mday=%d, mon=%d, year=%d, wday=%d\n",
289 __func__,
290 tm->tm_sec, tm->tm_min, tm->tm_hour,
291 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
292
293 return rtc_valid_tm(tm);
294}
295
296static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm)
297{
298 u8 txbuf[8];
299 int ret;
300
301 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
302 "mday=%d, mon=%d, year=%d, wday=%d\n",
303 __func__,
304 tm->tm_sec, tm->tm_min, tm->tm_hour,
305 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
306
307 /* Stop the counter first */
308 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
309 if (ret < 0)
310 return ret;
311
312 /* Set the new time */
313 txbuf[0] = PCF2123_REG_SC;
314 txbuf[1] = bin2bcd(tm->tm_sec & 0x7F);
315 txbuf[2] = bin2bcd(tm->tm_min & 0x7F);
316 txbuf[3] = bin2bcd(tm->tm_hour & 0x3F);
317 txbuf[4] = bin2bcd(tm->tm_mday & 0x3F);
318 txbuf[5] = tm->tm_wday & 0x07;
319 txbuf[6] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
320 txbuf[7] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100);
321
322 ret = pcf2123_write(dev, txbuf, sizeof(txbuf));
323 if (ret < 0)
324 return ret;
325
326 /* Start the counter */
327 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
328 if (ret < 0)
329 return ret;
330
331 return 0;
332}
333
334static int pcf2123_reset(struct device *dev)
335{
336 int ret;
337 u8 rxbuf[2];
338
339 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
340 if (ret < 0)
341 return ret;
342
343 /* Stop the counter */
344 dev_dbg(dev, "stopping RTC\n");
345 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
346 if (ret < 0)
347 return ret;
348
349 /* See if the counter was actually stopped */
350 dev_dbg(dev, "checking for presence of RTC\n");
351 ret = pcf2123_read(dev, PCF2123_REG_CTRL1, rxbuf, sizeof(rxbuf));
352 if (ret < 0)
353 return ret;
354
355 dev_dbg(dev, "received data from RTC (0x%02X 0x%02X)\n",
356 rxbuf[0], rxbuf[1]);
357 if (!(rxbuf[0] & CTRL1_STOP))
358 return -ENODEV;
359
360 /* Start the counter */
361 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
362 if (ret < 0)
363 return ret;
364
365 return 0;
366}
367
368static const struct rtc_class_ops pcf2123_rtc_ops = {
369 .read_time = pcf2123_rtc_read_time,
370 .set_time = pcf2123_rtc_set_time,
371 .read_offset = pcf2123_read_offset,
372 .set_offset = pcf2123_set_offset,
373
374};
375
376static int pcf2123_probe(struct spi_device *spi)
377{
378 struct rtc_device *rtc;
379 struct rtc_time tm;
380 struct pcf2123_plat_data *pdata;
381 int ret, i;
382
383 pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data),
384 GFP_KERNEL);
385 if (!pdata)
386 return -ENOMEM;
387 spi->dev.platform_data = pdata;
388
389 ret = pcf2123_rtc_read_time(&spi->dev, &tm);
390 if (ret < 0) {
391 ret = pcf2123_reset(&spi->dev);
392 if (ret < 0) {
393 dev_err(&spi->dev, "chip not found\n");
394 goto kfree_exit;
395 }
396 }
397
398 dev_info(&spi->dev, "chip found, driver version " DRV_VERSION "\n");
399 dev_info(&spi->dev, "spiclk %u KHz.\n",
400 (spi->max_speed_hz + 500) / 1000);
401
402 /* Finalize the initialization */
403 rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name,
404 &pcf2123_rtc_ops, THIS_MODULE);
405
406 if (IS_ERR(rtc)) {
407 dev_err(&spi->dev, "failed to register.\n");
408 ret = PTR_ERR(rtc);
409 goto kfree_exit;
410 }
411
412 pdata->rtc = rtc;
413
414 for (i = 0; i < 16; i++) {
415 sysfs_attr_init(&pdata->regs[i].attr.attr);
416 sprintf(pdata->regs[i].name, "%1x", i);
417 pdata->regs[i].attr.attr.mode = S_IRUGO | S_IWUSR;
418 pdata->regs[i].attr.attr.name = pdata->regs[i].name;
419 pdata->regs[i].attr.show = pcf2123_show;
420 pdata->regs[i].attr.store = pcf2123_store;
421 ret = device_create_file(&spi->dev, &pdata->regs[i].attr);
422 if (ret) {
423 dev_err(&spi->dev, "Unable to create sysfs %s\n",
424 pdata->regs[i].name);
425 goto sysfs_exit;
426 }
427 }
428
429 return 0;
430
431sysfs_exit:
432 for (i--; i >= 0; i--)
433 device_remove_file(&spi->dev, &pdata->regs[i].attr);
434
435kfree_exit:
436 spi->dev.platform_data = NULL;
437 return ret;
438}
439
440static int pcf2123_remove(struct spi_device *spi)
441{
442 struct pcf2123_plat_data *pdata = dev_get_platdata(&spi->dev);
443 int i;
444
445 if (pdata) {
446 for (i = 0; i < 16; i++)
447 if (pdata->regs[i].name[0])
448 device_remove_file(&spi->dev,
449 &pdata->regs[i].attr);
450 }
451
452 return 0;
453}
454
455#ifdef CONFIG_OF
456static const struct of_device_id pcf2123_dt_ids[] = {
457 { .compatible = "nxp,rtc-pcf2123", },
458 { /* sentinel */ }
459};
460MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
461#endif
462
463static struct spi_driver pcf2123_driver = {
464 .driver = {
465 .name = "rtc-pcf2123",
466 .of_match_table = of_match_ptr(pcf2123_dt_ids),
467 },
468 .probe = pcf2123_probe,
469 .remove = pcf2123_remove,
470};
471
472module_spi_driver(pcf2123_driver);
473
474MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
475MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
476MODULE_LICENSE("GPL");
477MODULE_VERSION(DRV_VERSION);
1/*
2 * An SPI driver for the Philips PCF2123 RTC
3 * Copyright 2009 Cyber Switching, Inc.
4 *
5 * Author: Chris Verges <chrisv@cyberswitching.com>
6 * Maintainers: http://www.cyberswitching.com
7 *
8 * based on the RS5C348 driver in this same directory.
9 *
10 * Thanks to Christian Pellegrin <chripell@fsfe.org> for
11 * the sysfs contributions to this driver.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 *
17 * Please note that the CS is active high, so platform data
18 * should look something like:
19 *
20 * static struct spi_board_info ek_spi_devices[] = {
21 * ...
22 * {
23 * .modalias = "rtc-pcf2123",
24 * .chip_select = 1,
25 * .controller_data = (void *)AT91_PIN_PA10,
26 * .max_speed_hz = 1000 * 1000,
27 * .mode = SPI_CS_HIGH,
28 * .bus_num = 0,
29 * },
30 * ...
31 *};
32 *
33 */
34
35#include <linux/bcd.h>
36#include <linux/delay.h>
37#include <linux/device.h>
38#include <linux/errno.h>
39#include <linux/init.h>
40#include <linux/kernel.h>
41#include <linux/of.h>
42#include <linux/string.h>
43#include <linux/slab.h>
44#include <linux/rtc.h>
45#include <linux/spi/spi.h>
46#include <linux/module.h>
47#include <linux/sysfs.h>
48
49/* REGISTERS */
50#define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */
51#define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */
52#define PCF2123_REG_SC (0x02) /* datetime */
53#define PCF2123_REG_MN (0x03)
54#define PCF2123_REG_HR (0x04)
55#define PCF2123_REG_DM (0x05)
56#define PCF2123_REG_DW (0x06)
57#define PCF2123_REG_MO (0x07)
58#define PCF2123_REG_YR (0x08)
59#define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */
60#define PCF2123_REG_ALRM_HR (0x0a)
61#define PCF2123_REG_ALRM_DM (0x0b)
62#define PCF2123_REG_ALRM_DW (0x0c)
63#define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */
64#define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */
65#define PCF2123_REG_CTDWN_TMR (0x0f)
66
67/* PCF2123_REG_CTRL1 BITS */
68#define CTRL1_CLEAR (0) /* Clear */
69#define CTRL1_CORR_INT BIT(1) /* Correction irq enable */
70#define CTRL1_12_HOUR BIT(2) /* 12 hour time */
71#define CTRL1_SW_RESET (BIT(3) | BIT(4) | BIT(6)) /* Software reset */
72#define CTRL1_STOP BIT(5) /* Stop the clock */
73#define CTRL1_EXT_TEST BIT(7) /* External clock test mode */
74
75/* PCF2123_REG_CTRL2 BITS */
76#define CTRL2_TIE BIT(0) /* Countdown timer irq enable */
77#define CTRL2_AIE BIT(1) /* Alarm irq enable */
78#define CTRL2_TF BIT(2) /* Countdown timer flag */
79#define CTRL2_AF BIT(3) /* Alarm flag */
80#define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */
81#define CTRL2_MSF BIT(5) /* Minute or second irq flag */
82#define CTRL2_SI BIT(6) /* Second irq enable */
83#define CTRL2_MI BIT(7) /* Minute irq enable */
84
85/* PCF2123_REG_SC BITS */
86#define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */
87
88/* PCF2123_REG_ALRM_XX BITS */
89#define ALRM_ENABLE BIT(7) /* MN, HR, DM, or DW alarm enable */
90
91/* PCF2123_REG_TMR_CLKOUT BITS */
92#define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */
93#define CD_TMR_64HZ (1) /* 64 Hz countdown timer */
94#define CD_TMR_1HZ (2) /* 1 Hz countdown timer */
95#define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */
96#define CD_TMR_TE BIT(3) /* Countdown timer enable */
97
98/* PCF2123_REG_OFFSET BITS */
99#define OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
100#define OFFSET_COARSE BIT(7) /* Coarse mode offset */
101#define OFFSET_STEP (2170) /* Offset step in parts per billion */
102
103/* READ/WRITE ADDRESS BITS */
104#define PCF2123_WRITE BIT(4)
105#define PCF2123_READ (BIT(4) | BIT(7))
106
107
108static struct spi_driver pcf2123_driver;
109
110struct pcf2123_sysfs_reg {
111 struct device_attribute attr;
112 char name[2];
113};
114
115struct pcf2123_plat_data {
116 struct rtc_device *rtc;
117 struct pcf2123_sysfs_reg regs[16];
118};
119
120/*
121 * Causes a 30 nanosecond delay to ensure that the PCF2123 chip select
122 * is released properly after an SPI write. This function should be
123 * called after EVERY read/write call over SPI.
124 */
125static inline void pcf2123_delay_trec(void)
126{
127 ndelay(30);
128}
129
130static int pcf2123_read(struct device *dev, u8 reg, u8 *rxbuf, size_t size)
131{
132 struct spi_device *spi = to_spi_device(dev);
133 int ret;
134
135 reg |= PCF2123_READ;
136 ret = spi_write_then_read(spi, ®, 1, rxbuf, size);
137 pcf2123_delay_trec();
138
139 return ret;
140}
141
142static int pcf2123_write(struct device *dev, u8 *txbuf, size_t size)
143{
144 struct spi_device *spi = to_spi_device(dev);
145 int ret;
146
147 txbuf[0] |= PCF2123_WRITE;
148 ret = spi_write(spi, txbuf, size);
149 pcf2123_delay_trec();
150
151 return ret;
152}
153
154static int pcf2123_write_reg(struct device *dev, u8 reg, u8 val)
155{
156 u8 txbuf[2];
157
158 txbuf[0] = reg;
159 txbuf[1] = val;
160 return pcf2123_write(dev, txbuf, sizeof(txbuf));
161}
162
163static ssize_t pcf2123_show(struct device *dev, struct device_attribute *attr,
164 char *buffer)
165{
166 struct pcf2123_sysfs_reg *r;
167 u8 rxbuf[1];
168 unsigned long reg;
169 int ret;
170
171 r = container_of(attr, struct pcf2123_sysfs_reg, attr);
172
173 ret = kstrtoul(r->name, 16, ®);
174 if (ret)
175 return ret;
176
177 ret = pcf2123_read(dev, reg, rxbuf, 1);
178 if (ret < 0)
179 return -EIO;
180
181 return sprintf(buffer, "0x%x\n", rxbuf[0]);
182}
183
184static ssize_t pcf2123_store(struct device *dev, struct device_attribute *attr,
185 const char *buffer, size_t count)
186{
187 struct pcf2123_sysfs_reg *r;
188 unsigned long reg;
189 unsigned long val;
190
191 int ret;
192
193 r = container_of(attr, struct pcf2123_sysfs_reg, attr);
194
195 ret = kstrtoul(r->name, 16, ®);
196 if (ret)
197 return ret;
198
199 ret = kstrtoul(buffer, 10, &val);
200 if (ret)
201 return ret;
202
203 ret = pcf2123_write_reg(dev, reg, val);
204 if (ret < 0)
205 return -EIO;
206 return count;
207}
208
209static int pcf2123_read_offset(struct device *dev, long *offset)
210{
211 int ret;
212 s8 reg;
213
214 ret = pcf2123_read(dev, PCF2123_REG_OFFSET, ®, 1);
215 if (ret < 0)
216 return ret;
217
218 if (reg & OFFSET_COARSE)
219 reg <<= 1; /* multiply by 2 and sign extend */
220 else
221 reg = sign_extend32(reg, OFFSET_SIGN_BIT);
222
223 *offset = ((long)reg) * OFFSET_STEP;
224
225 return 0;
226}
227
228/*
229 * The offset register is a 7 bit signed value with a coarse bit in bit 7.
230 * The main difference between the two is normal offset adjusts the first
231 * second of n minutes every other hour, with 61, 62 and 63 being shoved
232 * into the 60th minute.
233 * The coarse adjustment does the same, but every hour.
234 * the two overlap, with every even normal offset value corresponding
235 * to a coarse offset. Based on this algorithm, it seems that despite the
236 * name, coarse offset is a better fit for overlapping values.
237 */
238static int pcf2123_set_offset(struct device *dev, long offset)
239{
240 s8 reg;
241
242 if (offset > OFFSET_STEP * 127)
243 reg = 127;
244 else if (offset < OFFSET_STEP * -128)
245 reg = -128;
246 else
247 reg = (s8)((offset + (OFFSET_STEP >> 1)) / OFFSET_STEP);
248
249 /* choose fine offset only for odd values in the normal range */
250 if (reg & 1 && reg <= 63 && reg >= -64) {
251 /* Normal offset. Clear the coarse bit */
252 reg &= ~OFFSET_COARSE;
253 } else {
254 /* Coarse offset. Divide by 2 and set the coarse bit */
255 reg >>= 1;
256 reg |= OFFSET_COARSE;
257 }
258
259 return pcf2123_write_reg(dev, PCF2123_REG_OFFSET, reg);
260}
261
262static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm)
263{
264 u8 rxbuf[7];
265 int ret;
266
267 ret = pcf2123_read(dev, PCF2123_REG_SC, rxbuf, sizeof(rxbuf));
268 if (ret < 0)
269 return ret;
270
271 if (rxbuf[0] & OSC_HAS_STOPPED) {
272 dev_info(dev, "clock was stopped. Time is not valid\n");
273 return -EINVAL;
274 }
275
276 tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
277 tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
278 tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
279 tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
280 tm->tm_wday = rxbuf[4] & 0x07;
281 tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
282 tm->tm_year = bcd2bin(rxbuf[6]);
283 if (tm->tm_year < 70)
284 tm->tm_year += 100; /* assume we are in 1970...2069 */
285
286 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
287 "mday=%d, mon=%d, year=%d, wday=%d\n",
288 __func__,
289 tm->tm_sec, tm->tm_min, tm->tm_hour,
290 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
291
292 return 0;
293}
294
295static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm)
296{
297 u8 txbuf[8];
298 int ret;
299
300 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
301 "mday=%d, mon=%d, year=%d, wday=%d\n",
302 __func__,
303 tm->tm_sec, tm->tm_min, tm->tm_hour,
304 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
305
306 /* Stop the counter first */
307 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
308 if (ret < 0)
309 return ret;
310
311 /* Set the new time */
312 txbuf[0] = PCF2123_REG_SC;
313 txbuf[1] = bin2bcd(tm->tm_sec & 0x7F);
314 txbuf[2] = bin2bcd(tm->tm_min & 0x7F);
315 txbuf[3] = bin2bcd(tm->tm_hour & 0x3F);
316 txbuf[4] = bin2bcd(tm->tm_mday & 0x3F);
317 txbuf[5] = tm->tm_wday & 0x07;
318 txbuf[6] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
319 txbuf[7] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100);
320
321 ret = pcf2123_write(dev, txbuf, sizeof(txbuf));
322 if (ret < 0)
323 return ret;
324
325 /* Start the counter */
326 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
327 if (ret < 0)
328 return ret;
329
330 return 0;
331}
332
333static int pcf2123_reset(struct device *dev)
334{
335 int ret;
336 u8 rxbuf[2];
337
338 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
339 if (ret < 0)
340 return ret;
341
342 /* Stop the counter */
343 dev_dbg(dev, "stopping RTC\n");
344 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
345 if (ret < 0)
346 return ret;
347
348 /* See if the counter was actually stopped */
349 dev_dbg(dev, "checking for presence of RTC\n");
350 ret = pcf2123_read(dev, PCF2123_REG_CTRL1, rxbuf, sizeof(rxbuf));
351 if (ret < 0)
352 return ret;
353
354 dev_dbg(dev, "received data from RTC (0x%02X 0x%02X)\n",
355 rxbuf[0], rxbuf[1]);
356 if (!(rxbuf[0] & CTRL1_STOP))
357 return -ENODEV;
358
359 /* Start the counter */
360 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
361 if (ret < 0)
362 return ret;
363
364 return 0;
365}
366
367static const struct rtc_class_ops pcf2123_rtc_ops = {
368 .read_time = pcf2123_rtc_read_time,
369 .set_time = pcf2123_rtc_set_time,
370 .read_offset = pcf2123_read_offset,
371 .set_offset = pcf2123_set_offset,
372
373};
374
375static int pcf2123_probe(struct spi_device *spi)
376{
377 struct rtc_device *rtc;
378 struct rtc_time tm;
379 struct pcf2123_plat_data *pdata;
380 int ret, i;
381
382 pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data),
383 GFP_KERNEL);
384 if (!pdata)
385 return -ENOMEM;
386 spi->dev.platform_data = pdata;
387
388 ret = pcf2123_rtc_read_time(&spi->dev, &tm);
389 if (ret < 0) {
390 ret = pcf2123_reset(&spi->dev);
391 if (ret < 0) {
392 dev_err(&spi->dev, "chip not found\n");
393 goto kfree_exit;
394 }
395 }
396
397 dev_info(&spi->dev, "spiclk %u KHz.\n",
398 (spi->max_speed_hz + 500) / 1000);
399
400 /* Finalize the initialization */
401 rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name,
402 &pcf2123_rtc_ops, THIS_MODULE);
403
404 if (IS_ERR(rtc)) {
405 dev_err(&spi->dev, "failed to register.\n");
406 ret = PTR_ERR(rtc);
407 goto kfree_exit;
408 }
409
410 pdata->rtc = rtc;
411
412 for (i = 0; i < 16; i++) {
413 sysfs_attr_init(&pdata->regs[i].attr.attr);
414 sprintf(pdata->regs[i].name, "%1x", i);
415 pdata->regs[i].attr.attr.mode = S_IRUGO | S_IWUSR;
416 pdata->regs[i].attr.attr.name = pdata->regs[i].name;
417 pdata->regs[i].attr.show = pcf2123_show;
418 pdata->regs[i].attr.store = pcf2123_store;
419 ret = device_create_file(&spi->dev, &pdata->regs[i].attr);
420 if (ret) {
421 dev_err(&spi->dev, "Unable to create sysfs %s\n",
422 pdata->regs[i].name);
423 goto sysfs_exit;
424 }
425 }
426
427 return 0;
428
429sysfs_exit:
430 for (i--; i >= 0; i--)
431 device_remove_file(&spi->dev, &pdata->regs[i].attr);
432
433kfree_exit:
434 spi->dev.platform_data = NULL;
435 return ret;
436}
437
438static int pcf2123_remove(struct spi_device *spi)
439{
440 struct pcf2123_plat_data *pdata = dev_get_platdata(&spi->dev);
441 int i;
442
443 if (pdata) {
444 for (i = 0; i < 16; i++)
445 if (pdata->regs[i].name[0])
446 device_remove_file(&spi->dev,
447 &pdata->regs[i].attr);
448 }
449
450 return 0;
451}
452
453#ifdef CONFIG_OF
454static const struct of_device_id pcf2123_dt_ids[] = {
455 { .compatible = "nxp,rtc-pcf2123", },
456 { /* sentinel */ }
457};
458MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
459#endif
460
461static struct spi_driver pcf2123_driver = {
462 .driver = {
463 .name = "rtc-pcf2123",
464 .of_match_table = of_match_ptr(pcf2123_dt_ids),
465 },
466 .probe = pcf2123_probe,
467 .remove = pcf2123_remove,
468};
469
470module_spi_driver(pcf2123_driver);
471
472MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
473MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
474MODULE_LICENSE("GPL");