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1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3/*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31#include <linux/sysrq.h>
32#include <linux/slab.h>
33#include <linux/circ_buf.h>
34#include <drm/drmP.h>
35#include <drm/i915_drm.h>
36#include "i915_drv.h"
37#include "i915_trace.h"
38#include "intel_drv.h"
39
40/**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
48static const u32 hpd_ilk[HPD_NUM_PINS] = {
49 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
50};
51
52static const u32 hpd_ivb[HPD_NUM_PINS] = {
53 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
54};
55
56static const u32 hpd_bdw[HPD_NUM_PINS] = {
57 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
58};
59
60static const u32 hpd_ibx[HPD_NUM_PINS] = {
61 [HPD_CRT] = SDE_CRT_HOTPLUG,
62 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
63 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
64 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
65 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
66};
67
68static const u32 hpd_cpt[HPD_NUM_PINS] = {
69 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
70 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
71 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
72 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
73 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
74};
75
76static const u32 hpd_spt[HPD_NUM_PINS] = {
77 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
78 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
79 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
80 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
81 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
82};
83
84static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
85 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
86 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
87 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
88 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
89 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
90 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
91};
92
93static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
94 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
95 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
96 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
97 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
98 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
99 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
100};
101
102static const u32 hpd_status_i915[HPD_NUM_PINS] = {
103 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
104 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
105 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
106 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
107 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
108 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
109};
110
111/* BXT hpd list */
112static const u32 hpd_bxt[HPD_NUM_PINS] = {
113 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
114 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
115 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
116};
117
118/* IIR can theoretically queue up two events. Be paranoid. */
119#define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
127} while (0)
128
129#define GEN5_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
137} while (0)
138
139/*
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
141 */
142static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
143 i915_reg_t reg)
144{
145 u32 val = I915_READ(reg);
146
147 if (val == 0)
148 return;
149
150 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
151 i915_mmio_reg_offset(reg), val);
152 I915_WRITE(reg, 0xffffffff);
153 POSTING_READ(reg);
154 I915_WRITE(reg, 0xffffffff);
155 POSTING_READ(reg);
156}
157
158#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
159 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
160 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
161 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
162 POSTING_READ(GEN8_##type##_IMR(which)); \
163} while (0)
164
165#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
166 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
167 I915_WRITE(type##IER, (ier_val)); \
168 I915_WRITE(type##IMR, (imr_val)); \
169 POSTING_READ(type##IMR); \
170} while (0)
171
172static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
173
174/* For display hotplug interrupt */
175static inline void
176i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
177 uint32_t mask,
178 uint32_t bits)
179{
180 uint32_t val;
181
182 assert_spin_locked(&dev_priv->irq_lock);
183 WARN_ON(bits & ~mask);
184
185 val = I915_READ(PORT_HOTPLUG_EN);
186 val &= ~mask;
187 val |= bits;
188 I915_WRITE(PORT_HOTPLUG_EN, val);
189}
190
191/**
192 * i915_hotplug_interrupt_update - update hotplug interrupt enable
193 * @dev_priv: driver private
194 * @mask: bits to update
195 * @bits: bits to enable
196 * NOTE: the HPD enable bits are modified both inside and outside
197 * of an interrupt context. To avoid that read-modify-write cycles
198 * interfer, these bits are protected by a spinlock. Since this
199 * function is usually not called from a context where the lock is
200 * held already, this function acquires the lock itself. A non-locking
201 * version is also available.
202 */
203void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
204 uint32_t mask,
205 uint32_t bits)
206{
207 spin_lock_irq(&dev_priv->irq_lock);
208 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
209 spin_unlock_irq(&dev_priv->irq_lock);
210}
211
212/**
213 * ilk_update_display_irq - update DEIMR
214 * @dev_priv: driver private
215 * @interrupt_mask: mask of interrupt bits to update
216 * @enabled_irq_mask: mask of interrupt bits to enable
217 */
218void ilk_update_display_irq(struct drm_i915_private *dev_priv,
219 uint32_t interrupt_mask,
220 uint32_t enabled_irq_mask)
221{
222 uint32_t new_val;
223
224 assert_spin_locked(&dev_priv->irq_lock);
225
226 WARN_ON(enabled_irq_mask & ~interrupt_mask);
227
228 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
229 return;
230
231 new_val = dev_priv->irq_mask;
232 new_val &= ~interrupt_mask;
233 new_val |= (~enabled_irq_mask & interrupt_mask);
234
235 if (new_val != dev_priv->irq_mask) {
236 dev_priv->irq_mask = new_val;
237 I915_WRITE(DEIMR, dev_priv->irq_mask);
238 POSTING_READ(DEIMR);
239 }
240}
241
242/**
243 * ilk_update_gt_irq - update GTIMR
244 * @dev_priv: driver private
245 * @interrupt_mask: mask of interrupt bits to update
246 * @enabled_irq_mask: mask of interrupt bits to enable
247 */
248static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
249 uint32_t interrupt_mask,
250 uint32_t enabled_irq_mask)
251{
252 assert_spin_locked(&dev_priv->irq_lock);
253
254 WARN_ON(enabled_irq_mask & ~interrupt_mask);
255
256 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
257 return;
258
259 dev_priv->gt_irq_mask &= ~interrupt_mask;
260 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
261 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
262 POSTING_READ(GTIMR);
263}
264
265void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
266{
267 ilk_update_gt_irq(dev_priv, mask, mask);
268}
269
270void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
271{
272 ilk_update_gt_irq(dev_priv, mask, 0);
273}
274
275static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
276{
277 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
278}
279
280static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
281{
282 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
283}
284
285static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
286{
287 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
288}
289
290/**
291 * snb_update_pm_irq - update GEN6_PMIMR
292 * @dev_priv: driver private
293 * @interrupt_mask: mask of interrupt bits to update
294 * @enabled_irq_mask: mask of interrupt bits to enable
295 */
296static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
297 uint32_t interrupt_mask,
298 uint32_t enabled_irq_mask)
299{
300 uint32_t new_val;
301
302 WARN_ON(enabled_irq_mask & ~interrupt_mask);
303
304 assert_spin_locked(&dev_priv->irq_lock);
305
306 new_val = dev_priv->pm_irq_mask;
307 new_val &= ~interrupt_mask;
308 new_val |= (~enabled_irq_mask & interrupt_mask);
309
310 if (new_val != dev_priv->pm_irq_mask) {
311 dev_priv->pm_irq_mask = new_val;
312 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
313 POSTING_READ(gen6_pm_imr(dev_priv));
314 }
315}
316
317void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
318{
319 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
320 return;
321
322 snb_update_pm_irq(dev_priv, mask, mask);
323}
324
325static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
326 uint32_t mask)
327{
328 snb_update_pm_irq(dev_priv, mask, 0);
329}
330
331void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
332{
333 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
334 return;
335
336 __gen6_disable_pm_irq(dev_priv, mask);
337}
338
339void gen6_reset_rps_interrupts(struct drm_device *dev)
340{
341 struct drm_i915_private *dev_priv = dev->dev_private;
342 i915_reg_t reg = gen6_pm_iir(dev_priv);
343
344 spin_lock_irq(&dev_priv->irq_lock);
345 I915_WRITE(reg, dev_priv->pm_rps_events);
346 I915_WRITE(reg, dev_priv->pm_rps_events);
347 POSTING_READ(reg);
348 dev_priv->rps.pm_iir = 0;
349 spin_unlock_irq(&dev_priv->irq_lock);
350}
351
352void gen6_enable_rps_interrupts(struct drm_device *dev)
353{
354 struct drm_i915_private *dev_priv = dev->dev_private;
355
356 spin_lock_irq(&dev_priv->irq_lock);
357
358 WARN_ON(dev_priv->rps.pm_iir);
359 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
360 dev_priv->rps.interrupts_enabled = true;
361 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
362 dev_priv->pm_rps_events);
363 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
364
365 spin_unlock_irq(&dev_priv->irq_lock);
366}
367
368u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
369{
370 /*
371 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
372 * if GEN6_PM_UP_EI_EXPIRED is masked.
373 *
374 * TODO: verify if this can be reproduced on VLV,CHV.
375 */
376 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
377 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
378
379 if (INTEL_INFO(dev_priv)->gen >= 8)
380 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
381
382 return mask;
383}
384
385void gen6_disable_rps_interrupts(struct drm_device *dev)
386{
387 struct drm_i915_private *dev_priv = dev->dev_private;
388
389 spin_lock_irq(&dev_priv->irq_lock);
390 dev_priv->rps.interrupts_enabled = false;
391 spin_unlock_irq(&dev_priv->irq_lock);
392
393 cancel_work_sync(&dev_priv->rps.work);
394
395 spin_lock_irq(&dev_priv->irq_lock);
396
397 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
398
399 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
400 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
401 ~dev_priv->pm_rps_events);
402
403 spin_unlock_irq(&dev_priv->irq_lock);
404
405 synchronize_irq(dev->irq);
406}
407
408/**
409 * bdw_update_port_irq - update DE port interrupt
410 * @dev_priv: driver private
411 * @interrupt_mask: mask of interrupt bits to update
412 * @enabled_irq_mask: mask of interrupt bits to enable
413 */
414static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
415 uint32_t interrupt_mask,
416 uint32_t enabled_irq_mask)
417{
418 uint32_t new_val;
419 uint32_t old_val;
420
421 assert_spin_locked(&dev_priv->irq_lock);
422
423 WARN_ON(enabled_irq_mask & ~interrupt_mask);
424
425 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
426 return;
427
428 old_val = I915_READ(GEN8_DE_PORT_IMR);
429
430 new_val = old_val;
431 new_val &= ~interrupt_mask;
432 new_val |= (~enabled_irq_mask & interrupt_mask);
433
434 if (new_val != old_val) {
435 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
436 POSTING_READ(GEN8_DE_PORT_IMR);
437 }
438}
439
440/**
441 * bdw_update_pipe_irq - update DE pipe interrupt
442 * @dev_priv: driver private
443 * @pipe: pipe whose interrupt to update
444 * @interrupt_mask: mask of interrupt bits to update
445 * @enabled_irq_mask: mask of interrupt bits to enable
446 */
447void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
448 enum pipe pipe,
449 uint32_t interrupt_mask,
450 uint32_t enabled_irq_mask)
451{
452 uint32_t new_val;
453
454 assert_spin_locked(&dev_priv->irq_lock);
455
456 WARN_ON(enabled_irq_mask & ~interrupt_mask);
457
458 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
459 return;
460
461 new_val = dev_priv->de_irq_mask[pipe];
462 new_val &= ~interrupt_mask;
463 new_val |= (~enabled_irq_mask & interrupt_mask);
464
465 if (new_val != dev_priv->de_irq_mask[pipe]) {
466 dev_priv->de_irq_mask[pipe] = new_val;
467 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
468 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
469 }
470}
471
472/**
473 * ibx_display_interrupt_update - update SDEIMR
474 * @dev_priv: driver private
475 * @interrupt_mask: mask of interrupt bits to update
476 * @enabled_irq_mask: mask of interrupt bits to enable
477 */
478void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
479 uint32_t interrupt_mask,
480 uint32_t enabled_irq_mask)
481{
482 uint32_t sdeimr = I915_READ(SDEIMR);
483 sdeimr &= ~interrupt_mask;
484 sdeimr |= (~enabled_irq_mask & interrupt_mask);
485
486 WARN_ON(enabled_irq_mask & ~interrupt_mask);
487
488 assert_spin_locked(&dev_priv->irq_lock);
489
490 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
491 return;
492
493 I915_WRITE(SDEIMR, sdeimr);
494 POSTING_READ(SDEIMR);
495}
496
497static void
498__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
499 u32 enable_mask, u32 status_mask)
500{
501 i915_reg_t reg = PIPESTAT(pipe);
502 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
503
504 assert_spin_locked(&dev_priv->irq_lock);
505 WARN_ON(!intel_irqs_enabled(dev_priv));
506
507 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
508 status_mask & ~PIPESTAT_INT_STATUS_MASK,
509 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
510 pipe_name(pipe), enable_mask, status_mask))
511 return;
512
513 if ((pipestat & enable_mask) == enable_mask)
514 return;
515
516 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
517
518 /* Enable the interrupt, clear any pending status */
519 pipestat |= enable_mask | status_mask;
520 I915_WRITE(reg, pipestat);
521 POSTING_READ(reg);
522}
523
524static void
525__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
526 u32 enable_mask, u32 status_mask)
527{
528 i915_reg_t reg = PIPESTAT(pipe);
529 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
530
531 assert_spin_locked(&dev_priv->irq_lock);
532 WARN_ON(!intel_irqs_enabled(dev_priv));
533
534 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
535 status_mask & ~PIPESTAT_INT_STATUS_MASK,
536 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
537 pipe_name(pipe), enable_mask, status_mask))
538 return;
539
540 if ((pipestat & enable_mask) == 0)
541 return;
542
543 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
544
545 pipestat &= ~enable_mask;
546 I915_WRITE(reg, pipestat);
547 POSTING_READ(reg);
548}
549
550static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
551{
552 u32 enable_mask = status_mask << 16;
553
554 /*
555 * On pipe A we don't support the PSR interrupt yet,
556 * on pipe B and C the same bit MBZ.
557 */
558 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
559 return 0;
560 /*
561 * On pipe B and C we don't support the PSR interrupt yet, on pipe
562 * A the same bit is for perf counters which we don't use either.
563 */
564 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
565 return 0;
566
567 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
568 SPRITE0_FLIP_DONE_INT_EN_VLV |
569 SPRITE1_FLIP_DONE_INT_EN_VLV);
570 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
571 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
572 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
573 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
574
575 return enable_mask;
576}
577
578void
579i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
580 u32 status_mask)
581{
582 u32 enable_mask;
583
584 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
585 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
586 status_mask);
587 else
588 enable_mask = status_mask << 16;
589 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
590}
591
592void
593i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
594 u32 status_mask)
595{
596 u32 enable_mask;
597
598 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
599 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
600 status_mask);
601 else
602 enable_mask = status_mask << 16;
603 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
604}
605
606/**
607 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
608 * @dev: drm device
609 */
610static void i915_enable_asle_pipestat(struct drm_device *dev)
611{
612 struct drm_i915_private *dev_priv = dev->dev_private;
613
614 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
615 return;
616
617 spin_lock_irq(&dev_priv->irq_lock);
618
619 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
620 if (INTEL_INFO(dev)->gen >= 4)
621 i915_enable_pipestat(dev_priv, PIPE_A,
622 PIPE_LEGACY_BLC_EVENT_STATUS);
623
624 spin_unlock_irq(&dev_priv->irq_lock);
625}
626
627/*
628 * This timing diagram depicts the video signal in and
629 * around the vertical blanking period.
630 *
631 * Assumptions about the fictitious mode used in this example:
632 * vblank_start >= 3
633 * vsync_start = vblank_start + 1
634 * vsync_end = vblank_start + 2
635 * vtotal = vblank_start + 3
636 *
637 * start of vblank:
638 * latch double buffered registers
639 * increment frame counter (ctg+)
640 * generate start of vblank interrupt (gen4+)
641 * |
642 * | frame start:
643 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
644 * | may be shifted forward 1-3 extra lines via PIPECONF
645 * | |
646 * | | start of vsync:
647 * | | generate vsync interrupt
648 * | | |
649 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
650 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
651 * ----va---> <-----------------vb--------------------> <--------va-------------
652 * | | <----vs-----> |
653 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
654 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
655 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
656 * | | |
657 * last visible pixel first visible pixel
658 * | increment frame counter (gen3/4)
659 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
660 *
661 * x = horizontal active
662 * _ = horizontal blanking
663 * hs = horizontal sync
664 * va = vertical active
665 * vb = vertical blanking
666 * vs = vertical sync
667 * vbs = vblank_start (number)
668 *
669 * Summary:
670 * - most events happen at the start of horizontal sync
671 * - frame start happens at the start of horizontal blank, 1-4 lines
672 * (depending on PIPECONF settings) after the start of vblank
673 * - gen3/4 pixel and frame counter are synchronized with the start
674 * of horizontal active on the first line of vertical active
675 */
676
677static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
678{
679 /* Gen2 doesn't have a hardware frame counter */
680 return 0;
681}
682
683/* Called from drm generic code, passed a 'crtc', which
684 * we use as a pipe index
685 */
686static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
687{
688 struct drm_i915_private *dev_priv = dev->dev_private;
689 i915_reg_t high_frame, low_frame;
690 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
691 struct intel_crtc *intel_crtc =
692 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
693 const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
694
695 htotal = mode->crtc_htotal;
696 hsync_start = mode->crtc_hsync_start;
697 vbl_start = mode->crtc_vblank_start;
698 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
699 vbl_start = DIV_ROUND_UP(vbl_start, 2);
700
701 /* Convert to pixel count */
702 vbl_start *= htotal;
703
704 /* Start of vblank event occurs at start of hsync */
705 vbl_start -= htotal - hsync_start;
706
707 high_frame = PIPEFRAME(pipe);
708 low_frame = PIPEFRAMEPIXEL(pipe);
709
710 /*
711 * High & low register fields aren't synchronized, so make sure
712 * we get a low value that's stable across two reads of the high
713 * register.
714 */
715 do {
716 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
717 low = I915_READ(low_frame);
718 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
719 } while (high1 != high2);
720
721 high1 >>= PIPE_FRAME_HIGH_SHIFT;
722 pixel = low & PIPE_PIXEL_MASK;
723 low >>= PIPE_FRAME_LOW_SHIFT;
724
725 /*
726 * The frame counter increments at beginning of active.
727 * Cook up a vblank counter by also checking the pixel
728 * counter against vblank start.
729 */
730 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
731}
732
733static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
734{
735 struct drm_i915_private *dev_priv = dev->dev_private;
736
737 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
738}
739
740/* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
741static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
742{
743 struct drm_device *dev = crtc->base.dev;
744 struct drm_i915_private *dev_priv = dev->dev_private;
745 const struct drm_display_mode *mode = &crtc->base.hwmode;
746 enum pipe pipe = crtc->pipe;
747 int position, vtotal;
748
749 vtotal = mode->crtc_vtotal;
750 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
751 vtotal /= 2;
752
753 if (IS_GEN2(dev))
754 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
755 else
756 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
757
758 /*
759 * On HSW, the DSL reg (0x70000) appears to return 0 if we
760 * read it just before the start of vblank. So try it again
761 * so we don't accidentally end up spanning a vblank frame
762 * increment, causing the pipe_update_end() code to squak at us.
763 *
764 * The nature of this problem means we can't simply check the ISR
765 * bit and return the vblank start value; nor can we use the scanline
766 * debug register in the transcoder as it appears to have the same
767 * problem. We may need to extend this to include other platforms,
768 * but so far testing only shows the problem on HSW.
769 */
770 if (HAS_DDI(dev) && !position) {
771 int i, temp;
772
773 for (i = 0; i < 100; i++) {
774 udelay(1);
775 temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
776 DSL_LINEMASK_GEN3;
777 if (temp != position) {
778 position = temp;
779 break;
780 }
781 }
782 }
783
784 /*
785 * See update_scanline_offset() for the details on the
786 * scanline_offset adjustment.
787 */
788 return (position + crtc->scanline_offset) % vtotal;
789}
790
791static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
792 unsigned int flags, int *vpos, int *hpos,
793 ktime_t *stime, ktime_t *etime,
794 const struct drm_display_mode *mode)
795{
796 struct drm_i915_private *dev_priv = dev->dev_private;
797 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
799 int position;
800 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
801 bool in_vbl = true;
802 int ret = 0;
803 unsigned long irqflags;
804
805 if (WARN_ON(!mode->crtc_clock)) {
806 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
807 "pipe %c\n", pipe_name(pipe));
808 return 0;
809 }
810
811 htotal = mode->crtc_htotal;
812 hsync_start = mode->crtc_hsync_start;
813 vtotal = mode->crtc_vtotal;
814 vbl_start = mode->crtc_vblank_start;
815 vbl_end = mode->crtc_vblank_end;
816
817 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
818 vbl_start = DIV_ROUND_UP(vbl_start, 2);
819 vbl_end /= 2;
820 vtotal /= 2;
821 }
822
823 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
824
825 /*
826 * Lock uncore.lock, as we will do multiple timing critical raw
827 * register reads, potentially with preemption disabled, so the
828 * following code must not block on uncore.lock.
829 */
830 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
831
832 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
833
834 /* Get optional system timestamp before query. */
835 if (stime)
836 *stime = ktime_get();
837
838 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
839 /* No obvious pixelcount register. Only query vertical
840 * scanout position from Display scan line register.
841 */
842 position = __intel_get_crtc_scanline(intel_crtc);
843 } else {
844 /* Have access to pixelcount since start of frame.
845 * We can split this into vertical and horizontal
846 * scanout position.
847 */
848 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
849
850 /* convert to pixel counts */
851 vbl_start *= htotal;
852 vbl_end *= htotal;
853 vtotal *= htotal;
854
855 /*
856 * In interlaced modes, the pixel counter counts all pixels,
857 * so one field will have htotal more pixels. In order to avoid
858 * the reported position from jumping backwards when the pixel
859 * counter is beyond the length of the shorter field, just
860 * clamp the position the length of the shorter field. This
861 * matches how the scanline counter based position works since
862 * the scanline counter doesn't count the two half lines.
863 */
864 if (position >= vtotal)
865 position = vtotal - 1;
866
867 /*
868 * Start of vblank interrupt is triggered at start of hsync,
869 * just prior to the first active line of vblank. However we
870 * consider lines to start at the leading edge of horizontal
871 * active. So, should we get here before we've crossed into
872 * the horizontal active of the first line in vblank, we would
873 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
874 * always add htotal-hsync_start to the current pixel position.
875 */
876 position = (position + htotal - hsync_start) % vtotal;
877 }
878
879 /* Get optional system timestamp after query. */
880 if (etime)
881 *etime = ktime_get();
882
883 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
884
885 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
886
887 in_vbl = position >= vbl_start && position < vbl_end;
888
889 /*
890 * While in vblank, position will be negative
891 * counting up towards 0 at vbl_end. And outside
892 * vblank, position will be positive counting
893 * up since vbl_end.
894 */
895 if (position >= vbl_start)
896 position -= vbl_end;
897 else
898 position += vtotal - vbl_end;
899
900 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
901 *vpos = position;
902 *hpos = 0;
903 } else {
904 *vpos = position / htotal;
905 *hpos = position - (*vpos * htotal);
906 }
907
908 /* In vblank? */
909 if (in_vbl)
910 ret |= DRM_SCANOUTPOS_IN_VBLANK;
911
912 return ret;
913}
914
915int intel_get_crtc_scanline(struct intel_crtc *crtc)
916{
917 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
918 unsigned long irqflags;
919 int position;
920
921 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
922 position = __intel_get_crtc_scanline(crtc);
923 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
924
925 return position;
926}
927
928static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
929 int *max_error,
930 struct timeval *vblank_time,
931 unsigned flags)
932{
933 struct drm_crtc *crtc;
934
935 if (pipe >= INTEL_INFO(dev)->num_pipes) {
936 DRM_ERROR("Invalid crtc %u\n", pipe);
937 return -EINVAL;
938 }
939
940 /* Get drm_crtc to timestamp: */
941 crtc = intel_get_crtc_for_pipe(dev, pipe);
942 if (crtc == NULL) {
943 DRM_ERROR("Invalid crtc %u\n", pipe);
944 return -EINVAL;
945 }
946
947 if (!crtc->hwmode.crtc_clock) {
948 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
949 return -EBUSY;
950 }
951
952 /* Helper routine in DRM core does all the work: */
953 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
954 vblank_time, flags,
955 &crtc->hwmode);
956}
957
958static void ironlake_rps_change_irq_handler(struct drm_device *dev)
959{
960 struct drm_i915_private *dev_priv = dev->dev_private;
961 u32 busy_up, busy_down, max_avg, min_avg;
962 u8 new_delay;
963
964 spin_lock(&mchdev_lock);
965
966 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
967
968 new_delay = dev_priv->ips.cur_delay;
969
970 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
971 busy_up = I915_READ(RCPREVBSYTUPAVG);
972 busy_down = I915_READ(RCPREVBSYTDNAVG);
973 max_avg = I915_READ(RCBMAXAVG);
974 min_avg = I915_READ(RCBMINAVG);
975
976 /* Handle RCS change request from hw */
977 if (busy_up > max_avg) {
978 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
979 new_delay = dev_priv->ips.cur_delay - 1;
980 if (new_delay < dev_priv->ips.max_delay)
981 new_delay = dev_priv->ips.max_delay;
982 } else if (busy_down < min_avg) {
983 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
984 new_delay = dev_priv->ips.cur_delay + 1;
985 if (new_delay > dev_priv->ips.min_delay)
986 new_delay = dev_priv->ips.min_delay;
987 }
988
989 if (ironlake_set_drps(dev, new_delay))
990 dev_priv->ips.cur_delay = new_delay;
991
992 spin_unlock(&mchdev_lock);
993
994 return;
995}
996
997static void notify_ring(struct intel_engine_cs *ring)
998{
999 if (!intel_ring_initialized(ring))
1000 return;
1001
1002 trace_i915_gem_request_notify(ring);
1003
1004 wake_up_all(&ring->irq_queue);
1005}
1006
1007static void vlv_c0_read(struct drm_i915_private *dev_priv,
1008 struct intel_rps_ei *ei)
1009{
1010 ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1011 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1012 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1013}
1014
1015static bool vlv_c0_above(struct drm_i915_private *dev_priv,
1016 const struct intel_rps_ei *old,
1017 const struct intel_rps_ei *now,
1018 int threshold)
1019{
1020 u64 time, c0;
1021 unsigned int mul = 100;
1022
1023 if (old->cz_clock == 0)
1024 return false;
1025
1026 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1027 mul <<= 8;
1028
1029 time = now->cz_clock - old->cz_clock;
1030 time *= threshold * dev_priv->czclk_freq;
1031
1032 /* Workload can be split between render + media, e.g. SwapBuffers
1033 * being blitted in X after being rendered in mesa. To account for
1034 * this we need to combine both engines into our activity counter.
1035 */
1036 c0 = now->render_c0 - old->render_c0;
1037 c0 += now->media_c0 - old->media_c0;
1038 c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1039
1040 return c0 >= time;
1041}
1042
1043void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1044{
1045 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1046 dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1047}
1048
1049static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1050{
1051 struct intel_rps_ei now;
1052 u32 events = 0;
1053
1054 if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1055 return 0;
1056
1057 vlv_c0_read(dev_priv, &now);
1058 if (now.cz_clock == 0)
1059 return 0;
1060
1061 if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1062 if (!vlv_c0_above(dev_priv,
1063 &dev_priv->rps.down_ei, &now,
1064 dev_priv->rps.down_threshold))
1065 events |= GEN6_PM_RP_DOWN_THRESHOLD;
1066 dev_priv->rps.down_ei = now;
1067 }
1068
1069 if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1070 if (vlv_c0_above(dev_priv,
1071 &dev_priv->rps.up_ei, &now,
1072 dev_priv->rps.up_threshold))
1073 events |= GEN6_PM_RP_UP_THRESHOLD;
1074 dev_priv->rps.up_ei = now;
1075 }
1076
1077 return events;
1078}
1079
1080static bool any_waiters(struct drm_i915_private *dev_priv)
1081{
1082 struct intel_engine_cs *ring;
1083 int i;
1084
1085 for_each_ring(ring, dev_priv, i)
1086 if (ring->irq_refcount)
1087 return true;
1088
1089 return false;
1090}
1091
1092static void gen6_pm_rps_work(struct work_struct *work)
1093{
1094 struct drm_i915_private *dev_priv =
1095 container_of(work, struct drm_i915_private, rps.work);
1096 bool client_boost;
1097 int new_delay, adj, min, max;
1098 u32 pm_iir;
1099
1100 spin_lock_irq(&dev_priv->irq_lock);
1101 /* Speed up work cancelation during disabling rps interrupts. */
1102 if (!dev_priv->rps.interrupts_enabled) {
1103 spin_unlock_irq(&dev_priv->irq_lock);
1104 return;
1105 }
1106
1107 /*
1108 * The RPS work is synced during runtime suspend, we don't require a
1109 * wakeref. TODO: instead of disabling the asserts make sure that we
1110 * always hold an RPM reference while the work is running.
1111 */
1112 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1113
1114 pm_iir = dev_priv->rps.pm_iir;
1115 dev_priv->rps.pm_iir = 0;
1116 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1117 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1118 client_boost = dev_priv->rps.client_boost;
1119 dev_priv->rps.client_boost = false;
1120 spin_unlock_irq(&dev_priv->irq_lock);
1121
1122 /* Make sure we didn't queue anything we're not going to process. */
1123 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1124
1125 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1126 goto out;
1127
1128 mutex_lock(&dev_priv->rps.hw_lock);
1129
1130 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1131
1132 adj = dev_priv->rps.last_adj;
1133 new_delay = dev_priv->rps.cur_freq;
1134 min = dev_priv->rps.min_freq_softlimit;
1135 max = dev_priv->rps.max_freq_softlimit;
1136
1137 if (client_boost) {
1138 new_delay = dev_priv->rps.max_freq_softlimit;
1139 adj = 0;
1140 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1141 if (adj > 0)
1142 adj *= 2;
1143 else /* CHV needs even encode values */
1144 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1145 /*
1146 * For better performance, jump directly
1147 * to RPe if we're below it.
1148 */
1149 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1150 new_delay = dev_priv->rps.efficient_freq;
1151 adj = 0;
1152 }
1153 } else if (any_waiters(dev_priv)) {
1154 adj = 0;
1155 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1156 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1157 new_delay = dev_priv->rps.efficient_freq;
1158 else
1159 new_delay = dev_priv->rps.min_freq_softlimit;
1160 adj = 0;
1161 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1162 if (adj < 0)
1163 adj *= 2;
1164 else /* CHV needs even encode values */
1165 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1166 } else { /* unknown event */
1167 adj = 0;
1168 }
1169
1170 dev_priv->rps.last_adj = adj;
1171
1172 /* sysfs frequency interfaces may have snuck in while servicing the
1173 * interrupt
1174 */
1175 new_delay += adj;
1176 new_delay = clamp_t(int, new_delay, min, max);
1177
1178 intel_set_rps(dev_priv->dev, new_delay);
1179
1180 mutex_unlock(&dev_priv->rps.hw_lock);
1181out:
1182 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1183}
1184
1185
1186/**
1187 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1188 * occurred.
1189 * @work: workqueue struct
1190 *
1191 * Doesn't actually do anything except notify userspace. As a consequence of
1192 * this event, userspace should try to remap the bad rows since statistically
1193 * it is likely the same row is more likely to go bad again.
1194 */
1195static void ivybridge_parity_work(struct work_struct *work)
1196{
1197 struct drm_i915_private *dev_priv =
1198 container_of(work, struct drm_i915_private, l3_parity.error_work);
1199 u32 error_status, row, bank, subbank;
1200 char *parity_event[6];
1201 uint32_t misccpctl;
1202 uint8_t slice = 0;
1203
1204 /* We must turn off DOP level clock gating to access the L3 registers.
1205 * In order to prevent a get/put style interface, acquire struct mutex
1206 * any time we access those registers.
1207 */
1208 mutex_lock(&dev_priv->dev->struct_mutex);
1209
1210 /* If we've screwed up tracking, just let the interrupt fire again */
1211 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1212 goto out;
1213
1214 misccpctl = I915_READ(GEN7_MISCCPCTL);
1215 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1216 POSTING_READ(GEN7_MISCCPCTL);
1217
1218 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1219 i915_reg_t reg;
1220
1221 slice--;
1222 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1223 break;
1224
1225 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1226
1227 reg = GEN7_L3CDERRST1(slice);
1228
1229 error_status = I915_READ(reg);
1230 row = GEN7_PARITY_ERROR_ROW(error_status);
1231 bank = GEN7_PARITY_ERROR_BANK(error_status);
1232 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1233
1234 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1235 POSTING_READ(reg);
1236
1237 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1238 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1239 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1240 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1241 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1242 parity_event[5] = NULL;
1243
1244 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1245 KOBJ_CHANGE, parity_event);
1246
1247 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1248 slice, row, bank, subbank);
1249
1250 kfree(parity_event[4]);
1251 kfree(parity_event[3]);
1252 kfree(parity_event[2]);
1253 kfree(parity_event[1]);
1254 }
1255
1256 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1257
1258out:
1259 WARN_ON(dev_priv->l3_parity.which_slice);
1260 spin_lock_irq(&dev_priv->irq_lock);
1261 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1262 spin_unlock_irq(&dev_priv->irq_lock);
1263
1264 mutex_unlock(&dev_priv->dev->struct_mutex);
1265}
1266
1267static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1268{
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1270
1271 if (!HAS_L3_DPF(dev))
1272 return;
1273
1274 spin_lock(&dev_priv->irq_lock);
1275 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1276 spin_unlock(&dev_priv->irq_lock);
1277
1278 iir &= GT_PARITY_ERROR(dev);
1279 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1280 dev_priv->l3_parity.which_slice |= 1 << 1;
1281
1282 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1283 dev_priv->l3_parity.which_slice |= 1 << 0;
1284
1285 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1286}
1287
1288static void ilk_gt_irq_handler(struct drm_device *dev,
1289 struct drm_i915_private *dev_priv,
1290 u32 gt_iir)
1291{
1292 if (gt_iir &
1293 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1294 notify_ring(&dev_priv->ring[RCS]);
1295 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1296 notify_ring(&dev_priv->ring[VCS]);
1297}
1298
1299static void snb_gt_irq_handler(struct drm_device *dev,
1300 struct drm_i915_private *dev_priv,
1301 u32 gt_iir)
1302{
1303
1304 if (gt_iir &
1305 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1306 notify_ring(&dev_priv->ring[RCS]);
1307 if (gt_iir & GT_BSD_USER_INTERRUPT)
1308 notify_ring(&dev_priv->ring[VCS]);
1309 if (gt_iir & GT_BLT_USER_INTERRUPT)
1310 notify_ring(&dev_priv->ring[BCS]);
1311
1312 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1313 GT_BSD_CS_ERROR_INTERRUPT |
1314 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1315 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1316
1317 if (gt_iir & GT_PARITY_ERROR(dev))
1318 ivybridge_parity_error_irq_handler(dev, gt_iir);
1319}
1320
1321static __always_inline void
1322gen8_cs_irq_handler(struct intel_engine_cs *ring, u32 iir, int test_shift)
1323{
1324 if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1325 notify_ring(ring);
1326 if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
1327 intel_lrc_irq_handler(ring);
1328}
1329
1330static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1331 u32 master_ctl)
1332{
1333 irqreturn_t ret = IRQ_NONE;
1334
1335 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1336 u32 iir = I915_READ_FW(GEN8_GT_IIR(0));
1337 if (iir) {
1338 I915_WRITE_FW(GEN8_GT_IIR(0), iir);
1339 ret = IRQ_HANDLED;
1340
1341 gen8_cs_irq_handler(&dev_priv->ring[RCS],
1342 iir, GEN8_RCS_IRQ_SHIFT);
1343
1344 gen8_cs_irq_handler(&dev_priv->ring[BCS],
1345 iir, GEN8_BCS_IRQ_SHIFT);
1346 } else
1347 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1348 }
1349
1350 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1351 u32 iir = I915_READ_FW(GEN8_GT_IIR(1));
1352 if (iir) {
1353 I915_WRITE_FW(GEN8_GT_IIR(1), iir);
1354 ret = IRQ_HANDLED;
1355
1356 gen8_cs_irq_handler(&dev_priv->ring[VCS],
1357 iir, GEN8_VCS1_IRQ_SHIFT);
1358
1359 gen8_cs_irq_handler(&dev_priv->ring[VCS2],
1360 iir, GEN8_VCS2_IRQ_SHIFT);
1361 } else
1362 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1363 }
1364
1365 if (master_ctl & GEN8_GT_VECS_IRQ) {
1366 u32 iir = I915_READ_FW(GEN8_GT_IIR(3));
1367 if (iir) {
1368 I915_WRITE_FW(GEN8_GT_IIR(3), iir);
1369 ret = IRQ_HANDLED;
1370
1371 gen8_cs_irq_handler(&dev_priv->ring[VECS],
1372 iir, GEN8_VECS_IRQ_SHIFT);
1373 } else
1374 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1375 }
1376
1377 if (master_ctl & GEN8_GT_PM_IRQ) {
1378 u32 iir = I915_READ_FW(GEN8_GT_IIR(2));
1379 if (iir & dev_priv->pm_rps_events) {
1380 I915_WRITE_FW(GEN8_GT_IIR(2),
1381 iir & dev_priv->pm_rps_events);
1382 ret = IRQ_HANDLED;
1383 gen6_rps_irq_handler(dev_priv, iir);
1384 } else
1385 DRM_ERROR("The master control interrupt lied (PM)!\n");
1386 }
1387
1388 return ret;
1389}
1390
1391static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1392{
1393 switch (port) {
1394 case PORT_A:
1395 return val & PORTA_HOTPLUG_LONG_DETECT;
1396 case PORT_B:
1397 return val & PORTB_HOTPLUG_LONG_DETECT;
1398 case PORT_C:
1399 return val & PORTC_HOTPLUG_LONG_DETECT;
1400 default:
1401 return false;
1402 }
1403}
1404
1405static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1406{
1407 switch (port) {
1408 case PORT_E:
1409 return val & PORTE_HOTPLUG_LONG_DETECT;
1410 default:
1411 return false;
1412 }
1413}
1414
1415static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1416{
1417 switch (port) {
1418 case PORT_A:
1419 return val & PORTA_HOTPLUG_LONG_DETECT;
1420 case PORT_B:
1421 return val & PORTB_HOTPLUG_LONG_DETECT;
1422 case PORT_C:
1423 return val & PORTC_HOTPLUG_LONG_DETECT;
1424 case PORT_D:
1425 return val & PORTD_HOTPLUG_LONG_DETECT;
1426 default:
1427 return false;
1428 }
1429}
1430
1431static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1432{
1433 switch (port) {
1434 case PORT_A:
1435 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1436 default:
1437 return false;
1438 }
1439}
1440
1441static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1442{
1443 switch (port) {
1444 case PORT_B:
1445 return val & PORTB_HOTPLUG_LONG_DETECT;
1446 case PORT_C:
1447 return val & PORTC_HOTPLUG_LONG_DETECT;
1448 case PORT_D:
1449 return val & PORTD_HOTPLUG_LONG_DETECT;
1450 default:
1451 return false;
1452 }
1453}
1454
1455static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1456{
1457 switch (port) {
1458 case PORT_B:
1459 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1460 case PORT_C:
1461 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1462 case PORT_D:
1463 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1464 default:
1465 return false;
1466 }
1467}
1468
1469/*
1470 * Get a bit mask of pins that have triggered, and which ones may be long.
1471 * This can be called multiple times with the same masks to accumulate
1472 * hotplug detection results from several registers.
1473 *
1474 * Note that the caller is expected to zero out the masks initially.
1475 */
1476static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1477 u32 hotplug_trigger, u32 dig_hotplug_reg,
1478 const u32 hpd[HPD_NUM_PINS],
1479 bool long_pulse_detect(enum port port, u32 val))
1480{
1481 enum port port;
1482 int i;
1483
1484 for_each_hpd_pin(i) {
1485 if ((hpd[i] & hotplug_trigger) == 0)
1486 continue;
1487
1488 *pin_mask |= BIT(i);
1489
1490 if (!intel_hpd_pin_to_port(i, &port))
1491 continue;
1492
1493 if (long_pulse_detect(port, dig_hotplug_reg))
1494 *long_mask |= BIT(i);
1495 }
1496
1497 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1498 hotplug_trigger, dig_hotplug_reg, *pin_mask);
1499
1500}
1501
1502static void gmbus_irq_handler(struct drm_device *dev)
1503{
1504 struct drm_i915_private *dev_priv = dev->dev_private;
1505
1506 wake_up_all(&dev_priv->gmbus_wait_queue);
1507}
1508
1509static void dp_aux_irq_handler(struct drm_device *dev)
1510{
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512
1513 wake_up_all(&dev_priv->gmbus_wait_queue);
1514}
1515
1516#if defined(CONFIG_DEBUG_FS)
1517static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1518 uint32_t crc0, uint32_t crc1,
1519 uint32_t crc2, uint32_t crc3,
1520 uint32_t crc4)
1521{
1522 struct drm_i915_private *dev_priv = dev->dev_private;
1523 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1524 struct intel_pipe_crc_entry *entry;
1525 int head, tail;
1526
1527 spin_lock(&pipe_crc->lock);
1528
1529 if (!pipe_crc->entries) {
1530 spin_unlock(&pipe_crc->lock);
1531 DRM_DEBUG_KMS("spurious interrupt\n");
1532 return;
1533 }
1534
1535 head = pipe_crc->head;
1536 tail = pipe_crc->tail;
1537
1538 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1539 spin_unlock(&pipe_crc->lock);
1540 DRM_ERROR("CRC buffer overflowing\n");
1541 return;
1542 }
1543
1544 entry = &pipe_crc->entries[head];
1545
1546 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1547 entry->crc[0] = crc0;
1548 entry->crc[1] = crc1;
1549 entry->crc[2] = crc2;
1550 entry->crc[3] = crc3;
1551 entry->crc[4] = crc4;
1552
1553 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1554 pipe_crc->head = head;
1555
1556 spin_unlock(&pipe_crc->lock);
1557
1558 wake_up_interruptible(&pipe_crc->wq);
1559}
1560#else
1561static inline void
1562display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1563 uint32_t crc0, uint32_t crc1,
1564 uint32_t crc2, uint32_t crc3,
1565 uint32_t crc4) {}
1566#endif
1567
1568
1569static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1570{
1571 struct drm_i915_private *dev_priv = dev->dev_private;
1572
1573 display_pipe_crc_irq_handler(dev, pipe,
1574 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1575 0, 0, 0, 0);
1576}
1577
1578static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1579{
1580 struct drm_i915_private *dev_priv = dev->dev_private;
1581
1582 display_pipe_crc_irq_handler(dev, pipe,
1583 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1584 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1585 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1586 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1587 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1588}
1589
1590static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1591{
1592 struct drm_i915_private *dev_priv = dev->dev_private;
1593 uint32_t res1, res2;
1594
1595 if (INTEL_INFO(dev)->gen >= 3)
1596 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1597 else
1598 res1 = 0;
1599
1600 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1601 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1602 else
1603 res2 = 0;
1604
1605 display_pipe_crc_irq_handler(dev, pipe,
1606 I915_READ(PIPE_CRC_RES_RED(pipe)),
1607 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1608 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1609 res1, res2);
1610}
1611
1612/* The RPS events need forcewake, so we add them to a work queue and mask their
1613 * IMR bits until the work is done. Other interrupts can be processed without
1614 * the work queue. */
1615static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1616{
1617 if (pm_iir & dev_priv->pm_rps_events) {
1618 spin_lock(&dev_priv->irq_lock);
1619 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1620 if (dev_priv->rps.interrupts_enabled) {
1621 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1622 queue_work(dev_priv->wq, &dev_priv->rps.work);
1623 }
1624 spin_unlock(&dev_priv->irq_lock);
1625 }
1626
1627 if (INTEL_INFO(dev_priv)->gen >= 8)
1628 return;
1629
1630 if (HAS_VEBOX(dev_priv->dev)) {
1631 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1632 notify_ring(&dev_priv->ring[VECS]);
1633
1634 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1635 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1636 }
1637}
1638
1639static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1640{
1641 if (!drm_handle_vblank(dev, pipe))
1642 return false;
1643
1644 return true;
1645}
1646
1647static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1648{
1649 struct drm_i915_private *dev_priv = dev->dev_private;
1650 u32 pipe_stats[I915_MAX_PIPES] = { };
1651 int pipe;
1652
1653 spin_lock(&dev_priv->irq_lock);
1654
1655 if (!dev_priv->display_irqs_enabled) {
1656 spin_unlock(&dev_priv->irq_lock);
1657 return;
1658 }
1659
1660 for_each_pipe(dev_priv, pipe) {
1661 i915_reg_t reg;
1662 u32 mask, iir_bit = 0;
1663
1664 /*
1665 * PIPESTAT bits get signalled even when the interrupt is
1666 * disabled with the mask bits, and some of the status bits do
1667 * not generate interrupts at all (like the underrun bit). Hence
1668 * we need to be careful that we only handle what we want to
1669 * handle.
1670 */
1671
1672 /* fifo underruns are filterered in the underrun handler. */
1673 mask = PIPE_FIFO_UNDERRUN_STATUS;
1674
1675 switch (pipe) {
1676 case PIPE_A:
1677 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1678 break;
1679 case PIPE_B:
1680 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1681 break;
1682 case PIPE_C:
1683 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1684 break;
1685 }
1686 if (iir & iir_bit)
1687 mask |= dev_priv->pipestat_irq_mask[pipe];
1688
1689 if (!mask)
1690 continue;
1691
1692 reg = PIPESTAT(pipe);
1693 mask |= PIPESTAT_INT_ENABLE_MASK;
1694 pipe_stats[pipe] = I915_READ(reg) & mask;
1695
1696 /*
1697 * Clear the PIPE*STAT regs before the IIR
1698 */
1699 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1700 PIPESTAT_INT_STATUS_MASK))
1701 I915_WRITE(reg, pipe_stats[pipe]);
1702 }
1703 spin_unlock(&dev_priv->irq_lock);
1704
1705 for_each_pipe(dev_priv, pipe) {
1706 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1707 intel_pipe_handle_vblank(dev, pipe))
1708 intel_check_page_flip(dev, pipe);
1709
1710 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1711 intel_prepare_page_flip(dev, pipe);
1712 intel_finish_page_flip(dev, pipe);
1713 }
1714
1715 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1716 i9xx_pipe_crc_irq_handler(dev, pipe);
1717
1718 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1719 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1720 }
1721
1722 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1723 gmbus_irq_handler(dev);
1724}
1725
1726static void i9xx_hpd_irq_handler(struct drm_device *dev)
1727{
1728 struct drm_i915_private *dev_priv = dev->dev_private;
1729 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1730 u32 pin_mask = 0, long_mask = 0;
1731
1732 if (!hotplug_status)
1733 return;
1734
1735 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1736 /*
1737 * Make sure hotplug status is cleared before we clear IIR, or else we
1738 * may miss hotplug events.
1739 */
1740 POSTING_READ(PORT_HOTPLUG_STAT);
1741
1742 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1743 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1744
1745 if (hotplug_trigger) {
1746 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1747 hotplug_trigger, hpd_status_g4x,
1748 i9xx_port_hotplug_long_detect);
1749
1750 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1751 }
1752
1753 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1754 dp_aux_irq_handler(dev);
1755 } else {
1756 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1757
1758 if (hotplug_trigger) {
1759 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1760 hotplug_trigger, hpd_status_i915,
1761 i9xx_port_hotplug_long_detect);
1762 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1763 }
1764 }
1765}
1766
1767static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1768{
1769 struct drm_device *dev = arg;
1770 struct drm_i915_private *dev_priv = dev->dev_private;
1771 u32 iir, gt_iir, pm_iir;
1772 irqreturn_t ret = IRQ_NONE;
1773
1774 if (!intel_irqs_enabled(dev_priv))
1775 return IRQ_NONE;
1776
1777 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1778 disable_rpm_wakeref_asserts(dev_priv);
1779
1780 while (true) {
1781 /* Find, clear, then process each source of interrupt */
1782
1783 gt_iir = I915_READ(GTIIR);
1784 if (gt_iir)
1785 I915_WRITE(GTIIR, gt_iir);
1786
1787 pm_iir = I915_READ(GEN6_PMIIR);
1788 if (pm_iir)
1789 I915_WRITE(GEN6_PMIIR, pm_iir);
1790
1791 iir = I915_READ(VLV_IIR);
1792 if (iir) {
1793 /* Consume port before clearing IIR or we'll miss events */
1794 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1795 i9xx_hpd_irq_handler(dev);
1796 I915_WRITE(VLV_IIR, iir);
1797 }
1798
1799 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1800 goto out;
1801
1802 ret = IRQ_HANDLED;
1803
1804 if (gt_iir)
1805 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1806 if (pm_iir)
1807 gen6_rps_irq_handler(dev_priv, pm_iir);
1808 /* Call regardless, as some status bits might not be
1809 * signalled in iir */
1810 valleyview_pipestat_irq_handler(dev, iir);
1811 }
1812
1813out:
1814 enable_rpm_wakeref_asserts(dev_priv);
1815
1816 return ret;
1817}
1818
1819static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1820{
1821 struct drm_device *dev = arg;
1822 struct drm_i915_private *dev_priv = dev->dev_private;
1823 u32 master_ctl, iir;
1824 irqreturn_t ret = IRQ_NONE;
1825
1826 if (!intel_irqs_enabled(dev_priv))
1827 return IRQ_NONE;
1828
1829 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1830 disable_rpm_wakeref_asserts(dev_priv);
1831
1832 do {
1833 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1834 iir = I915_READ(VLV_IIR);
1835
1836 if (master_ctl == 0 && iir == 0)
1837 break;
1838
1839 ret = IRQ_HANDLED;
1840
1841 I915_WRITE(GEN8_MASTER_IRQ, 0);
1842
1843 /* Find, clear, then process each source of interrupt */
1844
1845 if (iir) {
1846 /* Consume port before clearing IIR or we'll miss events */
1847 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1848 i9xx_hpd_irq_handler(dev);
1849 I915_WRITE(VLV_IIR, iir);
1850 }
1851
1852 gen8_gt_irq_handler(dev_priv, master_ctl);
1853
1854 /* Call regardless, as some status bits might not be
1855 * signalled in iir */
1856 valleyview_pipestat_irq_handler(dev, iir);
1857
1858 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1859 POSTING_READ(GEN8_MASTER_IRQ);
1860 } while (0);
1861
1862 enable_rpm_wakeref_asserts(dev_priv);
1863
1864 return ret;
1865}
1866
1867static void ibx_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
1868 const u32 hpd[HPD_NUM_PINS])
1869{
1870 struct drm_i915_private *dev_priv = to_i915(dev);
1871 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1872
1873 /*
1874 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1875 * unless we touch the hotplug register, even if hotplug_trigger is
1876 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1877 * errors.
1878 */
1879 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1880 if (!hotplug_trigger) {
1881 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1882 PORTD_HOTPLUG_STATUS_MASK |
1883 PORTC_HOTPLUG_STATUS_MASK |
1884 PORTB_HOTPLUG_STATUS_MASK;
1885 dig_hotplug_reg &= ~mask;
1886 }
1887
1888 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1889 if (!hotplug_trigger)
1890 return;
1891
1892 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1893 dig_hotplug_reg, hpd,
1894 pch_port_hotplug_long_detect);
1895
1896 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1897}
1898
1899static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1900{
1901 struct drm_i915_private *dev_priv = dev->dev_private;
1902 int pipe;
1903 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1904
1905 ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1906
1907 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1908 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1909 SDE_AUDIO_POWER_SHIFT);
1910 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1911 port_name(port));
1912 }
1913
1914 if (pch_iir & SDE_AUX_MASK)
1915 dp_aux_irq_handler(dev);
1916
1917 if (pch_iir & SDE_GMBUS)
1918 gmbus_irq_handler(dev);
1919
1920 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1921 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1922
1923 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1924 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1925
1926 if (pch_iir & SDE_POISON)
1927 DRM_ERROR("PCH poison interrupt\n");
1928
1929 if (pch_iir & SDE_FDI_MASK)
1930 for_each_pipe(dev_priv, pipe)
1931 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1932 pipe_name(pipe),
1933 I915_READ(FDI_RX_IIR(pipe)));
1934
1935 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1936 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1937
1938 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1939 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1940
1941 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1942 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1943
1944 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1945 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1946}
1947
1948static void ivb_err_int_handler(struct drm_device *dev)
1949{
1950 struct drm_i915_private *dev_priv = dev->dev_private;
1951 u32 err_int = I915_READ(GEN7_ERR_INT);
1952 enum pipe pipe;
1953
1954 if (err_int & ERR_INT_POISON)
1955 DRM_ERROR("Poison interrupt\n");
1956
1957 for_each_pipe(dev_priv, pipe) {
1958 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1959 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1960
1961 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1962 if (IS_IVYBRIDGE(dev))
1963 ivb_pipe_crc_irq_handler(dev, pipe);
1964 else
1965 hsw_pipe_crc_irq_handler(dev, pipe);
1966 }
1967 }
1968
1969 I915_WRITE(GEN7_ERR_INT, err_int);
1970}
1971
1972static void cpt_serr_int_handler(struct drm_device *dev)
1973{
1974 struct drm_i915_private *dev_priv = dev->dev_private;
1975 u32 serr_int = I915_READ(SERR_INT);
1976
1977 if (serr_int & SERR_INT_POISON)
1978 DRM_ERROR("PCH poison interrupt\n");
1979
1980 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1981 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1982
1983 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1984 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1985
1986 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1987 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
1988
1989 I915_WRITE(SERR_INT, serr_int);
1990}
1991
1992static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1993{
1994 struct drm_i915_private *dev_priv = dev->dev_private;
1995 int pipe;
1996 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1997
1998 ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1999
2000 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2001 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2002 SDE_AUDIO_POWER_SHIFT_CPT);
2003 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2004 port_name(port));
2005 }
2006
2007 if (pch_iir & SDE_AUX_MASK_CPT)
2008 dp_aux_irq_handler(dev);
2009
2010 if (pch_iir & SDE_GMBUS_CPT)
2011 gmbus_irq_handler(dev);
2012
2013 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2014 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2015
2016 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2017 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2018
2019 if (pch_iir & SDE_FDI_MASK_CPT)
2020 for_each_pipe(dev_priv, pipe)
2021 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2022 pipe_name(pipe),
2023 I915_READ(FDI_RX_IIR(pipe)));
2024
2025 if (pch_iir & SDE_ERROR_CPT)
2026 cpt_serr_int_handler(dev);
2027}
2028
2029static void spt_irq_handler(struct drm_device *dev, u32 pch_iir)
2030{
2031 struct drm_i915_private *dev_priv = dev->dev_private;
2032 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2033 ~SDE_PORTE_HOTPLUG_SPT;
2034 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2035 u32 pin_mask = 0, long_mask = 0;
2036
2037 if (hotplug_trigger) {
2038 u32 dig_hotplug_reg;
2039
2040 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2041 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2042
2043 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2044 dig_hotplug_reg, hpd_spt,
2045 spt_port_hotplug_long_detect);
2046 }
2047
2048 if (hotplug2_trigger) {
2049 u32 dig_hotplug_reg;
2050
2051 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2052 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2053
2054 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2055 dig_hotplug_reg, hpd_spt,
2056 spt_port_hotplug2_long_detect);
2057 }
2058
2059 if (pin_mask)
2060 intel_hpd_irq_handler(dev, pin_mask, long_mask);
2061
2062 if (pch_iir & SDE_GMBUS_CPT)
2063 gmbus_irq_handler(dev);
2064}
2065
2066static void ilk_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
2067 const u32 hpd[HPD_NUM_PINS])
2068{
2069 struct drm_i915_private *dev_priv = to_i915(dev);
2070 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2071
2072 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2073 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2074
2075 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2076 dig_hotplug_reg, hpd,
2077 ilk_port_hotplug_long_detect);
2078
2079 intel_hpd_irq_handler(dev, pin_mask, long_mask);
2080}
2081
2082static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2083{
2084 struct drm_i915_private *dev_priv = dev->dev_private;
2085 enum pipe pipe;
2086 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2087
2088 if (hotplug_trigger)
2089 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ilk);
2090
2091 if (de_iir & DE_AUX_CHANNEL_A)
2092 dp_aux_irq_handler(dev);
2093
2094 if (de_iir & DE_GSE)
2095 intel_opregion_asle_intr(dev);
2096
2097 if (de_iir & DE_POISON)
2098 DRM_ERROR("Poison interrupt\n");
2099
2100 for_each_pipe(dev_priv, pipe) {
2101 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2102 intel_pipe_handle_vblank(dev, pipe))
2103 intel_check_page_flip(dev, pipe);
2104
2105 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2106 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2107
2108 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2109 i9xx_pipe_crc_irq_handler(dev, pipe);
2110
2111 /* plane/pipes map 1:1 on ilk+ */
2112 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2113 intel_prepare_page_flip(dev, pipe);
2114 intel_finish_page_flip_plane(dev, pipe);
2115 }
2116 }
2117
2118 /* check event from PCH */
2119 if (de_iir & DE_PCH_EVENT) {
2120 u32 pch_iir = I915_READ(SDEIIR);
2121
2122 if (HAS_PCH_CPT(dev))
2123 cpt_irq_handler(dev, pch_iir);
2124 else
2125 ibx_irq_handler(dev, pch_iir);
2126
2127 /* should clear PCH hotplug event before clear CPU irq */
2128 I915_WRITE(SDEIIR, pch_iir);
2129 }
2130
2131 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2132 ironlake_rps_change_irq_handler(dev);
2133}
2134
2135static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2136{
2137 struct drm_i915_private *dev_priv = dev->dev_private;
2138 enum pipe pipe;
2139 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2140
2141 if (hotplug_trigger)
2142 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ivb);
2143
2144 if (de_iir & DE_ERR_INT_IVB)
2145 ivb_err_int_handler(dev);
2146
2147 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2148 dp_aux_irq_handler(dev);
2149
2150 if (de_iir & DE_GSE_IVB)
2151 intel_opregion_asle_intr(dev);
2152
2153 for_each_pipe(dev_priv, pipe) {
2154 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2155 intel_pipe_handle_vblank(dev, pipe))
2156 intel_check_page_flip(dev, pipe);
2157
2158 /* plane/pipes map 1:1 on ilk+ */
2159 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2160 intel_prepare_page_flip(dev, pipe);
2161 intel_finish_page_flip_plane(dev, pipe);
2162 }
2163 }
2164
2165 /* check event from PCH */
2166 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2167 u32 pch_iir = I915_READ(SDEIIR);
2168
2169 cpt_irq_handler(dev, pch_iir);
2170
2171 /* clear PCH hotplug event before clear CPU irq */
2172 I915_WRITE(SDEIIR, pch_iir);
2173 }
2174}
2175
2176/*
2177 * To handle irqs with the minimum potential races with fresh interrupts, we:
2178 * 1 - Disable Master Interrupt Control.
2179 * 2 - Find the source(s) of the interrupt.
2180 * 3 - Clear the Interrupt Identity bits (IIR).
2181 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2182 * 5 - Re-enable Master Interrupt Control.
2183 */
2184static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2185{
2186 struct drm_device *dev = arg;
2187 struct drm_i915_private *dev_priv = dev->dev_private;
2188 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2189 irqreturn_t ret = IRQ_NONE;
2190
2191 if (!intel_irqs_enabled(dev_priv))
2192 return IRQ_NONE;
2193
2194 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2195 disable_rpm_wakeref_asserts(dev_priv);
2196
2197 /* disable master interrupt before clearing iir */
2198 de_ier = I915_READ(DEIER);
2199 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2200 POSTING_READ(DEIER);
2201
2202 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2203 * interrupts will will be stored on its back queue, and then we'll be
2204 * able to process them after we restore SDEIER (as soon as we restore
2205 * it, we'll get an interrupt if SDEIIR still has something to process
2206 * due to its back queue). */
2207 if (!HAS_PCH_NOP(dev)) {
2208 sde_ier = I915_READ(SDEIER);
2209 I915_WRITE(SDEIER, 0);
2210 POSTING_READ(SDEIER);
2211 }
2212
2213 /* Find, clear, then process each source of interrupt */
2214
2215 gt_iir = I915_READ(GTIIR);
2216 if (gt_iir) {
2217 I915_WRITE(GTIIR, gt_iir);
2218 ret = IRQ_HANDLED;
2219 if (INTEL_INFO(dev)->gen >= 6)
2220 snb_gt_irq_handler(dev, dev_priv, gt_iir);
2221 else
2222 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2223 }
2224
2225 de_iir = I915_READ(DEIIR);
2226 if (de_iir) {
2227 I915_WRITE(DEIIR, de_iir);
2228 ret = IRQ_HANDLED;
2229 if (INTEL_INFO(dev)->gen >= 7)
2230 ivb_display_irq_handler(dev, de_iir);
2231 else
2232 ilk_display_irq_handler(dev, de_iir);
2233 }
2234
2235 if (INTEL_INFO(dev)->gen >= 6) {
2236 u32 pm_iir = I915_READ(GEN6_PMIIR);
2237 if (pm_iir) {
2238 I915_WRITE(GEN6_PMIIR, pm_iir);
2239 ret = IRQ_HANDLED;
2240 gen6_rps_irq_handler(dev_priv, pm_iir);
2241 }
2242 }
2243
2244 I915_WRITE(DEIER, de_ier);
2245 POSTING_READ(DEIER);
2246 if (!HAS_PCH_NOP(dev)) {
2247 I915_WRITE(SDEIER, sde_ier);
2248 POSTING_READ(SDEIER);
2249 }
2250
2251 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2252 enable_rpm_wakeref_asserts(dev_priv);
2253
2254 return ret;
2255}
2256
2257static void bxt_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
2258 const u32 hpd[HPD_NUM_PINS])
2259{
2260 struct drm_i915_private *dev_priv = to_i915(dev);
2261 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2262
2263 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2264 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2265
2266 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2267 dig_hotplug_reg, hpd,
2268 bxt_port_hotplug_long_detect);
2269
2270 intel_hpd_irq_handler(dev, pin_mask, long_mask);
2271}
2272
2273static irqreturn_t
2274gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2275{
2276 struct drm_device *dev = dev_priv->dev;
2277 irqreturn_t ret = IRQ_NONE;
2278 u32 iir;
2279 enum pipe pipe;
2280
2281 if (master_ctl & GEN8_DE_MISC_IRQ) {
2282 iir = I915_READ(GEN8_DE_MISC_IIR);
2283 if (iir) {
2284 I915_WRITE(GEN8_DE_MISC_IIR, iir);
2285 ret = IRQ_HANDLED;
2286 if (iir & GEN8_DE_MISC_GSE)
2287 intel_opregion_asle_intr(dev);
2288 else
2289 DRM_ERROR("Unexpected DE Misc interrupt\n");
2290 }
2291 else
2292 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2293 }
2294
2295 if (master_ctl & GEN8_DE_PORT_IRQ) {
2296 iir = I915_READ(GEN8_DE_PORT_IIR);
2297 if (iir) {
2298 u32 tmp_mask;
2299 bool found = false;
2300
2301 I915_WRITE(GEN8_DE_PORT_IIR, iir);
2302 ret = IRQ_HANDLED;
2303
2304 tmp_mask = GEN8_AUX_CHANNEL_A;
2305 if (INTEL_INFO(dev_priv)->gen >= 9)
2306 tmp_mask |= GEN9_AUX_CHANNEL_B |
2307 GEN9_AUX_CHANNEL_C |
2308 GEN9_AUX_CHANNEL_D;
2309
2310 if (iir & tmp_mask) {
2311 dp_aux_irq_handler(dev);
2312 found = true;
2313 }
2314
2315 if (IS_BROXTON(dev_priv)) {
2316 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2317 if (tmp_mask) {
2318 bxt_hpd_irq_handler(dev, tmp_mask, hpd_bxt);
2319 found = true;
2320 }
2321 } else if (IS_BROADWELL(dev_priv)) {
2322 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2323 if (tmp_mask) {
2324 ilk_hpd_irq_handler(dev, tmp_mask, hpd_bdw);
2325 found = true;
2326 }
2327 }
2328
2329 if (IS_BROXTON(dev) && (iir & BXT_DE_PORT_GMBUS)) {
2330 gmbus_irq_handler(dev);
2331 found = true;
2332 }
2333
2334 if (!found)
2335 DRM_ERROR("Unexpected DE Port interrupt\n");
2336 }
2337 else
2338 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2339 }
2340
2341 for_each_pipe(dev_priv, pipe) {
2342 u32 flip_done, fault_errors;
2343
2344 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2345 continue;
2346
2347 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2348 if (!iir) {
2349 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2350 continue;
2351 }
2352
2353 ret = IRQ_HANDLED;
2354 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2355
2356 if (iir & GEN8_PIPE_VBLANK &&
2357 intel_pipe_handle_vblank(dev, pipe))
2358 intel_check_page_flip(dev, pipe);
2359
2360 flip_done = iir;
2361 if (INTEL_INFO(dev_priv)->gen >= 9)
2362 flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2363 else
2364 flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2365
2366 if (flip_done) {
2367 intel_prepare_page_flip(dev, pipe);
2368 intel_finish_page_flip_plane(dev, pipe);
2369 }
2370
2371 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2372 hsw_pipe_crc_irq_handler(dev, pipe);
2373
2374 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2375 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2376
2377 fault_errors = iir;
2378 if (INTEL_INFO(dev_priv)->gen >= 9)
2379 fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2380 else
2381 fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2382
2383 if (fault_errors)
2384 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2385 pipe_name(pipe),
2386 fault_errors);
2387 }
2388
2389 if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
2390 master_ctl & GEN8_DE_PCH_IRQ) {
2391 /*
2392 * FIXME(BDW): Assume for now that the new interrupt handling
2393 * scheme also closed the SDE interrupt handling race we've seen
2394 * on older pch-split platforms. But this needs testing.
2395 */
2396 iir = I915_READ(SDEIIR);
2397 if (iir) {
2398 I915_WRITE(SDEIIR, iir);
2399 ret = IRQ_HANDLED;
2400
2401 if (HAS_PCH_SPT(dev_priv))
2402 spt_irq_handler(dev, iir);
2403 else
2404 cpt_irq_handler(dev, iir);
2405 } else {
2406 /*
2407 * Like on previous PCH there seems to be something
2408 * fishy going on with forwarding PCH interrupts.
2409 */
2410 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2411 }
2412 }
2413
2414 return ret;
2415}
2416
2417static irqreturn_t gen8_irq_handler(int irq, void *arg)
2418{
2419 struct drm_device *dev = arg;
2420 struct drm_i915_private *dev_priv = dev->dev_private;
2421 u32 master_ctl;
2422 irqreturn_t ret;
2423
2424 if (!intel_irqs_enabled(dev_priv))
2425 return IRQ_NONE;
2426
2427 master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2428 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2429 if (!master_ctl)
2430 return IRQ_NONE;
2431
2432 I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2433
2434 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2435 disable_rpm_wakeref_asserts(dev_priv);
2436
2437 /* Find, clear, then process each source of interrupt */
2438 ret = gen8_gt_irq_handler(dev_priv, master_ctl);
2439 ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2440
2441 I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2442 POSTING_READ_FW(GEN8_MASTER_IRQ);
2443
2444 enable_rpm_wakeref_asserts(dev_priv);
2445
2446 return ret;
2447}
2448
2449static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2450 bool reset_completed)
2451{
2452 struct intel_engine_cs *ring;
2453 int i;
2454
2455 /*
2456 * Notify all waiters for GPU completion events that reset state has
2457 * been changed, and that they need to restart their wait after
2458 * checking for potential errors (and bail out to drop locks if there is
2459 * a gpu reset pending so that i915_error_work_func can acquire them).
2460 */
2461
2462 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2463 for_each_ring(ring, dev_priv, i)
2464 wake_up_all(&ring->irq_queue);
2465
2466 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2467 wake_up_all(&dev_priv->pending_flip_queue);
2468
2469 /*
2470 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2471 * reset state is cleared.
2472 */
2473 if (reset_completed)
2474 wake_up_all(&dev_priv->gpu_error.reset_queue);
2475}
2476
2477/**
2478 * i915_reset_and_wakeup - do process context error handling work
2479 * @dev: drm device
2480 *
2481 * Fire an error uevent so userspace can see that a hang or error
2482 * was detected.
2483 */
2484static void i915_reset_and_wakeup(struct drm_device *dev)
2485{
2486 struct drm_i915_private *dev_priv = to_i915(dev);
2487 struct i915_gpu_error *error = &dev_priv->gpu_error;
2488 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2489 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2490 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2491 int ret;
2492
2493 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2494
2495 /*
2496 * Note that there's only one work item which does gpu resets, so we
2497 * need not worry about concurrent gpu resets potentially incrementing
2498 * error->reset_counter twice. We only need to take care of another
2499 * racing irq/hangcheck declaring the gpu dead for a second time. A
2500 * quick check for that is good enough: schedule_work ensures the
2501 * correct ordering between hang detection and this work item, and since
2502 * the reset in-progress bit is only ever set by code outside of this
2503 * work we don't need to worry about any other races.
2504 */
2505 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2506 DRM_DEBUG_DRIVER("resetting chip\n");
2507 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2508 reset_event);
2509
2510 /*
2511 * In most cases it's guaranteed that we get here with an RPM
2512 * reference held, for example because there is a pending GPU
2513 * request that won't finish until the reset is done. This
2514 * isn't the case at least when we get here by doing a
2515 * simulated reset via debugs, so get an RPM reference.
2516 */
2517 intel_runtime_pm_get(dev_priv);
2518
2519 intel_prepare_reset(dev);
2520
2521 /*
2522 * All state reset _must_ be completed before we update the
2523 * reset counter, for otherwise waiters might miss the reset
2524 * pending state and not properly drop locks, resulting in
2525 * deadlocks with the reset work.
2526 */
2527 ret = i915_reset(dev);
2528
2529 intel_finish_reset(dev);
2530
2531 intel_runtime_pm_put(dev_priv);
2532
2533 if (ret == 0) {
2534 /*
2535 * After all the gem state is reset, increment the reset
2536 * counter and wake up everyone waiting for the reset to
2537 * complete.
2538 *
2539 * Since unlock operations are a one-sided barrier only,
2540 * we need to insert a barrier here to order any seqno
2541 * updates before
2542 * the counter increment.
2543 */
2544 smp_mb__before_atomic();
2545 atomic_inc(&dev_priv->gpu_error.reset_counter);
2546
2547 kobject_uevent_env(&dev->primary->kdev->kobj,
2548 KOBJ_CHANGE, reset_done_event);
2549 } else {
2550 atomic_or(I915_WEDGED, &error->reset_counter);
2551 }
2552
2553 /*
2554 * Note: The wake_up also serves as a memory barrier so that
2555 * waiters see the update value of the reset counter atomic_t.
2556 */
2557 i915_error_wake_up(dev_priv, true);
2558 }
2559}
2560
2561static void i915_report_and_clear_eir(struct drm_device *dev)
2562{
2563 struct drm_i915_private *dev_priv = dev->dev_private;
2564 uint32_t instdone[I915_NUM_INSTDONE_REG];
2565 u32 eir = I915_READ(EIR);
2566 int pipe, i;
2567
2568 if (!eir)
2569 return;
2570
2571 pr_err("render error detected, EIR: 0x%08x\n", eir);
2572
2573 i915_get_extra_instdone(dev, instdone);
2574
2575 if (IS_G4X(dev)) {
2576 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2577 u32 ipeir = I915_READ(IPEIR_I965);
2578
2579 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2580 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2581 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2582 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2583 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2584 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2585 I915_WRITE(IPEIR_I965, ipeir);
2586 POSTING_READ(IPEIR_I965);
2587 }
2588 if (eir & GM45_ERROR_PAGE_TABLE) {
2589 u32 pgtbl_err = I915_READ(PGTBL_ER);
2590 pr_err("page table error\n");
2591 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2592 I915_WRITE(PGTBL_ER, pgtbl_err);
2593 POSTING_READ(PGTBL_ER);
2594 }
2595 }
2596
2597 if (!IS_GEN2(dev)) {
2598 if (eir & I915_ERROR_PAGE_TABLE) {
2599 u32 pgtbl_err = I915_READ(PGTBL_ER);
2600 pr_err("page table error\n");
2601 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2602 I915_WRITE(PGTBL_ER, pgtbl_err);
2603 POSTING_READ(PGTBL_ER);
2604 }
2605 }
2606
2607 if (eir & I915_ERROR_MEMORY_REFRESH) {
2608 pr_err("memory refresh error:\n");
2609 for_each_pipe(dev_priv, pipe)
2610 pr_err("pipe %c stat: 0x%08x\n",
2611 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2612 /* pipestat has already been acked */
2613 }
2614 if (eir & I915_ERROR_INSTRUCTION) {
2615 pr_err("instruction error\n");
2616 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2617 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2618 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2619 if (INTEL_INFO(dev)->gen < 4) {
2620 u32 ipeir = I915_READ(IPEIR);
2621
2622 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2623 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2624 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2625 I915_WRITE(IPEIR, ipeir);
2626 POSTING_READ(IPEIR);
2627 } else {
2628 u32 ipeir = I915_READ(IPEIR_I965);
2629
2630 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2631 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2632 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2633 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2634 I915_WRITE(IPEIR_I965, ipeir);
2635 POSTING_READ(IPEIR_I965);
2636 }
2637 }
2638
2639 I915_WRITE(EIR, eir);
2640 POSTING_READ(EIR);
2641 eir = I915_READ(EIR);
2642 if (eir) {
2643 /*
2644 * some errors might have become stuck,
2645 * mask them.
2646 */
2647 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2648 I915_WRITE(EMR, I915_READ(EMR) | eir);
2649 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2650 }
2651}
2652
2653/**
2654 * i915_handle_error - handle a gpu error
2655 * @dev: drm device
2656 *
2657 * Do some basic checking of register state at error time and
2658 * dump it to the syslog. Also call i915_capture_error_state() to make
2659 * sure we get a record and make it available in debugfs. Fire a uevent
2660 * so userspace knows something bad happened (should trigger collection
2661 * of a ring dump etc.).
2662 */
2663void i915_handle_error(struct drm_device *dev, bool wedged,
2664 const char *fmt, ...)
2665{
2666 struct drm_i915_private *dev_priv = dev->dev_private;
2667 va_list args;
2668 char error_msg[80];
2669
2670 va_start(args, fmt);
2671 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2672 va_end(args);
2673
2674 i915_capture_error_state(dev, wedged, error_msg);
2675 i915_report_and_clear_eir(dev);
2676
2677 if (wedged) {
2678 atomic_or(I915_RESET_IN_PROGRESS_FLAG,
2679 &dev_priv->gpu_error.reset_counter);
2680
2681 /*
2682 * Wakeup waiting processes so that the reset function
2683 * i915_reset_and_wakeup doesn't deadlock trying to grab
2684 * various locks. By bumping the reset counter first, the woken
2685 * processes will see a reset in progress and back off,
2686 * releasing their locks and then wait for the reset completion.
2687 * We must do this for _all_ gpu waiters that might hold locks
2688 * that the reset work needs to acquire.
2689 *
2690 * Note: The wake_up serves as the required memory barrier to
2691 * ensure that the waiters see the updated value of the reset
2692 * counter atomic_t.
2693 */
2694 i915_error_wake_up(dev_priv, false);
2695 }
2696
2697 i915_reset_and_wakeup(dev);
2698}
2699
2700/* Called from drm generic code, passed 'crtc' which
2701 * we use as a pipe index
2702 */
2703static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2704{
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 unsigned long irqflags;
2707
2708 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2709 if (INTEL_INFO(dev)->gen >= 4)
2710 i915_enable_pipestat(dev_priv, pipe,
2711 PIPE_START_VBLANK_INTERRUPT_STATUS);
2712 else
2713 i915_enable_pipestat(dev_priv, pipe,
2714 PIPE_VBLANK_INTERRUPT_STATUS);
2715 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2716
2717 return 0;
2718}
2719
2720static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2721{
2722 struct drm_i915_private *dev_priv = dev->dev_private;
2723 unsigned long irqflags;
2724 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2725 DE_PIPE_VBLANK(pipe);
2726
2727 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2728 ilk_enable_display_irq(dev_priv, bit);
2729 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2730
2731 return 0;
2732}
2733
2734static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
2735{
2736 struct drm_i915_private *dev_priv = dev->dev_private;
2737 unsigned long irqflags;
2738
2739 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2740 i915_enable_pipestat(dev_priv, pipe,
2741 PIPE_START_VBLANK_INTERRUPT_STATUS);
2742 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2743
2744 return 0;
2745}
2746
2747static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2748{
2749 struct drm_i915_private *dev_priv = dev->dev_private;
2750 unsigned long irqflags;
2751
2752 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2753 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2754 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2755
2756 return 0;
2757}
2758
2759/* Called from drm generic code, passed 'crtc' which
2760 * we use as a pipe index
2761 */
2762static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2763{
2764 struct drm_i915_private *dev_priv = dev->dev_private;
2765 unsigned long irqflags;
2766
2767 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2768 i915_disable_pipestat(dev_priv, pipe,
2769 PIPE_VBLANK_INTERRUPT_STATUS |
2770 PIPE_START_VBLANK_INTERRUPT_STATUS);
2771 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2772}
2773
2774static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2775{
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 unsigned long irqflags;
2778 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2779 DE_PIPE_VBLANK(pipe);
2780
2781 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2782 ilk_disable_display_irq(dev_priv, bit);
2783 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2784}
2785
2786static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
2787{
2788 struct drm_i915_private *dev_priv = dev->dev_private;
2789 unsigned long irqflags;
2790
2791 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2792 i915_disable_pipestat(dev_priv, pipe,
2793 PIPE_START_VBLANK_INTERRUPT_STATUS);
2794 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2795}
2796
2797static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2798{
2799 struct drm_i915_private *dev_priv = dev->dev_private;
2800 unsigned long irqflags;
2801
2802 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2803 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2804 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2805}
2806
2807static bool
2808ring_idle(struct intel_engine_cs *ring, u32 seqno)
2809{
2810 return (list_empty(&ring->request_list) ||
2811 i915_seqno_passed(seqno, ring->last_submitted_seqno));
2812}
2813
2814static bool
2815ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2816{
2817 if (INTEL_INFO(dev)->gen >= 8) {
2818 return (ipehr >> 23) == 0x1c;
2819 } else {
2820 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2821 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2822 MI_SEMAPHORE_REGISTER);
2823 }
2824}
2825
2826static struct intel_engine_cs *
2827semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2828{
2829 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2830 struct intel_engine_cs *signaller;
2831 int i;
2832
2833 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2834 for_each_ring(signaller, dev_priv, i) {
2835 if (ring == signaller)
2836 continue;
2837
2838 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2839 return signaller;
2840 }
2841 } else {
2842 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2843
2844 for_each_ring(signaller, dev_priv, i) {
2845 if(ring == signaller)
2846 continue;
2847
2848 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2849 return signaller;
2850 }
2851 }
2852
2853 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2854 ring->id, ipehr, offset);
2855
2856 return NULL;
2857}
2858
2859static struct intel_engine_cs *
2860semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2861{
2862 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2863 u32 cmd, ipehr, head;
2864 u64 offset = 0;
2865 int i, backwards;
2866
2867 /*
2868 * This function does not support execlist mode - any attempt to
2869 * proceed further into this function will result in a kernel panic
2870 * when dereferencing ring->buffer, which is not set up in execlist
2871 * mode.
2872 *
2873 * The correct way of doing it would be to derive the currently
2874 * executing ring buffer from the current context, which is derived
2875 * from the currently running request. Unfortunately, to get the
2876 * current request we would have to grab the struct_mutex before doing
2877 * anything else, which would be ill-advised since some other thread
2878 * might have grabbed it already and managed to hang itself, causing
2879 * the hang checker to deadlock.
2880 *
2881 * Therefore, this function does not support execlist mode in its
2882 * current form. Just return NULL and move on.
2883 */
2884 if (ring->buffer == NULL)
2885 return NULL;
2886
2887 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2888 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2889 return NULL;
2890
2891 /*
2892 * HEAD is likely pointing to the dword after the actual command,
2893 * so scan backwards until we find the MBOX. But limit it to just 3
2894 * or 4 dwords depending on the semaphore wait command size.
2895 * Note that we don't care about ACTHD here since that might
2896 * point at at batch, and semaphores are always emitted into the
2897 * ringbuffer itself.
2898 */
2899 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2900 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2901
2902 for (i = backwards; i; --i) {
2903 /*
2904 * Be paranoid and presume the hw has gone off into the wild -
2905 * our ring is smaller than what the hardware (and hence
2906 * HEAD_ADDR) allows. Also handles wrap-around.
2907 */
2908 head &= ring->buffer->size - 1;
2909
2910 /* This here seems to blow up */
2911 cmd = ioread32(ring->buffer->virtual_start + head);
2912 if (cmd == ipehr)
2913 break;
2914
2915 head -= 4;
2916 }
2917
2918 if (!i)
2919 return NULL;
2920
2921 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2922 if (INTEL_INFO(ring->dev)->gen >= 8) {
2923 offset = ioread32(ring->buffer->virtual_start + head + 12);
2924 offset <<= 32;
2925 offset = ioread32(ring->buffer->virtual_start + head + 8);
2926 }
2927 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2928}
2929
2930static int semaphore_passed(struct intel_engine_cs *ring)
2931{
2932 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2933 struct intel_engine_cs *signaller;
2934 u32 seqno;
2935
2936 ring->hangcheck.deadlock++;
2937
2938 signaller = semaphore_waits_for(ring, &seqno);
2939 if (signaller == NULL)
2940 return -1;
2941
2942 /* Prevent pathological recursion due to driver bugs */
2943 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2944 return -1;
2945
2946 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2947 return 1;
2948
2949 /* cursory check for an unkickable deadlock */
2950 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2951 semaphore_passed(signaller) < 0)
2952 return -1;
2953
2954 return 0;
2955}
2956
2957static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2958{
2959 struct intel_engine_cs *ring;
2960 int i;
2961
2962 for_each_ring(ring, dev_priv, i)
2963 ring->hangcheck.deadlock = 0;
2964}
2965
2966static bool subunits_stuck(struct intel_engine_cs *ring)
2967{
2968 u32 instdone[I915_NUM_INSTDONE_REG];
2969 bool stuck;
2970 int i;
2971
2972 if (ring->id != RCS)
2973 return true;
2974
2975 i915_get_extra_instdone(ring->dev, instdone);
2976
2977 /* There might be unstable subunit states even when
2978 * actual head is not moving. Filter out the unstable ones by
2979 * accumulating the undone -> done transitions and only
2980 * consider those as progress.
2981 */
2982 stuck = true;
2983 for (i = 0; i < I915_NUM_INSTDONE_REG; i++) {
2984 const u32 tmp = instdone[i] | ring->hangcheck.instdone[i];
2985
2986 if (tmp != ring->hangcheck.instdone[i])
2987 stuck = false;
2988
2989 ring->hangcheck.instdone[i] |= tmp;
2990 }
2991
2992 return stuck;
2993}
2994
2995static enum intel_ring_hangcheck_action
2996head_stuck(struct intel_engine_cs *ring, u64 acthd)
2997{
2998 if (acthd != ring->hangcheck.acthd) {
2999
3000 /* Clear subunit states on head movement */
3001 memset(ring->hangcheck.instdone, 0,
3002 sizeof(ring->hangcheck.instdone));
3003
3004 if (acthd > ring->hangcheck.max_acthd) {
3005 ring->hangcheck.max_acthd = acthd;
3006 return HANGCHECK_ACTIVE;
3007 }
3008
3009 return HANGCHECK_ACTIVE_LOOP;
3010 }
3011
3012 if (!subunits_stuck(ring))
3013 return HANGCHECK_ACTIVE;
3014
3015 return HANGCHECK_HUNG;
3016}
3017
3018static enum intel_ring_hangcheck_action
3019ring_stuck(struct intel_engine_cs *ring, u64 acthd)
3020{
3021 struct drm_device *dev = ring->dev;
3022 struct drm_i915_private *dev_priv = dev->dev_private;
3023 enum intel_ring_hangcheck_action ha;
3024 u32 tmp;
3025
3026 ha = head_stuck(ring, acthd);
3027 if (ha != HANGCHECK_HUNG)
3028 return ha;
3029
3030 if (IS_GEN2(dev))
3031 return HANGCHECK_HUNG;
3032
3033 /* Is the chip hanging on a WAIT_FOR_EVENT?
3034 * If so we can simply poke the RB_WAIT bit
3035 * and break the hang. This should work on
3036 * all but the second generation chipsets.
3037 */
3038 tmp = I915_READ_CTL(ring);
3039 if (tmp & RING_WAIT) {
3040 i915_handle_error(dev, false,
3041 "Kicking stuck wait on %s",
3042 ring->name);
3043 I915_WRITE_CTL(ring, tmp);
3044 return HANGCHECK_KICK;
3045 }
3046
3047 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3048 switch (semaphore_passed(ring)) {
3049 default:
3050 return HANGCHECK_HUNG;
3051 case 1:
3052 i915_handle_error(dev, false,
3053 "Kicking stuck semaphore on %s",
3054 ring->name);
3055 I915_WRITE_CTL(ring, tmp);
3056 return HANGCHECK_KICK;
3057 case 0:
3058 return HANGCHECK_WAIT;
3059 }
3060 }
3061
3062 return HANGCHECK_HUNG;
3063}
3064
3065/*
3066 * This is called when the chip hasn't reported back with completed
3067 * batchbuffers in a long time. We keep track per ring seqno progress and
3068 * if there are no progress, hangcheck score for that ring is increased.
3069 * Further, acthd is inspected to see if the ring is stuck. On stuck case
3070 * we kick the ring. If we see no progress on three subsequent calls
3071 * we assume chip is wedged and try to fix it by resetting the chip.
3072 */
3073static void i915_hangcheck_elapsed(struct work_struct *work)
3074{
3075 struct drm_i915_private *dev_priv =
3076 container_of(work, typeof(*dev_priv),
3077 gpu_error.hangcheck_work.work);
3078 struct drm_device *dev = dev_priv->dev;
3079 struct intel_engine_cs *ring;
3080 int i;
3081 int busy_count = 0, rings_hung = 0;
3082 bool stuck[I915_NUM_RINGS] = { 0 };
3083#define BUSY 1
3084#define KICK 5
3085#define HUNG 20
3086
3087 if (!i915.enable_hangcheck)
3088 return;
3089
3090 /*
3091 * The hangcheck work is synced during runtime suspend, we don't
3092 * require a wakeref. TODO: instead of disabling the asserts make
3093 * sure that we hold a reference when this work is running.
3094 */
3095 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3096
3097 /* As enabling the GPU requires fairly extensive mmio access,
3098 * periodically arm the mmio checker to see if we are triggering
3099 * any invalid access.
3100 */
3101 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
3102
3103 for_each_ring(ring, dev_priv, i) {
3104 u64 acthd;
3105 u32 seqno;
3106 bool busy = true;
3107
3108 semaphore_clear_deadlocks(dev_priv);
3109
3110 seqno = ring->get_seqno(ring, false);
3111 acthd = intel_ring_get_active_head(ring);
3112
3113 if (ring->hangcheck.seqno == seqno) {
3114 if (ring_idle(ring, seqno)) {
3115 ring->hangcheck.action = HANGCHECK_IDLE;
3116
3117 if (waitqueue_active(&ring->irq_queue)) {
3118 /* Issue a wake-up to catch stuck h/w. */
3119 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
3120 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
3121 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3122 ring->name);
3123 else
3124 DRM_INFO("Fake missed irq on %s\n",
3125 ring->name);
3126 wake_up_all(&ring->irq_queue);
3127 }
3128 /* Safeguard against driver failure */
3129 ring->hangcheck.score += BUSY;
3130 } else
3131 busy = false;
3132 } else {
3133 /* We always increment the hangcheck score
3134 * if the ring is busy and still processing
3135 * the same request, so that no single request
3136 * can run indefinitely (such as a chain of
3137 * batches). The only time we do not increment
3138 * the hangcheck score on this ring, if this
3139 * ring is in a legitimate wait for another
3140 * ring. In that case the waiting ring is a
3141 * victim and we want to be sure we catch the
3142 * right culprit. Then every time we do kick
3143 * the ring, add a small increment to the
3144 * score so that we can catch a batch that is
3145 * being repeatedly kicked and so responsible
3146 * for stalling the machine.
3147 */
3148 ring->hangcheck.action = ring_stuck(ring,
3149 acthd);
3150
3151 switch (ring->hangcheck.action) {
3152 case HANGCHECK_IDLE:
3153 case HANGCHECK_WAIT:
3154 case HANGCHECK_ACTIVE:
3155 break;
3156 case HANGCHECK_ACTIVE_LOOP:
3157 ring->hangcheck.score += BUSY;
3158 break;
3159 case HANGCHECK_KICK:
3160 ring->hangcheck.score += KICK;
3161 break;
3162 case HANGCHECK_HUNG:
3163 ring->hangcheck.score += HUNG;
3164 stuck[i] = true;
3165 break;
3166 }
3167 }
3168 } else {
3169 ring->hangcheck.action = HANGCHECK_ACTIVE;
3170
3171 /* Gradually reduce the count so that we catch DoS
3172 * attempts across multiple batches.
3173 */
3174 if (ring->hangcheck.score > 0)
3175 ring->hangcheck.score--;
3176
3177 /* Clear head and subunit states on seqno movement */
3178 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3179
3180 memset(ring->hangcheck.instdone, 0,
3181 sizeof(ring->hangcheck.instdone));
3182 }
3183
3184 ring->hangcheck.seqno = seqno;
3185 ring->hangcheck.acthd = acthd;
3186 busy_count += busy;
3187 }
3188
3189 for_each_ring(ring, dev_priv, i) {
3190 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3191 DRM_INFO("%s on %s\n",
3192 stuck[i] ? "stuck" : "no progress",
3193 ring->name);
3194 rings_hung++;
3195 }
3196 }
3197
3198 if (rings_hung) {
3199 i915_handle_error(dev, true, "Ring hung");
3200 goto out;
3201 }
3202
3203 if (busy_count)
3204 /* Reset timer case chip hangs without another request
3205 * being added */
3206 i915_queue_hangcheck(dev);
3207
3208out:
3209 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3210}
3211
3212void i915_queue_hangcheck(struct drm_device *dev)
3213{
3214 struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
3215
3216 if (!i915.enable_hangcheck)
3217 return;
3218
3219 /* Don't continually defer the hangcheck so that it is always run at
3220 * least once after work has been scheduled on any ring. Otherwise,
3221 * we will ignore a hung ring if a second ring is kept busy.
3222 */
3223
3224 queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
3225 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
3226}
3227
3228static void ibx_irq_reset(struct drm_device *dev)
3229{
3230 struct drm_i915_private *dev_priv = dev->dev_private;
3231
3232 if (HAS_PCH_NOP(dev))
3233 return;
3234
3235 GEN5_IRQ_RESET(SDE);
3236
3237 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3238 I915_WRITE(SERR_INT, 0xffffffff);
3239}
3240
3241/*
3242 * SDEIER is also touched by the interrupt handler to work around missed PCH
3243 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3244 * instead we unconditionally enable all PCH interrupt sources here, but then
3245 * only unmask them as needed with SDEIMR.
3246 *
3247 * This function needs to be called before interrupts are enabled.
3248 */
3249static void ibx_irq_pre_postinstall(struct drm_device *dev)
3250{
3251 struct drm_i915_private *dev_priv = dev->dev_private;
3252
3253 if (HAS_PCH_NOP(dev))
3254 return;
3255
3256 WARN_ON(I915_READ(SDEIER) != 0);
3257 I915_WRITE(SDEIER, 0xffffffff);
3258 POSTING_READ(SDEIER);
3259}
3260
3261static void gen5_gt_irq_reset(struct drm_device *dev)
3262{
3263 struct drm_i915_private *dev_priv = dev->dev_private;
3264
3265 GEN5_IRQ_RESET(GT);
3266 if (INTEL_INFO(dev)->gen >= 6)
3267 GEN5_IRQ_RESET(GEN6_PM);
3268}
3269
3270/* drm_dma.h hooks
3271*/
3272static void ironlake_irq_reset(struct drm_device *dev)
3273{
3274 struct drm_i915_private *dev_priv = dev->dev_private;
3275
3276 I915_WRITE(HWSTAM, 0xffffffff);
3277
3278 GEN5_IRQ_RESET(DE);
3279 if (IS_GEN7(dev))
3280 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3281
3282 gen5_gt_irq_reset(dev);
3283
3284 ibx_irq_reset(dev);
3285}
3286
3287static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3288{
3289 enum pipe pipe;
3290
3291 i915_hotplug_interrupt_update(dev_priv, 0xFFFFFFFF, 0);
3292 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3293
3294 for_each_pipe(dev_priv, pipe)
3295 I915_WRITE(PIPESTAT(pipe), 0xffff);
3296
3297 GEN5_IRQ_RESET(VLV_);
3298}
3299
3300static void valleyview_irq_preinstall(struct drm_device *dev)
3301{
3302 struct drm_i915_private *dev_priv = dev->dev_private;
3303
3304 /* VLV magic */
3305 I915_WRITE(VLV_IMR, 0);
3306 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3307 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3308 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3309
3310 gen5_gt_irq_reset(dev);
3311
3312 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3313
3314 vlv_display_irq_reset(dev_priv);
3315}
3316
3317static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3318{
3319 GEN8_IRQ_RESET_NDX(GT, 0);
3320 GEN8_IRQ_RESET_NDX(GT, 1);
3321 GEN8_IRQ_RESET_NDX(GT, 2);
3322 GEN8_IRQ_RESET_NDX(GT, 3);
3323}
3324
3325static void gen8_irq_reset(struct drm_device *dev)
3326{
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 int pipe;
3329
3330 I915_WRITE(GEN8_MASTER_IRQ, 0);
3331 POSTING_READ(GEN8_MASTER_IRQ);
3332
3333 gen8_gt_irq_reset(dev_priv);
3334
3335 for_each_pipe(dev_priv, pipe)
3336 if (intel_display_power_is_enabled(dev_priv,
3337 POWER_DOMAIN_PIPE(pipe)))
3338 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3339
3340 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3341 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3342 GEN5_IRQ_RESET(GEN8_PCU_);
3343
3344 if (HAS_PCH_SPLIT(dev))
3345 ibx_irq_reset(dev);
3346}
3347
3348void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3349 unsigned int pipe_mask)
3350{
3351 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3352 enum pipe pipe;
3353
3354 spin_lock_irq(&dev_priv->irq_lock);
3355 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3356 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3357 dev_priv->de_irq_mask[pipe],
3358 ~dev_priv->de_irq_mask[pipe] | extra_ier);
3359 spin_unlock_irq(&dev_priv->irq_lock);
3360}
3361
3362void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3363 unsigned int pipe_mask)
3364{
3365 enum pipe pipe;
3366
3367 spin_lock_irq(&dev_priv->irq_lock);
3368 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3369 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3370 spin_unlock_irq(&dev_priv->irq_lock);
3371
3372 /* make sure we're done processing display irqs */
3373 synchronize_irq(dev_priv->dev->irq);
3374}
3375
3376static void cherryview_irq_preinstall(struct drm_device *dev)
3377{
3378 struct drm_i915_private *dev_priv = dev->dev_private;
3379
3380 I915_WRITE(GEN8_MASTER_IRQ, 0);
3381 POSTING_READ(GEN8_MASTER_IRQ);
3382
3383 gen8_gt_irq_reset(dev_priv);
3384
3385 GEN5_IRQ_RESET(GEN8_PCU_);
3386
3387 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3388
3389 vlv_display_irq_reset(dev_priv);
3390}
3391
3392static u32 intel_hpd_enabled_irqs(struct drm_device *dev,
3393 const u32 hpd[HPD_NUM_PINS])
3394{
3395 struct drm_i915_private *dev_priv = to_i915(dev);
3396 struct intel_encoder *encoder;
3397 u32 enabled_irqs = 0;
3398
3399 for_each_intel_encoder(dev, encoder)
3400 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3401 enabled_irqs |= hpd[encoder->hpd_pin];
3402
3403 return enabled_irqs;
3404}
3405
3406static void ibx_hpd_irq_setup(struct drm_device *dev)
3407{
3408 struct drm_i915_private *dev_priv = dev->dev_private;
3409 u32 hotplug_irqs, hotplug, enabled_irqs;
3410
3411 if (HAS_PCH_IBX(dev)) {
3412 hotplug_irqs = SDE_HOTPLUG_MASK;
3413 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ibx);
3414 } else {
3415 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3416 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_cpt);
3417 }
3418
3419 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3420
3421 /*
3422 * Enable digital hotplug on the PCH, and configure the DP short pulse
3423 * duration to 2ms (which is the minimum in the Display Port spec).
3424 * The pulse duration bits are reserved on LPT+.
3425 */
3426 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3427 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3428 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3429 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3430 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3431 /*
3432 * When CPU and PCH are on the same package, port A
3433 * HPD must be enabled in both north and south.
3434 */
3435 if (HAS_PCH_LPT_LP(dev))
3436 hotplug |= PORTA_HOTPLUG_ENABLE;
3437 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3438}
3439
3440static void spt_hpd_irq_setup(struct drm_device *dev)
3441{
3442 struct drm_i915_private *dev_priv = dev->dev_private;
3443 u32 hotplug_irqs, hotplug, enabled_irqs;
3444
3445 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3446 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_spt);
3447
3448 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3449
3450 /* Enable digital hotplug on the PCH */
3451 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3452 hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3453 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3454 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3455
3456 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3457 hotplug |= PORTE_HOTPLUG_ENABLE;
3458 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3459}
3460
3461static void ilk_hpd_irq_setup(struct drm_device *dev)
3462{
3463 struct drm_i915_private *dev_priv = dev->dev_private;
3464 u32 hotplug_irqs, hotplug, enabled_irqs;
3465
3466 if (INTEL_INFO(dev)->gen >= 8) {
3467 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3468 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bdw);
3469
3470 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3471 } else if (INTEL_INFO(dev)->gen >= 7) {
3472 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3473 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ivb);
3474
3475 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3476 } else {
3477 hotplug_irqs = DE_DP_A_HOTPLUG;
3478 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ilk);
3479
3480 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3481 }
3482
3483 /*
3484 * Enable digital hotplug on the CPU, and configure the DP short pulse
3485 * duration to 2ms (which is the minimum in the Display Port spec)
3486 * The pulse duration bits are reserved on HSW+.
3487 */
3488 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3489 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3490 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3491 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3492
3493 ibx_hpd_irq_setup(dev);
3494}
3495
3496static void bxt_hpd_irq_setup(struct drm_device *dev)
3497{
3498 struct drm_i915_private *dev_priv = dev->dev_private;
3499 u32 hotplug_irqs, hotplug, enabled_irqs;
3500
3501 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bxt);
3502 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3503
3504 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3505
3506 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3507 hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3508 PORTA_HOTPLUG_ENABLE;
3509 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3510}
3511
3512static void ibx_irq_postinstall(struct drm_device *dev)
3513{
3514 struct drm_i915_private *dev_priv = dev->dev_private;
3515 u32 mask;
3516
3517 if (HAS_PCH_NOP(dev))
3518 return;
3519
3520 if (HAS_PCH_IBX(dev))
3521 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3522 else
3523 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3524
3525 gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3526 I915_WRITE(SDEIMR, ~mask);
3527}
3528
3529static void gen5_gt_irq_postinstall(struct drm_device *dev)
3530{
3531 struct drm_i915_private *dev_priv = dev->dev_private;
3532 u32 pm_irqs, gt_irqs;
3533
3534 pm_irqs = gt_irqs = 0;
3535
3536 dev_priv->gt_irq_mask = ~0;
3537 if (HAS_L3_DPF(dev)) {
3538 /* L3 parity interrupt is always unmasked. */
3539 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3540 gt_irqs |= GT_PARITY_ERROR(dev);
3541 }
3542
3543 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3544 if (IS_GEN5(dev)) {
3545 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3546 ILK_BSD_USER_INTERRUPT;
3547 } else {
3548 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3549 }
3550
3551 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3552
3553 if (INTEL_INFO(dev)->gen >= 6) {
3554 /*
3555 * RPS interrupts will get enabled/disabled on demand when RPS
3556 * itself is enabled/disabled.
3557 */
3558 if (HAS_VEBOX(dev))
3559 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3560
3561 dev_priv->pm_irq_mask = 0xffffffff;
3562 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3563 }
3564}
3565
3566static int ironlake_irq_postinstall(struct drm_device *dev)
3567{
3568 struct drm_i915_private *dev_priv = dev->dev_private;
3569 u32 display_mask, extra_mask;
3570
3571 if (INTEL_INFO(dev)->gen >= 7) {
3572 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3573 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3574 DE_PLANEB_FLIP_DONE_IVB |
3575 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3576 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3577 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3578 DE_DP_A_HOTPLUG_IVB);
3579 } else {
3580 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3581 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3582 DE_AUX_CHANNEL_A |
3583 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3584 DE_POISON);
3585 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3586 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3587 DE_DP_A_HOTPLUG);
3588 }
3589
3590 dev_priv->irq_mask = ~display_mask;
3591
3592 I915_WRITE(HWSTAM, 0xeffe);
3593
3594 ibx_irq_pre_postinstall(dev);
3595
3596 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3597
3598 gen5_gt_irq_postinstall(dev);
3599
3600 ibx_irq_postinstall(dev);
3601
3602 if (IS_IRONLAKE_M(dev)) {
3603 /* Enable PCU event interrupts
3604 *
3605 * spinlocking not required here for correctness since interrupt
3606 * setup is guaranteed to run in single-threaded context. But we
3607 * need it to make the assert_spin_locked happy. */
3608 spin_lock_irq(&dev_priv->irq_lock);
3609 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3610 spin_unlock_irq(&dev_priv->irq_lock);
3611 }
3612
3613 return 0;
3614}
3615
3616static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3617{
3618 u32 pipestat_mask;
3619 u32 iir_mask;
3620 enum pipe pipe;
3621
3622 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3623 PIPE_FIFO_UNDERRUN_STATUS;
3624
3625 for_each_pipe(dev_priv, pipe)
3626 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3627 POSTING_READ(PIPESTAT(PIPE_A));
3628
3629 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3630 PIPE_CRC_DONE_INTERRUPT_STATUS;
3631
3632 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3633 for_each_pipe(dev_priv, pipe)
3634 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3635
3636 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3637 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3638 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3639 if (IS_CHERRYVIEW(dev_priv))
3640 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3641 dev_priv->irq_mask &= ~iir_mask;
3642
3643 I915_WRITE(VLV_IIR, iir_mask);
3644 I915_WRITE(VLV_IIR, iir_mask);
3645 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3646 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3647 POSTING_READ(VLV_IMR);
3648}
3649
3650static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3651{
3652 u32 pipestat_mask;
3653 u32 iir_mask;
3654 enum pipe pipe;
3655
3656 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3657 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3658 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3659 if (IS_CHERRYVIEW(dev_priv))
3660 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3661
3662 dev_priv->irq_mask |= iir_mask;
3663 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3664 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3665 I915_WRITE(VLV_IIR, iir_mask);
3666 I915_WRITE(VLV_IIR, iir_mask);
3667 POSTING_READ(VLV_IIR);
3668
3669 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3670 PIPE_CRC_DONE_INTERRUPT_STATUS;
3671
3672 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3673 for_each_pipe(dev_priv, pipe)
3674 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3675
3676 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3677 PIPE_FIFO_UNDERRUN_STATUS;
3678
3679 for_each_pipe(dev_priv, pipe)
3680 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3681 POSTING_READ(PIPESTAT(PIPE_A));
3682}
3683
3684void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3685{
3686 assert_spin_locked(&dev_priv->irq_lock);
3687
3688 if (dev_priv->display_irqs_enabled)
3689 return;
3690
3691 dev_priv->display_irqs_enabled = true;
3692
3693 if (intel_irqs_enabled(dev_priv))
3694 valleyview_display_irqs_install(dev_priv);
3695}
3696
3697void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3698{
3699 assert_spin_locked(&dev_priv->irq_lock);
3700
3701 if (!dev_priv->display_irqs_enabled)
3702 return;
3703
3704 dev_priv->display_irqs_enabled = false;
3705
3706 if (intel_irqs_enabled(dev_priv))
3707 valleyview_display_irqs_uninstall(dev_priv);
3708}
3709
3710static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3711{
3712 dev_priv->irq_mask = ~0;
3713
3714 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3715 POSTING_READ(PORT_HOTPLUG_EN);
3716
3717 I915_WRITE(VLV_IIR, 0xffffffff);
3718 I915_WRITE(VLV_IIR, 0xffffffff);
3719 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3720 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3721 POSTING_READ(VLV_IMR);
3722
3723 /* Interrupt setup is already guaranteed to be single-threaded, this is
3724 * just to make the assert_spin_locked check happy. */
3725 spin_lock_irq(&dev_priv->irq_lock);
3726 if (dev_priv->display_irqs_enabled)
3727 valleyview_display_irqs_install(dev_priv);
3728 spin_unlock_irq(&dev_priv->irq_lock);
3729}
3730
3731static int valleyview_irq_postinstall(struct drm_device *dev)
3732{
3733 struct drm_i915_private *dev_priv = dev->dev_private;
3734
3735 vlv_display_irq_postinstall(dev_priv);
3736
3737 gen5_gt_irq_postinstall(dev);
3738
3739 /* ack & enable invalid PTE error interrupts */
3740#if 0 /* FIXME: add support to irq handler for checking these bits */
3741 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3742 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3743#endif
3744
3745 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3746
3747 return 0;
3748}
3749
3750static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3751{
3752 /* These are interrupts we'll toggle with the ring mask register */
3753 uint32_t gt_interrupts[] = {
3754 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3755 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3756 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3757 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3758 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3759 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3760 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3761 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3762 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3763 0,
3764 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3765 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3766 };
3767
3768 dev_priv->pm_irq_mask = 0xffffffff;
3769 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3770 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3771 /*
3772 * RPS interrupts will get enabled/disabled on demand when RPS itself
3773 * is enabled/disabled.
3774 */
3775 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3776 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3777}
3778
3779static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3780{
3781 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3782 uint32_t de_pipe_enables;
3783 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3784 u32 de_port_enables;
3785 enum pipe pipe;
3786
3787 if (INTEL_INFO(dev_priv)->gen >= 9) {
3788 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3789 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3790 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3791 GEN9_AUX_CHANNEL_D;
3792 if (IS_BROXTON(dev_priv))
3793 de_port_masked |= BXT_DE_PORT_GMBUS;
3794 } else {
3795 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3796 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3797 }
3798
3799 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3800 GEN8_PIPE_FIFO_UNDERRUN;
3801
3802 de_port_enables = de_port_masked;
3803 if (IS_BROXTON(dev_priv))
3804 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3805 else if (IS_BROADWELL(dev_priv))
3806 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3807
3808 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3809 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3810 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3811
3812 for_each_pipe(dev_priv, pipe)
3813 if (intel_display_power_is_enabled(dev_priv,
3814 POWER_DOMAIN_PIPE(pipe)))
3815 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3816 dev_priv->de_irq_mask[pipe],
3817 de_pipe_enables);
3818
3819 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3820}
3821
3822static int gen8_irq_postinstall(struct drm_device *dev)
3823{
3824 struct drm_i915_private *dev_priv = dev->dev_private;
3825
3826 if (HAS_PCH_SPLIT(dev))
3827 ibx_irq_pre_postinstall(dev);
3828
3829 gen8_gt_irq_postinstall(dev_priv);
3830 gen8_de_irq_postinstall(dev_priv);
3831
3832 if (HAS_PCH_SPLIT(dev))
3833 ibx_irq_postinstall(dev);
3834
3835 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3836 POSTING_READ(GEN8_MASTER_IRQ);
3837
3838 return 0;
3839}
3840
3841static int cherryview_irq_postinstall(struct drm_device *dev)
3842{
3843 struct drm_i915_private *dev_priv = dev->dev_private;
3844
3845 vlv_display_irq_postinstall(dev_priv);
3846
3847 gen8_gt_irq_postinstall(dev_priv);
3848
3849 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3850 POSTING_READ(GEN8_MASTER_IRQ);
3851
3852 return 0;
3853}
3854
3855static void gen8_irq_uninstall(struct drm_device *dev)
3856{
3857 struct drm_i915_private *dev_priv = dev->dev_private;
3858
3859 if (!dev_priv)
3860 return;
3861
3862 gen8_irq_reset(dev);
3863}
3864
3865static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3866{
3867 /* Interrupt setup is already guaranteed to be single-threaded, this is
3868 * just to make the assert_spin_locked check happy. */
3869 spin_lock_irq(&dev_priv->irq_lock);
3870 if (dev_priv->display_irqs_enabled)
3871 valleyview_display_irqs_uninstall(dev_priv);
3872 spin_unlock_irq(&dev_priv->irq_lock);
3873
3874 vlv_display_irq_reset(dev_priv);
3875
3876 dev_priv->irq_mask = ~0;
3877}
3878
3879static void valleyview_irq_uninstall(struct drm_device *dev)
3880{
3881 struct drm_i915_private *dev_priv = dev->dev_private;
3882
3883 if (!dev_priv)
3884 return;
3885
3886 I915_WRITE(VLV_MASTER_IER, 0);
3887
3888 gen5_gt_irq_reset(dev);
3889
3890 I915_WRITE(HWSTAM, 0xffffffff);
3891
3892 vlv_display_irq_uninstall(dev_priv);
3893}
3894
3895static void cherryview_irq_uninstall(struct drm_device *dev)
3896{
3897 struct drm_i915_private *dev_priv = dev->dev_private;
3898
3899 if (!dev_priv)
3900 return;
3901
3902 I915_WRITE(GEN8_MASTER_IRQ, 0);
3903 POSTING_READ(GEN8_MASTER_IRQ);
3904
3905 gen8_gt_irq_reset(dev_priv);
3906
3907 GEN5_IRQ_RESET(GEN8_PCU_);
3908
3909 vlv_display_irq_uninstall(dev_priv);
3910}
3911
3912static void ironlake_irq_uninstall(struct drm_device *dev)
3913{
3914 struct drm_i915_private *dev_priv = dev->dev_private;
3915
3916 if (!dev_priv)
3917 return;
3918
3919 ironlake_irq_reset(dev);
3920}
3921
3922static void i8xx_irq_preinstall(struct drm_device * dev)
3923{
3924 struct drm_i915_private *dev_priv = dev->dev_private;
3925 int pipe;
3926
3927 for_each_pipe(dev_priv, pipe)
3928 I915_WRITE(PIPESTAT(pipe), 0);
3929 I915_WRITE16(IMR, 0xffff);
3930 I915_WRITE16(IER, 0x0);
3931 POSTING_READ16(IER);
3932}
3933
3934static int i8xx_irq_postinstall(struct drm_device *dev)
3935{
3936 struct drm_i915_private *dev_priv = dev->dev_private;
3937
3938 I915_WRITE16(EMR,
3939 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3940
3941 /* Unmask the interrupts that we always want on. */
3942 dev_priv->irq_mask =
3943 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3944 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3945 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3946 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3947 I915_WRITE16(IMR, dev_priv->irq_mask);
3948
3949 I915_WRITE16(IER,
3950 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3951 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3952 I915_USER_INTERRUPT);
3953 POSTING_READ16(IER);
3954
3955 /* Interrupt setup is already guaranteed to be single-threaded, this is
3956 * just to make the assert_spin_locked check happy. */
3957 spin_lock_irq(&dev_priv->irq_lock);
3958 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3959 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3960 spin_unlock_irq(&dev_priv->irq_lock);
3961
3962 return 0;
3963}
3964
3965/*
3966 * Returns true when a page flip has completed.
3967 */
3968static bool i8xx_handle_vblank(struct drm_device *dev,
3969 int plane, int pipe, u32 iir)
3970{
3971 struct drm_i915_private *dev_priv = dev->dev_private;
3972 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3973
3974 if (!intel_pipe_handle_vblank(dev, pipe))
3975 return false;
3976
3977 if ((iir & flip_pending) == 0)
3978 goto check_page_flip;
3979
3980 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3981 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3982 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3983 * the flip is completed (no longer pending). Since this doesn't raise
3984 * an interrupt per se, we watch for the change at vblank.
3985 */
3986 if (I915_READ16(ISR) & flip_pending)
3987 goto check_page_flip;
3988
3989 intel_prepare_page_flip(dev, plane);
3990 intel_finish_page_flip(dev, pipe);
3991 return true;
3992
3993check_page_flip:
3994 intel_check_page_flip(dev, pipe);
3995 return false;
3996}
3997
3998static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3999{
4000 struct drm_device *dev = arg;
4001 struct drm_i915_private *dev_priv = dev->dev_private;
4002 u16 iir, new_iir;
4003 u32 pipe_stats[2];
4004 int pipe;
4005 u16 flip_mask =
4006 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4007 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4008 irqreturn_t ret;
4009
4010 if (!intel_irqs_enabled(dev_priv))
4011 return IRQ_NONE;
4012
4013 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4014 disable_rpm_wakeref_asserts(dev_priv);
4015
4016 ret = IRQ_NONE;
4017 iir = I915_READ16(IIR);
4018 if (iir == 0)
4019 goto out;
4020
4021 while (iir & ~flip_mask) {
4022 /* Can't rely on pipestat interrupt bit in iir as it might
4023 * have been cleared after the pipestat interrupt was received.
4024 * It doesn't set the bit in iir again, but it still produces
4025 * interrupts (for non-MSI).
4026 */
4027 spin_lock(&dev_priv->irq_lock);
4028 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4029 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4030
4031 for_each_pipe(dev_priv, pipe) {
4032 i915_reg_t reg = PIPESTAT(pipe);
4033 pipe_stats[pipe] = I915_READ(reg);
4034
4035 /*
4036 * Clear the PIPE*STAT regs before the IIR
4037 */
4038 if (pipe_stats[pipe] & 0x8000ffff)
4039 I915_WRITE(reg, pipe_stats[pipe]);
4040 }
4041 spin_unlock(&dev_priv->irq_lock);
4042
4043 I915_WRITE16(IIR, iir & ~flip_mask);
4044 new_iir = I915_READ16(IIR); /* Flush posted writes */
4045
4046 if (iir & I915_USER_INTERRUPT)
4047 notify_ring(&dev_priv->ring[RCS]);
4048
4049 for_each_pipe(dev_priv, pipe) {
4050 int plane = pipe;
4051 if (HAS_FBC(dev))
4052 plane = !plane;
4053
4054 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4055 i8xx_handle_vblank(dev, plane, pipe, iir))
4056 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4057
4058 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4059 i9xx_pipe_crc_irq_handler(dev, pipe);
4060
4061 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4062 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4063 pipe);
4064 }
4065
4066 iir = new_iir;
4067 }
4068 ret = IRQ_HANDLED;
4069
4070out:
4071 enable_rpm_wakeref_asserts(dev_priv);
4072
4073 return ret;
4074}
4075
4076static void i8xx_irq_uninstall(struct drm_device * dev)
4077{
4078 struct drm_i915_private *dev_priv = dev->dev_private;
4079 int pipe;
4080
4081 for_each_pipe(dev_priv, pipe) {
4082 /* Clear enable bits; then clear status bits */
4083 I915_WRITE(PIPESTAT(pipe), 0);
4084 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4085 }
4086 I915_WRITE16(IMR, 0xffff);
4087 I915_WRITE16(IER, 0x0);
4088 I915_WRITE16(IIR, I915_READ16(IIR));
4089}
4090
4091static void i915_irq_preinstall(struct drm_device * dev)
4092{
4093 struct drm_i915_private *dev_priv = dev->dev_private;
4094 int pipe;
4095
4096 if (I915_HAS_HOTPLUG(dev)) {
4097 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4098 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4099 }
4100
4101 I915_WRITE16(HWSTAM, 0xeffe);
4102 for_each_pipe(dev_priv, pipe)
4103 I915_WRITE(PIPESTAT(pipe), 0);
4104 I915_WRITE(IMR, 0xffffffff);
4105 I915_WRITE(IER, 0x0);
4106 POSTING_READ(IER);
4107}
4108
4109static int i915_irq_postinstall(struct drm_device *dev)
4110{
4111 struct drm_i915_private *dev_priv = dev->dev_private;
4112 u32 enable_mask;
4113
4114 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4115
4116 /* Unmask the interrupts that we always want on. */
4117 dev_priv->irq_mask =
4118 ~(I915_ASLE_INTERRUPT |
4119 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4120 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4121 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4122 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4123
4124 enable_mask =
4125 I915_ASLE_INTERRUPT |
4126 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4127 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4128 I915_USER_INTERRUPT;
4129
4130 if (I915_HAS_HOTPLUG(dev)) {
4131 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4132 POSTING_READ(PORT_HOTPLUG_EN);
4133
4134 /* Enable in IER... */
4135 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4136 /* and unmask in IMR */
4137 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4138 }
4139
4140 I915_WRITE(IMR, dev_priv->irq_mask);
4141 I915_WRITE(IER, enable_mask);
4142 POSTING_READ(IER);
4143
4144 i915_enable_asle_pipestat(dev);
4145
4146 /* Interrupt setup is already guaranteed to be single-threaded, this is
4147 * just to make the assert_spin_locked check happy. */
4148 spin_lock_irq(&dev_priv->irq_lock);
4149 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4150 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4151 spin_unlock_irq(&dev_priv->irq_lock);
4152
4153 return 0;
4154}
4155
4156/*
4157 * Returns true when a page flip has completed.
4158 */
4159static bool i915_handle_vblank(struct drm_device *dev,
4160 int plane, int pipe, u32 iir)
4161{
4162 struct drm_i915_private *dev_priv = dev->dev_private;
4163 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4164
4165 if (!intel_pipe_handle_vblank(dev, pipe))
4166 return false;
4167
4168 if ((iir & flip_pending) == 0)
4169 goto check_page_flip;
4170
4171 /* We detect FlipDone by looking for the change in PendingFlip from '1'
4172 * to '0' on the following vblank, i.e. IIR has the Pendingflip
4173 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4174 * the flip is completed (no longer pending). Since this doesn't raise
4175 * an interrupt per se, we watch for the change at vblank.
4176 */
4177 if (I915_READ(ISR) & flip_pending)
4178 goto check_page_flip;
4179
4180 intel_prepare_page_flip(dev, plane);
4181 intel_finish_page_flip(dev, pipe);
4182 return true;
4183
4184check_page_flip:
4185 intel_check_page_flip(dev, pipe);
4186 return false;
4187}
4188
4189static irqreturn_t i915_irq_handler(int irq, void *arg)
4190{
4191 struct drm_device *dev = arg;
4192 struct drm_i915_private *dev_priv = dev->dev_private;
4193 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4194 u32 flip_mask =
4195 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4196 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4197 int pipe, ret = IRQ_NONE;
4198
4199 if (!intel_irqs_enabled(dev_priv))
4200 return IRQ_NONE;
4201
4202 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4203 disable_rpm_wakeref_asserts(dev_priv);
4204
4205 iir = I915_READ(IIR);
4206 do {
4207 bool irq_received = (iir & ~flip_mask) != 0;
4208 bool blc_event = false;
4209
4210 /* Can't rely on pipestat interrupt bit in iir as it might
4211 * have been cleared after the pipestat interrupt was received.
4212 * It doesn't set the bit in iir again, but it still produces
4213 * interrupts (for non-MSI).
4214 */
4215 spin_lock(&dev_priv->irq_lock);
4216 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4217 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4218
4219 for_each_pipe(dev_priv, pipe) {
4220 i915_reg_t reg = PIPESTAT(pipe);
4221 pipe_stats[pipe] = I915_READ(reg);
4222
4223 /* Clear the PIPE*STAT regs before the IIR */
4224 if (pipe_stats[pipe] & 0x8000ffff) {
4225 I915_WRITE(reg, pipe_stats[pipe]);
4226 irq_received = true;
4227 }
4228 }
4229 spin_unlock(&dev_priv->irq_lock);
4230
4231 if (!irq_received)
4232 break;
4233
4234 /* Consume port. Then clear IIR or we'll miss events */
4235 if (I915_HAS_HOTPLUG(dev) &&
4236 iir & I915_DISPLAY_PORT_INTERRUPT)
4237 i9xx_hpd_irq_handler(dev);
4238
4239 I915_WRITE(IIR, iir & ~flip_mask);
4240 new_iir = I915_READ(IIR); /* Flush posted writes */
4241
4242 if (iir & I915_USER_INTERRUPT)
4243 notify_ring(&dev_priv->ring[RCS]);
4244
4245 for_each_pipe(dev_priv, pipe) {
4246 int plane = pipe;
4247 if (HAS_FBC(dev))
4248 plane = !plane;
4249
4250 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4251 i915_handle_vblank(dev, plane, pipe, iir))
4252 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4253
4254 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4255 blc_event = true;
4256
4257 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4258 i9xx_pipe_crc_irq_handler(dev, pipe);
4259
4260 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4261 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4262 pipe);
4263 }
4264
4265 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4266 intel_opregion_asle_intr(dev);
4267
4268 /* With MSI, interrupts are only generated when iir
4269 * transitions from zero to nonzero. If another bit got
4270 * set while we were handling the existing iir bits, then
4271 * we would never get another interrupt.
4272 *
4273 * This is fine on non-MSI as well, as if we hit this path
4274 * we avoid exiting the interrupt handler only to generate
4275 * another one.
4276 *
4277 * Note that for MSI this could cause a stray interrupt report
4278 * if an interrupt landed in the time between writing IIR and
4279 * the posting read. This should be rare enough to never
4280 * trigger the 99% of 100,000 interrupts test for disabling
4281 * stray interrupts.
4282 */
4283 ret = IRQ_HANDLED;
4284 iir = new_iir;
4285 } while (iir & ~flip_mask);
4286
4287 enable_rpm_wakeref_asserts(dev_priv);
4288
4289 return ret;
4290}
4291
4292static void i915_irq_uninstall(struct drm_device * dev)
4293{
4294 struct drm_i915_private *dev_priv = dev->dev_private;
4295 int pipe;
4296
4297 if (I915_HAS_HOTPLUG(dev)) {
4298 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4299 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4300 }
4301
4302 I915_WRITE16(HWSTAM, 0xffff);
4303 for_each_pipe(dev_priv, pipe) {
4304 /* Clear enable bits; then clear status bits */
4305 I915_WRITE(PIPESTAT(pipe), 0);
4306 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4307 }
4308 I915_WRITE(IMR, 0xffffffff);
4309 I915_WRITE(IER, 0x0);
4310
4311 I915_WRITE(IIR, I915_READ(IIR));
4312}
4313
4314static void i965_irq_preinstall(struct drm_device * dev)
4315{
4316 struct drm_i915_private *dev_priv = dev->dev_private;
4317 int pipe;
4318
4319 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4320 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4321
4322 I915_WRITE(HWSTAM, 0xeffe);
4323 for_each_pipe(dev_priv, pipe)
4324 I915_WRITE(PIPESTAT(pipe), 0);
4325 I915_WRITE(IMR, 0xffffffff);
4326 I915_WRITE(IER, 0x0);
4327 POSTING_READ(IER);
4328}
4329
4330static int i965_irq_postinstall(struct drm_device *dev)
4331{
4332 struct drm_i915_private *dev_priv = dev->dev_private;
4333 u32 enable_mask;
4334 u32 error_mask;
4335
4336 /* Unmask the interrupts that we always want on. */
4337 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4338 I915_DISPLAY_PORT_INTERRUPT |
4339 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4340 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4341 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4342 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4343 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4344
4345 enable_mask = ~dev_priv->irq_mask;
4346 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4347 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4348 enable_mask |= I915_USER_INTERRUPT;
4349
4350 if (IS_G4X(dev))
4351 enable_mask |= I915_BSD_USER_INTERRUPT;
4352
4353 /* Interrupt setup is already guaranteed to be single-threaded, this is
4354 * just to make the assert_spin_locked check happy. */
4355 spin_lock_irq(&dev_priv->irq_lock);
4356 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4357 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4358 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4359 spin_unlock_irq(&dev_priv->irq_lock);
4360
4361 /*
4362 * Enable some error detection, note the instruction error mask
4363 * bit is reserved, so we leave it masked.
4364 */
4365 if (IS_G4X(dev)) {
4366 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4367 GM45_ERROR_MEM_PRIV |
4368 GM45_ERROR_CP_PRIV |
4369 I915_ERROR_MEMORY_REFRESH);
4370 } else {
4371 error_mask = ~(I915_ERROR_PAGE_TABLE |
4372 I915_ERROR_MEMORY_REFRESH);
4373 }
4374 I915_WRITE(EMR, error_mask);
4375
4376 I915_WRITE(IMR, dev_priv->irq_mask);
4377 I915_WRITE(IER, enable_mask);
4378 POSTING_READ(IER);
4379
4380 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4381 POSTING_READ(PORT_HOTPLUG_EN);
4382
4383 i915_enable_asle_pipestat(dev);
4384
4385 return 0;
4386}
4387
4388static void i915_hpd_irq_setup(struct drm_device *dev)
4389{
4390 struct drm_i915_private *dev_priv = dev->dev_private;
4391 u32 hotplug_en;
4392
4393 assert_spin_locked(&dev_priv->irq_lock);
4394
4395 /* Note HDMI and DP share hotplug bits */
4396 /* enable bits are the same for all generations */
4397 hotplug_en = intel_hpd_enabled_irqs(dev, hpd_mask_i915);
4398 /* Programming the CRT detection parameters tends
4399 to generate a spurious hotplug event about three
4400 seconds later. So just do it once.
4401 */
4402 if (IS_G4X(dev))
4403 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4404 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4405
4406 /* Ignore TV since it's buggy */
4407 i915_hotplug_interrupt_update_locked(dev_priv,
4408 HOTPLUG_INT_EN_MASK |
4409 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4410 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4411 hotplug_en);
4412}
4413
4414static irqreturn_t i965_irq_handler(int irq, void *arg)
4415{
4416 struct drm_device *dev = arg;
4417 struct drm_i915_private *dev_priv = dev->dev_private;
4418 u32 iir, new_iir;
4419 u32 pipe_stats[I915_MAX_PIPES];
4420 int ret = IRQ_NONE, pipe;
4421 u32 flip_mask =
4422 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4423 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4424
4425 if (!intel_irqs_enabled(dev_priv))
4426 return IRQ_NONE;
4427
4428 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4429 disable_rpm_wakeref_asserts(dev_priv);
4430
4431 iir = I915_READ(IIR);
4432
4433 for (;;) {
4434 bool irq_received = (iir & ~flip_mask) != 0;
4435 bool blc_event = false;
4436
4437 /* Can't rely on pipestat interrupt bit in iir as it might
4438 * have been cleared after the pipestat interrupt was received.
4439 * It doesn't set the bit in iir again, but it still produces
4440 * interrupts (for non-MSI).
4441 */
4442 spin_lock(&dev_priv->irq_lock);
4443 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4444 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4445
4446 for_each_pipe(dev_priv, pipe) {
4447 i915_reg_t reg = PIPESTAT(pipe);
4448 pipe_stats[pipe] = I915_READ(reg);
4449
4450 /*
4451 * Clear the PIPE*STAT regs before the IIR
4452 */
4453 if (pipe_stats[pipe] & 0x8000ffff) {
4454 I915_WRITE(reg, pipe_stats[pipe]);
4455 irq_received = true;
4456 }
4457 }
4458 spin_unlock(&dev_priv->irq_lock);
4459
4460 if (!irq_received)
4461 break;
4462
4463 ret = IRQ_HANDLED;
4464
4465 /* Consume port. Then clear IIR or we'll miss events */
4466 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4467 i9xx_hpd_irq_handler(dev);
4468
4469 I915_WRITE(IIR, iir & ~flip_mask);
4470 new_iir = I915_READ(IIR); /* Flush posted writes */
4471
4472 if (iir & I915_USER_INTERRUPT)
4473 notify_ring(&dev_priv->ring[RCS]);
4474 if (iir & I915_BSD_USER_INTERRUPT)
4475 notify_ring(&dev_priv->ring[VCS]);
4476
4477 for_each_pipe(dev_priv, pipe) {
4478 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4479 i915_handle_vblank(dev, pipe, pipe, iir))
4480 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4481
4482 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4483 blc_event = true;
4484
4485 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4486 i9xx_pipe_crc_irq_handler(dev, pipe);
4487
4488 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4489 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4490 }
4491
4492 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4493 intel_opregion_asle_intr(dev);
4494
4495 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4496 gmbus_irq_handler(dev);
4497
4498 /* With MSI, interrupts are only generated when iir
4499 * transitions from zero to nonzero. If another bit got
4500 * set while we were handling the existing iir bits, then
4501 * we would never get another interrupt.
4502 *
4503 * This is fine on non-MSI as well, as if we hit this path
4504 * we avoid exiting the interrupt handler only to generate
4505 * another one.
4506 *
4507 * Note that for MSI this could cause a stray interrupt report
4508 * if an interrupt landed in the time between writing IIR and
4509 * the posting read. This should be rare enough to never
4510 * trigger the 99% of 100,000 interrupts test for disabling
4511 * stray interrupts.
4512 */
4513 iir = new_iir;
4514 }
4515
4516 enable_rpm_wakeref_asserts(dev_priv);
4517
4518 return ret;
4519}
4520
4521static void i965_irq_uninstall(struct drm_device * dev)
4522{
4523 struct drm_i915_private *dev_priv = dev->dev_private;
4524 int pipe;
4525
4526 if (!dev_priv)
4527 return;
4528
4529 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4530 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4531
4532 I915_WRITE(HWSTAM, 0xffffffff);
4533 for_each_pipe(dev_priv, pipe)
4534 I915_WRITE(PIPESTAT(pipe), 0);
4535 I915_WRITE(IMR, 0xffffffff);
4536 I915_WRITE(IER, 0x0);
4537
4538 for_each_pipe(dev_priv, pipe)
4539 I915_WRITE(PIPESTAT(pipe),
4540 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4541 I915_WRITE(IIR, I915_READ(IIR));
4542}
4543
4544/**
4545 * intel_irq_init - initializes irq support
4546 * @dev_priv: i915 device instance
4547 *
4548 * This function initializes all the irq support including work items, timers
4549 * and all the vtables. It does not setup the interrupt itself though.
4550 */
4551void intel_irq_init(struct drm_i915_private *dev_priv)
4552{
4553 struct drm_device *dev = dev_priv->dev;
4554
4555 intel_hpd_init_work(dev_priv);
4556
4557 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4558 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4559
4560 /* Let's track the enabled rps events */
4561 if (IS_VALLEYVIEW(dev_priv))
4562 /* WaGsvRC0ResidencyMethod:vlv */
4563 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4564 else
4565 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4566
4567 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4568 i915_hangcheck_elapsed);
4569
4570 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4571
4572 if (IS_GEN2(dev_priv)) {
4573 dev->max_vblank_count = 0;
4574 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4575 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4576 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4577 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4578 } else {
4579 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4580 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4581 }
4582
4583 /*
4584 * Opt out of the vblank disable timer on everything except gen2.
4585 * Gen2 doesn't have a hardware frame counter and so depends on
4586 * vblank interrupts to produce sane vblank seuquence numbers.
4587 */
4588 if (!IS_GEN2(dev_priv))
4589 dev->vblank_disable_immediate = true;
4590
4591 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4592 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4593
4594 if (IS_CHERRYVIEW(dev_priv)) {
4595 dev->driver->irq_handler = cherryview_irq_handler;
4596 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4597 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4598 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4599 dev->driver->enable_vblank = valleyview_enable_vblank;
4600 dev->driver->disable_vblank = valleyview_disable_vblank;
4601 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4602 } else if (IS_VALLEYVIEW(dev_priv)) {
4603 dev->driver->irq_handler = valleyview_irq_handler;
4604 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4605 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4606 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4607 dev->driver->enable_vblank = valleyview_enable_vblank;
4608 dev->driver->disable_vblank = valleyview_disable_vblank;
4609 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4610 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4611 dev->driver->irq_handler = gen8_irq_handler;
4612 dev->driver->irq_preinstall = gen8_irq_reset;
4613 dev->driver->irq_postinstall = gen8_irq_postinstall;
4614 dev->driver->irq_uninstall = gen8_irq_uninstall;
4615 dev->driver->enable_vblank = gen8_enable_vblank;
4616 dev->driver->disable_vblank = gen8_disable_vblank;
4617 if (IS_BROXTON(dev))
4618 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4619 else if (HAS_PCH_SPT(dev))
4620 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4621 else
4622 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4623 } else if (HAS_PCH_SPLIT(dev)) {
4624 dev->driver->irq_handler = ironlake_irq_handler;
4625 dev->driver->irq_preinstall = ironlake_irq_reset;
4626 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4627 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4628 dev->driver->enable_vblank = ironlake_enable_vblank;
4629 dev->driver->disable_vblank = ironlake_disable_vblank;
4630 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4631 } else {
4632 if (INTEL_INFO(dev_priv)->gen == 2) {
4633 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4634 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4635 dev->driver->irq_handler = i8xx_irq_handler;
4636 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4637 } else if (INTEL_INFO(dev_priv)->gen == 3) {
4638 dev->driver->irq_preinstall = i915_irq_preinstall;
4639 dev->driver->irq_postinstall = i915_irq_postinstall;
4640 dev->driver->irq_uninstall = i915_irq_uninstall;
4641 dev->driver->irq_handler = i915_irq_handler;
4642 } else {
4643 dev->driver->irq_preinstall = i965_irq_preinstall;
4644 dev->driver->irq_postinstall = i965_irq_postinstall;
4645 dev->driver->irq_uninstall = i965_irq_uninstall;
4646 dev->driver->irq_handler = i965_irq_handler;
4647 }
4648 if (I915_HAS_HOTPLUG(dev_priv))
4649 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4650 dev->driver->enable_vblank = i915_enable_vblank;
4651 dev->driver->disable_vblank = i915_disable_vblank;
4652 }
4653}
4654
4655/**
4656 * intel_irq_install - enables the hardware interrupt
4657 * @dev_priv: i915 device instance
4658 *
4659 * This function enables the hardware interrupt handling, but leaves the hotplug
4660 * handling still disabled. It is called after intel_irq_init().
4661 *
4662 * In the driver load and resume code we need working interrupts in a few places
4663 * but don't want to deal with the hassle of concurrent probe and hotplug
4664 * workers. Hence the split into this two-stage approach.
4665 */
4666int intel_irq_install(struct drm_i915_private *dev_priv)
4667{
4668 /*
4669 * We enable some interrupt sources in our postinstall hooks, so mark
4670 * interrupts as enabled _before_ actually enabling them to avoid
4671 * special cases in our ordering checks.
4672 */
4673 dev_priv->pm.irqs_enabled = true;
4674
4675 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4676}
4677
4678/**
4679 * intel_irq_uninstall - finilizes all irq handling
4680 * @dev_priv: i915 device instance
4681 *
4682 * This stops interrupt and hotplug handling and unregisters and frees all
4683 * resources acquired in the init functions.
4684 */
4685void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4686{
4687 drm_irq_uninstall(dev_priv->dev);
4688 intel_hpd_cancel_work(dev_priv);
4689 dev_priv->pm.irqs_enabled = false;
4690}
4691
4692/**
4693 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4694 * @dev_priv: i915 device instance
4695 *
4696 * This function is used to disable interrupts at runtime, both in the runtime
4697 * pm and the system suspend/resume code.
4698 */
4699void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4700{
4701 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4702 dev_priv->pm.irqs_enabled = false;
4703 synchronize_irq(dev_priv->dev->irq);
4704}
4705
4706/**
4707 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4708 * @dev_priv: i915 device instance
4709 *
4710 * This function is used to enable interrupts at runtime, both in the runtime
4711 * pm and the system suspend/resume code.
4712 */
4713void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4714{
4715 dev_priv->pm.irqs_enabled = true;
4716 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4717 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4718}
1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3/*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31#include <linux/circ_buf.h>
32#include <linux/cpuidle.h>
33#include <linux/slab.h>
34#include <linux/sysrq.h>
35
36#include <drm/drm_drv.h>
37#include <drm/drm_irq.h>
38#include <drm/i915_drm.h>
39
40#include "display/intel_display_types.h"
41#include "display/intel_fifo_underrun.h"
42#include "display/intel_hotplug.h"
43#include "display/intel_lpe_audio.h"
44#include "display/intel_psr.h"
45
46#include "gt/intel_gt.h"
47#include "gt/intel_gt_irq.h"
48#include "gt/intel_gt_pm_irq.h"
49
50#include "i915_drv.h"
51#include "i915_irq.h"
52#include "i915_trace.h"
53#include "intel_pm.h"
54
55/**
56 * DOC: interrupt handling
57 *
58 * These functions provide the basic support for enabling and disabling the
59 * interrupt handling support. There's a lot more functionality in i915_irq.c
60 * and related files, but that will be described in separate chapters.
61 */
62
63typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
64
65static const u32 hpd_ilk[HPD_NUM_PINS] = {
66 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
67};
68
69static const u32 hpd_ivb[HPD_NUM_PINS] = {
70 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
71};
72
73static const u32 hpd_bdw[HPD_NUM_PINS] = {
74 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
75};
76
77static const u32 hpd_ibx[HPD_NUM_PINS] = {
78 [HPD_CRT] = SDE_CRT_HOTPLUG,
79 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
80 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
81 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
82 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
83};
84
85static const u32 hpd_cpt[HPD_NUM_PINS] = {
86 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
87 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
88 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
89 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
90 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
91};
92
93static const u32 hpd_spt[HPD_NUM_PINS] = {
94 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
95 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
96 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
97 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
98 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
99};
100
101static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
102 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
103 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
104 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
105 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
106 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
107 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
108};
109
110static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
111 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
112 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
113 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
114 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
115 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
116 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
117};
118
119static const u32 hpd_status_i915[HPD_NUM_PINS] = {
120 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
121 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
122 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
123 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
124 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
125 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
126};
127
128/* BXT hpd list */
129static const u32 hpd_bxt[HPD_NUM_PINS] = {
130 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
131 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
132 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
133};
134
135static const u32 hpd_gen11[HPD_NUM_PINS] = {
136 [HPD_PORT_C] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
137 [HPD_PORT_D] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
138 [HPD_PORT_E] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
139 [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG
140};
141
142static const u32 hpd_gen12[HPD_NUM_PINS] = {
143 [HPD_PORT_D] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
144 [HPD_PORT_E] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
145 [HPD_PORT_F] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
146 [HPD_PORT_G] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG,
147 [HPD_PORT_H] = GEN12_TC5_HOTPLUG | GEN12_TBT5_HOTPLUG,
148 [HPD_PORT_I] = GEN12_TC6_HOTPLUG | GEN12_TBT6_HOTPLUG
149};
150
151static const u32 hpd_icp[HPD_NUM_PINS] = {
152 [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
153 [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
154 [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP,
155 [HPD_PORT_D] = SDE_TC2_HOTPLUG_ICP,
156 [HPD_PORT_E] = SDE_TC3_HOTPLUG_ICP,
157 [HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP
158};
159
160static const u32 hpd_mcc[HPD_NUM_PINS] = {
161 [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
162 [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
163 [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP
164};
165
166static const u32 hpd_tgp[HPD_NUM_PINS] = {
167 [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
168 [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
169 [HPD_PORT_C] = SDE_DDIC_HOTPLUG_TGP,
170 [HPD_PORT_D] = SDE_TC1_HOTPLUG_ICP,
171 [HPD_PORT_E] = SDE_TC2_HOTPLUG_ICP,
172 [HPD_PORT_F] = SDE_TC3_HOTPLUG_ICP,
173 [HPD_PORT_G] = SDE_TC4_HOTPLUG_ICP,
174 [HPD_PORT_H] = SDE_TC5_HOTPLUG_TGP,
175 [HPD_PORT_I] = SDE_TC6_HOTPLUG_TGP,
176};
177
178void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
179 i915_reg_t iir, i915_reg_t ier)
180{
181 intel_uncore_write(uncore, imr, 0xffffffff);
182 intel_uncore_posting_read(uncore, imr);
183
184 intel_uncore_write(uncore, ier, 0);
185
186 /* IIR can theoretically queue up two events. Be paranoid. */
187 intel_uncore_write(uncore, iir, 0xffffffff);
188 intel_uncore_posting_read(uncore, iir);
189 intel_uncore_write(uncore, iir, 0xffffffff);
190 intel_uncore_posting_read(uncore, iir);
191}
192
193void gen2_irq_reset(struct intel_uncore *uncore)
194{
195 intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
196 intel_uncore_posting_read16(uncore, GEN2_IMR);
197
198 intel_uncore_write16(uncore, GEN2_IER, 0);
199
200 /* IIR can theoretically queue up two events. Be paranoid. */
201 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
202 intel_uncore_posting_read16(uncore, GEN2_IIR);
203 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
204 intel_uncore_posting_read16(uncore, GEN2_IIR);
205}
206
207/*
208 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
209 */
210static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
211{
212 u32 val = intel_uncore_read(uncore, reg);
213
214 if (val == 0)
215 return;
216
217 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
218 i915_mmio_reg_offset(reg), val);
219 intel_uncore_write(uncore, reg, 0xffffffff);
220 intel_uncore_posting_read(uncore, reg);
221 intel_uncore_write(uncore, reg, 0xffffffff);
222 intel_uncore_posting_read(uncore, reg);
223}
224
225static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
226{
227 u16 val = intel_uncore_read16(uncore, GEN2_IIR);
228
229 if (val == 0)
230 return;
231
232 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
233 i915_mmio_reg_offset(GEN2_IIR), val);
234 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
235 intel_uncore_posting_read16(uncore, GEN2_IIR);
236 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
237 intel_uncore_posting_read16(uncore, GEN2_IIR);
238}
239
240void gen3_irq_init(struct intel_uncore *uncore,
241 i915_reg_t imr, u32 imr_val,
242 i915_reg_t ier, u32 ier_val,
243 i915_reg_t iir)
244{
245 gen3_assert_iir_is_zero(uncore, iir);
246
247 intel_uncore_write(uncore, ier, ier_val);
248 intel_uncore_write(uncore, imr, imr_val);
249 intel_uncore_posting_read(uncore, imr);
250}
251
252void gen2_irq_init(struct intel_uncore *uncore,
253 u32 imr_val, u32 ier_val)
254{
255 gen2_assert_iir_is_zero(uncore);
256
257 intel_uncore_write16(uncore, GEN2_IER, ier_val);
258 intel_uncore_write16(uncore, GEN2_IMR, imr_val);
259 intel_uncore_posting_read16(uncore, GEN2_IMR);
260}
261
262/* For display hotplug interrupt */
263static inline void
264i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
265 u32 mask,
266 u32 bits)
267{
268 u32 val;
269
270 lockdep_assert_held(&dev_priv->irq_lock);
271 WARN_ON(bits & ~mask);
272
273 val = I915_READ(PORT_HOTPLUG_EN);
274 val &= ~mask;
275 val |= bits;
276 I915_WRITE(PORT_HOTPLUG_EN, val);
277}
278
279/**
280 * i915_hotplug_interrupt_update - update hotplug interrupt enable
281 * @dev_priv: driver private
282 * @mask: bits to update
283 * @bits: bits to enable
284 * NOTE: the HPD enable bits are modified both inside and outside
285 * of an interrupt context. To avoid that read-modify-write cycles
286 * interfer, these bits are protected by a spinlock. Since this
287 * function is usually not called from a context where the lock is
288 * held already, this function acquires the lock itself. A non-locking
289 * version is also available.
290 */
291void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
292 u32 mask,
293 u32 bits)
294{
295 spin_lock_irq(&dev_priv->irq_lock);
296 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
297 spin_unlock_irq(&dev_priv->irq_lock);
298}
299
300/**
301 * ilk_update_display_irq - update DEIMR
302 * @dev_priv: driver private
303 * @interrupt_mask: mask of interrupt bits to update
304 * @enabled_irq_mask: mask of interrupt bits to enable
305 */
306void ilk_update_display_irq(struct drm_i915_private *dev_priv,
307 u32 interrupt_mask,
308 u32 enabled_irq_mask)
309{
310 u32 new_val;
311
312 lockdep_assert_held(&dev_priv->irq_lock);
313
314 WARN_ON(enabled_irq_mask & ~interrupt_mask);
315
316 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
317 return;
318
319 new_val = dev_priv->irq_mask;
320 new_val &= ~interrupt_mask;
321 new_val |= (~enabled_irq_mask & interrupt_mask);
322
323 if (new_val != dev_priv->irq_mask) {
324 dev_priv->irq_mask = new_val;
325 I915_WRITE(DEIMR, dev_priv->irq_mask);
326 POSTING_READ(DEIMR);
327 }
328}
329
330static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
331{
332 WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11);
333
334 return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
335}
336
337void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv)
338{
339 struct intel_gt *gt = &dev_priv->gt;
340
341 spin_lock_irq(>->irq_lock);
342
343 while (gen11_gt_reset_one_iir(gt, 0, GEN11_GTPM))
344 ;
345
346 dev_priv->gt_pm.rps.pm_iir = 0;
347
348 spin_unlock_irq(>->irq_lock);
349}
350
351void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
352{
353 struct intel_gt *gt = &dev_priv->gt;
354
355 spin_lock_irq(>->irq_lock);
356 gen6_gt_pm_reset_iir(gt, GEN6_PM_RPS_EVENTS);
357 dev_priv->gt_pm.rps.pm_iir = 0;
358 spin_unlock_irq(>->irq_lock);
359}
360
361void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
362{
363 struct intel_gt *gt = &dev_priv->gt;
364 struct intel_rps *rps = &dev_priv->gt_pm.rps;
365
366 if (READ_ONCE(rps->interrupts_enabled))
367 return;
368
369 spin_lock_irq(>->irq_lock);
370 WARN_ON_ONCE(rps->pm_iir);
371
372 if (INTEL_GEN(dev_priv) >= 11)
373 WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_GTPM));
374 else
375 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
376
377 rps->interrupts_enabled = true;
378 gen6_gt_pm_enable_irq(gt, dev_priv->pm_rps_events);
379
380 spin_unlock_irq(>->irq_lock);
381}
382
383u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask)
384{
385 return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
386}
387
388void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
389{
390 struct intel_rps *rps = &dev_priv->gt_pm.rps;
391 struct intel_gt *gt = &dev_priv->gt;
392
393 if (!READ_ONCE(rps->interrupts_enabled))
394 return;
395
396 spin_lock_irq(>->irq_lock);
397 rps->interrupts_enabled = false;
398
399 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
400
401 gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS);
402
403 spin_unlock_irq(>->irq_lock);
404 intel_synchronize_irq(dev_priv);
405
406 /* Now that we will not be generating any more work, flush any
407 * outstanding tasks. As we are called on the RPS idle path,
408 * we will reset the GPU to minimum frequencies, so the current
409 * state of the worker can be discarded.
410 */
411 cancel_work_sync(&rps->work);
412 if (INTEL_GEN(dev_priv) >= 11)
413 gen11_reset_rps_interrupts(dev_priv);
414 else
415 gen6_reset_rps_interrupts(dev_priv);
416}
417
418void gen9_reset_guc_interrupts(struct intel_guc *guc)
419{
420 struct intel_gt *gt = guc_to_gt(guc);
421
422 assert_rpm_wakelock_held(>->i915->runtime_pm);
423
424 spin_lock_irq(>->irq_lock);
425 gen6_gt_pm_reset_iir(gt, gt->pm_guc_events);
426 spin_unlock_irq(>->irq_lock);
427}
428
429void gen9_enable_guc_interrupts(struct intel_guc *guc)
430{
431 struct intel_gt *gt = guc_to_gt(guc);
432
433 assert_rpm_wakelock_held(>->i915->runtime_pm);
434
435 spin_lock_irq(>->irq_lock);
436 if (!guc->interrupts.enabled) {
437 WARN_ON_ONCE(intel_uncore_read(gt->uncore,
438 gen6_pm_iir(gt->i915)) &
439 gt->pm_guc_events);
440 guc->interrupts.enabled = true;
441 gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
442 }
443 spin_unlock_irq(>->irq_lock);
444}
445
446void gen9_disable_guc_interrupts(struct intel_guc *guc)
447{
448 struct intel_gt *gt = guc_to_gt(guc);
449
450 assert_rpm_wakelock_held(>->i915->runtime_pm);
451
452 spin_lock_irq(>->irq_lock);
453 guc->interrupts.enabled = false;
454
455 gen6_gt_pm_disable_irq(gt, gt->pm_guc_events);
456
457 spin_unlock_irq(>->irq_lock);
458 intel_synchronize_irq(gt->i915);
459
460 gen9_reset_guc_interrupts(guc);
461}
462
463void gen11_reset_guc_interrupts(struct intel_guc *guc)
464{
465 struct intel_gt *gt = guc_to_gt(guc);
466
467 spin_lock_irq(>->irq_lock);
468 gen11_gt_reset_one_iir(gt, 0, GEN11_GUC);
469 spin_unlock_irq(>->irq_lock);
470}
471
472void gen11_enable_guc_interrupts(struct intel_guc *guc)
473{
474 struct intel_gt *gt = guc_to_gt(guc);
475
476 spin_lock_irq(>->irq_lock);
477 if (!guc->interrupts.enabled) {
478 u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
479
480 WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_GUC));
481 intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, events);
482 intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~events);
483 guc->interrupts.enabled = true;
484 }
485 spin_unlock_irq(>->irq_lock);
486}
487
488void gen11_disable_guc_interrupts(struct intel_guc *guc)
489{
490 struct intel_gt *gt = guc_to_gt(guc);
491
492 spin_lock_irq(>->irq_lock);
493 guc->interrupts.enabled = false;
494
495 intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~0);
496 intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
497
498 spin_unlock_irq(>->irq_lock);
499 intel_synchronize_irq(gt->i915);
500
501 gen11_reset_guc_interrupts(guc);
502}
503
504/**
505 * bdw_update_port_irq - update DE port interrupt
506 * @dev_priv: driver private
507 * @interrupt_mask: mask of interrupt bits to update
508 * @enabled_irq_mask: mask of interrupt bits to enable
509 */
510static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
511 u32 interrupt_mask,
512 u32 enabled_irq_mask)
513{
514 u32 new_val;
515 u32 old_val;
516
517 lockdep_assert_held(&dev_priv->irq_lock);
518
519 WARN_ON(enabled_irq_mask & ~interrupt_mask);
520
521 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
522 return;
523
524 old_val = I915_READ(GEN8_DE_PORT_IMR);
525
526 new_val = old_val;
527 new_val &= ~interrupt_mask;
528 new_val |= (~enabled_irq_mask & interrupt_mask);
529
530 if (new_val != old_val) {
531 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
532 POSTING_READ(GEN8_DE_PORT_IMR);
533 }
534}
535
536/**
537 * bdw_update_pipe_irq - update DE pipe interrupt
538 * @dev_priv: driver private
539 * @pipe: pipe whose interrupt to update
540 * @interrupt_mask: mask of interrupt bits to update
541 * @enabled_irq_mask: mask of interrupt bits to enable
542 */
543void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
544 enum pipe pipe,
545 u32 interrupt_mask,
546 u32 enabled_irq_mask)
547{
548 u32 new_val;
549
550 lockdep_assert_held(&dev_priv->irq_lock);
551
552 WARN_ON(enabled_irq_mask & ~interrupt_mask);
553
554 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
555 return;
556
557 new_val = dev_priv->de_irq_mask[pipe];
558 new_val &= ~interrupt_mask;
559 new_val |= (~enabled_irq_mask & interrupt_mask);
560
561 if (new_val != dev_priv->de_irq_mask[pipe]) {
562 dev_priv->de_irq_mask[pipe] = new_val;
563 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
564 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
565 }
566}
567
568/**
569 * ibx_display_interrupt_update - update SDEIMR
570 * @dev_priv: driver private
571 * @interrupt_mask: mask of interrupt bits to update
572 * @enabled_irq_mask: mask of interrupt bits to enable
573 */
574void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
575 u32 interrupt_mask,
576 u32 enabled_irq_mask)
577{
578 u32 sdeimr = I915_READ(SDEIMR);
579 sdeimr &= ~interrupt_mask;
580 sdeimr |= (~enabled_irq_mask & interrupt_mask);
581
582 WARN_ON(enabled_irq_mask & ~interrupt_mask);
583
584 lockdep_assert_held(&dev_priv->irq_lock);
585
586 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
587 return;
588
589 I915_WRITE(SDEIMR, sdeimr);
590 POSTING_READ(SDEIMR);
591}
592
593u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
594 enum pipe pipe)
595{
596 u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
597 u32 enable_mask = status_mask << 16;
598
599 lockdep_assert_held(&dev_priv->irq_lock);
600
601 if (INTEL_GEN(dev_priv) < 5)
602 goto out;
603
604 /*
605 * On pipe A we don't support the PSR interrupt yet,
606 * on pipe B and C the same bit MBZ.
607 */
608 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
609 return 0;
610 /*
611 * On pipe B and C we don't support the PSR interrupt yet, on pipe
612 * A the same bit is for perf counters which we don't use either.
613 */
614 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
615 return 0;
616
617 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
618 SPRITE0_FLIP_DONE_INT_EN_VLV |
619 SPRITE1_FLIP_DONE_INT_EN_VLV);
620 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
621 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
622 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
623 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
624
625out:
626 WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
627 status_mask & ~PIPESTAT_INT_STATUS_MASK,
628 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
629 pipe_name(pipe), enable_mask, status_mask);
630
631 return enable_mask;
632}
633
634void i915_enable_pipestat(struct drm_i915_private *dev_priv,
635 enum pipe pipe, u32 status_mask)
636{
637 i915_reg_t reg = PIPESTAT(pipe);
638 u32 enable_mask;
639
640 WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
641 "pipe %c: status_mask=0x%x\n",
642 pipe_name(pipe), status_mask);
643
644 lockdep_assert_held(&dev_priv->irq_lock);
645 WARN_ON(!intel_irqs_enabled(dev_priv));
646
647 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
648 return;
649
650 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
651 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
652
653 I915_WRITE(reg, enable_mask | status_mask);
654 POSTING_READ(reg);
655}
656
657void i915_disable_pipestat(struct drm_i915_private *dev_priv,
658 enum pipe pipe, u32 status_mask)
659{
660 i915_reg_t reg = PIPESTAT(pipe);
661 u32 enable_mask;
662
663 WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
664 "pipe %c: status_mask=0x%x\n",
665 pipe_name(pipe), status_mask);
666
667 lockdep_assert_held(&dev_priv->irq_lock);
668 WARN_ON(!intel_irqs_enabled(dev_priv));
669
670 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
671 return;
672
673 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
674 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
675
676 I915_WRITE(reg, enable_mask | status_mask);
677 POSTING_READ(reg);
678}
679
680static bool i915_has_asle(struct drm_i915_private *dev_priv)
681{
682 if (!dev_priv->opregion.asle)
683 return false;
684
685 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
686}
687
688/**
689 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
690 * @dev_priv: i915 device private
691 */
692static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
693{
694 if (!i915_has_asle(dev_priv))
695 return;
696
697 spin_lock_irq(&dev_priv->irq_lock);
698
699 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
700 if (INTEL_GEN(dev_priv) >= 4)
701 i915_enable_pipestat(dev_priv, PIPE_A,
702 PIPE_LEGACY_BLC_EVENT_STATUS);
703
704 spin_unlock_irq(&dev_priv->irq_lock);
705}
706
707/*
708 * This timing diagram depicts the video signal in and
709 * around the vertical blanking period.
710 *
711 * Assumptions about the fictitious mode used in this example:
712 * vblank_start >= 3
713 * vsync_start = vblank_start + 1
714 * vsync_end = vblank_start + 2
715 * vtotal = vblank_start + 3
716 *
717 * start of vblank:
718 * latch double buffered registers
719 * increment frame counter (ctg+)
720 * generate start of vblank interrupt (gen4+)
721 * |
722 * | frame start:
723 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
724 * | may be shifted forward 1-3 extra lines via PIPECONF
725 * | |
726 * | | start of vsync:
727 * | | generate vsync interrupt
728 * | | |
729 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
730 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
731 * ----va---> <-----------------vb--------------------> <--------va-------------
732 * | | <----vs-----> |
733 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
734 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
735 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
736 * | | |
737 * last visible pixel first visible pixel
738 * | increment frame counter (gen3/4)
739 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
740 *
741 * x = horizontal active
742 * _ = horizontal blanking
743 * hs = horizontal sync
744 * va = vertical active
745 * vb = vertical blanking
746 * vs = vertical sync
747 * vbs = vblank_start (number)
748 *
749 * Summary:
750 * - most events happen at the start of horizontal sync
751 * - frame start happens at the start of horizontal blank, 1-4 lines
752 * (depending on PIPECONF settings) after the start of vblank
753 * - gen3/4 pixel and frame counter are synchronized with the start
754 * of horizontal active on the first line of vertical active
755 */
756
757/* Called from drm generic code, passed a 'crtc', which
758 * we use as a pipe index
759 */
760u32 i915_get_vblank_counter(struct drm_crtc *crtc)
761{
762 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
763 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
764 const struct drm_display_mode *mode = &vblank->hwmode;
765 enum pipe pipe = to_intel_crtc(crtc)->pipe;
766 i915_reg_t high_frame, low_frame;
767 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
768 unsigned long irqflags;
769
770 /*
771 * On i965gm TV output the frame counter only works up to
772 * the point when we enable the TV encoder. After that the
773 * frame counter ceases to work and reads zero. We need a
774 * vblank wait before enabling the TV encoder and so we
775 * have to enable vblank interrupts while the frame counter
776 * is still in a working state. However the core vblank code
777 * does not like us returning non-zero frame counter values
778 * when we've told it that we don't have a working frame
779 * counter. Thus we must stop non-zero values leaking out.
780 */
781 if (!vblank->max_vblank_count)
782 return 0;
783
784 htotal = mode->crtc_htotal;
785 hsync_start = mode->crtc_hsync_start;
786 vbl_start = mode->crtc_vblank_start;
787 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
788 vbl_start = DIV_ROUND_UP(vbl_start, 2);
789
790 /* Convert to pixel count */
791 vbl_start *= htotal;
792
793 /* Start of vblank event occurs at start of hsync */
794 vbl_start -= htotal - hsync_start;
795
796 high_frame = PIPEFRAME(pipe);
797 low_frame = PIPEFRAMEPIXEL(pipe);
798
799 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
800
801 /*
802 * High & low register fields aren't synchronized, so make sure
803 * we get a low value that's stable across two reads of the high
804 * register.
805 */
806 do {
807 high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
808 low = I915_READ_FW(low_frame);
809 high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
810 } while (high1 != high2);
811
812 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
813
814 high1 >>= PIPE_FRAME_HIGH_SHIFT;
815 pixel = low & PIPE_PIXEL_MASK;
816 low >>= PIPE_FRAME_LOW_SHIFT;
817
818 /*
819 * The frame counter increments at beginning of active.
820 * Cook up a vblank counter by also checking the pixel
821 * counter against vblank start.
822 */
823 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
824}
825
826u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
827{
828 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
829 enum pipe pipe = to_intel_crtc(crtc)->pipe;
830
831 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
832}
833
834/*
835 * On certain encoders on certain platforms, pipe
836 * scanline register will not work to get the scanline,
837 * since the timings are driven from the PORT or issues
838 * with scanline register updates.
839 * This function will use Framestamp and current
840 * timestamp registers to calculate the scanline.
841 */
842static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
843{
844 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
845 struct drm_vblank_crtc *vblank =
846 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
847 const struct drm_display_mode *mode = &vblank->hwmode;
848 u32 vblank_start = mode->crtc_vblank_start;
849 u32 vtotal = mode->crtc_vtotal;
850 u32 htotal = mode->crtc_htotal;
851 u32 clock = mode->crtc_clock;
852 u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
853
854 /*
855 * To avoid the race condition where we might cross into the
856 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
857 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
858 * during the same frame.
859 */
860 do {
861 /*
862 * This field provides read back of the display
863 * pipe frame time stamp. The time stamp value
864 * is sampled at every start of vertical blank.
865 */
866 scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
867
868 /*
869 * The TIMESTAMP_CTR register has the current
870 * time stamp value.
871 */
872 scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR);
873
874 scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
875 } while (scan_post_time != scan_prev_time);
876
877 scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
878 clock), 1000 * htotal);
879 scanline = min(scanline, vtotal - 1);
880 scanline = (scanline + vblank_start) % vtotal;
881
882 return scanline;
883}
884
885/* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
886static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
887{
888 struct drm_device *dev = crtc->base.dev;
889 struct drm_i915_private *dev_priv = to_i915(dev);
890 const struct drm_display_mode *mode;
891 struct drm_vblank_crtc *vblank;
892 enum pipe pipe = crtc->pipe;
893 int position, vtotal;
894
895 if (!crtc->active)
896 return -1;
897
898 vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
899 mode = &vblank->hwmode;
900
901 if (mode->private_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
902 return __intel_get_crtc_scanline_from_timestamp(crtc);
903
904 vtotal = mode->crtc_vtotal;
905 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
906 vtotal /= 2;
907
908 if (IS_GEN(dev_priv, 2))
909 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
910 else
911 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
912
913 /*
914 * On HSW, the DSL reg (0x70000) appears to return 0 if we
915 * read it just before the start of vblank. So try it again
916 * so we don't accidentally end up spanning a vblank frame
917 * increment, causing the pipe_update_end() code to squak at us.
918 *
919 * The nature of this problem means we can't simply check the ISR
920 * bit and return the vblank start value; nor can we use the scanline
921 * debug register in the transcoder as it appears to have the same
922 * problem. We may need to extend this to include other platforms,
923 * but so far testing only shows the problem on HSW.
924 */
925 if (HAS_DDI(dev_priv) && !position) {
926 int i, temp;
927
928 for (i = 0; i < 100; i++) {
929 udelay(1);
930 temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
931 if (temp != position) {
932 position = temp;
933 break;
934 }
935 }
936 }
937
938 /*
939 * See update_scanline_offset() for the details on the
940 * scanline_offset adjustment.
941 */
942 return (position + crtc->scanline_offset) % vtotal;
943}
944
945bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
946 bool in_vblank_irq, int *vpos, int *hpos,
947 ktime_t *stime, ktime_t *etime,
948 const struct drm_display_mode *mode)
949{
950 struct drm_i915_private *dev_priv = to_i915(dev);
951 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
952 pipe);
953 int position;
954 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
955 unsigned long irqflags;
956 bool use_scanline_counter = INTEL_GEN(dev_priv) >= 5 ||
957 IS_G4X(dev_priv) || IS_GEN(dev_priv, 2) ||
958 mode->private_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
959
960 if (WARN_ON(!mode->crtc_clock)) {
961 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
962 "pipe %c\n", pipe_name(pipe));
963 return false;
964 }
965
966 htotal = mode->crtc_htotal;
967 hsync_start = mode->crtc_hsync_start;
968 vtotal = mode->crtc_vtotal;
969 vbl_start = mode->crtc_vblank_start;
970 vbl_end = mode->crtc_vblank_end;
971
972 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
973 vbl_start = DIV_ROUND_UP(vbl_start, 2);
974 vbl_end /= 2;
975 vtotal /= 2;
976 }
977
978 /*
979 * Lock uncore.lock, as we will do multiple timing critical raw
980 * register reads, potentially with preemption disabled, so the
981 * following code must not block on uncore.lock.
982 */
983 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
984
985 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
986
987 /* Get optional system timestamp before query. */
988 if (stime)
989 *stime = ktime_get();
990
991 if (use_scanline_counter) {
992 /* No obvious pixelcount register. Only query vertical
993 * scanout position from Display scan line register.
994 */
995 position = __intel_get_crtc_scanline(intel_crtc);
996 } else {
997 /* Have access to pixelcount since start of frame.
998 * We can split this into vertical and horizontal
999 * scanout position.
1000 */
1001 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
1002
1003 /* convert to pixel counts */
1004 vbl_start *= htotal;
1005 vbl_end *= htotal;
1006 vtotal *= htotal;
1007
1008 /*
1009 * In interlaced modes, the pixel counter counts all pixels,
1010 * so one field will have htotal more pixels. In order to avoid
1011 * the reported position from jumping backwards when the pixel
1012 * counter is beyond the length of the shorter field, just
1013 * clamp the position the length of the shorter field. This
1014 * matches how the scanline counter based position works since
1015 * the scanline counter doesn't count the two half lines.
1016 */
1017 if (position >= vtotal)
1018 position = vtotal - 1;
1019
1020 /*
1021 * Start of vblank interrupt is triggered at start of hsync,
1022 * just prior to the first active line of vblank. However we
1023 * consider lines to start at the leading edge of horizontal
1024 * active. So, should we get here before we've crossed into
1025 * the horizontal active of the first line in vblank, we would
1026 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
1027 * always add htotal-hsync_start to the current pixel position.
1028 */
1029 position = (position + htotal - hsync_start) % vtotal;
1030 }
1031
1032 /* Get optional system timestamp after query. */
1033 if (etime)
1034 *etime = ktime_get();
1035
1036 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1037
1038 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1039
1040 /*
1041 * While in vblank, position will be negative
1042 * counting up towards 0 at vbl_end. And outside
1043 * vblank, position will be positive counting
1044 * up since vbl_end.
1045 */
1046 if (position >= vbl_start)
1047 position -= vbl_end;
1048 else
1049 position += vtotal - vbl_end;
1050
1051 if (use_scanline_counter) {
1052 *vpos = position;
1053 *hpos = 0;
1054 } else {
1055 *vpos = position / htotal;
1056 *hpos = position - (*vpos * htotal);
1057 }
1058
1059 return true;
1060}
1061
1062int intel_get_crtc_scanline(struct intel_crtc *crtc)
1063{
1064 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1065 unsigned long irqflags;
1066 int position;
1067
1068 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1069 position = __intel_get_crtc_scanline(crtc);
1070 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1071
1072 return position;
1073}
1074
1075static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
1076{
1077 struct intel_uncore *uncore = &dev_priv->uncore;
1078 u32 busy_up, busy_down, max_avg, min_avg;
1079 u8 new_delay;
1080
1081 spin_lock(&mchdev_lock);
1082
1083 intel_uncore_write16(uncore,
1084 MEMINTRSTS,
1085 intel_uncore_read(uncore, MEMINTRSTS));
1086
1087 new_delay = dev_priv->ips.cur_delay;
1088
1089 intel_uncore_write16(uncore, MEMINTRSTS, MEMINT_EVAL_CHG);
1090 busy_up = intel_uncore_read(uncore, RCPREVBSYTUPAVG);
1091 busy_down = intel_uncore_read(uncore, RCPREVBSYTDNAVG);
1092 max_avg = intel_uncore_read(uncore, RCBMAXAVG);
1093 min_avg = intel_uncore_read(uncore, RCBMINAVG);
1094
1095 /* Handle RCS change request from hw */
1096 if (busy_up > max_avg) {
1097 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1098 new_delay = dev_priv->ips.cur_delay - 1;
1099 if (new_delay < dev_priv->ips.max_delay)
1100 new_delay = dev_priv->ips.max_delay;
1101 } else if (busy_down < min_avg) {
1102 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1103 new_delay = dev_priv->ips.cur_delay + 1;
1104 if (new_delay > dev_priv->ips.min_delay)
1105 new_delay = dev_priv->ips.min_delay;
1106 }
1107
1108 if (ironlake_set_drps(dev_priv, new_delay))
1109 dev_priv->ips.cur_delay = new_delay;
1110
1111 spin_unlock(&mchdev_lock);
1112
1113 return;
1114}
1115
1116static void vlv_c0_read(struct drm_i915_private *dev_priv,
1117 struct intel_rps_ei *ei)
1118{
1119 ei->ktime = ktime_get_raw();
1120 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1121 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1122}
1123
1124void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1125{
1126 memset(&dev_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei));
1127}
1128
1129static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1130{
1131 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1132 const struct intel_rps_ei *prev = &rps->ei;
1133 struct intel_rps_ei now;
1134 u32 events = 0;
1135
1136 if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
1137 return 0;
1138
1139 vlv_c0_read(dev_priv, &now);
1140
1141 if (prev->ktime) {
1142 u64 time, c0;
1143 u32 render, media;
1144
1145 time = ktime_us_delta(now.ktime, prev->ktime);
1146
1147 time *= dev_priv->czclk_freq;
1148
1149 /* Workload can be split between render + media,
1150 * e.g. SwapBuffers being blitted in X after being rendered in
1151 * mesa. To account for this we need to combine both engines
1152 * into our activity counter.
1153 */
1154 render = now.render_c0 - prev->render_c0;
1155 media = now.media_c0 - prev->media_c0;
1156 c0 = max(render, media);
1157 c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */
1158
1159 if (c0 > time * rps->power.up_threshold)
1160 events = GEN6_PM_RP_UP_THRESHOLD;
1161 else if (c0 < time * rps->power.down_threshold)
1162 events = GEN6_PM_RP_DOWN_THRESHOLD;
1163 }
1164
1165 rps->ei = now;
1166 return events;
1167}
1168
1169static void gen6_pm_rps_work(struct work_struct *work)
1170{
1171 struct drm_i915_private *dev_priv =
1172 container_of(work, struct drm_i915_private, gt_pm.rps.work);
1173 struct intel_gt *gt = &dev_priv->gt;
1174 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1175 bool client_boost = false;
1176 int new_delay, adj, min, max;
1177 u32 pm_iir = 0;
1178
1179 spin_lock_irq(>->irq_lock);
1180 if (rps->interrupts_enabled) {
1181 pm_iir = fetch_and_zero(&rps->pm_iir);
1182 client_boost = atomic_read(&rps->num_waiters);
1183 }
1184 spin_unlock_irq(>->irq_lock);
1185
1186 /* Make sure we didn't queue anything we're not going to process. */
1187 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1188 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1189 goto out;
1190
1191 mutex_lock(&rps->lock);
1192
1193 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1194
1195 adj = rps->last_adj;
1196 new_delay = rps->cur_freq;
1197 min = rps->min_freq_softlimit;
1198 max = rps->max_freq_softlimit;
1199 if (client_boost)
1200 max = rps->max_freq;
1201 if (client_boost && new_delay < rps->boost_freq) {
1202 new_delay = rps->boost_freq;
1203 adj = 0;
1204 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1205 if (adj > 0)
1206 adj *= 2;
1207 else /* CHV needs even encode values */
1208 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1209
1210 if (new_delay >= rps->max_freq_softlimit)
1211 adj = 0;
1212 } else if (client_boost) {
1213 adj = 0;
1214 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1215 if (rps->cur_freq > rps->efficient_freq)
1216 new_delay = rps->efficient_freq;
1217 else if (rps->cur_freq > rps->min_freq_softlimit)
1218 new_delay = rps->min_freq_softlimit;
1219 adj = 0;
1220 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1221 if (adj < 0)
1222 adj *= 2;
1223 else /* CHV needs even encode values */
1224 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1225
1226 if (new_delay <= rps->min_freq_softlimit)
1227 adj = 0;
1228 } else { /* unknown event */
1229 adj = 0;
1230 }
1231
1232 rps->last_adj = adj;
1233
1234 /*
1235 * Limit deboosting and boosting to keep ourselves at the extremes
1236 * when in the respective power modes (i.e. slowly decrease frequencies
1237 * while in the HIGH_POWER zone and slowly increase frequencies while
1238 * in the LOW_POWER zone). On idle, we will hit the timeout and drop
1239 * to the next level quickly, and conversely if busy we expect to
1240 * hit a waitboost and rapidly switch into max power.
1241 */
1242 if ((adj < 0 && rps->power.mode == HIGH_POWER) ||
1243 (adj > 0 && rps->power.mode == LOW_POWER))
1244 rps->last_adj = 0;
1245
1246 /* sysfs frequency interfaces may have snuck in while servicing the
1247 * interrupt
1248 */
1249 new_delay += adj;
1250 new_delay = clamp_t(int, new_delay, min, max);
1251
1252 if (intel_set_rps(dev_priv, new_delay)) {
1253 DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
1254 rps->last_adj = 0;
1255 }
1256
1257 mutex_unlock(&rps->lock);
1258
1259out:
1260 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1261 spin_lock_irq(>->irq_lock);
1262 if (rps->interrupts_enabled)
1263 gen6_gt_pm_unmask_irq(gt, dev_priv->pm_rps_events);
1264 spin_unlock_irq(>->irq_lock);
1265}
1266
1267
1268/**
1269 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1270 * occurred.
1271 * @work: workqueue struct
1272 *
1273 * Doesn't actually do anything except notify userspace. As a consequence of
1274 * this event, userspace should try to remap the bad rows since statistically
1275 * it is likely the same row is more likely to go bad again.
1276 */
1277static void ivybridge_parity_work(struct work_struct *work)
1278{
1279 struct drm_i915_private *dev_priv =
1280 container_of(work, typeof(*dev_priv), l3_parity.error_work);
1281 struct intel_gt *gt = &dev_priv->gt;
1282 u32 error_status, row, bank, subbank;
1283 char *parity_event[6];
1284 u32 misccpctl;
1285 u8 slice = 0;
1286
1287 /* We must turn off DOP level clock gating to access the L3 registers.
1288 * In order to prevent a get/put style interface, acquire struct mutex
1289 * any time we access those registers.
1290 */
1291 mutex_lock(&dev_priv->drm.struct_mutex);
1292
1293 /* If we've screwed up tracking, just let the interrupt fire again */
1294 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1295 goto out;
1296
1297 misccpctl = I915_READ(GEN7_MISCCPCTL);
1298 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1299 POSTING_READ(GEN7_MISCCPCTL);
1300
1301 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1302 i915_reg_t reg;
1303
1304 slice--;
1305 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1306 break;
1307
1308 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1309
1310 reg = GEN7_L3CDERRST1(slice);
1311
1312 error_status = I915_READ(reg);
1313 row = GEN7_PARITY_ERROR_ROW(error_status);
1314 bank = GEN7_PARITY_ERROR_BANK(error_status);
1315 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1316
1317 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1318 POSTING_READ(reg);
1319
1320 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1321 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1322 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1323 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1324 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1325 parity_event[5] = NULL;
1326
1327 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1328 KOBJ_CHANGE, parity_event);
1329
1330 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1331 slice, row, bank, subbank);
1332
1333 kfree(parity_event[4]);
1334 kfree(parity_event[3]);
1335 kfree(parity_event[2]);
1336 kfree(parity_event[1]);
1337 }
1338
1339 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1340
1341out:
1342 WARN_ON(dev_priv->l3_parity.which_slice);
1343 spin_lock_irq(>->irq_lock);
1344 gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));
1345 spin_unlock_irq(>->irq_lock);
1346
1347 mutex_unlock(&dev_priv->drm.struct_mutex);
1348}
1349
1350static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1351{
1352 switch (pin) {
1353 case HPD_PORT_C:
1354 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
1355 case HPD_PORT_D:
1356 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
1357 case HPD_PORT_E:
1358 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
1359 case HPD_PORT_F:
1360 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
1361 default:
1362 return false;
1363 }
1364}
1365
1366static bool gen12_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1367{
1368 switch (pin) {
1369 case HPD_PORT_D:
1370 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
1371 case HPD_PORT_E:
1372 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
1373 case HPD_PORT_F:
1374 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
1375 case HPD_PORT_G:
1376 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
1377 case HPD_PORT_H:
1378 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
1379 case HPD_PORT_I:
1380 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
1381 default:
1382 return false;
1383 }
1384}
1385
1386static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1387{
1388 switch (pin) {
1389 case HPD_PORT_A:
1390 return val & PORTA_HOTPLUG_LONG_DETECT;
1391 case HPD_PORT_B:
1392 return val & PORTB_HOTPLUG_LONG_DETECT;
1393 case HPD_PORT_C:
1394 return val & PORTC_HOTPLUG_LONG_DETECT;
1395 default:
1396 return false;
1397 }
1398}
1399
1400static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1401{
1402 switch (pin) {
1403 case HPD_PORT_A:
1404 return val & ICP_DDIA_HPD_LONG_DETECT;
1405 case HPD_PORT_B:
1406 return val & ICP_DDIB_HPD_LONG_DETECT;
1407 case HPD_PORT_C:
1408 return val & TGP_DDIC_HPD_LONG_DETECT;
1409 default:
1410 return false;
1411 }
1412}
1413
1414static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1415{
1416 switch (pin) {
1417 case HPD_PORT_C:
1418 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
1419 case HPD_PORT_D:
1420 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
1421 case HPD_PORT_E:
1422 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
1423 case HPD_PORT_F:
1424 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
1425 default:
1426 return false;
1427 }
1428}
1429
1430static bool tgp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1431{
1432 switch (pin) {
1433 case HPD_PORT_A:
1434 return val & ICP_DDIA_HPD_LONG_DETECT;
1435 case HPD_PORT_B:
1436 return val & ICP_DDIB_HPD_LONG_DETECT;
1437 case HPD_PORT_C:
1438 return val & TGP_DDIC_HPD_LONG_DETECT;
1439 default:
1440 return false;
1441 }
1442}
1443
1444static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1445{
1446 switch (pin) {
1447 case HPD_PORT_D:
1448 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
1449 case HPD_PORT_E:
1450 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
1451 case HPD_PORT_F:
1452 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
1453 case HPD_PORT_G:
1454 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
1455 case HPD_PORT_H:
1456 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
1457 case HPD_PORT_I:
1458 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
1459 default:
1460 return false;
1461 }
1462}
1463
1464static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
1465{
1466 switch (pin) {
1467 case HPD_PORT_E:
1468 return val & PORTE_HOTPLUG_LONG_DETECT;
1469 default:
1470 return false;
1471 }
1472}
1473
1474static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1475{
1476 switch (pin) {
1477 case HPD_PORT_A:
1478 return val & PORTA_HOTPLUG_LONG_DETECT;
1479 case HPD_PORT_B:
1480 return val & PORTB_HOTPLUG_LONG_DETECT;
1481 case HPD_PORT_C:
1482 return val & PORTC_HOTPLUG_LONG_DETECT;
1483 case HPD_PORT_D:
1484 return val & PORTD_HOTPLUG_LONG_DETECT;
1485 default:
1486 return false;
1487 }
1488}
1489
1490static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1491{
1492 switch (pin) {
1493 case HPD_PORT_A:
1494 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1495 default:
1496 return false;
1497 }
1498}
1499
1500static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1501{
1502 switch (pin) {
1503 case HPD_PORT_B:
1504 return val & PORTB_HOTPLUG_LONG_DETECT;
1505 case HPD_PORT_C:
1506 return val & PORTC_HOTPLUG_LONG_DETECT;
1507 case HPD_PORT_D:
1508 return val & PORTD_HOTPLUG_LONG_DETECT;
1509 default:
1510 return false;
1511 }
1512}
1513
1514static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1515{
1516 switch (pin) {
1517 case HPD_PORT_B:
1518 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1519 case HPD_PORT_C:
1520 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1521 case HPD_PORT_D:
1522 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1523 default:
1524 return false;
1525 }
1526}
1527
1528/*
1529 * Get a bit mask of pins that have triggered, and which ones may be long.
1530 * This can be called multiple times with the same masks to accumulate
1531 * hotplug detection results from several registers.
1532 *
1533 * Note that the caller is expected to zero out the masks initially.
1534 */
1535static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
1536 u32 *pin_mask, u32 *long_mask,
1537 u32 hotplug_trigger, u32 dig_hotplug_reg,
1538 const u32 hpd[HPD_NUM_PINS],
1539 bool long_pulse_detect(enum hpd_pin pin, u32 val))
1540{
1541 enum hpd_pin pin;
1542
1543 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
1544
1545 for_each_hpd_pin(pin) {
1546 if ((hpd[pin] & hotplug_trigger) == 0)
1547 continue;
1548
1549 *pin_mask |= BIT(pin);
1550
1551 if (long_pulse_detect(pin, dig_hotplug_reg))
1552 *long_mask |= BIT(pin);
1553 }
1554
1555 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
1556 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
1557
1558}
1559
1560static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1561{
1562 wake_up_all(&dev_priv->gmbus_wait_queue);
1563}
1564
1565static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1566{
1567 wake_up_all(&dev_priv->gmbus_wait_queue);
1568}
1569
1570#if defined(CONFIG_DEBUG_FS)
1571static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1572 enum pipe pipe,
1573 u32 crc0, u32 crc1,
1574 u32 crc2, u32 crc3,
1575 u32 crc4)
1576{
1577 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1578 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1579 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
1580
1581 trace_intel_pipe_crc(crtc, crcs);
1582
1583 spin_lock(&pipe_crc->lock);
1584 /*
1585 * For some not yet identified reason, the first CRC is
1586 * bonkers. So let's just wait for the next vblank and read
1587 * out the buggy result.
1588 *
1589 * On GEN8+ sometimes the second CRC is bonkers as well, so
1590 * don't trust that one either.
1591 */
1592 if (pipe_crc->skipped <= 0 ||
1593 (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
1594 pipe_crc->skipped++;
1595 spin_unlock(&pipe_crc->lock);
1596 return;
1597 }
1598 spin_unlock(&pipe_crc->lock);
1599
1600 drm_crtc_add_crc_entry(&crtc->base, true,
1601 drm_crtc_accurate_vblank_count(&crtc->base),
1602 crcs);
1603}
1604#else
1605static inline void
1606display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1607 enum pipe pipe,
1608 u32 crc0, u32 crc1,
1609 u32 crc2, u32 crc3,
1610 u32 crc4) {}
1611#endif
1612
1613
1614static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1615 enum pipe pipe)
1616{
1617 display_pipe_crc_irq_handler(dev_priv, pipe,
1618 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1619 0, 0, 0, 0);
1620}
1621
1622static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1623 enum pipe pipe)
1624{
1625 display_pipe_crc_irq_handler(dev_priv, pipe,
1626 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1627 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1628 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1629 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1630 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1631}
1632
1633static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1634 enum pipe pipe)
1635{
1636 u32 res1, res2;
1637
1638 if (INTEL_GEN(dev_priv) >= 3)
1639 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1640 else
1641 res1 = 0;
1642
1643 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1644 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1645 else
1646 res2 = 0;
1647
1648 display_pipe_crc_irq_handler(dev_priv, pipe,
1649 I915_READ(PIPE_CRC_RES_RED(pipe)),
1650 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1651 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1652 res1, res2);
1653}
1654
1655/* The RPS events need forcewake, so we add them to a work queue and mask their
1656 * IMR bits until the work is done. Other interrupts can be processed without
1657 * the work queue. */
1658void gen11_rps_irq_handler(struct intel_gt *gt, u32 pm_iir)
1659{
1660 struct drm_i915_private *i915 = gt->i915;
1661 struct intel_rps *rps = &i915->gt_pm.rps;
1662 const u32 events = i915->pm_rps_events & pm_iir;
1663
1664 lockdep_assert_held(>->irq_lock);
1665
1666 if (unlikely(!events))
1667 return;
1668
1669 gen6_gt_pm_mask_irq(gt, events);
1670
1671 if (!rps->interrupts_enabled)
1672 return;
1673
1674 rps->pm_iir |= events;
1675 schedule_work(&rps->work);
1676}
1677
1678void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1679{
1680 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1681 struct intel_gt *gt = &dev_priv->gt;
1682
1683 if (pm_iir & dev_priv->pm_rps_events) {
1684 spin_lock(>->irq_lock);
1685 gen6_gt_pm_mask_irq(gt, pm_iir & dev_priv->pm_rps_events);
1686 if (rps->interrupts_enabled) {
1687 rps->pm_iir |= pm_iir & dev_priv->pm_rps_events;
1688 schedule_work(&rps->work);
1689 }
1690 spin_unlock(>->irq_lock);
1691 }
1692
1693 if (INTEL_GEN(dev_priv) >= 8)
1694 return;
1695
1696 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1697 intel_engine_breadcrumbs_irq(dev_priv->engine[VECS0]);
1698
1699 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1700 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1701}
1702
1703static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1704{
1705 enum pipe pipe;
1706
1707 for_each_pipe(dev_priv, pipe) {
1708 I915_WRITE(PIPESTAT(pipe),
1709 PIPESTAT_INT_STATUS_MASK |
1710 PIPE_FIFO_UNDERRUN_STATUS);
1711
1712 dev_priv->pipestat_irq_mask[pipe] = 0;
1713 }
1714}
1715
1716static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1717 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1718{
1719 int pipe;
1720
1721 spin_lock(&dev_priv->irq_lock);
1722
1723 if (!dev_priv->display_irqs_enabled) {
1724 spin_unlock(&dev_priv->irq_lock);
1725 return;
1726 }
1727
1728 for_each_pipe(dev_priv, pipe) {
1729 i915_reg_t reg;
1730 u32 status_mask, enable_mask, iir_bit = 0;
1731
1732 /*
1733 * PIPESTAT bits get signalled even when the interrupt is
1734 * disabled with the mask bits, and some of the status bits do
1735 * not generate interrupts at all (like the underrun bit). Hence
1736 * we need to be careful that we only handle what we want to
1737 * handle.
1738 */
1739
1740 /* fifo underruns are filterered in the underrun handler. */
1741 status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1742
1743 switch (pipe) {
1744 case PIPE_A:
1745 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1746 break;
1747 case PIPE_B:
1748 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1749 break;
1750 case PIPE_C:
1751 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1752 break;
1753 }
1754 if (iir & iir_bit)
1755 status_mask |= dev_priv->pipestat_irq_mask[pipe];
1756
1757 if (!status_mask)
1758 continue;
1759
1760 reg = PIPESTAT(pipe);
1761 pipe_stats[pipe] = I915_READ(reg) & status_mask;
1762 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
1763
1764 /*
1765 * Clear the PIPE*STAT regs before the IIR
1766 *
1767 * Toggle the enable bits to make sure we get an
1768 * edge in the ISR pipe event bit if we don't clear
1769 * all the enabled status bits. Otherwise the edge
1770 * triggered IIR on i965/g4x wouldn't notice that
1771 * an interrupt is still pending.
1772 */
1773 if (pipe_stats[pipe]) {
1774 I915_WRITE(reg, pipe_stats[pipe]);
1775 I915_WRITE(reg, enable_mask);
1776 }
1777 }
1778 spin_unlock(&dev_priv->irq_lock);
1779}
1780
1781static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1782 u16 iir, u32 pipe_stats[I915_MAX_PIPES])
1783{
1784 enum pipe pipe;
1785
1786 for_each_pipe(dev_priv, pipe) {
1787 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1788 drm_handle_vblank(&dev_priv->drm, pipe);
1789
1790 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1791 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1792
1793 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1794 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1795 }
1796}
1797
1798static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1799 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1800{
1801 bool blc_event = false;
1802 enum pipe pipe;
1803
1804 for_each_pipe(dev_priv, pipe) {
1805 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1806 drm_handle_vblank(&dev_priv->drm, pipe);
1807
1808 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1809 blc_event = true;
1810
1811 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1812 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1813
1814 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1815 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1816 }
1817
1818 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1819 intel_opregion_asle_intr(dev_priv);
1820}
1821
1822static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1823 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1824{
1825 bool blc_event = false;
1826 enum pipe pipe;
1827
1828 for_each_pipe(dev_priv, pipe) {
1829 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1830 drm_handle_vblank(&dev_priv->drm, pipe);
1831
1832 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1833 blc_event = true;
1834
1835 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1836 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1837
1838 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1839 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1840 }
1841
1842 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1843 intel_opregion_asle_intr(dev_priv);
1844
1845 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1846 gmbus_irq_handler(dev_priv);
1847}
1848
1849static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1850 u32 pipe_stats[I915_MAX_PIPES])
1851{
1852 enum pipe pipe;
1853
1854 for_each_pipe(dev_priv, pipe) {
1855 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1856 drm_handle_vblank(&dev_priv->drm, pipe);
1857
1858 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1859 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1860
1861 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1862 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1863 }
1864
1865 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1866 gmbus_irq_handler(dev_priv);
1867}
1868
1869static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1870{
1871 u32 hotplug_status = 0, hotplug_status_mask;
1872 int i;
1873
1874 if (IS_G4X(dev_priv) ||
1875 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1876 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
1877 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
1878 else
1879 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
1880
1881 /*
1882 * We absolutely have to clear all the pending interrupt
1883 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
1884 * interrupt bit won't have an edge, and the i965/g4x
1885 * edge triggered IIR will not notice that an interrupt
1886 * is still pending. We can't use PORT_HOTPLUG_EN to
1887 * guarantee the edge as the act of toggling the enable
1888 * bits can itself generate a new hotplug interrupt :(
1889 */
1890 for (i = 0; i < 10; i++) {
1891 u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
1892
1893 if (tmp == 0)
1894 return hotplug_status;
1895
1896 hotplug_status |= tmp;
1897 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1898 }
1899
1900 WARN_ONCE(1,
1901 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
1902 I915_READ(PORT_HOTPLUG_STAT));
1903
1904 return hotplug_status;
1905}
1906
1907static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1908 u32 hotplug_status)
1909{
1910 u32 pin_mask = 0, long_mask = 0;
1911
1912 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1913 IS_CHERRYVIEW(dev_priv)) {
1914 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1915
1916 if (hotplug_trigger) {
1917 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1918 hotplug_trigger, hotplug_trigger,
1919 hpd_status_g4x,
1920 i9xx_port_hotplug_long_detect);
1921
1922 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1923 }
1924
1925 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1926 dp_aux_irq_handler(dev_priv);
1927 } else {
1928 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1929
1930 if (hotplug_trigger) {
1931 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1932 hotplug_trigger, hotplug_trigger,
1933 hpd_status_i915,
1934 i9xx_port_hotplug_long_detect);
1935 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1936 }
1937 }
1938}
1939
1940static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1941{
1942 struct drm_i915_private *dev_priv = arg;
1943 irqreturn_t ret = IRQ_NONE;
1944
1945 if (!intel_irqs_enabled(dev_priv))
1946 return IRQ_NONE;
1947
1948 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1949 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1950
1951 do {
1952 u32 iir, gt_iir, pm_iir;
1953 u32 pipe_stats[I915_MAX_PIPES] = {};
1954 u32 hotplug_status = 0;
1955 u32 ier = 0;
1956
1957 gt_iir = I915_READ(GTIIR);
1958 pm_iir = I915_READ(GEN6_PMIIR);
1959 iir = I915_READ(VLV_IIR);
1960
1961 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1962 break;
1963
1964 ret = IRQ_HANDLED;
1965
1966 /*
1967 * Theory on interrupt generation, based on empirical evidence:
1968 *
1969 * x = ((VLV_IIR & VLV_IER) ||
1970 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1971 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1972 *
1973 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1974 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1975 * guarantee the CPU interrupt will be raised again even if we
1976 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1977 * bits this time around.
1978 */
1979 I915_WRITE(VLV_MASTER_IER, 0);
1980 ier = I915_READ(VLV_IER);
1981 I915_WRITE(VLV_IER, 0);
1982
1983 if (gt_iir)
1984 I915_WRITE(GTIIR, gt_iir);
1985 if (pm_iir)
1986 I915_WRITE(GEN6_PMIIR, pm_iir);
1987
1988 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1989 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1990
1991 /* Call regardless, as some status bits might not be
1992 * signalled in iir */
1993 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1994
1995 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1996 I915_LPE_PIPE_B_INTERRUPT))
1997 intel_lpe_audio_irq_handler(dev_priv);
1998
1999 /*
2000 * VLV_IIR is single buffered, and reflects the level
2001 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2002 */
2003 if (iir)
2004 I915_WRITE(VLV_IIR, iir);
2005
2006 I915_WRITE(VLV_IER, ier);
2007 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2008
2009 if (gt_iir)
2010 gen6_gt_irq_handler(&dev_priv->gt, gt_iir);
2011 if (pm_iir)
2012 gen6_rps_irq_handler(dev_priv, pm_iir);
2013
2014 if (hotplug_status)
2015 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2016
2017 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2018 } while (0);
2019
2020 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2021
2022 return ret;
2023}
2024
2025static irqreturn_t cherryview_irq_handler(int irq, void *arg)
2026{
2027 struct drm_i915_private *dev_priv = arg;
2028 irqreturn_t ret = IRQ_NONE;
2029
2030 if (!intel_irqs_enabled(dev_priv))
2031 return IRQ_NONE;
2032
2033 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2034 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2035
2036 do {
2037 u32 master_ctl, iir;
2038 u32 pipe_stats[I915_MAX_PIPES] = {};
2039 u32 hotplug_status = 0;
2040 u32 gt_iir[4];
2041 u32 ier = 0;
2042
2043 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
2044 iir = I915_READ(VLV_IIR);
2045
2046 if (master_ctl == 0 && iir == 0)
2047 break;
2048
2049 ret = IRQ_HANDLED;
2050
2051 /*
2052 * Theory on interrupt generation, based on empirical evidence:
2053 *
2054 * x = ((VLV_IIR & VLV_IER) ||
2055 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
2056 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
2057 *
2058 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
2059 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
2060 * guarantee the CPU interrupt will be raised again even if we
2061 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
2062 * bits this time around.
2063 */
2064 I915_WRITE(GEN8_MASTER_IRQ, 0);
2065 ier = I915_READ(VLV_IER);
2066 I915_WRITE(VLV_IER, 0);
2067
2068 gen8_gt_irq_ack(&dev_priv->gt, master_ctl, gt_iir);
2069
2070 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2071 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
2072
2073 /* Call regardless, as some status bits might not be
2074 * signalled in iir */
2075 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
2076
2077 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
2078 I915_LPE_PIPE_B_INTERRUPT |
2079 I915_LPE_PIPE_C_INTERRUPT))
2080 intel_lpe_audio_irq_handler(dev_priv);
2081
2082 /*
2083 * VLV_IIR is single buffered, and reflects the level
2084 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2085 */
2086 if (iir)
2087 I915_WRITE(VLV_IIR, iir);
2088
2089 I915_WRITE(VLV_IER, ier);
2090 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2091
2092 gen8_gt_irq_handler(&dev_priv->gt, master_ctl, gt_iir);
2093
2094 if (hotplug_status)
2095 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2096
2097 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2098 } while (0);
2099
2100 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2101
2102 return ret;
2103}
2104
2105static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2106 u32 hotplug_trigger,
2107 const u32 hpd[HPD_NUM_PINS])
2108{
2109 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2110
2111 /*
2112 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
2113 * unless we touch the hotplug register, even if hotplug_trigger is
2114 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
2115 * errors.
2116 */
2117 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2118 if (!hotplug_trigger) {
2119 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
2120 PORTD_HOTPLUG_STATUS_MASK |
2121 PORTC_HOTPLUG_STATUS_MASK |
2122 PORTB_HOTPLUG_STATUS_MASK;
2123 dig_hotplug_reg &= ~mask;
2124 }
2125
2126 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2127 if (!hotplug_trigger)
2128 return;
2129
2130 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2131 dig_hotplug_reg, hpd,
2132 pch_port_hotplug_long_detect);
2133
2134 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2135}
2136
2137static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2138{
2139 int pipe;
2140 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2141
2142 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
2143
2144 if (pch_iir & SDE_AUDIO_POWER_MASK) {
2145 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2146 SDE_AUDIO_POWER_SHIFT);
2147 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2148 port_name(port));
2149 }
2150
2151 if (pch_iir & SDE_AUX_MASK)
2152 dp_aux_irq_handler(dev_priv);
2153
2154 if (pch_iir & SDE_GMBUS)
2155 gmbus_irq_handler(dev_priv);
2156
2157 if (pch_iir & SDE_AUDIO_HDCP_MASK)
2158 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2159
2160 if (pch_iir & SDE_AUDIO_TRANS_MASK)
2161 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2162
2163 if (pch_iir & SDE_POISON)
2164 DRM_ERROR("PCH poison interrupt\n");
2165
2166 if (pch_iir & SDE_FDI_MASK)
2167 for_each_pipe(dev_priv, pipe)
2168 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2169 pipe_name(pipe),
2170 I915_READ(FDI_RX_IIR(pipe)));
2171
2172 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2173 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2174
2175 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2176 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2177
2178 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2179 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
2180
2181 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2182 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
2183}
2184
2185static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
2186{
2187 u32 err_int = I915_READ(GEN7_ERR_INT);
2188 enum pipe pipe;
2189
2190 if (err_int & ERR_INT_POISON)
2191 DRM_ERROR("Poison interrupt\n");
2192
2193 for_each_pipe(dev_priv, pipe) {
2194 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2195 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2196
2197 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2198 if (IS_IVYBRIDGE(dev_priv))
2199 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2200 else
2201 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2202 }
2203 }
2204
2205 I915_WRITE(GEN7_ERR_INT, err_int);
2206}
2207
2208static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2209{
2210 u32 serr_int = I915_READ(SERR_INT);
2211 enum pipe pipe;
2212
2213 if (serr_int & SERR_INT_POISON)
2214 DRM_ERROR("PCH poison interrupt\n");
2215
2216 for_each_pipe(dev_priv, pipe)
2217 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
2218 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
2219
2220 I915_WRITE(SERR_INT, serr_int);
2221}
2222
2223static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2224{
2225 int pipe;
2226 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2227
2228 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2229
2230 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2231 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2232 SDE_AUDIO_POWER_SHIFT_CPT);
2233 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2234 port_name(port));
2235 }
2236
2237 if (pch_iir & SDE_AUX_MASK_CPT)
2238 dp_aux_irq_handler(dev_priv);
2239
2240 if (pch_iir & SDE_GMBUS_CPT)
2241 gmbus_irq_handler(dev_priv);
2242
2243 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2244 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2245
2246 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2247 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2248
2249 if (pch_iir & SDE_FDI_MASK_CPT)
2250 for_each_pipe(dev_priv, pipe)
2251 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2252 pipe_name(pipe),
2253 I915_READ(FDI_RX_IIR(pipe)));
2254
2255 if (pch_iir & SDE_ERROR_CPT)
2256 cpt_serr_int_handler(dev_priv);
2257}
2258
2259static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir,
2260 const u32 *pins)
2261{
2262 u32 ddi_hotplug_trigger;
2263 u32 tc_hotplug_trigger;
2264 u32 pin_mask = 0, long_mask = 0;
2265
2266 if (HAS_PCH_MCC(dev_priv)) {
2267 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
2268 tc_hotplug_trigger = 0;
2269 } else {
2270 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
2271 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
2272 }
2273
2274 if (ddi_hotplug_trigger) {
2275 u32 dig_hotplug_reg;
2276
2277 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
2278 I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
2279
2280 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2281 ddi_hotplug_trigger,
2282 dig_hotplug_reg, pins,
2283 icp_ddi_port_hotplug_long_detect);
2284 }
2285
2286 if (tc_hotplug_trigger) {
2287 u32 dig_hotplug_reg;
2288
2289 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
2290 I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
2291
2292 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2293 tc_hotplug_trigger,
2294 dig_hotplug_reg, pins,
2295 icp_tc_port_hotplug_long_detect);
2296 }
2297
2298 if (pin_mask)
2299 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2300
2301 if (pch_iir & SDE_GMBUS_ICP)
2302 gmbus_irq_handler(dev_priv);
2303}
2304
2305static void tgp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2306{
2307 u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
2308 u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
2309 u32 pin_mask = 0, long_mask = 0;
2310
2311 if (ddi_hotplug_trigger) {
2312 u32 dig_hotplug_reg;
2313
2314 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
2315 I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
2316
2317 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2318 ddi_hotplug_trigger,
2319 dig_hotplug_reg, hpd_tgp,
2320 tgp_ddi_port_hotplug_long_detect);
2321 }
2322
2323 if (tc_hotplug_trigger) {
2324 u32 dig_hotplug_reg;
2325
2326 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
2327 I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
2328
2329 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2330 tc_hotplug_trigger,
2331 dig_hotplug_reg, hpd_tgp,
2332 tgp_tc_port_hotplug_long_detect);
2333 }
2334
2335 if (pin_mask)
2336 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2337
2338 if (pch_iir & SDE_GMBUS_ICP)
2339 gmbus_irq_handler(dev_priv);
2340}
2341
2342static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2343{
2344 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2345 ~SDE_PORTE_HOTPLUG_SPT;
2346 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2347 u32 pin_mask = 0, long_mask = 0;
2348
2349 if (hotplug_trigger) {
2350 u32 dig_hotplug_reg;
2351
2352 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2353 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2354
2355 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2356 hotplug_trigger, dig_hotplug_reg, hpd_spt,
2357 spt_port_hotplug_long_detect);
2358 }
2359
2360 if (hotplug2_trigger) {
2361 u32 dig_hotplug_reg;
2362
2363 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2364 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2365
2366 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2367 hotplug2_trigger, dig_hotplug_reg, hpd_spt,
2368 spt_port_hotplug2_long_detect);
2369 }
2370
2371 if (pin_mask)
2372 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2373
2374 if (pch_iir & SDE_GMBUS_CPT)
2375 gmbus_irq_handler(dev_priv);
2376}
2377
2378static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2379 u32 hotplug_trigger,
2380 const u32 hpd[HPD_NUM_PINS])
2381{
2382 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2383
2384 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2385 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2386
2387 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2388 dig_hotplug_reg, hpd,
2389 ilk_port_hotplug_long_detect);
2390
2391 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2392}
2393
2394static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2395 u32 de_iir)
2396{
2397 enum pipe pipe;
2398 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2399
2400 if (hotplug_trigger)
2401 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2402
2403 if (de_iir & DE_AUX_CHANNEL_A)
2404 dp_aux_irq_handler(dev_priv);
2405
2406 if (de_iir & DE_GSE)
2407 intel_opregion_asle_intr(dev_priv);
2408
2409 if (de_iir & DE_POISON)
2410 DRM_ERROR("Poison interrupt\n");
2411
2412 for_each_pipe(dev_priv, pipe) {
2413 if (de_iir & DE_PIPE_VBLANK(pipe))
2414 drm_handle_vblank(&dev_priv->drm, pipe);
2415
2416 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2417 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2418
2419 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2420 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2421 }
2422
2423 /* check event from PCH */
2424 if (de_iir & DE_PCH_EVENT) {
2425 u32 pch_iir = I915_READ(SDEIIR);
2426
2427 if (HAS_PCH_CPT(dev_priv))
2428 cpt_irq_handler(dev_priv, pch_iir);
2429 else
2430 ibx_irq_handler(dev_priv, pch_iir);
2431
2432 /* should clear PCH hotplug event before clear CPU irq */
2433 I915_WRITE(SDEIIR, pch_iir);
2434 }
2435
2436 if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
2437 ironlake_rps_change_irq_handler(dev_priv);
2438}
2439
2440static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2441 u32 de_iir)
2442{
2443 enum pipe pipe;
2444 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2445
2446 if (hotplug_trigger)
2447 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2448
2449 if (de_iir & DE_ERR_INT_IVB)
2450 ivb_err_int_handler(dev_priv);
2451
2452 if (de_iir & DE_EDP_PSR_INT_HSW) {
2453 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2454
2455 intel_psr_irq_handler(dev_priv, psr_iir);
2456 I915_WRITE(EDP_PSR_IIR, psr_iir);
2457 }
2458
2459 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2460 dp_aux_irq_handler(dev_priv);
2461
2462 if (de_iir & DE_GSE_IVB)
2463 intel_opregion_asle_intr(dev_priv);
2464
2465 for_each_pipe(dev_priv, pipe) {
2466 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2467 drm_handle_vblank(&dev_priv->drm, pipe);
2468 }
2469
2470 /* check event from PCH */
2471 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2472 u32 pch_iir = I915_READ(SDEIIR);
2473
2474 cpt_irq_handler(dev_priv, pch_iir);
2475
2476 /* clear PCH hotplug event before clear CPU irq */
2477 I915_WRITE(SDEIIR, pch_iir);
2478 }
2479}
2480
2481/*
2482 * To handle irqs with the minimum potential races with fresh interrupts, we:
2483 * 1 - Disable Master Interrupt Control.
2484 * 2 - Find the source(s) of the interrupt.
2485 * 3 - Clear the Interrupt Identity bits (IIR).
2486 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2487 * 5 - Re-enable Master Interrupt Control.
2488 */
2489static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2490{
2491 struct drm_i915_private *dev_priv = arg;
2492 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2493 irqreturn_t ret = IRQ_NONE;
2494
2495 if (!intel_irqs_enabled(dev_priv))
2496 return IRQ_NONE;
2497
2498 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2499 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2500
2501 /* disable master interrupt before clearing iir */
2502 de_ier = I915_READ(DEIER);
2503 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2504
2505 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2506 * interrupts will will be stored on its back queue, and then we'll be
2507 * able to process them after we restore SDEIER (as soon as we restore
2508 * it, we'll get an interrupt if SDEIIR still has something to process
2509 * due to its back queue). */
2510 if (!HAS_PCH_NOP(dev_priv)) {
2511 sde_ier = I915_READ(SDEIER);
2512 I915_WRITE(SDEIER, 0);
2513 }
2514
2515 /* Find, clear, then process each source of interrupt */
2516
2517 gt_iir = I915_READ(GTIIR);
2518 if (gt_iir) {
2519 I915_WRITE(GTIIR, gt_iir);
2520 ret = IRQ_HANDLED;
2521 if (INTEL_GEN(dev_priv) >= 6)
2522 gen6_gt_irq_handler(&dev_priv->gt, gt_iir);
2523 else
2524 gen5_gt_irq_handler(&dev_priv->gt, gt_iir);
2525 }
2526
2527 de_iir = I915_READ(DEIIR);
2528 if (de_iir) {
2529 I915_WRITE(DEIIR, de_iir);
2530 ret = IRQ_HANDLED;
2531 if (INTEL_GEN(dev_priv) >= 7)
2532 ivb_display_irq_handler(dev_priv, de_iir);
2533 else
2534 ilk_display_irq_handler(dev_priv, de_iir);
2535 }
2536
2537 if (INTEL_GEN(dev_priv) >= 6) {
2538 u32 pm_iir = I915_READ(GEN6_PMIIR);
2539 if (pm_iir) {
2540 I915_WRITE(GEN6_PMIIR, pm_iir);
2541 ret = IRQ_HANDLED;
2542 gen6_rps_irq_handler(dev_priv, pm_iir);
2543 }
2544 }
2545
2546 I915_WRITE(DEIER, de_ier);
2547 if (!HAS_PCH_NOP(dev_priv))
2548 I915_WRITE(SDEIER, sde_ier);
2549
2550 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2551 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2552
2553 return ret;
2554}
2555
2556static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2557 u32 hotplug_trigger,
2558 const u32 hpd[HPD_NUM_PINS])
2559{
2560 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2561
2562 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2563 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2564
2565 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2566 dig_hotplug_reg, hpd,
2567 bxt_port_hotplug_long_detect);
2568
2569 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2570}
2571
2572static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2573{
2574 u32 pin_mask = 0, long_mask = 0;
2575 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
2576 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
2577 long_pulse_detect_func long_pulse_detect;
2578 const u32 *hpd;
2579
2580 if (INTEL_GEN(dev_priv) >= 12) {
2581 long_pulse_detect = gen12_port_hotplug_long_detect;
2582 hpd = hpd_gen12;
2583 } else {
2584 long_pulse_detect = gen11_port_hotplug_long_detect;
2585 hpd = hpd_gen11;
2586 }
2587
2588 if (trigger_tc) {
2589 u32 dig_hotplug_reg;
2590
2591 dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
2592 I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
2593
2594 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc,
2595 dig_hotplug_reg, hpd, long_pulse_detect);
2596 }
2597
2598 if (trigger_tbt) {
2599 u32 dig_hotplug_reg;
2600
2601 dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
2602 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
2603
2604 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt,
2605 dig_hotplug_reg, hpd, long_pulse_detect);
2606 }
2607
2608 if (pin_mask)
2609 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2610 else
2611 DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n", iir);
2612}
2613
2614static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
2615{
2616 u32 mask;
2617
2618 if (INTEL_GEN(dev_priv) >= 12)
2619 /* TODO: Add AUX entries for USBC */
2620 return TGL_DE_PORT_AUX_DDIA |
2621 TGL_DE_PORT_AUX_DDIB |
2622 TGL_DE_PORT_AUX_DDIC;
2623
2624 mask = GEN8_AUX_CHANNEL_A;
2625 if (INTEL_GEN(dev_priv) >= 9)
2626 mask |= GEN9_AUX_CHANNEL_B |
2627 GEN9_AUX_CHANNEL_C |
2628 GEN9_AUX_CHANNEL_D;
2629
2630 if (IS_CNL_WITH_PORT_F(dev_priv) || IS_GEN(dev_priv, 11))
2631 mask |= CNL_AUX_CHANNEL_F;
2632
2633 if (IS_GEN(dev_priv, 11))
2634 mask |= ICL_AUX_CHANNEL_E;
2635
2636 return mask;
2637}
2638
2639static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
2640{
2641 if (INTEL_GEN(dev_priv) >= 9)
2642 return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2643 else
2644 return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2645}
2646
2647static void
2648gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2649{
2650 bool found = false;
2651
2652 if (iir & GEN8_DE_MISC_GSE) {
2653 intel_opregion_asle_intr(dev_priv);
2654 found = true;
2655 }
2656
2657 if (iir & GEN8_DE_EDP_PSR) {
2658 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2659
2660 intel_psr_irq_handler(dev_priv, psr_iir);
2661 I915_WRITE(EDP_PSR_IIR, psr_iir);
2662 found = true;
2663 }
2664
2665 if (!found)
2666 DRM_ERROR("Unexpected DE Misc interrupt\n");
2667}
2668
2669static irqreturn_t
2670gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2671{
2672 irqreturn_t ret = IRQ_NONE;
2673 u32 iir;
2674 enum pipe pipe;
2675
2676 if (master_ctl & GEN8_DE_MISC_IRQ) {
2677 iir = I915_READ(GEN8_DE_MISC_IIR);
2678 if (iir) {
2679 I915_WRITE(GEN8_DE_MISC_IIR, iir);
2680 ret = IRQ_HANDLED;
2681 gen8_de_misc_irq_handler(dev_priv, iir);
2682 } else {
2683 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2684 }
2685 }
2686
2687 if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
2688 iir = I915_READ(GEN11_DE_HPD_IIR);
2689 if (iir) {
2690 I915_WRITE(GEN11_DE_HPD_IIR, iir);
2691 ret = IRQ_HANDLED;
2692 gen11_hpd_irq_handler(dev_priv, iir);
2693 } else {
2694 DRM_ERROR("The master control interrupt lied, (DE HPD)!\n");
2695 }
2696 }
2697
2698 if (master_ctl & GEN8_DE_PORT_IRQ) {
2699 iir = I915_READ(GEN8_DE_PORT_IIR);
2700 if (iir) {
2701 u32 tmp_mask;
2702 bool found = false;
2703
2704 I915_WRITE(GEN8_DE_PORT_IIR, iir);
2705 ret = IRQ_HANDLED;
2706
2707 if (iir & gen8_de_port_aux_mask(dev_priv)) {
2708 dp_aux_irq_handler(dev_priv);
2709 found = true;
2710 }
2711
2712 if (IS_GEN9_LP(dev_priv)) {
2713 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2714 if (tmp_mask) {
2715 bxt_hpd_irq_handler(dev_priv, tmp_mask,
2716 hpd_bxt);
2717 found = true;
2718 }
2719 } else if (IS_BROADWELL(dev_priv)) {
2720 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2721 if (tmp_mask) {
2722 ilk_hpd_irq_handler(dev_priv,
2723 tmp_mask, hpd_bdw);
2724 found = true;
2725 }
2726 }
2727
2728 if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2729 gmbus_irq_handler(dev_priv);
2730 found = true;
2731 }
2732
2733 if (!found)
2734 DRM_ERROR("Unexpected DE Port interrupt\n");
2735 }
2736 else
2737 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2738 }
2739
2740 for_each_pipe(dev_priv, pipe) {
2741 u32 fault_errors;
2742
2743 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2744 continue;
2745
2746 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2747 if (!iir) {
2748 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2749 continue;
2750 }
2751
2752 ret = IRQ_HANDLED;
2753 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2754
2755 if (iir & GEN8_PIPE_VBLANK)
2756 drm_handle_vblank(&dev_priv->drm, pipe);
2757
2758 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2759 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2760
2761 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2762 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2763
2764 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
2765 if (fault_errors)
2766 DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2767 pipe_name(pipe),
2768 fault_errors);
2769 }
2770
2771 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2772 master_ctl & GEN8_DE_PCH_IRQ) {
2773 /*
2774 * FIXME(BDW): Assume for now that the new interrupt handling
2775 * scheme also closed the SDE interrupt handling race we've seen
2776 * on older pch-split platforms. But this needs testing.
2777 */
2778 iir = I915_READ(SDEIIR);
2779 if (iir) {
2780 I915_WRITE(SDEIIR, iir);
2781 ret = IRQ_HANDLED;
2782
2783 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
2784 tgp_irq_handler(dev_priv, iir);
2785 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MCC)
2786 icp_irq_handler(dev_priv, iir, hpd_mcc);
2787 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2788 icp_irq_handler(dev_priv, iir, hpd_icp);
2789 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
2790 spt_irq_handler(dev_priv, iir);
2791 else
2792 cpt_irq_handler(dev_priv, iir);
2793 } else {
2794 /*
2795 * Like on previous PCH there seems to be something
2796 * fishy going on with forwarding PCH interrupts.
2797 */
2798 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2799 }
2800 }
2801
2802 return ret;
2803}
2804
2805static inline u32 gen8_master_intr_disable(void __iomem * const regs)
2806{
2807 raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
2808
2809 /*
2810 * Now with master disabled, get a sample of level indications
2811 * for this interrupt. Indications will be cleared on related acks.
2812 * New indications can and will light up during processing,
2813 * and will generate new interrupt after enabling master.
2814 */
2815 return raw_reg_read(regs, GEN8_MASTER_IRQ);
2816}
2817
2818static inline void gen8_master_intr_enable(void __iomem * const regs)
2819{
2820 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2821}
2822
2823static irqreturn_t gen8_irq_handler(int irq, void *arg)
2824{
2825 struct drm_i915_private *dev_priv = arg;
2826 void __iomem * const regs = dev_priv->uncore.regs;
2827 u32 master_ctl;
2828 u32 gt_iir[4];
2829
2830 if (!intel_irqs_enabled(dev_priv))
2831 return IRQ_NONE;
2832
2833 master_ctl = gen8_master_intr_disable(regs);
2834 if (!master_ctl) {
2835 gen8_master_intr_enable(regs);
2836 return IRQ_NONE;
2837 }
2838
2839 /* Find, clear, then process each source of interrupt */
2840 gen8_gt_irq_ack(&dev_priv->gt, master_ctl, gt_iir);
2841
2842 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2843 if (master_ctl & ~GEN8_GT_IRQS) {
2844 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2845 gen8_de_irq_handler(dev_priv, master_ctl);
2846 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2847 }
2848
2849 gen8_master_intr_enable(regs);
2850
2851 gen8_gt_irq_handler(&dev_priv->gt, master_ctl, gt_iir);
2852
2853 return IRQ_HANDLED;
2854}
2855
2856static u32
2857gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
2858{
2859 void __iomem * const regs = gt->uncore->regs;
2860 u32 iir;
2861
2862 if (!(master_ctl & GEN11_GU_MISC_IRQ))
2863 return 0;
2864
2865 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
2866 if (likely(iir))
2867 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
2868
2869 return iir;
2870}
2871
2872static void
2873gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
2874{
2875 if (iir & GEN11_GU_MISC_GSE)
2876 intel_opregion_asle_intr(gt->i915);
2877}
2878
2879static inline u32 gen11_master_intr_disable(void __iomem * const regs)
2880{
2881 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
2882
2883 /*
2884 * Now with master disabled, get a sample of level indications
2885 * for this interrupt. Indications will be cleared on related acks.
2886 * New indications can and will light up during processing,
2887 * and will generate new interrupt after enabling master.
2888 */
2889 return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
2890}
2891
2892static inline void gen11_master_intr_enable(void __iomem * const regs)
2893{
2894 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
2895}
2896
2897static irqreturn_t gen11_irq_handler(int irq, void *arg)
2898{
2899 struct drm_i915_private * const i915 = arg;
2900 void __iomem * const regs = i915->uncore.regs;
2901 struct intel_gt *gt = &i915->gt;
2902 u32 master_ctl;
2903 u32 gu_misc_iir;
2904
2905 if (!intel_irqs_enabled(i915))
2906 return IRQ_NONE;
2907
2908 master_ctl = gen11_master_intr_disable(regs);
2909 if (!master_ctl) {
2910 gen11_master_intr_enable(regs);
2911 return IRQ_NONE;
2912 }
2913
2914 /* Find, clear, then process each source of interrupt. */
2915 gen11_gt_irq_handler(gt, master_ctl);
2916
2917 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2918 if (master_ctl & GEN11_DISPLAY_IRQ) {
2919 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
2920
2921 disable_rpm_wakeref_asserts(&i915->runtime_pm);
2922 /*
2923 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
2924 * for the display related bits.
2925 */
2926 gen8_de_irq_handler(i915, disp_ctl);
2927 enable_rpm_wakeref_asserts(&i915->runtime_pm);
2928 }
2929
2930 gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
2931
2932 gen11_master_intr_enable(regs);
2933
2934 gen11_gu_misc_irq_handler(gt, gu_misc_iir);
2935
2936 return IRQ_HANDLED;
2937}
2938
2939/* Called from drm generic code, passed 'crtc' which
2940 * we use as a pipe index
2941 */
2942int i8xx_enable_vblank(struct drm_crtc *crtc)
2943{
2944 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2945 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2946 unsigned long irqflags;
2947
2948 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2949 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2950 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2951
2952 return 0;
2953}
2954
2955int i945gm_enable_vblank(struct drm_crtc *crtc)
2956{
2957 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2958
2959 if (dev_priv->i945gm_vblank.enabled++ == 0)
2960 schedule_work(&dev_priv->i945gm_vblank.work);
2961
2962 return i8xx_enable_vblank(crtc);
2963}
2964
2965int i965_enable_vblank(struct drm_crtc *crtc)
2966{
2967 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2968 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2969 unsigned long irqflags;
2970
2971 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2972 i915_enable_pipestat(dev_priv, pipe,
2973 PIPE_START_VBLANK_INTERRUPT_STATUS);
2974 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2975
2976 return 0;
2977}
2978
2979int ilk_enable_vblank(struct drm_crtc *crtc)
2980{
2981 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2982 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2983 unsigned long irqflags;
2984 u32 bit = INTEL_GEN(dev_priv) >= 7 ?
2985 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2986
2987 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2988 ilk_enable_display_irq(dev_priv, bit);
2989 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2990
2991 /* Even though there is no DMC, frame counter can get stuck when
2992 * PSR is active as no frames are generated.
2993 */
2994 if (HAS_PSR(dev_priv))
2995 drm_crtc_vblank_restore(crtc);
2996
2997 return 0;
2998}
2999
3000int bdw_enable_vblank(struct drm_crtc *crtc)
3001{
3002 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3003 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3004 unsigned long irqflags;
3005
3006 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3007 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
3008 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3009
3010 /* Even if there is no DMC, frame counter can get stuck when
3011 * PSR is active as no frames are generated, so check only for PSR.
3012 */
3013 if (HAS_PSR(dev_priv))
3014 drm_crtc_vblank_restore(crtc);
3015
3016 return 0;
3017}
3018
3019/* Called from drm generic code, passed 'crtc' which
3020 * we use as a pipe index
3021 */
3022void i8xx_disable_vblank(struct drm_crtc *crtc)
3023{
3024 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3025 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3026 unsigned long irqflags;
3027
3028 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3029 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
3030 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3031}
3032
3033void i945gm_disable_vblank(struct drm_crtc *crtc)
3034{
3035 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3036
3037 i8xx_disable_vblank(crtc);
3038
3039 if (--dev_priv->i945gm_vblank.enabled == 0)
3040 schedule_work(&dev_priv->i945gm_vblank.work);
3041}
3042
3043void i965_disable_vblank(struct drm_crtc *crtc)
3044{
3045 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3046 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3047 unsigned long irqflags;
3048
3049 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3050 i915_disable_pipestat(dev_priv, pipe,
3051 PIPE_START_VBLANK_INTERRUPT_STATUS);
3052 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3053}
3054
3055void ilk_disable_vblank(struct drm_crtc *crtc)
3056{
3057 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3058 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3059 unsigned long irqflags;
3060 u32 bit = INTEL_GEN(dev_priv) >= 7 ?
3061 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
3062
3063 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3064 ilk_disable_display_irq(dev_priv, bit);
3065 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3066}
3067
3068void bdw_disable_vblank(struct drm_crtc *crtc)
3069{
3070 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3071 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3072 unsigned long irqflags;
3073
3074 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3075 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
3076 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3077}
3078
3079static void i945gm_vblank_work_func(struct work_struct *work)
3080{
3081 struct drm_i915_private *dev_priv =
3082 container_of(work, struct drm_i915_private, i945gm_vblank.work);
3083
3084 /*
3085 * Vblank interrupts fail to wake up the device from C3,
3086 * hence we want to prevent C3 usage while vblank interrupts
3087 * are enabled.
3088 */
3089 pm_qos_update_request(&dev_priv->i945gm_vblank.pm_qos,
3090 READ_ONCE(dev_priv->i945gm_vblank.enabled) ?
3091 dev_priv->i945gm_vblank.c3_disable_latency :
3092 PM_QOS_DEFAULT_VALUE);
3093}
3094
3095static int cstate_disable_latency(const char *name)
3096{
3097 const struct cpuidle_driver *drv;
3098 int i;
3099
3100 drv = cpuidle_get_driver();
3101 if (!drv)
3102 return 0;
3103
3104 for (i = 0; i < drv->state_count; i++) {
3105 const struct cpuidle_state *state = &drv->states[i];
3106
3107 if (!strcmp(state->name, name))
3108 return state->exit_latency ?
3109 state->exit_latency - 1 : 0;
3110 }
3111
3112 return 0;
3113}
3114
3115static void i945gm_vblank_work_init(struct drm_i915_private *dev_priv)
3116{
3117 INIT_WORK(&dev_priv->i945gm_vblank.work,
3118 i945gm_vblank_work_func);
3119
3120 dev_priv->i945gm_vblank.c3_disable_latency =
3121 cstate_disable_latency("C3");
3122 pm_qos_add_request(&dev_priv->i945gm_vblank.pm_qos,
3123 PM_QOS_CPU_DMA_LATENCY,
3124 PM_QOS_DEFAULT_VALUE);
3125}
3126
3127static void i945gm_vblank_work_fini(struct drm_i915_private *dev_priv)
3128{
3129 cancel_work_sync(&dev_priv->i945gm_vblank.work);
3130 pm_qos_remove_request(&dev_priv->i945gm_vblank.pm_qos);
3131}
3132
3133static void ibx_irq_reset(struct drm_i915_private *dev_priv)
3134{
3135 struct intel_uncore *uncore = &dev_priv->uncore;
3136
3137 if (HAS_PCH_NOP(dev_priv))
3138 return;
3139
3140 GEN3_IRQ_RESET(uncore, SDE);
3141
3142 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3143 I915_WRITE(SERR_INT, 0xffffffff);
3144}
3145
3146/*
3147 * SDEIER is also touched by the interrupt handler to work around missed PCH
3148 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3149 * instead we unconditionally enable all PCH interrupt sources here, but then
3150 * only unmask them as needed with SDEIMR.
3151 *
3152 * This function needs to be called before interrupts are enabled.
3153 */
3154static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
3155{
3156 if (HAS_PCH_NOP(dev_priv))
3157 return;
3158
3159 WARN_ON(I915_READ(SDEIER) != 0);
3160 I915_WRITE(SDEIER, 0xffffffff);
3161 POSTING_READ(SDEIER);
3162}
3163
3164static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3165{
3166 struct intel_uncore *uncore = &dev_priv->uncore;
3167
3168 if (IS_CHERRYVIEW(dev_priv))
3169 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3170 else
3171 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
3172
3173 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3174 intel_uncore_write(uncore, PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3175
3176 i9xx_pipestat_irq_reset(dev_priv);
3177
3178 GEN3_IRQ_RESET(uncore, VLV_);
3179 dev_priv->irq_mask = ~0u;
3180}
3181
3182static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3183{
3184 struct intel_uncore *uncore = &dev_priv->uncore;
3185
3186 u32 pipestat_mask;
3187 u32 enable_mask;
3188 enum pipe pipe;
3189
3190 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
3191
3192 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3193 for_each_pipe(dev_priv, pipe)
3194 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3195
3196 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3197 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3198 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3199 I915_LPE_PIPE_A_INTERRUPT |
3200 I915_LPE_PIPE_B_INTERRUPT;
3201
3202 if (IS_CHERRYVIEW(dev_priv))
3203 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
3204 I915_LPE_PIPE_C_INTERRUPT;
3205
3206 WARN_ON(dev_priv->irq_mask != ~0u);
3207
3208 dev_priv->irq_mask = ~enable_mask;
3209
3210 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
3211}
3212
3213/* drm_dma.h hooks
3214*/
3215static void ironlake_irq_reset(struct drm_i915_private *dev_priv)
3216{
3217 struct intel_uncore *uncore = &dev_priv->uncore;
3218
3219 GEN3_IRQ_RESET(uncore, DE);
3220 if (IS_GEN(dev_priv, 7))
3221 intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
3222
3223 if (IS_HASWELL(dev_priv)) {
3224 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3225 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3226 }
3227
3228 gen5_gt_irq_reset(&dev_priv->gt);
3229
3230 ibx_irq_reset(dev_priv);
3231}
3232
3233static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
3234{
3235 I915_WRITE(VLV_MASTER_IER, 0);
3236 POSTING_READ(VLV_MASTER_IER);
3237
3238 gen5_gt_irq_reset(&dev_priv->gt);
3239
3240 spin_lock_irq(&dev_priv->irq_lock);
3241 if (dev_priv->display_irqs_enabled)
3242 vlv_display_irq_reset(dev_priv);
3243 spin_unlock_irq(&dev_priv->irq_lock);
3244}
3245
3246static void gen8_irq_reset(struct drm_i915_private *dev_priv)
3247{
3248 struct intel_uncore *uncore = &dev_priv->uncore;
3249 int pipe;
3250
3251 gen8_master_intr_disable(dev_priv->uncore.regs);
3252
3253 gen8_gt_irq_reset(&dev_priv->gt);
3254
3255 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3256 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3257
3258 for_each_pipe(dev_priv, pipe)
3259 if (intel_display_power_is_enabled(dev_priv,
3260 POWER_DOMAIN_PIPE(pipe)))
3261 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3262
3263 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3264 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3265 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3266
3267 if (HAS_PCH_SPLIT(dev_priv))
3268 ibx_irq_reset(dev_priv);
3269}
3270
3271static void gen11_irq_reset(struct drm_i915_private *dev_priv)
3272{
3273 struct intel_uncore *uncore = &dev_priv->uncore;
3274 int pipe;
3275
3276 gen11_master_intr_disable(dev_priv->uncore.regs);
3277
3278 gen11_gt_irq_reset(&dev_priv->gt);
3279
3280 intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
3281
3282 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3283 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3284
3285 for_each_pipe(dev_priv, pipe)
3286 if (intel_display_power_is_enabled(dev_priv,
3287 POWER_DOMAIN_PIPE(pipe)))
3288 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3289
3290 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3291 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3292 GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
3293 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
3294 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3295
3296 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3297 GEN3_IRQ_RESET(uncore, SDE);
3298}
3299
3300void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3301 u8 pipe_mask)
3302{
3303 struct intel_uncore *uncore = &dev_priv->uncore;
3304
3305 u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3306 enum pipe pipe;
3307
3308 spin_lock_irq(&dev_priv->irq_lock);
3309
3310 if (!intel_irqs_enabled(dev_priv)) {
3311 spin_unlock_irq(&dev_priv->irq_lock);
3312 return;
3313 }
3314
3315 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3316 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3317 dev_priv->de_irq_mask[pipe],
3318 ~dev_priv->de_irq_mask[pipe] | extra_ier);
3319
3320 spin_unlock_irq(&dev_priv->irq_lock);
3321}
3322
3323void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3324 u8 pipe_mask)
3325{
3326 struct intel_uncore *uncore = &dev_priv->uncore;
3327 enum pipe pipe;
3328
3329 spin_lock_irq(&dev_priv->irq_lock);
3330
3331 if (!intel_irqs_enabled(dev_priv)) {
3332 spin_unlock_irq(&dev_priv->irq_lock);
3333 return;
3334 }
3335
3336 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3337 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3338
3339 spin_unlock_irq(&dev_priv->irq_lock);
3340
3341 /* make sure we're done processing display irqs */
3342 intel_synchronize_irq(dev_priv);
3343}
3344
3345static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
3346{
3347 struct intel_uncore *uncore = &dev_priv->uncore;
3348
3349 I915_WRITE(GEN8_MASTER_IRQ, 0);
3350 POSTING_READ(GEN8_MASTER_IRQ);
3351
3352 gen8_gt_irq_reset(&dev_priv->gt);
3353
3354 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3355
3356 spin_lock_irq(&dev_priv->irq_lock);
3357 if (dev_priv->display_irqs_enabled)
3358 vlv_display_irq_reset(dev_priv);
3359 spin_unlock_irq(&dev_priv->irq_lock);
3360}
3361
3362static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3363 const u32 hpd[HPD_NUM_PINS])
3364{
3365 struct intel_encoder *encoder;
3366 u32 enabled_irqs = 0;
3367
3368 for_each_intel_encoder(&dev_priv->drm, encoder)
3369 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3370 enabled_irqs |= hpd[encoder->hpd_pin];
3371
3372 return enabled_irqs;
3373}
3374
3375static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3376{
3377 u32 hotplug;
3378
3379 /*
3380 * Enable digital hotplug on the PCH, and configure the DP short pulse
3381 * duration to 2ms (which is the minimum in the Display Port spec).
3382 * The pulse duration bits are reserved on LPT+.
3383 */
3384 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3385 hotplug &= ~(PORTB_PULSE_DURATION_MASK |
3386 PORTC_PULSE_DURATION_MASK |
3387 PORTD_PULSE_DURATION_MASK);
3388 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3389 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3390 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3391 /*
3392 * When CPU and PCH are on the same package, port A
3393 * HPD must be enabled in both north and south.
3394 */
3395 if (HAS_PCH_LPT_LP(dev_priv))
3396 hotplug |= PORTA_HOTPLUG_ENABLE;
3397 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3398}
3399
3400static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3401{
3402 u32 hotplug_irqs, enabled_irqs;
3403
3404 if (HAS_PCH_IBX(dev_priv)) {
3405 hotplug_irqs = SDE_HOTPLUG_MASK;
3406 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3407 } else {
3408 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3409 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3410 }
3411
3412 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3413
3414 ibx_hpd_detection_setup(dev_priv);
3415}
3416
3417static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv,
3418 u32 ddi_hotplug_enable_mask,
3419 u32 tc_hotplug_enable_mask)
3420{
3421 u32 hotplug;
3422
3423 hotplug = I915_READ(SHOTPLUG_CTL_DDI);
3424 hotplug |= ddi_hotplug_enable_mask;
3425 I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
3426
3427 if (tc_hotplug_enable_mask) {
3428 hotplug = I915_READ(SHOTPLUG_CTL_TC);
3429 hotplug |= tc_hotplug_enable_mask;
3430 I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
3431 }
3432}
3433
3434static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
3435{
3436 u32 hotplug_irqs, enabled_irqs;
3437
3438 hotplug_irqs = SDE_DDI_MASK_ICP | SDE_TC_MASK_ICP;
3439 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_icp);
3440
3441 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3442
3443 icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK,
3444 ICP_TC_HPD_ENABLE_MASK);
3445}
3446
3447static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
3448{
3449 u32 hotplug_irqs, enabled_irqs;
3450
3451 hotplug_irqs = SDE_DDI_MASK_TGP;
3452 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_mcc);
3453
3454 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3455
3456 icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, 0);
3457}
3458
3459static void tgp_hpd_irq_setup(struct drm_i915_private *dev_priv)
3460{
3461 u32 hotplug_irqs, enabled_irqs;
3462
3463 hotplug_irqs = SDE_DDI_MASK_TGP | SDE_TC_MASK_TGP;
3464 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_tgp);
3465
3466 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3467
3468 icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
3469 TGP_TC_HPD_ENABLE_MASK);
3470}
3471
3472static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
3473{
3474 u32 hotplug;
3475
3476 hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
3477 hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
3478 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
3479 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
3480 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
3481 I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
3482
3483 hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
3484 hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
3485 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
3486 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
3487 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
3488 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
3489}
3490
3491static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
3492{
3493 u32 hotplug_irqs, enabled_irqs;
3494 const u32 *hpd;
3495 u32 val;
3496
3497 hpd = INTEL_GEN(dev_priv) >= 12 ? hpd_gen12 : hpd_gen11;
3498 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd);
3499 hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK;
3500
3501 val = I915_READ(GEN11_DE_HPD_IMR);
3502 val &= ~hotplug_irqs;
3503 I915_WRITE(GEN11_DE_HPD_IMR, val);
3504 POSTING_READ(GEN11_DE_HPD_IMR);
3505
3506 gen11_hpd_detection_setup(dev_priv);
3507
3508 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
3509 tgp_hpd_irq_setup(dev_priv);
3510 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3511 icp_hpd_irq_setup(dev_priv);
3512}
3513
3514static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3515{
3516 u32 val, hotplug;
3517
3518 /* Display WA #1179 WaHardHangonHotPlug: cnp */
3519 if (HAS_PCH_CNP(dev_priv)) {
3520 val = I915_READ(SOUTH_CHICKEN1);
3521 val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
3522 val |= CHASSIS_CLK_REQ_DURATION(0xf);
3523 I915_WRITE(SOUTH_CHICKEN1, val);
3524 }
3525
3526 /* Enable digital hotplug on the PCH */
3527 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3528 hotplug |= PORTA_HOTPLUG_ENABLE |
3529 PORTB_HOTPLUG_ENABLE |
3530 PORTC_HOTPLUG_ENABLE |
3531 PORTD_HOTPLUG_ENABLE;
3532 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3533
3534 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3535 hotplug |= PORTE_HOTPLUG_ENABLE;
3536 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3537}
3538
3539static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3540{
3541 u32 hotplug_irqs, enabled_irqs;
3542
3543 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3544 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3545
3546 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3547
3548 spt_hpd_detection_setup(dev_priv);
3549}
3550
3551static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3552{
3553 u32 hotplug;
3554
3555 /*
3556 * Enable digital hotplug on the CPU, and configure the DP short pulse
3557 * duration to 2ms (which is the minimum in the Display Port spec)
3558 * The pulse duration bits are reserved on HSW+.
3559 */
3560 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3561 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3562 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
3563 DIGITAL_PORTA_PULSE_DURATION_2ms;
3564 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3565}
3566
3567static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3568{
3569 u32 hotplug_irqs, enabled_irqs;
3570
3571 if (INTEL_GEN(dev_priv) >= 8) {
3572 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3573 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3574
3575 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3576 } else if (INTEL_GEN(dev_priv) >= 7) {
3577 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3578 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3579
3580 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3581 } else {
3582 hotplug_irqs = DE_DP_A_HOTPLUG;
3583 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3584
3585 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3586 }
3587
3588 ilk_hpd_detection_setup(dev_priv);
3589
3590 ibx_hpd_irq_setup(dev_priv);
3591}
3592
3593static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
3594 u32 enabled_irqs)
3595{
3596 u32 hotplug;
3597
3598 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3599 hotplug |= PORTA_HOTPLUG_ENABLE |
3600 PORTB_HOTPLUG_ENABLE |
3601 PORTC_HOTPLUG_ENABLE;
3602
3603 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3604 hotplug, enabled_irqs);
3605 hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3606
3607 /*
3608 * For BXT invert bit has to be set based on AOB design
3609 * for HPD detection logic, update it based on VBT fields.
3610 */
3611 if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3612 intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3613 hotplug |= BXT_DDIA_HPD_INVERT;
3614 if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3615 intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3616 hotplug |= BXT_DDIB_HPD_INVERT;
3617 if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3618 intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3619 hotplug |= BXT_DDIC_HPD_INVERT;
3620
3621 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3622}
3623
3624static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3625{
3626 __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
3627}
3628
3629static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3630{
3631 u32 hotplug_irqs, enabled_irqs;
3632
3633 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3634 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3635
3636 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3637
3638 __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3639}
3640
3641static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
3642{
3643 u32 mask;
3644
3645 if (HAS_PCH_NOP(dev_priv))
3646 return;
3647
3648 if (HAS_PCH_IBX(dev_priv))
3649 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3650 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3651 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3652 else
3653 mask = SDE_GMBUS_CPT;
3654
3655 gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3656 I915_WRITE(SDEIMR, ~mask);
3657
3658 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
3659 HAS_PCH_LPT(dev_priv))
3660 ibx_hpd_detection_setup(dev_priv);
3661 else
3662 spt_hpd_detection_setup(dev_priv);
3663}
3664
3665static void ironlake_irq_postinstall(struct drm_i915_private *dev_priv)
3666{
3667 struct intel_uncore *uncore = &dev_priv->uncore;
3668 u32 display_mask, extra_mask;
3669
3670 if (INTEL_GEN(dev_priv) >= 7) {
3671 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3672 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
3673 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3674 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3675 DE_DP_A_HOTPLUG_IVB);
3676 } else {
3677 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3678 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
3679 DE_PIPEA_CRC_DONE | DE_POISON);
3680 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3681 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3682 DE_DP_A_HOTPLUG);
3683 }
3684
3685 if (IS_HASWELL(dev_priv)) {
3686 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3687 intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
3688 display_mask |= DE_EDP_PSR_INT_HSW;
3689 }
3690
3691 dev_priv->irq_mask = ~display_mask;
3692
3693 ibx_irq_pre_postinstall(dev_priv);
3694
3695 GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
3696 display_mask | extra_mask);
3697
3698 gen5_gt_irq_postinstall(&dev_priv->gt);
3699
3700 ilk_hpd_detection_setup(dev_priv);
3701
3702 ibx_irq_postinstall(dev_priv);
3703
3704 if (IS_IRONLAKE_M(dev_priv)) {
3705 /* Enable PCU event interrupts
3706 *
3707 * spinlocking not required here for correctness since interrupt
3708 * setup is guaranteed to run in single-threaded context. But we
3709 * need it to make the assert_spin_locked happy. */
3710 spin_lock_irq(&dev_priv->irq_lock);
3711 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3712 spin_unlock_irq(&dev_priv->irq_lock);
3713 }
3714}
3715
3716void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3717{
3718 lockdep_assert_held(&dev_priv->irq_lock);
3719
3720 if (dev_priv->display_irqs_enabled)
3721 return;
3722
3723 dev_priv->display_irqs_enabled = true;
3724
3725 if (intel_irqs_enabled(dev_priv)) {
3726 vlv_display_irq_reset(dev_priv);
3727 vlv_display_irq_postinstall(dev_priv);
3728 }
3729}
3730
3731void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3732{
3733 lockdep_assert_held(&dev_priv->irq_lock);
3734
3735 if (!dev_priv->display_irqs_enabled)
3736 return;
3737
3738 dev_priv->display_irqs_enabled = false;
3739
3740 if (intel_irqs_enabled(dev_priv))
3741 vlv_display_irq_reset(dev_priv);
3742}
3743
3744
3745static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
3746{
3747 gen5_gt_irq_postinstall(&dev_priv->gt);
3748
3749 spin_lock_irq(&dev_priv->irq_lock);
3750 if (dev_priv->display_irqs_enabled)
3751 vlv_display_irq_postinstall(dev_priv);
3752 spin_unlock_irq(&dev_priv->irq_lock);
3753
3754 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3755 POSTING_READ(VLV_MASTER_IER);
3756}
3757
3758static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3759{
3760 struct intel_uncore *uncore = &dev_priv->uncore;
3761
3762 u32 de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3763 u32 de_pipe_enables;
3764 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3765 u32 de_port_enables;
3766 u32 de_misc_masked = GEN8_DE_EDP_PSR;
3767 enum pipe pipe;
3768
3769 if (INTEL_GEN(dev_priv) <= 10)
3770 de_misc_masked |= GEN8_DE_MISC_GSE;
3771
3772 if (INTEL_GEN(dev_priv) >= 9) {
3773 de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3774 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3775 GEN9_AUX_CHANNEL_D;
3776 if (IS_GEN9_LP(dev_priv))
3777 de_port_masked |= BXT_DE_PORT_GMBUS;
3778 } else {
3779 de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3780 }
3781
3782 if (INTEL_GEN(dev_priv) >= 11)
3783 de_port_masked |= ICL_AUX_CHANNEL_E;
3784
3785 if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >= 11)
3786 de_port_masked |= CNL_AUX_CHANNEL_F;
3787
3788 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3789 GEN8_PIPE_FIFO_UNDERRUN;
3790
3791 de_port_enables = de_port_masked;
3792 if (IS_GEN9_LP(dev_priv))
3793 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3794 else if (IS_BROADWELL(dev_priv))
3795 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3796
3797 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3798 intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
3799
3800 for_each_pipe(dev_priv, pipe) {
3801 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
3802
3803 if (intel_display_power_is_enabled(dev_priv,
3804 POWER_DOMAIN_PIPE(pipe)))
3805 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3806 dev_priv->de_irq_mask[pipe],
3807 de_pipe_enables);
3808 }
3809
3810 GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3811 GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3812
3813 if (INTEL_GEN(dev_priv) >= 11) {
3814 u32 de_hpd_masked = 0;
3815 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
3816 GEN11_DE_TBT_HOTPLUG_MASK;
3817
3818 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
3819 de_hpd_enables);
3820 gen11_hpd_detection_setup(dev_priv);
3821 } else if (IS_GEN9_LP(dev_priv)) {
3822 bxt_hpd_detection_setup(dev_priv);
3823 } else if (IS_BROADWELL(dev_priv)) {
3824 ilk_hpd_detection_setup(dev_priv);
3825 }
3826}
3827
3828static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
3829{
3830 if (HAS_PCH_SPLIT(dev_priv))
3831 ibx_irq_pre_postinstall(dev_priv);
3832
3833 gen8_gt_irq_postinstall(&dev_priv->gt);
3834 gen8_de_irq_postinstall(dev_priv);
3835
3836 if (HAS_PCH_SPLIT(dev_priv))
3837 ibx_irq_postinstall(dev_priv);
3838
3839 gen8_master_intr_enable(dev_priv->uncore.regs);
3840}
3841
3842static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
3843{
3844 u32 mask = SDE_GMBUS_ICP;
3845
3846 WARN_ON(I915_READ(SDEIER) != 0);
3847 I915_WRITE(SDEIER, 0xffffffff);
3848 POSTING_READ(SDEIER);
3849
3850 gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3851 I915_WRITE(SDEIMR, ~mask);
3852
3853 if (HAS_PCH_TGP(dev_priv))
3854 icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
3855 TGP_TC_HPD_ENABLE_MASK);
3856 else if (HAS_PCH_MCC(dev_priv))
3857 icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, 0);
3858 else
3859 icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK,
3860 ICP_TC_HPD_ENABLE_MASK);
3861}
3862
3863static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
3864{
3865 struct intel_uncore *uncore = &dev_priv->uncore;
3866 u32 gu_misc_masked = GEN11_GU_MISC_GSE;
3867
3868 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3869 icp_irq_postinstall(dev_priv);
3870
3871 gen11_gt_irq_postinstall(&dev_priv->gt);
3872 gen8_de_irq_postinstall(dev_priv);
3873
3874 GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
3875
3876 I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
3877
3878 gen11_master_intr_enable(uncore->regs);
3879 POSTING_READ(GEN11_GFX_MSTR_IRQ);
3880}
3881
3882static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
3883{
3884 gen8_gt_irq_postinstall(&dev_priv->gt);
3885
3886 spin_lock_irq(&dev_priv->irq_lock);
3887 if (dev_priv->display_irqs_enabled)
3888 vlv_display_irq_postinstall(dev_priv);
3889 spin_unlock_irq(&dev_priv->irq_lock);
3890
3891 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3892 POSTING_READ(GEN8_MASTER_IRQ);
3893}
3894
3895static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
3896{
3897 struct intel_uncore *uncore = &dev_priv->uncore;
3898
3899 i9xx_pipestat_irq_reset(dev_priv);
3900
3901 GEN2_IRQ_RESET(uncore);
3902}
3903
3904static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
3905{
3906 struct intel_uncore *uncore = &dev_priv->uncore;
3907 u16 enable_mask;
3908
3909 intel_uncore_write16(uncore,
3910 EMR,
3911 ~(I915_ERROR_PAGE_TABLE |
3912 I915_ERROR_MEMORY_REFRESH));
3913
3914 /* Unmask the interrupts that we always want on. */
3915 dev_priv->irq_mask =
3916 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3917 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3918 I915_MASTER_ERROR_INTERRUPT);
3919
3920 enable_mask =
3921 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3922 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3923 I915_MASTER_ERROR_INTERRUPT |
3924 I915_USER_INTERRUPT;
3925
3926 GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
3927
3928 /* Interrupt setup is already guaranteed to be single-threaded, this is
3929 * just to make the assert_spin_locked check happy. */
3930 spin_lock_irq(&dev_priv->irq_lock);
3931 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3932 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3933 spin_unlock_irq(&dev_priv->irq_lock);
3934}
3935
3936static void i8xx_error_irq_ack(struct drm_i915_private *i915,
3937 u16 *eir, u16 *eir_stuck)
3938{
3939 struct intel_uncore *uncore = &i915->uncore;
3940 u16 emr;
3941
3942 *eir = intel_uncore_read16(uncore, EIR);
3943
3944 if (*eir)
3945 intel_uncore_write16(uncore, EIR, *eir);
3946
3947 *eir_stuck = intel_uncore_read16(uncore, EIR);
3948 if (*eir_stuck == 0)
3949 return;
3950
3951 /*
3952 * Toggle all EMR bits to make sure we get an edge
3953 * in the ISR master error bit if we don't clear
3954 * all the EIR bits. Otherwise the edge triggered
3955 * IIR on i965/g4x wouldn't notice that an interrupt
3956 * is still pending. Also some EIR bits can't be
3957 * cleared except by handling the underlying error
3958 * (or by a GPU reset) so we mask any bit that
3959 * remains set.
3960 */
3961 emr = intel_uncore_read16(uncore, EMR);
3962 intel_uncore_write16(uncore, EMR, 0xffff);
3963 intel_uncore_write16(uncore, EMR, emr | *eir_stuck);
3964}
3965
3966static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
3967 u16 eir, u16 eir_stuck)
3968{
3969 DRM_DEBUG("Master Error: EIR 0x%04x\n", eir);
3970
3971 if (eir_stuck)
3972 DRM_DEBUG_DRIVER("EIR stuck: 0x%04x, masked\n", eir_stuck);
3973}
3974
3975static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
3976 u32 *eir, u32 *eir_stuck)
3977{
3978 u32 emr;
3979
3980 *eir = I915_READ(EIR);
3981
3982 I915_WRITE(EIR, *eir);
3983
3984 *eir_stuck = I915_READ(EIR);
3985 if (*eir_stuck == 0)
3986 return;
3987
3988 /*
3989 * Toggle all EMR bits to make sure we get an edge
3990 * in the ISR master error bit if we don't clear
3991 * all the EIR bits. Otherwise the edge triggered
3992 * IIR on i965/g4x wouldn't notice that an interrupt
3993 * is still pending. Also some EIR bits can't be
3994 * cleared except by handling the underlying error
3995 * (or by a GPU reset) so we mask any bit that
3996 * remains set.
3997 */
3998 emr = I915_READ(EMR);
3999 I915_WRITE(EMR, 0xffffffff);
4000 I915_WRITE(EMR, emr | *eir_stuck);
4001}
4002
4003static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
4004 u32 eir, u32 eir_stuck)
4005{
4006 DRM_DEBUG("Master Error, EIR 0x%08x\n", eir);
4007
4008 if (eir_stuck)
4009 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masked\n", eir_stuck);
4010}
4011
4012static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4013{
4014 struct drm_i915_private *dev_priv = arg;
4015 irqreturn_t ret = IRQ_NONE;
4016
4017 if (!intel_irqs_enabled(dev_priv))
4018 return IRQ_NONE;
4019
4020 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4021 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4022
4023 do {
4024 u32 pipe_stats[I915_MAX_PIPES] = {};
4025 u16 eir = 0, eir_stuck = 0;
4026 u16 iir;
4027
4028 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
4029 if (iir == 0)
4030 break;
4031
4032 ret = IRQ_HANDLED;
4033
4034 /* Call regardless, as some status bits might not be
4035 * signalled in iir */
4036 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4037
4038 if (iir & I915_MASTER_ERROR_INTERRUPT)
4039 i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4040
4041 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
4042
4043 if (iir & I915_USER_INTERRUPT)
4044 intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
4045
4046 if (iir & I915_MASTER_ERROR_INTERRUPT)
4047 i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
4048
4049 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4050 } while (0);
4051
4052 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4053
4054 return ret;
4055}
4056
4057static void i915_irq_reset(struct drm_i915_private *dev_priv)
4058{
4059 struct intel_uncore *uncore = &dev_priv->uncore;
4060
4061 if (I915_HAS_HOTPLUG(dev_priv)) {
4062 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4063 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4064 }
4065
4066 i9xx_pipestat_irq_reset(dev_priv);
4067
4068 GEN3_IRQ_RESET(uncore, GEN2_);
4069}
4070
4071static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
4072{
4073 struct intel_uncore *uncore = &dev_priv->uncore;
4074 u32 enable_mask;
4075
4076 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
4077 I915_ERROR_MEMORY_REFRESH));
4078
4079 /* Unmask the interrupts that we always want on. */
4080 dev_priv->irq_mask =
4081 ~(I915_ASLE_INTERRUPT |
4082 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4083 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4084 I915_MASTER_ERROR_INTERRUPT);
4085
4086 enable_mask =
4087 I915_ASLE_INTERRUPT |
4088 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4089 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4090 I915_MASTER_ERROR_INTERRUPT |
4091 I915_USER_INTERRUPT;
4092
4093 if (I915_HAS_HOTPLUG(dev_priv)) {
4094 /* Enable in IER... */
4095 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4096 /* and unmask in IMR */
4097 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4098 }
4099
4100 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4101
4102 /* Interrupt setup is already guaranteed to be single-threaded, this is
4103 * just to make the assert_spin_locked check happy. */
4104 spin_lock_irq(&dev_priv->irq_lock);
4105 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4106 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4107 spin_unlock_irq(&dev_priv->irq_lock);
4108
4109 i915_enable_asle_pipestat(dev_priv);
4110}
4111
4112static irqreturn_t i915_irq_handler(int irq, void *arg)
4113{
4114 struct drm_i915_private *dev_priv = arg;
4115 irqreturn_t ret = IRQ_NONE;
4116
4117 if (!intel_irqs_enabled(dev_priv))
4118 return IRQ_NONE;
4119
4120 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4121 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4122
4123 do {
4124 u32 pipe_stats[I915_MAX_PIPES] = {};
4125 u32 eir = 0, eir_stuck = 0;
4126 u32 hotplug_status = 0;
4127 u32 iir;
4128
4129 iir = I915_READ(GEN2_IIR);
4130 if (iir == 0)
4131 break;
4132
4133 ret = IRQ_HANDLED;
4134
4135 if (I915_HAS_HOTPLUG(dev_priv) &&
4136 iir & I915_DISPLAY_PORT_INTERRUPT)
4137 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4138
4139 /* Call regardless, as some status bits might not be
4140 * signalled in iir */
4141 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4142
4143 if (iir & I915_MASTER_ERROR_INTERRUPT)
4144 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4145
4146 I915_WRITE(GEN2_IIR, iir);
4147
4148 if (iir & I915_USER_INTERRUPT)
4149 intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
4150
4151 if (iir & I915_MASTER_ERROR_INTERRUPT)
4152 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
4153
4154 if (hotplug_status)
4155 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4156
4157 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4158 } while (0);
4159
4160 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4161
4162 return ret;
4163}
4164
4165static void i965_irq_reset(struct drm_i915_private *dev_priv)
4166{
4167 struct intel_uncore *uncore = &dev_priv->uncore;
4168
4169 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4170 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4171
4172 i9xx_pipestat_irq_reset(dev_priv);
4173
4174 GEN3_IRQ_RESET(uncore, GEN2_);
4175}
4176
4177static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
4178{
4179 struct intel_uncore *uncore = &dev_priv->uncore;
4180 u32 enable_mask;
4181 u32 error_mask;
4182
4183 /*
4184 * Enable some error detection, note the instruction error mask
4185 * bit is reserved, so we leave it masked.
4186 */
4187 if (IS_G4X(dev_priv)) {
4188 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4189 GM45_ERROR_MEM_PRIV |
4190 GM45_ERROR_CP_PRIV |
4191 I915_ERROR_MEMORY_REFRESH);
4192 } else {
4193 error_mask = ~(I915_ERROR_PAGE_TABLE |
4194 I915_ERROR_MEMORY_REFRESH);
4195 }
4196 I915_WRITE(EMR, error_mask);
4197
4198 /* Unmask the interrupts that we always want on. */
4199 dev_priv->irq_mask =
4200 ~(I915_ASLE_INTERRUPT |
4201 I915_DISPLAY_PORT_INTERRUPT |
4202 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4203 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4204 I915_MASTER_ERROR_INTERRUPT);
4205
4206 enable_mask =
4207 I915_ASLE_INTERRUPT |
4208 I915_DISPLAY_PORT_INTERRUPT |
4209 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4210 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4211 I915_MASTER_ERROR_INTERRUPT |
4212 I915_USER_INTERRUPT;
4213
4214 if (IS_G4X(dev_priv))
4215 enable_mask |= I915_BSD_USER_INTERRUPT;
4216
4217 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4218
4219 /* Interrupt setup is already guaranteed to be single-threaded, this is
4220 * just to make the assert_spin_locked check happy. */
4221 spin_lock_irq(&dev_priv->irq_lock);
4222 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4223 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4224 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4225 spin_unlock_irq(&dev_priv->irq_lock);
4226
4227 i915_enable_asle_pipestat(dev_priv);
4228}
4229
4230static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4231{
4232 u32 hotplug_en;
4233
4234 lockdep_assert_held(&dev_priv->irq_lock);
4235
4236 /* Note HDMI and DP share hotplug bits */
4237 /* enable bits are the same for all generations */
4238 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4239 /* Programming the CRT detection parameters tends
4240 to generate a spurious hotplug event about three
4241 seconds later. So just do it once.
4242 */
4243 if (IS_G4X(dev_priv))
4244 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4245 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4246
4247 /* Ignore TV since it's buggy */
4248 i915_hotplug_interrupt_update_locked(dev_priv,
4249 HOTPLUG_INT_EN_MASK |
4250 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4251 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4252 hotplug_en);
4253}
4254
4255static irqreturn_t i965_irq_handler(int irq, void *arg)
4256{
4257 struct drm_i915_private *dev_priv = arg;
4258 irqreturn_t ret = IRQ_NONE;
4259
4260 if (!intel_irqs_enabled(dev_priv))
4261 return IRQ_NONE;
4262
4263 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4264 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4265
4266 do {
4267 u32 pipe_stats[I915_MAX_PIPES] = {};
4268 u32 eir = 0, eir_stuck = 0;
4269 u32 hotplug_status = 0;
4270 u32 iir;
4271
4272 iir = I915_READ(GEN2_IIR);
4273 if (iir == 0)
4274 break;
4275
4276 ret = IRQ_HANDLED;
4277
4278 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4279 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4280
4281 /* Call regardless, as some status bits might not be
4282 * signalled in iir */
4283 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4284
4285 if (iir & I915_MASTER_ERROR_INTERRUPT)
4286 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4287
4288 I915_WRITE(GEN2_IIR, iir);
4289
4290 if (iir & I915_USER_INTERRUPT)
4291 intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
4292
4293 if (iir & I915_BSD_USER_INTERRUPT)
4294 intel_engine_breadcrumbs_irq(dev_priv->engine[VCS0]);
4295
4296 if (iir & I915_MASTER_ERROR_INTERRUPT)
4297 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
4298
4299 if (hotplug_status)
4300 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4301
4302 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4303 } while (0);
4304
4305 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4306
4307 return ret;
4308}
4309
4310/**
4311 * intel_irq_init - initializes irq support
4312 * @dev_priv: i915 device instance
4313 *
4314 * This function initializes all the irq support including work items, timers
4315 * and all the vtables. It does not setup the interrupt itself though.
4316 */
4317void intel_irq_init(struct drm_i915_private *dev_priv)
4318{
4319 struct drm_device *dev = &dev_priv->drm;
4320 struct intel_rps *rps = &dev_priv->gt_pm.rps;
4321 int i;
4322
4323 if (IS_I945GM(dev_priv))
4324 i945gm_vblank_work_init(dev_priv);
4325
4326 intel_hpd_init_work(dev_priv);
4327
4328 INIT_WORK(&rps->work, gen6_pm_rps_work);
4329
4330 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4331 for (i = 0; i < MAX_L3_SLICES; ++i)
4332 dev_priv->l3_parity.remap_info[i] = NULL;
4333
4334 /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
4335 if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11)
4336 dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
4337
4338 /* Let's track the enabled rps events */
4339 if (IS_VALLEYVIEW(dev_priv))
4340 /* WaGsvRC0ResidencyMethod:vlv */
4341 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4342 else
4343 dev_priv->pm_rps_events = (GEN6_PM_RP_UP_THRESHOLD |
4344 GEN6_PM_RP_DOWN_THRESHOLD |
4345 GEN6_PM_RP_DOWN_TIMEOUT);
4346
4347 /* We share the register with other engine */
4348 if (INTEL_GEN(dev_priv) > 9)
4349 GEM_WARN_ON(dev_priv->pm_rps_events & 0xffff0000);
4350
4351 rps->pm_intrmsk_mbz = 0;
4352
4353 /*
4354 * SNB,IVB,HSW can while VLV,CHV may hard hang on looping batchbuffer
4355 * if GEN6_PM_UP_EI_EXPIRED is masked.
4356 *
4357 * TODO: verify if this can be reproduced on VLV,CHV.
4358 */
4359 if (INTEL_GEN(dev_priv) <= 7)
4360 rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
4361
4362 if (INTEL_GEN(dev_priv) >= 8)
4363 rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
4364
4365 dev->vblank_disable_immediate = true;
4366
4367 /* Most platforms treat the display irq block as an always-on
4368 * power domain. vlv/chv can disable it at runtime and need
4369 * special care to avoid writing any of the display block registers
4370 * outside of the power domain. We defer setting up the display irqs
4371 * in this case to the runtime pm.
4372 */
4373 dev_priv->display_irqs_enabled = true;
4374 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4375 dev_priv->display_irqs_enabled = false;
4376
4377 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4378 /* If we have MST support, we want to avoid doing short HPD IRQ storm
4379 * detection, as short HPD storms will occur as a natural part of
4380 * sideband messaging with MST.
4381 * On older platforms however, IRQ storms can occur with both long and
4382 * short pulses, as seen on some G4x systems.
4383 */
4384 dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
4385
4386 if (HAS_GMCH(dev_priv)) {
4387 if (I915_HAS_HOTPLUG(dev_priv))
4388 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4389 } else {
4390 if (HAS_PCH_MCC(dev_priv))
4391 /* EHL doesn't need most of gen11_hpd_irq_setup */
4392 dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
4393 else if (INTEL_GEN(dev_priv) >= 11)
4394 dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
4395 else if (IS_GEN9_LP(dev_priv))
4396 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4397 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
4398 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4399 else
4400 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4401 }
4402}
4403
4404/**
4405 * intel_irq_fini - deinitializes IRQ support
4406 * @i915: i915 device instance
4407 *
4408 * This function deinitializes all the IRQ support.
4409 */
4410void intel_irq_fini(struct drm_i915_private *i915)
4411{
4412 int i;
4413
4414 if (IS_I945GM(i915))
4415 i945gm_vblank_work_fini(i915);
4416
4417 for (i = 0; i < MAX_L3_SLICES; ++i)
4418 kfree(i915->l3_parity.remap_info[i]);
4419}
4420
4421static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
4422{
4423 if (HAS_GMCH(dev_priv)) {
4424 if (IS_CHERRYVIEW(dev_priv))
4425 return cherryview_irq_handler;
4426 else if (IS_VALLEYVIEW(dev_priv))
4427 return valleyview_irq_handler;
4428 else if (IS_GEN(dev_priv, 4))
4429 return i965_irq_handler;
4430 else if (IS_GEN(dev_priv, 3))
4431 return i915_irq_handler;
4432 else
4433 return i8xx_irq_handler;
4434 } else {
4435 if (INTEL_GEN(dev_priv) >= 11)
4436 return gen11_irq_handler;
4437 else if (INTEL_GEN(dev_priv) >= 8)
4438 return gen8_irq_handler;
4439 else
4440 return ironlake_irq_handler;
4441 }
4442}
4443
4444static void intel_irq_reset(struct drm_i915_private *dev_priv)
4445{
4446 if (HAS_GMCH(dev_priv)) {
4447 if (IS_CHERRYVIEW(dev_priv))
4448 cherryview_irq_reset(dev_priv);
4449 else if (IS_VALLEYVIEW(dev_priv))
4450 valleyview_irq_reset(dev_priv);
4451 else if (IS_GEN(dev_priv, 4))
4452 i965_irq_reset(dev_priv);
4453 else if (IS_GEN(dev_priv, 3))
4454 i915_irq_reset(dev_priv);
4455 else
4456 i8xx_irq_reset(dev_priv);
4457 } else {
4458 if (INTEL_GEN(dev_priv) >= 11)
4459 gen11_irq_reset(dev_priv);
4460 else if (INTEL_GEN(dev_priv) >= 8)
4461 gen8_irq_reset(dev_priv);
4462 else
4463 ironlake_irq_reset(dev_priv);
4464 }
4465}
4466
4467static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
4468{
4469 if (HAS_GMCH(dev_priv)) {
4470 if (IS_CHERRYVIEW(dev_priv))
4471 cherryview_irq_postinstall(dev_priv);
4472 else if (IS_VALLEYVIEW(dev_priv))
4473 valleyview_irq_postinstall(dev_priv);
4474 else if (IS_GEN(dev_priv, 4))
4475 i965_irq_postinstall(dev_priv);
4476 else if (IS_GEN(dev_priv, 3))
4477 i915_irq_postinstall(dev_priv);
4478 else
4479 i8xx_irq_postinstall(dev_priv);
4480 } else {
4481 if (INTEL_GEN(dev_priv) >= 11)
4482 gen11_irq_postinstall(dev_priv);
4483 else if (INTEL_GEN(dev_priv) >= 8)
4484 gen8_irq_postinstall(dev_priv);
4485 else
4486 ironlake_irq_postinstall(dev_priv);
4487 }
4488}
4489
4490/**
4491 * intel_irq_install - enables the hardware interrupt
4492 * @dev_priv: i915 device instance
4493 *
4494 * This function enables the hardware interrupt handling, but leaves the hotplug
4495 * handling still disabled. It is called after intel_irq_init().
4496 *
4497 * In the driver load and resume code we need working interrupts in a few places
4498 * but don't want to deal with the hassle of concurrent probe and hotplug
4499 * workers. Hence the split into this two-stage approach.
4500 */
4501int intel_irq_install(struct drm_i915_private *dev_priv)
4502{
4503 int irq = dev_priv->drm.pdev->irq;
4504 int ret;
4505
4506 /*
4507 * We enable some interrupt sources in our postinstall hooks, so mark
4508 * interrupts as enabled _before_ actually enabling them to avoid
4509 * special cases in our ordering checks.
4510 */
4511 dev_priv->runtime_pm.irqs_enabled = true;
4512
4513 dev_priv->drm.irq_enabled = true;
4514
4515 intel_irq_reset(dev_priv);
4516
4517 ret = request_irq(irq, intel_irq_handler(dev_priv),
4518 IRQF_SHARED, DRIVER_NAME, dev_priv);
4519 if (ret < 0) {
4520 dev_priv->drm.irq_enabled = false;
4521 return ret;
4522 }
4523
4524 intel_irq_postinstall(dev_priv);
4525
4526 return ret;
4527}
4528
4529/**
4530 * intel_irq_uninstall - finilizes all irq handling
4531 * @dev_priv: i915 device instance
4532 *
4533 * This stops interrupt and hotplug handling and unregisters and frees all
4534 * resources acquired in the init functions.
4535 */
4536void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4537{
4538 int irq = dev_priv->drm.pdev->irq;
4539
4540 /*
4541 * FIXME we can get called twice during driver load
4542 * error handling due to intel_modeset_cleanup()
4543 * calling us out of sequence. Would be nice if
4544 * it didn't do that...
4545 */
4546 if (!dev_priv->drm.irq_enabled)
4547 return;
4548
4549 dev_priv->drm.irq_enabled = false;
4550
4551 intel_irq_reset(dev_priv);
4552
4553 free_irq(irq, dev_priv);
4554
4555 intel_hpd_cancel_work(dev_priv);
4556 dev_priv->runtime_pm.irqs_enabled = false;
4557}
4558
4559/**
4560 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4561 * @dev_priv: i915 device instance
4562 *
4563 * This function is used to disable interrupts at runtime, both in the runtime
4564 * pm and the system suspend/resume code.
4565 */
4566void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4567{
4568 intel_irq_reset(dev_priv);
4569 dev_priv->runtime_pm.irqs_enabled = false;
4570 intel_synchronize_irq(dev_priv);
4571}
4572
4573/**
4574 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4575 * @dev_priv: i915 device instance
4576 *
4577 * This function is used to enable interrupts at runtime, both in the runtime
4578 * pm and the system suspend/resume code.
4579 */
4580void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4581{
4582 dev_priv->runtime_pm.irqs_enabled = true;
4583 intel_irq_reset(dev_priv);
4584 intel_irq_postinstall(dev_priv);
4585}
4586
4587bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
4588{
4589 /*
4590 * We only use drm_irq_uninstall() at unload and VT switch, so
4591 * this is the only thing we need to check.
4592 */
4593 return dev_priv->runtime_pm.irqs_enabled;
4594}
4595
4596void intel_synchronize_irq(struct drm_i915_private *i915)
4597{
4598 synchronize_irq(i915->drm.pdev->irq);
4599}