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1/*
2 * linux/arch/arm/mm/mmu.c
3 *
4 * Copyright (C) 1995-2005 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/mman.h>
15#include <linux/nodemask.h>
16#include <linux/memblock.h>
17#include <linux/fs.h>
18#include <linux/vmalloc.h>
19#include <linux/sizes.h>
20
21#include <asm/cp15.h>
22#include <asm/cputype.h>
23#include <asm/sections.h>
24#include <asm/cachetype.h>
25#include <asm/fixmap.h>
26#include <asm/sections.h>
27#include <asm/setup.h>
28#include <asm/smp_plat.h>
29#include <asm/tlb.h>
30#include <asm/highmem.h>
31#include <asm/system_info.h>
32#include <asm/traps.h>
33#include <asm/procinfo.h>
34#include <asm/memory.h>
35
36#include <asm/mach/arch.h>
37#include <asm/mach/map.h>
38#include <asm/mach/pci.h>
39#include <asm/fixmap.h>
40
41#include "fault.h"
42#include "mm.h"
43#include "tcm.h"
44
45/*
46 * empty_zero_page is a special page that is used for
47 * zero-initialized data and COW.
48 */
49struct page *empty_zero_page;
50EXPORT_SYMBOL(empty_zero_page);
51
52/*
53 * The pmd table for the upper-most set of pages.
54 */
55pmd_t *top_pmd;
56
57pmdval_t user_pmd_table = _PAGE_USER_TABLE;
58
59#define CPOLICY_UNCACHED 0
60#define CPOLICY_BUFFERED 1
61#define CPOLICY_WRITETHROUGH 2
62#define CPOLICY_WRITEBACK 3
63#define CPOLICY_WRITEALLOC 4
64
65static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
66static unsigned int ecc_mask __initdata = 0;
67pgprot_t pgprot_user;
68pgprot_t pgprot_kernel;
69pgprot_t pgprot_hyp_device;
70pgprot_t pgprot_s2;
71pgprot_t pgprot_s2_device;
72
73EXPORT_SYMBOL(pgprot_user);
74EXPORT_SYMBOL(pgprot_kernel);
75
76struct cachepolicy {
77 const char policy[16];
78 unsigned int cr_mask;
79 pmdval_t pmd;
80 pteval_t pte;
81 pteval_t pte_s2;
82};
83
84#ifdef CONFIG_ARM_LPAE
85#define s2_policy(policy) policy
86#else
87#define s2_policy(policy) 0
88#endif
89
90static struct cachepolicy cache_policies[] __initdata = {
91 {
92 .policy = "uncached",
93 .cr_mask = CR_W|CR_C,
94 .pmd = PMD_SECT_UNCACHED,
95 .pte = L_PTE_MT_UNCACHED,
96 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
97 }, {
98 .policy = "buffered",
99 .cr_mask = CR_C,
100 .pmd = PMD_SECT_BUFFERED,
101 .pte = L_PTE_MT_BUFFERABLE,
102 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
103 }, {
104 .policy = "writethrough",
105 .cr_mask = 0,
106 .pmd = PMD_SECT_WT,
107 .pte = L_PTE_MT_WRITETHROUGH,
108 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
109 }, {
110 .policy = "writeback",
111 .cr_mask = 0,
112 .pmd = PMD_SECT_WB,
113 .pte = L_PTE_MT_WRITEBACK,
114 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
115 }, {
116 .policy = "writealloc",
117 .cr_mask = 0,
118 .pmd = PMD_SECT_WBWA,
119 .pte = L_PTE_MT_WRITEALLOC,
120 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
121 }
122};
123
124#ifdef CONFIG_CPU_CP15
125static unsigned long initial_pmd_value __initdata = 0;
126
127/*
128 * Initialise the cache_policy variable with the initial state specified
129 * via the "pmd" value. This is used to ensure that on ARMv6 and later,
130 * the C code sets the page tables up with the same policy as the head
131 * assembly code, which avoids an illegal state where the TLBs can get
132 * confused. See comments in early_cachepolicy() for more information.
133 */
134void __init init_default_cache_policy(unsigned long pmd)
135{
136 int i;
137
138 initial_pmd_value = pmd;
139
140 pmd &= PMD_SECT_TEX(1) | PMD_SECT_BUFFERABLE | PMD_SECT_CACHEABLE;
141
142 for (i = 0; i < ARRAY_SIZE(cache_policies); i++)
143 if (cache_policies[i].pmd == pmd) {
144 cachepolicy = i;
145 break;
146 }
147
148 if (i == ARRAY_SIZE(cache_policies))
149 pr_err("ERROR: could not find cache policy\n");
150}
151
152/*
153 * These are useful for identifying cache coherency problems by allowing
154 * the cache or the cache and writebuffer to be turned off. (Note: the
155 * write buffer should not be on and the cache off).
156 */
157static int __init early_cachepolicy(char *p)
158{
159 int i, selected = -1;
160
161 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
162 int len = strlen(cache_policies[i].policy);
163
164 if (memcmp(p, cache_policies[i].policy, len) == 0) {
165 selected = i;
166 break;
167 }
168 }
169
170 if (selected == -1)
171 pr_err("ERROR: unknown or unsupported cache policy\n");
172
173 /*
174 * This restriction is partly to do with the way we boot; it is
175 * unpredictable to have memory mapped using two different sets of
176 * memory attributes (shared, type, and cache attribs). We can not
177 * change these attributes once the initial assembly has setup the
178 * page tables.
179 */
180 if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) {
181 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
182 cache_policies[cachepolicy].policy);
183 return 0;
184 }
185
186 if (selected != cachepolicy) {
187 unsigned long cr = __clear_cr(cache_policies[selected].cr_mask);
188 cachepolicy = selected;
189 flush_cache_all();
190 set_cr(cr);
191 }
192 return 0;
193}
194early_param("cachepolicy", early_cachepolicy);
195
196static int __init early_nocache(char *__unused)
197{
198 char *p = "buffered";
199 pr_warn("nocache is deprecated; use cachepolicy=%s\n", p);
200 early_cachepolicy(p);
201 return 0;
202}
203early_param("nocache", early_nocache);
204
205static int __init early_nowrite(char *__unused)
206{
207 char *p = "uncached";
208 pr_warn("nowb is deprecated; use cachepolicy=%s\n", p);
209 early_cachepolicy(p);
210 return 0;
211}
212early_param("nowb", early_nowrite);
213
214#ifndef CONFIG_ARM_LPAE
215static int __init early_ecc(char *p)
216{
217 if (memcmp(p, "on", 2) == 0)
218 ecc_mask = PMD_PROTECTION;
219 else if (memcmp(p, "off", 3) == 0)
220 ecc_mask = 0;
221 return 0;
222}
223early_param("ecc", early_ecc);
224#endif
225
226#else /* ifdef CONFIG_CPU_CP15 */
227
228static int __init early_cachepolicy(char *p)
229{
230 pr_warn("cachepolicy kernel parameter not supported without cp15\n");
231}
232early_param("cachepolicy", early_cachepolicy);
233
234static int __init noalign_setup(char *__unused)
235{
236 pr_warn("noalign kernel parameter not supported without cp15\n");
237}
238__setup("noalign", noalign_setup);
239
240#endif /* ifdef CONFIG_CPU_CP15 / else */
241
242#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
243#define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
244#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
245
246static struct mem_type mem_types[] = {
247 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
248 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
249 L_PTE_SHARED,
250 .prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) |
251 s2_policy(L_PTE_S2_MT_DEV_SHARED) |
252 L_PTE_SHARED,
253 .prot_l1 = PMD_TYPE_TABLE,
254 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
255 .domain = DOMAIN_IO,
256 },
257 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
258 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
259 .prot_l1 = PMD_TYPE_TABLE,
260 .prot_sect = PROT_SECT_DEVICE,
261 .domain = DOMAIN_IO,
262 },
263 [MT_DEVICE_CACHED] = { /* ioremap_cached */
264 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
265 .prot_l1 = PMD_TYPE_TABLE,
266 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
267 .domain = DOMAIN_IO,
268 },
269 [MT_DEVICE_WC] = { /* ioremap_wc */
270 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
271 .prot_l1 = PMD_TYPE_TABLE,
272 .prot_sect = PROT_SECT_DEVICE,
273 .domain = DOMAIN_IO,
274 },
275 [MT_UNCACHED] = {
276 .prot_pte = PROT_PTE_DEVICE,
277 .prot_l1 = PMD_TYPE_TABLE,
278 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
279 .domain = DOMAIN_IO,
280 },
281 [MT_CACHECLEAN] = {
282 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
283 .domain = DOMAIN_KERNEL,
284 },
285#ifndef CONFIG_ARM_LPAE
286 [MT_MINICLEAN] = {
287 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
288 .domain = DOMAIN_KERNEL,
289 },
290#endif
291 [MT_LOW_VECTORS] = {
292 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
293 L_PTE_RDONLY,
294 .prot_l1 = PMD_TYPE_TABLE,
295 .domain = DOMAIN_VECTORS,
296 },
297 [MT_HIGH_VECTORS] = {
298 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
299 L_PTE_USER | L_PTE_RDONLY,
300 .prot_l1 = PMD_TYPE_TABLE,
301 .domain = DOMAIN_VECTORS,
302 },
303 [MT_MEMORY_RWX] = {
304 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
305 .prot_l1 = PMD_TYPE_TABLE,
306 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
307 .domain = DOMAIN_KERNEL,
308 },
309 [MT_MEMORY_RW] = {
310 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
311 L_PTE_XN,
312 .prot_l1 = PMD_TYPE_TABLE,
313 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
314 .domain = DOMAIN_KERNEL,
315 },
316 [MT_ROM] = {
317 .prot_sect = PMD_TYPE_SECT,
318 .domain = DOMAIN_KERNEL,
319 },
320 [MT_MEMORY_RWX_NONCACHED] = {
321 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
322 L_PTE_MT_BUFFERABLE,
323 .prot_l1 = PMD_TYPE_TABLE,
324 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
325 .domain = DOMAIN_KERNEL,
326 },
327 [MT_MEMORY_RW_DTCM] = {
328 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
329 L_PTE_XN,
330 .prot_l1 = PMD_TYPE_TABLE,
331 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
332 .domain = DOMAIN_KERNEL,
333 },
334 [MT_MEMORY_RWX_ITCM] = {
335 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
336 .prot_l1 = PMD_TYPE_TABLE,
337 .domain = DOMAIN_KERNEL,
338 },
339 [MT_MEMORY_RW_SO] = {
340 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
341 L_PTE_MT_UNCACHED | L_PTE_XN,
342 .prot_l1 = PMD_TYPE_TABLE,
343 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
344 PMD_SECT_UNCACHED | PMD_SECT_XN,
345 .domain = DOMAIN_KERNEL,
346 },
347 [MT_MEMORY_DMA_READY] = {
348 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
349 L_PTE_XN,
350 .prot_l1 = PMD_TYPE_TABLE,
351 .domain = DOMAIN_KERNEL,
352 },
353};
354
355const struct mem_type *get_mem_type(unsigned int type)
356{
357 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
358}
359EXPORT_SYMBOL(get_mem_type);
360
361static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr);
362
363static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS]
364 __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata;
365
366static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr)
367{
368 return &bm_pte[pte_index(addr)];
369}
370
371static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr)
372{
373 return pte_offset_kernel(dir, addr);
374}
375
376static inline pmd_t * __init fixmap_pmd(unsigned long addr)
377{
378 pgd_t *pgd = pgd_offset_k(addr);
379 pud_t *pud = pud_offset(pgd, addr);
380 pmd_t *pmd = pmd_offset(pud, addr);
381
382 return pmd;
383}
384
385void __init early_fixmap_init(void)
386{
387 pmd_t *pmd;
388
389 /*
390 * The early fixmap range spans multiple pmds, for which
391 * we are not prepared:
392 */
393 BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT)
394 != FIXADDR_TOP >> PMD_SHIFT);
395
396 pmd = fixmap_pmd(FIXADDR_TOP);
397 pmd_populate_kernel(&init_mm, pmd, bm_pte);
398
399 pte_offset_fixmap = pte_offset_early_fixmap;
400}
401
402/*
403 * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range().
404 * As a result, this can only be called with preemption disabled, as under
405 * stop_machine().
406 */
407void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
408{
409 unsigned long vaddr = __fix_to_virt(idx);
410 pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr);
411
412 /* Make sure fixmap region does not exceed available allocation. */
413 BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) >
414 FIXADDR_END);
415 BUG_ON(idx >= __end_of_fixed_addresses);
416
417 if (pgprot_val(prot))
418 set_pte_at(NULL, vaddr, pte,
419 pfn_pte(phys >> PAGE_SHIFT, prot));
420 else
421 pte_clear(NULL, vaddr, pte);
422 local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
423}
424
425/*
426 * Adjust the PMD section entries according to the CPU in use.
427 */
428static void __init build_mem_type_table(void)
429{
430 struct cachepolicy *cp;
431 unsigned int cr = get_cr();
432 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
433 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
434 int cpu_arch = cpu_architecture();
435 int i;
436
437 if (cpu_arch < CPU_ARCH_ARMv6) {
438#if defined(CONFIG_CPU_DCACHE_DISABLE)
439 if (cachepolicy > CPOLICY_BUFFERED)
440 cachepolicy = CPOLICY_BUFFERED;
441#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
442 if (cachepolicy > CPOLICY_WRITETHROUGH)
443 cachepolicy = CPOLICY_WRITETHROUGH;
444#endif
445 }
446 if (cpu_arch < CPU_ARCH_ARMv5) {
447 if (cachepolicy >= CPOLICY_WRITEALLOC)
448 cachepolicy = CPOLICY_WRITEBACK;
449 ecc_mask = 0;
450 }
451
452 if (is_smp()) {
453 if (cachepolicy != CPOLICY_WRITEALLOC) {
454 pr_warn("Forcing write-allocate cache policy for SMP\n");
455 cachepolicy = CPOLICY_WRITEALLOC;
456 }
457 if (!(initial_pmd_value & PMD_SECT_S)) {
458 pr_warn("Forcing shared mappings for SMP\n");
459 initial_pmd_value |= PMD_SECT_S;
460 }
461 }
462
463 /*
464 * Strip out features not present on earlier architectures.
465 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
466 * without extended page tables don't have the 'Shared' bit.
467 */
468 if (cpu_arch < CPU_ARCH_ARMv5)
469 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
470 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
471 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
472 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
473 mem_types[i].prot_sect &= ~PMD_SECT_S;
474
475 /*
476 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
477 * "update-able on write" bit on ARM610). However, Xscale and
478 * Xscale3 require this bit to be cleared.
479 */
480 if (cpu_is_xscale_family()) {
481 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
482 mem_types[i].prot_sect &= ~PMD_BIT4;
483 mem_types[i].prot_l1 &= ~PMD_BIT4;
484 }
485 } else if (cpu_arch < CPU_ARCH_ARMv6) {
486 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
487 if (mem_types[i].prot_l1)
488 mem_types[i].prot_l1 |= PMD_BIT4;
489 if (mem_types[i].prot_sect)
490 mem_types[i].prot_sect |= PMD_BIT4;
491 }
492 }
493
494 /*
495 * Mark the device areas according to the CPU/architecture.
496 */
497 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
498 if (!cpu_is_xsc3()) {
499 /*
500 * Mark device regions on ARMv6+ as execute-never
501 * to prevent speculative instruction fetches.
502 */
503 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
504 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
505 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
506 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
507
508 /* Also setup NX memory mapping */
509 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
510 }
511 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
512 /*
513 * For ARMv7 with TEX remapping,
514 * - shared device is SXCB=1100
515 * - nonshared device is SXCB=0100
516 * - write combine device mem is SXCB=0001
517 * (Uncached Normal memory)
518 */
519 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
520 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
521 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
522 } else if (cpu_is_xsc3()) {
523 /*
524 * For Xscale3,
525 * - shared device is TEXCB=00101
526 * - nonshared device is TEXCB=01000
527 * - write combine device mem is TEXCB=00100
528 * (Inner/Outer Uncacheable in xsc3 parlance)
529 */
530 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
531 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
532 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
533 } else {
534 /*
535 * For ARMv6 and ARMv7 without TEX remapping,
536 * - shared device is TEXCB=00001
537 * - nonshared device is TEXCB=01000
538 * - write combine device mem is TEXCB=00100
539 * (Uncached Normal in ARMv6 parlance).
540 */
541 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
542 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
543 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
544 }
545 } else {
546 /*
547 * On others, write combining is "Uncached/Buffered"
548 */
549 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
550 }
551
552 /*
553 * Now deal with the memory-type mappings
554 */
555 cp = &cache_policies[cachepolicy];
556 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
557 s2_pgprot = cp->pte_s2;
558 hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
559 s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
560
561#ifndef CONFIG_ARM_LPAE
562 /*
563 * We don't use domains on ARMv6 (since this causes problems with
564 * v6/v7 kernels), so we must use a separate memory type for user
565 * r/o, kernel r/w to map the vectors page.
566 */
567 if (cpu_arch == CPU_ARCH_ARMv6)
568 vecs_pgprot |= L_PTE_MT_VECTORS;
569
570 /*
571 * Check is it with support for the PXN bit
572 * in the Short-descriptor translation table format descriptors.
573 */
574 if (cpu_arch == CPU_ARCH_ARMv7 &&
575 (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) {
576 user_pmd_table |= PMD_PXNTABLE;
577 }
578#endif
579
580 /*
581 * ARMv6 and above have extended page tables.
582 */
583 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
584#ifndef CONFIG_ARM_LPAE
585 /*
586 * Mark cache clean areas and XIP ROM read only
587 * from SVC mode and no access from userspace.
588 */
589 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
590 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
591 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
592#endif
593
594 /*
595 * If the initial page tables were created with the S bit
596 * set, then we need to do the same here for the same
597 * reasons given in early_cachepolicy().
598 */
599 if (initial_pmd_value & PMD_SECT_S) {
600 user_pgprot |= L_PTE_SHARED;
601 kern_pgprot |= L_PTE_SHARED;
602 vecs_pgprot |= L_PTE_SHARED;
603 s2_pgprot |= L_PTE_SHARED;
604 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
605 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
606 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
607 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
608 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
609 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
610 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
611 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
612 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
613 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
614 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
615 }
616 }
617
618 /*
619 * Non-cacheable Normal - intended for memory areas that must
620 * not cause dirty cache line writebacks when used
621 */
622 if (cpu_arch >= CPU_ARCH_ARMv6) {
623 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
624 /* Non-cacheable Normal is XCB = 001 */
625 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
626 PMD_SECT_BUFFERED;
627 } else {
628 /* For both ARMv6 and non-TEX-remapping ARMv7 */
629 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
630 PMD_SECT_TEX(1);
631 }
632 } else {
633 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
634 }
635
636#ifdef CONFIG_ARM_LPAE
637 /*
638 * Do not generate access flag faults for the kernel mappings.
639 */
640 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
641 mem_types[i].prot_pte |= PTE_EXT_AF;
642 if (mem_types[i].prot_sect)
643 mem_types[i].prot_sect |= PMD_SECT_AF;
644 }
645 kern_pgprot |= PTE_EXT_AF;
646 vecs_pgprot |= PTE_EXT_AF;
647
648 /*
649 * Set PXN for user mappings
650 */
651 user_pgprot |= PTE_EXT_PXN;
652#endif
653
654 for (i = 0; i < 16; i++) {
655 pteval_t v = pgprot_val(protection_map[i]);
656 protection_map[i] = __pgprot(v | user_pgprot);
657 }
658
659 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
660 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
661
662 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
663 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
664 L_PTE_DIRTY | kern_pgprot);
665 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
666 pgprot_s2_device = __pgprot(s2_device_pgprot);
667 pgprot_hyp_device = __pgprot(hyp_device_pgprot);
668
669 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
670 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
671 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
672 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
673 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
674 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
675 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
676 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
677 mem_types[MT_ROM].prot_sect |= cp->pmd;
678
679 switch (cp->pmd) {
680 case PMD_SECT_WT:
681 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
682 break;
683 case PMD_SECT_WB:
684 case PMD_SECT_WBWA:
685 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
686 break;
687 }
688 pr_info("Memory policy: %sData cache %s\n",
689 ecc_mask ? "ECC enabled, " : "", cp->policy);
690
691 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
692 struct mem_type *t = &mem_types[i];
693 if (t->prot_l1)
694 t->prot_l1 |= PMD_DOMAIN(t->domain);
695 if (t->prot_sect)
696 t->prot_sect |= PMD_DOMAIN(t->domain);
697 }
698}
699
700#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
701pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
702 unsigned long size, pgprot_t vma_prot)
703{
704 if (!pfn_valid(pfn))
705 return pgprot_noncached(vma_prot);
706 else if (file->f_flags & O_SYNC)
707 return pgprot_writecombine(vma_prot);
708 return vma_prot;
709}
710EXPORT_SYMBOL(phys_mem_access_prot);
711#endif
712
713#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
714
715static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
716{
717 void *ptr = __va(memblock_alloc(sz, align));
718 memset(ptr, 0, sz);
719 return ptr;
720}
721
722static void __init *early_alloc(unsigned long sz)
723{
724 return early_alloc_aligned(sz, sz);
725}
726
727static void *__init late_alloc(unsigned long sz)
728{
729 void *ptr = (void *)__get_free_pages(PGALLOC_GFP, get_order(sz));
730
731 BUG_ON(!ptr);
732 return ptr;
733}
734
735static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr,
736 unsigned long prot,
737 void *(*alloc)(unsigned long sz))
738{
739 if (pmd_none(*pmd)) {
740 pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
741 __pmd_populate(pmd, __pa(pte), prot);
742 }
743 BUG_ON(pmd_bad(*pmd));
744 return pte_offset_kernel(pmd, addr);
745}
746
747static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr,
748 unsigned long prot)
749{
750 return arm_pte_alloc(pmd, addr, prot, early_alloc);
751}
752
753static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
754 unsigned long end, unsigned long pfn,
755 const struct mem_type *type,
756 void *(*alloc)(unsigned long sz),
757 bool ng)
758{
759 pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc);
760 do {
761 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
762 ng ? PTE_EXT_NG : 0);
763 pfn++;
764 } while (pte++, addr += PAGE_SIZE, addr != end);
765}
766
767static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
768 unsigned long end, phys_addr_t phys,
769 const struct mem_type *type, bool ng)
770{
771 pmd_t *p = pmd;
772
773#ifndef CONFIG_ARM_LPAE
774 /*
775 * In classic MMU format, puds and pmds are folded in to
776 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
777 * group of L1 entries making up one logical pointer to
778 * an L2 table (2MB), where as PMDs refer to the individual
779 * L1 entries (1MB). Hence increment to get the correct
780 * offset for odd 1MB sections.
781 * (See arch/arm/include/asm/pgtable-2level.h)
782 */
783 if (addr & SECTION_SIZE)
784 pmd++;
785#endif
786 do {
787 *pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0));
788 phys += SECTION_SIZE;
789 } while (pmd++, addr += SECTION_SIZE, addr != end);
790
791 flush_pmd_entry(p);
792}
793
794static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
795 unsigned long end, phys_addr_t phys,
796 const struct mem_type *type,
797 void *(*alloc)(unsigned long sz), bool ng)
798{
799 pmd_t *pmd = pmd_offset(pud, addr);
800 unsigned long next;
801
802 do {
803 /*
804 * With LPAE, we must loop over to map
805 * all the pmds for the given range.
806 */
807 next = pmd_addr_end(addr, end);
808
809 /*
810 * Try a section mapping - addr, next and phys must all be
811 * aligned to a section boundary.
812 */
813 if (type->prot_sect &&
814 ((addr | next | phys) & ~SECTION_MASK) == 0) {
815 __map_init_section(pmd, addr, next, phys, type, ng);
816 } else {
817 alloc_init_pte(pmd, addr, next,
818 __phys_to_pfn(phys), type, alloc, ng);
819 }
820
821 phys += next - addr;
822
823 } while (pmd++, addr = next, addr != end);
824}
825
826static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
827 unsigned long end, phys_addr_t phys,
828 const struct mem_type *type,
829 void *(*alloc)(unsigned long sz), bool ng)
830{
831 pud_t *pud = pud_offset(pgd, addr);
832 unsigned long next;
833
834 do {
835 next = pud_addr_end(addr, end);
836 alloc_init_pmd(pud, addr, next, phys, type, alloc, ng);
837 phys += next - addr;
838 } while (pud++, addr = next, addr != end);
839}
840
841#ifndef CONFIG_ARM_LPAE
842static void __init create_36bit_mapping(struct mm_struct *mm,
843 struct map_desc *md,
844 const struct mem_type *type,
845 bool ng)
846{
847 unsigned long addr, length, end;
848 phys_addr_t phys;
849 pgd_t *pgd;
850
851 addr = md->virtual;
852 phys = __pfn_to_phys(md->pfn);
853 length = PAGE_ALIGN(md->length);
854
855 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
856 pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n",
857 (long long)__pfn_to_phys((u64)md->pfn), addr);
858 return;
859 }
860
861 /* N.B. ARMv6 supersections are only defined to work with domain 0.
862 * Since domain assignments can in fact be arbitrary, the
863 * 'domain == 0' check below is required to insure that ARMv6
864 * supersections are only allocated for domain 0 regardless
865 * of the actual domain assignments in use.
866 */
867 if (type->domain) {
868 pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n",
869 (long long)__pfn_to_phys((u64)md->pfn), addr);
870 return;
871 }
872
873 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
874 pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n",
875 (long long)__pfn_to_phys((u64)md->pfn), addr);
876 return;
877 }
878
879 /*
880 * Shift bits [35:32] of address into bits [23:20] of PMD
881 * (See ARMv6 spec).
882 */
883 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
884
885 pgd = pgd_offset(mm, addr);
886 end = addr + length;
887 do {
888 pud_t *pud = pud_offset(pgd, addr);
889 pmd_t *pmd = pmd_offset(pud, addr);
890 int i;
891
892 for (i = 0; i < 16; i++)
893 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER |
894 (ng ? PMD_SECT_nG : 0));
895
896 addr += SUPERSECTION_SIZE;
897 phys += SUPERSECTION_SIZE;
898 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
899 } while (addr != end);
900}
901#endif /* !CONFIG_ARM_LPAE */
902
903static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md,
904 void *(*alloc)(unsigned long sz),
905 bool ng)
906{
907 unsigned long addr, length, end;
908 phys_addr_t phys;
909 const struct mem_type *type;
910 pgd_t *pgd;
911
912 type = &mem_types[md->type];
913
914#ifndef CONFIG_ARM_LPAE
915 /*
916 * Catch 36-bit addresses
917 */
918 if (md->pfn >= 0x100000) {
919 create_36bit_mapping(mm, md, type, ng);
920 return;
921 }
922#endif
923
924 addr = md->virtual & PAGE_MASK;
925 phys = __pfn_to_phys(md->pfn);
926 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
927
928 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
929 pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n",
930 (long long)__pfn_to_phys(md->pfn), addr);
931 return;
932 }
933
934 pgd = pgd_offset(mm, addr);
935 end = addr + length;
936 do {
937 unsigned long next = pgd_addr_end(addr, end);
938
939 alloc_init_pud(pgd, addr, next, phys, type, alloc, ng);
940
941 phys += next - addr;
942 addr = next;
943 } while (pgd++, addr != end);
944}
945
946/*
947 * Create the page directory entries and any necessary
948 * page tables for the mapping specified by `md'. We
949 * are able to cope here with varying sizes and address
950 * offsets, and we take full advantage of sections and
951 * supersections.
952 */
953static void __init create_mapping(struct map_desc *md)
954{
955 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
956 pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n",
957 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
958 return;
959 }
960
961 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
962 md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START &&
963 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
964 pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n",
965 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
966 }
967
968 __create_mapping(&init_mm, md, early_alloc, false);
969}
970
971void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md,
972 bool ng)
973{
974#ifdef CONFIG_ARM_LPAE
975 pud_t *pud = pud_alloc(mm, pgd_offset(mm, md->virtual), md->virtual);
976 if (WARN_ON(!pud))
977 return;
978 pmd_alloc(mm, pud, 0);
979#endif
980 __create_mapping(mm, md, late_alloc, ng);
981}
982
983/*
984 * Create the architecture specific mappings
985 */
986void __init iotable_init(struct map_desc *io_desc, int nr)
987{
988 struct map_desc *md;
989 struct vm_struct *vm;
990 struct static_vm *svm;
991
992 if (!nr)
993 return;
994
995 svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
996
997 for (md = io_desc; nr; md++, nr--) {
998 create_mapping(md);
999
1000 vm = &svm->vm;
1001 vm->addr = (void *)(md->virtual & PAGE_MASK);
1002 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
1003 vm->phys_addr = __pfn_to_phys(md->pfn);
1004 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
1005 vm->flags |= VM_ARM_MTYPE(md->type);
1006 vm->caller = iotable_init;
1007 add_static_vm_early(svm++);
1008 }
1009}
1010
1011void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
1012 void *caller)
1013{
1014 struct vm_struct *vm;
1015 struct static_vm *svm;
1016
1017 svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
1018
1019 vm = &svm->vm;
1020 vm->addr = (void *)addr;
1021 vm->size = size;
1022 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
1023 vm->caller = caller;
1024 add_static_vm_early(svm);
1025}
1026
1027#ifndef CONFIG_ARM_LPAE
1028
1029/*
1030 * The Linux PMD is made of two consecutive section entries covering 2MB
1031 * (see definition in include/asm/pgtable-2level.h). However a call to
1032 * create_mapping() may optimize static mappings by using individual
1033 * 1MB section mappings. This leaves the actual PMD potentially half
1034 * initialized if the top or bottom section entry isn't used, leaving it
1035 * open to problems if a subsequent ioremap() or vmalloc() tries to use
1036 * the virtual space left free by that unused section entry.
1037 *
1038 * Let's avoid the issue by inserting dummy vm entries covering the unused
1039 * PMD halves once the static mappings are in place.
1040 */
1041
1042static void __init pmd_empty_section_gap(unsigned long addr)
1043{
1044 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
1045}
1046
1047static void __init fill_pmd_gaps(void)
1048{
1049 struct static_vm *svm;
1050 struct vm_struct *vm;
1051 unsigned long addr, next = 0;
1052 pmd_t *pmd;
1053
1054 list_for_each_entry(svm, &static_vmlist, list) {
1055 vm = &svm->vm;
1056 addr = (unsigned long)vm->addr;
1057 if (addr < next)
1058 continue;
1059
1060 /*
1061 * Check if this vm starts on an odd section boundary.
1062 * If so and the first section entry for this PMD is free
1063 * then we block the corresponding virtual address.
1064 */
1065 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1066 pmd = pmd_off_k(addr);
1067 if (pmd_none(*pmd))
1068 pmd_empty_section_gap(addr & PMD_MASK);
1069 }
1070
1071 /*
1072 * Then check if this vm ends on an odd section boundary.
1073 * If so and the second section entry for this PMD is empty
1074 * then we block the corresponding virtual address.
1075 */
1076 addr += vm->size;
1077 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1078 pmd = pmd_off_k(addr) + 1;
1079 if (pmd_none(*pmd))
1080 pmd_empty_section_gap(addr);
1081 }
1082
1083 /* no need to look at any vm entry until we hit the next PMD */
1084 next = (addr + PMD_SIZE - 1) & PMD_MASK;
1085 }
1086}
1087
1088#else
1089#define fill_pmd_gaps() do { } while (0)
1090#endif
1091
1092#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
1093static void __init pci_reserve_io(void)
1094{
1095 struct static_vm *svm;
1096
1097 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1098 if (svm)
1099 return;
1100
1101 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1102}
1103#else
1104#define pci_reserve_io() do { } while (0)
1105#endif
1106
1107#ifdef CONFIG_DEBUG_LL
1108void __init debug_ll_io_init(void)
1109{
1110 struct map_desc map;
1111
1112 debug_ll_addr(&map.pfn, &map.virtual);
1113 if (!map.pfn || !map.virtual)
1114 return;
1115 map.pfn = __phys_to_pfn(map.pfn);
1116 map.virtual &= PAGE_MASK;
1117 map.length = PAGE_SIZE;
1118 map.type = MT_DEVICE;
1119 iotable_init(&map, 1);
1120}
1121#endif
1122
1123static void * __initdata vmalloc_min =
1124 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
1125
1126/*
1127 * vmalloc=size forces the vmalloc area to be exactly 'size'
1128 * bytes. This can be used to increase (or decrease) the vmalloc
1129 * area - the default is 240m.
1130 */
1131static int __init early_vmalloc(char *arg)
1132{
1133 unsigned long vmalloc_reserve = memparse(arg, NULL);
1134
1135 if (vmalloc_reserve < SZ_16M) {
1136 vmalloc_reserve = SZ_16M;
1137 pr_warn("vmalloc area too small, limiting to %luMB\n",
1138 vmalloc_reserve >> 20);
1139 }
1140
1141 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
1142 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
1143 pr_warn("vmalloc area is too big, limiting to %luMB\n",
1144 vmalloc_reserve >> 20);
1145 }
1146
1147 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
1148 return 0;
1149}
1150early_param("vmalloc", early_vmalloc);
1151
1152phys_addr_t arm_lowmem_limit __initdata = 0;
1153
1154void __init sanity_check_meminfo(void)
1155{
1156 phys_addr_t memblock_limit = 0;
1157 int highmem = 0;
1158 phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
1159 struct memblock_region *reg;
1160 bool should_use_highmem = false;
1161
1162 for_each_memblock(memory, reg) {
1163 phys_addr_t block_start = reg->base;
1164 phys_addr_t block_end = reg->base + reg->size;
1165 phys_addr_t size_limit = reg->size;
1166
1167 if (reg->base >= vmalloc_limit)
1168 highmem = 1;
1169 else
1170 size_limit = vmalloc_limit - reg->base;
1171
1172
1173 if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
1174
1175 if (highmem) {
1176 pr_notice("Ignoring RAM at %pa-%pa (!CONFIG_HIGHMEM)\n",
1177 &block_start, &block_end);
1178 memblock_remove(reg->base, reg->size);
1179 should_use_highmem = true;
1180 continue;
1181 }
1182
1183 if (reg->size > size_limit) {
1184 phys_addr_t overlap_size = reg->size - size_limit;
1185
1186 pr_notice("Truncating RAM at %pa-%pa to -%pa",
1187 &block_start, &block_end, &vmalloc_limit);
1188 memblock_remove(vmalloc_limit, overlap_size);
1189 block_end = vmalloc_limit;
1190 should_use_highmem = true;
1191 }
1192 }
1193
1194 if (!highmem) {
1195 if (block_end > arm_lowmem_limit) {
1196 if (reg->size > size_limit)
1197 arm_lowmem_limit = vmalloc_limit;
1198 else
1199 arm_lowmem_limit = block_end;
1200 }
1201
1202 /*
1203 * Find the first non-pmd-aligned page, and point
1204 * memblock_limit at it. This relies on rounding the
1205 * limit down to be pmd-aligned, which happens at the
1206 * end of this function.
1207 *
1208 * With this algorithm, the start or end of almost any
1209 * bank can be non-pmd-aligned. The only exception is
1210 * that the start of the bank 0 must be section-
1211 * aligned, since otherwise memory would need to be
1212 * allocated when mapping the start of bank 0, which
1213 * occurs before any free memory is mapped.
1214 */
1215 if (!memblock_limit) {
1216 if (!IS_ALIGNED(block_start, PMD_SIZE))
1217 memblock_limit = block_start;
1218 else if (!IS_ALIGNED(block_end, PMD_SIZE))
1219 memblock_limit = arm_lowmem_limit;
1220 }
1221
1222 }
1223 }
1224
1225 if (should_use_highmem)
1226 pr_notice("Consider using a HIGHMEM enabled kernel.\n");
1227
1228 high_memory = __va(arm_lowmem_limit - 1) + 1;
1229
1230 /*
1231 * Round the memblock limit down to a pmd size. This
1232 * helps to ensure that we will allocate memory from the
1233 * last full pmd, which should be mapped.
1234 */
1235 if (memblock_limit)
1236 memblock_limit = round_down(memblock_limit, PMD_SIZE);
1237 if (!memblock_limit)
1238 memblock_limit = arm_lowmem_limit;
1239
1240 memblock_set_current_limit(memblock_limit);
1241}
1242
1243static inline void prepare_page_table(void)
1244{
1245 unsigned long addr;
1246 phys_addr_t end;
1247
1248 /*
1249 * Clear out all the mappings below the kernel image.
1250 */
1251 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1252 pmd_clear(pmd_off_k(addr));
1253
1254#ifdef CONFIG_XIP_KERNEL
1255 /* The XIP kernel is mapped in the module area -- skip over it */
1256 addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK;
1257#endif
1258 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1259 pmd_clear(pmd_off_k(addr));
1260
1261 /*
1262 * Find the end of the first block of lowmem.
1263 */
1264 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1265 if (end >= arm_lowmem_limit)
1266 end = arm_lowmem_limit;
1267
1268 /*
1269 * Clear out all the kernel space mappings, except for the first
1270 * memory bank, up to the vmalloc region.
1271 */
1272 for (addr = __phys_to_virt(end);
1273 addr < VMALLOC_START; addr += PMD_SIZE)
1274 pmd_clear(pmd_off_k(addr));
1275}
1276
1277#ifdef CONFIG_ARM_LPAE
1278/* the first page is reserved for pgd */
1279#define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1280 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1281#else
1282#define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1283#endif
1284
1285/*
1286 * Reserve the special regions of memory
1287 */
1288void __init arm_mm_memblock_reserve(void)
1289{
1290 /*
1291 * Reserve the page tables. These are already in use,
1292 * and can only be in node 0.
1293 */
1294 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1295
1296#ifdef CONFIG_SA1111
1297 /*
1298 * Because of the SA1111 DMA bug, we want to preserve our
1299 * precious DMA-able memory...
1300 */
1301 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1302#endif
1303}
1304
1305/*
1306 * Set up the device mappings. Since we clear out the page tables for all
1307 * mappings above VMALLOC_START, except early fixmap, we might remove debug
1308 * device mappings. This means earlycon can be used to debug this function
1309 * Any other function or debugging method which may touch any device _will_
1310 * crash the kernel.
1311 */
1312static void __init devicemaps_init(const struct machine_desc *mdesc)
1313{
1314 struct map_desc map;
1315 unsigned long addr;
1316 void *vectors;
1317
1318 /*
1319 * Allocate the vector page early.
1320 */
1321 vectors = early_alloc(PAGE_SIZE * 2);
1322
1323 early_trap_init(vectors);
1324
1325 /*
1326 * Clear page table except top pmd used by early fixmaps
1327 */
1328 for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE)
1329 pmd_clear(pmd_off_k(addr));
1330
1331 /*
1332 * Map the kernel if it is XIP.
1333 * It is always first in the modulearea.
1334 */
1335#ifdef CONFIG_XIP_KERNEL
1336 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1337 map.virtual = MODULES_VADDR;
1338 map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1339 map.type = MT_ROM;
1340 create_mapping(&map);
1341#endif
1342
1343 /*
1344 * Map the cache flushing regions.
1345 */
1346#ifdef FLUSH_BASE
1347 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1348 map.virtual = FLUSH_BASE;
1349 map.length = SZ_1M;
1350 map.type = MT_CACHECLEAN;
1351 create_mapping(&map);
1352#endif
1353#ifdef FLUSH_BASE_MINICACHE
1354 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1355 map.virtual = FLUSH_BASE_MINICACHE;
1356 map.length = SZ_1M;
1357 map.type = MT_MINICLEAN;
1358 create_mapping(&map);
1359#endif
1360
1361 /*
1362 * Create a mapping for the machine vectors at the high-vectors
1363 * location (0xffff0000). If we aren't using high-vectors, also
1364 * create a mapping at the low-vectors virtual address.
1365 */
1366 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1367 map.virtual = 0xffff0000;
1368 map.length = PAGE_SIZE;
1369#ifdef CONFIG_KUSER_HELPERS
1370 map.type = MT_HIGH_VECTORS;
1371#else
1372 map.type = MT_LOW_VECTORS;
1373#endif
1374 create_mapping(&map);
1375
1376 if (!vectors_high()) {
1377 map.virtual = 0;
1378 map.length = PAGE_SIZE * 2;
1379 map.type = MT_LOW_VECTORS;
1380 create_mapping(&map);
1381 }
1382
1383 /* Now create a kernel read-only mapping */
1384 map.pfn += 1;
1385 map.virtual = 0xffff0000 + PAGE_SIZE;
1386 map.length = PAGE_SIZE;
1387 map.type = MT_LOW_VECTORS;
1388 create_mapping(&map);
1389
1390 /*
1391 * Ask the machine support to map in the statically mapped devices.
1392 */
1393 if (mdesc->map_io)
1394 mdesc->map_io();
1395 else
1396 debug_ll_io_init();
1397 fill_pmd_gaps();
1398
1399 /* Reserve fixed i/o space in VMALLOC region */
1400 pci_reserve_io();
1401
1402 /*
1403 * Finally flush the caches and tlb to ensure that we're in a
1404 * consistent state wrt the writebuffer. This also ensures that
1405 * any write-allocated cache lines in the vector page are written
1406 * back. After this point, we can start to touch devices again.
1407 */
1408 local_flush_tlb_all();
1409 flush_cache_all();
1410
1411 /* Enable asynchronous aborts */
1412 early_abt_enable();
1413}
1414
1415static void __init kmap_init(void)
1416{
1417#ifdef CONFIG_HIGHMEM
1418 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1419 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1420#endif
1421
1422 early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START,
1423 _PAGE_KERNEL_TABLE);
1424}
1425
1426static void __init map_lowmem(void)
1427{
1428 struct memblock_region *reg;
1429#ifdef CONFIG_XIP_KERNEL
1430 phys_addr_t kernel_x_start = round_down(__pa(_sdata), SECTION_SIZE);
1431#else
1432 phys_addr_t kernel_x_start = round_down(__pa(_stext), SECTION_SIZE);
1433#endif
1434 phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1435
1436 /* Map all the lowmem memory banks. */
1437 for_each_memblock(memory, reg) {
1438 phys_addr_t start = reg->base;
1439 phys_addr_t end = start + reg->size;
1440 struct map_desc map;
1441
1442 if (memblock_is_nomap(reg))
1443 continue;
1444
1445 if (end > arm_lowmem_limit)
1446 end = arm_lowmem_limit;
1447 if (start >= end)
1448 break;
1449
1450 if (end < kernel_x_start) {
1451 map.pfn = __phys_to_pfn(start);
1452 map.virtual = __phys_to_virt(start);
1453 map.length = end - start;
1454 map.type = MT_MEMORY_RWX;
1455
1456 create_mapping(&map);
1457 } else if (start >= kernel_x_end) {
1458 map.pfn = __phys_to_pfn(start);
1459 map.virtual = __phys_to_virt(start);
1460 map.length = end - start;
1461 map.type = MT_MEMORY_RW;
1462
1463 create_mapping(&map);
1464 } else {
1465 /* This better cover the entire kernel */
1466 if (start < kernel_x_start) {
1467 map.pfn = __phys_to_pfn(start);
1468 map.virtual = __phys_to_virt(start);
1469 map.length = kernel_x_start - start;
1470 map.type = MT_MEMORY_RW;
1471
1472 create_mapping(&map);
1473 }
1474
1475 map.pfn = __phys_to_pfn(kernel_x_start);
1476 map.virtual = __phys_to_virt(kernel_x_start);
1477 map.length = kernel_x_end - kernel_x_start;
1478 map.type = MT_MEMORY_RWX;
1479
1480 create_mapping(&map);
1481
1482 if (kernel_x_end < end) {
1483 map.pfn = __phys_to_pfn(kernel_x_end);
1484 map.virtual = __phys_to_virt(kernel_x_end);
1485 map.length = end - kernel_x_end;
1486 map.type = MT_MEMORY_RW;
1487
1488 create_mapping(&map);
1489 }
1490 }
1491 }
1492}
1493
1494#ifdef CONFIG_ARM_PV_FIXUP
1495extern unsigned long __atags_pointer;
1496typedef void pgtables_remap(long long offset, unsigned long pgd, void *bdata);
1497pgtables_remap lpae_pgtables_remap_asm;
1498
1499/*
1500 * early_paging_init() recreates boot time page table setup, allowing machines
1501 * to switch over to a high (>4G) address space on LPAE systems
1502 */
1503void __init early_paging_init(const struct machine_desc *mdesc)
1504{
1505 pgtables_remap *lpae_pgtables_remap;
1506 unsigned long pa_pgd;
1507 unsigned int cr, ttbcr;
1508 long long offset;
1509 void *boot_data;
1510
1511 if (!mdesc->pv_fixup)
1512 return;
1513
1514 offset = mdesc->pv_fixup();
1515 if (offset == 0)
1516 return;
1517
1518 /*
1519 * Get the address of the remap function in the 1:1 identity
1520 * mapping setup by the early page table assembly code. We
1521 * must get this prior to the pv update. The following barrier
1522 * ensures that this is complete before we fixup any P:V offsets.
1523 */
1524 lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm);
1525 pa_pgd = __pa(swapper_pg_dir);
1526 boot_data = __va(__atags_pointer);
1527 barrier();
1528
1529 pr_info("Switching physical address space to 0x%08llx\n",
1530 (u64)PHYS_OFFSET + offset);
1531
1532 /* Re-set the phys pfn offset, and the pv offset */
1533 __pv_offset += offset;
1534 __pv_phys_pfn_offset += PFN_DOWN(offset);
1535
1536 /* Run the patch stub to update the constants */
1537 fixup_pv_table(&__pv_table_begin,
1538 (&__pv_table_end - &__pv_table_begin) << 2);
1539
1540 /*
1541 * We changing not only the virtual to physical mapping, but also
1542 * the physical addresses used to access memory. We need to flush
1543 * all levels of cache in the system with caching disabled to
1544 * ensure that all data is written back, and nothing is prefetched
1545 * into the caches. We also need to prevent the TLB walkers
1546 * allocating into the caches too. Note that this is ARMv7 LPAE
1547 * specific.
1548 */
1549 cr = get_cr();
1550 set_cr(cr & ~(CR_I | CR_C));
1551 asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr));
1552 asm volatile("mcr p15, 0, %0, c2, c0, 2"
1553 : : "r" (ttbcr & ~(3 << 8 | 3 << 10)));
1554 flush_cache_all();
1555
1556 /*
1557 * Fixup the page tables - this must be in the idmap region as
1558 * we need to disable the MMU to do this safely, and hence it
1559 * needs to be assembly. It's fairly simple, as we're using the
1560 * temporary tables setup by the initial assembly code.
1561 */
1562 lpae_pgtables_remap(offset, pa_pgd, boot_data);
1563
1564 /* Re-enable the caches and cacheable TLB walks */
1565 asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr));
1566 set_cr(cr);
1567}
1568
1569#else
1570
1571void __init early_paging_init(const struct machine_desc *mdesc)
1572{
1573 long long offset;
1574
1575 if (!mdesc->pv_fixup)
1576 return;
1577
1578 offset = mdesc->pv_fixup();
1579 if (offset == 0)
1580 return;
1581
1582 pr_crit("Physical address space modification is only to support Keystone2.\n");
1583 pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n");
1584 pr_crit("feature. Your kernel may crash now, have a good day.\n");
1585 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1586}
1587
1588#endif
1589
1590static void __init early_fixmap_shutdown(void)
1591{
1592 int i;
1593 unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1);
1594
1595 pte_offset_fixmap = pte_offset_late_fixmap;
1596 pmd_clear(fixmap_pmd(va));
1597 local_flush_tlb_kernel_page(va);
1598
1599 for (i = 0; i < __end_of_permanent_fixed_addresses; i++) {
1600 pte_t *pte;
1601 struct map_desc map;
1602
1603 map.virtual = fix_to_virt(i);
1604 pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual);
1605
1606 /* Only i/o device mappings are supported ATM */
1607 if (pte_none(*pte) ||
1608 (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED)
1609 continue;
1610
1611 map.pfn = pte_pfn(*pte);
1612 map.type = MT_DEVICE;
1613 map.length = PAGE_SIZE;
1614
1615 create_mapping(&map);
1616 }
1617}
1618
1619/*
1620 * paging_init() sets up the page tables, initialises the zone memory
1621 * maps, and sets up the zero page, bad page and bad page tables.
1622 */
1623void __init paging_init(const struct machine_desc *mdesc)
1624{
1625 void *zero_page;
1626
1627 build_mem_type_table();
1628 prepare_page_table();
1629 map_lowmem();
1630 memblock_set_current_limit(arm_lowmem_limit);
1631 dma_contiguous_remap();
1632 early_fixmap_shutdown();
1633 devicemaps_init(mdesc);
1634 kmap_init();
1635 tcm_init();
1636
1637 top_pmd = pmd_off_k(0xffff0000);
1638
1639 /* allocate the zero page. */
1640 zero_page = early_alloc(PAGE_SIZE);
1641
1642 bootmem_init();
1643
1644 empty_zero_page = virt_to_page(zero_page);
1645 __flush_dcache_page(NULL, empty_zero_page);
1646}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mm/mmu.c
4 *
5 * Copyright (C) 1995-2005 Russell King
6 */
7#include <linux/module.h>
8#include <linux/kernel.h>
9#include <linux/errno.h>
10#include <linux/init.h>
11#include <linux/mman.h>
12#include <linux/nodemask.h>
13#include <linux/memblock.h>
14#include <linux/fs.h>
15#include <linux/vmalloc.h>
16#include <linux/sizes.h>
17
18#include <asm/cp15.h>
19#include <asm/cputype.h>
20#include <asm/sections.h>
21#include <asm/cachetype.h>
22#include <asm/fixmap.h>
23#include <asm/sections.h>
24#include <asm/setup.h>
25#include <asm/smp_plat.h>
26#include <asm/tlb.h>
27#include <asm/highmem.h>
28#include <asm/system_info.h>
29#include <asm/traps.h>
30#include <asm/procinfo.h>
31#include <asm/memory.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/pci.h>
36#include <asm/fixmap.h>
37
38#include "fault.h"
39#include "mm.h"
40#include "tcm.h"
41
42/*
43 * empty_zero_page is a special page that is used for
44 * zero-initialized data and COW.
45 */
46struct page *empty_zero_page;
47EXPORT_SYMBOL(empty_zero_page);
48
49/*
50 * The pmd table for the upper-most set of pages.
51 */
52pmd_t *top_pmd;
53
54pmdval_t user_pmd_table = _PAGE_USER_TABLE;
55
56#define CPOLICY_UNCACHED 0
57#define CPOLICY_BUFFERED 1
58#define CPOLICY_WRITETHROUGH 2
59#define CPOLICY_WRITEBACK 3
60#define CPOLICY_WRITEALLOC 4
61
62static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
63static unsigned int ecc_mask __initdata = 0;
64pgprot_t pgprot_user;
65pgprot_t pgprot_kernel;
66pgprot_t pgprot_hyp_device;
67pgprot_t pgprot_s2;
68pgprot_t pgprot_s2_device;
69
70EXPORT_SYMBOL(pgprot_user);
71EXPORT_SYMBOL(pgprot_kernel);
72
73struct cachepolicy {
74 const char policy[16];
75 unsigned int cr_mask;
76 pmdval_t pmd;
77 pteval_t pte;
78 pteval_t pte_s2;
79};
80
81#ifdef CONFIG_ARM_LPAE
82#define s2_policy(policy) policy
83#else
84#define s2_policy(policy) 0
85#endif
86
87unsigned long kimage_voffset __ro_after_init;
88
89static struct cachepolicy cache_policies[] __initdata = {
90 {
91 .policy = "uncached",
92 .cr_mask = CR_W|CR_C,
93 .pmd = PMD_SECT_UNCACHED,
94 .pte = L_PTE_MT_UNCACHED,
95 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
96 }, {
97 .policy = "buffered",
98 .cr_mask = CR_C,
99 .pmd = PMD_SECT_BUFFERED,
100 .pte = L_PTE_MT_BUFFERABLE,
101 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
102 }, {
103 .policy = "writethrough",
104 .cr_mask = 0,
105 .pmd = PMD_SECT_WT,
106 .pte = L_PTE_MT_WRITETHROUGH,
107 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
108 }, {
109 .policy = "writeback",
110 .cr_mask = 0,
111 .pmd = PMD_SECT_WB,
112 .pte = L_PTE_MT_WRITEBACK,
113 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
114 }, {
115 .policy = "writealloc",
116 .cr_mask = 0,
117 .pmd = PMD_SECT_WBWA,
118 .pte = L_PTE_MT_WRITEALLOC,
119 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
120 }
121};
122
123#ifdef CONFIG_CPU_CP15
124static unsigned long initial_pmd_value __initdata = 0;
125
126/*
127 * Initialise the cache_policy variable with the initial state specified
128 * via the "pmd" value. This is used to ensure that on ARMv6 and later,
129 * the C code sets the page tables up with the same policy as the head
130 * assembly code, which avoids an illegal state where the TLBs can get
131 * confused. See comments in early_cachepolicy() for more information.
132 */
133void __init init_default_cache_policy(unsigned long pmd)
134{
135 int i;
136
137 initial_pmd_value = pmd;
138
139 pmd &= PMD_SECT_CACHE_MASK;
140
141 for (i = 0; i < ARRAY_SIZE(cache_policies); i++)
142 if (cache_policies[i].pmd == pmd) {
143 cachepolicy = i;
144 break;
145 }
146
147 if (i == ARRAY_SIZE(cache_policies))
148 pr_err("ERROR: could not find cache policy\n");
149}
150
151/*
152 * These are useful for identifying cache coherency problems by allowing
153 * the cache or the cache and writebuffer to be turned off. (Note: the
154 * write buffer should not be on and the cache off).
155 */
156static int __init early_cachepolicy(char *p)
157{
158 int i, selected = -1;
159
160 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
161 int len = strlen(cache_policies[i].policy);
162
163 if (memcmp(p, cache_policies[i].policy, len) == 0) {
164 selected = i;
165 break;
166 }
167 }
168
169 if (selected == -1)
170 pr_err("ERROR: unknown or unsupported cache policy\n");
171
172 /*
173 * This restriction is partly to do with the way we boot; it is
174 * unpredictable to have memory mapped using two different sets of
175 * memory attributes (shared, type, and cache attribs). We can not
176 * change these attributes once the initial assembly has setup the
177 * page tables.
178 */
179 if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) {
180 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
181 cache_policies[cachepolicy].policy);
182 return 0;
183 }
184
185 if (selected != cachepolicy) {
186 unsigned long cr = __clear_cr(cache_policies[selected].cr_mask);
187 cachepolicy = selected;
188 flush_cache_all();
189 set_cr(cr);
190 }
191 return 0;
192}
193early_param("cachepolicy", early_cachepolicy);
194
195static int __init early_nocache(char *__unused)
196{
197 char *p = "buffered";
198 pr_warn("nocache is deprecated; use cachepolicy=%s\n", p);
199 early_cachepolicy(p);
200 return 0;
201}
202early_param("nocache", early_nocache);
203
204static int __init early_nowrite(char *__unused)
205{
206 char *p = "uncached";
207 pr_warn("nowb is deprecated; use cachepolicy=%s\n", p);
208 early_cachepolicy(p);
209 return 0;
210}
211early_param("nowb", early_nowrite);
212
213#ifndef CONFIG_ARM_LPAE
214static int __init early_ecc(char *p)
215{
216 if (memcmp(p, "on", 2) == 0)
217 ecc_mask = PMD_PROTECTION;
218 else if (memcmp(p, "off", 3) == 0)
219 ecc_mask = 0;
220 return 0;
221}
222early_param("ecc", early_ecc);
223#endif
224
225#else /* ifdef CONFIG_CPU_CP15 */
226
227static int __init early_cachepolicy(char *p)
228{
229 pr_warn("cachepolicy kernel parameter not supported without cp15\n");
230}
231early_param("cachepolicy", early_cachepolicy);
232
233static int __init noalign_setup(char *__unused)
234{
235 pr_warn("noalign kernel parameter not supported without cp15\n");
236}
237__setup("noalign", noalign_setup);
238
239#endif /* ifdef CONFIG_CPU_CP15 / else */
240
241#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
242#define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
243#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
244
245static struct mem_type mem_types[] __ro_after_init = {
246 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
247 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
248 L_PTE_SHARED,
249 .prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) |
250 s2_policy(L_PTE_S2_MT_DEV_SHARED) |
251 L_PTE_SHARED,
252 .prot_l1 = PMD_TYPE_TABLE,
253 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
254 .domain = DOMAIN_IO,
255 },
256 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
257 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
258 .prot_l1 = PMD_TYPE_TABLE,
259 .prot_sect = PROT_SECT_DEVICE,
260 .domain = DOMAIN_IO,
261 },
262 [MT_DEVICE_CACHED] = { /* ioremap_cached */
263 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
264 .prot_l1 = PMD_TYPE_TABLE,
265 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
266 .domain = DOMAIN_IO,
267 },
268 [MT_DEVICE_WC] = { /* ioremap_wc */
269 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
270 .prot_l1 = PMD_TYPE_TABLE,
271 .prot_sect = PROT_SECT_DEVICE,
272 .domain = DOMAIN_IO,
273 },
274 [MT_UNCACHED] = {
275 .prot_pte = PROT_PTE_DEVICE,
276 .prot_l1 = PMD_TYPE_TABLE,
277 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
278 .domain = DOMAIN_IO,
279 },
280 [MT_CACHECLEAN] = {
281 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
282 .domain = DOMAIN_KERNEL,
283 },
284#ifndef CONFIG_ARM_LPAE
285 [MT_MINICLEAN] = {
286 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
287 .domain = DOMAIN_KERNEL,
288 },
289#endif
290 [MT_LOW_VECTORS] = {
291 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
292 L_PTE_RDONLY,
293 .prot_l1 = PMD_TYPE_TABLE,
294 .domain = DOMAIN_VECTORS,
295 },
296 [MT_HIGH_VECTORS] = {
297 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
298 L_PTE_USER | L_PTE_RDONLY,
299 .prot_l1 = PMD_TYPE_TABLE,
300 .domain = DOMAIN_VECTORS,
301 },
302 [MT_MEMORY_RWX] = {
303 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
304 .prot_l1 = PMD_TYPE_TABLE,
305 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
306 .domain = DOMAIN_KERNEL,
307 },
308 [MT_MEMORY_RW] = {
309 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
310 L_PTE_XN,
311 .prot_l1 = PMD_TYPE_TABLE,
312 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
313 .domain = DOMAIN_KERNEL,
314 },
315 [MT_ROM] = {
316 .prot_sect = PMD_TYPE_SECT,
317 .domain = DOMAIN_KERNEL,
318 },
319 [MT_MEMORY_RWX_NONCACHED] = {
320 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
321 L_PTE_MT_BUFFERABLE,
322 .prot_l1 = PMD_TYPE_TABLE,
323 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
324 .domain = DOMAIN_KERNEL,
325 },
326 [MT_MEMORY_RW_DTCM] = {
327 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
328 L_PTE_XN,
329 .prot_l1 = PMD_TYPE_TABLE,
330 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
331 .domain = DOMAIN_KERNEL,
332 },
333 [MT_MEMORY_RWX_ITCM] = {
334 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
335 .prot_l1 = PMD_TYPE_TABLE,
336 .domain = DOMAIN_KERNEL,
337 },
338 [MT_MEMORY_RW_SO] = {
339 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
340 L_PTE_MT_UNCACHED | L_PTE_XN,
341 .prot_l1 = PMD_TYPE_TABLE,
342 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
343 PMD_SECT_UNCACHED | PMD_SECT_XN,
344 .domain = DOMAIN_KERNEL,
345 },
346 [MT_MEMORY_DMA_READY] = {
347 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
348 L_PTE_XN,
349 .prot_l1 = PMD_TYPE_TABLE,
350 .domain = DOMAIN_KERNEL,
351 },
352};
353
354const struct mem_type *get_mem_type(unsigned int type)
355{
356 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
357}
358EXPORT_SYMBOL(get_mem_type);
359
360static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr);
361
362static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS]
363 __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata;
364
365static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr)
366{
367 return &bm_pte[pte_index(addr)];
368}
369
370static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr)
371{
372 return pte_offset_kernel(dir, addr);
373}
374
375static inline pmd_t * __init fixmap_pmd(unsigned long addr)
376{
377 pgd_t *pgd = pgd_offset_k(addr);
378 pud_t *pud = pud_offset(pgd, addr);
379 pmd_t *pmd = pmd_offset(pud, addr);
380
381 return pmd;
382}
383
384void __init early_fixmap_init(void)
385{
386 pmd_t *pmd;
387
388 /*
389 * The early fixmap range spans multiple pmds, for which
390 * we are not prepared:
391 */
392 BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT)
393 != FIXADDR_TOP >> PMD_SHIFT);
394
395 pmd = fixmap_pmd(FIXADDR_TOP);
396 pmd_populate_kernel(&init_mm, pmd, bm_pte);
397
398 pte_offset_fixmap = pte_offset_early_fixmap;
399}
400
401/*
402 * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range().
403 * As a result, this can only be called with preemption disabled, as under
404 * stop_machine().
405 */
406void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
407{
408 unsigned long vaddr = __fix_to_virt(idx);
409 pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr);
410
411 /* Make sure fixmap region does not exceed available allocation. */
412 BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) >
413 FIXADDR_END);
414 BUG_ON(idx >= __end_of_fixed_addresses);
415
416 /* we only support device mappings until pgprot_kernel has been set */
417 if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) &&
418 pgprot_val(pgprot_kernel) == 0))
419 return;
420
421 if (pgprot_val(prot))
422 set_pte_at(NULL, vaddr, pte,
423 pfn_pte(phys >> PAGE_SHIFT, prot));
424 else
425 pte_clear(NULL, vaddr, pte);
426 local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
427}
428
429/*
430 * Adjust the PMD section entries according to the CPU in use.
431 */
432static void __init build_mem_type_table(void)
433{
434 struct cachepolicy *cp;
435 unsigned int cr = get_cr();
436 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
437 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
438 int cpu_arch = cpu_architecture();
439 int i;
440
441 if (cpu_arch < CPU_ARCH_ARMv6) {
442#if defined(CONFIG_CPU_DCACHE_DISABLE)
443 if (cachepolicy > CPOLICY_BUFFERED)
444 cachepolicy = CPOLICY_BUFFERED;
445#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
446 if (cachepolicy > CPOLICY_WRITETHROUGH)
447 cachepolicy = CPOLICY_WRITETHROUGH;
448#endif
449 }
450 if (cpu_arch < CPU_ARCH_ARMv5) {
451 if (cachepolicy >= CPOLICY_WRITEALLOC)
452 cachepolicy = CPOLICY_WRITEBACK;
453 ecc_mask = 0;
454 }
455
456 if (is_smp()) {
457 if (cachepolicy != CPOLICY_WRITEALLOC) {
458 pr_warn("Forcing write-allocate cache policy for SMP\n");
459 cachepolicy = CPOLICY_WRITEALLOC;
460 }
461 if (!(initial_pmd_value & PMD_SECT_S)) {
462 pr_warn("Forcing shared mappings for SMP\n");
463 initial_pmd_value |= PMD_SECT_S;
464 }
465 }
466
467 /*
468 * Strip out features not present on earlier architectures.
469 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
470 * without extended page tables don't have the 'Shared' bit.
471 */
472 if (cpu_arch < CPU_ARCH_ARMv5)
473 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
474 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
475 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
476 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
477 mem_types[i].prot_sect &= ~PMD_SECT_S;
478
479 /*
480 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
481 * "update-able on write" bit on ARM610). However, Xscale and
482 * Xscale3 require this bit to be cleared.
483 */
484 if (cpu_is_xscale_family()) {
485 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
486 mem_types[i].prot_sect &= ~PMD_BIT4;
487 mem_types[i].prot_l1 &= ~PMD_BIT4;
488 }
489 } else if (cpu_arch < CPU_ARCH_ARMv6) {
490 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
491 if (mem_types[i].prot_l1)
492 mem_types[i].prot_l1 |= PMD_BIT4;
493 if (mem_types[i].prot_sect)
494 mem_types[i].prot_sect |= PMD_BIT4;
495 }
496 }
497
498 /*
499 * Mark the device areas according to the CPU/architecture.
500 */
501 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
502 if (!cpu_is_xsc3()) {
503 /*
504 * Mark device regions on ARMv6+ as execute-never
505 * to prevent speculative instruction fetches.
506 */
507 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
508 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
509 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
510 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
511
512 /* Also setup NX memory mapping */
513 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
514 }
515 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
516 /*
517 * For ARMv7 with TEX remapping,
518 * - shared device is SXCB=1100
519 * - nonshared device is SXCB=0100
520 * - write combine device mem is SXCB=0001
521 * (Uncached Normal memory)
522 */
523 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
524 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
525 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
526 } else if (cpu_is_xsc3()) {
527 /*
528 * For Xscale3,
529 * - shared device is TEXCB=00101
530 * - nonshared device is TEXCB=01000
531 * - write combine device mem is TEXCB=00100
532 * (Inner/Outer Uncacheable in xsc3 parlance)
533 */
534 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
535 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
536 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
537 } else {
538 /*
539 * For ARMv6 and ARMv7 without TEX remapping,
540 * - shared device is TEXCB=00001
541 * - nonshared device is TEXCB=01000
542 * - write combine device mem is TEXCB=00100
543 * (Uncached Normal in ARMv6 parlance).
544 */
545 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
546 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
547 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
548 }
549 } else {
550 /*
551 * On others, write combining is "Uncached/Buffered"
552 */
553 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
554 }
555
556 /*
557 * Now deal with the memory-type mappings
558 */
559 cp = &cache_policies[cachepolicy];
560 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
561 s2_pgprot = cp->pte_s2;
562 hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
563 s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
564
565#ifndef CONFIG_ARM_LPAE
566 /*
567 * We don't use domains on ARMv6 (since this causes problems with
568 * v6/v7 kernels), so we must use a separate memory type for user
569 * r/o, kernel r/w to map the vectors page.
570 */
571 if (cpu_arch == CPU_ARCH_ARMv6)
572 vecs_pgprot |= L_PTE_MT_VECTORS;
573
574 /*
575 * Check is it with support for the PXN bit
576 * in the Short-descriptor translation table format descriptors.
577 */
578 if (cpu_arch == CPU_ARCH_ARMv7 &&
579 (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) {
580 user_pmd_table |= PMD_PXNTABLE;
581 }
582#endif
583
584 /*
585 * ARMv6 and above have extended page tables.
586 */
587 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
588#ifndef CONFIG_ARM_LPAE
589 /*
590 * Mark cache clean areas and XIP ROM read only
591 * from SVC mode and no access from userspace.
592 */
593 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
594 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
595 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
596#endif
597
598 /*
599 * If the initial page tables were created with the S bit
600 * set, then we need to do the same here for the same
601 * reasons given in early_cachepolicy().
602 */
603 if (initial_pmd_value & PMD_SECT_S) {
604 user_pgprot |= L_PTE_SHARED;
605 kern_pgprot |= L_PTE_SHARED;
606 vecs_pgprot |= L_PTE_SHARED;
607 s2_pgprot |= L_PTE_SHARED;
608 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
609 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
610 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
611 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
612 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
613 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
614 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
615 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
616 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
617 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
618 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
619 }
620 }
621
622 /*
623 * Non-cacheable Normal - intended for memory areas that must
624 * not cause dirty cache line writebacks when used
625 */
626 if (cpu_arch >= CPU_ARCH_ARMv6) {
627 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
628 /* Non-cacheable Normal is XCB = 001 */
629 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
630 PMD_SECT_BUFFERED;
631 } else {
632 /* For both ARMv6 and non-TEX-remapping ARMv7 */
633 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
634 PMD_SECT_TEX(1);
635 }
636 } else {
637 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
638 }
639
640#ifdef CONFIG_ARM_LPAE
641 /*
642 * Do not generate access flag faults for the kernel mappings.
643 */
644 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
645 mem_types[i].prot_pte |= PTE_EXT_AF;
646 if (mem_types[i].prot_sect)
647 mem_types[i].prot_sect |= PMD_SECT_AF;
648 }
649 kern_pgprot |= PTE_EXT_AF;
650 vecs_pgprot |= PTE_EXT_AF;
651
652 /*
653 * Set PXN for user mappings
654 */
655 user_pgprot |= PTE_EXT_PXN;
656#endif
657
658 for (i = 0; i < 16; i++) {
659 pteval_t v = pgprot_val(protection_map[i]);
660 protection_map[i] = __pgprot(v | user_pgprot);
661 }
662
663 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
664 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
665
666 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
667 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
668 L_PTE_DIRTY | kern_pgprot);
669 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
670 pgprot_s2_device = __pgprot(s2_device_pgprot);
671 pgprot_hyp_device = __pgprot(hyp_device_pgprot);
672
673 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
674 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
675 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
676 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
677 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
678 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
679 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
680 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
681 mem_types[MT_ROM].prot_sect |= cp->pmd;
682
683 switch (cp->pmd) {
684 case PMD_SECT_WT:
685 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
686 break;
687 case PMD_SECT_WB:
688 case PMD_SECT_WBWA:
689 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
690 break;
691 }
692 pr_info("Memory policy: %sData cache %s\n",
693 ecc_mask ? "ECC enabled, " : "", cp->policy);
694
695 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
696 struct mem_type *t = &mem_types[i];
697 if (t->prot_l1)
698 t->prot_l1 |= PMD_DOMAIN(t->domain);
699 if (t->prot_sect)
700 t->prot_sect |= PMD_DOMAIN(t->domain);
701 }
702}
703
704#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
705pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
706 unsigned long size, pgprot_t vma_prot)
707{
708 if (!pfn_valid(pfn))
709 return pgprot_noncached(vma_prot);
710 else if (file->f_flags & O_SYNC)
711 return pgprot_writecombine(vma_prot);
712 return vma_prot;
713}
714EXPORT_SYMBOL(phys_mem_access_prot);
715#endif
716
717#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
718
719static void __init *early_alloc(unsigned long sz)
720{
721 void *ptr = memblock_alloc(sz, sz);
722
723 if (!ptr)
724 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
725 __func__, sz, sz);
726
727 return ptr;
728}
729
730static void *__init late_alloc(unsigned long sz)
731{
732 void *ptr = (void *)__get_free_pages(GFP_PGTABLE_KERNEL, get_order(sz));
733
734 if (!ptr || !pgtable_pte_page_ctor(virt_to_page(ptr)))
735 BUG();
736 return ptr;
737}
738
739static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr,
740 unsigned long prot,
741 void *(*alloc)(unsigned long sz))
742{
743 if (pmd_none(*pmd)) {
744 pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
745 __pmd_populate(pmd, __pa(pte), prot);
746 }
747 BUG_ON(pmd_bad(*pmd));
748 return pte_offset_kernel(pmd, addr);
749}
750
751static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr,
752 unsigned long prot)
753{
754 return arm_pte_alloc(pmd, addr, prot, early_alloc);
755}
756
757static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
758 unsigned long end, unsigned long pfn,
759 const struct mem_type *type,
760 void *(*alloc)(unsigned long sz),
761 bool ng)
762{
763 pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc);
764 do {
765 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
766 ng ? PTE_EXT_NG : 0);
767 pfn++;
768 } while (pte++, addr += PAGE_SIZE, addr != end);
769}
770
771static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
772 unsigned long end, phys_addr_t phys,
773 const struct mem_type *type, bool ng)
774{
775 pmd_t *p = pmd;
776
777#ifndef CONFIG_ARM_LPAE
778 /*
779 * In classic MMU format, puds and pmds are folded in to
780 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
781 * group of L1 entries making up one logical pointer to
782 * an L2 table (2MB), where as PMDs refer to the individual
783 * L1 entries (1MB). Hence increment to get the correct
784 * offset for odd 1MB sections.
785 * (See arch/arm/include/asm/pgtable-2level.h)
786 */
787 if (addr & SECTION_SIZE)
788 pmd++;
789#endif
790 do {
791 *pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0));
792 phys += SECTION_SIZE;
793 } while (pmd++, addr += SECTION_SIZE, addr != end);
794
795 flush_pmd_entry(p);
796}
797
798static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
799 unsigned long end, phys_addr_t phys,
800 const struct mem_type *type,
801 void *(*alloc)(unsigned long sz), bool ng)
802{
803 pmd_t *pmd = pmd_offset(pud, addr);
804 unsigned long next;
805
806 do {
807 /*
808 * With LPAE, we must loop over to map
809 * all the pmds for the given range.
810 */
811 next = pmd_addr_end(addr, end);
812
813 /*
814 * Try a section mapping - addr, next and phys must all be
815 * aligned to a section boundary.
816 */
817 if (type->prot_sect &&
818 ((addr | next | phys) & ~SECTION_MASK) == 0) {
819 __map_init_section(pmd, addr, next, phys, type, ng);
820 } else {
821 alloc_init_pte(pmd, addr, next,
822 __phys_to_pfn(phys), type, alloc, ng);
823 }
824
825 phys += next - addr;
826
827 } while (pmd++, addr = next, addr != end);
828}
829
830static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
831 unsigned long end, phys_addr_t phys,
832 const struct mem_type *type,
833 void *(*alloc)(unsigned long sz), bool ng)
834{
835 pud_t *pud = pud_offset(pgd, addr);
836 unsigned long next;
837
838 do {
839 next = pud_addr_end(addr, end);
840 alloc_init_pmd(pud, addr, next, phys, type, alloc, ng);
841 phys += next - addr;
842 } while (pud++, addr = next, addr != end);
843}
844
845#ifndef CONFIG_ARM_LPAE
846static void __init create_36bit_mapping(struct mm_struct *mm,
847 struct map_desc *md,
848 const struct mem_type *type,
849 bool ng)
850{
851 unsigned long addr, length, end;
852 phys_addr_t phys;
853 pgd_t *pgd;
854
855 addr = md->virtual;
856 phys = __pfn_to_phys(md->pfn);
857 length = PAGE_ALIGN(md->length);
858
859 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
860 pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n",
861 (long long)__pfn_to_phys((u64)md->pfn), addr);
862 return;
863 }
864
865 /* N.B. ARMv6 supersections are only defined to work with domain 0.
866 * Since domain assignments can in fact be arbitrary, the
867 * 'domain == 0' check below is required to insure that ARMv6
868 * supersections are only allocated for domain 0 regardless
869 * of the actual domain assignments in use.
870 */
871 if (type->domain) {
872 pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n",
873 (long long)__pfn_to_phys((u64)md->pfn), addr);
874 return;
875 }
876
877 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
878 pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n",
879 (long long)__pfn_to_phys((u64)md->pfn), addr);
880 return;
881 }
882
883 /*
884 * Shift bits [35:32] of address into bits [23:20] of PMD
885 * (See ARMv6 spec).
886 */
887 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
888
889 pgd = pgd_offset(mm, addr);
890 end = addr + length;
891 do {
892 pud_t *pud = pud_offset(pgd, addr);
893 pmd_t *pmd = pmd_offset(pud, addr);
894 int i;
895
896 for (i = 0; i < 16; i++)
897 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER |
898 (ng ? PMD_SECT_nG : 0));
899
900 addr += SUPERSECTION_SIZE;
901 phys += SUPERSECTION_SIZE;
902 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
903 } while (addr != end);
904}
905#endif /* !CONFIG_ARM_LPAE */
906
907static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md,
908 void *(*alloc)(unsigned long sz),
909 bool ng)
910{
911 unsigned long addr, length, end;
912 phys_addr_t phys;
913 const struct mem_type *type;
914 pgd_t *pgd;
915
916 type = &mem_types[md->type];
917
918#ifndef CONFIG_ARM_LPAE
919 /*
920 * Catch 36-bit addresses
921 */
922 if (md->pfn >= 0x100000) {
923 create_36bit_mapping(mm, md, type, ng);
924 return;
925 }
926#endif
927
928 addr = md->virtual & PAGE_MASK;
929 phys = __pfn_to_phys(md->pfn);
930 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
931
932 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
933 pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n",
934 (long long)__pfn_to_phys(md->pfn), addr);
935 return;
936 }
937
938 pgd = pgd_offset(mm, addr);
939 end = addr + length;
940 do {
941 unsigned long next = pgd_addr_end(addr, end);
942
943 alloc_init_pud(pgd, addr, next, phys, type, alloc, ng);
944
945 phys += next - addr;
946 addr = next;
947 } while (pgd++, addr != end);
948}
949
950/*
951 * Create the page directory entries and any necessary
952 * page tables for the mapping specified by `md'. We
953 * are able to cope here with varying sizes and address
954 * offsets, and we take full advantage of sections and
955 * supersections.
956 */
957static void __init create_mapping(struct map_desc *md)
958{
959 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
960 pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n",
961 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
962 return;
963 }
964
965 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
966 md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START &&
967 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
968 pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n",
969 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
970 }
971
972 __create_mapping(&init_mm, md, early_alloc, false);
973}
974
975void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md,
976 bool ng)
977{
978#ifdef CONFIG_ARM_LPAE
979 pud_t *pud = pud_alloc(mm, pgd_offset(mm, md->virtual), md->virtual);
980 if (WARN_ON(!pud))
981 return;
982 pmd_alloc(mm, pud, 0);
983#endif
984 __create_mapping(mm, md, late_alloc, ng);
985}
986
987/*
988 * Create the architecture specific mappings
989 */
990void __init iotable_init(struct map_desc *io_desc, int nr)
991{
992 struct map_desc *md;
993 struct vm_struct *vm;
994 struct static_vm *svm;
995
996 if (!nr)
997 return;
998
999 svm = memblock_alloc(sizeof(*svm) * nr, __alignof__(*svm));
1000 if (!svm)
1001 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
1002 __func__, sizeof(*svm) * nr, __alignof__(*svm));
1003
1004 for (md = io_desc; nr; md++, nr--) {
1005 create_mapping(md);
1006
1007 vm = &svm->vm;
1008 vm->addr = (void *)(md->virtual & PAGE_MASK);
1009 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
1010 vm->phys_addr = __pfn_to_phys(md->pfn);
1011 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
1012 vm->flags |= VM_ARM_MTYPE(md->type);
1013 vm->caller = iotable_init;
1014 add_static_vm_early(svm++);
1015 }
1016}
1017
1018void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
1019 void *caller)
1020{
1021 struct vm_struct *vm;
1022 struct static_vm *svm;
1023
1024 svm = memblock_alloc(sizeof(*svm), __alignof__(*svm));
1025 if (!svm)
1026 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
1027 __func__, sizeof(*svm), __alignof__(*svm));
1028
1029 vm = &svm->vm;
1030 vm->addr = (void *)addr;
1031 vm->size = size;
1032 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
1033 vm->caller = caller;
1034 add_static_vm_early(svm);
1035}
1036
1037#ifndef CONFIG_ARM_LPAE
1038
1039/*
1040 * The Linux PMD is made of two consecutive section entries covering 2MB
1041 * (see definition in include/asm/pgtable-2level.h). However a call to
1042 * create_mapping() may optimize static mappings by using individual
1043 * 1MB section mappings. This leaves the actual PMD potentially half
1044 * initialized if the top or bottom section entry isn't used, leaving it
1045 * open to problems if a subsequent ioremap() or vmalloc() tries to use
1046 * the virtual space left free by that unused section entry.
1047 *
1048 * Let's avoid the issue by inserting dummy vm entries covering the unused
1049 * PMD halves once the static mappings are in place.
1050 */
1051
1052static void __init pmd_empty_section_gap(unsigned long addr)
1053{
1054 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
1055}
1056
1057static void __init fill_pmd_gaps(void)
1058{
1059 struct static_vm *svm;
1060 struct vm_struct *vm;
1061 unsigned long addr, next = 0;
1062 pmd_t *pmd;
1063
1064 list_for_each_entry(svm, &static_vmlist, list) {
1065 vm = &svm->vm;
1066 addr = (unsigned long)vm->addr;
1067 if (addr < next)
1068 continue;
1069
1070 /*
1071 * Check if this vm starts on an odd section boundary.
1072 * If so and the first section entry for this PMD is free
1073 * then we block the corresponding virtual address.
1074 */
1075 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1076 pmd = pmd_off_k(addr);
1077 if (pmd_none(*pmd))
1078 pmd_empty_section_gap(addr & PMD_MASK);
1079 }
1080
1081 /*
1082 * Then check if this vm ends on an odd section boundary.
1083 * If so and the second section entry for this PMD is empty
1084 * then we block the corresponding virtual address.
1085 */
1086 addr += vm->size;
1087 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1088 pmd = pmd_off_k(addr) + 1;
1089 if (pmd_none(*pmd))
1090 pmd_empty_section_gap(addr);
1091 }
1092
1093 /* no need to look at any vm entry until we hit the next PMD */
1094 next = (addr + PMD_SIZE - 1) & PMD_MASK;
1095 }
1096}
1097
1098#else
1099#define fill_pmd_gaps() do { } while (0)
1100#endif
1101
1102#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
1103static void __init pci_reserve_io(void)
1104{
1105 struct static_vm *svm;
1106
1107 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1108 if (svm)
1109 return;
1110
1111 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1112}
1113#else
1114#define pci_reserve_io() do { } while (0)
1115#endif
1116
1117#ifdef CONFIG_DEBUG_LL
1118void __init debug_ll_io_init(void)
1119{
1120 struct map_desc map;
1121
1122 debug_ll_addr(&map.pfn, &map.virtual);
1123 if (!map.pfn || !map.virtual)
1124 return;
1125 map.pfn = __phys_to_pfn(map.pfn);
1126 map.virtual &= PAGE_MASK;
1127 map.length = PAGE_SIZE;
1128 map.type = MT_DEVICE;
1129 iotable_init(&map, 1);
1130}
1131#endif
1132
1133static void * __initdata vmalloc_min =
1134 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
1135
1136/*
1137 * vmalloc=size forces the vmalloc area to be exactly 'size'
1138 * bytes. This can be used to increase (or decrease) the vmalloc
1139 * area - the default is 240m.
1140 */
1141static int __init early_vmalloc(char *arg)
1142{
1143 unsigned long vmalloc_reserve = memparse(arg, NULL);
1144
1145 if (vmalloc_reserve < SZ_16M) {
1146 vmalloc_reserve = SZ_16M;
1147 pr_warn("vmalloc area too small, limiting to %luMB\n",
1148 vmalloc_reserve >> 20);
1149 }
1150
1151 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
1152 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
1153 pr_warn("vmalloc area is too big, limiting to %luMB\n",
1154 vmalloc_reserve >> 20);
1155 }
1156
1157 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
1158 return 0;
1159}
1160early_param("vmalloc", early_vmalloc);
1161
1162phys_addr_t arm_lowmem_limit __initdata = 0;
1163
1164void __init adjust_lowmem_bounds(void)
1165{
1166 phys_addr_t memblock_limit = 0;
1167 u64 vmalloc_limit;
1168 struct memblock_region *reg;
1169 phys_addr_t lowmem_limit = 0;
1170
1171 /*
1172 * Let's use our own (unoptimized) equivalent of __pa() that is
1173 * not affected by wrap-arounds when sizeof(phys_addr_t) == 4.
1174 * The result is used as the upper bound on physical memory address
1175 * and may itself be outside the valid range for which phys_addr_t
1176 * and therefore __pa() is defined.
1177 */
1178 vmalloc_limit = (u64)(uintptr_t)vmalloc_min - PAGE_OFFSET + PHYS_OFFSET;
1179
1180 /*
1181 * The first usable region must be PMD aligned. Mark its start
1182 * as MEMBLOCK_NOMAP if it isn't
1183 */
1184 for_each_memblock(memory, reg) {
1185 if (!memblock_is_nomap(reg)) {
1186 if (!IS_ALIGNED(reg->base, PMD_SIZE)) {
1187 phys_addr_t len;
1188
1189 len = round_up(reg->base, PMD_SIZE) - reg->base;
1190 memblock_mark_nomap(reg->base, len);
1191 }
1192 break;
1193 }
1194 }
1195
1196 for_each_memblock(memory, reg) {
1197 phys_addr_t block_start = reg->base;
1198 phys_addr_t block_end = reg->base + reg->size;
1199
1200 if (memblock_is_nomap(reg))
1201 continue;
1202
1203 if (reg->base < vmalloc_limit) {
1204 if (block_end > lowmem_limit)
1205 /*
1206 * Compare as u64 to ensure vmalloc_limit does
1207 * not get truncated. block_end should always
1208 * fit in phys_addr_t so there should be no
1209 * issue with assignment.
1210 */
1211 lowmem_limit = min_t(u64,
1212 vmalloc_limit,
1213 block_end);
1214
1215 /*
1216 * Find the first non-pmd-aligned page, and point
1217 * memblock_limit at it. This relies on rounding the
1218 * limit down to be pmd-aligned, which happens at the
1219 * end of this function.
1220 *
1221 * With this algorithm, the start or end of almost any
1222 * bank can be non-pmd-aligned. The only exception is
1223 * that the start of the bank 0 must be section-
1224 * aligned, since otherwise memory would need to be
1225 * allocated when mapping the start of bank 0, which
1226 * occurs before any free memory is mapped.
1227 */
1228 if (!memblock_limit) {
1229 if (!IS_ALIGNED(block_start, PMD_SIZE))
1230 memblock_limit = block_start;
1231 else if (!IS_ALIGNED(block_end, PMD_SIZE))
1232 memblock_limit = lowmem_limit;
1233 }
1234
1235 }
1236 }
1237
1238 arm_lowmem_limit = lowmem_limit;
1239
1240 high_memory = __va(arm_lowmem_limit - 1) + 1;
1241
1242 if (!memblock_limit)
1243 memblock_limit = arm_lowmem_limit;
1244
1245 /*
1246 * Round the memblock limit down to a pmd size. This
1247 * helps to ensure that we will allocate memory from the
1248 * last full pmd, which should be mapped.
1249 */
1250 memblock_limit = round_down(memblock_limit, PMD_SIZE);
1251
1252 if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
1253 if (memblock_end_of_DRAM() > arm_lowmem_limit) {
1254 phys_addr_t end = memblock_end_of_DRAM();
1255
1256 pr_notice("Ignoring RAM at %pa-%pa\n",
1257 &memblock_limit, &end);
1258 pr_notice("Consider using a HIGHMEM enabled kernel.\n");
1259
1260 memblock_remove(memblock_limit, end - memblock_limit);
1261 }
1262 }
1263
1264 memblock_set_current_limit(memblock_limit);
1265}
1266
1267static inline void prepare_page_table(void)
1268{
1269 unsigned long addr;
1270 phys_addr_t end;
1271
1272 /*
1273 * Clear out all the mappings below the kernel image.
1274 */
1275 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1276 pmd_clear(pmd_off_k(addr));
1277
1278#ifdef CONFIG_XIP_KERNEL
1279 /* The XIP kernel is mapped in the module area -- skip over it */
1280 addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK;
1281#endif
1282 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1283 pmd_clear(pmd_off_k(addr));
1284
1285 /*
1286 * Find the end of the first block of lowmem.
1287 */
1288 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1289 if (end >= arm_lowmem_limit)
1290 end = arm_lowmem_limit;
1291
1292 /*
1293 * Clear out all the kernel space mappings, except for the first
1294 * memory bank, up to the vmalloc region.
1295 */
1296 for (addr = __phys_to_virt(end);
1297 addr < VMALLOC_START; addr += PMD_SIZE)
1298 pmd_clear(pmd_off_k(addr));
1299}
1300
1301#ifdef CONFIG_ARM_LPAE
1302/* the first page is reserved for pgd */
1303#define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1304 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1305#else
1306#define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1307#endif
1308
1309/*
1310 * Reserve the special regions of memory
1311 */
1312void __init arm_mm_memblock_reserve(void)
1313{
1314 /*
1315 * Reserve the page tables. These are already in use,
1316 * and can only be in node 0.
1317 */
1318 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1319
1320#ifdef CONFIG_SA1111
1321 /*
1322 * Because of the SA1111 DMA bug, we want to preserve our
1323 * precious DMA-able memory...
1324 */
1325 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1326#endif
1327}
1328
1329/*
1330 * Set up the device mappings. Since we clear out the page tables for all
1331 * mappings above VMALLOC_START, except early fixmap, we might remove debug
1332 * device mappings. This means earlycon can be used to debug this function
1333 * Any other function or debugging method which may touch any device _will_
1334 * crash the kernel.
1335 */
1336static void __init devicemaps_init(const struct machine_desc *mdesc)
1337{
1338 struct map_desc map;
1339 unsigned long addr;
1340 void *vectors;
1341
1342 /*
1343 * Allocate the vector page early.
1344 */
1345 vectors = early_alloc(PAGE_SIZE * 2);
1346
1347 early_trap_init(vectors);
1348
1349 /*
1350 * Clear page table except top pmd used by early fixmaps
1351 */
1352 for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE)
1353 pmd_clear(pmd_off_k(addr));
1354
1355 /*
1356 * Map the kernel if it is XIP.
1357 * It is always first in the modulearea.
1358 */
1359#ifdef CONFIG_XIP_KERNEL
1360 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1361 map.virtual = MODULES_VADDR;
1362 map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1363 map.type = MT_ROM;
1364 create_mapping(&map);
1365#endif
1366
1367 /*
1368 * Map the cache flushing regions.
1369 */
1370#ifdef FLUSH_BASE
1371 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1372 map.virtual = FLUSH_BASE;
1373 map.length = SZ_1M;
1374 map.type = MT_CACHECLEAN;
1375 create_mapping(&map);
1376#endif
1377#ifdef FLUSH_BASE_MINICACHE
1378 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1379 map.virtual = FLUSH_BASE_MINICACHE;
1380 map.length = SZ_1M;
1381 map.type = MT_MINICLEAN;
1382 create_mapping(&map);
1383#endif
1384
1385 /*
1386 * Create a mapping for the machine vectors at the high-vectors
1387 * location (0xffff0000). If we aren't using high-vectors, also
1388 * create a mapping at the low-vectors virtual address.
1389 */
1390 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1391 map.virtual = 0xffff0000;
1392 map.length = PAGE_SIZE;
1393#ifdef CONFIG_KUSER_HELPERS
1394 map.type = MT_HIGH_VECTORS;
1395#else
1396 map.type = MT_LOW_VECTORS;
1397#endif
1398 create_mapping(&map);
1399
1400 if (!vectors_high()) {
1401 map.virtual = 0;
1402 map.length = PAGE_SIZE * 2;
1403 map.type = MT_LOW_VECTORS;
1404 create_mapping(&map);
1405 }
1406
1407 /* Now create a kernel read-only mapping */
1408 map.pfn += 1;
1409 map.virtual = 0xffff0000 + PAGE_SIZE;
1410 map.length = PAGE_SIZE;
1411 map.type = MT_LOW_VECTORS;
1412 create_mapping(&map);
1413
1414 /*
1415 * Ask the machine support to map in the statically mapped devices.
1416 */
1417 if (mdesc->map_io)
1418 mdesc->map_io();
1419 else
1420 debug_ll_io_init();
1421 fill_pmd_gaps();
1422
1423 /* Reserve fixed i/o space in VMALLOC region */
1424 pci_reserve_io();
1425
1426 /*
1427 * Finally flush the caches and tlb to ensure that we're in a
1428 * consistent state wrt the writebuffer. This also ensures that
1429 * any write-allocated cache lines in the vector page are written
1430 * back. After this point, we can start to touch devices again.
1431 */
1432 local_flush_tlb_all();
1433 flush_cache_all();
1434
1435 /* Enable asynchronous aborts */
1436 early_abt_enable();
1437}
1438
1439static void __init kmap_init(void)
1440{
1441#ifdef CONFIG_HIGHMEM
1442 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1443 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1444#endif
1445
1446 early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START,
1447 _PAGE_KERNEL_TABLE);
1448}
1449
1450static void __init map_lowmem(void)
1451{
1452 struct memblock_region *reg;
1453 phys_addr_t kernel_x_start = round_down(__pa(KERNEL_START), SECTION_SIZE);
1454 phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1455
1456 /* Map all the lowmem memory banks. */
1457 for_each_memblock(memory, reg) {
1458 phys_addr_t start = reg->base;
1459 phys_addr_t end = start + reg->size;
1460 struct map_desc map;
1461
1462 if (memblock_is_nomap(reg))
1463 continue;
1464
1465 if (end > arm_lowmem_limit)
1466 end = arm_lowmem_limit;
1467 if (start >= end)
1468 break;
1469
1470 if (end < kernel_x_start) {
1471 map.pfn = __phys_to_pfn(start);
1472 map.virtual = __phys_to_virt(start);
1473 map.length = end - start;
1474 map.type = MT_MEMORY_RWX;
1475
1476 create_mapping(&map);
1477 } else if (start >= kernel_x_end) {
1478 map.pfn = __phys_to_pfn(start);
1479 map.virtual = __phys_to_virt(start);
1480 map.length = end - start;
1481 map.type = MT_MEMORY_RW;
1482
1483 create_mapping(&map);
1484 } else {
1485 /* This better cover the entire kernel */
1486 if (start < kernel_x_start) {
1487 map.pfn = __phys_to_pfn(start);
1488 map.virtual = __phys_to_virt(start);
1489 map.length = kernel_x_start - start;
1490 map.type = MT_MEMORY_RW;
1491
1492 create_mapping(&map);
1493 }
1494
1495 map.pfn = __phys_to_pfn(kernel_x_start);
1496 map.virtual = __phys_to_virt(kernel_x_start);
1497 map.length = kernel_x_end - kernel_x_start;
1498 map.type = MT_MEMORY_RWX;
1499
1500 create_mapping(&map);
1501
1502 if (kernel_x_end < end) {
1503 map.pfn = __phys_to_pfn(kernel_x_end);
1504 map.virtual = __phys_to_virt(kernel_x_end);
1505 map.length = end - kernel_x_end;
1506 map.type = MT_MEMORY_RW;
1507
1508 create_mapping(&map);
1509 }
1510 }
1511 }
1512}
1513
1514#ifdef CONFIG_ARM_PV_FIXUP
1515extern unsigned long __atags_pointer;
1516typedef void pgtables_remap(long long offset, unsigned long pgd, void *bdata);
1517pgtables_remap lpae_pgtables_remap_asm;
1518
1519/*
1520 * early_paging_init() recreates boot time page table setup, allowing machines
1521 * to switch over to a high (>4G) address space on LPAE systems
1522 */
1523static void __init early_paging_init(const struct machine_desc *mdesc)
1524{
1525 pgtables_remap *lpae_pgtables_remap;
1526 unsigned long pa_pgd;
1527 unsigned int cr, ttbcr;
1528 long long offset;
1529 void *boot_data;
1530
1531 if (!mdesc->pv_fixup)
1532 return;
1533
1534 offset = mdesc->pv_fixup();
1535 if (offset == 0)
1536 return;
1537
1538 /*
1539 * Get the address of the remap function in the 1:1 identity
1540 * mapping setup by the early page table assembly code. We
1541 * must get this prior to the pv update. The following barrier
1542 * ensures that this is complete before we fixup any P:V offsets.
1543 */
1544 lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm);
1545 pa_pgd = __pa(swapper_pg_dir);
1546 boot_data = __va(__atags_pointer);
1547 barrier();
1548
1549 pr_info("Switching physical address space to 0x%08llx\n",
1550 (u64)PHYS_OFFSET + offset);
1551
1552 /* Re-set the phys pfn offset, and the pv offset */
1553 __pv_offset += offset;
1554 __pv_phys_pfn_offset += PFN_DOWN(offset);
1555
1556 /* Run the patch stub to update the constants */
1557 fixup_pv_table(&__pv_table_begin,
1558 (&__pv_table_end - &__pv_table_begin) << 2);
1559
1560 /*
1561 * We changing not only the virtual to physical mapping, but also
1562 * the physical addresses used to access memory. We need to flush
1563 * all levels of cache in the system with caching disabled to
1564 * ensure that all data is written back, and nothing is prefetched
1565 * into the caches. We also need to prevent the TLB walkers
1566 * allocating into the caches too. Note that this is ARMv7 LPAE
1567 * specific.
1568 */
1569 cr = get_cr();
1570 set_cr(cr & ~(CR_I | CR_C));
1571 asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr));
1572 asm volatile("mcr p15, 0, %0, c2, c0, 2"
1573 : : "r" (ttbcr & ~(3 << 8 | 3 << 10)));
1574 flush_cache_all();
1575
1576 /*
1577 * Fixup the page tables - this must be in the idmap region as
1578 * we need to disable the MMU to do this safely, and hence it
1579 * needs to be assembly. It's fairly simple, as we're using the
1580 * temporary tables setup by the initial assembly code.
1581 */
1582 lpae_pgtables_remap(offset, pa_pgd, boot_data);
1583
1584 /* Re-enable the caches and cacheable TLB walks */
1585 asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr));
1586 set_cr(cr);
1587}
1588
1589#else
1590
1591static void __init early_paging_init(const struct machine_desc *mdesc)
1592{
1593 long long offset;
1594
1595 if (!mdesc->pv_fixup)
1596 return;
1597
1598 offset = mdesc->pv_fixup();
1599 if (offset == 0)
1600 return;
1601
1602 pr_crit("Physical address space modification is only to support Keystone2.\n");
1603 pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n");
1604 pr_crit("feature. Your kernel may crash now, have a good day.\n");
1605 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1606}
1607
1608#endif
1609
1610static void __init early_fixmap_shutdown(void)
1611{
1612 int i;
1613 unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1);
1614
1615 pte_offset_fixmap = pte_offset_late_fixmap;
1616 pmd_clear(fixmap_pmd(va));
1617 local_flush_tlb_kernel_page(va);
1618
1619 for (i = 0; i < __end_of_permanent_fixed_addresses; i++) {
1620 pte_t *pte;
1621 struct map_desc map;
1622
1623 map.virtual = fix_to_virt(i);
1624 pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual);
1625
1626 /* Only i/o device mappings are supported ATM */
1627 if (pte_none(*pte) ||
1628 (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED)
1629 continue;
1630
1631 map.pfn = pte_pfn(*pte);
1632 map.type = MT_DEVICE;
1633 map.length = PAGE_SIZE;
1634
1635 create_mapping(&map);
1636 }
1637}
1638
1639/*
1640 * paging_init() sets up the page tables, initialises the zone memory
1641 * maps, and sets up the zero page, bad page and bad page tables.
1642 */
1643void __init paging_init(const struct machine_desc *mdesc)
1644{
1645 void *zero_page;
1646
1647 prepare_page_table();
1648 map_lowmem();
1649 memblock_set_current_limit(arm_lowmem_limit);
1650 dma_contiguous_remap();
1651 early_fixmap_shutdown();
1652 devicemaps_init(mdesc);
1653 kmap_init();
1654 tcm_init();
1655
1656 top_pmd = pmd_off_k(0xffff0000);
1657
1658 /* allocate the zero page. */
1659 zero_page = early_alloc(PAGE_SIZE);
1660
1661 bootmem_init();
1662
1663 empty_zero_page = virt_to_page(zero_page);
1664 __flush_dcache_page(NULL, empty_zero_page);
1665
1666 /* Compute the virt/idmap offset, mostly for the sake of KVM */
1667 kimage_voffset = (unsigned long)&kimage_voffset - virt_to_idmap(&kimage_voffset);
1668}
1669
1670void __init early_mm_init(const struct machine_desc *mdesc)
1671{
1672 build_mem_type_table();
1673 early_paging_init(mdesc);
1674}