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1/*
2 * linux/arch/arm/mm/mmu.c
3 *
4 * Copyright (C) 1995-2005 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/mman.h>
15#include <linux/nodemask.h>
16#include <linux/memblock.h>
17#include <linux/fs.h>
18#include <linux/vmalloc.h>
19#include <linux/sizes.h>
20
21#include <asm/cp15.h>
22#include <asm/cputype.h>
23#include <asm/sections.h>
24#include <asm/cachetype.h>
25#include <asm/fixmap.h>
26#include <asm/sections.h>
27#include <asm/setup.h>
28#include <asm/smp_plat.h>
29#include <asm/tlb.h>
30#include <asm/highmem.h>
31#include <asm/system_info.h>
32#include <asm/traps.h>
33#include <asm/procinfo.h>
34#include <asm/memory.h>
35
36#include <asm/mach/arch.h>
37#include <asm/mach/map.h>
38#include <asm/mach/pci.h>
39#include <asm/fixmap.h>
40
41#include "fault.h"
42#include "mm.h"
43#include "tcm.h"
44
45/*
46 * empty_zero_page is a special page that is used for
47 * zero-initialized data and COW.
48 */
49struct page *empty_zero_page;
50EXPORT_SYMBOL(empty_zero_page);
51
52/*
53 * The pmd table for the upper-most set of pages.
54 */
55pmd_t *top_pmd;
56
57pmdval_t user_pmd_table = _PAGE_USER_TABLE;
58
59#define CPOLICY_UNCACHED 0
60#define CPOLICY_BUFFERED 1
61#define CPOLICY_WRITETHROUGH 2
62#define CPOLICY_WRITEBACK 3
63#define CPOLICY_WRITEALLOC 4
64
65static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
66static unsigned int ecc_mask __initdata = 0;
67pgprot_t pgprot_user;
68pgprot_t pgprot_kernel;
69pgprot_t pgprot_hyp_device;
70pgprot_t pgprot_s2;
71pgprot_t pgprot_s2_device;
72
73EXPORT_SYMBOL(pgprot_user);
74EXPORT_SYMBOL(pgprot_kernel);
75
76struct cachepolicy {
77 const char policy[16];
78 unsigned int cr_mask;
79 pmdval_t pmd;
80 pteval_t pte;
81 pteval_t pte_s2;
82};
83
84#ifdef CONFIG_ARM_LPAE
85#define s2_policy(policy) policy
86#else
87#define s2_policy(policy) 0
88#endif
89
90static struct cachepolicy cache_policies[] __initdata = {
91 {
92 .policy = "uncached",
93 .cr_mask = CR_W|CR_C,
94 .pmd = PMD_SECT_UNCACHED,
95 .pte = L_PTE_MT_UNCACHED,
96 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
97 }, {
98 .policy = "buffered",
99 .cr_mask = CR_C,
100 .pmd = PMD_SECT_BUFFERED,
101 .pte = L_PTE_MT_BUFFERABLE,
102 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
103 }, {
104 .policy = "writethrough",
105 .cr_mask = 0,
106 .pmd = PMD_SECT_WT,
107 .pte = L_PTE_MT_WRITETHROUGH,
108 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
109 }, {
110 .policy = "writeback",
111 .cr_mask = 0,
112 .pmd = PMD_SECT_WB,
113 .pte = L_PTE_MT_WRITEBACK,
114 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
115 }, {
116 .policy = "writealloc",
117 .cr_mask = 0,
118 .pmd = PMD_SECT_WBWA,
119 .pte = L_PTE_MT_WRITEALLOC,
120 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
121 }
122};
123
124#ifdef CONFIG_CPU_CP15
125static unsigned long initial_pmd_value __initdata = 0;
126
127/*
128 * Initialise the cache_policy variable with the initial state specified
129 * via the "pmd" value. This is used to ensure that on ARMv6 and later,
130 * the C code sets the page tables up with the same policy as the head
131 * assembly code, which avoids an illegal state where the TLBs can get
132 * confused. See comments in early_cachepolicy() for more information.
133 */
134void __init init_default_cache_policy(unsigned long pmd)
135{
136 int i;
137
138 initial_pmd_value = pmd;
139
140 pmd &= PMD_SECT_TEX(1) | PMD_SECT_BUFFERABLE | PMD_SECT_CACHEABLE;
141
142 for (i = 0; i < ARRAY_SIZE(cache_policies); i++)
143 if (cache_policies[i].pmd == pmd) {
144 cachepolicy = i;
145 break;
146 }
147
148 if (i == ARRAY_SIZE(cache_policies))
149 pr_err("ERROR: could not find cache policy\n");
150}
151
152/*
153 * These are useful for identifying cache coherency problems by allowing
154 * the cache or the cache and writebuffer to be turned off. (Note: the
155 * write buffer should not be on and the cache off).
156 */
157static int __init early_cachepolicy(char *p)
158{
159 int i, selected = -1;
160
161 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
162 int len = strlen(cache_policies[i].policy);
163
164 if (memcmp(p, cache_policies[i].policy, len) == 0) {
165 selected = i;
166 break;
167 }
168 }
169
170 if (selected == -1)
171 pr_err("ERROR: unknown or unsupported cache policy\n");
172
173 /*
174 * This restriction is partly to do with the way we boot; it is
175 * unpredictable to have memory mapped using two different sets of
176 * memory attributes (shared, type, and cache attribs). We can not
177 * change these attributes once the initial assembly has setup the
178 * page tables.
179 */
180 if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) {
181 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
182 cache_policies[cachepolicy].policy);
183 return 0;
184 }
185
186 if (selected != cachepolicy) {
187 unsigned long cr = __clear_cr(cache_policies[selected].cr_mask);
188 cachepolicy = selected;
189 flush_cache_all();
190 set_cr(cr);
191 }
192 return 0;
193}
194early_param("cachepolicy", early_cachepolicy);
195
196static int __init early_nocache(char *__unused)
197{
198 char *p = "buffered";
199 pr_warn("nocache is deprecated; use cachepolicy=%s\n", p);
200 early_cachepolicy(p);
201 return 0;
202}
203early_param("nocache", early_nocache);
204
205static int __init early_nowrite(char *__unused)
206{
207 char *p = "uncached";
208 pr_warn("nowb is deprecated; use cachepolicy=%s\n", p);
209 early_cachepolicy(p);
210 return 0;
211}
212early_param("nowb", early_nowrite);
213
214#ifndef CONFIG_ARM_LPAE
215static int __init early_ecc(char *p)
216{
217 if (memcmp(p, "on", 2) == 0)
218 ecc_mask = PMD_PROTECTION;
219 else if (memcmp(p, "off", 3) == 0)
220 ecc_mask = 0;
221 return 0;
222}
223early_param("ecc", early_ecc);
224#endif
225
226#else /* ifdef CONFIG_CPU_CP15 */
227
228static int __init early_cachepolicy(char *p)
229{
230 pr_warn("cachepolicy kernel parameter not supported without cp15\n");
231}
232early_param("cachepolicy", early_cachepolicy);
233
234static int __init noalign_setup(char *__unused)
235{
236 pr_warn("noalign kernel parameter not supported without cp15\n");
237}
238__setup("noalign", noalign_setup);
239
240#endif /* ifdef CONFIG_CPU_CP15 / else */
241
242#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
243#define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
244#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
245
246static struct mem_type mem_types[] = {
247 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
248 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
249 L_PTE_SHARED,
250 .prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) |
251 s2_policy(L_PTE_S2_MT_DEV_SHARED) |
252 L_PTE_SHARED,
253 .prot_l1 = PMD_TYPE_TABLE,
254 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
255 .domain = DOMAIN_IO,
256 },
257 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
258 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
259 .prot_l1 = PMD_TYPE_TABLE,
260 .prot_sect = PROT_SECT_DEVICE,
261 .domain = DOMAIN_IO,
262 },
263 [MT_DEVICE_CACHED] = { /* ioremap_cached */
264 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
265 .prot_l1 = PMD_TYPE_TABLE,
266 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
267 .domain = DOMAIN_IO,
268 },
269 [MT_DEVICE_WC] = { /* ioremap_wc */
270 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
271 .prot_l1 = PMD_TYPE_TABLE,
272 .prot_sect = PROT_SECT_DEVICE,
273 .domain = DOMAIN_IO,
274 },
275 [MT_UNCACHED] = {
276 .prot_pte = PROT_PTE_DEVICE,
277 .prot_l1 = PMD_TYPE_TABLE,
278 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
279 .domain = DOMAIN_IO,
280 },
281 [MT_CACHECLEAN] = {
282 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
283 .domain = DOMAIN_KERNEL,
284 },
285#ifndef CONFIG_ARM_LPAE
286 [MT_MINICLEAN] = {
287 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
288 .domain = DOMAIN_KERNEL,
289 },
290#endif
291 [MT_LOW_VECTORS] = {
292 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
293 L_PTE_RDONLY,
294 .prot_l1 = PMD_TYPE_TABLE,
295 .domain = DOMAIN_VECTORS,
296 },
297 [MT_HIGH_VECTORS] = {
298 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
299 L_PTE_USER | L_PTE_RDONLY,
300 .prot_l1 = PMD_TYPE_TABLE,
301 .domain = DOMAIN_VECTORS,
302 },
303 [MT_MEMORY_RWX] = {
304 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
305 .prot_l1 = PMD_TYPE_TABLE,
306 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
307 .domain = DOMAIN_KERNEL,
308 },
309 [MT_MEMORY_RW] = {
310 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
311 L_PTE_XN,
312 .prot_l1 = PMD_TYPE_TABLE,
313 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
314 .domain = DOMAIN_KERNEL,
315 },
316 [MT_ROM] = {
317 .prot_sect = PMD_TYPE_SECT,
318 .domain = DOMAIN_KERNEL,
319 },
320 [MT_MEMORY_RWX_NONCACHED] = {
321 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
322 L_PTE_MT_BUFFERABLE,
323 .prot_l1 = PMD_TYPE_TABLE,
324 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
325 .domain = DOMAIN_KERNEL,
326 },
327 [MT_MEMORY_RW_DTCM] = {
328 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
329 L_PTE_XN,
330 .prot_l1 = PMD_TYPE_TABLE,
331 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
332 .domain = DOMAIN_KERNEL,
333 },
334 [MT_MEMORY_RWX_ITCM] = {
335 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
336 .prot_l1 = PMD_TYPE_TABLE,
337 .domain = DOMAIN_KERNEL,
338 },
339 [MT_MEMORY_RW_SO] = {
340 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
341 L_PTE_MT_UNCACHED | L_PTE_XN,
342 .prot_l1 = PMD_TYPE_TABLE,
343 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
344 PMD_SECT_UNCACHED | PMD_SECT_XN,
345 .domain = DOMAIN_KERNEL,
346 },
347 [MT_MEMORY_DMA_READY] = {
348 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
349 L_PTE_XN,
350 .prot_l1 = PMD_TYPE_TABLE,
351 .domain = DOMAIN_KERNEL,
352 },
353};
354
355const struct mem_type *get_mem_type(unsigned int type)
356{
357 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
358}
359EXPORT_SYMBOL(get_mem_type);
360
361static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr);
362
363static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS]
364 __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata;
365
366static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr)
367{
368 return &bm_pte[pte_index(addr)];
369}
370
371static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr)
372{
373 return pte_offset_kernel(dir, addr);
374}
375
376static inline pmd_t * __init fixmap_pmd(unsigned long addr)
377{
378 pgd_t *pgd = pgd_offset_k(addr);
379 pud_t *pud = pud_offset(pgd, addr);
380 pmd_t *pmd = pmd_offset(pud, addr);
381
382 return pmd;
383}
384
385void __init early_fixmap_init(void)
386{
387 pmd_t *pmd;
388
389 /*
390 * The early fixmap range spans multiple pmds, for which
391 * we are not prepared:
392 */
393 BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT)
394 != FIXADDR_TOP >> PMD_SHIFT);
395
396 pmd = fixmap_pmd(FIXADDR_TOP);
397 pmd_populate_kernel(&init_mm, pmd, bm_pte);
398
399 pte_offset_fixmap = pte_offset_early_fixmap;
400}
401
402/*
403 * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range().
404 * As a result, this can only be called with preemption disabled, as under
405 * stop_machine().
406 */
407void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
408{
409 unsigned long vaddr = __fix_to_virt(idx);
410 pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr);
411
412 /* Make sure fixmap region does not exceed available allocation. */
413 BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) >
414 FIXADDR_END);
415 BUG_ON(idx >= __end_of_fixed_addresses);
416
417 if (pgprot_val(prot))
418 set_pte_at(NULL, vaddr, pte,
419 pfn_pte(phys >> PAGE_SHIFT, prot));
420 else
421 pte_clear(NULL, vaddr, pte);
422 local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
423}
424
425/*
426 * Adjust the PMD section entries according to the CPU in use.
427 */
428static void __init build_mem_type_table(void)
429{
430 struct cachepolicy *cp;
431 unsigned int cr = get_cr();
432 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
433 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
434 int cpu_arch = cpu_architecture();
435 int i;
436
437 if (cpu_arch < CPU_ARCH_ARMv6) {
438#if defined(CONFIG_CPU_DCACHE_DISABLE)
439 if (cachepolicy > CPOLICY_BUFFERED)
440 cachepolicy = CPOLICY_BUFFERED;
441#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
442 if (cachepolicy > CPOLICY_WRITETHROUGH)
443 cachepolicy = CPOLICY_WRITETHROUGH;
444#endif
445 }
446 if (cpu_arch < CPU_ARCH_ARMv5) {
447 if (cachepolicy >= CPOLICY_WRITEALLOC)
448 cachepolicy = CPOLICY_WRITEBACK;
449 ecc_mask = 0;
450 }
451
452 if (is_smp()) {
453 if (cachepolicy != CPOLICY_WRITEALLOC) {
454 pr_warn("Forcing write-allocate cache policy for SMP\n");
455 cachepolicy = CPOLICY_WRITEALLOC;
456 }
457 if (!(initial_pmd_value & PMD_SECT_S)) {
458 pr_warn("Forcing shared mappings for SMP\n");
459 initial_pmd_value |= PMD_SECT_S;
460 }
461 }
462
463 /*
464 * Strip out features not present on earlier architectures.
465 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
466 * without extended page tables don't have the 'Shared' bit.
467 */
468 if (cpu_arch < CPU_ARCH_ARMv5)
469 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
470 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
471 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
472 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
473 mem_types[i].prot_sect &= ~PMD_SECT_S;
474
475 /*
476 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
477 * "update-able on write" bit on ARM610). However, Xscale and
478 * Xscale3 require this bit to be cleared.
479 */
480 if (cpu_is_xscale_family()) {
481 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
482 mem_types[i].prot_sect &= ~PMD_BIT4;
483 mem_types[i].prot_l1 &= ~PMD_BIT4;
484 }
485 } else if (cpu_arch < CPU_ARCH_ARMv6) {
486 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
487 if (mem_types[i].prot_l1)
488 mem_types[i].prot_l1 |= PMD_BIT4;
489 if (mem_types[i].prot_sect)
490 mem_types[i].prot_sect |= PMD_BIT4;
491 }
492 }
493
494 /*
495 * Mark the device areas according to the CPU/architecture.
496 */
497 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
498 if (!cpu_is_xsc3()) {
499 /*
500 * Mark device regions on ARMv6+ as execute-never
501 * to prevent speculative instruction fetches.
502 */
503 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
504 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
505 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
506 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
507
508 /* Also setup NX memory mapping */
509 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
510 }
511 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
512 /*
513 * For ARMv7 with TEX remapping,
514 * - shared device is SXCB=1100
515 * - nonshared device is SXCB=0100
516 * - write combine device mem is SXCB=0001
517 * (Uncached Normal memory)
518 */
519 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
520 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
521 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
522 } else if (cpu_is_xsc3()) {
523 /*
524 * For Xscale3,
525 * - shared device is TEXCB=00101
526 * - nonshared device is TEXCB=01000
527 * - write combine device mem is TEXCB=00100
528 * (Inner/Outer Uncacheable in xsc3 parlance)
529 */
530 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
531 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
532 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
533 } else {
534 /*
535 * For ARMv6 and ARMv7 without TEX remapping,
536 * - shared device is TEXCB=00001
537 * - nonshared device is TEXCB=01000
538 * - write combine device mem is TEXCB=00100
539 * (Uncached Normal in ARMv6 parlance).
540 */
541 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
542 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
543 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
544 }
545 } else {
546 /*
547 * On others, write combining is "Uncached/Buffered"
548 */
549 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
550 }
551
552 /*
553 * Now deal with the memory-type mappings
554 */
555 cp = &cache_policies[cachepolicy];
556 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
557 s2_pgprot = cp->pte_s2;
558 hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
559 s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
560
561#ifndef CONFIG_ARM_LPAE
562 /*
563 * We don't use domains on ARMv6 (since this causes problems with
564 * v6/v7 kernels), so we must use a separate memory type for user
565 * r/o, kernel r/w to map the vectors page.
566 */
567 if (cpu_arch == CPU_ARCH_ARMv6)
568 vecs_pgprot |= L_PTE_MT_VECTORS;
569
570 /*
571 * Check is it with support for the PXN bit
572 * in the Short-descriptor translation table format descriptors.
573 */
574 if (cpu_arch == CPU_ARCH_ARMv7 &&
575 (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) {
576 user_pmd_table |= PMD_PXNTABLE;
577 }
578#endif
579
580 /*
581 * ARMv6 and above have extended page tables.
582 */
583 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
584#ifndef CONFIG_ARM_LPAE
585 /*
586 * Mark cache clean areas and XIP ROM read only
587 * from SVC mode and no access from userspace.
588 */
589 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
590 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
591 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
592#endif
593
594 /*
595 * If the initial page tables were created with the S bit
596 * set, then we need to do the same here for the same
597 * reasons given in early_cachepolicy().
598 */
599 if (initial_pmd_value & PMD_SECT_S) {
600 user_pgprot |= L_PTE_SHARED;
601 kern_pgprot |= L_PTE_SHARED;
602 vecs_pgprot |= L_PTE_SHARED;
603 s2_pgprot |= L_PTE_SHARED;
604 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
605 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
606 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
607 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
608 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
609 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
610 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
611 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
612 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
613 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
614 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
615 }
616 }
617
618 /*
619 * Non-cacheable Normal - intended for memory areas that must
620 * not cause dirty cache line writebacks when used
621 */
622 if (cpu_arch >= CPU_ARCH_ARMv6) {
623 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
624 /* Non-cacheable Normal is XCB = 001 */
625 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
626 PMD_SECT_BUFFERED;
627 } else {
628 /* For both ARMv6 and non-TEX-remapping ARMv7 */
629 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
630 PMD_SECT_TEX(1);
631 }
632 } else {
633 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
634 }
635
636#ifdef CONFIG_ARM_LPAE
637 /*
638 * Do not generate access flag faults for the kernel mappings.
639 */
640 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
641 mem_types[i].prot_pte |= PTE_EXT_AF;
642 if (mem_types[i].prot_sect)
643 mem_types[i].prot_sect |= PMD_SECT_AF;
644 }
645 kern_pgprot |= PTE_EXT_AF;
646 vecs_pgprot |= PTE_EXT_AF;
647
648 /*
649 * Set PXN for user mappings
650 */
651 user_pgprot |= PTE_EXT_PXN;
652#endif
653
654 for (i = 0; i < 16; i++) {
655 pteval_t v = pgprot_val(protection_map[i]);
656 protection_map[i] = __pgprot(v | user_pgprot);
657 }
658
659 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
660 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
661
662 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
663 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
664 L_PTE_DIRTY | kern_pgprot);
665 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
666 pgprot_s2_device = __pgprot(s2_device_pgprot);
667 pgprot_hyp_device = __pgprot(hyp_device_pgprot);
668
669 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
670 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
671 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
672 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
673 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
674 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
675 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
676 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
677 mem_types[MT_ROM].prot_sect |= cp->pmd;
678
679 switch (cp->pmd) {
680 case PMD_SECT_WT:
681 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
682 break;
683 case PMD_SECT_WB:
684 case PMD_SECT_WBWA:
685 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
686 break;
687 }
688 pr_info("Memory policy: %sData cache %s\n",
689 ecc_mask ? "ECC enabled, " : "", cp->policy);
690
691 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
692 struct mem_type *t = &mem_types[i];
693 if (t->prot_l1)
694 t->prot_l1 |= PMD_DOMAIN(t->domain);
695 if (t->prot_sect)
696 t->prot_sect |= PMD_DOMAIN(t->domain);
697 }
698}
699
700#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
701pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
702 unsigned long size, pgprot_t vma_prot)
703{
704 if (!pfn_valid(pfn))
705 return pgprot_noncached(vma_prot);
706 else if (file->f_flags & O_SYNC)
707 return pgprot_writecombine(vma_prot);
708 return vma_prot;
709}
710EXPORT_SYMBOL(phys_mem_access_prot);
711#endif
712
713#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
714
715static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
716{
717 void *ptr = __va(memblock_alloc(sz, align));
718 memset(ptr, 0, sz);
719 return ptr;
720}
721
722static void __init *early_alloc(unsigned long sz)
723{
724 return early_alloc_aligned(sz, sz);
725}
726
727static void *__init late_alloc(unsigned long sz)
728{
729 void *ptr = (void *)__get_free_pages(PGALLOC_GFP, get_order(sz));
730
731 BUG_ON(!ptr);
732 return ptr;
733}
734
735static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr,
736 unsigned long prot,
737 void *(*alloc)(unsigned long sz))
738{
739 if (pmd_none(*pmd)) {
740 pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
741 __pmd_populate(pmd, __pa(pte), prot);
742 }
743 BUG_ON(pmd_bad(*pmd));
744 return pte_offset_kernel(pmd, addr);
745}
746
747static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr,
748 unsigned long prot)
749{
750 return arm_pte_alloc(pmd, addr, prot, early_alloc);
751}
752
753static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
754 unsigned long end, unsigned long pfn,
755 const struct mem_type *type,
756 void *(*alloc)(unsigned long sz),
757 bool ng)
758{
759 pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc);
760 do {
761 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
762 ng ? PTE_EXT_NG : 0);
763 pfn++;
764 } while (pte++, addr += PAGE_SIZE, addr != end);
765}
766
767static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
768 unsigned long end, phys_addr_t phys,
769 const struct mem_type *type, bool ng)
770{
771 pmd_t *p = pmd;
772
773#ifndef CONFIG_ARM_LPAE
774 /*
775 * In classic MMU format, puds and pmds are folded in to
776 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
777 * group of L1 entries making up one logical pointer to
778 * an L2 table (2MB), where as PMDs refer to the individual
779 * L1 entries (1MB). Hence increment to get the correct
780 * offset for odd 1MB sections.
781 * (See arch/arm/include/asm/pgtable-2level.h)
782 */
783 if (addr & SECTION_SIZE)
784 pmd++;
785#endif
786 do {
787 *pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0));
788 phys += SECTION_SIZE;
789 } while (pmd++, addr += SECTION_SIZE, addr != end);
790
791 flush_pmd_entry(p);
792}
793
794static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
795 unsigned long end, phys_addr_t phys,
796 const struct mem_type *type,
797 void *(*alloc)(unsigned long sz), bool ng)
798{
799 pmd_t *pmd = pmd_offset(pud, addr);
800 unsigned long next;
801
802 do {
803 /*
804 * With LPAE, we must loop over to map
805 * all the pmds for the given range.
806 */
807 next = pmd_addr_end(addr, end);
808
809 /*
810 * Try a section mapping - addr, next and phys must all be
811 * aligned to a section boundary.
812 */
813 if (type->prot_sect &&
814 ((addr | next | phys) & ~SECTION_MASK) == 0) {
815 __map_init_section(pmd, addr, next, phys, type, ng);
816 } else {
817 alloc_init_pte(pmd, addr, next,
818 __phys_to_pfn(phys), type, alloc, ng);
819 }
820
821 phys += next - addr;
822
823 } while (pmd++, addr = next, addr != end);
824}
825
826static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
827 unsigned long end, phys_addr_t phys,
828 const struct mem_type *type,
829 void *(*alloc)(unsigned long sz), bool ng)
830{
831 pud_t *pud = pud_offset(pgd, addr);
832 unsigned long next;
833
834 do {
835 next = pud_addr_end(addr, end);
836 alloc_init_pmd(pud, addr, next, phys, type, alloc, ng);
837 phys += next - addr;
838 } while (pud++, addr = next, addr != end);
839}
840
841#ifndef CONFIG_ARM_LPAE
842static void __init create_36bit_mapping(struct mm_struct *mm,
843 struct map_desc *md,
844 const struct mem_type *type,
845 bool ng)
846{
847 unsigned long addr, length, end;
848 phys_addr_t phys;
849 pgd_t *pgd;
850
851 addr = md->virtual;
852 phys = __pfn_to_phys(md->pfn);
853 length = PAGE_ALIGN(md->length);
854
855 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
856 pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n",
857 (long long)__pfn_to_phys((u64)md->pfn), addr);
858 return;
859 }
860
861 /* N.B. ARMv6 supersections are only defined to work with domain 0.
862 * Since domain assignments can in fact be arbitrary, the
863 * 'domain == 0' check below is required to insure that ARMv6
864 * supersections are only allocated for domain 0 regardless
865 * of the actual domain assignments in use.
866 */
867 if (type->domain) {
868 pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n",
869 (long long)__pfn_to_phys((u64)md->pfn), addr);
870 return;
871 }
872
873 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
874 pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n",
875 (long long)__pfn_to_phys((u64)md->pfn), addr);
876 return;
877 }
878
879 /*
880 * Shift bits [35:32] of address into bits [23:20] of PMD
881 * (See ARMv6 spec).
882 */
883 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
884
885 pgd = pgd_offset(mm, addr);
886 end = addr + length;
887 do {
888 pud_t *pud = pud_offset(pgd, addr);
889 pmd_t *pmd = pmd_offset(pud, addr);
890 int i;
891
892 for (i = 0; i < 16; i++)
893 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER |
894 (ng ? PMD_SECT_nG : 0));
895
896 addr += SUPERSECTION_SIZE;
897 phys += SUPERSECTION_SIZE;
898 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
899 } while (addr != end);
900}
901#endif /* !CONFIG_ARM_LPAE */
902
903static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md,
904 void *(*alloc)(unsigned long sz),
905 bool ng)
906{
907 unsigned long addr, length, end;
908 phys_addr_t phys;
909 const struct mem_type *type;
910 pgd_t *pgd;
911
912 type = &mem_types[md->type];
913
914#ifndef CONFIG_ARM_LPAE
915 /*
916 * Catch 36-bit addresses
917 */
918 if (md->pfn >= 0x100000) {
919 create_36bit_mapping(mm, md, type, ng);
920 return;
921 }
922#endif
923
924 addr = md->virtual & PAGE_MASK;
925 phys = __pfn_to_phys(md->pfn);
926 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
927
928 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
929 pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n",
930 (long long)__pfn_to_phys(md->pfn), addr);
931 return;
932 }
933
934 pgd = pgd_offset(mm, addr);
935 end = addr + length;
936 do {
937 unsigned long next = pgd_addr_end(addr, end);
938
939 alloc_init_pud(pgd, addr, next, phys, type, alloc, ng);
940
941 phys += next - addr;
942 addr = next;
943 } while (pgd++, addr != end);
944}
945
946/*
947 * Create the page directory entries and any necessary
948 * page tables for the mapping specified by `md'. We
949 * are able to cope here with varying sizes and address
950 * offsets, and we take full advantage of sections and
951 * supersections.
952 */
953static void __init create_mapping(struct map_desc *md)
954{
955 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
956 pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n",
957 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
958 return;
959 }
960
961 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
962 md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START &&
963 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
964 pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n",
965 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
966 }
967
968 __create_mapping(&init_mm, md, early_alloc, false);
969}
970
971void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md,
972 bool ng)
973{
974#ifdef CONFIG_ARM_LPAE
975 pud_t *pud = pud_alloc(mm, pgd_offset(mm, md->virtual), md->virtual);
976 if (WARN_ON(!pud))
977 return;
978 pmd_alloc(mm, pud, 0);
979#endif
980 __create_mapping(mm, md, late_alloc, ng);
981}
982
983/*
984 * Create the architecture specific mappings
985 */
986void __init iotable_init(struct map_desc *io_desc, int nr)
987{
988 struct map_desc *md;
989 struct vm_struct *vm;
990 struct static_vm *svm;
991
992 if (!nr)
993 return;
994
995 svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
996
997 for (md = io_desc; nr; md++, nr--) {
998 create_mapping(md);
999
1000 vm = &svm->vm;
1001 vm->addr = (void *)(md->virtual & PAGE_MASK);
1002 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
1003 vm->phys_addr = __pfn_to_phys(md->pfn);
1004 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
1005 vm->flags |= VM_ARM_MTYPE(md->type);
1006 vm->caller = iotable_init;
1007 add_static_vm_early(svm++);
1008 }
1009}
1010
1011void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
1012 void *caller)
1013{
1014 struct vm_struct *vm;
1015 struct static_vm *svm;
1016
1017 svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
1018
1019 vm = &svm->vm;
1020 vm->addr = (void *)addr;
1021 vm->size = size;
1022 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
1023 vm->caller = caller;
1024 add_static_vm_early(svm);
1025}
1026
1027#ifndef CONFIG_ARM_LPAE
1028
1029/*
1030 * The Linux PMD is made of two consecutive section entries covering 2MB
1031 * (see definition in include/asm/pgtable-2level.h). However a call to
1032 * create_mapping() may optimize static mappings by using individual
1033 * 1MB section mappings. This leaves the actual PMD potentially half
1034 * initialized if the top or bottom section entry isn't used, leaving it
1035 * open to problems if a subsequent ioremap() or vmalloc() tries to use
1036 * the virtual space left free by that unused section entry.
1037 *
1038 * Let's avoid the issue by inserting dummy vm entries covering the unused
1039 * PMD halves once the static mappings are in place.
1040 */
1041
1042static void __init pmd_empty_section_gap(unsigned long addr)
1043{
1044 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
1045}
1046
1047static void __init fill_pmd_gaps(void)
1048{
1049 struct static_vm *svm;
1050 struct vm_struct *vm;
1051 unsigned long addr, next = 0;
1052 pmd_t *pmd;
1053
1054 list_for_each_entry(svm, &static_vmlist, list) {
1055 vm = &svm->vm;
1056 addr = (unsigned long)vm->addr;
1057 if (addr < next)
1058 continue;
1059
1060 /*
1061 * Check if this vm starts on an odd section boundary.
1062 * If so and the first section entry for this PMD is free
1063 * then we block the corresponding virtual address.
1064 */
1065 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1066 pmd = pmd_off_k(addr);
1067 if (pmd_none(*pmd))
1068 pmd_empty_section_gap(addr & PMD_MASK);
1069 }
1070
1071 /*
1072 * Then check if this vm ends on an odd section boundary.
1073 * If so and the second section entry for this PMD is empty
1074 * then we block the corresponding virtual address.
1075 */
1076 addr += vm->size;
1077 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1078 pmd = pmd_off_k(addr) + 1;
1079 if (pmd_none(*pmd))
1080 pmd_empty_section_gap(addr);
1081 }
1082
1083 /* no need to look at any vm entry until we hit the next PMD */
1084 next = (addr + PMD_SIZE - 1) & PMD_MASK;
1085 }
1086}
1087
1088#else
1089#define fill_pmd_gaps() do { } while (0)
1090#endif
1091
1092#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
1093static void __init pci_reserve_io(void)
1094{
1095 struct static_vm *svm;
1096
1097 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1098 if (svm)
1099 return;
1100
1101 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1102}
1103#else
1104#define pci_reserve_io() do { } while (0)
1105#endif
1106
1107#ifdef CONFIG_DEBUG_LL
1108void __init debug_ll_io_init(void)
1109{
1110 struct map_desc map;
1111
1112 debug_ll_addr(&map.pfn, &map.virtual);
1113 if (!map.pfn || !map.virtual)
1114 return;
1115 map.pfn = __phys_to_pfn(map.pfn);
1116 map.virtual &= PAGE_MASK;
1117 map.length = PAGE_SIZE;
1118 map.type = MT_DEVICE;
1119 iotable_init(&map, 1);
1120}
1121#endif
1122
1123static void * __initdata vmalloc_min =
1124 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
1125
1126/*
1127 * vmalloc=size forces the vmalloc area to be exactly 'size'
1128 * bytes. This can be used to increase (or decrease) the vmalloc
1129 * area - the default is 240m.
1130 */
1131static int __init early_vmalloc(char *arg)
1132{
1133 unsigned long vmalloc_reserve = memparse(arg, NULL);
1134
1135 if (vmalloc_reserve < SZ_16M) {
1136 vmalloc_reserve = SZ_16M;
1137 pr_warn("vmalloc area too small, limiting to %luMB\n",
1138 vmalloc_reserve >> 20);
1139 }
1140
1141 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
1142 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
1143 pr_warn("vmalloc area is too big, limiting to %luMB\n",
1144 vmalloc_reserve >> 20);
1145 }
1146
1147 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
1148 return 0;
1149}
1150early_param("vmalloc", early_vmalloc);
1151
1152phys_addr_t arm_lowmem_limit __initdata = 0;
1153
1154void __init sanity_check_meminfo(void)
1155{
1156 phys_addr_t memblock_limit = 0;
1157 int highmem = 0;
1158 phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
1159 struct memblock_region *reg;
1160 bool should_use_highmem = false;
1161
1162 for_each_memblock(memory, reg) {
1163 phys_addr_t block_start = reg->base;
1164 phys_addr_t block_end = reg->base + reg->size;
1165 phys_addr_t size_limit = reg->size;
1166
1167 if (reg->base >= vmalloc_limit)
1168 highmem = 1;
1169 else
1170 size_limit = vmalloc_limit - reg->base;
1171
1172
1173 if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
1174
1175 if (highmem) {
1176 pr_notice("Ignoring RAM at %pa-%pa (!CONFIG_HIGHMEM)\n",
1177 &block_start, &block_end);
1178 memblock_remove(reg->base, reg->size);
1179 should_use_highmem = true;
1180 continue;
1181 }
1182
1183 if (reg->size > size_limit) {
1184 phys_addr_t overlap_size = reg->size - size_limit;
1185
1186 pr_notice("Truncating RAM at %pa-%pa to -%pa",
1187 &block_start, &block_end, &vmalloc_limit);
1188 memblock_remove(vmalloc_limit, overlap_size);
1189 block_end = vmalloc_limit;
1190 should_use_highmem = true;
1191 }
1192 }
1193
1194 if (!highmem) {
1195 if (block_end > arm_lowmem_limit) {
1196 if (reg->size > size_limit)
1197 arm_lowmem_limit = vmalloc_limit;
1198 else
1199 arm_lowmem_limit = block_end;
1200 }
1201
1202 /*
1203 * Find the first non-pmd-aligned page, and point
1204 * memblock_limit at it. This relies on rounding the
1205 * limit down to be pmd-aligned, which happens at the
1206 * end of this function.
1207 *
1208 * With this algorithm, the start or end of almost any
1209 * bank can be non-pmd-aligned. The only exception is
1210 * that the start of the bank 0 must be section-
1211 * aligned, since otherwise memory would need to be
1212 * allocated when mapping the start of bank 0, which
1213 * occurs before any free memory is mapped.
1214 */
1215 if (!memblock_limit) {
1216 if (!IS_ALIGNED(block_start, PMD_SIZE))
1217 memblock_limit = block_start;
1218 else if (!IS_ALIGNED(block_end, PMD_SIZE))
1219 memblock_limit = arm_lowmem_limit;
1220 }
1221
1222 }
1223 }
1224
1225 if (should_use_highmem)
1226 pr_notice("Consider using a HIGHMEM enabled kernel.\n");
1227
1228 high_memory = __va(arm_lowmem_limit - 1) + 1;
1229
1230 /*
1231 * Round the memblock limit down to a pmd size. This
1232 * helps to ensure that we will allocate memory from the
1233 * last full pmd, which should be mapped.
1234 */
1235 if (memblock_limit)
1236 memblock_limit = round_down(memblock_limit, PMD_SIZE);
1237 if (!memblock_limit)
1238 memblock_limit = arm_lowmem_limit;
1239
1240 memblock_set_current_limit(memblock_limit);
1241}
1242
1243static inline void prepare_page_table(void)
1244{
1245 unsigned long addr;
1246 phys_addr_t end;
1247
1248 /*
1249 * Clear out all the mappings below the kernel image.
1250 */
1251 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1252 pmd_clear(pmd_off_k(addr));
1253
1254#ifdef CONFIG_XIP_KERNEL
1255 /* The XIP kernel is mapped in the module area -- skip over it */
1256 addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK;
1257#endif
1258 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1259 pmd_clear(pmd_off_k(addr));
1260
1261 /*
1262 * Find the end of the first block of lowmem.
1263 */
1264 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1265 if (end >= arm_lowmem_limit)
1266 end = arm_lowmem_limit;
1267
1268 /*
1269 * Clear out all the kernel space mappings, except for the first
1270 * memory bank, up to the vmalloc region.
1271 */
1272 for (addr = __phys_to_virt(end);
1273 addr < VMALLOC_START; addr += PMD_SIZE)
1274 pmd_clear(pmd_off_k(addr));
1275}
1276
1277#ifdef CONFIG_ARM_LPAE
1278/* the first page is reserved for pgd */
1279#define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1280 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1281#else
1282#define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1283#endif
1284
1285/*
1286 * Reserve the special regions of memory
1287 */
1288void __init arm_mm_memblock_reserve(void)
1289{
1290 /*
1291 * Reserve the page tables. These are already in use,
1292 * and can only be in node 0.
1293 */
1294 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1295
1296#ifdef CONFIG_SA1111
1297 /*
1298 * Because of the SA1111 DMA bug, we want to preserve our
1299 * precious DMA-able memory...
1300 */
1301 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1302#endif
1303}
1304
1305/*
1306 * Set up the device mappings. Since we clear out the page tables for all
1307 * mappings above VMALLOC_START, except early fixmap, we might remove debug
1308 * device mappings. This means earlycon can be used to debug this function
1309 * Any other function or debugging method which may touch any device _will_
1310 * crash the kernel.
1311 */
1312static void __init devicemaps_init(const struct machine_desc *mdesc)
1313{
1314 struct map_desc map;
1315 unsigned long addr;
1316 void *vectors;
1317
1318 /*
1319 * Allocate the vector page early.
1320 */
1321 vectors = early_alloc(PAGE_SIZE * 2);
1322
1323 early_trap_init(vectors);
1324
1325 /*
1326 * Clear page table except top pmd used by early fixmaps
1327 */
1328 for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE)
1329 pmd_clear(pmd_off_k(addr));
1330
1331 /*
1332 * Map the kernel if it is XIP.
1333 * It is always first in the modulearea.
1334 */
1335#ifdef CONFIG_XIP_KERNEL
1336 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1337 map.virtual = MODULES_VADDR;
1338 map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1339 map.type = MT_ROM;
1340 create_mapping(&map);
1341#endif
1342
1343 /*
1344 * Map the cache flushing regions.
1345 */
1346#ifdef FLUSH_BASE
1347 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1348 map.virtual = FLUSH_BASE;
1349 map.length = SZ_1M;
1350 map.type = MT_CACHECLEAN;
1351 create_mapping(&map);
1352#endif
1353#ifdef FLUSH_BASE_MINICACHE
1354 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1355 map.virtual = FLUSH_BASE_MINICACHE;
1356 map.length = SZ_1M;
1357 map.type = MT_MINICLEAN;
1358 create_mapping(&map);
1359#endif
1360
1361 /*
1362 * Create a mapping for the machine vectors at the high-vectors
1363 * location (0xffff0000). If we aren't using high-vectors, also
1364 * create a mapping at the low-vectors virtual address.
1365 */
1366 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1367 map.virtual = 0xffff0000;
1368 map.length = PAGE_SIZE;
1369#ifdef CONFIG_KUSER_HELPERS
1370 map.type = MT_HIGH_VECTORS;
1371#else
1372 map.type = MT_LOW_VECTORS;
1373#endif
1374 create_mapping(&map);
1375
1376 if (!vectors_high()) {
1377 map.virtual = 0;
1378 map.length = PAGE_SIZE * 2;
1379 map.type = MT_LOW_VECTORS;
1380 create_mapping(&map);
1381 }
1382
1383 /* Now create a kernel read-only mapping */
1384 map.pfn += 1;
1385 map.virtual = 0xffff0000 + PAGE_SIZE;
1386 map.length = PAGE_SIZE;
1387 map.type = MT_LOW_VECTORS;
1388 create_mapping(&map);
1389
1390 /*
1391 * Ask the machine support to map in the statically mapped devices.
1392 */
1393 if (mdesc->map_io)
1394 mdesc->map_io();
1395 else
1396 debug_ll_io_init();
1397 fill_pmd_gaps();
1398
1399 /* Reserve fixed i/o space in VMALLOC region */
1400 pci_reserve_io();
1401
1402 /*
1403 * Finally flush the caches and tlb to ensure that we're in a
1404 * consistent state wrt the writebuffer. This also ensures that
1405 * any write-allocated cache lines in the vector page are written
1406 * back. After this point, we can start to touch devices again.
1407 */
1408 local_flush_tlb_all();
1409 flush_cache_all();
1410
1411 /* Enable asynchronous aborts */
1412 early_abt_enable();
1413}
1414
1415static void __init kmap_init(void)
1416{
1417#ifdef CONFIG_HIGHMEM
1418 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1419 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1420#endif
1421
1422 early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START,
1423 _PAGE_KERNEL_TABLE);
1424}
1425
1426static void __init map_lowmem(void)
1427{
1428 struct memblock_region *reg;
1429#ifdef CONFIG_XIP_KERNEL
1430 phys_addr_t kernel_x_start = round_down(__pa(_sdata), SECTION_SIZE);
1431#else
1432 phys_addr_t kernel_x_start = round_down(__pa(_stext), SECTION_SIZE);
1433#endif
1434 phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1435
1436 /* Map all the lowmem memory banks. */
1437 for_each_memblock(memory, reg) {
1438 phys_addr_t start = reg->base;
1439 phys_addr_t end = start + reg->size;
1440 struct map_desc map;
1441
1442 if (memblock_is_nomap(reg))
1443 continue;
1444
1445 if (end > arm_lowmem_limit)
1446 end = arm_lowmem_limit;
1447 if (start >= end)
1448 break;
1449
1450 if (end < kernel_x_start) {
1451 map.pfn = __phys_to_pfn(start);
1452 map.virtual = __phys_to_virt(start);
1453 map.length = end - start;
1454 map.type = MT_MEMORY_RWX;
1455
1456 create_mapping(&map);
1457 } else if (start >= kernel_x_end) {
1458 map.pfn = __phys_to_pfn(start);
1459 map.virtual = __phys_to_virt(start);
1460 map.length = end - start;
1461 map.type = MT_MEMORY_RW;
1462
1463 create_mapping(&map);
1464 } else {
1465 /* This better cover the entire kernel */
1466 if (start < kernel_x_start) {
1467 map.pfn = __phys_to_pfn(start);
1468 map.virtual = __phys_to_virt(start);
1469 map.length = kernel_x_start - start;
1470 map.type = MT_MEMORY_RW;
1471
1472 create_mapping(&map);
1473 }
1474
1475 map.pfn = __phys_to_pfn(kernel_x_start);
1476 map.virtual = __phys_to_virt(kernel_x_start);
1477 map.length = kernel_x_end - kernel_x_start;
1478 map.type = MT_MEMORY_RWX;
1479
1480 create_mapping(&map);
1481
1482 if (kernel_x_end < end) {
1483 map.pfn = __phys_to_pfn(kernel_x_end);
1484 map.virtual = __phys_to_virt(kernel_x_end);
1485 map.length = end - kernel_x_end;
1486 map.type = MT_MEMORY_RW;
1487
1488 create_mapping(&map);
1489 }
1490 }
1491 }
1492}
1493
1494#ifdef CONFIG_ARM_PV_FIXUP
1495extern unsigned long __atags_pointer;
1496typedef void pgtables_remap(long long offset, unsigned long pgd, void *bdata);
1497pgtables_remap lpae_pgtables_remap_asm;
1498
1499/*
1500 * early_paging_init() recreates boot time page table setup, allowing machines
1501 * to switch over to a high (>4G) address space on LPAE systems
1502 */
1503void __init early_paging_init(const struct machine_desc *mdesc)
1504{
1505 pgtables_remap *lpae_pgtables_remap;
1506 unsigned long pa_pgd;
1507 unsigned int cr, ttbcr;
1508 long long offset;
1509 void *boot_data;
1510
1511 if (!mdesc->pv_fixup)
1512 return;
1513
1514 offset = mdesc->pv_fixup();
1515 if (offset == 0)
1516 return;
1517
1518 /*
1519 * Get the address of the remap function in the 1:1 identity
1520 * mapping setup by the early page table assembly code. We
1521 * must get this prior to the pv update. The following barrier
1522 * ensures that this is complete before we fixup any P:V offsets.
1523 */
1524 lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm);
1525 pa_pgd = __pa(swapper_pg_dir);
1526 boot_data = __va(__atags_pointer);
1527 barrier();
1528
1529 pr_info("Switching physical address space to 0x%08llx\n",
1530 (u64)PHYS_OFFSET + offset);
1531
1532 /* Re-set the phys pfn offset, and the pv offset */
1533 __pv_offset += offset;
1534 __pv_phys_pfn_offset += PFN_DOWN(offset);
1535
1536 /* Run the patch stub to update the constants */
1537 fixup_pv_table(&__pv_table_begin,
1538 (&__pv_table_end - &__pv_table_begin) << 2);
1539
1540 /*
1541 * We changing not only the virtual to physical mapping, but also
1542 * the physical addresses used to access memory. We need to flush
1543 * all levels of cache in the system with caching disabled to
1544 * ensure that all data is written back, and nothing is prefetched
1545 * into the caches. We also need to prevent the TLB walkers
1546 * allocating into the caches too. Note that this is ARMv7 LPAE
1547 * specific.
1548 */
1549 cr = get_cr();
1550 set_cr(cr & ~(CR_I | CR_C));
1551 asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr));
1552 asm volatile("mcr p15, 0, %0, c2, c0, 2"
1553 : : "r" (ttbcr & ~(3 << 8 | 3 << 10)));
1554 flush_cache_all();
1555
1556 /*
1557 * Fixup the page tables - this must be in the idmap region as
1558 * we need to disable the MMU to do this safely, and hence it
1559 * needs to be assembly. It's fairly simple, as we're using the
1560 * temporary tables setup by the initial assembly code.
1561 */
1562 lpae_pgtables_remap(offset, pa_pgd, boot_data);
1563
1564 /* Re-enable the caches and cacheable TLB walks */
1565 asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr));
1566 set_cr(cr);
1567}
1568
1569#else
1570
1571void __init early_paging_init(const struct machine_desc *mdesc)
1572{
1573 long long offset;
1574
1575 if (!mdesc->pv_fixup)
1576 return;
1577
1578 offset = mdesc->pv_fixup();
1579 if (offset == 0)
1580 return;
1581
1582 pr_crit("Physical address space modification is only to support Keystone2.\n");
1583 pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n");
1584 pr_crit("feature. Your kernel may crash now, have a good day.\n");
1585 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1586}
1587
1588#endif
1589
1590static void __init early_fixmap_shutdown(void)
1591{
1592 int i;
1593 unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1);
1594
1595 pte_offset_fixmap = pte_offset_late_fixmap;
1596 pmd_clear(fixmap_pmd(va));
1597 local_flush_tlb_kernel_page(va);
1598
1599 for (i = 0; i < __end_of_permanent_fixed_addresses; i++) {
1600 pte_t *pte;
1601 struct map_desc map;
1602
1603 map.virtual = fix_to_virt(i);
1604 pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual);
1605
1606 /* Only i/o device mappings are supported ATM */
1607 if (pte_none(*pte) ||
1608 (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED)
1609 continue;
1610
1611 map.pfn = pte_pfn(*pte);
1612 map.type = MT_DEVICE;
1613 map.length = PAGE_SIZE;
1614
1615 create_mapping(&map);
1616 }
1617}
1618
1619/*
1620 * paging_init() sets up the page tables, initialises the zone memory
1621 * maps, and sets up the zero page, bad page and bad page tables.
1622 */
1623void __init paging_init(const struct machine_desc *mdesc)
1624{
1625 void *zero_page;
1626
1627 build_mem_type_table();
1628 prepare_page_table();
1629 map_lowmem();
1630 memblock_set_current_limit(arm_lowmem_limit);
1631 dma_contiguous_remap();
1632 early_fixmap_shutdown();
1633 devicemaps_init(mdesc);
1634 kmap_init();
1635 tcm_init();
1636
1637 top_pmd = pmd_off_k(0xffff0000);
1638
1639 /* allocate the zero page. */
1640 zero_page = early_alloc(PAGE_SIZE);
1641
1642 bootmem_init();
1643
1644 empty_zero_page = virt_to_page(zero_page);
1645 __flush_dcache_page(NULL, empty_zero_page);
1646}
1/*
2 * linux/arch/arm/mm/mmu.c
3 *
4 * Copyright (C) 1995-2005 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/mman.h>
15#include <linux/nodemask.h>
16#include <linux/memblock.h>
17#include <linux/fs.h>
18#include <linux/vmalloc.h>
19#include <linux/sizes.h>
20
21#include <asm/cp15.h>
22#include <asm/cputype.h>
23#include <asm/sections.h>
24#include <asm/cachetype.h>
25#include <asm/sections.h>
26#include <asm/setup.h>
27#include <asm/smp_plat.h>
28#include <asm/tlb.h>
29#include <asm/highmem.h>
30#include <asm/system_info.h>
31#include <asm/traps.h>
32#include <asm/procinfo.h>
33#include <asm/memory.h>
34
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37#include <asm/mach/pci.h>
38
39#include "mm.h"
40#include "tcm.h"
41
42/*
43 * empty_zero_page is a special page that is used for
44 * zero-initialized data and COW.
45 */
46struct page *empty_zero_page;
47EXPORT_SYMBOL(empty_zero_page);
48
49/*
50 * The pmd table for the upper-most set of pages.
51 */
52pmd_t *top_pmd;
53
54#define CPOLICY_UNCACHED 0
55#define CPOLICY_BUFFERED 1
56#define CPOLICY_WRITETHROUGH 2
57#define CPOLICY_WRITEBACK 3
58#define CPOLICY_WRITEALLOC 4
59
60static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
61static unsigned int ecc_mask __initdata = 0;
62pgprot_t pgprot_user;
63pgprot_t pgprot_kernel;
64pgprot_t pgprot_hyp_device;
65pgprot_t pgprot_s2;
66pgprot_t pgprot_s2_device;
67
68EXPORT_SYMBOL(pgprot_user);
69EXPORT_SYMBOL(pgprot_kernel);
70
71struct cachepolicy {
72 const char policy[16];
73 unsigned int cr_mask;
74 pmdval_t pmd;
75 pteval_t pte;
76 pteval_t pte_s2;
77};
78
79#ifdef CONFIG_ARM_LPAE
80#define s2_policy(policy) policy
81#else
82#define s2_policy(policy) 0
83#endif
84
85static struct cachepolicy cache_policies[] __initdata = {
86 {
87 .policy = "uncached",
88 .cr_mask = CR_W|CR_C,
89 .pmd = PMD_SECT_UNCACHED,
90 .pte = L_PTE_MT_UNCACHED,
91 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
92 }, {
93 .policy = "buffered",
94 .cr_mask = CR_C,
95 .pmd = PMD_SECT_BUFFERED,
96 .pte = L_PTE_MT_BUFFERABLE,
97 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
98 }, {
99 .policy = "writethrough",
100 .cr_mask = 0,
101 .pmd = PMD_SECT_WT,
102 .pte = L_PTE_MT_WRITETHROUGH,
103 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
104 }, {
105 .policy = "writeback",
106 .cr_mask = 0,
107 .pmd = PMD_SECT_WB,
108 .pte = L_PTE_MT_WRITEBACK,
109 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
110 }, {
111 .policy = "writealloc",
112 .cr_mask = 0,
113 .pmd = PMD_SECT_WBWA,
114 .pte = L_PTE_MT_WRITEALLOC,
115 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
116 }
117};
118
119#ifdef CONFIG_CPU_CP15
120/*
121 * These are useful for identifying cache coherency
122 * problems by allowing the cache or the cache and
123 * writebuffer to be turned off. (Note: the write
124 * buffer should not be on and the cache off).
125 */
126static int __init early_cachepolicy(char *p)
127{
128 int i;
129
130 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
131 int len = strlen(cache_policies[i].policy);
132
133 if (memcmp(p, cache_policies[i].policy, len) == 0) {
134 cachepolicy = i;
135 cr_alignment &= ~cache_policies[i].cr_mask;
136 cr_no_alignment &= ~cache_policies[i].cr_mask;
137 break;
138 }
139 }
140 if (i == ARRAY_SIZE(cache_policies))
141 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
142 /*
143 * This restriction is partly to do with the way we boot; it is
144 * unpredictable to have memory mapped using two different sets of
145 * memory attributes (shared, type, and cache attribs). We can not
146 * change these attributes once the initial assembly has setup the
147 * page tables.
148 */
149 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
150 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
151 cachepolicy = CPOLICY_WRITEBACK;
152 }
153 flush_cache_all();
154 set_cr(cr_alignment);
155 return 0;
156}
157early_param("cachepolicy", early_cachepolicy);
158
159static int __init early_nocache(char *__unused)
160{
161 char *p = "buffered";
162 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
163 early_cachepolicy(p);
164 return 0;
165}
166early_param("nocache", early_nocache);
167
168static int __init early_nowrite(char *__unused)
169{
170 char *p = "uncached";
171 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
172 early_cachepolicy(p);
173 return 0;
174}
175early_param("nowb", early_nowrite);
176
177#ifndef CONFIG_ARM_LPAE
178static int __init early_ecc(char *p)
179{
180 if (memcmp(p, "on", 2) == 0)
181 ecc_mask = PMD_PROTECTION;
182 else if (memcmp(p, "off", 3) == 0)
183 ecc_mask = 0;
184 return 0;
185}
186early_param("ecc", early_ecc);
187#endif
188
189static int __init noalign_setup(char *__unused)
190{
191 cr_alignment &= ~CR_A;
192 cr_no_alignment &= ~CR_A;
193 set_cr(cr_alignment);
194 return 1;
195}
196__setup("noalign", noalign_setup);
197
198#ifndef CONFIG_SMP
199void adjust_cr(unsigned long mask, unsigned long set)
200{
201 unsigned long flags;
202
203 mask &= ~CR_A;
204
205 set &= mask;
206
207 local_irq_save(flags);
208
209 cr_no_alignment = (cr_no_alignment & ~mask) | set;
210 cr_alignment = (cr_alignment & ~mask) | set;
211
212 set_cr((get_cr() & ~mask) | set);
213
214 local_irq_restore(flags);
215}
216#endif
217
218#else /* ifdef CONFIG_CPU_CP15 */
219
220static int __init early_cachepolicy(char *p)
221{
222 pr_warning("cachepolicy kernel parameter not supported without cp15\n");
223}
224early_param("cachepolicy", early_cachepolicy);
225
226static int __init noalign_setup(char *__unused)
227{
228 pr_warning("noalign kernel parameter not supported without cp15\n");
229}
230__setup("noalign", noalign_setup);
231
232#endif /* ifdef CONFIG_CPU_CP15 / else */
233
234#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
235#define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
236#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
237
238static struct mem_type mem_types[] = {
239 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
240 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
241 L_PTE_SHARED,
242 .prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) |
243 s2_policy(L_PTE_S2_MT_DEV_SHARED) |
244 L_PTE_SHARED,
245 .prot_l1 = PMD_TYPE_TABLE,
246 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
247 .domain = DOMAIN_IO,
248 },
249 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
250 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
251 .prot_l1 = PMD_TYPE_TABLE,
252 .prot_sect = PROT_SECT_DEVICE,
253 .domain = DOMAIN_IO,
254 },
255 [MT_DEVICE_CACHED] = { /* ioremap_cached */
256 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
257 .prot_l1 = PMD_TYPE_TABLE,
258 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
259 .domain = DOMAIN_IO,
260 },
261 [MT_DEVICE_WC] = { /* ioremap_wc */
262 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
263 .prot_l1 = PMD_TYPE_TABLE,
264 .prot_sect = PROT_SECT_DEVICE,
265 .domain = DOMAIN_IO,
266 },
267 [MT_UNCACHED] = {
268 .prot_pte = PROT_PTE_DEVICE,
269 .prot_l1 = PMD_TYPE_TABLE,
270 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
271 .domain = DOMAIN_IO,
272 },
273 [MT_CACHECLEAN] = {
274 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
275 .domain = DOMAIN_KERNEL,
276 },
277#ifndef CONFIG_ARM_LPAE
278 [MT_MINICLEAN] = {
279 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
280 .domain = DOMAIN_KERNEL,
281 },
282#endif
283 [MT_LOW_VECTORS] = {
284 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
285 L_PTE_RDONLY,
286 .prot_l1 = PMD_TYPE_TABLE,
287 .domain = DOMAIN_USER,
288 },
289 [MT_HIGH_VECTORS] = {
290 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
291 L_PTE_USER | L_PTE_RDONLY,
292 .prot_l1 = PMD_TYPE_TABLE,
293 .domain = DOMAIN_USER,
294 },
295 [MT_MEMORY_RWX] = {
296 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
297 .prot_l1 = PMD_TYPE_TABLE,
298 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
299 .domain = DOMAIN_KERNEL,
300 },
301 [MT_MEMORY_RW] = {
302 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
303 L_PTE_XN,
304 .prot_l1 = PMD_TYPE_TABLE,
305 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
306 .domain = DOMAIN_KERNEL,
307 },
308 [MT_ROM] = {
309 .prot_sect = PMD_TYPE_SECT,
310 .domain = DOMAIN_KERNEL,
311 },
312 [MT_MEMORY_RWX_NONCACHED] = {
313 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
314 L_PTE_MT_BUFFERABLE,
315 .prot_l1 = PMD_TYPE_TABLE,
316 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
317 .domain = DOMAIN_KERNEL,
318 },
319 [MT_MEMORY_RW_DTCM] = {
320 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
321 L_PTE_XN,
322 .prot_l1 = PMD_TYPE_TABLE,
323 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
324 .domain = DOMAIN_KERNEL,
325 },
326 [MT_MEMORY_RWX_ITCM] = {
327 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
328 .prot_l1 = PMD_TYPE_TABLE,
329 .domain = DOMAIN_KERNEL,
330 },
331 [MT_MEMORY_RW_SO] = {
332 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
333 L_PTE_MT_UNCACHED | L_PTE_XN,
334 .prot_l1 = PMD_TYPE_TABLE,
335 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
336 PMD_SECT_UNCACHED | PMD_SECT_XN,
337 .domain = DOMAIN_KERNEL,
338 },
339 [MT_MEMORY_DMA_READY] = {
340 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
341 L_PTE_XN,
342 .prot_l1 = PMD_TYPE_TABLE,
343 .domain = DOMAIN_KERNEL,
344 },
345};
346
347const struct mem_type *get_mem_type(unsigned int type)
348{
349 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
350}
351EXPORT_SYMBOL(get_mem_type);
352
353#define PTE_SET_FN(_name, pteop) \
354static int pte_set_##_name(pte_t *ptep, pgtable_t token, unsigned long addr, \
355 void *data) \
356{ \
357 pte_t pte = pteop(*ptep); \
358\
359 set_pte_ext(ptep, pte, 0); \
360 return 0; \
361} \
362
363#define SET_MEMORY_FN(_name, callback) \
364int set_memory_##_name(unsigned long addr, int numpages) \
365{ \
366 unsigned long start = addr; \
367 unsigned long size = PAGE_SIZE*numpages; \
368 unsigned end = start + size; \
369\
370 if (start < MODULES_VADDR || start >= MODULES_END) \
371 return -EINVAL;\
372\
373 if (end < MODULES_VADDR || end >= MODULES_END) \
374 return -EINVAL; \
375\
376 apply_to_page_range(&init_mm, start, size, callback, NULL); \
377 flush_tlb_kernel_range(start, end); \
378 return 0;\
379}
380
381PTE_SET_FN(ro, pte_wrprotect)
382PTE_SET_FN(rw, pte_mkwrite)
383PTE_SET_FN(x, pte_mkexec)
384PTE_SET_FN(nx, pte_mknexec)
385
386SET_MEMORY_FN(ro, pte_set_ro)
387SET_MEMORY_FN(rw, pte_set_rw)
388SET_MEMORY_FN(x, pte_set_x)
389SET_MEMORY_FN(nx, pte_set_nx)
390
391/*
392 * Adjust the PMD section entries according to the CPU in use.
393 */
394static void __init build_mem_type_table(void)
395{
396 struct cachepolicy *cp;
397 unsigned int cr = get_cr();
398 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
399 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
400 int cpu_arch = cpu_architecture();
401 int i;
402
403 if (cpu_arch < CPU_ARCH_ARMv6) {
404#if defined(CONFIG_CPU_DCACHE_DISABLE)
405 if (cachepolicy > CPOLICY_BUFFERED)
406 cachepolicy = CPOLICY_BUFFERED;
407#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
408 if (cachepolicy > CPOLICY_WRITETHROUGH)
409 cachepolicy = CPOLICY_WRITETHROUGH;
410#endif
411 }
412 if (cpu_arch < CPU_ARCH_ARMv5) {
413 if (cachepolicy >= CPOLICY_WRITEALLOC)
414 cachepolicy = CPOLICY_WRITEBACK;
415 ecc_mask = 0;
416 }
417 if (is_smp())
418 cachepolicy = CPOLICY_WRITEALLOC;
419
420 /*
421 * Strip out features not present on earlier architectures.
422 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
423 * without extended page tables don't have the 'Shared' bit.
424 */
425 if (cpu_arch < CPU_ARCH_ARMv5)
426 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
427 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
428 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
429 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
430 mem_types[i].prot_sect &= ~PMD_SECT_S;
431
432 /*
433 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
434 * "update-able on write" bit on ARM610). However, Xscale and
435 * Xscale3 require this bit to be cleared.
436 */
437 if (cpu_is_xscale() || cpu_is_xsc3()) {
438 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
439 mem_types[i].prot_sect &= ~PMD_BIT4;
440 mem_types[i].prot_l1 &= ~PMD_BIT4;
441 }
442 } else if (cpu_arch < CPU_ARCH_ARMv6) {
443 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
444 if (mem_types[i].prot_l1)
445 mem_types[i].prot_l1 |= PMD_BIT4;
446 if (mem_types[i].prot_sect)
447 mem_types[i].prot_sect |= PMD_BIT4;
448 }
449 }
450
451 /*
452 * Mark the device areas according to the CPU/architecture.
453 */
454 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
455 if (!cpu_is_xsc3()) {
456 /*
457 * Mark device regions on ARMv6+ as execute-never
458 * to prevent speculative instruction fetches.
459 */
460 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
461 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
462 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
463 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
464
465 /* Also setup NX memory mapping */
466 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
467 }
468 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
469 /*
470 * For ARMv7 with TEX remapping,
471 * - shared device is SXCB=1100
472 * - nonshared device is SXCB=0100
473 * - write combine device mem is SXCB=0001
474 * (Uncached Normal memory)
475 */
476 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
477 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
478 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
479 } else if (cpu_is_xsc3()) {
480 /*
481 * For Xscale3,
482 * - shared device is TEXCB=00101
483 * - nonshared device is TEXCB=01000
484 * - write combine device mem is TEXCB=00100
485 * (Inner/Outer Uncacheable in xsc3 parlance)
486 */
487 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
488 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
489 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
490 } else {
491 /*
492 * For ARMv6 and ARMv7 without TEX remapping,
493 * - shared device is TEXCB=00001
494 * - nonshared device is TEXCB=01000
495 * - write combine device mem is TEXCB=00100
496 * (Uncached Normal in ARMv6 parlance).
497 */
498 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
499 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
500 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
501 }
502 } else {
503 /*
504 * On others, write combining is "Uncached/Buffered"
505 */
506 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
507 }
508
509 /*
510 * Now deal with the memory-type mappings
511 */
512 cp = &cache_policies[cachepolicy];
513 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
514 s2_pgprot = cp->pte_s2;
515 hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
516 s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
517
518 /*
519 * We don't use domains on ARMv6 (since this causes problems with
520 * v6/v7 kernels), so we must use a separate memory type for user
521 * r/o, kernel r/w to map the vectors page.
522 */
523#ifndef CONFIG_ARM_LPAE
524 if (cpu_arch == CPU_ARCH_ARMv6)
525 vecs_pgprot |= L_PTE_MT_VECTORS;
526#endif
527
528 /*
529 * ARMv6 and above have extended page tables.
530 */
531 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
532#ifndef CONFIG_ARM_LPAE
533 /*
534 * Mark cache clean areas and XIP ROM read only
535 * from SVC mode and no access from userspace.
536 */
537 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
538 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
539 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
540#endif
541
542 if (is_smp()) {
543 /*
544 * Mark memory with the "shared" attribute
545 * for SMP systems
546 */
547 user_pgprot |= L_PTE_SHARED;
548 kern_pgprot |= L_PTE_SHARED;
549 vecs_pgprot |= L_PTE_SHARED;
550 s2_pgprot |= L_PTE_SHARED;
551 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
552 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
553 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
554 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
555 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
556 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
557 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
558 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
559 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
560 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
561 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
562 }
563 }
564
565 /*
566 * Non-cacheable Normal - intended for memory areas that must
567 * not cause dirty cache line writebacks when used
568 */
569 if (cpu_arch >= CPU_ARCH_ARMv6) {
570 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
571 /* Non-cacheable Normal is XCB = 001 */
572 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
573 PMD_SECT_BUFFERED;
574 } else {
575 /* For both ARMv6 and non-TEX-remapping ARMv7 */
576 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
577 PMD_SECT_TEX(1);
578 }
579 } else {
580 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
581 }
582
583#ifdef CONFIG_ARM_LPAE
584 /*
585 * Do not generate access flag faults for the kernel mappings.
586 */
587 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
588 mem_types[i].prot_pte |= PTE_EXT_AF;
589 if (mem_types[i].prot_sect)
590 mem_types[i].prot_sect |= PMD_SECT_AF;
591 }
592 kern_pgprot |= PTE_EXT_AF;
593 vecs_pgprot |= PTE_EXT_AF;
594#endif
595
596 for (i = 0; i < 16; i++) {
597 pteval_t v = pgprot_val(protection_map[i]);
598 protection_map[i] = __pgprot(v | user_pgprot);
599 }
600
601 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
602 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
603
604 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
605 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
606 L_PTE_DIRTY | kern_pgprot);
607 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
608 pgprot_s2_device = __pgprot(s2_device_pgprot);
609 pgprot_hyp_device = __pgprot(hyp_device_pgprot);
610
611 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
612 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
613 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
614 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
615 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
616 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
617 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
618 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
619 mem_types[MT_ROM].prot_sect |= cp->pmd;
620
621 switch (cp->pmd) {
622 case PMD_SECT_WT:
623 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
624 break;
625 case PMD_SECT_WB:
626 case PMD_SECT_WBWA:
627 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
628 break;
629 }
630 pr_info("Memory policy: %sData cache %s\n",
631 ecc_mask ? "ECC enabled, " : "", cp->policy);
632
633 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
634 struct mem_type *t = &mem_types[i];
635 if (t->prot_l1)
636 t->prot_l1 |= PMD_DOMAIN(t->domain);
637 if (t->prot_sect)
638 t->prot_sect |= PMD_DOMAIN(t->domain);
639 }
640}
641
642#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
643pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
644 unsigned long size, pgprot_t vma_prot)
645{
646 if (!pfn_valid(pfn))
647 return pgprot_noncached(vma_prot);
648 else if (file->f_flags & O_SYNC)
649 return pgprot_writecombine(vma_prot);
650 return vma_prot;
651}
652EXPORT_SYMBOL(phys_mem_access_prot);
653#endif
654
655#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
656
657static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
658{
659 void *ptr = __va(memblock_alloc(sz, align));
660 memset(ptr, 0, sz);
661 return ptr;
662}
663
664static void __init *early_alloc(unsigned long sz)
665{
666 return early_alloc_aligned(sz, sz);
667}
668
669static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
670{
671 if (pmd_none(*pmd)) {
672 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
673 __pmd_populate(pmd, __pa(pte), prot);
674 }
675 BUG_ON(pmd_bad(*pmd));
676 return pte_offset_kernel(pmd, addr);
677}
678
679static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
680 unsigned long end, unsigned long pfn,
681 const struct mem_type *type)
682{
683 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
684 do {
685 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
686 pfn++;
687 } while (pte++, addr += PAGE_SIZE, addr != end);
688}
689
690static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
691 unsigned long end, phys_addr_t phys,
692 const struct mem_type *type)
693{
694 pmd_t *p = pmd;
695
696#ifndef CONFIG_ARM_LPAE
697 /*
698 * In classic MMU format, puds and pmds are folded in to
699 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
700 * group of L1 entries making up one logical pointer to
701 * an L2 table (2MB), where as PMDs refer to the individual
702 * L1 entries (1MB). Hence increment to get the correct
703 * offset for odd 1MB sections.
704 * (See arch/arm/include/asm/pgtable-2level.h)
705 */
706 if (addr & SECTION_SIZE)
707 pmd++;
708#endif
709 do {
710 *pmd = __pmd(phys | type->prot_sect);
711 phys += SECTION_SIZE;
712 } while (pmd++, addr += SECTION_SIZE, addr != end);
713
714 flush_pmd_entry(p);
715}
716
717static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
718 unsigned long end, phys_addr_t phys,
719 const struct mem_type *type)
720{
721 pmd_t *pmd = pmd_offset(pud, addr);
722 unsigned long next;
723
724 do {
725 /*
726 * With LPAE, we must loop over to map
727 * all the pmds for the given range.
728 */
729 next = pmd_addr_end(addr, end);
730
731 /*
732 * Try a section mapping - addr, next and phys must all be
733 * aligned to a section boundary.
734 */
735 if (type->prot_sect &&
736 ((addr | next | phys) & ~SECTION_MASK) == 0) {
737 __map_init_section(pmd, addr, next, phys, type);
738 } else {
739 alloc_init_pte(pmd, addr, next,
740 __phys_to_pfn(phys), type);
741 }
742
743 phys += next - addr;
744
745 } while (pmd++, addr = next, addr != end);
746}
747
748static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
749 unsigned long end, phys_addr_t phys,
750 const struct mem_type *type)
751{
752 pud_t *pud = pud_offset(pgd, addr);
753 unsigned long next;
754
755 do {
756 next = pud_addr_end(addr, end);
757 alloc_init_pmd(pud, addr, next, phys, type);
758 phys += next - addr;
759 } while (pud++, addr = next, addr != end);
760}
761
762#ifndef CONFIG_ARM_LPAE
763static void __init create_36bit_mapping(struct map_desc *md,
764 const struct mem_type *type)
765{
766 unsigned long addr, length, end;
767 phys_addr_t phys;
768 pgd_t *pgd;
769
770 addr = md->virtual;
771 phys = __pfn_to_phys(md->pfn);
772 length = PAGE_ALIGN(md->length);
773
774 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
775 printk(KERN_ERR "MM: CPU does not support supersection "
776 "mapping for 0x%08llx at 0x%08lx\n",
777 (long long)__pfn_to_phys((u64)md->pfn), addr);
778 return;
779 }
780
781 /* N.B. ARMv6 supersections are only defined to work with domain 0.
782 * Since domain assignments can in fact be arbitrary, the
783 * 'domain == 0' check below is required to insure that ARMv6
784 * supersections are only allocated for domain 0 regardless
785 * of the actual domain assignments in use.
786 */
787 if (type->domain) {
788 printk(KERN_ERR "MM: invalid domain in supersection "
789 "mapping for 0x%08llx at 0x%08lx\n",
790 (long long)__pfn_to_phys((u64)md->pfn), addr);
791 return;
792 }
793
794 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
795 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
796 " at 0x%08lx invalid alignment\n",
797 (long long)__pfn_to_phys((u64)md->pfn), addr);
798 return;
799 }
800
801 /*
802 * Shift bits [35:32] of address into bits [23:20] of PMD
803 * (See ARMv6 spec).
804 */
805 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
806
807 pgd = pgd_offset_k(addr);
808 end = addr + length;
809 do {
810 pud_t *pud = pud_offset(pgd, addr);
811 pmd_t *pmd = pmd_offset(pud, addr);
812 int i;
813
814 for (i = 0; i < 16; i++)
815 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
816
817 addr += SUPERSECTION_SIZE;
818 phys += SUPERSECTION_SIZE;
819 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
820 } while (addr != end);
821}
822#endif /* !CONFIG_ARM_LPAE */
823
824/*
825 * Create the page directory entries and any necessary
826 * page tables for the mapping specified by `md'. We
827 * are able to cope here with varying sizes and address
828 * offsets, and we take full advantage of sections and
829 * supersections.
830 */
831static void __init create_mapping(struct map_desc *md)
832{
833 unsigned long addr, length, end;
834 phys_addr_t phys;
835 const struct mem_type *type;
836 pgd_t *pgd;
837
838 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
839 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
840 " at 0x%08lx in user region\n",
841 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
842 return;
843 }
844
845 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
846 md->virtual >= PAGE_OFFSET &&
847 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
848 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
849 " at 0x%08lx out of vmalloc space\n",
850 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
851 }
852
853 type = &mem_types[md->type];
854
855#ifndef CONFIG_ARM_LPAE
856 /*
857 * Catch 36-bit addresses
858 */
859 if (md->pfn >= 0x100000) {
860 create_36bit_mapping(md, type);
861 return;
862 }
863#endif
864
865 addr = md->virtual & PAGE_MASK;
866 phys = __pfn_to_phys(md->pfn);
867 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
868
869 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
870 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
871 "be mapped using pages, ignoring.\n",
872 (long long)__pfn_to_phys(md->pfn), addr);
873 return;
874 }
875
876 pgd = pgd_offset_k(addr);
877 end = addr + length;
878 do {
879 unsigned long next = pgd_addr_end(addr, end);
880
881 alloc_init_pud(pgd, addr, next, phys, type);
882
883 phys += next - addr;
884 addr = next;
885 } while (pgd++, addr != end);
886}
887
888/*
889 * Create the architecture specific mappings
890 */
891void __init iotable_init(struct map_desc *io_desc, int nr)
892{
893 struct map_desc *md;
894 struct vm_struct *vm;
895 struct static_vm *svm;
896
897 if (!nr)
898 return;
899
900 svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
901
902 for (md = io_desc; nr; md++, nr--) {
903 create_mapping(md);
904
905 vm = &svm->vm;
906 vm->addr = (void *)(md->virtual & PAGE_MASK);
907 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
908 vm->phys_addr = __pfn_to_phys(md->pfn);
909 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
910 vm->flags |= VM_ARM_MTYPE(md->type);
911 vm->caller = iotable_init;
912 add_static_vm_early(svm++);
913 }
914}
915
916void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
917 void *caller)
918{
919 struct vm_struct *vm;
920 struct static_vm *svm;
921
922 svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
923
924 vm = &svm->vm;
925 vm->addr = (void *)addr;
926 vm->size = size;
927 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
928 vm->caller = caller;
929 add_static_vm_early(svm);
930}
931
932#ifndef CONFIG_ARM_LPAE
933
934/*
935 * The Linux PMD is made of two consecutive section entries covering 2MB
936 * (see definition in include/asm/pgtable-2level.h). However a call to
937 * create_mapping() may optimize static mappings by using individual
938 * 1MB section mappings. This leaves the actual PMD potentially half
939 * initialized if the top or bottom section entry isn't used, leaving it
940 * open to problems if a subsequent ioremap() or vmalloc() tries to use
941 * the virtual space left free by that unused section entry.
942 *
943 * Let's avoid the issue by inserting dummy vm entries covering the unused
944 * PMD halves once the static mappings are in place.
945 */
946
947static void __init pmd_empty_section_gap(unsigned long addr)
948{
949 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
950}
951
952static void __init fill_pmd_gaps(void)
953{
954 struct static_vm *svm;
955 struct vm_struct *vm;
956 unsigned long addr, next = 0;
957 pmd_t *pmd;
958
959 list_for_each_entry(svm, &static_vmlist, list) {
960 vm = &svm->vm;
961 addr = (unsigned long)vm->addr;
962 if (addr < next)
963 continue;
964
965 /*
966 * Check if this vm starts on an odd section boundary.
967 * If so and the first section entry for this PMD is free
968 * then we block the corresponding virtual address.
969 */
970 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
971 pmd = pmd_off_k(addr);
972 if (pmd_none(*pmd))
973 pmd_empty_section_gap(addr & PMD_MASK);
974 }
975
976 /*
977 * Then check if this vm ends on an odd section boundary.
978 * If so and the second section entry for this PMD is empty
979 * then we block the corresponding virtual address.
980 */
981 addr += vm->size;
982 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
983 pmd = pmd_off_k(addr) + 1;
984 if (pmd_none(*pmd))
985 pmd_empty_section_gap(addr);
986 }
987
988 /* no need to look at any vm entry until we hit the next PMD */
989 next = (addr + PMD_SIZE - 1) & PMD_MASK;
990 }
991}
992
993#else
994#define fill_pmd_gaps() do { } while (0)
995#endif
996
997#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
998static void __init pci_reserve_io(void)
999{
1000 struct static_vm *svm;
1001
1002 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1003 if (svm)
1004 return;
1005
1006 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1007}
1008#else
1009#define pci_reserve_io() do { } while (0)
1010#endif
1011
1012#ifdef CONFIG_DEBUG_LL
1013void __init debug_ll_io_init(void)
1014{
1015 struct map_desc map;
1016
1017 debug_ll_addr(&map.pfn, &map.virtual);
1018 if (!map.pfn || !map.virtual)
1019 return;
1020 map.pfn = __phys_to_pfn(map.pfn);
1021 map.virtual &= PAGE_MASK;
1022 map.length = PAGE_SIZE;
1023 map.type = MT_DEVICE;
1024 iotable_init(&map, 1);
1025}
1026#endif
1027
1028static void * __initdata vmalloc_min =
1029 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
1030
1031/*
1032 * vmalloc=size forces the vmalloc area to be exactly 'size'
1033 * bytes. This can be used to increase (or decrease) the vmalloc
1034 * area - the default is 240m.
1035 */
1036static int __init early_vmalloc(char *arg)
1037{
1038 unsigned long vmalloc_reserve = memparse(arg, NULL);
1039
1040 if (vmalloc_reserve < SZ_16M) {
1041 vmalloc_reserve = SZ_16M;
1042 printk(KERN_WARNING
1043 "vmalloc area too small, limiting to %luMB\n",
1044 vmalloc_reserve >> 20);
1045 }
1046
1047 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
1048 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
1049 printk(KERN_WARNING
1050 "vmalloc area is too big, limiting to %luMB\n",
1051 vmalloc_reserve >> 20);
1052 }
1053
1054 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
1055 return 0;
1056}
1057early_param("vmalloc", early_vmalloc);
1058
1059phys_addr_t arm_lowmem_limit __initdata = 0;
1060
1061void __init sanity_check_meminfo(void)
1062{
1063 phys_addr_t memblock_limit = 0;
1064 int i, j, highmem = 0;
1065 phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
1066
1067 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
1068 struct membank *bank = &meminfo.bank[j];
1069 phys_addr_t size_limit;
1070
1071 *bank = meminfo.bank[i];
1072 size_limit = bank->size;
1073
1074 if (bank->start >= vmalloc_limit)
1075 highmem = 1;
1076 else
1077 size_limit = vmalloc_limit - bank->start;
1078
1079 bank->highmem = highmem;
1080
1081#ifdef CONFIG_HIGHMEM
1082 /*
1083 * Split those memory banks which are partially overlapping
1084 * the vmalloc area greatly simplifying things later.
1085 */
1086 if (!highmem && bank->size > size_limit) {
1087 if (meminfo.nr_banks >= NR_BANKS) {
1088 printk(KERN_CRIT "NR_BANKS too low, "
1089 "ignoring high memory\n");
1090 } else {
1091 memmove(bank + 1, bank,
1092 (meminfo.nr_banks - i) * sizeof(*bank));
1093 meminfo.nr_banks++;
1094 i++;
1095 bank[1].size -= size_limit;
1096 bank[1].start = vmalloc_limit;
1097 bank[1].highmem = highmem = 1;
1098 j++;
1099 }
1100 bank->size = size_limit;
1101 }
1102#else
1103 /*
1104 * Highmem banks not allowed with !CONFIG_HIGHMEM.
1105 */
1106 if (highmem) {
1107 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1108 "(!CONFIG_HIGHMEM).\n",
1109 (unsigned long long)bank->start,
1110 (unsigned long long)bank->start + bank->size - 1);
1111 continue;
1112 }
1113
1114 /*
1115 * Check whether this memory bank would partially overlap
1116 * the vmalloc area.
1117 */
1118 if (bank->size > size_limit) {
1119 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
1120 "to -%.8llx (vmalloc region overlap).\n",
1121 (unsigned long long)bank->start,
1122 (unsigned long long)bank->start + bank->size - 1,
1123 (unsigned long long)bank->start + size_limit - 1);
1124 bank->size = size_limit;
1125 }
1126#endif
1127 if (!bank->highmem) {
1128 phys_addr_t bank_end = bank->start + bank->size;
1129
1130 if (bank_end > arm_lowmem_limit)
1131 arm_lowmem_limit = bank_end;
1132
1133 /*
1134 * Find the first non-section-aligned page, and point
1135 * memblock_limit at it. This relies on rounding the
1136 * limit down to be section-aligned, which happens at
1137 * the end of this function.
1138 *
1139 * With this algorithm, the start or end of almost any
1140 * bank can be non-section-aligned. The only exception
1141 * is that the start of the bank 0 must be section-
1142 * aligned, since otherwise memory would need to be
1143 * allocated when mapping the start of bank 0, which
1144 * occurs before any free memory is mapped.
1145 */
1146 if (!memblock_limit) {
1147 if (!IS_ALIGNED(bank->start, SECTION_SIZE))
1148 memblock_limit = bank->start;
1149 else if (!IS_ALIGNED(bank_end, SECTION_SIZE))
1150 memblock_limit = bank_end;
1151 }
1152 }
1153 j++;
1154 }
1155#ifdef CONFIG_HIGHMEM
1156 if (highmem) {
1157 const char *reason = NULL;
1158
1159 if (cache_is_vipt_aliasing()) {
1160 /*
1161 * Interactions between kmap and other mappings
1162 * make highmem support with aliasing VIPT caches
1163 * rather difficult.
1164 */
1165 reason = "with VIPT aliasing cache";
1166 }
1167 if (reason) {
1168 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
1169 reason);
1170 while (j > 0 && meminfo.bank[j - 1].highmem)
1171 j--;
1172 }
1173 }
1174#endif
1175 meminfo.nr_banks = j;
1176 high_memory = __va(arm_lowmem_limit - 1) + 1;
1177
1178 /*
1179 * Round the memblock limit down to a section size. This
1180 * helps to ensure that we will allocate memory from the
1181 * last full section, which should be mapped.
1182 */
1183 if (memblock_limit)
1184 memblock_limit = round_down(memblock_limit, SECTION_SIZE);
1185 if (!memblock_limit)
1186 memblock_limit = arm_lowmem_limit;
1187
1188 memblock_set_current_limit(memblock_limit);
1189}
1190
1191static inline void prepare_page_table(void)
1192{
1193 unsigned long addr;
1194 phys_addr_t end;
1195
1196 /*
1197 * Clear out all the mappings below the kernel image.
1198 */
1199 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1200 pmd_clear(pmd_off_k(addr));
1201
1202#ifdef CONFIG_XIP_KERNEL
1203 /* The XIP kernel is mapped in the module area -- skip over it */
1204 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1205#endif
1206 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1207 pmd_clear(pmd_off_k(addr));
1208
1209 /*
1210 * Find the end of the first block of lowmem.
1211 */
1212 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1213 if (end >= arm_lowmem_limit)
1214 end = arm_lowmem_limit;
1215
1216 /*
1217 * Clear out all the kernel space mappings, except for the first
1218 * memory bank, up to the vmalloc region.
1219 */
1220 for (addr = __phys_to_virt(end);
1221 addr < VMALLOC_START; addr += PMD_SIZE)
1222 pmd_clear(pmd_off_k(addr));
1223}
1224
1225#ifdef CONFIG_ARM_LPAE
1226/* the first page is reserved for pgd */
1227#define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1228 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1229#else
1230#define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1231#endif
1232
1233/*
1234 * Reserve the special regions of memory
1235 */
1236void __init arm_mm_memblock_reserve(void)
1237{
1238 /*
1239 * Reserve the page tables. These are already in use,
1240 * and can only be in node 0.
1241 */
1242 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1243
1244#ifdef CONFIG_SA1111
1245 /*
1246 * Because of the SA1111 DMA bug, we want to preserve our
1247 * precious DMA-able memory...
1248 */
1249 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1250#endif
1251}
1252
1253/*
1254 * Set up the device mappings. Since we clear out the page tables for all
1255 * mappings above VMALLOC_START, we will remove any debug device mappings.
1256 * This means you have to be careful how you debug this function, or any
1257 * called function. This means you can't use any function or debugging
1258 * method which may touch any device, otherwise the kernel _will_ crash.
1259 */
1260static void __init devicemaps_init(const struct machine_desc *mdesc)
1261{
1262 struct map_desc map;
1263 unsigned long addr;
1264 void *vectors;
1265
1266 /*
1267 * Allocate the vector page early.
1268 */
1269 vectors = early_alloc(PAGE_SIZE * 2);
1270
1271 early_trap_init(vectors);
1272
1273 for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1274 pmd_clear(pmd_off_k(addr));
1275
1276 /*
1277 * Map the kernel if it is XIP.
1278 * It is always first in the modulearea.
1279 */
1280#ifdef CONFIG_XIP_KERNEL
1281 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1282 map.virtual = MODULES_VADDR;
1283 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1284 map.type = MT_ROM;
1285 create_mapping(&map);
1286#endif
1287
1288 /*
1289 * Map the cache flushing regions.
1290 */
1291#ifdef FLUSH_BASE
1292 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1293 map.virtual = FLUSH_BASE;
1294 map.length = SZ_1M;
1295 map.type = MT_CACHECLEAN;
1296 create_mapping(&map);
1297#endif
1298#ifdef FLUSH_BASE_MINICACHE
1299 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1300 map.virtual = FLUSH_BASE_MINICACHE;
1301 map.length = SZ_1M;
1302 map.type = MT_MINICLEAN;
1303 create_mapping(&map);
1304#endif
1305
1306 /*
1307 * Create a mapping for the machine vectors at the high-vectors
1308 * location (0xffff0000). If we aren't using high-vectors, also
1309 * create a mapping at the low-vectors virtual address.
1310 */
1311 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1312 map.virtual = 0xffff0000;
1313 map.length = PAGE_SIZE;
1314#ifdef CONFIG_KUSER_HELPERS
1315 map.type = MT_HIGH_VECTORS;
1316#else
1317 map.type = MT_LOW_VECTORS;
1318#endif
1319 create_mapping(&map);
1320
1321 if (!vectors_high()) {
1322 map.virtual = 0;
1323 map.length = PAGE_SIZE * 2;
1324 map.type = MT_LOW_VECTORS;
1325 create_mapping(&map);
1326 }
1327
1328 /* Now create a kernel read-only mapping */
1329 map.pfn += 1;
1330 map.virtual = 0xffff0000 + PAGE_SIZE;
1331 map.length = PAGE_SIZE;
1332 map.type = MT_LOW_VECTORS;
1333 create_mapping(&map);
1334
1335 /*
1336 * Ask the machine support to map in the statically mapped devices.
1337 */
1338 if (mdesc->map_io)
1339 mdesc->map_io();
1340 else
1341 debug_ll_io_init();
1342 fill_pmd_gaps();
1343
1344 /* Reserve fixed i/o space in VMALLOC region */
1345 pci_reserve_io();
1346
1347 /*
1348 * Finally flush the caches and tlb to ensure that we're in a
1349 * consistent state wrt the writebuffer. This also ensures that
1350 * any write-allocated cache lines in the vector page are written
1351 * back. After this point, we can start to touch devices again.
1352 */
1353 local_flush_tlb_all();
1354 flush_cache_all();
1355}
1356
1357static void __init kmap_init(void)
1358{
1359#ifdef CONFIG_HIGHMEM
1360 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1361 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1362#endif
1363}
1364
1365static void __init map_lowmem(void)
1366{
1367 struct memblock_region *reg;
1368 unsigned long kernel_x_start = round_down(__pa(_stext), SECTION_SIZE);
1369 unsigned long kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1370
1371 /* Map all the lowmem memory banks. */
1372 for_each_memblock(memory, reg) {
1373 phys_addr_t start = reg->base;
1374 phys_addr_t end = start + reg->size;
1375 struct map_desc map;
1376
1377 if (end > arm_lowmem_limit)
1378 end = arm_lowmem_limit;
1379 if (start >= end)
1380 break;
1381
1382 if (end < kernel_x_start || start >= kernel_x_end) {
1383 map.pfn = __phys_to_pfn(start);
1384 map.virtual = __phys_to_virt(start);
1385 map.length = end - start;
1386 map.type = MT_MEMORY_RWX;
1387
1388 create_mapping(&map);
1389 } else {
1390 /* This better cover the entire kernel */
1391 if (start < kernel_x_start) {
1392 map.pfn = __phys_to_pfn(start);
1393 map.virtual = __phys_to_virt(start);
1394 map.length = kernel_x_start - start;
1395 map.type = MT_MEMORY_RW;
1396
1397 create_mapping(&map);
1398 }
1399
1400 map.pfn = __phys_to_pfn(kernel_x_start);
1401 map.virtual = __phys_to_virt(kernel_x_start);
1402 map.length = kernel_x_end - kernel_x_start;
1403 map.type = MT_MEMORY_RWX;
1404
1405 create_mapping(&map);
1406
1407 if (kernel_x_end < end) {
1408 map.pfn = __phys_to_pfn(kernel_x_end);
1409 map.virtual = __phys_to_virt(kernel_x_end);
1410 map.length = end - kernel_x_end;
1411 map.type = MT_MEMORY_RW;
1412
1413 create_mapping(&map);
1414 }
1415 }
1416 }
1417}
1418
1419#ifdef CONFIG_ARM_LPAE
1420/*
1421 * early_paging_init() recreates boot time page table setup, allowing machines
1422 * to switch over to a high (>4G) address space on LPAE systems
1423 */
1424void __init early_paging_init(const struct machine_desc *mdesc,
1425 struct proc_info_list *procinfo)
1426{
1427 pmdval_t pmdprot = procinfo->__cpu_mm_mmu_flags;
1428 unsigned long map_start, map_end;
1429 pgd_t *pgd0, *pgdk;
1430 pud_t *pud0, *pudk, *pud_start;
1431 pmd_t *pmd0, *pmdk;
1432 phys_addr_t phys;
1433 int i;
1434
1435 if (!(mdesc->init_meminfo))
1436 return;
1437
1438 /* remap kernel code and data */
1439 map_start = init_mm.start_code;
1440 map_end = init_mm.brk;
1441
1442 /* get a handle on things... */
1443 pgd0 = pgd_offset_k(0);
1444 pud_start = pud0 = pud_offset(pgd0, 0);
1445 pmd0 = pmd_offset(pud0, 0);
1446
1447 pgdk = pgd_offset_k(map_start);
1448 pudk = pud_offset(pgdk, map_start);
1449 pmdk = pmd_offset(pudk, map_start);
1450
1451 mdesc->init_meminfo();
1452
1453 /* Run the patch stub to update the constants */
1454 fixup_pv_table(&__pv_table_begin,
1455 (&__pv_table_end - &__pv_table_begin) << 2);
1456
1457 /*
1458 * Cache cleaning operations for self-modifying code
1459 * We should clean the entries by MVA but running a
1460 * for loop over every pv_table entry pointer would
1461 * just complicate the code.
1462 */
1463 flush_cache_louis();
1464 dsb();
1465 isb();
1466
1467 /* remap level 1 table */
1468 for (i = 0; i < PTRS_PER_PGD; pud0++, i++) {
1469 set_pud(pud0,
1470 __pud(__pa(pmd0) | PMD_TYPE_TABLE | L_PGD_SWAPPER));
1471 pmd0 += PTRS_PER_PMD;
1472 }
1473
1474 /* remap pmds for kernel mapping */
1475 phys = __pa(map_start) & PMD_MASK;
1476 do {
1477 *pmdk++ = __pmd(phys | pmdprot);
1478 phys += PMD_SIZE;
1479 } while (phys < map_end);
1480
1481 flush_cache_all();
1482 cpu_switch_mm(pgd0, &init_mm);
1483 cpu_set_ttbr(1, __pa(pgd0) + TTBR1_OFFSET);
1484 local_flush_bp_all();
1485 local_flush_tlb_all();
1486}
1487
1488#else
1489
1490void __init early_paging_init(const struct machine_desc *mdesc,
1491 struct proc_info_list *procinfo)
1492{
1493 if (mdesc->init_meminfo)
1494 mdesc->init_meminfo();
1495}
1496
1497#endif
1498
1499/*
1500 * paging_init() sets up the page tables, initialises the zone memory
1501 * maps, and sets up the zero page, bad page and bad page tables.
1502 */
1503void __init paging_init(const struct machine_desc *mdesc)
1504{
1505 void *zero_page;
1506
1507 build_mem_type_table();
1508 prepare_page_table();
1509 map_lowmem();
1510 dma_contiguous_remap();
1511 devicemaps_init(mdesc);
1512 kmap_init();
1513 tcm_init();
1514
1515 top_pmd = pmd_off_k(0xffff0000);
1516
1517 /* allocate the zero page. */
1518 zero_page = early_alloc(PAGE_SIZE);
1519
1520 bootmem_init();
1521
1522 empty_zero_page = virt_to_page(zero_page);
1523 __flush_dcache_page(NULL, empty_zero_page);
1524}