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1/**
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * S3C USB2.0 High-speed / OtG driver
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/spinlock.h>
20#include <linux/interrupt.h>
21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h>
23#include <linux/mutex.h>
24#include <linux/seq_file.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/slab.h>
28#include <linux/of_platform.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32#include <linux/usb/phy.h>
33
34#include "core.h"
35#include "hw.h"
36
37/* conversion functions */
38static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
39{
40 return container_of(req, struct dwc2_hsotg_req, req);
41}
42
43static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
44{
45 return container_of(ep, struct dwc2_hsotg_ep, ep);
46}
47
48static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
49{
50 return container_of(gadget, struct dwc2_hsotg, gadget);
51}
52
53static inline void __orr32(void __iomem *ptr, u32 val)
54{
55 dwc2_writel(dwc2_readl(ptr) | val, ptr);
56}
57
58static inline void __bic32(void __iomem *ptr, u32 val)
59{
60 dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
61}
62
63static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
64 u32 ep_index, u32 dir_in)
65{
66 if (dir_in)
67 return hsotg->eps_in[ep_index];
68 else
69 return hsotg->eps_out[ep_index];
70}
71
72/* forward declaration of functions */
73static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
74
75/**
76 * using_dma - return the DMA status of the driver.
77 * @hsotg: The driver state.
78 *
79 * Return true if we're using DMA.
80 *
81 * Currently, we have the DMA support code worked into everywhere
82 * that needs it, but the AMBA DMA implementation in the hardware can
83 * only DMA from 32bit aligned addresses. This means that gadgets such
84 * as the CDC Ethernet cannot work as they often pass packets which are
85 * not 32bit aligned.
86 *
87 * Unfortunately the choice to use DMA or not is global to the controller
88 * and seems to be only settable when the controller is being put through
89 * a core reset. This means we either need to fix the gadgets to take
90 * account of DMA alignment, or add bounce buffers (yuerk).
91 *
92 * g_using_dma is set depending on dts flag.
93 */
94static inline bool using_dma(struct dwc2_hsotg *hsotg)
95{
96 return hsotg->g_using_dma;
97}
98
99/**
100 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
101 * @hsotg: The device state
102 * @ints: A bitmask of the interrupts to enable
103 */
104static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
105{
106 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
107 u32 new_gsintmsk;
108
109 new_gsintmsk = gsintmsk | ints;
110
111 if (new_gsintmsk != gsintmsk) {
112 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
113 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
114 }
115}
116
117/**
118 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
119 * @hsotg: The device state
120 * @ints: A bitmask of the interrupts to enable
121 */
122static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
123{
124 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
125 u32 new_gsintmsk;
126
127 new_gsintmsk = gsintmsk & ~ints;
128
129 if (new_gsintmsk != gsintmsk)
130 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
131}
132
133/**
134 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
135 * @hsotg: The device state
136 * @ep: The endpoint index
137 * @dir_in: True if direction is in.
138 * @en: The enable value, true to enable
139 *
140 * Set or clear the mask for an individual endpoint's interrupt
141 * request.
142 */
143static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
144 unsigned int ep, unsigned int dir_in,
145 unsigned int en)
146{
147 unsigned long flags;
148 u32 bit = 1 << ep;
149 u32 daint;
150
151 if (!dir_in)
152 bit <<= 16;
153
154 local_irq_save(flags);
155 daint = dwc2_readl(hsotg->regs + DAINTMSK);
156 if (en)
157 daint |= bit;
158 else
159 daint &= ~bit;
160 dwc2_writel(daint, hsotg->regs + DAINTMSK);
161 local_irq_restore(flags);
162}
163
164/**
165 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
166 * @hsotg: The device instance.
167 */
168static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
169{
170 unsigned int ep;
171 unsigned int addr;
172 int timeout;
173 u32 val;
174
175 /* Reset fifo map if not correctly cleared during previous session */
176 WARN_ON(hsotg->fifo_map);
177 hsotg->fifo_map = 0;
178
179 /* set RX/NPTX FIFO sizes */
180 dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ);
181 dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) |
182 (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT),
183 hsotg->regs + GNPTXFSIZ);
184
185 /*
186 * arange all the rest of the TX FIFOs, as some versions of this
187 * block have overlapping default addresses. This also ensures
188 * that if the settings have been changed, then they are set to
189 * known values.
190 */
191
192 /* start at the end of the GNPTXFSIZ, rounded up */
193 addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz;
194
195 /*
196 * Configure fifos sizes from provided configuration and assign
197 * them to endpoints dynamically according to maxpacket size value of
198 * given endpoint.
199 */
200 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
201 if (!hsotg->g_tx_fifo_sz[ep])
202 continue;
203 val = addr;
204 val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT;
205 WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem,
206 "insufficient fifo memory");
207 addr += hsotg->g_tx_fifo_sz[ep];
208
209 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
210 }
211
212 /*
213 * according to p428 of the design guide, we need to ensure that
214 * all fifos are flushed before continuing
215 */
216
217 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
218 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
219
220 /* wait until the fifos are both flushed */
221 timeout = 100;
222 while (1) {
223 val = dwc2_readl(hsotg->regs + GRSTCTL);
224
225 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
226 break;
227
228 if (--timeout == 0) {
229 dev_err(hsotg->dev,
230 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
231 __func__, val);
232 break;
233 }
234
235 udelay(1);
236 }
237
238 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
239}
240
241/**
242 * @ep: USB endpoint to allocate request for.
243 * @flags: Allocation flags
244 *
245 * Allocate a new USB request structure appropriate for the specified endpoint
246 */
247static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
248 gfp_t flags)
249{
250 struct dwc2_hsotg_req *req;
251
252 req = kzalloc(sizeof(struct dwc2_hsotg_req), flags);
253 if (!req)
254 return NULL;
255
256 INIT_LIST_HEAD(&req->queue);
257
258 return &req->req;
259}
260
261/**
262 * is_ep_periodic - return true if the endpoint is in periodic mode.
263 * @hs_ep: The endpoint to query.
264 *
265 * Returns true if the endpoint is in periodic mode, meaning it is being
266 * used for an Interrupt or ISO transfer.
267 */
268static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
269{
270 return hs_ep->periodic;
271}
272
273/**
274 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
275 * @hsotg: The device state.
276 * @hs_ep: The endpoint for the request
277 * @hs_req: The request being processed.
278 *
279 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
280 * of a request to ensure the buffer is ready for access by the caller.
281 */
282static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
283 struct dwc2_hsotg_ep *hs_ep,
284 struct dwc2_hsotg_req *hs_req)
285{
286 struct usb_request *req = &hs_req->req;
287
288 /* ignore this if we're not moving any data */
289 if (hs_req->req.length == 0)
290 return;
291
292 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
293}
294
295/**
296 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
297 * @hsotg: The controller state.
298 * @hs_ep: The endpoint we're going to write for.
299 * @hs_req: The request to write data for.
300 *
301 * This is called when the TxFIFO has some space in it to hold a new
302 * transmission and we have something to give it. The actual setup of
303 * the data size is done elsewhere, so all we have to do is to actually
304 * write the data.
305 *
306 * The return value is zero if there is more space (or nothing was done)
307 * otherwise -ENOSPC is returned if the FIFO space was used up.
308 *
309 * This routine is only needed for PIO
310 */
311static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
312 struct dwc2_hsotg_ep *hs_ep,
313 struct dwc2_hsotg_req *hs_req)
314{
315 bool periodic = is_ep_periodic(hs_ep);
316 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
317 int buf_pos = hs_req->req.actual;
318 int to_write = hs_ep->size_loaded;
319 void *data;
320 int can_write;
321 int pkt_round;
322 int max_transfer;
323
324 to_write -= (buf_pos - hs_ep->last_load);
325
326 /* if there's nothing to write, get out early */
327 if (to_write == 0)
328 return 0;
329
330 if (periodic && !hsotg->dedicated_fifos) {
331 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
332 int size_left;
333 int size_done;
334
335 /*
336 * work out how much data was loaded so we can calculate
337 * how much data is left in the fifo.
338 */
339
340 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
341
342 /*
343 * if shared fifo, we cannot write anything until the
344 * previous data has been completely sent.
345 */
346 if (hs_ep->fifo_load != 0) {
347 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
348 return -ENOSPC;
349 }
350
351 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
352 __func__, size_left,
353 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
354
355 /* how much of the data has moved */
356 size_done = hs_ep->size_loaded - size_left;
357
358 /* how much data is left in the fifo */
359 can_write = hs_ep->fifo_load - size_done;
360 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
361 __func__, can_write);
362
363 can_write = hs_ep->fifo_size - can_write;
364 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
365 __func__, can_write);
366
367 if (can_write <= 0) {
368 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
369 return -ENOSPC;
370 }
371 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
372 can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index));
373
374 can_write &= 0xffff;
375 can_write *= 4;
376 } else {
377 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
378 dev_dbg(hsotg->dev,
379 "%s: no queue slots available (0x%08x)\n",
380 __func__, gnptxsts);
381
382 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
383 return -ENOSPC;
384 }
385
386 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
387 can_write *= 4; /* fifo size is in 32bit quantities. */
388 }
389
390 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
391
392 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
393 __func__, gnptxsts, can_write, to_write, max_transfer);
394
395 /*
396 * limit to 512 bytes of data, it seems at least on the non-periodic
397 * FIFO, requests of >512 cause the endpoint to get stuck with a
398 * fragment of the end of the transfer in it.
399 */
400 if (can_write > 512 && !periodic)
401 can_write = 512;
402
403 /*
404 * limit the write to one max-packet size worth of data, but allow
405 * the transfer to return that it did not run out of fifo space
406 * doing it.
407 */
408 if (to_write > max_transfer) {
409 to_write = max_transfer;
410
411 /* it's needed only when we do not use dedicated fifos */
412 if (!hsotg->dedicated_fifos)
413 dwc2_hsotg_en_gsint(hsotg,
414 periodic ? GINTSTS_PTXFEMP :
415 GINTSTS_NPTXFEMP);
416 }
417
418 /* see if we can write data */
419
420 if (to_write > can_write) {
421 to_write = can_write;
422 pkt_round = to_write % max_transfer;
423
424 /*
425 * Round the write down to an
426 * exact number of packets.
427 *
428 * Note, we do not currently check to see if we can ever
429 * write a full packet or not to the FIFO.
430 */
431
432 if (pkt_round)
433 to_write -= pkt_round;
434
435 /*
436 * enable correct FIFO interrupt to alert us when there
437 * is more room left.
438 */
439
440 /* it's needed only when we do not use dedicated fifos */
441 if (!hsotg->dedicated_fifos)
442 dwc2_hsotg_en_gsint(hsotg,
443 periodic ? GINTSTS_PTXFEMP :
444 GINTSTS_NPTXFEMP);
445 }
446
447 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
448 to_write, hs_req->req.length, can_write, buf_pos);
449
450 if (to_write <= 0)
451 return -ENOSPC;
452
453 hs_req->req.actual = buf_pos + to_write;
454 hs_ep->total_data += to_write;
455
456 if (periodic)
457 hs_ep->fifo_load += to_write;
458
459 to_write = DIV_ROUND_UP(to_write, 4);
460 data = hs_req->req.buf + buf_pos;
461
462 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
463
464 return (to_write >= can_write) ? -ENOSPC : 0;
465}
466
467/**
468 * get_ep_limit - get the maximum data legnth for this endpoint
469 * @hs_ep: The endpoint
470 *
471 * Return the maximum data that can be queued in one go on a given endpoint
472 * so that transfers that are too long can be split.
473 */
474static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
475{
476 int index = hs_ep->index;
477 unsigned maxsize;
478 unsigned maxpkt;
479
480 if (index != 0) {
481 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
482 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
483 } else {
484 maxsize = 64+64;
485 if (hs_ep->dir_in)
486 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
487 else
488 maxpkt = 2;
489 }
490
491 /* we made the constant loading easier above by using +1 */
492 maxpkt--;
493 maxsize--;
494
495 /*
496 * constrain by packet count if maxpkts*pktsize is greater
497 * than the length register size.
498 */
499
500 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
501 maxsize = maxpkt * hs_ep->ep.maxpacket;
502
503 return maxsize;
504}
505
506/**
507 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
508 * @hsotg: The controller state.
509 * @hs_ep: The endpoint to process a request for
510 * @hs_req: The request to start.
511 * @continuing: True if we are doing more for the current request.
512 *
513 * Start the given request running by setting the endpoint registers
514 * appropriately, and writing any data to the FIFOs.
515 */
516static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
517 struct dwc2_hsotg_ep *hs_ep,
518 struct dwc2_hsotg_req *hs_req,
519 bool continuing)
520{
521 struct usb_request *ureq = &hs_req->req;
522 int index = hs_ep->index;
523 int dir_in = hs_ep->dir_in;
524 u32 epctrl_reg;
525 u32 epsize_reg;
526 u32 epsize;
527 u32 ctrl;
528 unsigned length;
529 unsigned packets;
530 unsigned maxreq;
531
532 if (index != 0) {
533 if (hs_ep->req && !continuing) {
534 dev_err(hsotg->dev, "%s: active request\n", __func__);
535 WARN_ON(1);
536 return;
537 } else if (hs_ep->req != hs_req && continuing) {
538 dev_err(hsotg->dev,
539 "%s: continue different req\n", __func__);
540 WARN_ON(1);
541 return;
542 }
543 }
544
545 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
546 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
547
548 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
549 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
550 hs_ep->dir_in ? "in" : "out");
551
552 /* If endpoint is stalled, we will restart request later */
553 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
554
555 if (index && ctrl & DXEPCTL_STALL) {
556 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
557 return;
558 }
559
560 length = ureq->length - ureq->actual;
561 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
562 ureq->length, ureq->actual);
563
564 maxreq = get_ep_limit(hs_ep);
565 if (length > maxreq) {
566 int round = maxreq % hs_ep->ep.maxpacket;
567
568 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
569 __func__, length, maxreq, round);
570
571 /* round down to multiple of packets */
572 if (round)
573 maxreq -= round;
574
575 length = maxreq;
576 }
577
578 if (length)
579 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
580 else
581 packets = 1; /* send one packet if length is zero. */
582
583 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
584 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
585 return;
586 }
587
588 if (dir_in && index != 0)
589 if (hs_ep->isochronous)
590 epsize = DXEPTSIZ_MC(packets);
591 else
592 epsize = DXEPTSIZ_MC(1);
593 else
594 epsize = 0;
595
596 /*
597 * zero length packet should be programmed on its own and should not
598 * be counted in DIEPTSIZ.PktCnt with other packets.
599 */
600 if (dir_in && ureq->zero && !continuing) {
601 /* Test if zlp is actually required. */
602 if ((ureq->length >= hs_ep->ep.maxpacket) &&
603 !(ureq->length % hs_ep->ep.maxpacket))
604 hs_ep->send_zlp = 1;
605 }
606
607 epsize |= DXEPTSIZ_PKTCNT(packets);
608 epsize |= DXEPTSIZ_XFERSIZE(length);
609
610 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
611 __func__, packets, length, ureq->length, epsize, epsize_reg);
612
613 /* store the request as the current one we're doing */
614 hs_ep->req = hs_req;
615
616 /* write size / packets */
617 dwc2_writel(epsize, hsotg->regs + epsize_reg);
618
619 if (using_dma(hsotg) && !continuing) {
620 unsigned int dma_reg;
621
622 /*
623 * write DMA address to control register, buffer already
624 * synced by dwc2_hsotg_ep_queue().
625 */
626
627 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
628 dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
629
630 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
631 __func__, &ureq->dma, dma_reg);
632 }
633
634 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
635 ctrl |= DXEPCTL_USBACTEP;
636
637 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
638
639 /* For Setup request do not clear NAK */
640 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
641 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
642
643 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
644 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
645
646 /*
647 * set these, it seems that DMA support increments past the end
648 * of the packet buffer so we need to calculate the length from
649 * this information.
650 */
651 hs_ep->size_loaded = length;
652 hs_ep->last_load = ureq->actual;
653
654 if (dir_in && !using_dma(hsotg)) {
655 /* set these anyway, we may need them for non-periodic in */
656 hs_ep->fifo_load = 0;
657
658 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
659 }
660
661 /*
662 * clear the INTknTXFEmpMsk when we start request, more as a aide
663 * to debugging to see what is going on.
664 */
665 if (dir_in)
666 dwc2_writel(DIEPMSK_INTKNTXFEMPMSK,
667 hsotg->regs + DIEPINT(index));
668
669 /*
670 * Note, trying to clear the NAK here causes problems with transmit
671 * on the S3C6400 ending up with the TXFIFO becoming full.
672 */
673
674 /* check ep is enabled */
675 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
676 dev_dbg(hsotg->dev,
677 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
678 index, dwc2_readl(hsotg->regs + epctrl_reg));
679
680 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
681 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
682
683 /* enable ep interrupts */
684 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
685}
686
687/**
688 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
689 * @hsotg: The device state.
690 * @hs_ep: The endpoint the request is on.
691 * @req: The request being processed.
692 *
693 * We've been asked to queue a request, so ensure that the memory buffer
694 * is correctly setup for DMA. If we've been passed an extant DMA address
695 * then ensure the buffer has been synced to memory. If our buffer has no
696 * DMA memory, then we map the memory and mark our request to allow us to
697 * cleanup on completion.
698 */
699static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
700 struct dwc2_hsotg_ep *hs_ep,
701 struct usb_request *req)
702{
703 struct dwc2_hsotg_req *hs_req = our_req(req);
704 int ret;
705
706 /* if the length is zero, ignore the DMA data */
707 if (hs_req->req.length == 0)
708 return 0;
709
710 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
711 if (ret)
712 goto dma_error;
713
714 return 0;
715
716dma_error:
717 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
718 __func__, req->buf, req->length);
719
720 return -EIO;
721}
722
723static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
724 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
725{
726 void *req_buf = hs_req->req.buf;
727
728 /* If dma is not being used or buffer is aligned */
729 if (!using_dma(hsotg) || !((long)req_buf & 3))
730 return 0;
731
732 WARN_ON(hs_req->saved_req_buf);
733
734 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
735 hs_ep->ep.name, req_buf, hs_req->req.length);
736
737 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
738 if (!hs_req->req.buf) {
739 hs_req->req.buf = req_buf;
740 dev_err(hsotg->dev,
741 "%s: unable to allocate memory for bounce buffer\n",
742 __func__);
743 return -ENOMEM;
744 }
745
746 /* Save actual buffer */
747 hs_req->saved_req_buf = req_buf;
748
749 if (hs_ep->dir_in)
750 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
751 return 0;
752}
753
754static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
755 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
756{
757 /* If dma is not being used or buffer was aligned */
758 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
759 return;
760
761 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
762 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
763
764 /* Copy data from bounce buffer on successful out transfer */
765 if (!hs_ep->dir_in && !hs_req->req.status)
766 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
767 hs_req->req.actual);
768
769 /* Free bounce buffer */
770 kfree(hs_req->req.buf);
771
772 hs_req->req.buf = hs_req->saved_req_buf;
773 hs_req->saved_req_buf = NULL;
774}
775
776static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
777 gfp_t gfp_flags)
778{
779 struct dwc2_hsotg_req *hs_req = our_req(req);
780 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
781 struct dwc2_hsotg *hs = hs_ep->parent;
782 bool first;
783 int ret;
784
785 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
786 ep->name, req, req->length, req->buf, req->no_interrupt,
787 req->zero, req->short_not_ok);
788
789 /* Prevent new request submission when controller is suspended */
790 if (hs->lx_state == DWC2_L2) {
791 dev_dbg(hs->dev, "%s: don't submit request while suspended\n",
792 __func__);
793 return -EAGAIN;
794 }
795
796 /* initialise status of the request */
797 INIT_LIST_HEAD(&hs_req->queue);
798 req->actual = 0;
799 req->status = -EINPROGRESS;
800
801 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
802 if (ret)
803 return ret;
804
805 /* if we're using DMA, sync the buffers as necessary */
806 if (using_dma(hs)) {
807 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
808 if (ret)
809 return ret;
810 }
811
812 first = list_empty(&hs_ep->queue);
813 list_add_tail(&hs_req->queue, &hs_ep->queue);
814
815 if (first)
816 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
817
818 return 0;
819}
820
821static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
822 gfp_t gfp_flags)
823{
824 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
825 struct dwc2_hsotg *hs = hs_ep->parent;
826 unsigned long flags = 0;
827 int ret = 0;
828
829 spin_lock_irqsave(&hs->lock, flags);
830 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
831 spin_unlock_irqrestore(&hs->lock, flags);
832
833 return ret;
834}
835
836static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
837 struct usb_request *req)
838{
839 struct dwc2_hsotg_req *hs_req = our_req(req);
840
841 kfree(hs_req);
842}
843
844/**
845 * dwc2_hsotg_complete_oursetup - setup completion callback
846 * @ep: The endpoint the request was on.
847 * @req: The request completed.
848 *
849 * Called on completion of any requests the driver itself
850 * submitted that need cleaning up.
851 */
852static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
853 struct usb_request *req)
854{
855 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
856 struct dwc2_hsotg *hsotg = hs_ep->parent;
857
858 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
859
860 dwc2_hsotg_ep_free_request(ep, req);
861}
862
863/**
864 * ep_from_windex - convert control wIndex value to endpoint
865 * @hsotg: The driver state.
866 * @windex: The control request wIndex field (in host order).
867 *
868 * Convert the given wIndex into a pointer to an driver endpoint
869 * structure, or return NULL if it is not a valid endpoint.
870 */
871static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
872 u32 windex)
873{
874 struct dwc2_hsotg_ep *ep;
875 int dir = (windex & USB_DIR_IN) ? 1 : 0;
876 int idx = windex & 0x7F;
877
878 if (windex >= 0x100)
879 return NULL;
880
881 if (idx > hsotg->num_of_eps)
882 return NULL;
883
884 ep = index_to_ep(hsotg, idx, dir);
885
886 if (idx && ep->dir_in != dir)
887 return NULL;
888
889 return ep;
890}
891
892/**
893 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
894 * @hsotg: The driver state.
895 * @testmode: requested usb test mode
896 * Enable usb Test Mode requested by the Host.
897 */
898int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
899{
900 int dctl = dwc2_readl(hsotg->regs + DCTL);
901
902 dctl &= ~DCTL_TSTCTL_MASK;
903 switch (testmode) {
904 case TEST_J:
905 case TEST_K:
906 case TEST_SE0_NAK:
907 case TEST_PACKET:
908 case TEST_FORCE_EN:
909 dctl |= testmode << DCTL_TSTCTL_SHIFT;
910 break;
911 default:
912 return -EINVAL;
913 }
914 dwc2_writel(dctl, hsotg->regs + DCTL);
915 return 0;
916}
917
918/**
919 * dwc2_hsotg_send_reply - send reply to control request
920 * @hsotg: The device state
921 * @ep: Endpoint 0
922 * @buff: Buffer for request
923 * @length: Length of reply.
924 *
925 * Create a request and queue it on the given endpoint. This is useful as
926 * an internal method of sending replies to certain control requests, etc.
927 */
928static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
929 struct dwc2_hsotg_ep *ep,
930 void *buff,
931 int length)
932{
933 struct usb_request *req;
934 int ret;
935
936 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
937
938 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
939 hsotg->ep0_reply = req;
940 if (!req) {
941 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
942 return -ENOMEM;
943 }
944
945 req->buf = hsotg->ep0_buff;
946 req->length = length;
947 /*
948 * zero flag is for sending zlp in DATA IN stage. It has no impact on
949 * STATUS stage.
950 */
951 req->zero = 0;
952 req->complete = dwc2_hsotg_complete_oursetup;
953
954 if (length)
955 memcpy(req->buf, buff, length);
956
957 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
958 if (ret) {
959 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
960 return ret;
961 }
962
963 return 0;
964}
965
966/**
967 * dwc2_hsotg_process_req_status - process request GET_STATUS
968 * @hsotg: The device state
969 * @ctrl: USB control request
970 */
971static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
972 struct usb_ctrlrequest *ctrl)
973{
974 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
975 struct dwc2_hsotg_ep *ep;
976 __le16 reply;
977 int ret;
978
979 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
980
981 if (!ep0->dir_in) {
982 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
983 return -EINVAL;
984 }
985
986 switch (ctrl->bRequestType & USB_RECIP_MASK) {
987 case USB_RECIP_DEVICE:
988 reply = cpu_to_le16(0); /* bit 0 => self powered,
989 * bit 1 => remote wakeup */
990 break;
991
992 case USB_RECIP_INTERFACE:
993 /* currently, the data result should be zero */
994 reply = cpu_to_le16(0);
995 break;
996
997 case USB_RECIP_ENDPOINT:
998 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
999 if (!ep)
1000 return -ENOENT;
1001
1002 reply = cpu_to_le16(ep->halted ? 1 : 0);
1003 break;
1004
1005 default:
1006 return 0;
1007 }
1008
1009 if (le16_to_cpu(ctrl->wLength) != 2)
1010 return -EINVAL;
1011
1012 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1013 if (ret) {
1014 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1015 return ret;
1016 }
1017
1018 return 1;
1019}
1020
1021static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1022
1023/**
1024 * get_ep_head - return the first request on the endpoint
1025 * @hs_ep: The controller endpoint to get
1026 *
1027 * Get the first request on the endpoint.
1028 */
1029static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1030{
1031 if (list_empty(&hs_ep->queue))
1032 return NULL;
1033
1034 return list_first_entry(&hs_ep->queue, struct dwc2_hsotg_req, queue);
1035}
1036
1037/**
1038 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1039 * @hsotg: The device state
1040 * @ctrl: USB control request
1041 */
1042static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1043 struct usb_ctrlrequest *ctrl)
1044{
1045 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1046 struct dwc2_hsotg_req *hs_req;
1047 bool restart;
1048 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1049 struct dwc2_hsotg_ep *ep;
1050 int ret;
1051 bool halted;
1052 u32 recip;
1053 u32 wValue;
1054 u32 wIndex;
1055
1056 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1057 __func__, set ? "SET" : "CLEAR");
1058
1059 wValue = le16_to_cpu(ctrl->wValue);
1060 wIndex = le16_to_cpu(ctrl->wIndex);
1061 recip = ctrl->bRequestType & USB_RECIP_MASK;
1062
1063 switch (recip) {
1064 case USB_RECIP_DEVICE:
1065 switch (wValue) {
1066 case USB_DEVICE_TEST_MODE:
1067 if ((wIndex & 0xff) != 0)
1068 return -EINVAL;
1069 if (!set)
1070 return -EINVAL;
1071
1072 hsotg->test_mode = wIndex >> 8;
1073 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1074 if (ret) {
1075 dev_err(hsotg->dev,
1076 "%s: failed to send reply\n", __func__);
1077 return ret;
1078 }
1079 break;
1080 default:
1081 return -ENOENT;
1082 }
1083 break;
1084
1085 case USB_RECIP_ENDPOINT:
1086 ep = ep_from_windex(hsotg, wIndex);
1087 if (!ep) {
1088 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1089 __func__, wIndex);
1090 return -ENOENT;
1091 }
1092
1093 switch (wValue) {
1094 case USB_ENDPOINT_HALT:
1095 halted = ep->halted;
1096
1097 dwc2_hsotg_ep_sethalt(&ep->ep, set);
1098
1099 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1100 if (ret) {
1101 dev_err(hsotg->dev,
1102 "%s: failed to send reply\n", __func__);
1103 return ret;
1104 }
1105
1106 /*
1107 * we have to complete all requests for ep if it was
1108 * halted, and the halt was cleared by CLEAR_FEATURE
1109 */
1110
1111 if (!set && halted) {
1112 /*
1113 * If we have request in progress,
1114 * then complete it
1115 */
1116 if (ep->req) {
1117 hs_req = ep->req;
1118 ep->req = NULL;
1119 list_del_init(&hs_req->queue);
1120 if (hs_req->req.complete) {
1121 spin_unlock(&hsotg->lock);
1122 usb_gadget_giveback_request(
1123 &ep->ep, &hs_req->req);
1124 spin_lock(&hsotg->lock);
1125 }
1126 }
1127
1128 /* If we have pending request, then start it */
1129 if (!ep->req) {
1130 restart = !list_empty(&ep->queue);
1131 if (restart) {
1132 hs_req = get_ep_head(ep);
1133 dwc2_hsotg_start_req(hsotg, ep,
1134 hs_req, false);
1135 }
1136 }
1137 }
1138
1139 break;
1140
1141 default:
1142 return -ENOENT;
1143 }
1144 break;
1145 default:
1146 return -ENOENT;
1147 }
1148 return 1;
1149}
1150
1151static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1152
1153/**
1154 * dwc2_hsotg_stall_ep0 - stall ep0
1155 * @hsotg: The device state
1156 *
1157 * Set stall for ep0 as response for setup request.
1158 */
1159static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1160{
1161 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1162 u32 reg;
1163 u32 ctrl;
1164
1165 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1166 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1167
1168 /*
1169 * DxEPCTL_Stall will be cleared by EP once it has
1170 * taken effect, so no need to clear later.
1171 */
1172
1173 ctrl = dwc2_readl(hsotg->regs + reg);
1174 ctrl |= DXEPCTL_STALL;
1175 ctrl |= DXEPCTL_CNAK;
1176 dwc2_writel(ctrl, hsotg->regs + reg);
1177
1178 dev_dbg(hsotg->dev,
1179 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1180 ctrl, reg, dwc2_readl(hsotg->regs + reg));
1181
1182 /*
1183 * complete won't be called, so we enqueue
1184 * setup request here
1185 */
1186 dwc2_hsotg_enqueue_setup(hsotg);
1187}
1188
1189/**
1190 * dwc2_hsotg_process_control - process a control request
1191 * @hsotg: The device state
1192 * @ctrl: The control request received
1193 *
1194 * The controller has received the SETUP phase of a control request, and
1195 * needs to work out what to do next (and whether to pass it on to the
1196 * gadget driver).
1197 */
1198static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1199 struct usb_ctrlrequest *ctrl)
1200{
1201 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1202 int ret = 0;
1203 u32 dcfg;
1204
1205 dev_dbg(hsotg->dev,
1206 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1207 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1208 ctrl->wIndex, ctrl->wLength);
1209
1210 if (ctrl->wLength == 0) {
1211 ep0->dir_in = 1;
1212 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1213 } else if (ctrl->bRequestType & USB_DIR_IN) {
1214 ep0->dir_in = 1;
1215 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1216 } else {
1217 ep0->dir_in = 0;
1218 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1219 }
1220
1221 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1222 switch (ctrl->bRequest) {
1223 case USB_REQ_SET_ADDRESS:
1224 hsotg->connected = 1;
1225 dcfg = dwc2_readl(hsotg->regs + DCFG);
1226 dcfg &= ~DCFG_DEVADDR_MASK;
1227 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1228 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1229 dwc2_writel(dcfg, hsotg->regs + DCFG);
1230
1231 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1232
1233 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1234 return;
1235
1236 case USB_REQ_GET_STATUS:
1237 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1238 break;
1239
1240 case USB_REQ_CLEAR_FEATURE:
1241 case USB_REQ_SET_FEATURE:
1242 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1243 break;
1244 }
1245 }
1246
1247 /* as a fallback, try delivering it to the driver to deal with */
1248
1249 if (ret == 0 && hsotg->driver) {
1250 spin_unlock(&hsotg->lock);
1251 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1252 spin_lock(&hsotg->lock);
1253 if (ret < 0)
1254 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1255 }
1256
1257 /*
1258 * the request is either unhandlable, or is not formatted correctly
1259 * so respond with a STALL for the status stage to indicate failure.
1260 */
1261
1262 if (ret < 0)
1263 dwc2_hsotg_stall_ep0(hsotg);
1264}
1265
1266/**
1267 * dwc2_hsotg_complete_setup - completion of a setup transfer
1268 * @ep: The endpoint the request was on.
1269 * @req: The request completed.
1270 *
1271 * Called on completion of any requests the driver itself submitted for
1272 * EP0 setup packets
1273 */
1274static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1275 struct usb_request *req)
1276{
1277 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1278 struct dwc2_hsotg *hsotg = hs_ep->parent;
1279
1280 if (req->status < 0) {
1281 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1282 return;
1283 }
1284
1285 spin_lock(&hsotg->lock);
1286 if (req->actual == 0)
1287 dwc2_hsotg_enqueue_setup(hsotg);
1288 else
1289 dwc2_hsotg_process_control(hsotg, req->buf);
1290 spin_unlock(&hsotg->lock);
1291}
1292
1293/**
1294 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1295 * @hsotg: The device state.
1296 *
1297 * Enqueue a request on EP0 if necessary to received any SETUP packets
1298 * received from the host.
1299 */
1300static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1301{
1302 struct usb_request *req = hsotg->ctrl_req;
1303 struct dwc2_hsotg_req *hs_req = our_req(req);
1304 int ret;
1305
1306 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1307
1308 req->zero = 0;
1309 req->length = 8;
1310 req->buf = hsotg->ctrl_buff;
1311 req->complete = dwc2_hsotg_complete_setup;
1312
1313 if (!list_empty(&hs_req->queue)) {
1314 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1315 return;
1316 }
1317
1318 hsotg->eps_out[0]->dir_in = 0;
1319 hsotg->eps_out[0]->send_zlp = 0;
1320 hsotg->ep0_state = DWC2_EP0_SETUP;
1321
1322 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1323 if (ret < 0) {
1324 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1325 /*
1326 * Don't think there's much we can do other than watch the
1327 * driver fail.
1328 */
1329 }
1330}
1331
1332static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1333 struct dwc2_hsotg_ep *hs_ep)
1334{
1335 u32 ctrl;
1336 u8 index = hs_ep->index;
1337 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1338 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1339
1340 if (hs_ep->dir_in)
1341 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
1342 index);
1343 else
1344 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1345 index);
1346
1347 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1348 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1349 epsiz_reg);
1350
1351 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1352 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1353 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1354 ctrl |= DXEPCTL_USBACTEP;
1355 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1356}
1357
1358/**
1359 * dwc2_hsotg_complete_request - complete a request given to us
1360 * @hsotg: The device state.
1361 * @hs_ep: The endpoint the request was on.
1362 * @hs_req: The request to complete.
1363 * @result: The result code (0 => Ok, otherwise errno)
1364 *
1365 * The given request has finished, so call the necessary completion
1366 * if it has one and then look to see if we can start a new request
1367 * on the endpoint.
1368 *
1369 * Note, expects the ep to already be locked as appropriate.
1370 */
1371static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1372 struct dwc2_hsotg_ep *hs_ep,
1373 struct dwc2_hsotg_req *hs_req,
1374 int result)
1375{
1376 bool restart;
1377
1378 if (!hs_req) {
1379 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1380 return;
1381 }
1382
1383 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1384 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1385
1386 /*
1387 * only replace the status if we've not already set an error
1388 * from a previous transaction
1389 */
1390
1391 if (hs_req->req.status == -EINPROGRESS)
1392 hs_req->req.status = result;
1393
1394 if (using_dma(hsotg))
1395 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1396
1397 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
1398
1399 hs_ep->req = NULL;
1400 list_del_init(&hs_req->queue);
1401
1402 /*
1403 * call the complete request with the locks off, just in case the
1404 * request tries to queue more work for this endpoint.
1405 */
1406
1407 if (hs_req->req.complete) {
1408 spin_unlock(&hsotg->lock);
1409 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
1410 spin_lock(&hsotg->lock);
1411 }
1412
1413 /*
1414 * Look to see if there is anything else to do. Note, the completion
1415 * of the previous request may have caused a new request to be started
1416 * so be careful when doing this.
1417 */
1418
1419 if (!hs_ep->req && result >= 0) {
1420 restart = !list_empty(&hs_ep->queue);
1421 if (restart) {
1422 hs_req = get_ep_head(hs_ep);
1423 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1424 }
1425 }
1426}
1427
1428/**
1429 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
1430 * @hsotg: The device state.
1431 * @ep_idx: The endpoint index for the data
1432 * @size: The size of data in the fifo, in bytes
1433 *
1434 * The FIFO status shows there is data to read from the FIFO for a given
1435 * endpoint, so sort out whether we need to read the data into a request
1436 * that has been made for that endpoint.
1437 */
1438static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
1439{
1440 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
1441 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1442 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1443 int to_read;
1444 int max_req;
1445 int read_ptr;
1446
1447
1448 if (!hs_req) {
1449 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
1450 int ptr;
1451
1452 dev_dbg(hsotg->dev,
1453 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1454 __func__, size, ep_idx, epctl);
1455
1456 /* dump the data from the FIFO, we've nothing we can do */
1457 for (ptr = 0; ptr < size; ptr += 4)
1458 (void)dwc2_readl(fifo);
1459
1460 return;
1461 }
1462
1463 to_read = size;
1464 read_ptr = hs_req->req.actual;
1465 max_req = hs_req->req.length - read_ptr;
1466
1467 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1468 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1469
1470 if (to_read > max_req) {
1471 /*
1472 * more data appeared than we where willing
1473 * to deal with in this request.
1474 */
1475
1476 /* currently we don't deal this */
1477 WARN_ON_ONCE(1);
1478 }
1479
1480 hs_ep->total_data += to_read;
1481 hs_req->req.actual += to_read;
1482 to_read = DIV_ROUND_UP(to_read, 4);
1483
1484 /*
1485 * note, we might over-write the buffer end by 3 bytes depending on
1486 * alignment of the data.
1487 */
1488 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
1489}
1490
1491/**
1492 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
1493 * @hsotg: The device instance
1494 * @dir_in: If IN zlp
1495 *
1496 * Generate a zero-length IN packet request for terminating a SETUP
1497 * transaction.
1498 *
1499 * Note, since we don't write any data to the TxFIFO, then it is
1500 * currently believed that we do not need to wait for any space in
1501 * the TxFIFO.
1502 */
1503static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
1504{
1505 /* eps_out[0] is used in both directions */
1506 hsotg->eps_out[0]->dir_in = dir_in;
1507 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
1508
1509 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
1510}
1511
1512static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
1513 u32 epctl_reg)
1514{
1515 u32 ctrl;
1516
1517 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1518 if (ctrl & DXEPCTL_EOFRNUM)
1519 ctrl |= DXEPCTL_SETEVENFR;
1520 else
1521 ctrl |= DXEPCTL_SETODDFR;
1522 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1523}
1524
1525/**
1526 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1527 * @hsotg: The device instance
1528 * @epnum: The endpoint received from
1529 *
1530 * The RXFIFO has delivered an OutDone event, which means that the data
1531 * transfer for an OUT endpoint has been completed, either by a short
1532 * packet or by the finish of a transfer.
1533 */
1534static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
1535{
1536 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
1537 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
1538 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1539 struct usb_request *req = &hs_req->req;
1540 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1541 int result = 0;
1542
1543 if (!hs_req) {
1544 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1545 return;
1546 }
1547
1548 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
1549 dev_dbg(hsotg->dev, "zlp packet received\n");
1550 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1551 dwc2_hsotg_enqueue_setup(hsotg);
1552 return;
1553 }
1554
1555 if (using_dma(hsotg)) {
1556 unsigned size_done;
1557
1558 /*
1559 * Calculate the size of the transfer by checking how much
1560 * is left in the endpoint size register and then working it
1561 * out from the amount we loaded for the transfer.
1562 *
1563 * We need to do this as DMA pointers are always 32bit aligned
1564 * so may overshoot/undershoot the transfer.
1565 */
1566
1567 size_done = hs_ep->size_loaded - size_left;
1568 size_done += hs_ep->last_load;
1569
1570 req->actual = size_done;
1571 }
1572
1573 /* if there is more request to do, schedule new transfer */
1574 if (req->actual < req->length && size_left == 0) {
1575 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1576 return;
1577 }
1578
1579 if (req->actual < req->length && req->short_not_ok) {
1580 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1581 __func__, req->actual, req->length);
1582
1583 /*
1584 * todo - what should we return here? there's no one else
1585 * even bothering to check the status.
1586 */
1587 }
1588
1589 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
1590 /* Move to STATUS IN */
1591 dwc2_hsotg_ep0_zlp(hsotg, true);
1592 return;
1593 }
1594
1595 /*
1596 * Slave mode OUT transfers do not go through XferComplete so
1597 * adjust the ISOC parity here.
1598 */
1599 if (!using_dma(hsotg)) {
1600 hs_ep->has_correct_parity = 1;
1601 if (hs_ep->isochronous && hs_ep->interval == 1)
1602 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
1603 }
1604
1605 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1606}
1607
1608/**
1609 * dwc2_hsotg_read_frameno - read current frame number
1610 * @hsotg: The device instance
1611 *
1612 * Return the current frame number
1613 */
1614static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
1615{
1616 u32 dsts;
1617
1618 dsts = dwc2_readl(hsotg->regs + DSTS);
1619 dsts &= DSTS_SOFFN_MASK;
1620 dsts >>= DSTS_SOFFN_SHIFT;
1621
1622 return dsts;
1623}
1624
1625/**
1626 * dwc2_hsotg_handle_rx - RX FIFO has data
1627 * @hsotg: The device instance
1628 *
1629 * The IRQ handler has detected that the RX FIFO has some data in it
1630 * that requires processing, so find out what is in there and do the
1631 * appropriate read.
1632 *
1633 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1634 * chunks, so if you have x packets received on an endpoint you'll get x
1635 * FIFO events delivered, each with a packet's worth of data in it.
1636 *
1637 * When using DMA, we should not be processing events from the RXFIFO
1638 * as the actual data should be sent to the memory directly and we turn
1639 * on the completion interrupts to get notifications of transfer completion.
1640 */
1641static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
1642{
1643 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
1644 u32 epnum, status, size;
1645
1646 WARN_ON(using_dma(hsotg));
1647
1648 epnum = grxstsr & GRXSTS_EPNUM_MASK;
1649 status = grxstsr & GRXSTS_PKTSTS_MASK;
1650
1651 size = grxstsr & GRXSTS_BYTECNT_MASK;
1652 size >>= GRXSTS_BYTECNT_SHIFT;
1653
1654 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1655 __func__, grxstsr, size, epnum);
1656
1657 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
1658 case GRXSTS_PKTSTS_GLOBALOUTNAK:
1659 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
1660 break;
1661
1662 case GRXSTS_PKTSTS_OUTDONE:
1663 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1664 dwc2_hsotg_read_frameno(hsotg));
1665
1666 if (!using_dma(hsotg))
1667 dwc2_hsotg_handle_outdone(hsotg, epnum);
1668 break;
1669
1670 case GRXSTS_PKTSTS_SETUPDONE:
1671 dev_dbg(hsotg->dev,
1672 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1673 dwc2_hsotg_read_frameno(hsotg),
1674 dwc2_readl(hsotg->regs + DOEPCTL(0)));
1675 /*
1676 * Call dwc2_hsotg_handle_outdone here if it was not called from
1677 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
1678 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
1679 */
1680 if (hsotg->ep0_state == DWC2_EP0_SETUP)
1681 dwc2_hsotg_handle_outdone(hsotg, epnum);
1682 break;
1683
1684 case GRXSTS_PKTSTS_OUTRX:
1685 dwc2_hsotg_rx_data(hsotg, epnum, size);
1686 break;
1687
1688 case GRXSTS_PKTSTS_SETUPRX:
1689 dev_dbg(hsotg->dev,
1690 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1691 dwc2_hsotg_read_frameno(hsotg),
1692 dwc2_readl(hsotg->regs + DOEPCTL(0)));
1693
1694 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
1695
1696 dwc2_hsotg_rx_data(hsotg, epnum, size);
1697 break;
1698
1699 default:
1700 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1701 __func__, grxstsr);
1702
1703 dwc2_hsotg_dump(hsotg);
1704 break;
1705 }
1706}
1707
1708/**
1709 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
1710 * @mps: The maximum packet size in bytes.
1711 */
1712static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
1713{
1714 switch (mps) {
1715 case 64:
1716 return D0EPCTL_MPS_64;
1717 case 32:
1718 return D0EPCTL_MPS_32;
1719 case 16:
1720 return D0EPCTL_MPS_16;
1721 case 8:
1722 return D0EPCTL_MPS_8;
1723 }
1724
1725 /* bad max packet size, warn and return invalid result */
1726 WARN_ON(1);
1727 return (u32)-1;
1728}
1729
1730/**
1731 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1732 * @hsotg: The driver state.
1733 * @ep: The index number of the endpoint
1734 * @mps: The maximum packet size in bytes
1735 *
1736 * Configure the maximum packet size for the given endpoint, updating
1737 * the hardware control registers to reflect this.
1738 */
1739static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
1740 unsigned int ep, unsigned int mps, unsigned int dir_in)
1741{
1742 struct dwc2_hsotg_ep *hs_ep;
1743 void __iomem *regs = hsotg->regs;
1744 u32 mpsval;
1745 u32 mcval;
1746 u32 reg;
1747
1748 hs_ep = index_to_ep(hsotg, ep, dir_in);
1749 if (!hs_ep)
1750 return;
1751
1752 if (ep == 0) {
1753 /* EP0 is a special case */
1754 mpsval = dwc2_hsotg_ep0_mps(mps);
1755 if (mpsval > 3)
1756 goto bad_mps;
1757 hs_ep->ep.maxpacket = mps;
1758 hs_ep->mc = 1;
1759 } else {
1760 mpsval = mps & DXEPCTL_MPS_MASK;
1761 if (mpsval > 1024)
1762 goto bad_mps;
1763 mcval = ((mps >> 11) & 0x3) + 1;
1764 hs_ep->mc = mcval;
1765 if (mcval > 3)
1766 goto bad_mps;
1767 hs_ep->ep.maxpacket = mpsval;
1768 }
1769
1770 if (dir_in) {
1771 reg = dwc2_readl(regs + DIEPCTL(ep));
1772 reg &= ~DXEPCTL_MPS_MASK;
1773 reg |= mpsval;
1774 dwc2_writel(reg, regs + DIEPCTL(ep));
1775 } else {
1776 reg = dwc2_readl(regs + DOEPCTL(ep));
1777 reg &= ~DXEPCTL_MPS_MASK;
1778 reg |= mpsval;
1779 dwc2_writel(reg, regs + DOEPCTL(ep));
1780 }
1781
1782 return;
1783
1784bad_mps:
1785 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1786}
1787
1788/**
1789 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
1790 * @hsotg: The driver state
1791 * @idx: The index for the endpoint (0..15)
1792 */
1793static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
1794{
1795 int timeout;
1796 int val;
1797
1798 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1799 hsotg->regs + GRSTCTL);
1800
1801 /* wait until the fifo is flushed */
1802 timeout = 100;
1803
1804 while (1) {
1805 val = dwc2_readl(hsotg->regs + GRSTCTL);
1806
1807 if ((val & (GRSTCTL_TXFFLSH)) == 0)
1808 break;
1809
1810 if (--timeout == 0) {
1811 dev_err(hsotg->dev,
1812 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1813 __func__, val);
1814 break;
1815 }
1816
1817 udelay(1);
1818 }
1819}
1820
1821/**
1822 * dwc2_hsotg_trytx - check to see if anything needs transmitting
1823 * @hsotg: The driver state
1824 * @hs_ep: The driver endpoint to check.
1825 *
1826 * Check to see if there is a request that has data to send, and if so
1827 * make an attempt to write data into the FIFO.
1828 */
1829static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
1830 struct dwc2_hsotg_ep *hs_ep)
1831{
1832 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1833
1834 if (!hs_ep->dir_in || !hs_req) {
1835 /**
1836 * if request is not enqueued, we disable interrupts
1837 * for endpoints, excepting ep0
1838 */
1839 if (hs_ep->index != 0)
1840 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
1841 hs_ep->dir_in, 0);
1842 return 0;
1843 }
1844
1845 if (hs_req->req.actual < hs_req->req.length) {
1846 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1847 hs_ep->index);
1848 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1849 }
1850
1851 return 0;
1852}
1853
1854/**
1855 * dwc2_hsotg_complete_in - complete IN transfer
1856 * @hsotg: The device state.
1857 * @hs_ep: The endpoint that has just completed.
1858 *
1859 * An IN transfer has been completed, update the transfer's state and then
1860 * call the relevant completion routines.
1861 */
1862static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
1863 struct dwc2_hsotg_ep *hs_ep)
1864{
1865 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1866 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1867 int size_left, size_done;
1868
1869 if (!hs_req) {
1870 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1871 return;
1872 }
1873
1874 /* Finish ZLP handling for IN EP0 transactions */
1875 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
1876 dev_dbg(hsotg->dev, "zlp packet sent\n");
1877 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1878 if (hsotg->test_mode) {
1879 int ret;
1880
1881 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
1882 if (ret < 0) {
1883 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
1884 hsotg->test_mode);
1885 dwc2_hsotg_stall_ep0(hsotg);
1886 return;
1887 }
1888 }
1889 dwc2_hsotg_enqueue_setup(hsotg);
1890 return;
1891 }
1892
1893 /*
1894 * Calculate the size of the transfer by checking how much is left
1895 * in the endpoint size register and then working it out from
1896 * the amount we loaded for the transfer.
1897 *
1898 * We do this even for DMA, as the transfer may have incremented
1899 * past the end of the buffer (DMA transfers are always 32bit
1900 * aligned).
1901 */
1902
1903 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1904
1905 size_done = hs_ep->size_loaded - size_left;
1906 size_done += hs_ep->last_load;
1907
1908 if (hs_req->req.actual != size_done)
1909 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1910 __func__, hs_req->req.actual, size_done);
1911
1912 hs_req->req.actual = size_done;
1913 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1914 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1915
1916 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1917 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1918 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1919 return;
1920 }
1921
1922 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
1923 if (hs_ep->send_zlp) {
1924 dwc2_hsotg_program_zlp(hsotg, hs_ep);
1925 hs_ep->send_zlp = 0;
1926 /* transfer will be completed on next complete interrupt */
1927 return;
1928 }
1929
1930 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
1931 /* Move to STATUS OUT */
1932 dwc2_hsotg_ep0_zlp(hsotg, false);
1933 return;
1934 }
1935
1936 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1937}
1938
1939/**
1940 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
1941 * @hsotg: The driver state
1942 * @idx: The index for the endpoint (0..15)
1943 * @dir_in: Set if this is an IN endpoint
1944 *
1945 * Process and clear any interrupt pending for an individual endpoint
1946 */
1947static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
1948 int dir_in)
1949{
1950 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
1951 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1952 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1953 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1954 u32 ints;
1955 u32 ctrl;
1956
1957 ints = dwc2_readl(hsotg->regs + epint_reg);
1958 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1959
1960 /* Clear endpoint interrupts */
1961 dwc2_writel(ints, hsotg->regs + epint_reg);
1962
1963 if (!hs_ep) {
1964 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
1965 __func__, idx, dir_in ? "in" : "out");
1966 return;
1967 }
1968
1969 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1970 __func__, idx, dir_in ? "in" : "out", ints);
1971
1972 /* Don't process XferCompl interrupt if it is a setup packet */
1973 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
1974 ints &= ~DXEPINT_XFERCOMPL;
1975
1976 if (ints & DXEPINT_XFERCOMPL) {
1977 hs_ep->has_correct_parity = 1;
1978 if (hs_ep->isochronous && hs_ep->interval == 1)
1979 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
1980
1981 dev_dbg(hsotg->dev,
1982 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
1983 __func__, dwc2_readl(hsotg->regs + epctl_reg),
1984 dwc2_readl(hsotg->regs + epsiz_reg));
1985
1986 /*
1987 * we get OutDone from the FIFO, so we only need to look
1988 * at completing IN requests here
1989 */
1990 if (dir_in) {
1991 dwc2_hsotg_complete_in(hsotg, hs_ep);
1992
1993 if (idx == 0 && !hs_ep->req)
1994 dwc2_hsotg_enqueue_setup(hsotg);
1995 } else if (using_dma(hsotg)) {
1996 /*
1997 * We're using DMA, we need to fire an OutDone here
1998 * as we ignore the RXFIFO.
1999 */
2000
2001 dwc2_hsotg_handle_outdone(hsotg, idx);
2002 }
2003 }
2004
2005 if (ints & DXEPINT_EPDISBLD) {
2006 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2007
2008 if (dir_in) {
2009 int epctl = dwc2_readl(hsotg->regs + epctl_reg);
2010
2011 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2012
2013 if ((epctl & DXEPCTL_STALL) &&
2014 (epctl & DXEPCTL_EPTYPE_BULK)) {
2015 int dctl = dwc2_readl(hsotg->regs + DCTL);
2016
2017 dctl |= DCTL_CGNPINNAK;
2018 dwc2_writel(dctl, hsotg->regs + DCTL);
2019 }
2020 }
2021 }
2022
2023 if (ints & DXEPINT_AHBERR)
2024 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2025
2026 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
2027 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2028
2029 if (using_dma(hsotg) && idx == 0) {
2030 /*
2031 * this is the notification we've received a
2032 * setup packet. In non-DMA mode we'd get this
2033 * from the RXFIFO, instead we need to process
2034 * the setup here.
2035 */
2036
2037 if (dir_in)
2038 WARN_ON_ONCE(1);
2039 else
2040 dwc2_hsotg_handle_outdone(hsotg, 0);
2041 }
2042 }
2043
2044 if (ints & DXEPINT_BACK2BACKSETUP)
2045 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2046
2047 if (dir_in && !hs_ep->isochronous) {
2048 /* not sure if this is important, but we'll clear it anyway */
2049 if (ints & DIEPMSK_INTKNTXFEMPMSK) {
2050 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2051 __func__, idx);
2052 }
2053
2054 /* this probably means something bad is happening */
2055 if (ints & DIEPMSK_INTKNEPMISMSK) {
2056 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2057 __func__, idx);
2058 }
2059
2060 /* FIFO has space or is empty (see GAHBCFG) */
2061 if (hsotg->dedicated_fifos &&
2062 ints & DIEPMSK_TXFIFOEMPTY) {
2063 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2064 __func__, idx);
2065 if (!using_dma(hsotg))
2066 dwc2_hsotg_trytx(hsotg, hs_ep);
2067 }
2068 }
2069}
2070
2071/**
2072 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2073 * @hsotg: The device state.
2074 *
2075 * Handle updating the device settings after the enumeration phase has
2076 * been completed.
2077 */
2078static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
2079{
2080 u32 dsts = dwc2_readl(hsotg->regs + DSTS);
2081 int ep0_mps = 0, ep_mps = 8;
2082
2083 /*
2084 * This should signal the finish of the enumeration phase
2085 * of the USB handshaking, so we should now know what rate
2086 * we connected at.
2087 */
2088
2089 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
2090
2091 /*
2092 * note, since we're limited by the size of transfer on EP0, and
2093 * it seems IN transfers must be a even number of packets we do
2094 * not advertise a 64byte MPS on EP0.
2095 */
2096
2097 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2098 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
2099 case DSTS_ENUMSPD_FS:
2100 case DSTS_ENUMSPD_FS48:
2101 hsotg->gadget.speed = USB_SPEED_FULL;
2102 ep0_mps = EP0_MPS_LIMIT;
2103 ep_mps = 1023;
2104 break;
2105
2106 case DSTS_ENUMSPD_HS:
2107 hsotg->gadget.speed = USB_SPEED_HIGH;
2108 ep0_mps = EP0_MPS_LIMIT;
2109 ep_mps = 1024;
2110 break;
2111
2112 case DSTS_ENUMSPD_LS:
2113 hsotg->gadget.speed = USB_SPEED_LOW;
2114 /*
2115 * note, we don't actually support LS in this driver at the
2116 * moment, and the documentation seems to imply that it isn't
2117 * supported by the PHYs on some of the devices.
2118 */
2119 break;
2120 }
2121 dev_info(hsotg->dev, "new device is %s\n",
2122 usb_speed_string(hsotg->gadget.speed));
2123
2124 /*
2125 * we should now know the maximum packet size for an
2126 * endpoint, so set the endpoints to a default value.
2127 */
2128
2129 if (ep0_mps) {
2130 int i;
2131 /* Initialize ep0 for both in and out directions */
2132 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1);
2133 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0);
2134 for (i = 1; i < hsotg->num_of_eps; i++) {
2135 if (hsotg->eps_in[i])
2136 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1);
2137 if (hsotg->eps_out[i])
2138 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0);
2139 }
2140 }
2141
2142 /* ensure after enumeration our EP0 is active */
2143
2144 dwc2_hsotg_enqueue_setup(hsotg);
2145
2146 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2147 dwc2_readl(hsotg->regs + DIEPCTL0),
2148 dwc2_readl(hsotg->regs + DOEPCTL0));
2149}
2150
2151/**
2152 * kill_all_requests - remove all requests from the endpoint's queue
2153 * @hsotg: The device state.
2154 * @ep: The endpoint the requests may be on.
2155 * @result: The result code to use.
2156 *
2157 * Go through the requests on the given endpoint and mark them
2158 * completed with the given result code.
2159 */
2160static void kill_all_requests(struct dwc2_hsotg *hsotg,
2161 struct dwc2_hsotg_ep *ep,
2162 int result)
2163{
2164 struct dwc2_hsotg_req *req, *treq;
2165 unsigned size;
2166
2167 ep->req = NULL;
2168
2169 list_for_each_entry_safe(req, treq, &ep->queue, queue)
2170 dwc2_hsotg_complete_request(hsotg, ep, req,
2171 result);
2172
2173 if (!hsotg->dedicated_fifos)
2174 return;
2175 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
2176 if (size < ep->fifo_size)
2177 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
2178}
2179
2180/**
2181 * dwc2_hsotg_disconnect - disconnect service
2182 * @hsotg: The device state.
2183 *
2184 * The device has been disconnected. Remove all current
2185 * transactions and signal the gadget driver that this
2186 * has happened.
2187 */
2188void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
2189{
2190 unsigned ep;
2191
2192 if (!hsotg->connected)
2193 return;
2194
2195 hsotg->connected = 0;
2196 hsotg->test_mode = 0;
2197
2198 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
2199 if (hsotg->eps_in[ep])
2200 kill_all_requests(hsotg, hsotg->eps_in[ep],
2201 -ESHUTDOWN);
2202 if (hsotg->eps_out[ep])
2203 kill_all_requests(hsotg, hsotg->eps_out[ep],
2204 -ESHUTDOWN);
2205 }
2206
2207 call_gadget(hsotg, disconnect);
2208 hsotg->lx_state = DWC2_L3;
2209}
2210
2211/**
2212 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2213 * @hsotg: The device state:
2214 * @periodic: True if this is a periodic FIFO interrupt
2215 */
2216static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
2217{
2218 struct dwc2_hsotg_ep *ep;
2219 int epno, ret;
2220
2221 /* look through for any more data to transmit */
2222 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2223 ep = index_to_ep(hsotg, epno, 1);
2224
2225 if (!ep)
2226 continue;
2227
2228 if (!ep->dir_in)
2229 continue;
2230
2231 if ((periodic && !ep->periodic) ||
2232 (!periodic && ep->periodic))
2233 continue;
2234
2235 ret = dwc2_hsotg_trytx(hsotg, ep);
2236 if (ret < 0)
2237 break;
2238 }
2239}
2240
2241/* IRQ flags which will trigger a retry around the IRQ loop */
2242#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2243 GINTSTS_PTXFEMP | \
2244 GINTSTS_RXFLVL)
2245
2246/**
2247 * dwc2_hsotg_core_init - issue softreset to the core
2248 * @hsotg: The device state
2249 *
2250 * Issue a soft reset to the core, and await the core finishing it.
2251 */
2252void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
2253 bool is_usb_reset)
2254{
2255 u32 intmsk;
2256 u32 val;
2257 u32 usbcfg;
2258
2259 /* Kill any ep0 requests as controller will be reinitialized */
2260 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
2261
2262 if (!is_usb_reset)
2263 if (dwc2_core_reset(hsotg))
2264 return;
2265
2266 /*
2267 * we must now enable ep0 ready for host detection and then
2268 * set configuration.
2269 */
2270
2271 /* keep other bits untouched (so e.g. forced modes are not lost) */
2272 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2273 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
2274 GUSBCFG_HNPCAP);
2275
2276 /* set the PLL on, remove the HNP/SRP and set the PHY */
2277 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
2278 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
2279 (val << GUSBCFG_USBTRDTIM_SHIFT);
2280 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2281
2282 dwc2_hsotg_init_fifo(hsotg);
2283
2284 if (!is_usb_reset)
2285 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2286
2287 dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
2288
2289 /* Clear any pending OTG interrupts */
2290 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
2291
2292 /* Clear any pending interrupts */
2293 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
2294 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
2295 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
2296 GINTSTS_USBRST | GINTSTS_RESETDET |
2297 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
2298 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
2299 GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
2300
2301 if (hsotg->core_params->external_id_pin_ctl <= 0)
2302 intmsk |= GINTSTS_CONIDSTSCHNG;
2303
2304 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
2305
2306 if (using_dma(hsotg))
2307 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
2308 (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT),
2309 hsotg->regs + GAHBCFG);
2310 else
2311 dwc2_writel(((hsotg->dedicated_fifos) ?
2312 (GAHBCFG_NP_TXF_EMP_LVL |
2313 GAHBCFG_P_TXF_EMP_LVL) : 0) |
2314 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
2315
2316 /*
2317 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2318 * when we have no data to transfer. Otherwise we get being flooded by
2319 * interrupts.
2320 */
2321
2322 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
2323 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
2324 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
2325 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2326 DIEPMSK_INTKNEPMISMSK,
2327 hsotg->regs + DIEPMSK);
2328
2329 /*
2330 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2331 * DMA mode we may need this.
2332 */
2333 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
2334 DIEPMSK_TIMEOUTMSK) : 0) |
2335 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
2336 DOEPMSK_SETUPMSK,
2337 hsotg->regs + DOEPMSK);
2338
2339 dwc2_writel(0, hsotg->regs + DAINTMSK);
2340
2341 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2342 dwc2_readl(hsotg->regs + DIEPCTL0),
2343 dwc2_readl(hsotg->regs + DOEPCTL0));
2344
2345 /* enable in and out endpoint interrupts */
2346 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
2347
2348 /*
2349 * Enable the RXFIFO when in slave mode, as this is how we collect
2350 * the data. In DMA mode, we get events from the FIFO but also
2351 * things we cannot process, so do not use it.
2352 */
2353 if (!using_dma(hsotg))
2354 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
2355
2356 /* Enable interrupts for EP0 in and out */
2357 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2358 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2359
2360 if (!is_usb_reset) {
2361 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2362 udelay(10); /* see openiboot */
2363 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2364 }
2365
2366 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
2367
2368 /*
2369 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2370 * writing to the EPCTL register..
2371 */
2372
2373 /* set to read 1 8byte packet */
2374 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2375 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
2376
2377 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2378 DXEPCTL_CNAK | DXEPCTL_EPENA |
2379 DXEPCTL_USBACTEP,
2380 hsotg->regs + DOEPCTL0);
2381
2382 /* enable, but don't activate EP0in */
2383 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2384 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
2385
2386 dwc2_hsotg_enqueue_setup(hsotg);
2387
2388 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2389 dwc2_readl(hsotg->regs + DIEPCTL0),
2390 dwc2_readl(hsotg->regs + DOEPCTL0));
2391
2392 /* clear global NAKs */
2393 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
2394 if (!is_usb_reset)
2395 val |= DCTL_SFTDISCON;
2396 __orr32(hsotg->regs + DCTL, val);
2397
2398 /* must be at-least 3ms to allow bus to see disconnect */
2399 mdelay(3);
2400
2401 hsotg->lx_state = DWC2_L0;
2402}
2403
2404static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
2405{
2406 /* set the soft-disconnect bit */
2407 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2408}
2409
2410void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
2411{
2412 /* remove the soft-disconnect and let's go */
2413 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2414}
2415
2416/**
2417 * dwc2_hsotg_irq - handle device interrupt
2418 * @irq: The IRQ number triggered
2419 * @pw: The pw value when registered the handler.
2420 */
2421static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
2422{
2423 struct dwc2_hsotg *hsotg = pw;
2424 int retry_count = 8;
2425 u32 gintsts;
2426 u32 gintmsk;
2427
2428 spin_lock(&hsotg->lock);
2429irq_retry:
2430 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
2431 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2432
2433 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2434 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2435
2436 gintsts &= gintmsk;
2437
2438 if (gintsts & GINTSTS_RESETDET) {
2439 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
2440
2441 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
2442
2443 /* This event must be used only if controller is suspended */
2444 if (hsotg->lx_state == DWC2_L2) {
2445 dwc2_exit_hibernation(hsotg, true);
2446 hsotg->lx_state = DWC2_L0;
2447 }
2448 }
2449
2450 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
2451
2452 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
2453 u32 connected = hsotg->connected;
2454
2455 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
2456 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2457 dwc2_readl(hsotg->regs + GNPTXSTS));
2458
2459 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
2460
2461 /* Report disconnection if it is not already done. */
2462 dwc2_hsotg_disconnect(hsotg);
2463
2464 if (usb_status & GOTGCTL_BSESVLD && connected)
2465 dwc2_hsotg_core_init_disconnected(hsotg, true);
2466 }
2467
2468 if (gintsts & GINTSTS_ENUMDONE) {
2469 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
2470
2471 dwc2_hsotg_irq_enumdone(hsotg);
2472 }
2473
2474 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
2475 u32 daint = dwc2_readl(hsotg->regs + DAINT);
2476 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
2477 u32 daint_out, daint_in;
2478 int ep;
2479
2480 daint &= daintmsk;
2481 daint_out = daint >> DAINT_OUTEP_SHIFT;
2482 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
2483
2484 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2485
2486 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
2487 ep++, daint_out >>= 1) {
2488 if (daint_out & 1)
2489 dwc2_hsotg_epint(hsotg, ep, 0);
2490 }
2491
2492 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
2493 ep++, daint_in >>= 1) {
2494 if (daint_in & 1)
2495 dwc2_hsotg_epint(hsotg, ep, 1);
2496 }
2497 }
2498
2499 /* check both FIFOs */
2500
2501 if (gintsts & GINTSTS_NPTXFEMP) {
2502 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2503
2504 /*
2505 * Disable the interrupt to stop it happening again
2506 * unless one of these endpoint routines decides that
2507 * it needs re-enabling
2508 */
2509
2510 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
2511 dwc2_hsotg_irq_fifoempty(hsotg, false);
2512 }
2513
2514 if (gintsts & GINTSTS_PTXFEMP) {
2515 dev_dbg(hsotg->dev, "PTxFEmp\n");
2516
2517 /* See note in GINTSTS_NPTxFEmp */
2518
2519 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
2520 dwc2_hsotg_irq_fifoempty(hsotg, true);
2521 }
2522
2523 if (gintsts & GINTSTS_RXFLVL) {
2524 /*
2525 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2526 * we need to retry dwc2_hsotg_handle_rx if this is still
2527 * set.
2528 */
2529
2530 dwc2_hsotg_handle_rx(hsotg);
2531 }
2532
2533 if (gintsts & GINTSTS_ERLYSUSP) {
2534 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2535 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
2536 }
2537
2538 /*
2539 * these next two seem to crop-up occasionally causing the core
2540 * to shutdown the USB transfer, so try clearing them and logging
2541 * the occurrence.
2542 */
2543
2544 if (gintsts & GINTSTS_GOUTNAKEFF) {
2545 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2546
2547 __orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK);
2548
2549 dwc2_hsotg_dump(hsotg);
2550 }
2551
2552 if (gintsts & GINTSTS_GINNAKEFF) {
2553 dev_info(hsotg->dev, "GINNakEff triggered\n");
2554
2555 __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
2556
2557 dwc2_hsotg_dump(hsotg);
2558 }
2559
2560 if (gintsts & GINTSTS_INCOMPL_SOIN) {
2561 u32 idx, epctl_reg;
2562 struct dwc2_hsotg_ep *hs_ep;
2563
2564 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOIN\n", __func__);
2565 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
2566 hs_ep = hsotg->eps_in[idx];
2567
2568 if (!hs_ep->isochronous || hs_ep->has_correct_parity)
2569 continue;
2570
2571 epctl_reg = DIEPCTL(idx);
2572 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
2573 }
2574 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS);
2575 }
2576
2577 if (gintsts & GINTSTS_INCOMPL_SOOUT) {
2578 u32 idx, epctl_reg;
2579 struct dwc2_hsotg_ep *hs_ep;
2580
2581 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
2582 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
2583 hs_ep = hsotg->eps_out[idx];
2584
2585 if (!hs_ep->isochronous || hs_ep->has_correct_parity)
2586 continue;
2587
2588 epctl_reg = DOEPCTL(idx);
2589 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
2590 }
2591 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS);
2592 }
2593
2594 /*
2595 * if we've had fifo events, we should try and go around the
2596 * loop again to see if there's any point in returning yet.
2597 */
2598
2599 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2600 goto irq_retry;
2601
2602 spin_unlock(&hsotg->lock);
2603
2604 return IRQ_HANDLED;
2605}
2606
2607/**
2608 * dwc2_hsotg_ep_enable - enable the given endpoint
2609 * @ep: The USB endpint to configure
2610 * @desc: The USB endpoint descriptor to configure with.
2611 *
2612 * This is called from the USB gadget code's usb_ep_enable().
2613 */
2614static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
2615 const struct usb_endpoint_descriptor *desc)
2616{
2617 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2618 struct dwc2_hsotg *hsotg = hs_ep->parent;
2619 unsigned long flags;
2620 unsigned int index = hs_ep->index;
2621 u32 epctrl_reg;
2622 u32 epctrl;
2623 u32 mps;
2624 unsigned int dir_in;
2625 unsigned int i, val, size;
2626 int ret = 0;
2627
2628 dev_dbg(hsotg->dev,
2629 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2630 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2631 desc->wMaxPacketSize, desc->bInterval);
2632
2633 /* not to be called for EP0 */
2634 WARN_ON(index == 0);
2635
2636 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2637 if (dir_in != hs_ep->dir_in) {
2638 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2639 return -EINVAL;
2640 }
2641
2642 mps = usb_endpoint_maxp(desc);
2643
2644 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
2645
2646 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2647 epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2648
2649 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2650 __func__, epctrl, epctrl_reg);
2651
2652 spin_lock_irqsave(&hsotg->lock, flags);
2653
2654 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
2655 epctrl |= DXEPCTL_MPS(mps);
2656
2657 /*
2658 * mark the endpoint as active, otherwise the core may ignore
2659 * transactions entirely for this endpoint
2660 */
2661 epctrl |= DXEPCTL_USBACTEP;
2662
2663 /*
2664 * set the NAK status on the endpoint, otherwise we might try and
2665 * do something with data that we've yet got a request to process
2666 * since the RXFIFO will take data for an endpoint even if the
2667 * size register hasn't been set.
2668 */
2669
2670 epctrl |= DXEPCTL_SNAK;
2671
2672 /* update the endpoint state */
2673 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in);
2674
2675 /* default, set to non-periodic */
2676 hs_ep->isochronous = 0;
2677 hs_ep->periodic = 0;
2678 hs_ep->halted = 0;
2679 hs_ep->interval = desc->bInterval;
2680 hs_ep->has_correct_parity = 0;
2681
2682 if (hs_ep->interval > 1 && hs_ep->mc > 1)
2683 dev_err(hsotg->dev, "MC > 1 when interval is not 1\n");
2684
2685 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2686 case USB_ENDPOINT_XFER_ISOC:
2687 epctrl |= DXEPCTL_EPTYPE_ISO;
2688 epctrl |= DXEPCTL_SETEVENFR;
2689 hs_ep->isochronous = 1;
2690 if (dir_in)
2691 hs_ep->periodic = 1;
2692 break;
2693
2694 case USB_ENDPOINT_XFER_BULK:
2695 epctrl |= DXEPCTL_EPTYPE_BULK;
2696 break;
2697
2698 case USB_ENDPOINT_XFER_INT:
2699 if (dir_in)
2700 hs_ep->periodic = 1;
2701
2702 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
2703 break;
2704
2705 case USB_ENDPOINT_XFER_CONTROL:
2706 epctrl |= DXEPCTL_EPTYPE_CONTROL;
2707 break;
2708 }
2709
2710 /* If fifo is already allocated for this ep */
2711 if (hs_ep->fifo_index) {
2712 size = hs_ep->ep.maxpacket * hs_ep->mc;
2713 /* If bigger fifo is required deallocate current one */
2714 if (size > hs_ep->fifo_size) {
2715 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
2716 hs_ep->fifo_index = 0;
2717 hs_ep->fifo_size = 0;
2718 }
2719 }
2720
2721 /*
2722 * if the hardware has dedicated fifos, we must give each IN EP
2723 * a unique tx-fifo even if it is non-periodic.
2724 */
2725 if (dir_in && hsotg->dedicated_fifos && !hs_ep->fifo_index) {
2726 u32 fifo_index = 0;
2727 u32 fifo_size = UINT_MAX;
2728 size = hs_ep->ep.maxpacket*hs_ep->mc;
2729 for (i = 1; i < hsotg->num_of_eps; ++i) {
2730 if (hsotg->fifo_map & (1<<i))
2731 continue;
2732 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
2733 val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
2734 if (val < size)
2735 continue;
2736 /* Search for smallest acceptable fifo */
2737 if (val < fifo_size) {
2738 fifo_size = val;
2739 fifo_index = i;
2740 }
2741 }
2742 if (!fifo_index) {
2743 dev_err(hsotg->dev,
2744 "%s: No suitable fifo found\n", __func__);
2745 ret = -ENOMEM;
2746 goto error;
2747 }
2748 hsotg->fifo_map |= 1 << fifo_index;
2749 epctrl |= DXEPCTL_TXFNUM(fifo_index);
2750 hs_ep->fifo_index = fifo_index;
2751 hs_ep->fifo_size = fifo_size;
2752 }
2753
2754 /* for non control endpoints, set PID to D0 */
2755 if (index)
2756 epctrl |= DXEPCTL_SETD0PID;
2757
2758 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2759 __func__, epctrl);
2760
2761 dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
2762 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2763 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
2764
2765 /* enable the endpoint interrupt */
2766 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2767
2768error:
2769 spin_unlock_irqrestore(&hsotg->lock, flags);
2770 return ret;
2771}
2772
2773/**
2774 * dwc2_hsotg_ep_disable - disable given endpoint
2775 * @ep: The endpoint to disable.
2776 */
2777static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
2778{
2779 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2780 struct dwc2_hsotg *hsotg = hs_ep->parent;
2781 int dir_in = hs_ep->dir_in;
2782 int index = hs_ep->index;
2783 unsigned long flags;
2784 u32 epctrl_reg;
2785 u32 ctrl;
2786
2787 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2788
2789 if (ep == &hsotg->eps_out[0]->ep) {
2790 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2791 return -EINVAL;
2792 }
2793
2794 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2795
2796 spin_lock_irqsave(&hsotg->lock, flags);
2797
2798 hsotg->fifo_map &= ~(1<<hs_ep->fifo_index);
2799 hs_ep->fifo_index = 0;
2800 hs_ep->fifo_size = 0;
2801
2802 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2803 ctrl &= ~DXEPCTL_EPENA;
2804 ctrl &= ~DXEPCTL_USBACTEP;
2805 ctrl |= DXEPCTL_SNAK;
2806
2807 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2808 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
2809
2810 /* disable endpoint interrupts */
2811 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2812
2813 /* terminate all requests with shutdown */
2814 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
2815
2816 spin_unlock_irqrestore(&hsotg->lock, flags);
2817 return 0;
2818}
2819
2820/**
2821 * on_list - check request is on the given endpoint
2822 * @ep: The endpoint to check.
2823 * @test: The request to test if it is on the endpoint.
2824 */
2825static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
2826{
2827 struct dwc2_hsotg_req *req, *treq;
2828
2829 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2830 if (req == test)
2831 return true;
2832 }
2833
2834 return false;
2835}
2836
2837static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg,
2838 u32 bit, u32 timeout)
2839{
2840 u32 i;
2841
2842 for (i = 0; i < timeout; i++) {
2843 if (dwc2_readl(hs_otg->regs + reg) & bit)
2844 return 0;
2845 udelay(1);
2846 }
2847
2848 return -ETIMEDOUT;
2849}
2850
2851static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2852 struct dwc2_hsotg_ep *hs_ep)
2853{
2854 u32 epctrl_reg;
2855 u32 epint_reg;
2856
2857 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
2858 DOEPCTL(hs_ep->index);
2859 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
2860 DOEPINT(hs_ep->index);
2861
2862 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
2863 hs_ep->name);
2864 if (hs_ep->dir_in) {
2865 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
2866 /* Wait for Nak effect */
2867 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
2868 DXEPINT_INEPNAKEFF, 100))
2869 dev_warn(hsotg->dev,
2870 "%s: timeout DIEPINT.NAKEFF\n", __func__);
2871 } else {
2872 /* Clear any pending nak effect interrupt */
2873 dwc2_writel(GINTSTS_GOUTNAKEFF, hsotg->regs + GINTSTS);
2874
2875 __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
2876
2877 /* Wait for global nak to take effect */
2878 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
2879 GINTSTS_GOUTNAKEFF, 100))
2880 dev_warn(hsotg->dev,
2881 "%s: timeout GINTSTS.GOUTNAKEFF\n", __func__);
2882 }
2883
2884 /* Disable ep */
2885 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
2886
2887 /* Wait for ep to be disabled */
2888 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
2889 dev_warn(hsotg->dev,
2890 "%s: timeout DOEPCTL.EPDisable\n", __func__);
2891
2892 if (hs_ep->dir_in) {
2893 if (hsotg->dedicated_fifos) {
2894 dwc2_writel(GRSTCTL_TXFNUM(hs_ep->fifo_index) |
2895 GRSTCTL_TXFFLSH, hsotg->regs + GRSTCTL);
2896 /* Wait for fifo flush */
2897 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
2898 GRSTCTL_TXFFLSH, 100))
2899 dev_warn(hsotg->dev,
2900 "%s: timeout flushing fifos\n",
2901 __func__);
2902 }
2903 /* TODO: Flush shared tx fifo */
2904 } else {
2905 /* Remove global NAKs */
2906 __bic32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
2907 }
2908}
2909
2910/**
2911 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
2912 * @ep: The endpoint to dequeue.
2913 * @req: The request to be removed from a queue.
2914 */
2915static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2916{
2917 struct dwc2_hsotg_req *hs_req = our_req(req);
2918 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2919 struct dwc2_hsotg *hs = hs_ep->parent;
2920 unsigned long flags;
2921
2922 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2923
2924 spin_lock_irqsave(&hs->lock, flags);
2925
2926 if (!on_list(hs_ep, hs_req)) {
2927 spin_unlock_irqrestore(&hs->lock, flags);
2928 return -EINVAL;
2929 }
2930
2931 /* Dequeue already started request */
2932 if (req == &hs_ep->req->req)
2933 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
2934
2935 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2936 spin_unlock_irqrestore(&hs->lock, flags);
2937
2938 return 0;
2939}
2940
2941/**
2942 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
2943 * @ep: The endpoint to set halt.
2944 * @value: Set or unset the halt.
2945 */
2946static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2947{
2948 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2949 struct dwc2_hsotg *hs = hs_ep->parent;
2950 int index = hs_ep->index;
2951 u32 epreg;
2952 u32 epctl;
2953 u32 xfertype;
2954
2955 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2956
2957 if (index == 0) {
2958 if (value)
2959 dwc2_hsotg_stall_ep0(hs);
2960 else
2961 dev_warn(hs->dev,
2962 "%s: can't clear halt on ep0\n", __func__);
2963 return 0;
2964 }
2965
2966 if (hs_ep->dir_in) {
2967 epreg = DIEPCTL(index);
2968 epctl = dwc2_readl(hs->regs + epreg);
2969
2970 if (value) {
2971 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
2972 if (epctl & DXEPCTL_EPENA)
2973 epctl |= DXEPCTL_EPDIS;
2974 } else {
2975 epctl &= ~DXEPCTL_STALL;
2976 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2977 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2978 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2979 epctl |= DXEPCTL_SETD0PID;
2980 }
2981 dwc2_writel(epctl, hs->regs + epreg);
2982 } else {
2983
2984 epreg = DOEPCTL(index);
2985 epctl = dwc2_readl(hs->regs + epreg);
2986
2987 if (value)
2988 epctl |= DXEPCTL_STALL;
2989 else {
2990 epctl &= ~DXEPCTL_STALL;
2991 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2992 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2993 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2994 epctl |= DXEPCTL_SETD0PID;
2995 }
2996 dwc2_writel(epctl, hs->regs + epreg);
2997 }
2998
2999 hs_ep->halted = value;
3000
3001 return 0;
3002}
3003
3004/**
3005 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
3006 * @ep: The endpoint to set halt.
3007 * @value: Set or unset the halt.
3008 */
3009static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
3010{
3011 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3012 struct dwc2_hsotg *hs = hs_ep->parent;
3013 unsigned long flags = 0;
3014 int ret = 0;
3015
3016 spin_lock_irqsave(&hs->lock, flags);
3017 ret = dwc2_hsotg_ep_sethalt(ep, value);
3018 spin_unlock_irqrestore(&hs->lock, flags);
3019
3020 return ret;
3021}
3022
3023static struct usb_ep_ops dwc2_hsotg_ep_ops = {
3024 .enable = dwc2_hsotg_ep_enable,
3025 .disable = dwc2_hsotg_ep_disable,
3026 .alloc_request = dwc2_hsotg_ep_alloc_request,
3027 .free_request = dwc2_hsotg_ep_free_request,
3028 .queue = dwc2_hsotg_ep_queue_lock,
3029 .dequeue = dwc2_hsotg_ep_dequeue,
3030 .set_halt = dwc2_hsotg_ep_sethalt_lock,
3031 /* note, don't believe we have any call for the fifo routines */
3032};
3033
3034/**
3035 * dwc2_hsotg_init - initalize the usb core
3036 * @hsotg: The driver state
3037 */
3038static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
3039{
3040 u32 trdtim;
3041 u32 usbcfg;
3042 /* unmask subset of endpoint interrupts */
3043
3044 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
3045 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
3046 hsotg->regs + DIEPMSK);
3047
3048 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
3049 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
3050 hsotg->regs + DOEPMSK);
3051
3052 dwc2_writel(0, hsotg->regs + DAINTMSK);
3053
3054 /* Be in disconnected state until gadget is registered */
3055 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3056
3057 /* setup fifos */
3058
3059 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3060 dwc2_readl(hsotg->regs + GRXFSIZ),
3061 dwc2_readl(hsotg->regs + GNPTXFSIZ));
3062
3063 dwc2_hsotg_init_fifo(hsotg);
3064
3065 /* keep other bits untouched (so e.g. forced modes are not lost) */
3066 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3067 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3068 GUSBCFG_HNPCAP);
3069
3070 /* set the PLL on, remove the HNP/SRP and set the PHY */
3071 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3072 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3073 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
3074 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
3075
3076 if (using_dma(hsotg))
3077 __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
3078}
3079
3080/**
3081 * dwc2_hsotg_udc_start - prepare the udc for work
3082 * @gadget: The usb gadget state
3083 * @driver: The usb gadget driver
3084 *
3085 * Perform initialization to prepare udc device and driver
3086 * to work.
3087 */
3088static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
3089 struct usb_gadget_driver *driver)
3090{
3091 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3092 unsigned long flags;
3093 int ret;
3094
3095 if (!hsotg) {
3096 pr_err("%s: called with no device\n", __func__);
3097 return -ENODEV;
3098 }
3099
3100 if (!driver) {
3101 dev_err(hsotg->dev, "%s: no driver\n", __func__);
3102 return -EINVAL;
3103 }
3104
3105 if (driver->max_speed < USB_SPEED_FULL)
3106 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
3107
3108 if (!driver->setup) {
3109 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
3110 return -EINVAL;
3111 }
3112
3113 WARN_ON(hsotg->driver);
3114
3115 driver->driver.bus = NULL;
3116 hsotg->driver = driver;
3117 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
3118 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3119
3120 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
3121 ret = dwc2_lowlevel_hw_enable(hsotg);
3122 if (ret)
3123 goto err;
3124 }
3125
3126 if (!IS_ERR_OR_NULL(hsotg->uphy))
3127 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
3128
3129 spin_lock_irqsave(&hsotg->lock, flags);
3130 dwc2_hsotg_init(hsotg);
3131 dwc2_hsotg_core_init_disconnected(hsotg, false);
3132 hsotg->enabled = 0;
3133 spin_unlock_irqrestore(&hsotg->lock, flags);
3134
3135 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
3136
3137 return 0;
3138
3139err:
3140 hsotg->driver = NULL;
3141 return ret;
3142}
3143
3144/**
3145 * dwc2_hsotg_udc_stop - stop the udc
3146 * @gadget: The usb gadget state
3147 * @driver: The usb gadget driver
3148 *
3149 * Stop udc hw block and stay tunned for future transmissions
3150 */
3151static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
3152{
3153 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3154 unsigned long flags = 0;
3155 int ep;
3156
3157 if (!hsotg)
3158 return -ENODEV;
3159
3160 /* all endpoints should be shutdown */
3161 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3162 if (hsotg->eps_in[ep])
3163 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3164 if (hsotg->eps_out[ep])
3165 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3166 }
3167
3168 spin_lock_irqsave(&hsotg->lock, flags);
3169
3170 hsotg->driver = NULL;
3171 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3172 hsotg->enabled = 0;
3173
3174 spin_unlock_irqrestore(&hsotg->lock, flags);
3175
3176 if (!IS_ERR_OR_NULL(hsotg->uphy))
3177 otg_set_peripheral(hsotg->uphy->otg, NULL);
3178
3179 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3180 dwc2_lowlevel_hw_disable(hsotg);
3181
3182 return 0;
3183}
3184
3185/**
3186 * dwc2_hsotg_gadget_getframe - read the frame number
3187 * @gadget: The usb gadget state
3188 *
3189 * Read the {micro} frame number
3190 */
3191static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
3192{
3193 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
3194}
3195
3196/**
3197 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
3198 * @gadget: The usb gadget state
3199 * @is_on: Current state of the USB PHY
3200 *
3201 * Connect/Disconnect the USB PHY pullup
3202 */
3203static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
3204{
3205 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3206 unsigned long flags = 0;
3207
3208 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
3209 hsotg->op_state);
3210
3211 /* Don't modify pullup state while in host mode */
3212 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
3213 hsotg->enabled = is_on;
3214 return 0;
3215 }
3216
3217 spin_lock_irqsave(&hsotg->lock, flags);
3218 if (is_on) {
3219 hsotg->enabled = 1;
3220 dwc2_hsotg_core_init_disconnected(hsotg, false);
3221 dwc2_hsotg_core_connect(hsotg);
3222 } else {
3223 dwc2_hsotg_core_disconnect(hsotg);
3224 dwc2_hsotg_disconnect(hsotg);
3225 hsotg->enabled = 0;
3226 }
3227
3228 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3229 spin_unlock_irqrestore(&hsotg->lock, flags);
3230
3231 return 0;
3232}
3233
3234static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
3235{
3236 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3237 unsigned long flags;
3238
3239 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
3240 spin_lock_irqsave(&hsotg->lock, flags);
3241
3242 /*
3243 * If controller is hibernated, it must exit from hibernation
3244 * before being initialized / de-initialized
3245 */
3246 if (hsotg->lx_state == DWC2_L2)
3247 dwc2_exit_hibernation(hsotg, false);
3248
3249 if (is_active) {
3250 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3251
3252 dwc2_hsotg_core_init_disconnected(hsotg, false);
3253 if (hsotg->enabled)
3254 dwc2_hsotg_core_connect(hsotg);
3255 } else {
3256 dwc2_hsotg_core_disconnect(hsotg);
3257 dwc2_hsotg_disconnect(hsotg);
3258 }
3259
3260 spin_unlock_irqrestore(&hsotg->lock, flags);
3261 return 0;
3262}
3263
3264/**
3265 * dwc2_hsotg_vbus_draw - report bMaxPower field
3266 * @gadget: The usb gadget state
3267 * @mA: Amount of current
3268 *
3269 * Report how much power the device may consume to the phy.
3270 */
3271static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA)
3272{
3273 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3274
3275 if (IS_ERR_OR_NULL(hsotg->uphy))
3276 return -ENOTSUPP;
3277 return usb_phy_set_power(hsotg->uphy, mA);
3278}
3279
3280static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
3281 .get_frame = dwc2_hsotg_gadget_getframe,
3282 .udc_start = dwc2_hsotg_udc_start,
3283 .udc_stop = dwc2_hsotg_udc_stop,
3284 .pullup = dwc2_hsotg_pullup,
3285 .vbus_session = dwc2_hsotg_vbus_session,
3286 .vbus_draw = dwc2_hsotg_vbus_draw,
3287};
3288
3289/**
3290 * dwc2_hsotg_initep - initialise a single endpoint
3291 * @hsotg: The device state.
3292 * @hs_ep: The endpoint to be initialised.
3293 * @epnum: The endpoint number
3294 *
3295 * Initialise the given endpoint (as part of the probe and device state
3296 * creation) to give to the gadget driver. Setup the endpoint name, any
3297 * direction information and other state that may be required.
3298 */
3299static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
3300 struct dwc2_hsotg_ep *hs_ep,
3301 int epnum,
3302 bool dir_in)
3303{
3304 char *dir;
3305
3306 if (epnum == 0)
3307 dir = "";
3308 else if (dir_in)
3309 dir = "in";
3310 else
3311 dir = "out";
3312
3313 hs_ep->dir_in = dir_in;
3314 hs_ep->index = epnum;
3315
3316 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3317
3318 INIT_LIST_HEAD(&hs_ep->queue);
3319 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3320
3321 /* add to the list of endpoints known by the gadget driver */
3322 if (epnum)
3323 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3324
3325 hs_ep->parent = hsotg;
3326 hs_ep->ep.name = hs_ep->name;
3327 usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT);
3328 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
3329
3330 if (epnum == 0) {
3331 hs_ep->ep.caps.type_control = true;
3332 } else {
3333 hs_ep->ep.caps.type_iso = true;
3334 hs_ep->ep.caps.type_bulk = true;
3335 hs_ep->ep.caps.type_int = true;
3336 }
3337
3338 if (dir_in)
3339 hs_ep->ep.caps.dir_in = true;
3340 else
3341 hs_ep->ep.caps.dir_out = true;
3342
3343 /*
3344 * if we're using dma, we need to set the next-endpoint pointer
3345 * to be something valid.
3346 */
3347
3348 if (using_dma(hsotg)) {
3349 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
3350 if (dir_in)
3351 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
3352 else
3353 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
3354 }
3355}
3356
3357/**
3358 * dwc2_hsotg_hw_cfg - read HW configuration registers
3359 * @param: The device state
3360 *
3361 * Read the USB core HW configuration registers
3362 */
3363static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
3364{
3365 u32 cfg;
3366 u32 ep_type;
3367 u32 i;
3368
3369 /* check hardware configuration */
3370
3371 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
3372
3373 /* Add ep0 */
3374 hsotg->num_of_eps++;
3375
3376 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct dwc2_hsotg_ep),
3377 GFP_KERNEL);
3378 if (!hsotg->eps_in[0])
3379 return -ENOMEM;
3380 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
3381 hsotg->eps_out[0] = hsotg->eps_in[0];
3382
3383 cfg = hsotg->hw_params.dev_ep_dirs;
3384 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
3385 ep_type = cfg & 3;
3386 /* Direction in or both */
3387 if (!(ep_type & 2)) {
3388 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
3389 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
3390 if (!hsotg->eps_in[i])
3391 return -ENOMEM;
3392 }
3393 /* Direction out or both */
3394 if (!(ep_type & 1)) {
3395 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
3396 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
3397 if (!hsotg->eps_out[i])
3398 return -ENOMEM;
3399 }
3400 }
3401
3402 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
3403 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
3404
3405 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3406 hsotg->num_of_eps,
3407 hsotg->dedicated_fifos ? "dedicated" : "shared",
3408 hsotg->fifo_mem);
3409 return 0;
3410}
3411
3412/**
3413 * dwc2_hsotg_dump - dump state of the udc
3414 * @param: The device state
3415 */
3416static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
3417{
3418#ifdef DEBUG
3419 struct device *dev = hsotg->dev;
3420 void __iomem *regs = hsotg->regs;
3421 u32 val;
3422 int idx;
3423
3424 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3425 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
3426 dwc2_readl(regs + DIEPMSK));
3427
3428 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
3429 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
3430
3431 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3432 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
3433
3434 /* show periodic fifo settings */
3435
3436 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3437 val = dwc2_readl(regs + DPTXFSIZN(idx));
3438 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3439 val >> FIFOSIZE_DEPTH_SHIFT,
3440 val & FIFOSIZE_STARTADDR_MASK);
3441 }
3442
3443 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
3444 dev_info(dev,
3445 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3446 dwc2_readl(regs + DIEPCTL(idx)),
3447 dwc2_readl(regs + DIEPTSIZ(idx)),
3448 dwc2_readl(regs + DIEPDMA(idx)));
3449
3450 val = dwc2_readl(regs + DOEPCTL(idx));
3451 dev_info(dev,
3452 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3453 idx, dwc2_readl(regs + DOEPCTL(idx)),
3454 dwc2_readl(regs + DOEPTSIZ(idx)),
3455 dwc2_readl(regs + DOEPDMA(idx)));
3456
3457 }
3458
3459 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3460 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
3461#endif
3462}
3463
3464#ifdef CONFIG_OF
3465static void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg)
3466{
3467 struct device_node *np = hsotg->dev->of_node;
3468 u32 len = 0;
3469 u32 i = 0;
3470
3471 /* Enable dma if requested in device tree */
3472 hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma");
3473
3474 /*
3475 * Register TX periodic fifo size per endpoint.
3476 * EP0 is excluded since it has no fifo configuration.
3477 */
3478 if (!of_find_property(np, "g-tx-fifo-size", &len))
3479 goto rx_fifo;
3480
3481 len /= sizeof(u32);
3482
3483 /* Read tx fifo sizes other than ep0 */
3484 if (of_property_read_u32_array(np, "g-tx-fifo-size",
3485 &hsotg->g_tx_fifo_sz[1], len))
3486 goto rx_fifo;
3487
3488 /* Add ep0 */
3489 len++;
3490
3491 /* Make remaining TX fifos unavailable */
3492 if (len < MAX_EPS_CHANNELS) {
3493 for (i = len; i < MAX_EPS_CHANNELS; i++)
3494 hsotg->g_tx_fifo_sz[i] = 0;
3495 }
3496
3497rx_fifo:
3498 /* Register RX fifo size */
3499 of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz);
3500
3501 /* Register NPTX fifo size */
3502 of_property_read_u32(np, "g-np-tx-fifo-size",
3503 &hsotg->g_np_g_tx_fifo_sz);
3504}
3505#else
3506static inline void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) { }
3507#endif
3508
3509/**
3510 * dwc2_gadget_init - init function for gadget
3511 * @dwc2: The data structure for the DWC2 driver.
3512 * @irq: The IRQ number for the controller.
3513 */
3514int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
3515{
3516 struct device *dev = hsotg->dev;
3517 int epnum;
3518 int ret;
3519 int i;
3520 u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE;
3521
3522 /* Initialize to legacy fifo configuration values */
3523 hsotg->g_rx_fifo_sz = 2048;
3524 hsotg->g_np_g_tx_fifo_sz = 1024;
3525 memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo));
3526 /* Device tree specific probe */
3527 dwc2_hsotg_of_probe(hsotg);
3528
3529 /* Check against largest possible value. */
3530 if (hsotg->g_np_g_tx_fifo_sz >
3531 hsotg->hw_params.dev_nperio_tx_fifo_size) {
3532 dev_warn(dev, "Specified GNPTXFDEP=%d > %d\n",
3533 hsotg->g_np_g_tx_fifo_sz,
3534 hsotg->hw_params.dev_nperio_tx_fifo_size);
3535 hsotg->g_np_g_tx_fifo_sz =
3536 hsotg->hw_params.dev_nperio_tx_fifo_size;
3537 }
3538
3539 /* Dump fifo information */
3540 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
3541 hsotg->g_np_g_tx_fifo_sz);
3542 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz);
3543 for (i = 0; i < MAX_EPS_CHANNELS; i++)
3544 dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i,
3545 hsotg->g_tx_fifo_sz[i]);
3546
3547 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3548 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
3549 hsotg->gadget.name = dev_name(dev);
3550 if (hsotg->dr_mode == USB_DR_MODE_OTG)
3551 hsotg->gadget.is_otg = 1;
3552 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3553 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3554
3555 ret = dwc2_hsotg_hw_cfg(hsotg);
3556 if (ret) {
3557 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
3558 return ret;
3559 }
3560
3561 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
3562 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3563 if (!hsotg->ctrl_buff) {
3564 dev_err(dev, "failed to allocate ctrl request buff\n");
3565 return -ENOMEM;
3566 }
3567
3568 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
3569 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3570 if (!hsotg->ep0_buff) {
3571 dev_err(dev, "failed to allocate ctrl reply buff\n");
3572 return -ENOMEM;
3573 }
3574
3575 ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED,
3576 dev_name(hsotg->dev), hsotg);
3577 if (ret < 0) {
3578 dev_err(dev, "cannot claim IRQ for gadget\n");
3579 return ret;
3580 }
3581
3582 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3583
3584 if (hsotg->num_of_eps == 0) {
3585 dev_err(dev, "wrong number of EPs (zero)\n");
3586 return -EINVAL;
3587 }
3588
3589 /* setup endpoint information */
3590
3591 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3592 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
3593
3594 /* allocate EP0 request */
3595
3596 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
3597 GFP_KERNEL);
3598 if (!hsotg->ctrl_req) {
3599 dev_err(dev, "failed to allocate ctrl req\n");
3600 return -ENOMEM;
3601 }
3602
3603 /* initialise the endpoints now the core has been initialised */
3604 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
3605 if (hsotg->eps_in[epnum])
3606 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
3607 epnum, 1);
3608 if (hsotg->eps_out[epnum])
3609 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
3610 epnum, 0);
3611 }
3612
3613 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
3614 if (ret)
3615 return ret;
3616
3617 dwc2_hsotg_dump(hsotg);
3618
3619 return 0;
3620}
3621
3622/**
3623 * dwc2_hsotg_remove - remove function for hsotg driver
3624 * @pdev: The platform information for the driver
3625 */
3626int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
3627{
3628 usb_del_gadget_udc(&hsotg->gadget);
3629
3630 return 0;
3631}
3632
3633int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
3634{
3635 unsigned long flags;
3636
3637 if (hsotg->lx_state != DWC2_L0)
3638 return 0;
3639
3640 if (hsotg->driver) {
3641 int ep;
3642
3643 dev_info(hsotg->dev, "suspending usb gadget %s\n",
3644 hsotg->driver->driver.name);
3645
3646 spin_lock_irqsave(&hsotg->lock, flags);
3647 if (hsotg->enabled)
3648 dwc2_hsotg_core_disconnect(hsotg);
3649 dwc2_hsotg_disconnect(hsotg);
3650 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3651 spin_unlock_irqrestore(&hsotg->lock, flags);
3652
3653 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3654 if (hsotg->eps_in[ep])
3655 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3656 if (hsotg->eps_out[ep])
3657 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3658 }
3659 }
3660
3661 return 0;
3662}
3663
3664int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
3665{
3666 unsigned long flags;
3667
3668 if (hsotg->lx_state == DWC2_L2)
3669 return 0;
3670
3671 if (hsotg->driver) {
3672 dev_info(hsotg->dev, "resuming usb gadget %s\n",
3673 hsotg->driver->driver.name);
3674
3675 spin_lock_irqsave(&hsotg->lock, flags);
3676 dwc2_hsotg_core_init_disconnected(hsotg, false);
3677 if (hsotg->enabled)
3678 dwc2_hsotg_core_connect(hsotg);
3679 spin_unlock_irqrestore(&hsotg->lock, flags);
3680 }
3681
3682 return 0;
3683}
3684
3685/**
3686 * dwc2_backup_device_registers() - Backup controller device registers.
3687 * When suspending usb bus, registers needs to be backuped
3688 * if controller power is disabled once suspended.
3689 *
3690 * @hsotg: Programming view of the DWC_otg controller
3691 */
3692int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
3693{
3694 struct dwc2_dregs_backup *dr;
3695 int i;
3696
3697 dev_dbg(hsotg->dev, "%s\n", __func__);
3698
3699 /* Backup dev regs */
3700 dr = &hsotg->dr_backup;
3701
3702 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
3703 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
3704 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3705 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
3706 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
3707
3708 for (i = 0; i < hsotg->num_of_eps; i++) {
3709 /* Backup IN EPs */
3710 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
3711
3712 /* Ensure DATA PID is correctly configured */
3713 if (dr->diepctl[i] & DXEPCTL_DPID)
3714 dr->diepctl[i] |= DXEPCTL_SETD1PID;
3715 else
3716 dr->diepctl[i] |= DXEPCTL_SETD0PID;
3717
3718 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
3719 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
3720
3721 /* Backup OUT EPs */
3722 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
3723
3724 /* Ensure DATA PID is correctly configured */
3725 if (dr->doepctl[i] & DXEPCTL_DPID)
3726 dr->doepctl[i] |= DXEPCTL_SETD1PID;
3727 else
3728 dr->doepctl[i] |= DXEPCTL_SETD0PID;
3729
3730 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
3731 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
3732 }
3733 dr->valid = true;
3734 return 0;
3735}
3736
3737/**
3738 * dwc2_restore_device_registers() - Restore controller device registers.
3739 * When resuming usb bus, device registers needs to be restored
3740 * if controller power were disabled.
3741 *
3742 * @hsotg: Programming view of the DWC_otg controller
3743 */
3744int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
3745{
3746 struct dwc2_dregs_backup *dr;
3747 u32 dctl;
3748 int i;
3749
3750 dev_dbg(hsotg->dev, "%s\n", __func__);
3751
3752 /* Restore dev regs */
3753 dr = &hsotg->dr_backup;
3754 if (!dr->valid) {
3755 dev_err(hsotg->dev, "%s: no device registers to restore\n",
3756 __func__);
3757 return -EINVAL;
3758 }
3759 dr->valid = false;
3760
3761 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
3762 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
3763 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
3764 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
3765 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
3766
3767 for (i = 0; i < hsotg->num_of_eps; i++) {
3768 /* Restore IN EPs */
3769 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
3770 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
3771 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
3772
3773 /* Restore OUT EPs */
3774 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
3775 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
3776 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
3777 }
3778
3779 /* Set the Power-On Programming done bit */
3780 dctl = dwc2_readl(hsotg->regs + DCTL);
3781 dctl |= DCTL_PWRONPRGDONE;
3782 dwc2_writel(dctl, hsotg->regs + DCTL);
3783
3784 return 0;
3785}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * S3C USB2.0 High-speed / OtG driver
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/spinlock.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
20#include <linux/mutex.h>
21#include <linux/seq_file.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25#include <linux/of_platform.h>
26
27#include <linux/usb/ch9.h>
28#include <linux/usb/gadget.h>
29#include <linux/usb/phy.h>
30#include <linux/usb/composite.h>
31
32
33#include "core.h"
34#include "hw.h"
35
36/* conversion functions */
37static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
38{
39 return container_of(req, struct dwc2_hsotg_req, req);
40}
41
42static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
43{
44 return container_of(ep, struct dwc2_hsotg_ep, ep);
45}
46
47static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
48{
49 return container_of(gadget, struct dwc2_hsotg, gadget);
50}
51
52static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
53{
54 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
55}
56
57static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
58{
59 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
60}
61
62static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
63 u32 ep_index, u32 dir_in)
64{
65 if (dir_in)
66 return hsotg->eps_in[ep_index];
67 else
68 return hsotg->eps_out[ep_index];
69}
70
71/* forward declaration of functions */
72static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
73
74/**
75 * using_dma - return the DMA status of the driver.
76 * @hsotg: The driver state.
77 *
78 * Return true if we're using DMA.
79 *
80 * Currently, we have the DMA support code worked into everywhere
81 * that needs it, but the AMBA DMA implementation in the hardware can
82 * only DMA from 32bit aligned addresses. This means that gadgets such
83 * as the CDC Ethernet cannot work as they often pass packets which are
84 * not 32bit aligned.
85 *
86 * Unfortunately the choice to use DMA or not is global to the controller
87 * and seems to be only settable when the controller is being put through
88 * a core reset. This means we either need to fix the gadgets to take
89 * account of DMA alignment, or add bounce buffers (yuerk).
90 *
91 * g_using_dma is set depending on dts flag.
92 */
93static inline bool using_dma(struct dwc2_hsotg *hsotg)
94{
95 return hsotg->params.g_dma;
96}
97
98/*
99 * using_desc_dma - return the descriptor DMA status of the driver.
100 * @hsotg: The driver state.
101 *
102 * Return true if we're using descriptor DMA.
103 */
104static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
105{
106 return hsotg->params.g_dma_desc;
107}
108
109/**
110 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
111 * @hs_ep: The endpoint
112 *
113 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
114 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
115 */
116static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
117{
118 struct dwc2_hsotg *hsotg = hs_ep->parent;
119 u16 limit = DSTS_SOFFN_LIMIT;
120
121 if (hsotg->gadget.speed != USB_SPEED_HIGH)
122 limit >>= 3;
123
124 hs_ep->target_frame += hs_ep->interval;
125 if (hs_ep->target_frame > limit) {
126 hs_ep->frame_overrun = true;
127 hs_ep->target_frame &= limit;
128 } else {
129 hs_ep->frame_overrun = false;
130 }
131}
132
133/**
134 * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
135 * by one.
136 * @hs_ep: The endpoint.
137 *
138 * This function used in service interval based scheduling flow to calculate
139 * descriptor frame number filed value. For service interval mode frame
140 * number in descriptor should point to last (u)frame in the interval.
141 *
142 */
143static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
144{
145 struct dwc2_hsotg *hsotg = hs_ep->parent;
146 u16 limit = DSTS_SOFFN_LIMIT;
147
148 if (hsotg->gadget.speed != USB_SPEED_HIGH)
149 limit >>= 3;
150
151 if (hs_ep->target_frame)
152 hs_ep->target_frame -= 1;
153 else
154 hs_ep->target_frame = limit;
155}
156
157/**
158 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
159 * @hsotg: The device state
160 * @ints: A bitmask of the interrupts to enable
161 */
162static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
163{
164 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
165 u32 new_gsintmsk;
166
167 new_gsintmsk = gsintmsk | ints;
168
169 if (new_gsintmsk != gsintmsk) {
170 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
171 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
172 }
173}
174
175/**
176 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
177 * @hsotg: The device state
178 * @ints: A bitmask of the interrupts to enable
179 */
180static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
181{
182 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
183 u32 new_gsintmsk;
184
185 new_gsintmsk = gsintmsk & ~ints;
186
187 if (new_gsintmsk != gsintmsk)
188 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
189}
190
191/**
192 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
193 * @hsotg: The device state
194 * @ep: The endpoint index
195 * @dir_in: True if direction is in.
196 * @en: The enable value, true to enable
197 *
198 * Set or clear the mask for an individual endpoint's interrupt
199 * request.
200 */
201static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
202 unsigned int ep, unsigned int dir_in,
203 unsigned int en)
204{
205 unsigned long flags;
206 u32 bit = 1 << ep;
207 u32 daint;
208
209 if (!dir_in)
210 bit <<= 16;
211
212 local_irq_save(flags);
213 daint = dwc2_readl(hsotg, DAINTMSK);
214 if (en)
215 daint |= bit;
216 else
217 daint &= ~bit;
218 dwc2_writel(hsotg, daint, DAINTMSK);
219 local_irq_restore(flags);
220}
221
222/**
223 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
224 *
225 * @hsotg: Programming view of the DWC_otg controller
226 */
227int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
228{
229 if (hsotg->hw_params.en_multiple_tx_fifo)
230 /* In dedicated FIFO mode we need count of IN EPs */
231 return hsotg->hw_params.num_dev_in_eps;
232 else
233 /* In shared FIFO mode we need count of Periodic IN EPs */
234 return hsotg->hw_params.num_dev_perio_in_ep;
235}
236
237/**
238 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
239 * device mode TX FIFOs
240 *
241 * @hsotg: Programming view of the DWC_otg controller
242 */
243int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
244{
245 int addr;
246 int tx_addr_max;
247 u32 np_tx_fifo_size;
248
249 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
250 hsotg->params.g_np_tx_fifo_size);
251
252 /* Get Endpoint Info Control block size in DWORDs. */
253 tx_addr_max = hsotg->hw_params.total_fifo_size;
254
255 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
256 if (tx_addr_max <= addr)
257 return 0;
258
259 return tx_addr_max - addr;
260}
261
262/**
263 * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
264 *
265 * @hsotg: Programming view of the DWC_otg controller
266 *
267 */
268static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
269{
270 u32 gintsts2;
271 u32 gintmsk2;
272
273 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
274 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
275 gintsts2 &= gintmsk2;
276
277 if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
278 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
279 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
280 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
281 }
282}
283
284/**
285 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
286 * TX FIFOs
287 *
288 * @hsotg: Programming view of the DWC_otg controller
289 */
290int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
291{
292 int tx_fifo_count;
293 int tx_fifo_depth;
294
295 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
296
297 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
298
299 if (!tx_fifo_count)
300 return tx_fifo_depth;
301 else
302 return tx_fifo_depth / tx_fifo_count;
303}
304
305/**
306 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
307 * @hsotg: The device instance.
308 */
309static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
310{
311 unsigned int ep;
312 unsigned int addr;
313 int timeout;
314
315 u32 val;
316 u32 *txfsz = hsotg->params.g_tx_fifo_size;
317
318 /* Reset fifo map if not correctly cleared during previous session */
319 WARN_ON(hsotg->fifo_map);
320 hsotg->fifo_map = 0;
321
322 /* set RX/NPTX FIFO sizes */
323 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
324 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
325 FIFOSIZE_STARTADDR_SHIFT) |
326 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
327 GNPTXFSIZ);
328
329 /*
330 * arange all the rest of the TX FIFOs, as some versions of this
331 * block have overlapping default addresses. This also ensures
332 * that if the settings have been changed, then they are set to
333 * known values.
334 */
335
336 /* start at the end of the GNPTXFSIZ, rounded up */
337 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
338
339 /*
340 * Configure fifos sizes from provided configuration and assign
341 * them to endpoints dynamically according to maxpacket size value of
342 * given endpoint.
343 */
344 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
345 if (!txfsz[ep])
346 continue;
347 val = addr;
348 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
349 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
350 "insufficient fifo memory");
351 addr += txfsz[ep];
352
353 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
354 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
355 }
356
357 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
358 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
359 GDFIFOCFG);
360 /*
361 * according to p428 of the design guide, we need to ensure that
362 * all fifos are flushed before continuing
363 */
364
365 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
366 GRSTCTL_RXFFLSH, GRSTCTL);
367
368 /* wait until the fifos are both flushed */
369 timeout = 100;
370 while (1) {
371 val = dwc2_readl(hsotg, GRSTCTL);
372
373 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
374 break;
375
376 if (--timeout == 0) {
377 dev_err(hsotg->dev,
378 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
379 __func__, val);
380 break;
381 }
382
383 udelay(1);
384 }
385
386 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
387}
388
389/**
390 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
391 * @ep: USB endpoint to allocate request for.
392 * @flags: Allocation flags
393 *
394 * Allocate a new USB request structure appropriate for the specified endpoint
395 */
396static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
397 gfp_t flags)
398{
399 struct dwc2_hsotg_req *req;
400
401 req = kzalloc(sizeof(*req), flags);
402 if (!req)
403 return NULL;
404
405 INIT_LIST_HEAD(&req->queue);
406
407 return &req->req;
408}
409
410/**
411 * is_ep_periodic - return true if the endpoint is in periodic mode.
412 * @hs_ep: The endpoint to query.
413 *
414 * Returns true if the endpoint is in periodic mode, meaning it is being
415 * used for an Interrupt or ISO transfer.
416 */
417static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
418{
419 return hs_ep->periodic;
420}
421
422/**
423 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
424 * @hsotg: The device state.
425 * @hs_ep: The endpoint for the request
426 * @hs_req: The request being processed.
427 *
428 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
429 * of a request to ensure the buffer is ready for access by the caller.
430 */
431static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
432 struct dwc2_hsotg_ep *hs_ep,
433 struct dwc2_hsotg_req *hs_req)
434{
435 struct usb_request *req = &hs_req->req;
436
437 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir);
438}
439
440/*
441 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
442 * for Control endpoint
443 * @hsotg: The device state.
444 *
445 * This function will allocate 4 descriptor chains for EP 0: 2 for
446 * Setup stage, per one for IN and OUT data/status transactions.
447 */
448static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
449{
450 hsotg->setup_desc[0] =
451 dmam_alloc_coherent(hsotg->dev,
452 sizeof(struct dwc2_dma_desc),
453 &hsotg->setup_desc_dma[0],
454 GFP_KERNEL);
455 if (!hsotg->setup_desc[0])
456 goto fail;
457
458 hsotg->setup_desc[1] =
459 dmam_alloc_coherent(hsotg->dev,
460 sizeof(struct dwc2_dma_desc),
461 &hsotg->setup_desc_dma[1],
462 GFP_KERNEL);
463 if (!hsotg->setup_desc[1])
464 goto fail;
465
466 hsotg->ctrl_in_desc =
467 dmam_alloc_coherent(hsotg->dev,
468 sizeof(struct dwc2_dma_desc),
469 &hsotg->ctrl_in_desc_dma,
470 GFP_KERNEL);
471 if (!hsotg->ctrl_in_desc)
472 goto fail;
473
474 hsotg->ctrl_out_desc =
475 dmam_alloc_coherent(hsotg->dev,
476 sizeof(struct dwc2_dma_desc),
477 &hsotg->ctrl_out_desc_dma,
478 GFP_KERNEL);
479 if (!hsotg->ctrl_out_desc)
480 goto fail;
481
482 return 0;
483
484fail:
485 return -ENOMEM;
486}
487
488/**
489 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
490 * @hsotg: The controller state.
491 * @hs_ep: The endpoint we're going to write for.
492 * @hs_req: The request to write data for.
493 *
494 * This is called when the TxFIFO has some space in it to hold a new
495 * transmission and we have something to give it. The actual setup of
496 * the data size is done elsewhere, so all we have to do is to actually
497 * write the data.
498 *
499 * The return value is zero if there is more space (or nothing was done)
500 * otherwise -ENOSPC is returned if the FIFO space was used up.
501 *
502 * This routine is only needed for PIO
503 */
504static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
505 struct dwc2_hsotg_ep *hs_ep,
506 struct dwc2_hsotg_req *hs_req)
507{
508 bool periodic = is_ep_periodic(hs_ep);
509 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
510 int buf_pos = hs_req->req.actual;
511 int to_write = hs_ep->size_loaded;
512 void *data;
513 int can_write;
514 int pkt_round;
515 int max_transfer;
516
517 to_write -= (buf_pos - hs_ep->last_load);
518
519 /* if there's nothing to write, get out early */
520 if (to_write == 0)
521 return 0;
522
523 if (periodic && !hsotg->dedicated_fifos) {
524 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
525 int size_left;
526 int size_done;
527
528 /*
529 * work out how much data was loaded so we can calculate
530 * how much data is left in the fifo.
531 */
532
533 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
534
535 /*
536 * if shared fifo, we cannot write anything until the
537 * previous data has been completely sent.
538 */
539 if (hs_ep->fifo_load != 0) {
540 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
541 return -ENOSPC;
542 }
543
544 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
545 __func__, size_left,
546 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
547
548 /* how much of the data has moved */
549 size_done = hs_ep->size_loaded - size_left;
550
551 /* how much data is left in the fifo */
552 can_write = hs_ep->fifo_load - size_done;
553 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
554 __func__, can_write);
555
556 can_write = hs_ep->fifo_size - can_write;
557 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
558 __func__, can_write);
559
560 if (can_write <= 0) {
561 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
562 return -ENOSPC;
563 }
564 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
565 can_write = dwc2_readl(hsotg,
566 DTXFSTS(hs_ep->fifo_index));
567
568 can_write &= 0xffff;
569 can_write *= 4;
570 } else {
571 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
572 dev_dbg(hsotg->dev,
573 "%s: no queue slots available (0x%08x)\n",
574 __func__, gnptxsts);
575
576 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
577 return -ENOSPC;
578 }
579
580 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
581 can_write *= 4; /* fifo size is in 32bit quantities. */
582 }
583
584 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
585
586 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
587 __func__, gnptxsts, can_write, to_write, max_transfer);
588
589 /*
590 * limit to 512 bytes of data, it seems at least on the non-periodic
591 * FIFO, requests of >512 cause the endpoint to get stuck with a
592 * fragment of the end of the transfer in it.
593 */
594 if (can_write > 512 && !periodic)
595 can_write = 512;
596
597 /*
598 * limit the write to one max-packet size worth of data, but allow
599 * the transfer to return that it did not run out of fifo space
600 * doing it.
601 */
602 if (to_write > max_transfer) {
603 to_write = max_transfer;
604
605 /* it's needed only when we do not use dedicated fifos */
606 if (!hsotg->dedicated_fifos)
607 dwc2_hsotg_en_gsint(hsotg,
608 periodic ? GINTSTS_PTXFEMP :
609 GINTSTS_NPTXFEMP);
610 }
611
612 /* see if we can write data */
613
614 if (to_write > can_write) {
615 to_write = can_write;
616 pkt_round = to_write % max_transfer;
617
618 /*
619 * Round the write down to an
620 * exact number of packets.
621 *
622 * Note, we do not currently check to see if we can ever
623 * write a full packet or not to the FIFO.
624 */
625
626 if (pkt_round)
627 to_write -= pkt_round;
628
629 /*
630 * enable correct FIFO interrupt to alert us when there
631 * is more room left.
632 */
633
634 /* it's needed only when we do not use dedicated fifos */
635 if (!hsotg->dedicated_fifos)
636 dwc2_hsotg_en_gsint(hsotg,
637 periodic ? GINTSTS_PTXFEMP :
638 GINTSTS_NPTXFEMP);
639 }
640
641 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
642 to_write, hs_req->req.length, can_write, buf_pos);
643
644 if (to_write <= 0)
645 return -ENOSPC;
646
647 hs_req->req.actual = buf_pos + to_write;
648 hs_ep->total_data += to_write;
649
650 if (periodic)
651 hs_ep->fifo_load += to_write;
652
653 to_write = DIV_ROUND_UP(to_write, 4);
654 data = hs_req->req.buf + buf_pos;
655
656 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
657
658 return (to_write >= can_write) ? -ENOSPC : 0;
659}
660
661/**
662 * get_ep_limit - get the maximum data legnth for this endpoint
663 * @hs_ep: The endpoint
664 *
665 * Return the maximum data that can be queued in one go on a given endpoint
666 * so that transfers that are too long can be split.
667 */
668static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
669{
670 int index = hs_ep->index;
671 unsigned int maxsize;
672 unsigned int maxpkt;
673
674 if (index != 0) {
675 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
676 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
677 } else {
678 maxsize = 64 + 64;
679 if (hs_ep->dir_in)
680 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
681 else
682 maxpkt = 2;
683 }
684
685 /* we made the constant loading easier above by using +1 */
686 maxpkt--;
687 maxsize--;
688
689 /*
690 * constrain by packet count if maxpkts*pktsize is greater
691 * than the length register size.
692 */
693
694 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
695 maxsize = maxpkt * hs_ep->ep.maxpacket;
696
697 return maxsize;
698}
699
700/**
701 * dwc2_hsotg_read_frameno - read current frame number
702 * @hsotg: The device instance
703 *
704 * Return the current frame number
705 */
706static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
707{
708 u32 dsts;
709
710 dsts = dwc2_readl(hsotg, DSTS);
711 dsts &= DSTS_SOFFN_MASK;
712 dsts >>= DSTS_SOFFN_SHIFT;
713
714 return dsts;
715}
716
717/**
718 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
719 * DMA descriptor chain prepared for specific endpoint
720 * @hs_ep: The endpoint
721 *
722 * Return the maximum data that can be queued in one go on a given endpoint
723 * depending on its descriptor chain capacity so that transfers that
724 * are too long can be split.
725 */
726static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
727{
728 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
729 int is_isoc = hs_ep->isochronous;
730 unsigned int maxsize;
731 u32 mps = hs_ep->ep.maxpacket;
732 int dir_in = hs_ep->dir_in;
733
734 if (is_isoc)
735 maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
736 DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
737 MAX_DMA_DESC_NUM_HS_ISOC;
738 else
739 maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
740
741 /* Interrupt OUT EP with mps not multiple of 4 */
742 if (hs_ep->index)
743 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
744 maxsize = mps * MAX_DMA_DESC_NUM_GENERIC;
745
746 return maxsize;
747}
748
749/*
750 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
751 * @hs_ep: The endpoint
752 * @mask: RX/TX bytes mask to be defined
753 *
754 * Returns maximum data payload for one descriptor after analyzing endpoint
755 * characteristics.
756 * DMA descriptor transfer bytes limit depends on EP type:
757 * Control out - MPS,
758 * Isochronous - descriptor rx/tx bytes bitfield limit,
759 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
760 * have concatenations from various descriptors within one packet.
761 * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds
762 * to a single descriptor.
763 *
764 * Selects corresponding mask for RX/TX bytes as well.
765 */
766static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
767{
768 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
769 u32 mps = hs_ep->ep.maxpacket;
770 int dir_in = hs_ep->dir_in;
771 u32 desc_size = 0;
772
773 if (!hs_ep->index && !dir_in) {
774 desc_size = mps;
775 *mask = DEV_DMA_NBYTES_MASK;
776 } else if (hs_ep->isochronous) {
777 if (dir_in) {
778 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
779 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
780 } else {
781 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
782 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
783 }
784 } else {
785 desc_size = DEV_DMA_NBYTES_LIMIT;
786 *mask = DEV_DMA_NBYTES_MASK;
787
788 /* Round down desc_size to be mps multiple */
789 desc_size -= desc_size % mps;
790 }
791
792 /* Interrupt OUT EP with mps not multiple of 4 */
793 if (hs_ep->index)
794 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) {
795 desc_size = mps;
796 *mask = DEV_DMA_NBYTES_MASK;
797 }
798
799 return desc_size;
800}
801
802static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
803 struct dwc2_dma_desc **desc,
804 dma_addr_t dma_buff,
805 unsigned int len,
806 bool true_last)
807{
808 int dir_in = hs_ep->dir_in;
809 u32 mps = hs_ep->ep.maxpacket;
810 u32 maxsize = 0;
811 u32 offset = 0;
812 u32 mask = 0;
813 int i;
814
815 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
816
817 hs_ep->desc_count = (len / maxsize) +
818 ((len % maxsize) ? 1 : 0);
819 if (len == 0)
820 hs_ep->desc_count = 1;
821
822 for (i = 0; i < hs_ep->desc_count; ++i) {
823 (*desc)->status = 0;
824 (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
825 << DEV_DMA_BUFF_STS_SHIFT);
826
827 if (len > maxsize) {
828 if (!hs_ep->index && !dir_in)
829 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
830
831 (*desc)->status |=
832 maxsize << DEV_DMA_NBYTES_SHIFT & mask;
833 (*desc)->buf = dma_buff + offset;
834
835 len -= maxsize;
836 offset += maxsize;
837 } else {
838 if (true_last)
839 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
840
841 if (dir_in)
842 (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
843 ((hs_ep->send_zlp && true_last) ?
844 DEV_DMA_SHORT : 0);
845
846 (*desc)->status |=
847 len << DEV_DMA_NBYTES_SHIFT & mask;
848 (*desc)->buf = dma_buff + offset;
849 }
850
851 (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
852 (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
853 << DEV_DMA_BUFF_STS_SHIFT);
854 (*desc)++;
855 }
856}
857
858/*
859 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
860 * @hs_ep: The endpoint
861 * @ureq: Request to transfer
862 * @offset: offset in bytes
863 * @len: Length of the transfer
864 *
865 * This function will iterate over descriptor chain and fill its entries
866 * with corresponding information based on transfer data.
867 */
868static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
869 dma_addr_t dma_buff,
870 unsigned int len)
871{
872 struct usb_request *ureq = NULL;
873 struct dwc2_dma_desc *desc = hs_ep->desc_list;
874 struct scatterlist *sg;
875 int i;
876 u8 desc_count = 0;
877
878 if (hs_ep->req)
879 ureq = &hs_ep->req->req;
880
881 /* non-DMA sg buffer */
882 if (!ureq || !ureq->num_sgs) {
883 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
884 dma_buff, len, true);
885 return;
886 }
887
888 /* DMA sg buffer */
889 for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
890 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
891 sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
892 sg_is_last(sg));
893 desc_count += hs_ep->desc_count;
894 }
895
896 hs_ep->desc_count = desc_count;
897}
898
899/*
900 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
901 * @hs_ep: The isochronous endpoint.
902 * @dma_buff: usb requests dma buffer.
903 * @len: usb request transfer length.
904 *
905 * Fills next free descriptor with the data of the arrived usb request,
906 * frame info, sets Last and IOC bits increments next_desc. If filled
907 * descriptor is not the first one, removes L bit from the previous descriptor
908 * status.
909 */
910static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
911 dma_addr_t dma_buff, unsigned int len)
912{
913 struct dwc2_dma_desc *desc;
914 struct dwc2_hsotg *hsotg = hs_ep->parent;
915 u32 index;
916 u32 mask = 0;
917 u8 pid = 0;
918
919 dwc2_gadget_get_desc_params(hs_ep, &mask);
920
921 index = hs_ep->next_desc;
922 desc = &hs_ep->desc_list[index];
923
924 /* Check if descriptor chain full */
925 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
926 DEV_DMA_BUFF_STS_HREADY) {
927 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
928 return 1;
929 }
930
931 /* Clear L bit of previous desc if more than one entries in the chain */
932 if (hs_ep->next_desc)
933 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
934
935 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
936 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
937
938 desc->status = 0;
939 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
940
941 desc->buf = dma_buff;
942 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
943 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
944
945 if (hs_ep->dir_in) {
946 if (len)
947 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
948 else
949 pid = 1;
950 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
951 DEV_DMA_ISOC_PID_MASK) |
952 ((len % hs_ep->ep.maxpacket) ?
953 DEV_DMA_SHORT : 0) |
954 ((hs_ep->target_frame <<
955 DEV_DMA_ISOC_FRNUM_SHIFT) &
956 DEV_DMA_ISOC_FRNUM_MASK);
957 }
958
959 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
960 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
961
962 /* Increment frame number by interval for IN */
963 if (hs_ep->dir_in)
964 dwc2_gadget_incr_frame_num(hs_ep);
965
966 /* Update index of last configured entry in the chain */
967 hs_ep->next_desc++;
968 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
969 hs_ep->next_desc = 0;
970
971 return 0;
972}
973
974/*
975 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
976 * @hs_ep: The isochronous endpoint.
977 *
978 * Prepare descriptor chain for isochronous endpoints. Afterwards
979 * write DMA address to HW and enable the endpoint.
980 */
981static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
982{
983 struct dwc2_hsotg *hsotg = hs_ep->parent;
984 struct dwc2_hsotg_req *hs_req, *treq;
985 int index = hs_ep->index;
986 int ret;
987 int i;
988 u32 dma_reg;
989 u32 depctl;
990 u32 ctrl;
991 struct dwc2_dma_desc *desc;
992
993 if (list_empty(&hs_ep->queue)) {
994 hs_ep->target_frame = TARGET_FRAME_INITIAL;
995 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
996 return;
997 }
998
999 /* Initialize descriptor chain by Host Busy status */
1000 for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
1001 desc = &hs_ep->desc_list[i];
1002 desc->status = 0;
1003 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
1004 << DEV_DMA_BUFF_STS_SHIFT);
1005 }
1006
1007 hs_ep->next_desc = 0;
1008 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
1009 dma_addr_t dma_addr = hs_req->req.dma;
1010
1011 if (hs_req->req.num_sgs) {
1012 WARN_ON(hs_req->req.num_sgs > 1);
1013 dma_addr = sg_dma_address(hs_req->req.sg);
1014 }
1015 ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1016 hs_req->req.length);
1017 if (ret)
1018 break;
1019 }
1020
1021 hs_ep->compl_desc = 0;
1022 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1023 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
1024
1025 /* write descriptor chain address to control register */
1026 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1027
1028 ctrl = dwc2_readl(hsotg, depctl);
1029 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
1030 dwc2_writel(hsotg, ctrl, depctl);
1031}
1032
1033static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep);
1034static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1035 struct dwc2_hsotg_ep *hs_ep,
1036 struct dwc2_hsotg_req *hs_req,
1037 int result);
1038
1039/**
1040 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
1041 * @hsotg: The controller state.
1042 * @hs_ep: The endpoint to process a request for
1043 * @hs_req: The request to start.
1044 * @continuing: True if we are doing more for the current request.
1045 *
1046 * Start the given request running by setting the endpoint registers
1047 * appropriately, and writing any data to the FIFOs.
1048 */
1049static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1050 struct dwc2_hsotg_ep *hs_ep,
1051 struct dwc2_hsotg_req *hs_req,
1052 bool continuing)
1053{
1054 struct usb_request *ureq = &hs_req->req;
1055 int index = hs_ep->index;
1056 int dir_in = hs_ep->dir_in;
1057 u32 epctrl_reg;
1058 u32 epsize_reg;
1059 u32 epsize;
1060 u32 ctrl;
1061 unsigned int length;
1062 unsigned int packets;
1063 unsigned int maxreq;
1064 unsigned int dma_reg;
1065
1066 if (index != 0) {
1067 if (hs_ep->req && !continuing) {
1068 dev_err(hsotg->dev, "%s: active request\n", __func__);
1069 WARN_ON(1);
1070 return;
1071 } else if (hs_ep->req != hs_req && continuing) {
1072 dev_err(hsotg->dev,
1073 "%s: continue different req\n", __func__);
1074 WARN_ON(1);
1075 return;
1076 }
1077 }
1078
1079 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1080 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1081 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1082
1083 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1084 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1085 hs_ep->dir_in ? "in" : "out");
1086
1087 /* If endpoint is stalled, we will restart request later */
1088 ctrl = dwc2_readl(hsotg, epctrl_reg);
1089
1090 if (index && ctrl & DXEPCTL_STALL) {
1091 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1092 return;
1093 }
1094
1095 length = ureq->length - ureq->actual;
1096 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1097 ureq->length, ureq->actual);
1098
1099 if (!using_desc_dma(hsotg))
1100 maxreq = get_ep_limit(hs_ep);
1101 else
1102 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1103
1104 if (length > maxreq) {
1105 int round = maxreq % hs_ep->ep.maxpacket;
1106
1107 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1108 __func__, length, maxreq, round);
1109
1110 /* round down to multiple of packets */
1111 if (round)
1112 maxreq -= round;
1113
1114 length = maxreq;
1115 }
1116
1117 if (length)
1118 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1119 else
1120 packets = 1; /* send one packet if length is zero. */
1121
1122 if (dir_in && index != 0)
1123 if (hs_ep->isochronous)
1124 epsize = DXEPTSIZ_MC(packets);
1125 else
1126 epsize = DXEPTSIZ_MC(1);
1127 else
1128 epsize = 0;
1129
1130 /*
1131 * zero length packet should be programmed on its own and should not
1132 * be counted in DIEPTSIZ.PktCnt with other packets.
1133 */
1134 if (dir_in && ureq->zero && !continuing) {
1135 /* Test if zlp is actually required. */
1136 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1137 !(ureq->length % hs_ep->ep.maxpacket))
1138 hs_ep->send_zlp = 1;
1139 }
1140
1141 epsize |= DXEPTSIZ_PKTCNT(packets);
1142 epsize |= DXEPTSIZ_XFERSIZE(length);
1143
1144 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1145 __func__, packets, length, ureq->length, epsize, epsize_reg);
1146
1147 /* store the request as the current one we're doing */
1148 hs_ep->req = hs_req;
1149
1150 if (using_desc_dma(hsotg)) {
1151 u32 offset = 0;
1152 u32 mps = hs_ep->ep.maxpacket;
1153
1154 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1155 if (!dir_in) {
1156 if (!index)
1157 length = mps;
1158 else if (length % mps)
1159 length += (mps - (length % mps));
1160 }
1161
1162 if (continuing)
1163 offset = ureq->actual;
1164
1165 /* Fill DDMA chain entries */
1166 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1167 length);
1168
1169 /* write descriptor chain address to control register */
1170 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1171
1172 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1173 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1174 } else {
1175 /* write size / packets */
1176 dwc2_writel(hsotg, epsize, epsize_reg);
1177
1178 if (using_dma(hsotg) && !continuing && (length != 0)) {
1179 /*
1180 * write DMA address to control register, buffer
1181 * already synced by dwc2_hsotg_ep_queue().
1182 */
1183
1184 dwc2_writel(hsotg, ureq->dma, dma_reg);
1185
1186 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1187 __func__, &ureq->dma, dma_reg);
1188 }
1189 }
1190
1191 if (hs_ep->isochronous) {
1192 if (!dwc2_gadget_target_frame_elapsed(hs_ep)) {
1193 if (hs_ep->interval == 1) {
1194 if (hs_ep->target_frame & 0x1)
1195 ctrl |= DXEPCTL_SETODDFR;
1196 else
1197 ctrl |= DXEPCTL_SETEVENFR;
1198 }
1199 ctrl |= DXEPCTL_CNAK;
1200 } else {
1201 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
1202 return;
1203 }
1204 }
1205
1206 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1207
1208 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1209
1210 /* For Setup request do not clear NAK */
1211 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1212 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1213
1214 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1215 dwc2_writel(hsotg, ctrl, epctrl_reg);
1216
1217 /*
1218 * set these, it seems that DMA support increments past the end
1219 * of the packet buffer so we need to calculate the length from
1220 * this information.
1221 */
1222 hs_ep->size_loaded = length;
1223 hs_ep->last_load = ureq->actual;
1224
1225 if (dir_in && !using_dma(hsotg)) {
1226 /* set these anyway, we may need them for non-periodic in */
1227 hs_ep->fifo_load = 0;
1228
1229 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1230 }
1231
1232 /*
1233 * Note, trying to clear the NAK here causes problems with transmit
1234 * on the S3C6400 ending up with the TXFIFO becoming full.
1235 */
1236
1237 /* check ep is enabled */
1238 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1239 dev_dbg(hsotg->dev,
1240 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1241 index, dwc2_readl(hsotg, epctrl_reg));
1242
1243 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1244 __func__, dwc2_readl(hsotg, epctrl_reg));
1245
1246 /* enable ep interrupts */
1247 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1248}
1249
1250/**
1251 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1252 * @hsotg: The device state.
1253 * @hs_ep: The endpoint the request is on.
1254 * @req: The request being processed.
1255 *
1256 * We've been asked to queue a request, so ensure that the memory buffer
1257 * is correctly setup for DMA. If we've been passed an extant DMA address
1258 * then ensure the buffer has been synced to memory. If our buffer has no
1259 * DMA memory, then we map the memory and mark our request to allow us to
1260 * cleanup on completion.
1261 */
1262static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1263 struct dwc2_hsotg_ep *hs_ep,
1264 struct usb_request *req)
1265{
1266 int ret;
1267
1268 hs_ep->map_dir = hs_ep->dir_in;
1269 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1270 if (ret)
1271 goto dma_error;
1272
1273 return 0;
1274
1275dma_error:
1276 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1277 __func__, req->buf, req->length);
1278
1279 return -EIO;
1280}
1281
1282static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1283 struct dwc2_hsotg_ep *hs_ep,
1284 struct dwc2_hsotg_req *hs_req)
1285{
1286 void *req_buf = hs_req->req.buf;
1287
1288 /* If dma is not being used or buffer is aligned */
1289 if (!using_dma(hsotg) || !((long)req_buf & 3))
1290 return 0;
1291
1292 WARN_ON(hs_req->saved_req_buf);
1293
1294 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1295 hs_ep->ep.name, req_buf, hs_req->req.length);
1296
1297 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1298 if (!hs_req->req.buf) {
1299 hs_req->req.buf = req_buf;
1300 dev_err(hsotg->dev,
1301 "%s: unable to allocate memory for bounce buffer\n",
1302 __func__);
1303 return -ENOMEM;
1304 }
1305
1306 /* Save actual buffer */
1307 hs_req->saved_req_buf = req_buf;
1308
1309 if (hs_ep->dir_in)
1310 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1311 return 0;
1312}
1313
1314static void
1315dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1316 struct dwc2_hsotg_ep *hs_ep,
1317 struct dwc2_hsotg_req *hs_req)
1318{
1319 /* If dma is not being used or buffer was aligned */
1320 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1321 return;
1322
1323 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1324 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1325
1326 /* Copy data from bounce buffer on successful out transfer */
1327 if (!hs_ep->dir_in && !hs_req->req.status)
1328 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1329 hs_req->req.actual);
1330
1331 /* Free bounce buffer */
1332 kfree(hs_req->req.buf);
1333
1334 hs_req->req.buf = hs_req->saved_req_buf;
1335 hs_req->saved_req_buf = NULL;
1336}
1337
1338/**
1339 * dwc2_gadget_target_frame_elapsed - Checks target frame
1340 * @hs_ep: The driver endpoint to check
1341 *
1342 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1343 * corresponding transfer.
1344 */
1345static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1346{
1347 struct dwc2_hsotg *hsotg = hs_ep->parent;
1348 u32 target_frame = hs_ep->target_frame;
1349 u32 current_frame = hsotg->frame_number;
1350 bool frame_overrun = hs_ep->frame_overrun;
1351 u16 limit = DSTS_SOFFN_LIMIT;
1352
1353 if (hsotg->gadget.speed != USB_SPEED_HIGH)
1354 limit >>= 3;
1355
1356 if (!frame_overrun && current_frame >= target_frame)
1357 return true;
1358
1359 if (frame_overrun && current_frame >= target_frame &&
1360 ((current_frame - target_frame) < limit / 2))
1361 return true;
1362
1363 return false;
1364}
1365
1366/*
1367 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1368 * @hsotg: The driver state
1369 * @hs_ep: the ep descriptor chain is for
1370 *
1371 * Called to update EP0 structure's pointers depend on stage of
1372 * control transfer.
1373 */
1374static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1375 struct dwc2_hsotg_ep *hs_ep)
1376{
1377 switch (hsotg->ep0_state) {
1378 case DWC2_EP0_SETUP:
1379 case DWC2_EP0_STATUS_OUT:
1380 hs_ep->desc_list = hsotg->setup_desc[0];
1381 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1382 break;
1383 case DWC2_EP0_DATA_IN:
1384 case DWC2_EP0_STATUS_IN:
1385 hs_ep->desc_list = hsotg->ctrl_in_desc;
1386 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1387 break;
1388 case DWC2_EP0_DATA_OUT:
1389 hs_ep->desc_list = hsotg->ctrl_out_desc;
1390 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1391 break;
1392 default:
1393 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1394 hsotg->ep0_state);
1395 return -EINVAL;
1396 }
1397
1398 return 0;
1399}
1400
1401static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1402 gfp_t gfp_flags)
1403{
1404 struct dwc2_hsotg_req *hs_req = our_req(req);
1405 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1406 struct dwc2_hsotg *hs = hs_ep->parent;
1407 bool first;
1408 int ret;
1409 u32 maxsize = 0;
1410 u32 mask = 0;
1411
1412
1413 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1414 ep->name, req, req->length, req->buf, req->no_interrupt,
1415 req->zero, req->short_not_ok);
1416
1417 /* Prevent new request submission when controller is suspended */
1418 if (hs->lx_state != DWC2_L0) {
1419 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1420 __func__);
1421 return -EAGAIN;
1422 }
1423
1424 /* initialise status of the request */
1425 INIT_LIST_HEAD(&hs_req->queue);
1426 req->actual = 0;
1427 req->status = -EINPROGRESS;
1428
1429 /* Don't queue ISOC request if length greater than mps*mc */
1430 if (hs_ep->isochronous &&
1431 req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1432 dev_err(hs->dev, "req length > maxpacket*mc\n");
1433 return -EINVAL;
1434 }
1435
1436 /* In DDMA mode for ISOC's don't queue request if length greater
1437 * than descriptor limits.
1438 */
1439 if (using_desc_dma(hs) && hs_ep->isochronous) {
1440 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1441 if (hs_ep->dir_in && req->length > maxsize) {
1442 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1443 req->length, maxsize);
1444 return -EINVAL;
1445 }
1446
1447 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1448 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1449 req->length, hs_ep->ep.maxpacket);
1450 return -EINVAL;
1451 }
1452 }
1453
1454 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1455 if (ret)
1456 return ret;
1457
1458 /* if we're using DMA, sync the buffers as necessary */
1459 if (using_dma(hs)) {
1460 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1461 if (ret)
1462 return ret;
1463 }
1464 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1465 if (using_desc_dma(hs) && !hs_ep->index) {
1466 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1467 if (ret)
1468 return ret;
1469 }
1470
1471 first = list_empty(&hs_ep->queue);
1472 list_add_tail(&hs_req->queue, &hs_ep->queue);
1473
1474 /*
1475 * Handle DDMA isochronous transfers separately - just add new entry
1476 * to the descriptor chain.
1477 * Transfer will be started once SW gets either one of NAK or
1478 * OutTknEpDis interrupts.
1479 */
1480 if (using_desc_dma(hs) && hs_ep->isochronous) {
1481 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1482 dma_addr_t dma_addr = hs_req->req.dma;
1483
1484 if (hs_req->req.num_sgs) {
1485 WARN_ON(hs_req->req.num_sgs > 1);
1486 dma_addr = sg_dma_address(hs_req->req.sg);
1487 }
1488 dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1489 hs_req->req.length);
1490 }
1491 return 0;
1492 }
1493
1494 /* Change EP direction if status phase request is after data out */
1495 if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1496 hs->ep0_state == DWC2_EP0_DATA_OUT)
1497 hs_ep->dir_in = 1;
1498
1499 if (first) {
1500 if (!hs_ep->isochronous) {
1501 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1502 return 0;
1503 }
1504
1505 /* Update current frame number value. */
1506 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1507 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1508 dwc2_gadget_incr_frame_num(hs_ep);
1509 /* Update current frame number value once more as it
1510 * changes here.
1511 */
1512 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1513 }
1514
1515 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1516 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1517 }
1518 return 0;
1519}
1520
1521static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1522 gfp_t gfp_flags)
1523{
1524 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1525 struct dwc2_hsotg *hs = hs_ep->parent;
1526 unsigned long flags;
1527 int ret;
1528
1529 spin_lock_irqsave(&hs->lock, flags);
1530 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1531 spin_unlock_irqrestore(&hs->lock, flags);
1532
1533 return ret;
1534}
1535
1536static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1537 struct usb_request *req)
1538{
1539 struct dwc2_hsotg_req *hs_req = our_req(req);
1540
1541 kfree(hs_req);
1542}
1543
1544/**
1545 * dwc2_hsotg_complete_oursetup - setup completion callback
1546 * @ep: The endpoint the request was on.
1547 * @req: The request completed.
1548 *
1549 * Called on completion of any requests the driver itself
1550 * submitted that need cleaning up.
1551 */
1552static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1553 struct usb_request *req)
1554{
1555 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1556 struct dwc2_hsotg *hsotg = hs_ep->parent;
1557
1558 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1559
1560 dwc2_hsotg_ep_free_request(ep, req);
1561}
1562
1563/**
1564 * ep_from_windex - convert control wIndex value to endpoint
1565 * @hsotg: The driver state.
1566 * @windex: The control request wIndex field (in host order).
1567 *
1568 * Convert the given wIndex into a pointer to an driver endpoint
1569 * structure, or return NULL if it is not a valid endpoint.
1570 */
1571static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1572 u32 windex)
1573{
1574 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1575 int idx = windex & 0x7F;
1576
1577 if (windex >= 0x100)
1578 return NULL;
1579
1580 if (idx > hsotg->num_of_eps)
1581 return NULL;
1582
1583 return index_to_ep(hsotg, idx, dir);
1584}
1585
1586/**
1587 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1588 * @hsotg: The driver state.
1589 * @testmode: requested usb test mode
1590 * Enable usb Test Mode requested by the Host.
1591 */
1592int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1593{
1594 int dctl = dwc2_readl(hsotg, DCTL);
1595
1596 dctl &= ~DCTL_TSTCTL_MASK;
1597 switch (testmode) {
1598 case USB_TEST_J:
1599 case USB_TEST_K:
1600 case USB_TEST_SE0_NAK:
1601 case USB_TEST_PACKET:
1602 case USB_TEST_FORCE_ENABLE:
1603 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1604 break;
1605 default:
1606 return -EINVAL;
1607 }
1608 dwc2_writel(hsotg, dctl, DCTL);
1609 return 0;
1610}
1611
1612/**
1613 * dwc2_hsotg_send_reply - send reply to control request
1614 * @hsotg: The device state
1615 * @ep: Endpoint 0
1616 * @buff: Buffer for request
1617 * @length: Length of reply.
1618 *
1619 * Create a request and queue it on the given endpoint. This is useful as
1620 * an internal method of sending replies to certain control requests, etc.
1621 */
1622static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1623 struct dwc2_hsotg_ep *ep,
1624 void *buff,
1625 int length)
1626{
1627 struct usb_request *req;
1628 int ret;
1629
1630 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1631
1632 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1633 hsotg->ep0_reply = req;
1634 if (!req) {
1635 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1636 return -ENOMEM;
1637 }
1638
1639 req->buf = hsotg->ep0_buff;
1640 req->length = length;
1641 /*
1642 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1643 * STATUS stage.
1644 */
1645 req->zero = 0;
1646 req->complete = dwc2_hsotg_complete_oursetup;
1647
1648 if (length)
1649 memcpy(req->buf, buff, length);
1650
1651 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1652 if (ret) {
1653 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1654 return ret;
1655 }
1656
1657 return 0;
1658}
1659
1660/**
1661 * dwc2_hsotg_process_req_status - process request GET_STATUS
1662 * @hsotg: The device state
1663 * @ctrl: USB control request
1664 */
1665static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1666 struct usb_ctrlrequest *ctrl)
1667{
1668 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1669 struct dwc2_hsotg_ep *ep;
1670 __le16 reply;
1671 u16 status;
1672 int ret;
1673
1674 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1675
1676 if (!ep0->dir_in) {
1677 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1678 return -EINVAL;
1679 }
1680
1681 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1682 case USB_RECIP_DEVICE:
1683 status = hsotg->gadget.is_selfpowered <<
1684 USB_DEVICE_SELF_POWERED;
1685 status |= hsotg->remote_wakeup_allowed <<
1686 USB_DEVICE_REMOTE_WAKEUP;
1687 reply = cpu_to_le16(status);
1688 break;
1689
1690 case USB_RECIP_INTERFACE:
1691 /* currently, the data result should be zero */
1692 reply = cpu_to_le16(0);
1693 break;
1694
1695 case USB_RECIP_ENDPOINT:
1696 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1697 if (!ep)
1698 return -ENOENT;
1699
1700 reply = cpu_to_le16(ep->halted ? 1 : 0);
1701 break;
1702
1703 default:
1704 return 0;
1705 }
1706
1707 if (le16_to_cpu(ctrl->wLength) != 2)
1708 return -EINVAL;
1709
1710 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1711 if (ret) {
1712 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1713 return ret;
1714 }
1715
1716 return 1;
1717}
1718
1719static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1720
1721/**
1722 * get_ep_head - return the first request on the endpoint
1723 * @hs_ep: The controller endpoint to get
1724 *
1725 * Get the first request on the endpoint.
1726 */
1727static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1728{
1729 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1730 queue);
1731}
1732
1733/**
1734 * dwc2_gadget_start_next_request - Starts next request from ep queue
1735 * @hs_ep: Endpoint structure
1736 *
1737 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1738 * in its handler. Hence we need to unmask it here to be able to do
1739 * resynchronization.
1740 */
1741static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1742{
1743 struct dwc2_hsotg *hsotg = hs_ep->parent;
1744 int dir_in = hs_ep->dir_in;
1745 struct dwc2_hsotg_req *hs_req;
1746
1747 if (!list_empty(&hs_ep->queue)) {
1748 hs_req = get_ep_head(hs_ep);
1749 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1750 return;
1751 }
1752 if (!hs_ep->isochronous)
1753 return;
1754
1755 if (dir_in) {
1756 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1757 __func__);
1758 } else {
1759 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1760 __func__);
1761 }
1762}
1763
1764/**
1765 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1766 * @hsotg: The device state
1767 * @ctrl: USB control request
1768 */
1769static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1770 struct usb_ctrlrequest *ctrl)
1771{
1772 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1773 struct dwc2_hsotg_req *hs_req;
1774 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1775 struct dwc2_hsotg_ep *ep;
1776 int ret;
1777 bool halted;
1778 u32 recip;
1779 u32 wValue;
1780 u32 wIndex;
1781
1782 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1783 __func__, set ? "SET" : "CLEAR");
1784
1785 wValue = le16_to_cpu(ctrl->wValue);
1786 wIndex = le16_to_cpu(ctrl->wIndex);
1787 recip = ctrl->bRequestType & USB_RECIP_MASK;
1788
1789 switch (recip) {
1790 case USB_RECIP_DEVICE:
1791 switch (wValue) {
1792 case USB_DEVICE_REMOTE_WAKEUP:
1793 if (set)
1794 hsotg->remote_wakeup_allowed = 1;
1795 else
1796 hsotg->remote_wakeup_allowed = 0;
1797 break;
1798
1799 case USB_DEVICE_TEST_MODE:
1800 if ((wIndex & 0xff) != 0)
1801 return -EINVAL;
1802 if (!set)
1803 return -EINVAL;
1804
1805 hsotg->test_mode = wIndex >> 8;
1806 break;
1807 default:
1808 return -ENOENT;
1809 }
1810
1811 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1812 if (ret) {
1813 dev_err(hsotg->dev,
1814 "%s: failed to send reply\n", __func__);
1815 return ret;
1816 }
1817 break;
1818
1819 case USB_RECIP_ENDPOINT:
1820 ep = ep_from_windex(hsotg, wIndex);
1821 if (!ep) {
1822 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1823 __func__, wIndex);
1824 return -ENOENT;
1825 }
1826
1827 switch (wValue) {
1828 case USB_ENDPOINT_HALT:
1829 halted = ep->halted;
1830
1831 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1832
1833 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1834 if (ret) {
1835 dev_err(hsotg->dev,
1836 "%s: failed to send reply\n", __func__);
1837 return ret;
1838 }
1839
1840 /*
1841 * we have to complete all requests for ep if it was
1842 * halted, and the halt was cleared by CLEAR_FEATURE
1843 */
1844
1845 if (!set && halted) {
1846 /*
1847 * If we have request in progress,
1848 * then complete it
1849 */
1850 if (ep->req) {
1851 hs_req = ep->req;
1852 ep->req = NULL;
1853 list_del_init(&hs_req->queue);
1854 if (hs_req->req.complete) {
1855 spin_unlock(&hsotg->lock);
1856 usb_gadget_giveback_request(
1857 &ep->ep, &hs_req->req);
1858 spin_lock(&hsotg->lock);
1859 }
1860 }
1861
1862 /* If we have pending request, then start it */
1863 if (!ep->req)
1864 dwc2_gadget_start_next_request(ep);
1865 }
1866
1867 break;
1868
1869 default:
1870 return -ENOENT;
1871 }
1872 break;
1873 default:
1874 return -ENOENT;
1875 }
1876 return 1;
1877}
1878
1879static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1880
1881/**
1882 * dwc2_hsotg_stall_ep0 - stall ep0
1883 * @hsotg: The device state
1884 *
1885 * Set stall for ep0 as response for setup request.
1886 */
1887static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1888{
1889 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1890 u32 reg;
1891 u32 ctrl;
1892
1893 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1894 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1895
1896 /*
1897 * DxEPCTL_Stall will be cleared by EP once it has
1898 * taken effect, so no need to clear later.
1899 */
1900
1901 ctrl = dwc2_readl(hsotg, reg);
1902 ctrl |= DXEPCTL_STALL;
1903 ctrl |= DXEPCTL_CNAK;
1904 dwc2_writel(hsotg, ctrl, reg);
1905
1906 dev_dbg(hsotg->dev,
1907 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1908 ctrl, reg, dwc2_readl(hsotg, reg));
1909
1910 /*
1911 * complete won't be called, so we enqueue
1912 * setup request here
1913 */
1914 dwc2_hsotg_enqueue_setup(hsotg);
1915}
1916
1917/**
1918 * dwc2_hsotg_process_control - process a control request
1919 * @hsotg: The device state
1920 * @ctrl: The control request received
1921 *
1922 * The controller has received the SETUP phase of a control request, and
1923 * needs to work out what to do next (and whether to pass it on to the
1924 * gadget driver).
1925 */
1926static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1927 struct usb_ctrlrequest *ctrl)
1928{
1929 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1930 int ret = 0;
1931 u32 dcfg;
1932
1933 dev_dbg(hsotg->dev,
1934 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1935 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1936 ctrl->wIndex, ctrl->wLength);
1937
1938 if (ctrl->wLength == 0) {
1939 ep0->dir_in = 1;
1940 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1941 } else if (ctrl->bRequestType & USB_DIR_IN) {
1942 ep0->dir_in = 1;
1943 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1944 } else {
1945 ep0->dir_in = 0;
1946 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1947 }
1948
1949 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1950 switch (ctrl->bRequest) {
1951 case USB_REQ_SET_ADDRESS:
1952 hsotg->connected = 1;
1953 dcfg = dwc2_readl(hsotg, DCFG);
1954 dcfg &= ~DCFG_DEVADDR_MASK;
1955 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1956 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1957 dwc2_writel(hsotg, dcfg, DCFG);
1958
1959 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1960
1961 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1962 return;
1963
1964 case USB_REQ_GET_STATUS:
1965 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1966 break;
1967
1968 case USB_REQ_CLEAR_FEATURE:
1969 case USB_REQ_SET_FEATURE:
1970 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1971 break;
1972 }
1973 }
1974
1975 /* as a fallback, try delivering it to the driver to deal with */
1976
1977 if (ret == 0 && hsotg->driver) {
1978 spin_unlock(&hsotg->lock);
1979 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1980 spin_lock(&hsotg->lock);
1981 if (ret < 0)
1982 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1983 }
1984
1985 hsotg->delayed_status = false;
1986 if (ret == USB_GADGET_DELAYED_STATUS)
1987 hsotg->delayed_status = true;
1988
1989 /*
1990 * the request is either unhandlable, or is not formatted correctly
1991 * so respond with a STALL for the status stage to indicate failure.
1992 */
1993
1994 if (ret < 0)
1995 dwc2_hsotg_stall_ep0(hsotg);
1996}
1997
1998/**
1999 * dwc2_hsotg_complete_setup - completion of a setup transfer
2000 * @ep: The endpoint the request was on.
2001 * @req: The request completed.
2002 *
2003 * Called on completion of any requests the driver itself submitted for
2004 * EP0 setup packets
2005 */
2006static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
2007 struct usb_request *req)
2008{
2009 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2010 struct dwc2_hsotg *hsotg = hs_ep->parent;
2011
2012 if (req->status < 0) {
2013 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
2014 return;
2015 }
2016
2017 spin_lock(&hsotg->lock);
2018 if (req->actual == 0)
2019 dwc2_hsotg_enqueue_setup(hsotg);
2020 else
2021 dwc2_hsotg_process_control(hsotg, req->buf);
2022 spin_unlock(&hsotg->lock);
2023}
2024
2025/**
2026 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
2027 * @hsotg: The device state.
2028 *
2029 * Enqueue a request on EP0 if necessary to received any SETUP packets
2030 * received from the host.
2031 */
2032static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
2033{
2034 struct usb_request *req = hsotg->ctrl_req;
2035 struct dwc2_hsotg_req *hs_req = our_req(req);
2036 int ret;
2037
2038 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2039
2040 req->zero = 0;
2041 req->length = 8;
2042 req->buf = hsotg->ctrl_buff;
2043 req->complete = dwc2_hsotg_complete_setup;
2044
2045 if (!list_empty(&hs_req->queue)) {
2046 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2047 return;
2048 }
2049
2050 hsotg->eps_out[0]->dir_in = 0;
2051 hsotg->eps_out[0]->send_zlp = 0;
2052 hsotg->ep0_state = DWC2_EP0_SETUP;
2053
2054 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2055 if (ret < 0) {
2056 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2057 /*
2058 * Don't think there's much we can do other than watch the
2059 * driver fail.
2060 */
2061 }
2062}
2063
2064static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2065 struct dwc2_hsotg_ep *hs_ep)
2066{
2067 u32 ctrl;
2068 u8 index = hs_ep->index;
2069 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2070 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
2071
2072 if (hs_ep->dir_in)
2073 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2074 index);
2075 else
2076 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2077 index);
2078 if (using_desc_dma(hsotg)) {
2079 /* Not specific buffer needed for ep0 ZLP */
2080 dma_addr_t dma = hs_ep->desc_list_dma;
2081
2082 if (!index)
2083 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2084
2085 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
2086 } else {
2087 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2088 DXEPTSIZ_XFERSIZE(0),
2089 epsiz_reg);
2090 }
2091
2092 ctrl = dwc2_readl(hsotg, epctl_reg);
2093 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
2094 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
2095 ctrl |= DXEPCTL_USBACTEP;
2096 dwc2_writel(hsotg, ctrl, epctl_reg);
2097}
2098
2099/**
2100 * dwc2_hsotg_complete_request - complete a request given to us
2101 * @hsotg: The device state.
2102 * @hs_ep: The endpoint the request was on.
2103 * @hs_req: The request to complete.
2104 * @result: The result code (0 => Ok, otherwise errno)
2105 *
2106 * The given request has finished, so call the necessary completion
2107 * if it has one and then look to see if we can start a new request
2108 * on the endpoint.
2109 *
2110 * Note, expects the ep to already be locked as appropriate.
2111 */
2112static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2113 struct dwc2_hsotg_ep *hs_ep,
2114 struct dwc2_hsotg_req *hs_req,
2115 int result)
2116{
2117 if (!hs_req) {
2118 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2119 return;
2120 }
2121
2122 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2123 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2124
2125 /*
2126 * only replace the status if we've not already set an error
2127 * from a previous transaction
2128 */
2129
2130 if (hs_req->req.status == -EINPROGRESS)
2131 hs_req->req.status = result;
2132
2133 if (using_dma(hsotg))
2134 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2135
2136 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2137
2138 hs_ep->req = NULL;
2139 list_del_init(&hs_req->queue);
2140
2141 /*
2142 * call the complete request with the locks off, just in case the
2143 * request tries to queue more work for this endpoint.
2144 */
2145
2146 if (hs_req->req.complete) {
2147 spin_unlock(&hsotg->lock);
2148 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2149 spin_lock(&hsotg->lock);
2150 }
2151
2152 /* In DDMA don't need to proceed to starting of next ISOC request */
2153 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2154 return;
2155
2156 /*
2157 * Look to see if there is anything else to do. Note, the completion
2158 * of the previous request may have caused a new request to be started
2159 * so be careful when doing this.
2160 */
2161
2162 if (!hs_ep->req && result >= 0)
2163 dwc2_gadget_start_next_request(hs_ep);
2164}
2165
2166/*
2167 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2168 * @hs_ep: The endpoint the request was on.
2169 *
2170 * Get first request from the ep queue, determine descriptor on which complete
2171 * happened. SW discovers which descriptor currently in use by HW, adjusts
2172 * dma_address and calculates index of completed descriptor based on the value
2173 * of DEPDMA register. Update actual length of request, giveback to gadget.
2174 */
2175static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2176{
2177 struct dwc2_hsotg *hsotg = hs_ep->parent;
2178 struct dwc2_hsotg_req *hs_req;
2179 struct usb_request *ureq;
2180 u32 desc_sts;
2181 u32 mask;
2182
2183 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2184
2185 /* Process only descriptors with buffer status set to DMA done */
2186 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2187 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2188
2189 hs_req = get_ep_head(hs_ep);
2190 if (!hs_req) {
2191 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2192 return;
2193 }
2194 ureq = &hs_req->req;
2195
2196 /* Check completion status */
2197 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2198 DEV_DMA_STS_SUCC) {
2199 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2200 DEV_DMA_ISOC_RX_NBYTES_MASK;
2201 ureq->actual = ureq->length - ((desc_sts & mask) >>
2202 DEV_DMA_ISOC_NBYTES_SHIFT);
2203
2204 /* Adjust actual len for ISOC Out if len is
2205 * not align of 4
2206 */
2207 if (!hs_ep->dir_in && ureq->length & 0x3)
2208 ureq->actual += 4 - (ureq->length & 0x3);
2209
2210 /* Set actual frame number for completed transfers */
2211 ureq->frame_number =
2212 (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2213 DEV_DMA_ISOC_FRNUM_SHIFT;
2214 }
2215
2216 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2217
2218 hs_ep->compl_desc++;
2219 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
2220 hs_ep->compl_desc = 0;
2221 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2222 }
2223}
2224
2225/*
2226 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2227 * @hs_ep: The isochronous endpoint.
2228 *
2229 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2230 * interrupt. Reset target frame and next_desc to allow to start
2231 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2232 * interrupt for OUT direction.
2233 */
2234static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2235{
2236 struct dwc2_hsotg *hsotg = hs_ep->parent;
2237
2238 if (!hs_ep->dir_in)
2239 dwc2_flush_rx_fifo(hsotg);
2240 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2241
2242 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2243 hs_ep->next_desc = 0;
2244 hs_ep->compl_desc = 0;
2245}
2246
2247/**
2248 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2249 * @hsotg: The device state.
2250 * @ep_idx: The endpoint index for the data
2251 * @size: The size of data in the fifo, in bytes
2252 *
2253 * The FIFO status shows there is data to read from the FIFO for a given
2254 * endpoint, so sort out whether we need to read the data into a request
2255 * that has been made for that endpoint.
2256 */
2257static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2258{
2259 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2260 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2261 int to_read;
2262 int max_req;
2263 int read_ptr;
2264
2265 if (!hs_req) {
2266 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2267 int ptr;
2268
2269 dev_dbg(hsotg->dev,
2270 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2271 __func__, size, ep_idx, epctl);
2272
2273 /* dump the data from the FIFO, we've nothing we can do */
2274 for (ptr = 0; ptr < size; ptr += 4)
2275 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2276
2277 return;
2278 }
2279
2280 to_read = size;
2281 read_ptr = hs_req->req.actual;
2282 max_req = hs_req->req.length - read_ptr;
2283
2284 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2285 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2286
2287 if (to_read > max_req) {
2288 /*
2289 * more data appeared than we where willing
2290 * to deal with in this request.
2291 */
2292
2293 /* currently we don't deal this */
2294 WARN_ON_ONCE(1);
2295 }
2296
2297 hs_ep->total_data += to_read;
2298 hs_req->req.actual += to_read;
2299 to_read = DIV_ROUND_UP(to_read, 4);
2300
2301 /*
2302 * note, we might over-write the buffer end by 3 bytes depending on
2303 * alignment of the data.
2304 */
2305 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2306 hs_req->req.buf + read_ptr, to_read);
2307}
2308
2309/**
2310 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2311 * @hsotg: The device instance
2312 * @dir_in: If IN zlp
2313 *
2314 * Generate a zero-length IN packet request for terminating a SETUP
2315 * transaction.
2316 *
2317 * Note, since we don't write any data to the TxFIFO, then it is
2318 * currently believed that we do not need to wait for any space in
2319 * the TxFIFO.
2320 */
2321static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2322{
2323 /* eps_out[0] is used in both directions */
2324 hsotg->eps_out[0]->dir_in = dir_in;
2325 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2326
2327 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2328}
2329
2330/*
2331 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2332 * @hs_ep - The endpoint on which transfer went
2333 *
2334 * Iterate over endpoints descriptor chain and get info on bytes remained
2335 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2336 */
2337static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2338{
2339 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
2340 struct dwc2_hsotg *hsotg = hs_ep->parent;
2341 unsigned int bytes_rem = 0;
2342 unsigned int bytes_rem_correction = 0;
2343 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2344 int i;
2345 u32 status;
2346 u32 mps = hs_ep->ep.maxpacket;
2347 int dir_in = hs_ep->dir_in;
2348
2349 if (!desc)
2350 return -EINVAL;
2351
2352 /* Interrupt OUT EP with mps not multiple of 4 */
2353 if (hs_ep->index)
2354 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
2355 bytes_rem_correction = 4 - (mps % 4);
2356
2357 for (i = 0; i < hs_ep->desc_count; ++i) {
2358 status = desc->status;
2359 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2360 bytes_rem -= bytes_rem_correction;
2361
2362 if (status & DEV_DMA_STS_MASK)
2363 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2364 i, status & DEV_DMA_STS_MASK);
2365
2366 if (status & DEV_DMA_L)
2367 break;
2368
2369 desc++;
2370 }
2371
2372 return bytes_rem;
2373}
2374
2375/**
2376 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2377 * @hsotg: The device instance
2378 * @epnum: The endpoint received from
2379 *
2380 * The RXFIFO has delivered an OutDone event, which means that the data
2381 * transfer for an OUT endpoint has been completed, either by a short
2382 * packet or by the finish of a transfer.
2383 */
2384static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2385{
2386 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2387 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2388 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2389 struct usb_request *req = &hs_req->req;
2390 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2391 int result = 0;
2392
2393 if (!hs_req) {
2394 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2395 return;
2396 }
2397
2398 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2399 dev_dbg(hsotg->dev, "zlp packet received\n");
2400 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2401 dwc2_hsotg_enqueue_setup(hsotg);
2402 return;
2403 }
2404
2405 if (using_desc_dma(hsotg))
2406 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2407
2408 if (using_dma(hsotg)) {
2409 unsigned int size_done;
2410
2411 /*
2412 * Calculate the size of the transfer by checking how much
2413 * is left in the endpoint size register and then working it
2414 * out from the amount we loaded for the transfer.
2415 *
2416 * We need to do this as DMA pointers are always 32bit aligned
2417 * so may overshoot/undershoot the transfer.
2418 */
2419
2420 size_done = hs_ep->size_loaded - size_left;
2421 size_done += hs_ep->last_load;
2422
2423 req->actual = size_done;
2424 }
2425
2426 /* if there is more request to do, schedule new transfer */
2427 if (req->actual < req->length && size_left == 0) {
2428 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2429 return;
2430 }
2431
2432 if (req->actual < req->length && req->short_not_ok) {
2433 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2434 __func__, req->actual, req->length);
2435
2436 /*
2437 * todo - what should we return here? there's no one else
2438 * even bothering to check the status.
2439 */
2440 }
2441
2442 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2443 if (!using_desc_dma(hsotg) && epnum == 0 &&
2444 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2445 /* Move to STATUS IN */
2446 if (!hsotg->delayed_status)
2447 dwc2_hsotg_ep0_zlp(hsotg, true);
2448 }
2449
2450 /* Set actual frame number for completed transfers */
2451 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2452 req->frame_number = hs_ep->target_frame;
2453 dwc2_gadget_incr_frame_num(hs_ep);
2454 }
2455
2456 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2457}
2458
2459/**
2460 * dwc2_hsotg_handle_rx - RX FIFO has data
2461 * @hsotg: The device instance
2462 *
2463 * The IRQ handler has detected that the RX FIFO has some data in it
2464 * that requires processing, so find out what is in there and do the
2465 * appropriate read.
2466 *
2467 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2468 * chunks, so if you have x packets received on an endpoint you'll get x
2469 * FIFO events delivered, each with a packet's worth of data in it.
2470 *
2471 * When using DMA, we should not be processing events from the RXFIFO
2472 * as the actual data should be sent to the memory directly and we turn
2473 * on the completion interrupts to get notifications of transfer completion.
2474 */
2475static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2476{
2477 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2478 u32 epnum, status, size;
2479
2480 WARN_ON(using_dma(hsotg));
2481
2482 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2483 status = grxstsr & GRXSTS_PKTSTS_MASK;
2484
2485 size = grxstsr & GRXSTS_BYTECNT_MASK;
2486 size >>= GRXSTS_BYTECNT_SHIFT;
2487
2488 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2489 __func__, grxstsr, size, epnum);
2490
2491 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2492 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2493 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2494 break;
2495
2496 case GRXSTS_PKTSTS_OUTDONE:
2497 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2498 dwc2_hsotg_read_frameno(hsotg));
2499
2500 if (!using_dma(hsotg))
2501 dwc2_hsotg_handle_outdone(hsotg, epnum);
2502 break;
2503
2504 case GRXSTS_PKTSTS_SETUPDONE:
2505 dev_dbg(hsotg->dev,
2506 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2507 dwc2_hsotg_read_frameno(hsotg),
2508 dwc2_readl(hsotg, DOEPCTL(0)));
2509 /*
2510 * Call dwc2_hsotg_handle_outdone here if it was not called from
2511 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2512 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2513 */
2514 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2515 dwc2_hsotg_handle_outdone(hsotg, epnum);
2516 break;
2517
2518 case GRXSTS_PKTSTS_OUTRX:
2519 dwc2_hsotg_rx_data(hsotg, epnum, size);
2520 break;
2521
2522 case GRXSTS_PKTSTS_SETUPRX:
2523 dev_dbg(hsotg->dev,
2524 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2525 dwc2_hsotg_read_frameno(hsotg),
2526 dwc2_readl(hsotg, DOEPCTL(0)));
2527
2528 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2529
2530 dwc2_hsotg_rx_data(hsotg, epnum, size);
2531 break;
2532
2533 default:
2534 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2535 __func__, grxstsr);
2536
2537 dwc2_hsotg_dump(hsotg);
2538 break;
2539 }
2540}
2541
2542/**
2543 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2544 * @mps: The maximum packet size in bytes.
2545 */
2546static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2547{
2548 switch (mps) {
2549 case 64:
2550 return D0EPCTL_MPS_64;
2551 case 32:
2552 return D0EPCTL_MPS_32;
2553 case 16:
2554 return D0EPCTL_MPS_16;
2555 case 8:
2556 return D0EPCTL_MPS_8;
2557 }
2558
2559 /* bad max packet size, warn and return invalid result */
2560 WARN_ON(1);
2561 return (u32)-1;
2562}
2563
2564/**
2565 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2566 * @hsotg: The driver state.
2567 * @ep: The index number of the endpoint
2568 * @mps: The maximum packet size in bytes
2569 * @mc: The multicount value
2570 * @dir_in: True if direction is in.
2571 *
2572 * Configure the maximum packet size for the given endpoint, updating
2573 * the hardware control registers to reflect this.
2574 */
2575static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2576 unsigned int ep, unsigned int mps,
2577 unsigned int mc, unsigned int dir_in)
2578{
2579 struct dwc2_hsotg_ep *hs_ep;
2580 u32 reg;
2581
2582 hs_ep = index_to_ep(hsotg, ep, dir_in);
2583 if (!hs_ep)
2584 return;
2585
2586 if (ep == 0) {
2587 u32 mps_bytes = mps;
2588
2589 /* EP0 is a special case */
2590 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2591 if (mps > 3)
2592 goto bad_mps;
2593 hs_ep->ep.maxpacket = mps_bytes;
2594 hs_ep->mc = 1;
2595 } else {
2596 if (mps > 1024)
2597 goto bad_mps;
2598 hs_ep->mc = mc;
2599 if (mc > 3)
2600 goto bad_mps;
2601 hs_ep->ep.maxpacket = mps;
2602 }
2603
2604 if (dir_in) {
2605 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2606 reg &= ~DXEPCTL_MPS_MASK;
2607 reg |= mps;
2608 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2609 } else {
2610 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2611 reg &= ~DXEPCTL_MPS_MASK;
2612 reg |= mps;
2613 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2614 }
2615
2616 return;
2617
2618bad_mps:
2619 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2620}
2621
2622/**
2623 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2624 * @hsotg: The driver state
2625 * @idx: The index for the endpoint (0..15)
2626 */
2627static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2628{
2629 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2630 GRSTCTL);
2631
2632 /* wait until the fifo is flushed */
2633 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2634 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2635 __func__);
2636}
2637
2638/**
2639 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2640 * @hsotg: The driver state
2641 * @hs_ep: The driver endpoint to check.
2642 *
2643 * Check to see if there is a request that has data to send, and if so
2644 * make an attempt to write data into the FIFO.
2645 */
2646static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2647 struct dwc2_hsotg_ep *hs_ep)
2648{
2649 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2650
2651 if (!hs_ep->dir_in || !hs_req) {
2652 /**
2653 * if request is not enqueued, we disable interrupts
2654 * for endpoints, excepting ep0
2655 */
2656 if (hs_ep->index != 0)
2657 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2658 hs_ep->dir_in, 0);
2659 return 0;
2660 }
2661
2662 if (hs_req->req.actual < hs_req->req.length) {
2663 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2664 hs_ep->index);
2665 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2666 }
2667
2668 return 0;
2669}
2670
2671/**
2672 * dwc2_hsotg_complete_in - complete IN transfer
2673 * @hsotg: The device state.
2674 * @hs_ep: The endpoint that has just completed.
2675 *
2676 * An IN transfer has been completed, update the transfer's state and then
2677 * call the relevant completion routines.
2678 */
2679static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2680 struct dwc2_hsotg_ep *hs_ep)
2681{
2682 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2683 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2684 int size_left, size_done;
2685
2686 if (!hs_req) {
2687 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2688 return;
2689 }
2690
2691 /* Finish ZLP handling for IN EP0 transactions */
2692 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2693 dev_dbg(hsotg->dev, "zlp packet sent\n");
2694
2695 /*
2696 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2697 * changed to IN. Change back to complete OUT transfer request
2698 */
2699 hs_ep->dir_in = 0;
2700
2701 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2702 if (hsotg->test_mode) {
2703 int ret;
2704
2705 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2706 if (ret < 0) {
2707 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2708 hsotg->test_mode);
2709 dwc2_hsotg_stall_ep0(hsotg);
2710 return;
2711 }
2712 }
2713 dwc2_hsotg_enqueue_setup(hsotg);
2714 return;
2715 }
2716
2717 /*
2718 * Calculate the size of the transfer by checking how much is left
2719 * in the endpoint size register and then working it out from
2720 * the amount we loaded for the transfer.
2721 *
2722 * We do this even for DMA, as the transfer may have incremented
2723 * past the end of the buffer (DMA transfers are always 32bit
2724 * aligned).
2725 */
2726 if (using_desc_dma(hsotg)) {
2727 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2728 if (size_left < 0)
2729 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2730 size_left);
2731 } else {
2732 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2733 }
2734
2735 size_done = hs_ep->size_loaded - size_left;
2736 size_done += hs_ep->last_load;
2737
2738 if (hs_req->req.actual != size_done)
2739 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2740 __func__, hs_req->req.actual, size_done);
2741
2742 hs_req->req.actual = size_done;
2743 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2744 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2745
2746 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2747 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2748 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2749 return;
2750 }
2751
2752 /* Zlp for all endpoints in non DDMA, for ep0 only in DATA IN stage */
2753 if (hs_ep->send_zlp) {
2754 hs_ep->send_zlp = 0;
2755 if (!using_desc_dma(hsotg)) {
2756 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2757 /* transfer will be completed on next complete interrupt */
2758 return;
2759 }
2760 }
2761
2762 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2763 /* Move to STATUS OUT */
2764 dwc2_hsotg_ep0_zlp(hsotg, false);
2765 return;
2766 }
2767
2768 /* Set actual frame number for completed transfers */
2769 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2770 hs_req->req.frame_number = hs_ep->target_frame;
2771 dwc2_gadget_incr_frame_num(hs_ep);
2772 }
2773
2774 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2775}
2776
2777/**
2778 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2779 * @hsotg: The device state.
2780 * @idx: Index of ep.
2781 * @dir_in: Endpoint direction 1-in 0-out.
2782 *
2783 * Reads for endpoint with given index and direction, by masking
2784 * epint_reg with coresponding mask.
2785 */
2786static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2787 unsigned int idx, int dir_in)
2788{
2789 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2790 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2791 u32 ints;
2792 u32 mask;
2793 u32 diepempmsk;
2794
2795 mask = dwc2_readl(hsotg, epmsk_reg);
2796 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2797 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2798 mask |= DXEPINT_SETUP_RCVD;
2799
2800 ints = dwc2_readl(hsotg, epint_reg);
2801 ints &= mask;
2802 return ints;
2803}
2804
2805/**
2806 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2807 * @hs_ep: The endpoint on which interrupt is asserted.
2808 *
2809 * This interrupt indicates that the endpoint has been disabled per the
2810 * application's request.
2811 *
2812 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2813 * in case of ISOC completes current request.
2814 *
2815 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2816 * request starts it.
2817 */
2818static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2819{
2820 struct dwc2_hsotg *hsotg = hs_ep->parent;
2821 struct dwc2_hsotg_req *hs_req;
2822 unsigned char idx = hs_ep->index;
2823 int dir_in = hs_ep->dir_in;
2824 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2825 int dctl = dwc2_readl(hsotg, DCTL);
2826
2827 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2828
2829 if (dir_in) {
2830 int epctl = dwc2_readl(hsotg, epctl_reg);
2831
2832 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2833
2834 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2835 int dctl = dwc2_readl(hsotg, DCTL);
2836
2837 dctl |= DCTL_CGNPINNAK;
2838 dwc2_writel(hsotg, dctl, DCTL);
2839 }
2840 } else {
2841
2842 if (dctl & DCTL_GOUTNAKSTS) {
2843 dctl |= DCTL_CGOUTNAK;
2844 dwc2_writel(hsotg, dctl, DCTL);
2845 }
2846 }
2847
2848 if (!hs_ep->isochronous)
2849 return;
2850
2851 if (list_empty(&hs_ep->queue)) {
2852 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2853 __func__, hs_ep);
2854 return;
2855 }
2856
2857 do {
2858 hs_req = get_ep_head(hs_ep);
2859 if (hs_req)
2860 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2861 -ENODATA);
2862 dwc2_gadget_incr_frame_num(hs_ep);
2863 /* Update current frame number value. */
2864 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2865 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2866}
2867
2868/**
2869 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2870 * @ep: The endpoint on which interrupt is asserted.
2871 *
2872 * This is starting point for ISOC-OUT transfer, synchronization done with
2873 * first out token received from host while corresponding EP is disabled.
2874 *
2875 * Device does not know initial frame in which out token will come. For this
2876 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2877 * getting this interrupt SW starts calculation for next transfer frame.
2878 */
2879static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2880{
2881 struct dwc2_hsotg *hsotg = ep->parent;
2882 struct dwc2_hsotg_req *hs_req;
2883 int dir_in = ep->dir_in;
2884
2885 if (dir_in || !ep->isochronous)
2886 return;
2887
2888 if (using_desc_dma(hsotg)) {
2889 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2890 /* Start first ISO Out */
2891 ep->target_frame = hsotg->frame_number;
2892 dwc2_gadget_start_isoc_ddma(ep);
2893 }
2894 return;
2895 }
2896
2897 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2898 u32 ctrl;
2899
2900 ep->target_frame = hsotg->frame_number;
2901 if (ep->interval > 1) {
2902 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2903 if (ep->target_frame & 0x1)
2904 ctrl |= DXEPCTL_SETODDFR;
2905 else
2906 ctrl |= DXEPCTL_SETEVENFR;
2907
2908 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2909 }
2910 }
2911
2912 while (dwc2_gadget_target_frame_elapsed(ep)) {
2913 hs_req = get_ep_head(ep);
2914 if (hs_req)
2915 dwc2_hsotg_complete_request(hsotg, ep, hs_req, -ENODATA);
2916
2917 dwc2_gadget_incr_frame_num(ep);
2918 /* Update current frame number value. */
2919 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2920 }
2921
2922 if (!ep->req)
2923 dwc2_gadget_start_next_request(ep);
2924
2925}
2926
2927static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2928 struct dwc2_hsotg_ep *hs_ep);
2929
2930/**
2931 * dwc2_gadget_handle_nak - handle NAK interrupt
2932 * @hs_ep: The endpoint on which interrupt is asserted.
2933 *
2934 * This is starting point for ISOC-IN transfer, synchronization done with
2935 * first IN token received from host while corresponding EP is disabled.
2936 *
2937 * Device does not know when first one token will arrive from host. On first
2938 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2939 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2940 * sent in response to that as there was no data in FIFO. SW is basing on this
2941 * interrupt to obtain frame in which token has come and then based on the
2942 * interval calculates next frame for transfer.
2943 */
2944static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2945{
2946 struct dwc2_hsotg *hsotg = hs_ep->parent;
2947 struct dwc2_hsotg_req *hs_req;
2948 int dir_in = hs_ep->dir_in;
2949 u32 ctrl;
2950
2951 if (!dir_in || !hs_ep->isochronous)
2952 return;
2953
2954 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2955
2956 if (using_desc_dma(hsotg)) {
2957 hs_ep->target_frame = hsotg->frame_number;
2958 dwc2_gadget_incr_frame_num(hs_ep);
2959
2960 /* In service interval mode target_frame must
2961 * be set to last (u)frame of the service interval.
2962 */
2963 if (hsotg->params.service_interval) {
2964 /* Set target_frame to the first (u)frame of
2965 * the service interval
2966 */
2967 hs_ep->target_frame &= ~hs_ep->interval + 1;
2968
2969 /* Set target_frame to the last (u)frame of
2970 * the service interval
2971 */
2972 dwc2_gadget_incr_frame_num(hs_ep);
2973 dwc2_gadget_dec_frame_num_by_one(hs_ep);
2974 }
2975
2976 dwc2_gadget_start_isoc_ddma(hs_ep);
2977 return;
2978 }
2979
2980 hs_ep->target_frame = hsotg->frame_number;
2981 if (hs_ep->interval > 1) {
2982 u32 ctrl = dwc2_readl(hsotg,
2983 DIEPCTL(hs_ep->index));
2984 if (hs_ep->target_frame & 0x1)
2985 ctrl |= DXEPCTL_SETODDFR;
2986 else
2987 ctrl |= DXEPCTL_SETEVENFR;
2988
2989 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
2990 }
2991 }
2992
2993 if (using_desc_dma(hsotg))
2994 return;
2995
2996 ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index));
2997 if (ctrl & DXEPCTL_EPENA)
2998 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
2999 else
3000 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
3001
3002 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
3003 hs_req = get_ep_head(hs_ep);
3004 if (hs_req)
3005 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
3006
3007 dwc2_gadget_incr_frame_num(hs_ep);
3008 /* Update current frame number value. */
3009 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
3010 }
3011
3012 if (!hs_ep->req)
3013 dwc2_gadget_start_next_request(hs_ep);
3014}
3015
3016/**
3017 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
3018 * @hsotg: The driver state
3019 * @idx: The index for the endpoint (0..15)
3020 * @dir_in: Set if this is an IN endpoint
3021 *
3022 * Process and clear any interrupt pending for an individual endpoint
3023 */
3024static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
3025 int dir_in)
3026{
3027 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
3028 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
3029 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
3030 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
3031 u32 ints;
3032
3033 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
3034
3035 /* Clear endpoint interrupts */
3036 dwc2_writel(hsotg, ints, epint_reg);
3037
3038 if (!hs_ep) {
3039 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
3040 __func__, idx, dir_in ? "in" : "out");
3041 return;
3042 }
3043
3044 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
3045 __func__, idx, dir_in ? "in" : "out", ints);
3046
3047 /* Don't process XferCompl interrupt if it is a setup packet */
3048 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
3049 ints &= ~DXEPINT_XFERCOMPL;
3050
3051 /*
3052 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
3053 * stage and xfercomplete was generated without SETUP phase done
3054 * interrupt. SW should parse received setup packet only after host's
3055 * exit from setup phase of control transfer.
3056 */
3057 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
3058 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
3059 ints &= ~DXEPINT_XFERCOMPL;
3060
3061 if (ints & DXEPINT_XFERCOMPL) {
3062 dev_dbg(hsotg->dev,
3063 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
3064 __func__, dwc2_readl(hsotg, epctl_reg),
3065 dwc2_readl(hsotg, epsiz_reg));
3066
3067 /* In DDMA handle isochronous requests separately */
3068 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3069 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
3070 } else if (dir_in) {
3071 /*
3072 * We get OutDone from the FIFO, so we only
3073 * need to look at completing IN requests here
3074 * if operating slave mode
3075 */
3076 if (!hs_ep->isochronous || !(ints & DXEPINT_NAKINTRPT))
3077 dwc2_hsotg_complete_in(hsotg, hs_ep);
3078
3079 if (idx == 0 && !hs_ep->req)
3080 dwc2_hsotg_enqueue_setup(hsotg);
3081 } else if (using_dma(hsotg)) {
3082 /*
3083 * We're using DMA, we need to fire an OutDone here
3084 * as we ignore the RXFIFO.
3085 */
3086 if (!hs_ep->isochronous || !(ints & DXEPINT_OUTTKNEPDIS))
3087 dwc2_hsotg_handle_outdone(hsotg, idx);
3088 }
3089 }
3090
3091 if (ints & DXEPINT_EPDISBLD)
3092 dwc2_gadget_handle_ep_disabled(hs_ep);
3093
3094 if (ints & DXEPINT_OUTTKNEPDIS)
3095 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3096
3097 if (ints & DXEPINT_NAKINTRPT)
3098 dwc2_gadget_handle_nak(hs_ep);
3099
3100 if (ints & DXEPINT_AHBERR)
3101 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3102
3103 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
3104 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3105
3106 if (using_dma(hsotg) && idx == 0) {
3107 /*
3108 * this is the notification we've received a
3109 * setup packet. In non-DMA mode we'd get this
3110 * from the RXFIFO, instead we need to process
3111 * the setup here.
3112 */
3113
3114 if (dir_in)
3115 WARN_ON_ONCE(1);
3116 else
3117 dwc2_hsotg_handle_outdone(hsotg, 0);
3118 }
3119 }
3120
3121 if (ints & DXEPINT_STSPHSERCVD) {
3122 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3123
3124 /* Safety check EP0 state when STSPHSERCVD asserted */
3125 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3126 /* Move to STATUS IN for DDMA */
3127 if (using_desc_dma(hsotg)) {
3128 if (!hsotg->delayed_status)
3129 dwc2_hsotg_ep0_zlp(hsotg, true);
3130 else
3131 /* In case of 3 stage Control Write with delayed
3132 * status, when Status IN transfer started
3133 * before STSPHSERCVD asserted, NAKSTS bit not
3134 * cleared by CNAK in dwc2_hsotg_start_req()
3135 * function. Clear now NAKSTS to allow complete
3136 * transfer.
3137 */
3138 dwc2_set_bit(hsotg, DIEPCTL(0),
3139 DXEPCTL_CNAK);
3140 }
3141 }
3142
3143 }
3144
3145 if (ints & DXEPINT_BACK2BACKSETUP)
3146 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3147
3148 if (ints & DXEPINT_BNAINTR) {
3149 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3150 if (hs_ep->isochronous)
3151 dwc2_gadget_handle_isoc_bna(hs_ep);
3152 }
3153
3154 if (dir_in && !hs_ep->isochronous) {
3155 /* not sure if this is important, but we'll clear it anyway */
3156 if (ints & DXEPINT_INTKNTXFEMP) {
3157 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3158 __func__, idx);
3159 }
3160
3161 /* this probably means something bad is happening */
3162 if (ints & DXEPINT_INTKNEPMIS) {
3163 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3164 __func__, idx);
3165 }
3166
3167 /* FIFO has space or is empty (see GAHBCFG) */
3168 if (hsotg->dedicated_fifos &&
3169 ints & DXEPINT_TXFEMP) {
3170 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3171 __func__, idx);
3172 if (!using_dma(hsotg))
3173 dwc2_hsotg_trytx(hsotg, hs_ep);
3174 }
3175 }
3176}
3177
3178/**
3179 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3180 * @hsotg: The device state.
3181 *
3182 * Handle updating the device settings after the enumeration phase has
3183 * been completed.
3184 */
3185static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3186{
3187 u32 dsts = dwc2_readl(hsotg, DSTS);
3188 int ep0_mps = 0, ep_mps = 8;
3189
3190 /*
3191 * This should signal the finish of the enumeration phase
3192 * of the USB handshaking, so we should now know what rate
3193 * we connected at.
3194 */
3195
3196 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3197
3198 /*
3199 * note, since we're limited by the size of transfer on EP0, and
3200 * it seems IN transfers must be a even number of packets we do
3201 * not advertise a 64byte MPS on EP0.
3202 */
3203
3204 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3205 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3206 case DSTS_ENUMSPD_FS:
3207 case DSTS_ENUMSPD_FS48:
3208 hsotg->gadget.speed = USB_SPEED_FULL;
3209 ep0_mps = EP0_MPS_LIMIT;
3210 ep_mps = 1023;
3211 break;
3212
3213 case DSTS_ENUMSPD_HS:
3214 hsotg->gadget.speed = USB_SPEED_HIGH;
3215 ep0_mps = EP0_MPS_LIMIT;
3216 ep_mps = 1024;
3217 break;
3218
3219 case DSTS_ENUMSPD_LS:
3220 hsotg->gadget.speed = USB_SPEED_LOW;
3221 ep0_mps = 8;
3222 ep_mps = 8;
3223 /*
3224 * note, we don't actually support LS in this driver at the
3225 * moment, and the documentation seems to imply that it isn't
3226 * supported by the PHYs on some of the devices.
3227 */
3228 break;
3229 }
3230 dev_info(hsotg->dev, "new device is %s\n",
3231 usb_speed_string(hsotg->gadget.speed));
3232
3233 /*
3234 * we should now know the maximum packet size for an
3235 * endpoint, so set the endpoints to a default value.
3236 */
3237
3238 if (ep0_mps) {
3239 int i;
3240 /* Initialize ep0 for both in and out directions */
3241 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3242 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3243 for (i = 1; i < hsotg->num_of_eps; i++) {
3244 if (hsotg->eps_in[i])
3245 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3246 0, 1);
3247 if (hsotg->eps_out[i])
3248 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3249 0, 0);
3250 }
3251 }
3252
3253 /* ensure after enumeration our EP0 is active */
3254
3255 dwc2_hsotg_enqueue_setup(hsotg);
3256
3257 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3258 dwc2_readl(hsotg, DIEPCTL0),
3259 dwc2_readl(hsotg, DOEPCTL0));
3260}
3261
3262/**
3263 * kill_all_requests - remove all requests from the endpoint's queue
3264 * @hsotg: The device state.
3265 * @ep: The endpoint the requests may be on.
3266 * @result: The result code to use.
3267 *
3268 * Go through the requests on the given endpoint and mark them
3269 * completed with the given result code.
3270 */
3271static void kill_all_requests(struct dwc2_hsotg *hsotg,
3272 struct dwc2_hsotg_ep *ep,
3273 int result)
3274{
3275 unsigned int size;
3276
3277 ep->req = NULL;
3278
3279 while (!list_empty(&ep->queue)) {
3280 struct dwc2_hsotg_req *req = get_ep_head(ep);
3281
3282 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3283 }
3284
3285 if (!hsotg->dedicated_fifos)
3286 return;
3287 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3288 if (size < ep->fifo_size)
3289 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3290}
3291
3292/**
3293 * dwc2_hsotg_disconnect - disconnect service
3294 * @hsotg: The device state.
3295 *
3296 * The device has been disconnected. Remove all current
3297 * transactions and signal the gadget driver that this
3298 * has happened.
3299 */
3300void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3301{
3302 unsigned int ep;
3303
3304 if (!hsotg->connected)
3305 return;
3306
3307 hsotg->connected = 0;
3308 hsotg->test_mode = 0;
3309
3310 /* all endpoints should be shutdown */
3311 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3312 if (hsotg->eps_in[ep])
3313 kill_all_requests(hsotg, hsotg->eps_in[ep],
3314 -ESHUTDOWN);
3315 if (hsotg->eps_out[ep])
3316 kill_all_requests(hsotg, hsotg->eps_out[ep],
3317 -ESHUTDOWN);
3318 }
3319
3320 call_gadget(hsotg, disconnect);
3321 hsotg->lx_state = DWC2_L3;
3322
3323 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3324}
3325
3326/**
3327 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3328 * @hsotg: The device state:
3329 * @periodic: True if this is a periodic FIFO interrupt
3330 */
3331static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3332{
3333 struct dwc2_hsotg_ep *ep;
3334 int epno, ret;
3335
3336 /* look through for any more data to transmit */
3337 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3338 ep = index_to_ep(hsotg, epno, 1);
3339
3340 if (!ep)
3341 continue;
3342
3343 if (!ep->dir_in)
3344 continue;
3345
3346 if ((periodic && !ep->periodic) ||
3347 (!periodic && ep->periodic))
3348 continue;
3349
3350 ret = dwc2_hsotg_trytx(hsotg, ep);
3351 if (ret < 0)
3352 break;
3353 }
3354}
3355
3356/* IRQ flags which will trigger a retry around the IRQ loop */
3357#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3358 GINTSTS_PTXFEMP | \
3359 GINTSTS_RXFLVL)
3360
3361static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3362/**
3363 * dwc2_hsotg_core_init_disconnected - issue softreset to the core
3364 * @hsotg: The device state
3365 * @is_usb_reset: Usb resetting flag
3366 *
3367 * Issue a soft reset to the core, and await the core finishing it.
3368 */
3369void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3370 bool is_usb_reset)
3371{
3372 u32 intmsk;
3373 u32 val;
3374 u32 usbcfg;
3375 u32 dcfg = 0;
3376 int ep;
3377
3378 /* Kill any ep0 requests as controller will be reinitialized */
3379 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3380
3381 if (!is_usb_reset) {
3382 if (dwc2_core_reset(hsotg, true))
3383 return;
3384 } else {
3385 /* all endpoints should be shutdown */
3386 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3387 if (hsotg->eps_in[ep])
3388 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3389 if (hsotg->eps_out[ep])
3390 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3391 }
3392 }
3393
3394 /*
3395 * we must now enable ep0 ready for host detection and then
3396 * set configuration.
3397 */
3398
3399 /* keep other bits untouched (so e.g. forced modes are not lost) */
3400 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3401 usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3402 usbcfg |= GUSBCFG_TOUTCAL(7);
3403
3404 /* remove the HNP/SRP and set the PHY */
3405 usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3406 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3407
3408 dwc2_phy_init(hsotg, true);
3409
3410 dwc2_hsotg_init_fifo(hsotg);
3411
3412 if (!is_usb_reset)
3413 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3414
3415 dcfg |= DCFG_EPMISCNT(1);
3416
3417 switch (hsotg->params.speed) {
3418 case DWC2_SPEED_PARAM_LOW:
3419 dcfg |= DCFG_DEVSPD_LS;
3420 break;
3421 case DWC2_SPEED_PARAM_FULL:
3422 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3423 dcfg |= DCFG_DEVSPD_FS48;
3424 else
3425 dcfg |= DCFG_DEVSPD_FS;
3426 break;
3427 default:
3428 dcfg |= DCFG_DEVSPD_HS;
3429 }
3430
3431 if (hsotg->params.ipg_isoc_en)
3432 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3433
3434 dwc2_writel(hsotg, dcfg, DCFG);
3435
3436 /* Clear any pending OTG interrupts */
3437 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3438
3439 /* Clear any pending interrupts */
3440 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3441 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3442 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3443 GINTSTS_USBRST | GINTSTS_RESETDET |
3444 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3445 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3446 GINTSTS_LPMTRANRCVD;
3447
3448 if (!using_desc_dma(hsotg))
3449 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3450
3451 if (!hsotg->params.external_id_pin_ctl)
3452 intmsk |= GINTSTS_CONIDSTSCHNG;
3453
3454 dwc2_writel(hsotg, intmsk, GINTMSK);
3455
3456 if (using_dma(hsotg)) {
3457 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3458 hsotg->params.ahbcfg,
3459 GAHBCFG);
3460
3461 /* Set DDMA mode support in the core if needed */
3462 if (using_desc_dma(hsotg))
3463 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3464
3465 } else {
3466 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3467 (GAHBCFG_NP_TXF_EMP_LVL |
3468 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3469 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3470 }
3471
3472 /*
3473 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3474 * when we have no data to transfer. Otherwise we get being flooded by
3475 * interrupts.
3476 */
3477
3478 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3479 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3480 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3481 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3482 DIEPMSK);
3483
3484 /*
3485 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3486 * DMA mode we may need this and StsPhseRcvd.
3487 */
3488 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3489 DOEPMSK_STSPHSERCVDMSK) : 0) |
3490 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3491 DOEPMSK_SETUPMSK,
3492 DOEPMSK);
3493
3494 /* Enable BNA interrupt for DDMA */
3495 if (using_desc_dma(hsotg)) {
3496 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3497 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3498 }
3499
3500 /* Enable Service Interval mode if supported */
3501 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3502 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3503
3504 dwc2_writel(hsotg, 0, DAINTMSK);
3505
3506 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3507 dwc2_readl(hsotg, DIEPCTL0),
3508 dwc2_readl(hsotg, DOEPCTL0));
3509
3510 /* enable in and out endpoint interrupts */
3511 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3512
3513 /*
3514 * Enable the RXFIFO when in slave mode, as this is how we collect
3515 * the data. In DMA mode, we get events from the FIFO but also
3516 * things we cannot process, so do not use it.
3517 */
3518 if (!using_dma(hsotg))
3519 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3520
3521 /* Enable interrupts for EP0 in and out */
3522 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3523 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3524
3525 if (!is_usb_reset) {
3526 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3527 udelay(10); /* see openiboot */
3528 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3529 }
3530
3531 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3532
3533 /*
3534 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3535 * writing to the EPCTL register..
3536 */
3537
3538 /* set to read 1 8byte packet */
3539 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3540 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3541
3542 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3543 DXEPCTL_CNAK | DXEPCTL_EPENA |
3544 DXEPCTL_USBACTEP,
3545 DOEPCTL0);
3546
3547 /* enable, but don't activate EP0in */
3548 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3549 DXEPCTL_USBACTEP, DIEPCTL0);
3550
3551 /* clear global NAKs */
3552 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3553 if (!is_usb_reset)
3554 val |= DCTL_SFTDISCON;
3555 dwc2_set_bit(hsotg, DCTL, val);
3556
3557 /* configure the core to support LPM */
3558 dwc2_gadget_init_lpm(hsotg);
3559
3560 /* program GREFCLK register if needed */
3561 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3562 dwc2_gadget_program_ref_clk(hsotg);
3563
3564 /* must be at-least 3ms to allow bus to see disconnect */
3565 mdelay(3);
3566
3567 hsotg->lx_state = DWC2_L0;
3568
3569 dwc2_hsotg_enqueue_setup(hsotg);
3570
3571 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3572 dwc2_readl(hsotg, DIEPCTL0),
3573 dwc2_readl(hsotg, DOEPCTL0));
3574}
3575
3576void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3577{
3578 /* set the soft-disconnect bit */
3579 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3580}
3581
3582void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3583{
3584 /* remove the soft-disconnect and let's go */
3585 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3586}
3587
3588/**
3589 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3590 * @hsotg: The device state:
3591 *
3592 * This interrupt indicates one of the following conditions occurred while
3593 * transmitting an ISOC transaction.
3594 * - Corrupted IN Token for ISOC EP.
3595 * - Packet not complete in FIFO.
3596 *
3597 * The following actions will be taken:
3598 * - Determine the EP
3599 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3600 */
3601static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3602{
3603 struct dwc2_hsotg_ep *hs_ep;
3604 u32 epctrl;
3605 u32 daintmsk;
3606 u32 idx;
3607
3608 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3609
3610 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3611
3612 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3613 hs_ep = hsotg->eps_in[idx];
3614 /* Proceed only unmasked ISOC EPs */
3615 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3616 continue;
3617
3618 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3619 if ((epctrl & DXEPCTL_EPENA) &&
3620 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3621 epctrl |= DXEPCTL_SNAK;
3622 epctrl |= DXEPCTL_EPDIS;
3623 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3624 }
3625 }
3626
3627 /* Clear interrupt */
3628 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3629}
3630
3631/**
3632 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3633 * @hsotg: The device state:
3634 *
3635 * This interrupt indicates one of the following conditions occurred while
3636 * transmitting an ISOC transaction.
3637 * - Corrupted OUT Token for ISOC EP.
3638 * - Packet not complete in FIFO.
3639 *
3640 * The following actions will be taken:
3641 * - Determine the EP
3642 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3643 */
3644static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3645{
3646 u32 gintsts;
3647 u32 gintmsk;
3648 u32 daintmsk;
3649 u32 epctrl;
3650 struct dwc2_hsotg_ep *hs_ep;
3651 int idx;
3652
3653 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3654
3655 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3656 daintmsk >>= DAINT_OUTEP_SHIFT;
3657
3658 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3659 hs_ep = hsotg->eps_out[idx];
3660 /* Proceed only unmasked ISOC EPs */
3661 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3662 continue;
3663
3664 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3665 if ((epctrl & DXEPCTL_EPENA) &&
3666 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3667 /* Unmask GOUTNAKEFF interrupt */
3668 gintmsk = dwc2_readl(hsotg, GINTMSK);
3669 gintmsk |= GINTSTS_GOUTNAKEFF;
3670 dwc2_writel(hsotg, gintmsk, GINTMSK);
3671
3672 gintsts = dwc2_readl(hsotg, GINTSTS);
3673 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3674 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3675 break;
3676 }
3677 }
3678 }
3679
3680 /* Clear interrupt */
3681 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3682}
3683
3684/**
3685 * dwc2_hsotg_irq - handle device interrupt
3686 * @irq: The IRQ number triggered
3687 * @pw: The pw value when registered the handler.
3688 */
3689static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3690{
3691 struct dwc2_hsotg *hsotg = pw;
3692 int retry_count = 8;
3693 u32 gintsts;
3694 u32 gintmsk;
3695
3696 if (!dwc2_is_device_mode(hsotg))
3697 return IRQ_NONE;
3698
3699 spin_lock(&hsotg->lock);
3700irq_retry:
3701 gintsts = dwc2_readl(hsotg, GINTSTS);
3702 gintmsk = dwc2_readl(hsotg, GINTMSK);
3703
3704 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3705 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3706
3707 gintsts &= gintmsk;
3708
3709 if (gintsts & GINTSTS_RESETDET) {
3710 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3711
3712 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3713
3714 /* This event must be used only if controller is suspended */
3715 if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2)
3716 dwc2_exit_partial_power_down(hsotg, 0, true);
3717
3718 hsotg->lx_state = DWC2_L0;
3719 }
3720
3721 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3722 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3723 u32 connected = hsotg->connected;
3724
3725 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3726 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3727 dwc2_readl(hsotg, GNPTXSTS));
3728
3729 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3730
3731 /* Report disconnection if it is not already done. */
3732 dwc2_hsotg_disconnect(hsotg);
3733
3734 /* Reset device address to zero */
3735 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3736
3737 if (usb_status & GOTGCTL_BSESVLD && connected)
3738 dwc2_hsotg_core_init_disconnected(hsotg, true);
3739 }
3740
3741 if (gintsts & GINTSTS_ENUMDONE) {
3742 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3743
3744 dwc2_hsotg_irq_enumdone(hsotg);
3745 }
3746
3747 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3748 u32 daint = dwc2_readl(hsotg, DAINT);
3749 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3750 u32 daint_out, daint_in;
3751 int ep;
3752
3753 daint &= daintmsk;
3754 daint_out = daint >> DAINT_OUTEP_SHIFT;
3755 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3756
3757 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3758
3759 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3760 ep++, daint_out >>= 1) {
3761 if (daint_out & 1)
3762 dwc2_hsotg_epint(hsotg, ep, 0);
3763 }
3764
3765 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3766 ep++, daint_in >>= 1) {
3767 if (daint_in & 1)
3768 dwc2_hsotg_epint(hsotg, ep, 1);
3769 }
3770 }
3771
3772 /* check both FIFOs */
3773
3774 if (gintsts & GINTSTS_NPTXFEMP) {
3775 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3776
3777 /*
3778 * Disable the interrupt to stop it happening again
3779 * unless one of these endpoint routines decides that
3780 * it needs re-enabling
3781 */
3782
3783 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3784 dwc2_hsotg_irq_fifoempty(hsotg, false);
3785 }
3786
3787 if (gintsts & GINTSTS_PTXFEMP) {
3788 dev_dbg(hsotg->dev, "PTxFEmp\n");
3789
3790 /* See note in GINTSTS_NPTxFEmp */
3791
3792 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3793 dwc2_hsotg_irq_fifoempty(hsotg, true);
3794 }
3795
3796 if (gintsts & GINTSTS_RXFLVL) {
3797 /*
3798 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3799 * we need to retry dwc2_hsotg_handle_rx if this is still
3800 * set.
3801 */
3802
3803 dwc2_hsotg_handle_rx(hsotg);
3804 }
3805
3806 if (gintsts & GINTSTS_ERLYSUSP) {
3807 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3808 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3809 }
3810
3811 /*
3812 * these next two seem to crop-up occasionally causing the core
3813 * to shutdown the USB transfer, so try clearing them and logging
3814 * the occurrence.
3815 */
3816
3817 if (gintsts & GINTSTS_GOUTNAKEFF) {
3818 u8 idx;
3819 u32 epctrl;
3820 u32 gintmsk;
3821 u32 daintmsk;
3822 struct dwc2_hsotg_ep *hs_ep;
3823
3824 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3825 daintmsk >>= DAINT_OUTEP_SHIFT;
3826 /* Mask this interrupt */
3827 gintmsk = dwc2_readl(hsotg, GINTMSK);
3828 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3829 dwc2_writel(hsotg, gintmsk, GINTMSK);
3830
3831 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3832 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3833 hs_ep = hsotg->eps_out[idx];
3834 /* Proceed only unmasked ISOC EPs */
3835 if (BIT(idx) & ~daintmsk)
3836 continue;
3837
3838 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3839
3840 //ISOC Ep's only
3841 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3842 epctrl |= DXEPCTL_SNAK;
3843 epctrl |= DXEPCTL_EPDIS;
3844 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3845 continue;
3846 }
3847
3848 //Non-ISOC EP's
3849 if (hs_ep->halted) {
3850 if (!(epctrl & DXEPCTL_EPENA))
3851 epctrl |= DXEPCTL_EPENA;
3852 epctrl |= DXEPCTL_EPDIS;
3853 epctrl |= DXEPCTL_STALL;
3854 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3855 }
3856 }
3857
3858 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3859 }
3860
3861 if (gintsts & GINTSTS_GINNAKEFF) {
3862 dev_info(hsotg->dev, "GINNakEff triggered\n");
3863
3864 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3865
3866 dwc2_hsotg_dump(hsotg);
3867 }
3868
3869 if (gintsts & GINTSTS_INCOMPL_SOIN)
3870 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3871
3872 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3873 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3874
3875 /*
3876 * if we've had fifo events, we should try and go around the
3877 * loop again to see if there's any point in returning yet.
3878 */
3879
3880 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3881 goto irq_retry;
3882
3883 /* Check WKUP_ALERT interrupt*/
3884 if (hsotg->params.service_interval)
3885 dwc2_gadget_wkup_alert_handler(hsotg);
3886
3887 spin_unlock(&hsotg->lock);
3888
3889 return IRQ_HANDLED;
3890}
3891
3892static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3893 struct dwc2_hsotg_ep *hs_ep)
3894{
3895 u32 epctrl_reg;
3896 u32 epint_reg;
3897
3898 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3899 DOEPCTL(hs_ep->index);
3900 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3901 DOEPINT(hs_ep->index);
3902
3903 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3904 hs_ep->name);
3905
3906 if (hs_ep->dir_in) {
3907 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3908 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3909 /* Wait for Nak effect */
3910 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3911 DXEPINT_INEPNAKEFF, 100))
3912 dev_warn(hsotg->dev,
3913 "%s: timeout DIEPINT.NAKEFF\n",
3914 __func__);
3915 } else {
3916 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3917 /* Wait for Nak effect */
3918 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3919 GINTSTS_GINNAKEFF, 100))
3920 dev_warn(hsotg->dev,
3921 "%s: timeout GINTSTS.GINNAKEFF\n",
3922 __func__);
3923 }
3924 } else {
3925 /* Mask GINTSTS_GOUTNAKEFF interrupt */
3926 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF);
3927
3928 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3929 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3930
3931 if (!using_dma(hsotg)) {
3932 /* Wait for GINTSTS_RXFLVL interrupt */
3933 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3934 GINTSTS_RXFLVL, 100)) {
3935 dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n",
3936 __func__);
3937 } else {
3938 /*
3939 * Pop GLOBAL OUT NAK status packet from RxFIFO
3940 * to assert GOUTNAKEFF interrupt
3941 */
3942 dwc2_readl(hsotg, GRXSTSP);
3943 }
3944 }
3945
3946 /* Wait for global nak to take effect */
3947 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3948 GINTSTS_GOUTNAKEFF, 100))
3949 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3950 __func__);
3951 }
3952
3953 /* Disable ep */
3954 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3955
3956 /* Wait for ep to be disabled */
3957 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3958 dev_warn(hsotg->dev,
3959 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3960
3961 /* Clear EPDISBLD interrupt */
3962 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3963
3964 if (hs_ep->dir_in) {
3965 unsigned short fifo_index;
3966
3967 if (hsotg->dedicated_fifos || hs_ep->periodic)
3968 fifo_index = hs_ep->fifo_index;
3969 else
3970 fifo_index = 0;
3971
3972 /* Flush TX FIFO */
3973 dwc2_flush_tx_fifo(hsotg, fifo_index);
3974
3975 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3976 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3977 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3978
3979 } else {
3980 /* Remove global NAKs */
3981 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
3982 }
3983}
3984
3985/**
3986 * dwc2_hsotg_ep_enable - enable the given endpoint
3987 * @ep: The USB endpint to configure
3988 * @desc: The USB endpoint descriptor to configure with.
3989 *
3990 * This is called from the USB gadget code's usb_ep_enable().
3991 */
3992static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3993 const struct usb_endpoint_descriptor *desc)
3994{
3995 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3996 struct dwc2_hsotg *hsotg = hs_ep->parent;
3997 unsigned long flags;
3998 unsigned int index = hs_ep->index;
3999 u32 epctrl_reg;
4000 u32 epctrl;
4001 u32 mps;
4002 u32 mc;
4003 u32 mask;
4004 unsigned int dir_in;
4005 unsigned int i, val, size;
4006 int ret = 0;
4007 unsigned char ep_type;
4008 int desc_num;
4009
4010 dev_dbg(hsotg->dev,
4011 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
4012 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
4013 desc->wMaxPacketSize, desc->bInterval);
4014
4015 /* not to be called for EP0 */
4016 if (index == 0) {
4017 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
4018 return -EINVAL;
4019 }
4020
4021 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
4022 if (dir_in != hs_ep->dir_in) {
4023 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
4024 return -EINVAL;
4025 }
4026
4027 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
4028 mps = usb_endpoint_maxp(desc);
4029 mc = usb_endpoint_maxp_mult(desc);
4030
4031 /* ISOC IN in DDMA supported bInterval up to 10 */
4032 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4033 dir_in && desc->bInterval > 10) {
4034 dev_err(hsotg->dev,
4035 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
4036 return -EINVAL;
4037 }
4038
4039 /* High bandwidth ISOC OUT in DDMA not supported */
4040 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4041 !dir_in && mc > 1) {
4042 dev_err(hsotg->dev,
4043 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
4044 return -EINVAL;
4045 }
4046
4047 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
4048
4049 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4050 epctrl = dwc2_readl(hsotg, epctrl_reg);
4051
4052 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
4053 __func__, epctrl, epctrl_reg);
4054
4055 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
4056 desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
4057 else
4058 desc_num = MAX_DMA_DESC_NUM_GENERIC;
4059
4060 /* Allocate DMA descriptor chain for non-ctrl endpoints */
4061 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
4062 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
4063 desc_num * sizeof(struct dwc2_dma_desc),
4064 &hs_ep->desc_list_dma, GFP_ATOMIC);
4065 if (!hs_ep->desc_list) {
4066 ret = -ENOMEM;
4067 goto error2;
4068 }
4069 }
4070
4071 spin_lock_irqsave(&hsotg->lock, flags);
4072
4073 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
4074 epctrl |= DXEPCTL_MPS(mps);
4075
4076 /*
4077 * mark the endpoint as active, otherwise the core may ignore
4078 * transactions entirely for this endpoint
4079 */
4080 epctrl |= DXEPCTL_USBACTEP;
4081
4082 /* update the endpoint state */
4083 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
4084
4085 /* default, set to non-periodic */
4086 hs_ep->isochronous = 0;
4087 hs_ep->periodic = 0;
4088 hs_ep->halted = 0;
4089 hs_ep->interval = desc->bInterval;
4090
4091 switch (ep_type) {
4092 case USB_ENDPOINT_XFER_ISOC:
4093 epctrl |= DXEPCTL_EPTYPE_ISO;
4094 epctrl |= DXEPCTL_SETEVENFR;
4095 hs_ep->isochronous = 1;
4096 hs_ep->interval = 1 << (desc->bInterval - 1);
4097 hs_ep->target_frame = TARGET_FRAME_INITIAL;
4098 hs_ep->next_desc = 0;
4099 hs_ep->compl_desc = 0;
4100 if (dir_in) {
4101 hs_ep->periodic = 1;
4102 mask = dwc2_readl(hsotg, DIEPMSK);
4103 mask |= DIEPMSK_NAKMSK;
4104 dwc2_writel(hsotg, mask, DIEPMSK);
4105 } else {
4106 epctrl |= DXEPCTL_SNAK;
4107 mask = dwc2_readl(hsotg, DOEPMSK);
4108 mask |= DOEPMSK_OUTTKNEPDISMSK;
4109 dwc2_writel(hsotg, mask, DOEPMSK);
4110 }
4111 break;
4112
4113 case USB_ENDPOINT_XFER_BULK:
4114 epctrl |= DXEPCTL_EPTYPE_BULK;
4115 break;
4116
4117 case USB_ENDPOINT_XFER_INT:
4118 if (dir_in)
4119 hs_ep->periodic = 1;
4120
4121 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4122 hs_ep->interval = 1 << (desc->bInterval - 1);
4123
4124 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
4125 break;
4126
4127 case USB_ENDPOINT_XFER_CONTROL:
4128 epctrl |= DXEPCTL_EPTYPE_CONTROL;
4129 break;
4130 }
4131
4132 /*
4133 * if the hardware has dedicated fifos, we must give each IN EP
4134 * a unique tx-fifo even if it is non-periodic.
4135 */
4136 if (dir_in && hsotg->dedicated_fifos) {
4137 unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
4138 u32 fifo_index = 0;
4139 u32 fifo_size = UINT_MAX;
4140
4141 size = hs_ep->ep.maxpacket * hs_ep->mc;
4142 for (i = 1; i <= fifo_count; ++i) {
4143 if (hsotg->fifo_map & (1 << i))
4144 continue;
4145 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4146 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
4147 if (val < size)
4148 continue;
4149 /* Search for smallest acceptable fifo */
4150 if (val < fifo_size) {
4151 fifo_size = val;
4152 fifo_index = i;
4153 }
4154 }
4155 if (!fifo_index) {
4156 dev_err(hsotg->dev,
4157 "%s: No suitable fifo found\n", __func__);
4158 ret = -ENOMEM;
4159 goto error1;
4160 }
4161 epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
4162 hsotg->fifo_map |= 1 << fifo_index;
4163 epctrl |= DXEPCTL_TXFNUM(fifo_index);
4164 hs_ep->fifo_index = fifo_index;
4165 hs_ep->fifo_size = fifo_size;
4166 }
4167
4168 /* for non control endpoints, set PID to D0 */
4169 if (index && !hs_ep->isochronous)
4170 epctrl |= DXEPCTL_SETD0PID;
4171
4172 /* WA for Full speed ISOC IN in DDMA mode.
4173 * By Clear NAK status of EP, core will send ZLP
4174 * to IN token and assert NAK interrupt relying
4175 * on TxFIFO status only
4176 */
4177
4178 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4179 hs_ep->isochronous && dir_in) {
4180 /* The WA applies only to core versions from 2.72a
4181 * to 4.00a (including both). Also for FS_IOT_1.00a
4182 * and HS_IOT_1.00a.
4183 */
4184 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4185
4186 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
4187 gsnpsid <= DWC2_CORE_REV_4_00a) ||
4188 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
4189 gsnpsid == DWC2_HS_IOT_REV_1_00a)
4190 epctrl |= DXEPCTL_CNAK;
4191 }
4192
4193 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4194 __func__, epctrl);
4195
4196 dwc2_writel(hsotg, epctrl, epctrl_reg);
4197 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4198 __func__, dwc2_readl(hsotg, epctrl_reg));
4199
4200 /* enable the endpoint interrupt */
4201 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4202
4203error1:
4204 spin_unlock_irqrestore(&hsotg->lock, flags);
4205
4206error2:
4207 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4208 dmam_free_coherent(hsotg->dev, desc_num *
4209 sizeof(struct dwc2_dma_desc),
4210 hs_ep->desc_list, hs_ep->desc_list_dma);
4211 hs_ep->desc_list = NULL;
4212 }
4213
4214 return ret;
4215}
4216
4217/**
4218 * dwc2_hsotg_ep_disable - disable given endpoint
4219 * @ep: The endpoint to disable.
4220 */
4221static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4222{
4223 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4224 struct dwc2_hsotg *hsotg = hs_ep->parent;
4225 int dir_in = hs_ep->dir_in;
4226 int index = hs_ep->index;
4227 u32 epctrl_reg;
4228 u32 ctrl;
4229
4230 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4231
4232 if (ep == &hsotg->eps_out[0]->ep) {
4233 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4234 return -EINVAL;
4235 }
4236
4237 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4238 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4239 return -EINVAL;
4240 }
4241
4242 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4243
4244 ctrl = dwc2_readl(hsotg, epctrl_reg);
4245
4246 if (ctrl & DXEPCTL_EPENA)
4247 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4248
4249 ctrl &= ~DXEPCTL_EPENA;
4250 ctrl &= ~DXEPCTL_USBACTEP;
4251 ctrl |= DXEPCTL_SNAK;
4252
4253 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4254 dwc2_writel(hsotg, ctrl, epctrl_reg);
4255
4256 /* disable endpoint interrupts */
4257 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4258
4259 /* terminate all requests with shutdown */
4260 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4261
4262 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4263 hs_ep->fifo_index = 0;
4264 hs_ep->fifo_size = 0;
4265
4266 return 0;
4267}
4268
4269static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
4270{
4271 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4272 struct dwc2_hsotg *hsotg = hs_ep->parent;
4273 unsigned long flags;
4274 int ret;
4275
4276 spin_lock_irqsave(&hsotg->lock, flags);
4277 ret = dwc2_hsotg_ep_disable(ep);
4278 spin_unlock_irqrestore(&hsotg->lock, flags);
4279 return ret;
4280}
4281
4282/**
4283 * on_list - check request is on the given endpoint
4284 * @ep: The endpoint to check.
4285 * @test: The request to test if it is on the endpoint.
4286 */
4287static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4288{
4289 struct dwc2_hsotg_req *req, *treq;
4290
4291 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4292 if (req == test)
4293 return true;
4294 }
4295
4296 return false;
4297}
4298
4299/**
4300 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4301 * @ep: The endpoint to dequeue.
4302 * @req: The request to be removed from a queue.
4303 */
4304static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4305{
4306 struct dwc2_hsotg_req *hs_req = our_req(req);
4307 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4308 struct dwc2_hsotg *hs = hs_ep->parent;
4309 unsigned long flags;
4310
4311 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4312
4313 spin_lock_irqsave(&hs->lock, flags);
4314
4315 if (!on_list(hs_ep, hs_req)) {
4316 spin_unlock_irqrestore(&hs->lock, flags);
4317 return -EINVAL;
4318 }
4319
4320 /* Dequeue already started request */
4321 if (req == &hs_ep->req->req)
4322 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4323
4324 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4325 spin_unlock_irqrestore(&hs->lock, flags);
4326
4327 return 0;
4328}
4329
4330/**
4331 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4332 * @ep: The endpoint to set halt.
4333 * @value: Set or unset the halt.
4334 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4335 * the endpoint is busy processing requests.
4336 *
4337 * We need to stall the endpoint immediately if request comes from set_feature
4338 * protocol command handler.
4339 */
4340static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4341{
4342 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4343 struct dwc2_hsotg *hs = hs_ep->parent;
4344 int index = hs_ep->index;
4345 u32 epreg;
4346 u32 epctl;
4347 u32 xfertype;
4348
4349 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4350
4351 if (index == 0) {
4352 if (value)
4353 dwc2_hsotg_stall_ep0(hs);
4354 else
4355 dev_warn(hs->dev,
4356 "%s: can't clear halt on ep0\n", __func__);
4357 return 0;
4358 }
4359
4360 if (hs_ep->isochronous) {
4361 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4362 return -EINVAL;
4363 }
4364
4365 if (!now && value && !list_empty(&hs_ep->queue)) {
4366 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4367 ep->name);
4368 return -EAGAIN;
4369 }
4370
4371 if (hs_ep->dir_in) {
4372 epreg = DIEPCTL(index);
4373 epctl = dwc2_readl(hs, epreg);
4374
4375 if (value) {
4376 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4377 if (epctl & DXEPCTL_EPENA)
4378 epctl |= DXEPCTL_EPDIS;
4379 } else {
4380 epctl &= ~DXEPCTL_STALL;
4381 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4382 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4383 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4384 epctl |= DXEPCTL_SETD0PID;
4385 }
4386 dwc2_writel(hs, epctl, epreg);
4387 } else {
4388 epreg = DOEPCTL(index);
4389 epctl = dwc2_readl(hs, epreg);
4390
4391 if (value) {
4392 /* Unmask GOUTNAKEFF interrupt */
4393 dwc2_hsotg_en_gsint(hs, GINTSTS_GOUTNAKEFF);
4394
4395 if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
4396 dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
4397 // STALL bit will be set in GOUTNAKEFF interrupt handler
4398 } else {
4399 epctl &= ~DXEPCTL_STALL;
4400 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4401 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4402 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4403 epctl |= DXEPCTL_SETD0PID;
4404 dwc2_writel(hs, epctl, epreg);
4405 }
4406 }
4407
4408 hs_ep->halted = value;
4409 return 0;
4410}
4411
4412/**
4413 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4414 * @ep: The endpoint to set halt.
4415 * @value: Set or unset the halt.
4416 */
4417static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4418{
4419 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4420 struct dwc2_hsotg *hs = hs_ep->parent;
4421 unsigned long flags;
4422 int ret;
4423
4424 spin_lock_irqsave(&hs->lock, flags);
4425 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4426 spin_unlock_irqrestore(&hs->lock, flags);
4427
4428 return ret;
4429}
4430
4431static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4432 .enable = dwc2_hsotg_ep_enable,
4433 .disable = dwc2_hsotg_ep_disable_lock,
4434 .alloc_request = dwc2_hsotg_ep_alloc_request,
4435 .free_request = dwc2_hsotg_ep_free_request,
4436 .queue = dwc2_hsotg_ep_queue_lock,
4437 .dequeue = dwc2_hsotg_ep_dequeue,
4438 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4439 /* note, don't believe we have any call for the fifo routines */
4440};
4441
4442/**
4443 * dwc2_hsotg_init - initialize the usb core
4444 * @hsotg: The driver state
4445 */
4446static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4447{
4448 /* unmask subset of endpoint interrupts */
4449
4450 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4451 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4452 DIEPMSK);
4453
4454 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4455 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4456 DOEPMSK);
4457
4458 dwc2_writel(hsotg, 0, DAINTMSK);
4459
4460 /* Be in disconnected state until gadget is registered */
4461 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4462
4463 /* setup fifos */
4464
4465 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4466 dwc2_readl(hsotg, GRXFSIZ),
4467 dwc2_readl(hsotg, GNPTXFSIZ));
4468
4469 dwc2_hsotg_init_fifo(hsotg);
4470
4471 if (using_dma(hsotg))
4472 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4473}
4474
4475/**
4476 * dwc2_hsotg_udc_start - prepare the udc for work
4477 * @gadget: The usb gadget state
4478 * @driver: The usb gadget driver
4479 *
4480 * Perform initialization to prepare udc device and driver
4481 * to work.
4482 */
4483static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4484 struct usb_gadget_driver *driver)
4485{
4486 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4487 unsigned long flags;
4488 int ret;
4489
4490 if (!hsotg) {
4491 pr_err("%s: called with no device\n", __func__);
4492 return -ENODEV;
4493 }
4494
4495 if (!driver) {
4496 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4497 return -EINVAL;
4498 }
4499
4500 if (driver->max_speed < USB_SPEED_FULL)
4501 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4502
4503 if (!driver->setup) {
4504 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4505 return -EINVAL;
4506 }
4507
4508 WARN_ON(hsotg->driver);
4509
4510 driver->driver.bus = NULL;
4511 hsotg->driver = driver;
4512 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4513 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4514
4515 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4516 ret = dwc2_lowlevel_hw_enable(hsotg);
4517 if (ret)
4518 goto err;
4519 }
4520
4521 if (!IS_ERR_OR_NULL(hsotg->uphy))
4522 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4523
4524 spin_lock_irqsave(&hsotg->lock, flags);
4525 if (dwc2_hw_is_device(hsotg)) {
4526 dwc2_hsotg_init(hsotg);
4527 dwc2_hsotg_core_init_disconnected(hsotg, false);
4528 }
4529
4530 hsotg->enabled = 0;
4531 spin_unlock_irqrestore(&hsotg->lock, flags);
4532
4533 gadget->sg_supported = using_desc_dma(hsotg);
4534 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4535
4536 return 0;
4537
4538err:
4539 hsotg->driver = NULL;
4540 return ret;
4541}
4542
4543/**
4544 * dwc2_hsotg_udc_stop - stop the udc
4545 * @gadget: The usb gadget state
4546 *
4547 * Stop udc hw block and stay tunned for future transmissions
4548 */
4549static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4550{
4551 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4552 unsigned long flags;
4553 int ep;
4554
4555 if (!hsotg)
4556 return -ENODEV;
4557
4558 /* all endpoints should be shutdown */
4559 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4560 if (hsotg->eps_in[ep])
4561 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4562 if (hsotg->eps_out[ep])
4563 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4564 }
4565
4566 spin_lock_irqsave(&hsotg->lock, flags);
4567
4568 hsotg->driver = NULL;
4569 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4570 hsotg->enabled = 0;
4571
4572 spin_unlock_irqrestore(&hsotg->lock, flags);
4573
4574 if (!IS_ERR_OR_NULL(hsotg->uphy))
4575 otg_set_peripheral(hsotg->uphy->otg, NULL);
4576
4577 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4578 dwc2_lowlevel_hw_disable(hsotg);
4579
4580 return 0;
4581}
4582
4583/**
4584 * dwc2_hsotg_gadget_getframe - read the frame number
4585 * @gadget: The usb gadget state
4586 *
4587 * Read the {micro} frame number
4588 */
4589static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4590{
4591 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4592}
4593
4594/**
4595 * dwc2_hsotg_set_selfpowered - set if device is self/bus powered
4596 * @gadget: The usb gadget state
4597 * @is_selfpowered: Whether the device is self-powered
4598 *
4599 * Set if the device is self or bus powered.
4600 */
4601static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
4602 int is_selfpowered)
4603{
4604 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4605 unsigned long flags;
4606
4607 spin_lock_irqsave(&hsotg->lock, flags);
4608 gadget->is_selfpowered = !!is_selfpowered;
4609 spin_unlock_irqrestore(&hsotg->lock, flags);
4610
4611 return 0;
4612}
4613
4614/**
4615 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4616 * @gadget: The usb gadget state
4617 * @is_on: Current state of the USB PHY
4618 *
4619 * Connect/Disconnect the USB PHY pullup
4620 */
4621static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4622{
4623 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4624 unsigned long flags;
4625
4626 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4627 hsotg->op_state);
4628
4629 /* Don't modify pullup state while in host mode */
4630 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4631 hsotg->enabled = is_on;
4632 return 0;
4633 }
4634
4635 spin_lock_irqsave(&hsotg->lock, flags);
4636 if (is_on) {
4637 hsotg->enabled = 1;
4638 dwc2_hsotg_core_init_disconnected(hsotg, false);
4639 /* Enable ACG feature in device mode,if supported */
4640 dwc2_enable_acg(hsotg);
4641 dwc2_hsotg_core_connect(hsotg);
4642 } else {
4643 dwc2_hsotg_core_disconnect(hsotg);
4644 dwc2_hsotg_disconnect(hsotg);
4645 hsotg->enabled = 0;
4646 }
4647
4648 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4649 spin_unlock_irqrestore(&hsotg->lock, flags);
4650
4651 return 0;
4652}
4653
4654static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4655{
4656 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4657 unsigned long flags;
4658
4659 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4660 spin_lock_irqsave(&hsotg->lock, flags);
4661
4662 /*
4663 * If controller is in partial power down state, it must exit from
4664 * that state before being initialized / de-initialized
4665 */
4666 if (hsotg->lx_state == DWC2_L2 && hsotg->in_ppd)
4667 /*
4668 * No need to check the return value as
4669 * registers are not being restored.
4670 */
4671 dwc2_exit_partial_power_down(hsotg, 0, false);
4672
4673 if (is_active) {
4674 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4675
4676 dwc2_hsotg_core_init_disconnected(hsotg, false);
4677 if (hsotg->enabled) {
4678 /* Enable ACG feature in device mode,if supported */
4679 dwc2_enable_acg(hsotg);
4680 dwc2_hsotg_core_connect(hsotg);
4681 }
4682 } else {
4683 dwc2_hsotg_core_disconnect(hsotg);
4684 dwc2_hsotg_disconnect(hsotg);
4685 }
4686
4687 spin_unlock_irqrestore(&hsotg->lock, flags);
4688 return 0;
4689}
4690
4691/**
4692 * dwc2_hsotg_vbus_draw - report bMaxPower field
4693 * @gadget: The usb gadget state
4694 * @mA: Amount of current
4695 *
4696 * Report how much power the device may consume to the phy.
4697 */
4698static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4699{
4700 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4701
4702 if (IS_ERR_OR_NULL(hsotg->uphy))
4703 return -ENOTSUPP;
4704 return usb_phy_set_power(hsotg->uphy, mA);
4705}
4706
4707static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4708 .get_frame = dwc2_hsotg_gadget_getframe,
4709 .set_selfpowered = dwc2_hsotg_set_selfpowered,
4710 .udc_start = dwc2_hsotg_udc_start,
4711 .udc_stop = dwc2_hsotg_udc_stop,
4712 .pullup = dwc2_hsotg_pullup,
4713 .vbus_session = dwc2_hsotg_vbus_session,
4714 .vbus_draw = dwc2_hsotg_vbus_draw,
4715};
4716
4717/**
4718 * dwc2_hsotg_initep - initialise a single endpoint
4719 * @hsotg: The device state.
4720 * @hs_ep: The endpoint to be initialised.
4721 * @epnum: The endpoint number
4722 * @dir_in: True if direction is in.
4723 *
4724 * Initialise the given endpoint (as part of the probe and device state
4725 * creation) to give to the gadget driver. Setup the endpoint name, any
4726 * direction information and other state that may be required.
4727 */
4728static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4729 struct dwc2_hsotg_ep *hs_ep,
4730 int epnum,
4731 bool dir_in)
4732{
4733 char *dir;
4734
4735 if (epnum == 0)
4736 dir = "";
4737 else if (dir_in)
4738 dir = "in";
4739 else
4740 dir = "out";
4741
4742 hs_ep->dir_in = dir_in;
4743 hs_ep->index = epnum;
4744
4745 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4746
4747 INIT_LIST_HEAD(&hs_ep->queue);
4748 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4749
4750 /* add to the list of endpoints known by the gadget driver */
4751 if (epnum)
4752 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4753
4754 hs_ep->parent = hsotg;
4755 hs_ep->ep.name = hs_ep->name;
4756
4757 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4758 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4759 else
4760 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4761 epnum ? 1024 : EP0_MPS_LIMIT);
4762 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4763
4764 if (epnum == 0) {
4765 hs_ep->ep.caps.type_control = true;
4766 } else {
4767 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4768 hs_ep->ep.caps.type_iso = true;
4769 hs_ep->ep.caps.type_bulk = true;
4770 }
4771 hs_ep->ep.caps.type_int = true;
4772 }
4773
4774 if (dir_in)
4775 hs_ep->ep.caps.dir_in = true;
4776 else
4777 hs_ep->ep.caps.dir_out = true;
4778
4779 /*
4780 * if we're using dma, we need to set the next-endpoint pointer
4781 * to be something valid.
4782 */
4783
4784 if (using_dma(hsotg)) {
4785 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4786
4787 if (dir_in)
4788 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4789 else
4790 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4791 }
4792}
4793
4794/**
4795 * dwc2_hsotg_hw_cfg - read HW configuration registers
4796 * @hsotg: Programming view of the DWC_otg controller
4797 *
4798 * Read the USB core HW configuration registers
4799 */
4800static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4801{
4802 u32 cfg;
4803 u32 ep_type;
4804 u32 i;
4805
4806 /* check hardware configuration */
4807
4808 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4809
4810 /* Add ep0 */
4811 hsotg->num_of_eps++;
4812
4813 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4814 sizeof(struct dwc2_hsotg_ep),
4815 GFP_KERNEL);
4816 if (!hsotg->eps_in[0])
4817 return -ENOMEM;
4818 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4819 hsotg->eps_out[0] = hsotg->eps_in[0];
4820
4821 cfg = hsotg->hw_params.dev_ep_dirs;
4822 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4823 ep_type = cfg & 3;
4824 /* Direction in or both */
4825 if (!(ep_type & 2)) {
4826 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4827 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4828 if (!hsotg->eps_in[i])
4829 return -ENOMEM;
4830 }
4831 /* Direction out or both */
4832 if (!(ep_type & 1)) {
4833 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4834 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4835 if (!hsotg->eps_out[i])
4836 return -ENOMEM;
4837 }
4838 }
4839
4840 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4841 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4842
4843 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4844 hsotg->num_of_eps,
4845 hsotg->dedicated_fifos ? "dedicated" : "shared",
4846 hsotg->fifo_mem);
4847 return 0;
4848}
4849
4850/**
4851 * dwc2_hsotg_dump - dump state of the udc
4852 * @hsotg: Programming view of the DWC_otg controller
4853 *
4854 */
4855static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4856{
4857#ifdef DEBUG
4858 struct device *dev = hsotg->dev;
4859 u32 val;
4860 int idx;
4861
4862 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4863 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4864 dwc2_readl(hsotg, DIEPMSK));
4865
4866 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4867 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4868
4869 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4870 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4871
4872 /* show periodic fifo settings */
4873
4874 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4875 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4876 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4877 val >> FIFOSIZE_DEPTH_SHIFT,
4878 val & FIFOSIZE_STARTADDR_MASK);
4879 }
4880
4881 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4882 dev_info(dev,
4883 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4884 dwc2_readl(hsotg, DIEPCTL(idx)),
4885 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4886 dwc2_readl(hsotg, DIEPDMA(idx)));
4887
4888 val = dwc2_readl(hsotg, DOEPCTL(idx));
4889 dev_info(dev,
4890 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4891 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4892 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4893 dwc2_readl(hsotg, DOEPDMA(idx)));
4894 }
4895
4896 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4897 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4898#endif
4899}
4900
4901/**
4902 * dwc2_gadget_init - init function for gadget
4903 * @hsotg: Programming view of the DWC_otg controller
4904 *
4905 */
4906int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4907{
4908 struct device *dev = hsotg->dev;
4909 int epnum;
4910 int ret;
4911
4912 /* Dump fifo information */
4913 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4914 hsotg->params.g_np_tx_fifo_size);
4915 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4916
4917 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4918 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4919 hsotg->gadget.name = dev_name(dev);
4920 hsotg->remote_wakeup_allowed = 0;
4921
4922 if (hsotg->params.lpm)
4923 hsotg->gadget.lpm_capable = true;
4924
4925 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4926 hsotg->gadget.is_otg = 1;
4927 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4928 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4929
4930 ret = dwc2_hsotg_hw_cfg(hsotg);
4931 if (ret) {
4932 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4933 return ret;
4934 }
4935
4936 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4937 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4938 if (!hsotg->ctrl_buff)
4939 return -ENOMEM;
4940
4941 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4942 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4943 if (!hsotg->ep0_buff)
4944 return -ENOMEM;
4945
4946 if (using_desc_dma(hsotg)) {
4947 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4948 if (ret < 0)
4949 return ret;
4950 }
4951
4952 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
4953 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
4954 if (ret < 0) {
4955 dev_err(dev, "cannot claim IRQ for gadget\n");
4956 return ret;
4957 }
4958
4959 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4960
4961 if (hsotg->num_of_eps == 0) {
4962 dev_err(dev, "wrong number of EPs (zero)\n");
4963 return -EINVAL;
4964 }
4965
4966 /* setup endpoint information */
4967
4968 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4969 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4970
4971 /* allocate EP0 request */
4972
4973 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
4974 GFP_KERNEL);
4975 if (!hsotg->ctrl_req) {
4976 dev_err(dev, "failed to allocate ctrl req\n");
4977 return -ENOMEM;
4978 }
4979
4980 /* initialise the endpoints now the core has been initialised */
4981 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4982 if (hsotg->eps_in[epnum])
4983 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4984 epnum, 1);
4985 if (hsotg->eps_out[epnum])
4986 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
4987 epnum, 0);
4988 }
4989
4990 dwc2_hsotg_dump(hsotg);
4991
4992 return 0;
4993}
4994
4995/**
4996 * dwc2_hsotg_remove - remove function for hsotg driver
4997 * @hsotg: Programming view of the DWC_otg controller
4998 *
4999 */
5000int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
5001{
5002 usb_del_gadget_udc(&hsotg->gadget);
5003 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
5004
5005 return 0;
5006}
5007
5008int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
5009{
5010 unsigned long flags;
5011
5012 if (hsotg->lx_state != DWC2_L0)
5013 return 0;
5014
5015 if (hsotg->driver) {
5016 int ep;
5017
5018 dev_info(hsotg->dev, "suspending usb gadget %s\n",
5019 hsotg->driver->driver.name);
5020
5021 spin_lock_irqsave(&hsotg->lock, flags);
5022 if (hsotg->enabled)
5023 dwc2_hsotg_core_disconnect(hsotg);
5024 dwc2_hsotg_disconnect(hsotg);
5025 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
5026 spin_unlock_irqrestore(&hsotg->lock, flags);
5027
5028 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
5029 if (hsotg->eps_in[ep])
5030 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
5031 if (hsotg->eps_out[ep])
5032 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
5033 }
5034 }
5035
5036 return 0;
5037}
5038
5039int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
5040{
5041 unsigned long flags;
5042
5043 if (hsotg->lx_state == DWC2_L2)
5044 return 0;
5045
5046 if (hsotg->driver) {
5047 dev_info(hsotg->dev, "resuming usb gadget %s\n",
5048 hsotg->driver->driver.name);
5049
5050 spin_lock_irqsave(&hsotg->lock, flags);
5051 dwc2_hsotg_core_init_disconnected(hsotg, false);
5052 if (hsotg->enabled) {
5053 /* Enable ACG feature in device mode,if supported */
5054 dwc2_enable_acg(hsotg);
5055 dwc2_hsotg_core_connect(hsotg);
5056 }
5057 spin_unlock_irqrestore(&hsotg->lock, flags);
5058 }
5059
5060 return 0;
5061}
5062
5063/**
5064 * dwc2_backup_device_registers() - Backup controller device registers.
5065 * When suspending usb bus, registers needs to be backuped
5066 * if controller power is disabled once suspended.
5067 *
5068 * @hsotg: Programming view of the DWC_otg controller
5069 */
5070int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
5071{
5072 struct dwc2_dregs_backup *dr;
5073 int i;
5074
5075 dev_dbg(hsotg->dev, "%s\n", __func__);
5076
5077 /* Backup dev regs */
5078 dr = &hsotg->dr_backup;
5079
5080 dr->dcfg = dwc2_readl(hsotg, DCFG);
5081 dr->dctl = dwc2_readl(hsotg, DCTL);
5082 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
5083 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
5084 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
5085
5086 for (i = 0; i < hsotg->num_of_eps; i++) {
5087 /* Backup IN EPs */
5088 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
5089
5090 /* Ensure DATA PID is correctly configured */
5091 if (dr->diepctl[i] & DXEPCTL_DPID)
5092 dr->diepctl[i] |= DXEPCTL_SETD1PID;
5093 else
5094 dr->diepctl[i] |= DXEPCTL_SETD0PID;
5095
5096 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
5097 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
5098
5099 /* Backup OUT EPs */
5100 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
5101
5102 /* Ensure DATA PID is correctly configured */
5103 if (dr->doepctl[i] & DXEPCTL_DPID)
5104 dr->doepctl[i] |= DXEPCTL_SETD1PID;
5105 else
5106 dr->doepctl[i] |= DXEPCTL_SETD0PID;
5107
5108 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
5109 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
5110 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5111 }
5112 dr->valid = true;
5113 return 0;
5114}
5115
5116/**
5117 * dwc2_restore_device_registers() - Restore controller device registers.
5118 * When resuming usb bus, device registers needs to be restored
5119 * if controller power were disabled.
5120 *
5121 * @hsotg: Programming view of the DWC_otg controller
5122 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
5123 *
5124 * Return: 0 if successful, negative error code otherwise
5125 */
5126int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5127{
5128 struct dwc2_dregs_backup *dr;
5129 int i;
5130
5131 dev_dbg(hsotg->dev, "%s\n", __func__);
5132
5133 /* Restore dev regs */
5134 dr = &hsotg->dr_backup;
5135 if (!dr->valid) {
5136 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5137 __func__);
5138 return -EINVAL;
5139 }
5140 dr->valid = false;
5141
5142 if (!remote_wakeup)
5143 dwc2_writel(hsotg, dr->dctl, DCTL);
5144
5145 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5146 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5147 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5148
5149 for (i = 0; i < hsotg->num_of_eps; i++) {
5150 /* Restore IN EPs */
5151 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5152 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5153 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5154 /** WA for enabled EPx's IN in DDMA mode. On entering to
5155 * hibernation wrong value read and saved from DIEPDMAx,
5156 * as result BNA interrupt asserted on hibernation exit
5157 * by restoring from saved area.
5158 */
5159 if (hsotg->params.g_dma_desc &&
5160 (dr->diepctl[i] & DXEPCTL_EPENA))
5161 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5162 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5163 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5164 /* Restore OUT EPs */
5165 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5166 /* WA for enabled EPx's OUT in DDMA mode. On entering to
5167 * hibernation wrong value read and saved from DOEPDMAx,
5168 * as result BNA interrupt asserted on hibernation exit
5169 * by restoring from saved area.
5170 */
5171 if (hsotg->params.g_dma_desc &&
5172 (dr->doepctl[i] & DXEPCTL_EPENA))
5173 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5174 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5175 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5176 }
5177
5178 return 0;
5179}
5180
5181/**
5182 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
5183 *
5184 * @hsotg: Programming view of DWC_otg controller
5185 *
5186 */
5187void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5188{
5189 u32 val;
5190
5191 if (!hsotg->params.lpm)
5192 return;
5193
5194 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
5195 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5196 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5197 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5198 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5199 val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5200 val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
5201 dwc2_writel(hsotg, val, GLPMCFG);
5202 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5203
5204 /* Unmask WKUP_ALERT Interrupt */
5205 if (hsotg->params.service_interval)
5206 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5207}
5208
5209/**
5210 * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
5211 *
5212 * @hsotg: Programming view of DWC_otg controller
5213 *
5214 */
5215void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5216{
5217 u32 val = 0;
5218
5219 val |= GREFCLK_REF_CLK_MODE;
5220 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5221 val |= hsotg->params.sof_cnt_wkup_alert <<
5222 GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5223
5224 dwc2_writel(hsotg, val, GREFCLK);
5225 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5226}
5227
5228/**
5229 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
5230 *
5231 * @hsotg: Programming view of the DWC_otg controller
5232 *
5233 * Return non-zero if failed to enter to hibernation.
5234 */
5235int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5236{
5237 u32 gpwrdn;
5238 int ret = 0;
5239
5240 /* Change to L2(suspend) state */
5241 hsotg->lx_state = DWC2_L2;
5242 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5243 ret = dwc2_backup_global_registers(hsotg);
5244 if (ret) {
5245 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5246 __func__);
5247 return ret;
5248 }
5249 ret = dwc2_backup_device_registers(hsotg);
5250 if (ret) {
5251 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5252 __func__);
5253 return ret;
5254 }
5255
5256 gpwrdn = GPWRDN_PWRDNRSTN;
5257 gpwrdn |= GPWRDN_PMUACTV;
5258 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5259 udelay(10);
5260
5261 /* Set flag to indicate that we are in hibernation */
5262 hsotg->hibernated = 1;
5263
5264 /* Enable interrupts from wake up logic */
5265 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5266 gpwrdn |= GPWRDN_PMUINTSEL;
5267 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5268 udelay(10);
5269
5270 /* Unmask device mode interrupts in GPWRDN */
5271 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5272 gpwrdn |= GPWRDN_RST_DET_MSK;
5273 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5274 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5275 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5276 udelay(10);
5277
5278 /* Enable Power Down Clamp */
5279 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5280 gpwrdn |= GPWRDN_PWRDNCLMP;
5281 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5282 udelay(10);
5283
5284 /* Switch off VDD */
5285 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5286 gpwrdn |= GPWRDN_PWRDNSWTCH;
5287 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5288 udelay(10);
5289
5290 /* Save gpwrdn register for further usage if stschng interrupt */
5291 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5292 dev_dbg(hsotg->dev, "Hibernation completed\n");
5293
5294 return ret;
5295}
5296
5297/**
5298 * dwc2_gadget_exit_hibernation()
5299 * This function is for exiting from Device mode hibernation by host initiated
5300 * resume/reset and device initiated remote-wakeup.
5301 *
5302 * @hsotg: Programming view of the DWC_otg controller
5303 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5304 * @reset: indicates whether resume is initiated by Reset.
5305 *
5306 * Return non-zero if failed to exit from hibernation.
5307 */
5308int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5309 int rem_wakeup, int reset)
5310{
5311 u32 pcgcctl;
5312 u32 gpwrdn;
5313 u32 dctl;
5314 int ret = 0;
5315 struct dwc2_gregs_backup *gr;
5316 struct dwc2_dregs_backup *dr;
5317
5318 gr = &hsotg->gr_backup;
5319 dr = &hsotg->dr_backup;
5320
5321 if (!hsotg->hibernated) {
5322 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5323 return 1;
5324 }
5325 dev_dbg(hsotg->dev,
5326 "%s: called with rem_wakeup = %d reset = %d\n",
5327 __func__, rem_wakeup, reset);
5328
5329 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5330
5331 if (!reset) {
5332 /* Clear all pending interupts */
5333 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5334 }
5335
5336 /* De-assert Restore */
5337 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5338 gpwrdn &= ~GPWRDN_RESTORE;
5339 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5340 udelay(10);
5341
5342 if (!rem_wakeup) {
5343 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5344 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5345 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5346 }
5347
5348 /* Restore GUSBCFG, DCFG and DCTL */
5349 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5350 dwc2_writel(hsotg, dr->dcfg, DCFG);
5351 dwc2_writel(hsotg, dr->dctl, DCTL);
5352
5353 /* On USB Reset, reset device address to zero */
5354 if (reset)
5355 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
5356
5357 /* De-assert Wakeup Logic */
5358 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5359 gpwrdn &= ~GPWRDN_PMUACTV;
5360 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5361
5362 if (rem_wakeup) {
5363 udelay(10);
5364 /* Start Remote Wakeup Signaling */
5365 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5366 } else {
5367 udelay(50);
5368 /* Set Device programming done bit */
5369 dctl = dwc2_readl(hsotg, DCTL);
5370 dctl |= DCTL_PWRONPRGDONE;
5371 dwc2_writel(hsotg, dctl, DCTL);
5372 }
5373 /* Wait for interrupts which must be cleared */
5374 mdelay(2);
5375 /* Clear all pending interupts */
5376 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5377
5378 /* Restore global registers */
5379 ret = dwc2_restore_global_registers(hsotg);
5380 if (ret) {
5381 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5382 __func__);
5383 return ret;
5384 }
5385
5386 /* Restore device registers */
5387 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5388 if (ret) {
5389 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5390 __func__);
5391 return ret;
5392 }
5393
5394 if (rem_wakeup) {
5395 mdelay(10);
5396 dctl = dwc2_readl(hsotg, DCTL);
5397 dctl &= ~DCTL_RMTWKUPSIG;
5398 dwc2_writel(hsotg, dctl, DCTL);
5399 }
5400
5401 hsotg->hibernated = 0;
5402 hsotg->lx_state = DWC2_L0;
5403 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
5404
5405 return ret;
5406}
5407
5408/**
5409 * dwc2_gadget_enter_partial_power_down() - Put controller in partial
5410 * power down.
5411 *
5412 * @hsotg: Programming view of the DWC_otg controller
5413 *
5414 * Return: non-zero if failed to enter device partial power down.
5415 *
5416 * This function is for entering device mode partial power down.
5417 */
5418int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
5419{
5420 u32 pcgcctl;
5421 int ret = 0;
5422
5423 dev_dbg(hsotg->dev, "Entering device partial power down started.\n");
5424
5425 /* Backup all registers */
5426 ret = dwc2_backup_global_registers(hsotg);
5427 if (ret) {
5428 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5429 __func__);
5430 return ret;
5431 }
5432
5433 ret = dwc2_backup_device_registers(hsotg);
5434 if (ret) {
5435 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5436 __func__);
5437 return ret;
5438 }
5439
5440 /*
5441 * Clear any pending interrupts since dwc2 will not be able to
5442 * clear them after entering partial_power_down.
5443 */
5444 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5445
5446 /* Put the controller in low power state */
5447 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5448
5449 pcgcctl |= PCGCTL_PWRCLMP;
5450 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5451 udelay(5);
5452
5453 pcgcctl |= PCGCTL_RSTPDWNMODULE;
5454 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5455 udelay(5);
5456
5457 pcgcctl |= PCGCTL_STOPPCLK;
5458 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5459
5460 /* Set in_ppd flag to 1 as here core enters suspend. */
5461 hsotg->in_ppd = 1;
5462 hsotg->lx_state = DWC2_L2;
5463
5464 dev_dbg(hsotg->dev, "Entering device partial power down completed.\n");
5465
5466 return ret;
5467}
5468
5469/*
5470 * dwc2_gadget_exit_partial_power_down() - Exit controller from device partial
5471 * power down.
5472 *
5473 * @hsotg: Programming view of the DWC_otg controller
5474 * @restore: indicates whether need to restore the registers or not.
5475 *
5476 * Return: non-zero if failed to exit device partial power down.
5477 *
5478 * This function is for exiting from device mode partial power down.
5479 */
5480int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
5481 bool restore)
5482{
5483 u32 pcgcctl;
5484 u32 dctl;
5485 struct dwc2_dregs_backup *dr;
5486 int ret = 0;
5487
5488 dr = &hsotg->dr_backup;
5489
5490 dev_dbg(hsotg->dev, "Exiting device partial Power Down started.\n");
5491
5492 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5493 pcgcctl &= ~PCGCTL_STOPPCLK;
5494 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5495
5496 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5497 pcgcctl &= ~PCGCTL_PWRCLMP;
5498 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5499
5500 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5501 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5502 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5503
5504 udelay(100);
5505 if (restore) {
5506 ret = dwc2_restore_global_registers(hsotg);
5507 if (ret) {
5508 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5509 __func__);
5510 return ret;
5511 }
5512 /* Restore DCFG */
5513 dwc2_writel(hsotg, dr->dcfg, DCFG);
5514
5515 ret = dwc2_restore_device_registers(hsotg, 0);
5516 if (ret) {
5517 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5518 __func__);
5519 return ret;
5520 }
5521 }
5522
5523 /* Set the Power-On Programming done bit */
5524 dctl = dwc2_readl(hsotg, DCTL);
5525 dctl |= DCTL_PWRONPRGDONE;
5526 dwc2_writel(hsotg, dctl, DCTL);
5527
5528 /* Set in_ppd flag to 0 as here core exits from suspend. */
5529 hsotg->in_ppd = 0;
5530 hsotg->lx_state = DWC2_L0;
5531
5532 dev_dbg(hsotg->dev, "Exiting device partial Power Down completed.\n");
5533 return ret;
5534}
5535
5536/**
5537 * dwc2_gadget_enter_clock_gating() - Put controller in clock gating.
5538 *
5539 * @hsotg: Programming view of the DWC_otg controller
5540 *
5541 * Return: non-zero if failed to enter device partial power down.
5542 *
5543 * This function is for entering device mode clock gating.
5544 */
5545void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg)
5546{
5547 u32 pcgctl;
5548
5549 dev_dbg(hsotg->dev, "Entering device clock gating.\n");
5550
5551 /* Set the Phy Clock bit as suspend is received. */
5552 pcgctl = dwc2_readl(hsotg, PCGCTL);
5553 pcgctl |= PCGCTL_STOPPCLK;
5554 dwc2_writel(hsotg, pcgctl, PCGCTL);
5555 udelay(5);
5556
5557 /* Set the Gate hclk as suspend is received. */
5558 pcgctl = dwc2_readl(hsotg, PCGCTL);
5559 pcgctl |= PCGCTL_GATEHCLK;
5560 dwc2_writel(hsotg, pcgctl, PCGCTL);
5561 udelay(5);
5562
5563 hsotg->lx_state = DWC2_L2;
5564 hsotg->bus_suspended = true;
5565}
5566
5567/*
5568 * dwc2_gadget_exit_clock_gating() - Exit controller from device clock gating.
5569 *
5570 * @hsotg: Programming view of the DWC_otg controller
5571 * @rem_wakeup: indicates whether remote wake up is enabled.
5572 *
5573 * This function is for exiting from device mode clock gating.
5574 */
5575void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup)
5576{
5577 u32 pcgctl;
5578 u32 dctl;
5579
5580 dev_dbg(hsotg->dev, "Exiting device clock gating.\n");
5581
5582 /* Clear the Gate hclk. */
5583 pcgctl = dwc2_readl(hsotg, PCGCTL);
5584 pcgctl &= ~PCGCTL_GATEHCLK;
5585 dwc2_writel(hsotg, pcgctl, PCGCTL);
5586 udelay(5);
5587
5588 /* Phy Clock bit. */
5589 pcgctl = dwc2_readl(hsotg, PCGCTL);
5590 pcgctl &= ~PCGCTL_STOPPCLK;
5591 dwc2_writel(hsotg, pcgctl, PCGCTL);
5592 udelay(5);
5593
5594 if (rem_wakeup) {
5595 /* Set Remote Wakeup Signaling */
5596 dctl = dwc2_readl(hsotg, DCTL);
5597 dctl |= DCTL_RMTWKUPSIG;
5598 dwc2_writel(hsotg, dctl, DCTL);
5599 }
5600
5601 /* Change to L0 state */
5602 call_gadget(hsotg, resume);
5603 hsotg->lx_state = DWC2_L0;
5604 hsotg->bus_suspended = false;
5605}