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1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __MSM_DRV_H__
19#define __MSM_DRV_H__
20
21#include <linux/kernel.h>
22#include <linux/clk.h>
23#include <linux/cpufreq.h>
24#include <linux/module.h>
25#include <linux/component.h>
26#include <linux/platform_device.h>
27#include <linux/pm.h>
28#include <linux/pm_runtime.h>
29#include <linux/slab.h>
30#include <linux/list.h>
31#include <linux/iommu.h>
32#include <linux/types.h>
33#include <linux/of_graph.h>
34#include <linux/of_device.h>
35#include <asm/sizes.h>
36
37#include <drm/drmP.h>
38#include <drm/drm_atomic.h>
39#include <drm/drm_atomic_helper.h>
40#include <drm/drm_crtc_helper.h>
41#include <drm/drm_plane_helper.h>
42#include <drm/drm_fb_helper.h>
43#include <drm/msm_drm.h>
44#include <drm/drm_gem.h>
45
46struct msm_kms;
47struct msm_gpu;
48struct msm_mmu;
49struct msm_rd_state;
50struct msm_perf_state;
51struct msm_gem_submit;
52
53#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */
54
55struct msm_file_private {
56 /* currently we don't do anything useful with this.. but when
57 * per-context address spaces are supported we'd keep track of
58 * the context's page-tables here.
59 */
60 int dummy;
61};
62
63enum msm_mdp_plane_property {
64 PLANE_PROP_ZPOS,
65 PLANE_PROP_ALPHA,
66 PLANE_PROP_PREMULTIPLIED,
67 PLANE_PROP_MAX_NUM
68};
69
70struct msm_vblank_ctrl {
71 struct work_struct work;
72 struct list_head event_list;
73 spinlock_t lock;
74};
75
76struct msm_drm_private {
77
78 struct msm_kms *kms;
79
80 /* subordinate devices, if present: */
81 struct platform_device *gpu_pdev;
82
83 /* possibly this should be in the kms component, but it is
84 * shared by both mdp4 and mdp5..
85 */
86 struct hdmi *hdmi;
87
88 /* eDP is for mdp5 only, but kms has not been created
89 * when edp_bind() and edp_init() are called. Here is the only
90 * place to keep the edp instance.
91 */
92 struct msm_edp *edp;
93
94 /* DSI is shared by mdp4 and mdp5 */
95 struct msm_dsi *dsi[2];
96
97 /* when we have more than one 'msm_gpu' these need to be an array: */
98 struct msm_gpu *gpu;
99 struct msm_file_private *lastctx;
100
101 struct drm_fb_helper *fbdev;
102
103 uint32_t next_fence, completed_fence;
104 wait_queue_head_t fence_event;
105
106 struct msm_rd_state *rd;
107 struct msm_perf_state *perf;
108
109 /* list of GEM objects: */
110 struct list_head inactive_list;
111
112 struct workqueue_struct *wq;
113
114 /* callbacks deferred until bo is inactive: */
115 struct list_head fence_cbs;
116
117 /* crtcs pending async atomic updates: */
118 uint32_t pending_crtcs;
119 wait_queue_head_t pending_crtcs_event;
120
121 /* registered MMUs: */
122 unsigned int num_mmus;
123 struct msm_mmu *mmus[NUM_DOMAINS];
124
125 unsigned int num_planes;
126 struct drm_plane *planes[8];
127
128 unsigned int num_crtcs;
129 struct drm_crtc *crtcs[8];
130
131 unsigned int num_encoders;
132 struct drm_encoder *encoders[8];
133
134 unsigned int num_bridges;
135 struct drm_bridge *bridges[8];
136
137 unsigned int num_connectors;
138 struct drm_connector *connectors[8];
139
140 /* Properties */
141 struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
142
143 /* VRAM carveout, used when no IOMMU: */
144 struct {
145 unsigned long size;
146 dma_addr_t paddr;
147 /* NOTE: mm managed at the page level, size is in # of pages
148 * and position mm_node->start is in # of pages:
149 */
150 struct drm_mm mm;
151 } vram;
152
153 struct msm_vblank_ctrl vblank_ctrl;
154};
155
156struct msm_format {
157 uint32_t pixel_format;
158};
159
160/* callback from wq once fence has passed: */
161struct msm_fence_cb {
162 struct work_struct work;
163 uint32_t fence;
164 void (*func)(struct msm_fence_cb *cb);
165};
166
167void __msm_fence_worker(struct work_struct *work);
168
169#define INIT_FENCE_CB(_cb, _func) do { \
170 INIT_WORK(&(_cb)->work, __msm_fence_worker); \
171 (_cb)->func = _func; \
172 } while (0)
173
174int msm_atomic_check(struct drm_device *dev,
175 struct drm_atomic_state *state);
176int msm_atomic_commit(struct drm_device *dev,
177 struct drm_atomic_state *state, bool async);
178
179int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
180
181int msm_wait_fence(struct drm_device *dev, uint32_t fence,
182 ktime_t *timeout, bool interruptible);
183int msm_queue_fence_cb(struct drm_device *dev,
184 struct msm_fence_cb *cb, uint32_t fence);
185void msm_update_fence(struct drm_device *dev, uint32_t fence);
186
187int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
188 struct drm_file *file);
189
190int msm_gem_mmap_obj(struct drm_gem_object *obj,
191 struct vm_area_struct *vma);
192int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
193int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
194uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
195int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
196 uint32_t *iova);
197int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova);
198uint32_t msm_gem_iova(struct drm_gem_object *obj, int id);
199struct page **msm_gem_get_pages(struct drm_gem_object *obj);
200void msm_gem_put_pages(struct drm_gem_object *obj);
201void msm_gem_put_iova(struct drm_gem_object *obj, int id);
202int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
203 struct drm_mode_create_dumb *args);
204int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
205 uint32_t handle, uint64_t *offset);
206struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
207void *msm_gem_prime_vmap(struct drm_gem_object *obj);
208void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
209int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
210struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
211 struct dma_buf_attachment *attach, struct sg_table *sg);
212int msm_gem_prime_pin(struct drm_gem_object *obj);
213void msm_gem_prime_unpin(struct drm_gem_object *obj);
214void *msm_gem_vaddr_locked(struct drm_gem_object *obj);
215void *msm_gem_vaddr(struct drm_gem_object *obj);
216int msm_gem_queue_inactive_cb(struct drm_gem_object *obj,
217 struct msm_fence_cb *cb);
218void msm_gem_move_to_active(struct drm_gem_object *obj,
219 struct msm_gpu *gpu, bool write, uint32_t fence);
220void msm_gem_move_to_inactive(struct drm_gem_object *obj);
221int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
222 ktime_t *timeout);
223int msm_gem_cpu_fini(struct drm_gem_object *obj);
224void msm_gem_free_object(struct drm_gem_object *obj);
225int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
226 uint32_t size, uint32_t flags, uint32_t *handle);
227struct drm_gem_object *msm_gem_new(struct drm_device *dev,
228 uint32_t size, uint32_t flags);
229struct drm_gem_object *msm_gem_import(struct drm_device *dev,
230 uint32_t size, struct sg_table *sgt);
231
232int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id);
233void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id);
234uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane);
235struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
236const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
237struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
238 const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
239struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
240 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
241
242struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
243void msm_fbdev_free(struct drm_device *dev);
244
245struct hdmi;
246int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
247 struct drm_encoder *encoder);
248void __init msm_hdmi_register(void);
249void __exit msm_hdmi_unregister(void);
250
251struct msm_edp;
252void __init msm_edp_register(void);
253void __exit msm_edp_unregister(void);
254int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
255 struct drm_encoder *encoder);
256
257struct msm_dsi;
258enum msm_dsi_encoder_id {
259 MSM_DSI_VIDEO_ENCODER_ID = 0,
260 MSM_DSI_CMD_ENCODER_ID = 1,
261 MSM_DSI_ENCODER_NUM = 2
262};
263#ifdef CONFIG_DRM_MSM_DSI
264void __init msm_dsi_register(void);
265void __exit msm_dsi_unregister(void);
266int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
267 struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]);
268#else
269static inline void __init msm_dsi_register(void)
270{
271}
272static inline void __exit msm_dsi_unregister(void)
273{
274}
275static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
276 struct drm_device *dev,
277 struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM])
278{
279 return -EINVAL;
280}
281#endif
282
283#ifdef CONFIG_DEBUG_FS
284void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
285void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
286void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
287int msm_debugfs_late_init(struct drm_device *dev);
288int msm_rd_debugfs_init(struct drm_minor *minor);
289void msm_rd_debugfs_cleanup(struct drm_minor *minor);
290void msm_rd_dump_submit(struct msm_gem_submit *submit);
291int msm_perf_debugfs_init(struct drm_minor *minor);
292void msm_perf_debugfs_cleanup(struct drm_minor *minor);
293#else
294static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
295static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {}
296#endif
297
298void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
299 const char *dbgname);
300void msm_writel(u32 data, void __iomem *addr);
301u32 msm_readl(const void __iomem *addr);
302
303#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
304#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
305
306static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
307{
308 struct msm_drm_private *priv = dev->dev_private;
309 return priv->completed_fence >= fence;
310}
311
312static inline int align_pitch(int width, int bpp)
313{
314 int bytespp = (bpp + 7) / 8;
315 /* adreno needs pitch aligned to 32 pixels: */
316 return bytespp * ALIGN(width, 32);
317}
318
319/* for the generated headers: */
320#define INVALID_IDX(idx) ({BUG(); 0;})
321#define fui(x) ({BUG(); 0;})
322#define util_float_to_half(x) ({BUG(); 0;})
323
324
325#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
326
327/* for conditionally setting boolean flag(s): */
328#define COND(bool, val) ((bool) ? (val) : 0)
329
330
331#endif /* __MSM_DRV_H__ */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#ifndef __MSM_DRV_H__
9#define __MSM_DRV_H__
10
11#include <linux/kernel.h>
12#include <linux/clk.h>
13#include <linux/cpufreq.h>
14#include <linux/module.h>
15#include <linux/component.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/pm_runtime.h>
19#include <linux/slab.h>
20#include <linux/list.h>
21#include <linux/iommu.h>
22#include <linux/types.h>
23#include <linux/of_graph.h>
24#include <linux/of_device.h>
25#include <linux/sizes.h>
26#include <linux/kthread.h>
27
28#include <drm/drm_atomic.h>
29#include <drm/drm_atomic_helper.h>
30#include <drm/drm_plane_helper.h>
31#include <drm/drm_probe_helper.h>
32#include <drm/drm_fb_helper.h>
33#include <drm/msm_drm.h>
34#include <drm/drm_gem.h>
35
36struct msm_kms;
37struct msm_gpu;
38struct msm_mmu;
39struct msm_mdss;
40struct msm_rd_state;
41struct msm_perf_state;
42struct msm_gem_submit;
43struct msm_fence_context;
44struct msm_gem_address_space;
45struct msm_gem_vma;
46struct msm_disp_state;
47
48#define MAX_CRTCS 8
49#define MAX_PLANES 20
50#define MAX_ENCODERS 8
51#define MAX_BRIDGES 8
52#define MAX_CONNECTORS 8
53
54#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
55
56struct msm_file_private {
57 rwlock_t queuelock;
58 struct list_head submitqueues;
59 int queueid;
60 struct msm_gem_address_space *aspace;
61 struct kref ref;
62 int seqno;
63};
64
65enum msm_mdp_plane_property {
66 PLANE_PROP_ZPOS,
67 PLANE_PROP_ALPHA,
68 PLANE_PROP_PREMULTIPLIED,
69 PLANE_PROP_MAX_NUM
70};
71
72#define MSM_GPU_MAX_RINGS 4
73#define MAX_H_TILES_PER_DISPLAY 2
74
75/**
76 * enum msm_display_caps - features/capabilities supported by displays
77 * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported
78 * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported
79 * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported
80 * @MSM_DISPLAY_CAP_EDID: EDID supported
81 */
82enum msm_display_caps {
83 MSM_DISPLAY_CAP_VID_MODE = BIT(0),
84 MSM_DISPLAY_CAP_CMD_MODE = BIT(1),
85 MSM_DISPLAY_CAP_HOT_PLUG = BIT(2),
86 MSM_DISPLAY_CAP_EDID = BIT(3),
87};
88
89/**
90 * enum msm_event_wait - type of HW events to wait for
91 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
92 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
93 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
94 */
95enum msm_event_wait {
96 MSM_ENC_COMMIT_DONE = 0,
97 MSM_ENC_TX_COMPLETE,
98 MSM_ENC_VBLANK,
99};
100
101/**
102 * struct msm_display_topology - defines a display topology pipeline
103 * @num_lm: number of layer mixers used
104 * @num_enc: number of compression encoder blocks used
105 * @num_intf: number of interfaces the panel is mounted on
106 */
107struct msm_display_topology {
108 u32 num_lm;
109 u32 num_enc;
110 u32 num_intf;
111 u32 num_dspp;
112};
113
114/**
115 * struct msm_display_info - defines display properties
116 * @intf_type: DRM_MODE_ENCODER_ type
117 * @capabilities: Bitmask of display flags
118 * @num_of_h_tiles: Number of horizontal tiles in case of split interface
119 * @h_tile_instance: Controller instance used per tile. Number of elements is
120 * based on num_of_h_tiles
121 * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
122 * used instead of panel TE in cmd mode panels
123 */
124struct msm_display_info {
125 int intf_type;
126 uint32_t capabilities;
127 uint32_t num_of_h_tiles;
128 uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
129 bool is_te_using_watchdog_timer;
130};
131
132/* Commit/Event thread specific structure */
133struct msm_drm_thread {
134 struct drm_device *dev;
135 unsigned int crtc_id;
136 struct kthread_worker *worker;
137};
138
139struct msm_drm_private {
140
141 struct drm_device *dev;
142
143 struct msm_kms *kms;
144
145 /* subordinate devices, if present: */
146 struct platform_device *gpu_pdev;
147
148 /* top level MDSS wrapper device (for MDP5/DPU only) */
149 struct msm_mdss *mdss;
150
151 /* possibly this should be in the kms component, but it is
152 * shared by both mdp4 and mdp5..
153 */
154 struct hdmi *hdmi;
155
156 /* eDP is for mdp5 only, but kms has not been created
157 * when edp_bind() and edp_init() are called. Here is the only
158 * place to keep the edp instance.
159 */
160 struct msm_edp *edp;
161
162 /* DSI is shared by mdp4 and mdp5 */
163 struct msm_dsi *dsi[2];
164
165 struct msm_dp *dp;
166
167 /* when we have more than one 'msm_gpu' these need to be an array: */
168 struct msm_gpu *gpu;
169 struct msm_file_private *lastctx;
170 /* gpu is only set on open(), but we need this info earlier */
171 bool is_a2xx;
172 bool has_cached_coherent;
173
174 struct drm_fb_helper *fbdev;
175
176 struct msm_rd_state *rd; /* debugfs to dump all submits */
177 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
178 struct msm_perf_state *perf;
179
180 /**
181 * List of all GEM objects (mainly for debugfs, protected by obj_lock
182 * (acquire before per GEM object lock)
183 */
184 struct list_head objects;
185 struct mutex obj_lock;
186
187 /**
188 * LRUs of inactive GEM objects. Every bo is either in one of the
189 * inactive lists (depending on whether or not it is shrinkable) or
190 * gpu->active_list (for the gpu it is active on[1]), or transiently
191 * on a temporary list as the shrinker is running.
192 *
193 * Note that inactive_willneed also contains pinned and vmap'd bos,
194 * but the number of pinned-but-not-active objects is small (scanout
195 * buffers, ringbuffer, etc).
196 *
197 * These lists are protected by mm_lock (which should be acquired
198 * before per GEM object lock). One should *not* hold mm_lock in
199 * get_pages()/vmap()/etc paths, as they can trigger the shrinker.
200 *
201 * [1] if someone ever added support for the old 2d cores, there could be
202 * more than one gpu object
203 */
204 struct list_head inactive_willneed; /* inactive + potentially unpin/evictable */
205 struct list_head inactive_dontneed; /* inactive + shrinkable */
206 struct list_head inactive_unpinned; /* inactive + purged or unpinned */
207 long shrinkable_count; /* write access under mm_lock */
208 long evictable_count; /* write access under mm_lock */
209 struct mutex mm_lock;
210
211 struct workqueue_struct *wq;
212
213 unsigned int num_planes;
214 struct drm_plane *planes[MAX_PLANES];
215
216 unsigned int num_crtcs;
217 struct drm_crtc *crtcs[MAX_CRTCS];
218
219 struct msm_drm_thread event_thread[MAX_CRTCS];
220
221 unsigned int num_encoders;
222 struct drm_encoder *encoders[MAX_ENCODERS];
223
224 unsigned int num_bridges;
225 struct drm_bridge *bridges[MAX_BRIDGES];
226
227 unsigned int num_connectors;
228 struct drm_connector *connectors[MAX_CONNECTORS];
229
230 /* Properties */
231 struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
232
233 /* VRAM carveout, used when no IOMMU: */
234 struct {
235 unsigned long size;
236 dma_addr_t paddr;
237 /* NOTE: mm managed at the page level, size is in # of pages
238 * and position mm_node->start is in # of pages:
239 */
240 struct drm_mm mm;
241 spinlock_t lock; /* Protects drm_mm node allocation/removal */
242 } vram;
243
244 struct notifier_block vmap_notifier;
245 struct shrinker shrinker;
246
247 struct drm_atomic_state *pm_state;
248
249 /* For hang detection, in ms */
250 unsigned int hangcheck_period;
251};
252
253struct msm_format {
254 uint32_t pixel_format;
255};
256
257struct msm_pending_timer;
258
259int msm_atomic_prepare_fb(struct drm_plane *plane,
260 struct drm_plane_state *new_state);
261int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
262 struct msm_kms *kms, int crtc_idx);
263void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer);
264void msm_atomic_commit_tail(struct drm_atomic_state *state);
265struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
266void msm_atomic_state_clear(struct drm_atomic_state *state);
267void msm_atomic_state_free(struct drm_atomic_state *state);
268
269int msm_crtc_enable_vblank(struct drm_crtc *crtc);
270void msm_crtc_disable_vblank(struct drm_crtc *crtc);
271
272int msm_gem_init_vma(struct msm_gem_address_space *aspace,
273 struct msm_gem_vma *vma, int npages,
274 u64 range_start, u64 range_end);
275void msm_gem_purge_vma(struct msm_gem_address_space *aspace,
276 struct msm_gem_vma *vma);
277void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
278 struct msm_gem_vma *vma);
279int msm_gem_map_vma(struct msm_gem_address_space *aspace,
280 struct msm_gem_vma *vma, int prot,
281 struct sg_table *sgt, int npages);
282void msm_gem_close_vma(struct msm_gem_address_space *aspace,
283 struct msm_gem_vma *vma);
284
285
286struct msm_gem_address_space *
287msm_gem_address_space_get(struct msm_gem_address_space *aspace);
288
289void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
290
291struct msm_gem_address_space *
292msm_gem_address_space_create(struct msm_mmu *mmu, const char *name,
293 u64 va_start, u64 size);
294
295int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
296void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
297
298bool msm_use_mmu(struct drm_device *dev);
299
300int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
301 struct drm_file *file);
302
303#ifdef CONFIG_DEBUG_FS
304unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan);
305#endif
306
307void msm_gem_shrinker_init(struct drm_device *dev);
308void msm_gem_shrinker_cleanup(struct drm_device *dev);
309
310struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
311int msm_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
312void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map);
313int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
314struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
315 struct dma_buf_attachment *attach, struct sg_table *sg);
316int msm_gem_prime_pin(struct drm_gem_object *obj);
317void msm_gem_prime_unpin(struct drm_gem_object *obj);
318
319int msm_framebuffer_prepare(struct drm_framebuffer *fb,
320 struct msm_gem_address_space *aspace);
321void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
322 struct msm_gem_address_space *aspace);
323uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
324 struct msm_gem_address_space *aspace, int plane);
325struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
326const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
327struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
328 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
329struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
330 int w, int h, int p, uint32_t format);
331
332struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
333void msm_fbdev_free(struct drm_device *dev);
334
335struct hdmi;
336int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
337 struct drm_encoder *encoder);
338void __init msm_hdmi_register(void);
339void __exit msm_hdmi_unregister(void);
340
341struct msm_edp;
342void __init msm_edp_register(void);
343void __exit msm_edp_unregister(void);
344int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
345 struct drm_encoder *encoder);
346
347struct msm_dsi;
348#ifdef CONFIG_DRM_MSM_DSI
349void __init msm_dsi_register(void);
350void __exit msm_dsi_unregister(void);
351int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
352 struct drm_encoder *encoder);
353void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi);
354
355#else
356static inline void __init msm_dsi_register(void)
357{
358}
359static inline void __exit msm_dsi_unregister(void)
360{
361}
362static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
363 struct drm_device *dev,
364 struct drm_encoder *encoder)
365{
366 return -EINVAL;
367}
368static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi)
369{
370}
371
372#endif
373
374#ifdef CONFIG_DRM_MSM_DP
375int __init msm_dp_register(void);
376void __exit msm_dp_unregister(void);
377int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
378 struct drm_encoder *encoder);
379int msm_dp_display_enable(struct msm_dp *dp, struct drm_encoder *encoder);
380int msm_dp_display_disable(struct msm_dp *dp, struct drm_encoder *encoder);
381int msm_dp_display_pre_disable(struct msm_dp *dp, struct drm_encoder *encoder);
382void msm_dp_display_mode_set(struct msm_dp *dp, struct drm_encoder *encoder,
383 struct drm_display_mode *mode,
384 struct drm_display_mode *adjusted_mode);
385void msm_dp_irq_postinstall(struct msm_dp *dp_display);
386void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display);
387
388void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor);
389
390#else
391static inline int __init msm_dp_register(void)
392{
393 return -EINVAL;
394}
395static inline void __exit msm_dp_unregister(void)
396{
397}
398static inline int msm_dp_modeset_init(struct msm_dp *dp_display,
399 struct drm_device *dev,
400 struct drm_encoder *encoder)
401{
402 return -EINVAL;
403}
404static inline int msm_dp_display_enable(struct msm_dp *dp,
405 struct drm_encoder *encoder)
406{
407 return -EINVAL;
408}
409static inline int msm_dp_display_disable(struct msm_dp *dp,
410 struct drm_encoder *encoder)
411{
412 return -EINVAL;
413}
414static inline int msm_dp_display_pre_disable(struct msm_dp *dp,
415 struct drm_encoder *encoder)
416{
417 return -EINVAL;
418}
419static inline void msm_dp_display_mode_set(struct msm_dp *dp,
420 struct drm_encoder *encoder,
421 struct drm_display_mode *mode,
422 struct drm_display_mode *adjusted_mode)
423{
424}
425
426static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display)
427{
428}
429
430static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display)
431{
432}
433
434static inline void msm_dp_debugfs_init(struct msm_dp *dp_display,
435 struct drm_minor *minor)
436{
437}
438
439#endif
440
441void __init msm_mdp_register(void);
442void __exit msm_mdp_unregister(void);
443void __init msm_dpu_register(void);
444void __exit msm_dpu_unregister(void);
445
446#ifdef CONFIG_DEBUG_FS
447void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
448int msm_debugfs_late_init(struct drm_device *dev);
449int msm_rd_debugfs_init(struct drm_minor *minor);
450void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
451__printf(3, 4)
452void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
453 const char *fmt, ...);
454int msm_perf_debugfs_init(struct drm_minor *minor);
455void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
456#else
457static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
458__printf(3, 4)
459static inline void msm_rd_dump_submit(struct msm_rd_state *rd,
460 struct msm_gem_submit *submit,
461 const char *fmt, ...) {}
462static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
463static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
464#endif
465
466struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
467
468struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
469 const char *name);
470void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
471 const char *dbgname);
472void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
473 const char *dbgname, phys_addr_t *size);
474void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
475 const char *dbgname);
476void msm_writel(u32 data, void __iomem *addr);
477u32 msm_readl(const void __iomem *addr);
478void msm_rmw(void __iomem *addr, u32 mask, u32 or);
479
480struct msm_gpu_submitqueue;
481int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
482struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx,
483 u32 id);
484int msm_submitqueue_create(struct drm_device *drm,
485 struct msm_file_private *ctx,
486 u32 prio, u32 flags, u32 *id);
487int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx,
488 struct drm_msm_submitqueue_query *args);
489int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
490void msm_submitqueue_close(struct msm_file_private *ctx);
491
492void msm_submitqueue_destroy(struct kref *kref);
493
494static inline void __msm_file_private_destroy(struct kref *kref)
495{
496 struct msm_file_private *ctx = container_of(kref,
497 struct msm_file_private, ref);
498
499 msm_gem_address_space_put(ctx->aspace);
500 kfree(ctx);
501}
502
503static inline void msm_file_private_put(struct msm_file_private *ctx)
504{
505 kref_put(&ctx->ref, __msm_file_private_destroy);
506}
507
508static inline struct msm_file_private *msm_file_private_get(
509 struct msm_file_private *ctx)
510{
511 kref_get(&ctx->ref);
512 return ctx;
513}
514
515#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
516#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
517
518static inline int align_pitch(int width, int bpp)
519{
520 int bytespp = (bpp + 7) / 8;
521 /* adreno needs pitch aligned to 32 pixels: */
522 return bytespp * ALIGN(width, 32);
523}
524
525/* for the generated headers: */
526#define INVALID_IDX(idx) ({BUG(); 0;})
527#define fui(x) ({BUG(); 0;})
528#define _mesa_float_to_half(x) ({BUG(); 0;})
529
530
531#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
532
533/* for conditionally setting boolean flag(s): */
534#define COND(bool, val) ((bool) ? (val) : 0)
535
536static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
537{
538 ktime_t now = ktime_get();
539 s64 remaining_jiffies;
540
541 if (ktime_compare(*timeout, now) < 0) {
542 remaining_jiffies = 0;
543 } else {
544 ktime_t rem = ktime_sub(*timeout, now);
545 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
546 }
547
548 return clamp(remaining_jiffies, 0LL, (s64)INT_MAX);
549}
550
551#endif /* __MSM_DRV_H__ */