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1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __MSM_DRV_H__
19#define __MSM_DRV_H__
20
21#include <linux/kernel.h>
22#include <linux/clk.h>
23#include <linux/cpufreq.h>
24#include <linux/module.h>
25#include <linux/component.h>
26#include <linux/platform_device.h>
27#include <linux/pm.h>
28#include <linux/pm_runtime.h>
29#include <linux/slab.h>
30#include <linux/list.h>
31#include <linux/iommu.h>
32#include <linux/types.h>
33#include <linux/of_graph.h>
34#include <linux/of_device.h>
35#include <asm/sizes.h>
36
37#include <drm/drmP.h>
38#include <drm/drm_atomic.h>
39#include <drm/drm_atomic_helper.h>
40#include <drm/drm_crtc_helper.h>
41#include <drm/drm_plane_helper.h>
42#include <drm/drm_fb_helper.h>
43#include <drm/msm_drm.h>
44#include <drm/drm_gem.h>
45
46struct msm_kms;
47struct msm_gpu;
48struct msm_mmu;
49struct msm_rd_state;
50struct msm_perf_state;
51struct msm_gem_submit;
52
53#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */
54
55struct msm_file_private {
56 /* currently we don't do anything useful with this.. but when
57 * per-context address spaces are supported we'd keep track of
58 * the context's page-tables here.
59 */
60 int dummy;
61};
62
63enum msm_mdp_plane_property {
64 PLANE_PROP_ZPOS,
65 PLANE_PROP_ALPHA,
66 PLANE_PROP_PREMULTIPLIED,
67 PLANE_PROP_MAX_NUM
68};
69
70struct msm_vblank_ctrl {
71 struct work_struct work;
72 struct list_head event_list;
73 spinlock_t lock;
74};
75
76struct msm_drm_private {
77
78 struct msm_kms *kms;
79
80 /* subordinate devices, if present: */
81 struct platform_device *gpu_pdev;
82
83 /* possibly this should be in the kms component, but it is
84 * shared by both mdp4 and mdp5..
85 */
86 struct hdmi *hdmi;
87
88 /* eDP is for mdp5 only, but kms has not been created
89 * when edp_bind() and edp_init() are called. Here is the only
90 * place to keep the edp instance.
91 */
92 struct msm_edp *edp;
93
94 /* DSI is shared by mdp4 and mdp5 */
95 struct msm_dsi *dsi[2];
96
97 /* when we have more than one 'msm_gpu' these need to be an array: */
98 struct msm_gpu *gpu;
99 struct msm_file_private *lastctx;
100
101 struct drm_fb_helper *fbdev;
102
103 uint32_t next_fence, completed_fence;
104 wait_queue_head_t fence_event;
105
106 struct msm_rd_state *rd;
107 struct msm_perf_state *perf;
108
109 /* list of GEM objects: */
110 struct list_head inactive_list;
111
112 struct workqueue_struct *wq;
113
114 /* callbacks deferred until bo is inactive: */
115 struct list_head fence_cbs;
116
117 /* crtcs pending async atomic updates: */
118 uint32_t pending_crtcs;
119 wait_queue_head_t pending_crtcs_event;
120
121 /* registered MMUs: */
122 unsigned int num_mmus;
123 struct msm_mmu *mmus[NUM_DOMAINS];
124
125 unsigned int num_planes;
126 struct drm_plane *planes[8];
127
128 unsigned int num_crtcs;
129 struct drm_crtc *crtcs[8];
130
131 unsigned int num_encoders;
132 struct drm_encoder *encoders[8];
133
134 unsigned int num_bridges;
135 struct drm_bridge *bridges[8];
136
137 unsigned int num_connectors;
138 struct drm_connector *connectors[8];
139
140 /* Properties */
141 struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
142
143 /* VRAM carveout, used when no IOMMU: */
144 struct {
145 unsigned long size;
146 dma_addr_t paddr;
147 /* NOTE: mm managed at the page level, size is in # of pages
148 * and position mm_node->start is in # of pages:
149 */
150 struct drm_mm mm;
151 } vram;
152
153 struct msm_vblank_ctrl vblank_ctrl;
154};
155
156struct msm_format {
157 uint32_t pixel_format;
158};
159
160/* callback from wq once fence has passed: */
161struct msm_fence_cb {
162 struct work_struct work;
163 uint32_t fence;
164 void (*func)(struct msm_fence_cb *cb);
165};
166
167void __msm_fence_worker(struct work_struct *work);
168
169#define INIT_FENCE_CB(_cb, _func) do { \
170 INIT_WORK(&(_cb)->work, __msm_fence_worker); \
171 (_cb)->func = _func; \
172 } while (0)
173
174int msm_atomic_check(struct drm_device *dev,
175 struct drm_atomic_state *state);
176int msm_atomic_commit(struct drm_device *dev,
177 struct drm_atomic_state *state, bool async);
178
179int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
180
181int msm_wait_fence(struct drm_device *dev, uint32_t fence,
182 ktime_t *timeout, bool interruptible);
183int msm_queue_fence_cb(struct drm_device *dev,
184 struct msm_fence_cb *cb, uint32_t fence);
185void msm_update_fence(struct drm_device *dev, uint32_t fence);
186
187int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
188 struct drm_file *file);
189
190int msm_gem_mmap_obj(struct drm_gem_object *obj,
191 struct vm_area_struct *vma);
192int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
193int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
194uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
195int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
196 uint32_t *iova);
197int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova);
198uint32_t msm_gem_iova(struct drm_gem_object *obj, int id);
199struct page **msm_gem_get_pages(struct drm_gem_object *obj);
200void msm_gem_put_pages(struct drm_gem_object *obj);
201void msm_gem_put_iova(struct drm_gem_object *obj, int id);
202int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
203 struct drm_mode_create_dumb *args);
204int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
205 uint32_t handle, uint64_t *offset);
206struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
207void *msm_gem_prime_vmap(struct drm_gem_object *obj);
208void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
209int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
210struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
211 struct dma_buf_attachment *attach, struct sg_table *sg);
212int msm_gem_prime_pin(struct drm_gem_object *obj);
213void msm_gem_prime_unpin(struct drm_gem_object *obj);
214void *msm_gem_vaddr_locked(struct drm_gem_object *obj);
215void *msm_gem_vaddr(struct drm_gem_object *obj);
216int msm_gem_queue_inactive_cb(struct drm_gem_object *obj,
217 struct msm_fence_cb *cb);
218void msm_gem_move_to_active(struct drm_gem_object *obj,
219 struct msm_gpu *gpu, bool write, uint32_t fence);
220void msm_gem_move_to_inactive(struct drm_gem_object *obj);
221int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
222 ktime_t *timeout);
223int msm_gem_cpu_fini(struct drm_gem_object *obj);
224void msm_gem_free_object(struct drm_gem_object *obj);
225int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
226 uint32_t size, uint32_t flags, uint32_t *handle);
227struct drm_gem_object *msm_gem_new(struct drm_device *dev,
228 uint32_t size, uint32_t flags);
229struct drm_gem_object *msm_gem_import(struct drm_device *dev,
230 uint32_t size, struct sg_table *sgt);
231
232int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id);
233void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id);
234uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane);
235struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
236const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
237struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
238 const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
239struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
240 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
241
242struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
243void msm_fbdev_free(struct drm_device *dev);
244
245struct hdmi;
246int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
247 struct drm_encoder *encoder);
248void __init msm_hdmi_register(void);
249void __exit msm_hdmi_unregister(void);
250
251struct msm_edp;
252void __init msm_edp_register(void);
253void __exit msm_edp_unregister(void);
254int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
255 struct drm_encoder *encoder);
256
257struct msm_dsi;
258enum msm_dsi_encoder_id {
259 MSM_DSI_VIDEO_ENCODER_ID = 0,
260 MSM_DSI_CMD_ENCODER_ID = 1,
261 MSM_DSI_ENCODER_NUM = 2
262};
263#ifdef CONFIG_DRM_MSM_DSI
264void __init msm_dsi_register(void);
265void __exit msm_dsi_unregister(void);
266int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
267 struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]);
268#else
269static inline void __init msm_dsi_register(void)
270{
271}
272static inline void __exit msm_dsi_unregister(void)
273{
274}
275static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
276 struct drm_device *dev,
277 struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM])
278{
279 return -EINVAL;
280}
281#endif
282
283#ifdef CONFIG_DEBUG_FS
284void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
285void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
286void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
287int msm_debugfs_late_init(struct drm_device *dev);
288int msm_rd_debugfs_init(struct drm_minor *minor);
289void msm_rd_debugfs_cleanup(struct drm_minor *minor);
290void msm_rd_dump_submit(struct msm_gem_submit *submit);
291int msm_perf_debugfs_init(struct drm_minor *minor);
292void msm_perf_debugfs_cleanup(struct drm_minor *minor);
293#else
294static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
295static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {}
296#endif
297
298void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
299 const char *dbgname);
300void msm_writel(u32 data, void __iomem *addr);
301u32 msm_readl(const void __iomem *addr);
302
303#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
304#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
305
306static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
307{
308 struct msm_drm_private *priv = dev->dev_private;
309 return priv->completed_fence >= fence;
310}
311
312static inline int align_pitch(int width, int bpp)
313{
314 int bytespp = (bpp + 7) / 8;
315 /* adreno needs pitch aligned to 32 pixels: */
316 return bytespp * ALIGN(width, 32);
317}
318
319/* for the generated headers: */
320#define INVALID_IDX(idx) ({BUG(); 0;})
321#define fui(x) ({BUG(); 0;})
322#define util_float_to_half(x) ({BUG(); 0;})
323
324
325#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
326
327/* for conditionally setting boolean flag(s): */
328#define COND(bool, val) ((bool) ? (val) : 0)
329
330
331#endif /* __MSM_DRV_H__ */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#ifndef __MSM_DRV_H__
9#define __MSM_DRV_H__
10
11#include <linux/kernel.h>
12#include <linux/clk.h>
13#include <linux/cpufreq.h>
14#include <linux/devfreq.h>
15#include <linux/module.h>
16#include <linux/component.h>
17#include <linux/platform_device.h>
18#include <linux/pm.h>
19#include <linux/pm_runtime.h>
20#include <linux/slab.h>
21#include <linux/list.h>
22#include <linux/iommu.h>
23#include <linux/types.h>
24#include <linux/of_graph.h>
25#include <linux/of_device.h>
26#include <linux/sizes.h>
27#include <linux/kthread.h>
28
29#include <drm/drm_atomic.h>
30#include <drm/drm_atomic_helper.h>
31#include <drm/drm_probe_helper.h>
32#include <drm/display/drm_dsc.h>
33#include <drm/msm_drm.h>
34#include <drm/drm_gem.h>
35
36extern struct fault_attr fail_gem_alloc;
37extern struct fault_attr fail_gem_iova;
38
39struct drm_fb_helper;
40struct drm_fb_helper_surface_size;
41
42struct msm_kms;
43struct msm_gpu;
44struct msm_mmu;
45struct msm_mdss;
46struct msm_rd_state;
47struct msm_perf_state;
48struct msm_gem_submit;
49struct msm_fence_context;
50struct msm_gem_address_space;
51struct msm_gem_vma;
52struct msm_disp_state;
53
54#define MAX_CRTCS 8
55
56#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
57
58enum msm_dp_controller {
59 MSM_DP_CONTROLLER_0,
60 MSM_DP_CONTROLLER_1,
61 MSM_DP_CONTROLLER_2,
62 MSM_DP_CONTROLLER_3,
63 MSM_DP_CONTROLLER_COUNT,
64};
65
66enum msm_dsi_controller {
67 MSM_DSI_CONTROLLER_0,
68 MSM_DSI_CONTROLLER_1,
69 MSM_DSI_CONTROLLER_COUNT,
70};
71
72#define MSM_GPU_MAX_RINGS 4
73
74/* Commit/Event thread specific structure */
75struct msm_drm_thread {
76 struct drm_device *dev;
77 struct kthread_worker *worker;
78};
79
80struct msm_drm_private {
81
82 struct drm_device *dev;
83
84 struct msm_kms *kms;
85 int (*kms_init)(struct drm_device *dev);
86
87 /* subordinate devices, if present: */
88 struct platform_device *gpu_pdev;
89
90 /* possibly this should be in the kms component, but it is
91 * shared by both mdp4 and mdp5..
92 */
93 struct hdmi *hdmi;
94
95 /* DSI is shared by mdp4 and mdp5 */
96 struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT];
97
98 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT];
99
100 /* when we have more than one 'msm_gpu' these need to be an array: */
101 struct msm_gpu *gpu;
102
103 /* gpu is only set on open(), but we need this info earlier */
104 bool is_a2xx;
105 bool has_cached_coherent;
106
107 struct msm_rd_state *rd; /* debugfs to dump all submits */
108 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
109 struct msm_perf_state *perf;
110
111 /**
112 * total_mem: Total/global amount of memory backing GEM objects.
113 */
114 atomic64_t total_mem;
115
116 /**
117 * List of all GEM objects (mainly for debugfs, protected by obj_lock
118 * (acquire before per GEM object lock)
119 */
120 struct list_head objects;
121 struct mutex obj_lock;
122
123 /**
124 * lru:
125 *
126 * The various LRU's that a GEM object is in at various stages of
127 * it's lifetime. Objects start out in the unbacked LRU. When
128 * pinned (for scannout or permanently mapped GPU buffers, like
129 * ringbuffer, memptr, fw, etc) it moves to the pinned LRU. When
130 * unpinned, it moves into willneed or dontneed LRU depending on
131 * madvise state. When backing pages are evicted (willneed) or
132 * purged (dontneed) it moves back into the unbacked LRU.
133 *
134 * The dontneed LRU is considered by the shrinker for objects
135 * that are candidate for purging, and the willneed LRU is
136 * considered for objects that could be evicted.
137 */
138 struct {
139 /**
140 * unbacked:
141 *
142 * The LRU for GEM objects without backing pages allocated.
143 * This mostly exists so that objects are always is one
144 * LRU.
145 */
146 struct drm_gem_lru unbacked;
147
148 /**
149 * pinned:
150 *
151 * The LRU for pinned GEM objects
152 */
153 struct drm_gem_lru pinned;
154
155 /**
156 * willneed:
157 *
158 * The LRU for unpinned GEM objects which are in madvise
159 * WILLNEED state (ie. can be evicted)
160 */
161 struct drm_gem_lru willneed;
162
163 /**
164 * dontneed:
165 *
166 * The LRU for unpinned GEM objects which are in madvise
167 * DONTNEED state (ie. can be purged)
168 */
169 struct drm_gem_lru dontneed;
170
171 /**
172 * lock:
173 *
174 * Protects manipulation of all of the LRUs.
175 */
176 struct mutex lock;
177 } lru;
178
179 struct workqueue_struct *wq;
180
181 unsigned int num_crtcs;
182
183 struct msm_drm_thread event_thread[MAX_CRTCS];
184
185 /* VRAM carveout, used when no IOMMU: */
186 struct {
187 unsigned long size;
188 dma_addr_t paddr;
189 /* NOTE: mm managed at the page level, size is in # of pages
190 * and position mm_node->start is in # of pages:
191 */
192 struct drm_mm mm;
193 spinlock_t lock; /* Protects drm_mm node allocation/removal */
194 } vram;
195
196 struct notifier_block vmap_notifier;
197 struct shrinker *shrinker;
198
199 /**
200 * hangcheck_period: For hang detection, in ms
201 *
202 * Note that in practice, a submit/job will get at least two hangcheck
203 * periods, due to checking for progress being implemented as simply
204 * "have the CP position registers changed since last time?"
205 */
206 unsigned int hangcheck_period;
207
208 /** gpu_devfreq_config: Devfreq tuning config for the GPU. */
209 struct devfreq_simple_ondemand_data gpu_devfreq_config;
210
211 /**
212 * gpu_clamp_to_idle: Enable clamping to idle freq when inactive
213 */
214 bool gpu_clamp_to_idle;
215
216 /**
217 * disable_err_irq:
218 *
219 * Disable handling of GPU hw error interrupts, to force fallback to
220 * sw hangcheck timer. Written (via debugfs) by igt tests to test
221 * the sw hangcheck mechanism.
222 */
223 bool disable_err_irq;
224};
225
226const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
227
228struct msm_pending_timer;
229
230int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
231 struct msm_kms *kms, int crtc_idx);
232void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer);
233void msm_atomic_commit_tail(struct drm_atomic_state *state);
234int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
235struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
236
237int msm_crtc_enable_vblank(struct drm_crtc *crtc);
238void msm_crtc_disable_vblank(struct drm_crtc *crtc);
239
240int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
241void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
242
243struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev);
244bool msm_use_mmu(struct drm_device *dev);
245
246int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
247 struct drm_file *file);
248
249#ifdef CONFIG_DEBUG_FS
250unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan);
251#endif
252
253int msm_gem_shrinker_init(struct drm_device *dev);
254void msm_gem_shrinker_cleanup(struct drm_device *dev);
255
256struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
257int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map);
258void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map);
259struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
260 struct dma_buf_attachment *attach, struct sg_table *sg);
261int msm_gem_prime_pin(struct drm_gem_object *obj);
262void msm_gem_prime_unpin(struct drm_gem_object *obj);
263
264int msm_framebuffer_prepare(struct drm_framebuffer *fb,
265 struct msm_gem_address_space *aspace, bool needs_dirtyfb);
266void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
267 struct msm_gem_address_space *aspace, bool needed_dirtyfb);
268uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
269 struct msm_gem_address_space *aspace, int plane);
270struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
271const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
272struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
273 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
274struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
275 int w, int h, int p, uint32_t format);
276
277#ifdef CONFIG_DRM_FBDEV_EMULATION
278int msm_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper,
279 struct drm_fb_helper_surface_size *sizes);
280#define MSM_FBDEV_DRIVER_OPS \
281 .fbdev_probe = msm_fbdev_driver_fbdev_probe
282#else
283#define MSM_FBDEV_DRIVER_OPS \
284 .fbdev_probe = NULL
285#endif
286
287struct hdmi;
288#ifdef CONFIG_DRM_MSM_HDMI
289int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
290 struct drm_encoder *encoder);
291void __init msm_hdmi_register(void);
292void __exit msm_hdmi_unregister(void);
293#else
294static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
295 struct drm_encoder *encoder)
296{
297 return -EINVAL;
298}
299static inline void __init msm_hdmi_register(void) {}
300static inline void __exit msm_hdmi_unregister(void) {}
301#endif
302
303struct msm_dsi;
304#ifdef CONFIG_DRM_MSM_DSI
305int dsi_dev_attach(struct platform_device *pdev);
306void dsi_dev_detach(struct platform_device *pdev);
307void __init msm_dsi_register(void);
308void __exit msm_dsi_unregister(void);
309int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
310 struct drm_encoder *encoder);
311void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi);
312bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
313bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
314bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
315bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi);
316struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
317const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi);
318#else
319static inline void __init msm_dsi_register(void)
320{
321}
322static inline void __exit msm_dsi_unregister(void)
323{
324}
325static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
326 struct drm_device *dev,
327 struct drm_encoder *encoder)
328{
329 return -EINVAL;
330}
331static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi)
332{
333}
334static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
335{
336 return false;
337}
338static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi)
339{
340 return false;
341}
342static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
343{
344 return false;
345}
346static inline bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi)
347{
348 return false;
349}
350
351static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
352{
353 return NULL;
354}
355
356static inline const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi)
357{
358 return NULL;
359}
360#endif
361
362#ifdef CONFIG_DRM_MSM_DP
363int __init msm_dp_register(void);
364void __exit msm_dp_unregister(void);
365int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
366 struct drm_encoder *encoder, bool yuv_supported);
367void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display);
368bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display,
369 const struct drm_display_mode *mode);
370bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display,
371 const struct drm_display_mode *mode);
372bool msm_dp_wide_bus_available(const struct msm_dp *dp_display);
373
374#else
375static inline int __init msm_dp_register(void)
376{
377 return -EINVAL;
378}
379static inline void __exit msm_dp_unregister(void)
380{
381}
382static inline int msm_dp_modeset_init(struct msm_dp *dp_display,
383 struct drm_device *dev,
384 struct drm_encoder *encoder,
385 bool yuv_supported)
386{
387 return -EINVAL;
388}
389
390static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display)
391{
392}
393
394static inline bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display,
395 const struct drm_display_mode *mode)
396{
397 return false;
398}
399
400static inline bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display,
401 const struct drm_display_mode *mode)
402{
403 return false;
404}
405
406static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display)
407{
408 return false;
409}
410
411#endif
412
413#ifdef CONFIG_DRM_MSM_MDP4
414void msm_mdp4_register(void);
415void msm_mdp4_unregister(void);
416#else
417static inline void msm_mdp4_register(void) {}
418static inline void msm_mdp4_unregister(void) {}
419#endif
420
421#ifdef CONFIG_DRM_MSM_MDP5
422void msm_mdp_register(void);
423void msm_mdp_unregister(void);
424#else
425static inline void msm_mdp_register(void) {}
426static inline void msm_mdp_unregister(void) {}
427#endif
428
429#ifdef CONFIG_DRM_MSM_DPU
430void msm_dpu_register(void);
431void msm_dpu_unregister(void);
432#else
433static inline void msm_dpu_register(void) {}
434static inline void msm_dpu_unregister(void) {}
435#endif
436
437#ifdef CONFIG_DRM_MSM_MDSS
438void msm_mdss_register(void);
439void msm_mdss_unregister(void);
440#else
441static inline void msm_mdss_register(void) {}
442static inline void msm_mdss_unregister(void) {}
443#endif
444
445#ifdef CONFIG_DEBUG_FS
446void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
447int msm_debugfs_late_init(struct drm_device *dev);
448int msm_rd_debugfs_init(struct drm_minor *minor);
449void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
450__printf(3, 4)
451void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
452 const char *fmt, ...);
453int msm_perf_debugfs_init(struct drm_minor *minor);
454void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
455#else
456static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
457__printf(3, 4)
458static inline void msm_rd_dump_submit(struct msm_rd_state *rd,
459 struct msm_gem_submit *submit,
460 const char *fmt, ...) {}
461static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
462static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
463#endif
464
465struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
466
467struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
468 const char *name);
469void __iomem *msm_ioremap(struct platform_device *pdev, const char *name);
470void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
471 phys_addr_t *size);
472void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name);
473void __iomem *msm_ioremap_mdss(struct platform_device *mdss_pdev,
474 struct platform_device *dev,
475 const char *name);
476
477struct icc_path *msm_icc_get(struct device *dev, const char *name);
478
479static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or)
480{
481 u32 val = readl(addr);
482
483 val &= ~mask;
484 writel(val | or, addr);
485}
486
487/**
488 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work
489 *
490 * @timer: hrtimer to control when the kthread work is triggered
491 * @work: the kthread work
492 * @worker: the kthread worker the work will be scheduled on
493 */
494struct msm_hrtimer_work {
495 struct hrtimer timer;
496 struct kthread_work work;
497 struct kthread_worker *worker;
498};
499
500void msm_hrtimer_queue_work(struct msm_hrtimer_work *work,
501 ktime_t wakeup_time,
502 enum hrtimer_mode mode);
503void msm_hrtimer_work_init(struct msm_hrtimer_work *work,
504 struct kthread_worker *worker,
505 kthread_work_func_t fn,
506 clockid_t clock_id,
507 enum hrtimer_mode mode);
508
509#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
510#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
511
512static inline int align_pitch(int width, int bpp)
513{
514 int bytespp = (bpp + 7) / 8;
515 /* adreno needs pitch aligned to 32 pixels: */
516 return bytespp * ALIGN(width, 32);
517}
518
519/* for the generated headers: */
520#define INVALID_IDX(idx) ({BUG(); 0;})
521#define fui(x) ({BUG(); 0;})
522#define _mesa_float_to_half(x) ({BUG(); 0;})
523
524
525#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
526
527/* for conditionally setting boolean flag(s): */
528#define COND(bool, val) ((bool) ? (val) : 0)
529
530static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
531{
532 ktime_t now = ktime_get();
533
534 if (ktime_compare(*timeout, now) <= 0)
535 return 0;
536
537 ktime_t rem = ktime_sub(*timeout, now);
538 s64 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
539 return clamp(remaining_jiffies, 1LL, (s64)INT_MAX);
540}
541
542/* Driver helpers */
543
544extern const struct component_master_ops msm_drm_ops;
545
546int msm_kms_pm_prepare(struct device *dev);
547void msm_kms_pm_complete(struct device *dev);
548
549int msm_drv_probe(struct device *dev,
550 int (*kms_init)(struct drm_device *dev),
551 struct msm_kms *kms);
552void msm_kms_shutdown(struct platform_device *pdev);
553
554bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver);
555
556#endif /* __MSM_DRV_H__ */