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1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __MSM_DRV_H__
19#define __MSM_DRV_H__
20
21#include <linux/kernel.h>
22#include <linux/clk.h>
23#include <linux/cpufreq.h>
24#include <linux/module.h>
25#include <linux/component.h>
26#include <linux/platform_device.h>
27#include <linux/pm.h>
28#include <linux/pm_runtime.h>
29#include <linux/slab.h>
30#include <linux/list.h>
31#include <linux/iommu.h>
32#include <linux/types.h>
33#include <linux/of_graph.h>
34#include <linux/of_device.h>
35#include <asm/sizes.h>
36
37#include <drm/drmP.h>
38#include <drm/drm_atomic.h>
39#include <drm/drm_atomic_helper.h>
40#include <drm/drm_crtc_helper.h>
41#include <drm/drm_plane_helper.h>
42#include <drm/drm_fb_helper.h>
43#include <drm/msm_drm.h>
44#include <drm/drm_gem.h>
45
46struct msm_kms;
47struct msm_gpu;
48struct msm_mmu;
49struct msm_rd_state;
50struct msm_perf_state;
51struct msm_gem_submit;
52
53#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */
54
55struct msm_file_private {
56 /* currently we don't do anything useful with this.. but when
57 * per-context address spaces are supported we'd keep track of
58 * the context's page-tables here.
59 */
60 int dummy;
61};
62
63enum msm_mdp_plane_property {
64 PLANE_PROP_ZPOS,
65 PLANE_PROP_ALPHA,
66 PLANE_PROP_PREMULTIPLIED,
67 PLANE_PROP_MAX_NUM
68};
69
70struct msm_vblank_ctrl {
71 struct work_struct work;
72 struct list_head event_list;
73 spinlock_t lock;
74};
75
76struct msm_drm_private {
77
78 struct msm_kms *kms;
79
80 /* subordinate devices, if present: */
81 struct platform_device *gpu_pdev;
82
83 /* possibly this should be in the kms component, but it is
84 * shared by both mdp4 and mdp5..
85 */
86 struct hdmi *hdmi;
87
88 /* eDP is for mdp5 only, but kms has not been created
89 * when edp_bind() and edp_init() are called. Here is the only
90 * place to keep the edp instance.
91 */
92 struct msm_edp *edp;
93
94 /* DSI is shared by mdp4 and mdp5 */
95 struct msm_dsi *dsi[2];
96
97 /* when we have more than one 'msm_gpu' these need to be an array: */
98 struct msm_gpu *gpu;
99 struct msm_file_private *lastctx;
100
101 struct drm_fb_helper *fbdev;
102
103 uint32_t next_fence, completed_fence;
104 wait_queue_head_t fence_event;
105
106 struct msm_rd_state *rd;
107 struct msm_perf_state *perf;
108
109 /* list of GEM objects: */
110 struct list_head inactive_list;
111
112 struct workqueue_struct *wq;
113
114 /* callbacks deferred until bo is inactive: */
115 struct list_head fence_cbs;
116
117 /* crtcs pending async atomic updates: */
118 uint32_t pending_crtcs;
119 wait_queue_head_t pending_crtcs_event;
120
121 /* registered MMUs: */
122 unsigned int num_mmus;
123 struct msm_mmu *mmus[NUM_DOMAINS];
124
125 unsigned int num_planes;
126 struct drm_plane *planes[8];
127
128 unsigned int num_crtcs;
129 struct drm_crtc *crtcs[8];
130
131 unsigned int num_encoders;
132 struct drm_encoder *encoders[8];
133
134 unsigned int num_bridges;
135 struct drm_bridge *bridges[8];
136
137 unsigned int num_connectors;
138 struct drm_connector *connectors[8];
139
140 /* Properties */
141 struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
142
143 /* VRAM carveout, used when no IOMMU: */
144 struct {
145 unsigned long size;
146 dma_addr_t paddr;
147 /* NOTE: mm managed at the page level, size is in # of pages
148 * and position mm_node->start is in # of pages:
149 */
150 struct drm_mm mm;
151 } vram;
152
153 struct msm_vblank_ctrl vblank_ctrl;
154};
155
156struct msm_format {
157 uint32_t pixel_format;
158};
159
160/* callback from wq once fence has passed: */
161struct msm_fence_cb {
162 struct work_struct work;
163 uint32_t fence;
164 void (*func)(struct msm_fence_cb *cb);
165};
166
167void __msm_fence_worker(struct work_struct *work);
168
169#define INIT_FENCE_CB(_cb, _func) do { \
170 INIT_WORK(&(_cb)->work, __msm_fence_worker); \
171 (_cb)->func = _func; \
172 } while (0)
173
174int msm_atomic_check(struct drm_device *dev,
175 struct drm_atomic_state *state);
176int msm_atomic_commit(struct drm_device *dev,
177 struct drm_atomic_state *state, bool async);
178
179int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
180
181int msm_wait_fence(struct drm_device *dev, uint32_t fence,
182 ktime_t *timeout, bool interruptible);
183int msm_queue_fence_cb(struct drm_device *dev,
184 struct msm_fence_cb *cb, uint32_t fence);
185void msm_update_fence(struct drm_device *dev, uint32_t fence);
186
187int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
188 struct drm_file *file);
189
190int msm_gem_mmap_obj(struct drm_gem_object *obj,
191 struct vm_area_struct *vma);
192int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
193int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
194uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
195int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
196 uint32_t *iova);
197int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova);
198uint32_t msm_gem_iova(struct drm_gem_object *obj, int id);
199struct page **msm_gem_get_pages(struct drm_gem_object *obj);
200void msm_gem_put_pages(struct drm_gem_object *obj);
201void msm_gem_put_iova(struct drm_gem_object *obj, int id);
202int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
203 struct drm_mode_create_dumb *args);
204int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
205 uint32_t handle, uint64_t *offset);
206struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
207void *msm_gem_prime_vmap(struct drm_gem_object *obj);
208void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
209int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
210struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
211 struct dma_buf_attachment *attach, struct sg_table *sg);
212int msm_gem_prime_pin(struct drm_gem_object *obj);
213void msm_gem_prime_unpin(struct drm_gem_object *obj);
214void *msm_gem_vaddr_locked(struct drm_gem_object *obj);
215void *msm_gem_vaddr(struct drm_gem_object *obj);
216int msm_gem_queue_inactive_cb(struct drm_gem_object *obj,
217 struct msm_fence_cb *cb);
218void msm_gem_move_to_active(struct drm_gem_object *obj,
219 struct msm_gpu *gpu, bool write, uint32_t fence);
220void msm_gem_move_to_inactive(struct drm_gem_object *obj);
221int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
222 ktime_t *timeout);
223int msm_gem_cpu_fini(struct drm_gem_object *obj);
224void msm_gem_free_object(struct drm_gem_object *obj);
225int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
226 uint32_t size, uint32_t flags, uint32_t *handle);
227struct drm_gem_object *msm_gem_new(struct drm_device *dev,
228 uint32_t size, uint32_t flags);
229struct drm_gem_object *msm_gem_import(struct drm_device *dev,
230 uint32_t size, struct sg_table *sgt);
231
232int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id);
233void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id);
234uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane);
235struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
236const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
237struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
238 const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
239struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
240 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
241
242struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
243void msm_fbdev_free(struct drm_device *dev);
244
245struct hdmi;
246int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
247 struct drm_encoder *encoder);
248void __init msm_hdmi_register(void);
249void __exit msm_hdmi_unregister(void);
250
251struct msm_edp;
252void __init msm_edp_register(void);
253void __exit msm_edp_unregister(void);
254int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
255 struct drm_encoder *encoder);
256
257struct msm_dsi;
258enum msm_dsi_encoder_id {
259 MSM_DSI_VIDEO_ENCODER_ID = 0,
260 MSM_DSI_CMD_ENCODER_ID = 1,
261 MSM_DSI_ENCODER_NUM = 2
262};
263#ifdef CONFIG_DRM_MSM_DSI
264void __init msm_dsi_register(void);
265void __exit msm_dsi_unregister(void);
266int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
267 struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]);
268#else
269static inline void __init msm_dsi_register(void)
270{
271}
272static inline void __exit msm_dsi_unregister(void)
273{
274}
275static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
276 struct drm_device *dev,
277 struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM])
278{
279 return -EINVAL;
280}
281#endif
282
283#ifdef CONFIG_DEBUG_FS
284void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
285void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
286void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
287int msm_debugfs_late_init(struct drm_device *dev);
288int msm_rd_debugfs_init(struct drm_minor *minor);
289void msm_rd_debugfs_cleanup(struct drm_minor *minor);
290void msm_rd_dump_submit(struct msm_gem_submit *submit);
291int msm_perf_debugfs_init(struct drm_minor *minor);
292void msm_perf_debugfs_cleanup(struct drm_minor *minor);
293#else
294static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
295static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {}
296#endif
297
298void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
299 const char *dbgname);
300void msm_writel(u32 data, void __iomem *addr);
301u32 msm_readl(const void __iomem *addr);
302
303#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
304#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
305
306static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
307{
308 struct msm_drm_private *priv = dev->dev_private;
309 return priv->completed_fence >= fence;
310}
311
312static inline int align_pitch(int width, int bpp)
313{
314 int bytespp = (bpp + 7) / 8;
315 /* adreno needs pitch aligned to 32 pixels: */
316 return bytespp * ALIGN(width, 32);
317}
318
319/* for the generated headers: */
320#define INVALID_IDX(idx) ({BUG(); 0;})
321#define fui(x) ({BUG(); 0;})
322#define util_float_to_half(x) ({BUG(); 0;})
323
324
325#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
326
327/* for conditionally setting boolean flag(s): */
328#define COND(bool, val) ((bool) ? (val) : 0)
329
330
331#endif /* __MSM_DRV_H__ */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#ifndef __MSM_DRV_H__
9#define __MSM_DRV_H__
10
11#include <linux/kernel.h>
12#include <linux/clk.h>
13#include <linux/cpufreq.h>
14#include <linux/devfreq.h>
15#include <linux/module.h>
16#include <linux/component.h>
17#include <linux/platform_device.h>
18#include <linux/pm.h>
19#include <linux/pm_runtime.h>
20#include <linux/slab.h>
21#include <linux/list.h>
22#include <linux/iommu.h>
23#include <linux/types.h>
24#include <linux/of_graph.h>
25#include <linux/of_device.h>
26#include <linux/sizes.h>
27#include <linux/kthread.h>
28
29#include <drm/drm_atomic.h>
30#include <drm/drm_atomic_helper.h>
31#include <drm/drm_probe_helper.h>
32#include <drm/display/drm_dsc.h>
33#include <drm/msm_drm.h>
34#include <drm/drm_gem.h>
35
36#ifdef CONFIG_FAULT_INJECTION
37extern struct fault_attr fail_gem_alloc;
38extern struct fault_attr fail_gem_iova;
39#else
40# define should_fail(attr, size) 0
41#endif
42
43struct msm_kms;
44struct msm_gpu;
45struct msm_mmu;
46struct msm_mdss;
47struct msm_rd_state;
48struct msm_perf_state;
49struct msm_gem_submit;
50struct msm_fence_context;
51struct msm_gem_address_space;
52struct msm_gem_vma;
53struct msm_disp_state;
54
55#define MAX_CRTCS 8
56#define MAX_BRIDGES 8
57
58#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
59
60enum msm_dp_controller {
61 MSM_DP_CONTROLLER_0,
62 MSM_DP_CONTROLLER_1,
63 MSM_DP_CONTROLLER_2,
64 MSM_DP_CONTROLLER_3,
65 MSM_DP_CONTROLLER_COUNT,
66};
67
68enum msm_dsi_controller {
69 MSM_DSI_CONTROLLER_0,
70 MSM_DSI_CONTROLLER_1,
71 MSM_DSI_CONTROLLER_COUNT,
72};
73
74#define MSM_GPU_MAX_RINGS 4
75#define MAX_H_TILES_PER_DISPLAY 2
76
77/**
78 * struct msm_display_topology - defines a display topology pipeline
79 * @num_lm: number of layer mixers used
80 * @num_intf: number of interfaces the panel is mounted on
81 * @num_dspp: number of dspp blocks used
82 * @num_dsc: number of Display Stream Compression (DSC) blocks used
83 * @needs_cdm: indicates whether cdm block is needed for this display topology
84 */
85struct msm_display_topology {
86 u32 num_lm;
87 u32 num_intf;
88 u32 num_dspp;
89 u32 num_dsc;
90 bool needs_cdm;
91};
92
93/* Commit/Event thread specific structure */
94struct msm_drm_thread {
95 struct drm_device *dev;
96 struct kthread_worker *worker;
97};
98
99struct msm_drm_private {
100
101 struct drm_device *dev;
102
103 struct msm_kms *kms;
104 int (*kms_init)(struct drm_device *dev);
105
106 /* subordinate devices, if present: */
107 struct platform_device *gpu_pdev;
108
109 /* possibly this should be in the kms component, but it is
110 * shared by both mdp4 and mdp5..
111 */
112 struct hdmi *hdmi;
113
114 /* DSI is shared by mdp4 and mdp5 */
115 struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT];
116
117 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT];
118
119 /* when we have more than one 'msm_gpu' these need to be an array: */
120 struct msm_gpu *gpu;
121
122 /* gpu is only set on open(), but we need this info earlier */
123 bool is_a2xx;
124 bool has_cached_coherent;
125
126 struct msm_rd_state *rd; /* debugfs to dump all submits */
127 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
128 struct msm_perf_state *perf;
129
130 /**
131 * List of all GEM objects (mainly for debugfs, protected by obj_lock
132 * (acquire before per GEM object lock)
133 */
134 struct list_head objects;
135 struct mutex obj_lock;
136
137 /**
138 * lru:
139 *
140 * The various LRU's that a GEM object is in at various stages of
141 * it's lifetime. Objects start out in the unbacked LRU. When
142 * pinned (for scannout or permanently mapped GPU buffers, like
143 * ringbuffer, memptr, fw, etc) it moves to the pinned LRU. When
144 * unpinned, it moves into willneed or dontneed LRU depending on
145 * madvise state. When backing pages are evicted (willneed) or
146 * purged (dontneed) it moves back into the unbacked LRU.
147 *
148 * The dontneed LRU is considered by the shrinker for objects
149 * that are candidate for purging, and the willneed LRU is
150 * considered for objects that could be evicted.
151 */
152 struct {
153 /**
154 * unbacked:
155 *
156 * The LRU for GEM objects without backing pages allocated.
157 * This mostly exists so that objects are always is one
158 * LRU.
159 */
160 struct drm_gem_lru unbacked;
161
162 /**
163 * pinned:
164 *
165 * The LRU for pinned GEM objects
166 */
167 struct drm_gem_lru pinned;
168
169 /**
170 * willneed:
171 *
172 * The LRU for unpinned GEM objects which are in madvise
173 * WILLNEED state (ie. can be evicted)
174 */
175 struct drm_gem_lru willneed;
176
177 /**
178 * dontneed:
179 *
180 * The LRU for unpinned GEM objects which are in madvise
181 * DONTNEED state (ie. can be purged)
182 */
183 struct drm_gem_lru dontneed;
184
185 /**
186 * lock:
187 *
188 * Protects manipulation of all of the LRUs.
189 */
190 struct mutex lock;
191 } lru;
192
193 struct workqueue_struct *wq;
194
195 unsigned int num_crtcs;
196
197 struct msm_drm_thread event_thread[MAX_CRTCS];
198
199 /* VRAM carveout, used when no IOMMU: */
200 struct {
201 unsigned long size;
202 dma_addr_t paddr;
203 /* NOTE: mm managed at the page level, size is in # of pages
204 * and position mm_node->start is in # of pages:
205 */
206 struct drm_mm mm;
207 spinlock_t lock; /* Protects drm_mm node allocation/removal */
208 } vram;
209
210 struct notifier_block vmap_notifier;
211 struct shrinker *shrinker;
212
213 struct drm_atomic_state *pm_state;
214
215 /**
216 * hangcheck_period: For hang detection, in ms
217 *
218 * Note that in practice, a submit/job will get at least two hangcheck
219 * periods, due to checking for progress being implemented as simply
220 * "have the CP position registers changed since last time?"
221 */
222 unsigned int hangcheck_period;
223
224 /** gpu_devfreq_config: Devfreq tuning config for the GPU. */
225 struct devfreq_simple_ondemand_data gpu_devfreq_config;
226
227 /**
228 * gpu_clamp_to_idle: Enable clamping to idle freq when inactive
229 */
230 bool gpu_clamp_to_idle;
231
232 /**
233 * disable_err_irq:
234 *
235 * Disable handling of GPU hw error interrupts, to force fallback to
236 * sw hangcheck timer. Written (via debugfs) by igt tests to test
237 * the sw hangcheck mechanism.
238 */
239 bool disable_err_irq;
240};
241
242struct msm_format {
243 uint32_t pixel_format;
244};
245
246struct msm_pending_timer;
247
248int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
249 struct msm_kms *kms, int crtc_idx);
250void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer);
251void msm_atomic_commit_tail(struct drm_atomic_state *state);
252int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
253struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
254void msm_atomic_state_clear(struct drm_atomic_state *state);
255void msm_atomic_state_free(struct drm_atomic_state *state);
256
257int msm_crtc_enable_vblank(struct drm_crtc *crtc);
258void msm_crtc_disable_vblank(struct drm_crtc *crtc);
259
260int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
261void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
262
263struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev);
264bool msm_use_mmu(struct drm_device *dev);
265
266int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
267 struct drm_file *file);
268
269#ifdef CONFIG_DEBUG_FS
270unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan);
271#endif
272
273int msm_gem_shrinker_init(struct drm_device *dev);
274void msm_gem_shrinker_cleanup(struct drm_device *dev);
275
276struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
277int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map);
278void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map);
279struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
280 struct dma_buf_attachment *attach, struct sg_table *sg);
281int msm_gem_prime_pin(struct drm_gem_object *obj);
282void msm_gem_prime_unpin(struct drm_gem_object *obj);
283
284int msm_framebuffer_prepare(struct drm_framebuffer *fb,
285 struct msm_gem_address_space *aspace, bool needs_dirtyfb);
286void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
287 struct msm_gem_address_space *aspace, bool needed_dirtyfb);
288uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
289 struct msm_gem_address_space *aspace, int plane);
290struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
291const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
292struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
293 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
294struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
295 int w, int h, int p, uint32_t format);
296
297#ifdef CONFIG_DRM_FBDEV_EMULATION
298void msm_fbdev_setup(struct drm_device *dev);
299#else
300static inline void msm_fbdev_setup(struct drm_device *dev)
301{
302}
303#endif
304
305struct hdmi;
306#ifdef CONFIG_DRM_MSM_HDMI
307int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
308 struct drm_encoder *encoder);
309void __init msm_hdmi_register(void);
310void __exit msm_hdmi_unregister(void);
311#else
312static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
313 struct drm_encoder *encoder)
314{
315 return -EINVAL;
316}
317static inline void __init msm_hdmi_register(void) {}
318static inline void __exit msm_hdmi_unregister(void) {}
319#endif
320
321struct msm_dsi;
322#ifdef CONFIG_DRM_MSM_DSI
323int dsi_dev_attach(struct platform_device *pdev);
324void dsi_dev_detach(struct platform_device *pdev);
325void __init msm_dsi_register(void);
326void __exit msm_dsi_unregister(void);
327int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
328 struct drm_encoder *encoder);
329void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi);
330bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
331bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
332bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
333bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi);
334struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
335#else
336static inline void __init msm_dsi_register(void)
337{
338}
339static inline void __exit msm_dsi_unregister(void)
340{
341}
342static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
343 struct drm_device *dev,
344 struct drm_encoder *encoder)
345{
346 return -EINVAL;
347}
348static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi)
349{
350}
351static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
352{
353 return false;
354}
355static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi)
356{
357 return false;
358}
359static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
360{
361 return false;
362}
363static inline bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi)
364{
365 return false;
366}
367
368static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
369{
370 return NULL;
371}
372#endif
373
374#ifdef CONFIG_DRM_MSM_DP
375int __init msm_dp_register(void);
376void __exit msm_dp_unregister(void);
377int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
378 struct drm_encoder *encoder, bool yuv_supported);
379void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display);
380bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display,
381 const struct drm_display_mode *mode);
382bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display,
383 const struct drm_display_mode *mode);
384bool msm_dp_wide_bus_available(const struct msm_dp *dp_display);
385
386#else
387static inline int __init msm_dp_register(void)
388{
389 return -EINVAL;
390}
391static inline void __exit msm_dp_unregister(void)
392{
393}
394static inline int msm_dp_modeset_init(struct msm_dp *dp_display,
395 struct drm_device *dev,
396 struct drm_encoder *encoder,
397 bool yuv_supported)
398{
399 return -EINVAL;
400}
401
402static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display)
403{
404}
405
406static inline bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display,
407 const struct drm_display_mode *mode)
408{
409 return false;
410}
411
412static inline bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display,
413 const struct drm_display_mode *mode)
414{
415 return false;
416}
417
418static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display)
419{
420 return false;
421}
422
423#endif
424
425#ifdef CONFIG_DRM_MSM_MDP4
426void msm_mdp4_register(void);
427void msm_mdp4_unregister(void);
428#else
429static inline void msm_mdp4_register(void) {}
430static inline void msm_mdp4_unregister(void) {}
431#endif
432
433#ifdef CONFIG_DRM_MSM_MDP5
434void msm_mdp_register(void);
435void msm_mdp_unregister(void);
436#else
437static inline void msm_mdp_register(void) {}
438static inline void msm_mdp_unregister(void) {}
439#endif
440
441#ifdef CONFIG_DRM_MSM_DPU
442void msm_dpu_register(void);
443void msm_dpu_unregister(void);
444#else
445static inline void msm_dpu_register(void) {}
446static inline void msm_dpu_unregister(void) {}
447#endif
448
449#ifdef CONFIG_DRM_MSM_MDSS
450void msm_mdss_register(void);
451void msm_mdss_unregister(void);
452#else
453static inline void msm_mdss_register(void) {}
454static inline void msm_mdss_unregister(void) {}
455#endif
456
457#ifdef CONFIG_DEBUG_FS
458void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
459int msm_debugfs_late_init(struct drm_device *dev);
460int msm_rd_debugfs_init(struct drm_minor *minor);
461void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
462__printf(3, 4)
463void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
464 const char *fmt, ...);
465int msm_perf_debugfs_init(struct drm_minor *minor);
466void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
467#else
468static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
469__printf(3, 4)
470static inline void msm_rd_dump_submit(struct msm_rd_state *rd,
471 struct msm_gem_submit *submit,
472 const char *fmt, ...) {}
473static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
474static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
475#endif
476
477struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
478
479struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
480 const char *name);
481void __iomem *msm_ioremap(struct platform_device *pdev, const char *name);
482void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
483 phys_addr_t *size);
484void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name);
485void __iomem *msm_ioremap_mdss(struct platform_device *mdss_pdev,
486 struct platform_device *dev,
487 const char *name);
488
489struct icc_path *msm_icc_get(struct device *dev, const char *name);
490
491#define msm_writel(data, addr) writel((data), (addr))
492#define msm_readl(addr) readl((addr))
493
494static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or)
495{
496 u32 val = msm_readl(addr);
497
498 val &= ~mask;
499 msm_writel(val | or, addr);
500}
501
502/**
503 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work
504 *
505 * @timer: hrtimer to control when the kthread work is triggered
506 * @work: the kthread work
507 * @worker: the kthread worker the work will be scheduled on
508 */
509struct msm_hrtimer_work {
510 struct hrtimer timer;
511 struct kthread_work work;
512 struct kthread_worker *worker;
513};
514
515void msm_hrtimer_queue_work(struct msm_hrtimer_work *work,
516 ktime_t wakeup_time,
517 enum hrtimer_mode mode);
518void msm_hrtimer_work_init(struct msm_hrtimer_work *work,
519 struct kthread_worker *worker,
520 kthread_work_func_t fn,
521 clockid_t clock_id,
522 enum hrtimer_mode mode);
523
524#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
525#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
526
527static inline int align_pitch(int width, int bpp)
528{
529 int bytespp = (bpp + 7) / 8;
530 /* adreno needs pitch aligned to 32 pixels: */
531 return bytespp * ALIGN(width, 32);
532}
533
534/* for the generated headers: */
535#define INVALID_IDX(idx) ({BUG(); 0;})
536#define fui(x) ({BUG(); 0;})
537#define _mesa_float_to_half(x) ({BUG(); 0;})
538
539
540#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
541
542/* for conditionally setting boolean flag(s): */
543#define COND(bool, val) ((bool) ? (val) : 0)
544
545static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
546{
547 ktime_t now = ktime_get();
548 s64 remaining_jiffies;
549
550 if (ktime_compare(*timeout, now) < 0) {
551 remaining_jiffies = 0;
552 } else {
553 ktime_t rem = ktime_sub(*timeout, now);
554 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
555 }
556
557 return clamp(remaining_jiffies, 1LL, (s64)INT_MAX);
558}
559
560/* Driver helpers */
561
562extern const struct component_master_ops msm_drm_ops;
563
564int msm_kms_pm_prepare(struct device *dev);
565void msm_kms_pm_complete(struct device *dev);
566
567int msm_drv_probe(struct device *dev,
568 int (*kms_init)(struct drm_device *dev),
569 struct msm_kms *kms);
570void msm_kms_shutdown(struct platform_device *pdev);
571
572bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver);
573
574#endif /* __MSM_DRV_H__ */