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1/*
2 * Copyright (C) 2015 Broadcom
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/**
10 * DOC: VC4 CRTC module
11 *
12 * In VC4, the Pixel Valve is what most closely corresponds to the
13 * DRM's concept of a CRTC. The PV generates video timings from the
14 * output's clock plus its configuration. It pulls scaled pixels from
15 * the HVS at that timing, and feeds it to the encoder.
16 *
17 * However, the DRM CRTC also collects the configuration of all the
18 * DRM planes attached to it. As a result, this file also manages
19 * setup of the VC4 HVS's display elements on the CRTC.
20 *
21 * The 2835 has 3 different pixel valves. pv0 in the audio power
22 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
23 * image domain can feed either HDMI or the SDTV controller. The
24 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
25 * SDTV, etc.) according to which output type is chosen in the mux.
26 *
27 * For power management, the pixel valve's registers are all clocked
28 * by the AXI clock, while the timings and FIFOs make use of the
29 * output-specific clock. Since the encoders also directly consume
30 * the CPRMAN clocks, and know what timings they need, they are the
31 * ones that set the clock.
32 */
33
34#include "drm_atomic.h"
35#include "drm_atomic_helper.h"
36#include "drm_crtc_helper.h"
37#include "linux/clk.h"
38#include "drm_fb_cma_helper.h"
39#include "linux/component.h"
40#include "linux/of_device.h"
41#include "vc4_drv.h"
42#include "vc4_regs.h"
43
44struct vc4_crtc {
45 struct drm_crtc base;
46 const struct vc4_crtc_data *data;
47 void __iomem *regs;
48
49 /* Which HVS channel we're using for our CRTC. */
50 int channel;
51
52 struct drm_pending_vblank_event *event;
53};
54
55struct vc4_crtc_state {
56 struct drm_crtc_state base;
57 /* Dlist area for this CRTC configuration. */
58 struct drm_mm_node mm;
59};
60
61static inline struct vc4_crtc *
62to_vc4_crtc(struct drm_crtc *crtc)
63{
64 return (struct vc4_crtc *)crtc;
65}
66
67static inline struct vc4_crtc_state *
68to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
69{
70 return (struct vc4_crtc_state *)crtc_state;
71}
72
73struct vc4_crtc_data {
74 /* Which channel of the HVS this pixelvalve sources from. */
75 int hvs_channel;
76
77 enum vc4_encoder_type encoder0_type;
78 enum vc4_encoder_type encoder1_type;
79};
80
81#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
82#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
83
84#define CRTC_REG(reg) { reg, #reg }
85static const struct {
86 u32 reg;
87 const char *name;
88} crtc_regs[] = {
89 CRTC_REG(PV_CONTROL),
90 CRTC_REG(PV_V_CONTROL),
91 CRTC_REG(PV_VSYNCD_EVEN),
92 CRTC_REG(PV_HORZA),
93 CRTC_REG(PV_HORZB),
94 CRTC_REG(PV_VERTA),
95 CRTC_REG(PV_VERTB),
96 CRTC_REG(PV_VERTA_EVEN),
97 CRTC_REG(PV_VERTB_EVEN),
98 CRTC_REG(PV_INTEN),
99 CRTC_REG(PV_INTSTAT),
100 CRTC_REG(PV_STAT),
101 CRTC_REG(PV_HACT_ACT),
102};
103
104static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
105{
106 int i;
107
108 for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
109 DRM_INFO("0x%04x (%s): 0x%08x\n",
110 crtc_regs[i].reg, crtc_regs[i].name,
111 CRTC_READ(crtc_regs[i].reg));
112 }
113}
114
115#ifdef CONFIG_DEBUG_FS
116int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
117{
118 struct drm_info_node *node = (struct drm_info_node *)m->private;
119 struct drm_device *dev = node->minor->dev;
120 int crtc_index = (uintptr_t)node->info_ent->data;
121 struct drm_crtc *crtc;
122 struct vc4_crtc *vc4_crtc;
123 int i;
124
125 i = 0;
126 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
127 if (i == crtc_index)
128 break;
129 i++;
130 }
131 if (!crtc)
132 return 0;
133 vc4_crtc = to_vc4_crtc(crtc);
134
135 for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
136 seq_printf(m, "%s (0x%04x): 0x%08x\n",
137 crtc_regs[i].name, crtc_regs[i].reg,
138 CRTC_READ(crtc_regs[i].reg));
139 }
140
141 return 0;
142}
143#endif
144
145static void vc4_crtc_destroy(struct drm_crtc *crtc)
146{
147 drm_crtc_cleanup(crtc);
148}
149
150static u32 vc4_get_fifo_full_level(u32 format)
151{
152 static const u32 fifo_len_bytes = 64;
153 static const u32 hvs_latency_pix = 6;
154
155 switch (format) {
156 case PV_CONTROL_FORMAT_DSIV_16:
157 case PV_CONTROL_FORMAT_DSIC_16:
158 return fifo_len_bytes - 2 * hvs_latency_pix;
159 case PV_CONTROL_FORMAT_DSIV_18:
160 return fifo_len_bytes - 14;
161 case PV_CONTROL_FORMAT_24:
162 case PV_CONTROL_FORMAT_DSIV_24:
163 default:
164 return fifo_len_bytes - 3 * hvs_latency_pix;
165 }
166}
167
168/*
169 * Returns the clock select bit for the connector attached to the
170 * CRTC.
171 */
172static int vc4_get_clock_select(struct drm_crtc *crtc)
173{
174 struct drm_connector *connector;
175
176 drm_for_each_connector(connector, crtc->dev) {
177 if (connector->state->crtc == crtc) {
178 struct drm_encoder *encoder = connector->encoder;
179 struct vc4_encoder *vc4_encoder =
180 to_vc4_encoder(encoder);
181
182 return vc4_encoder->clock_select;
183 }
184 }
185
186 return -1;
187}
188
189static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
190{
191 struct drm_device *dev = crtc->dev;
192 struct vc4_dev *vc4 = to_vc4_dev(dev);
193 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
194 struct drm_crtc_state *state = crtc->state;
195 struct drm_display_mode *mode = &state->adjusted_mode;
196 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
197 u32 vactive = (mode->vdisplay >> (interlace ? 1 : 0));
198 u32 format = PV_CONTROL_FORMAT_24;
199 bool debug_dump_regs = false;
200 int clock_select = vc4_get_clock_select(crtc);
201
202 if (debug_dump_regs) {
203 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
204 vc4_crtc_dump_regs(vc4_crtc);
205 }
206
207 /* Reset the PV fifo. */
208 CRTC_WRITE(PV_CONTROL, 0);
209 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
210 CRTC_WRITE(PV_CONTROL, 0);
211
212 CRTC_WRITE(PV_HORZA,
213 VC4_SET_FIELD(mode->htotal - mode->hsync_end,
214 PV_HORZA_HBP) |
215 VC4_SET_FIELD(mode->hsync_end - mode->hsync_start,
216 PV_HORZA_HSYNC));
217 CRTC_WRITE(PV_HORZB,
218 VC4_SET_FIELD(mode->hsync_start - mode->hdisplay,
219 PV_HORZB_HFP) |
220 VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));
221
222 CRTC_WRITE(PV_VERTA,
223 VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
224 PV_VERTA_VBP) |
225 VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
226 PV_VERTA_VSYNC));
227 CRTC_WRITE(PV_VERTB,
228 VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
229 PV_VERTB_VFP) |
230 VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
231
232 if (interlace) {
233 CRTC_WRITE(PV_VERTA_EVEN,
234 VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,
235 PV_VERTA_VBP) |
236 VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
237 PV_VERTA_VSYNC));
238 CRTC_WRITE(PV_VERTB_EVEN,
239 VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
240 PV_VERTB_VFP) |
241 VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
242 }
243
244 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay);
245
246 CRTC_WRITE(PV_V_CONTROL,
247 PV_VCONTROL_CONTINUOUS |
248 (interlace ? PV_VCONTROL_INTERLACE : 0));
249
250 CRTC_WRITE(PV_CONTROL,
251 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
252 VC4_SET_FIELD(vc4_get_fifo_full_level(format),
253 PV_CONTROL_FIFO_LEVEL) |
254 PV_CONTROL_CLR_AT_START |
255 PV_CONTROL_TRIGGER_UNDERFLOW |
256 PV_CONTROL_WAIT_HSTART |
257 VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) |
258 PV_CONTROL_FIFO_CLR |
259 PV_CONTROL_EN);
260
261 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
262 SCALER_DISPBKGND_AUTOHS |
263 (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
264
265 if (debug_dump_regs) {
266 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
267 vc4_crtc_dump_regs(vc4_crtc);
268 }
269}
270
271static void require_hvs_enabled(struct drm_device *dev)
272{
273 struct vc4_dev *vc4 = to_vc4_dev(dev);
274
275 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
276 SCALER_DISPCTRL_ENABLE);
277}
278
279static void vc4_crtc_disable(struct drm_crtc *crtc)
280{
281 struct drm_device *dev = crtc->dev;
282 struct vc4_dev *vc4 = to_vc4_dev(dev);
283 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
284 u32 chan = vc4_crtc->channel;
285 int ret;
286 require_hvs_enabled(dev);
287
288 CRTC_WRITE(PV_V_CONTROL,
289 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
290 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
291 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
292
293 if (HVS_READ(SCALER_DISPCTRLX(chan)) &
294 SCALER_DISPCTRLX_ENABLE) {
295 HVS_WRITE(SCALER_DISPCTRLX(chan),
296 SCALER_DISPCTRLX_RESET);
297
298 /* While the docs say that reset is self-clearing, it
299 * seems it doesn't actually.
300 */
301 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
302 }
303
304 /* Once we leave, the scaler should be disabled and its fifo empty. */
305
306 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
307
308 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
309 SCALER_DISPSTATX_MODE) !=
310 SCALER_DISPSTATX_MODE_DISABLED);
311
312 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
313 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
314 SCALER_DISPSTATX_EMPTY);
315}
316
317static void vc4_crtc_enable(struct drm_crtc *crtc)
318{
319 struct drm_device *dev = crtc->dev;
320 struct vc4_dev *vc4 = to_vc4_dev(dev);
321 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
322 struct drm_crtc_state *state = crtc->state;
323 struct drm_display_mode *mode = &state->adjusted_mode;
324
325 require_hvs_enabled(dev);
326
327 /* Turn on the scaler, which will wait for vstart to start
328 * compositing.
329 */
330 HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
331 VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
332 VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
333 SCALER_DISPCTRLX_ENABLE);
334
335 /* Turn on the pixel valve, which will emit the vstart signal. */
336 CRTC_WRITE(PV_V_CONTROL,
337 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
338}
339
340static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
341 struct drm_crtc_state *state)
342{
343 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
344 struct drm_device *dev = crtc->dev;
345 struct vc4_dev *vc4 = to_vc4_dev(dev);
346 struct drm_plane *plane;
347 unsigned long flags;
348 u32 dlist_count = 0;
349 int ret;
350
351 /* The pixelvalve can only feed one encoder (and encoders are
352 * 1:1 with connectors.)
353 */
354 if (hweight32(state->connector_mask) > 1)
355 return -EINVAL;
356
357 drm_atomic_crtc_state_for_each_plane(plane, state) {
358 struct drm_plane_state *plane_state =
359 state->state->plane_states[drm_plane_index(plane)];
360
361 /* plane might not have changed, in which case take
362 * current state:
363 */
364 if (!plane_state)
365 plane_state = plane->state;
366
367 dlist_count += vc4_plane_dlist_size(plane_state);
368 }
369
370 dlist_count++; /* Account for SCALER_CTL0_END. */
371
372 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
373 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
374 dlist_count, 1, 0);
375 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
376 if (ret)
377 return ret;
378
379 return 0;
380}
381
382static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
383 struct drm_crtc_state *old_state)
384{
385 struct drm_device *dev = crtc->dev;
386 struct vc4_dev *vc4 = to_vc4_dev(dev);
387 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
388 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
389 struct drm_plane *plane;
390 bool debug_dump_regs = false;
391 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
392 u32 __iomem *dlist_next = dlist_start;
393
394 if (debug_dump_regs) {
395 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
396 vc4_hvs_dump_state(dev);
397 }
398
399 /* Copy all the active planes' dlist contents to the hardware dlist. */
400 drm_atomic_crtc_for_each_plane(plane, crtc) {
401 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
402 }
403
404 writel(SCALER_CTL0_END, dlist_next);
405 dlist_next++;
406
407 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
408
409 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
410 vc4_state->mm.start);
411
412 if (debug_dump_regs) {
413 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
414 vc4_hvs_dump_state(dev);
415 }
416
417 if (crtc->state->event) {
418 unsigned long flags;
419
420 crtc->state->event->pipe = drm_crtc_index(crtc);
421
422 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
423
424 spin_lock_irqsave(&dev->event_lock, flags);
425 vc4_crtc->event = crtc->state->event;
426 spin_unlock_irqrestore(&dev->event_lock, flags);
427 crtc->state->event = NULL;
428 }
429}
430
431int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id)
432{
433 struct vc4_dev *vc4 = to_vc4_dev(dev);
434 struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
435
436 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
437
438 return 0;
439}
440
441void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id)
442{
443 struct vc4_dev *vc4 = to_vc4_dev(dev);
444 struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
445
446 CRTC_WRITE(PV_INTEN, 0);
447}
448
449static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
450{
451 struct drm_crtc *crtc = &vc4_crtc->base;
452 struct drm_device *dev = crtc->dev;
453 unsigned long flags;
454
455 spin_lock_irqsave(&dev->event_lock, flags);
456 if (vc4_crtc->event) {
457 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
458 vc4_crtc->event = NULL;
459 }
460 spin_unlock_irqrestore(&dev->event_lock, flags);
461}
462
463static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
464{
465 struct vc4_crtc *vc4_crtc = data;
466 u32 stat = CRTC_READ(PV_INTSTAT);
467 irqreturn_t ret = IRQ_NONE;
468
469 if (stat & PV_INT_VFP_START) {
470 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
471 drm_crtc_handle_vblank(&vc4_crtc->base);
472 vc4_crtc_handle_page_flip(vc4_crtc);
473 ret = IRQ_HANDLED;
474 }
475
476 return ret;
477}
478
479struct vc4_async_flip_state {
480 struct drm_crtc *crtc;
481 struct drm_framebuffer *fb;
482 struct drm_pending_vblank_event *event;
483
484 struct vc4_seqno_cb cb;
485};
486
487/* Called when the V3D execution for the BO being flipped to is done, so that
488 * we can actually update the plane's address to point to it.
489 */
490static void
491vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
492{
493 struct vc4_async_flip_state *flip_state =
494 container_of(cb, struct vc4_async_flip_state, cb);
495 struct drm_crtc *crtc = flip_state->crtc;
496 struct drm_device *dev = crtc->dev;
497 struct vc4_dev *vc4 = to_vc4_dev(dev);
498 struct drm_plane *plane = crtc->primary;
499
500 vc4_plane_async_set_fb(plane, flip_state->fb);
501 if (flip_state->event) {
502 unsigned long flags;
503
504 spin_lock_irqsave(&dev->event_lock, flags);
505 drm_crtc_send_vblank_event(crtc, flip_state->event);
506 spin_unlock_irqrestore(&dev->event_lock, flags);
507 }
508
509 drm_framebuffer_unreference(flip_state->fb);
510 kfree(flip_state);
511
512 up(&vc4->async_modeset);
513}
514
515/* Implements async (non-vblank-synced) page flips.
516 *
517 * The page flip ioctl needs to return immediately, so we grab the
518 * modeset semaphore on the pipe, and queue the address update for
519 * when V3D is done with the BO being flipped to.
520 */
521static int vc4_async_page_flip(struct drm_crtc *crtc,
522 struct drm_framebuffer *fb,
523 struct drm_pending_vblank_event *event,
524 uint32_t flags)
525{
526 struct drm_device *dev = crtc->dev;
527 struct vc4_dev *vc4 = to_vc4_dev(dev);
528 struct drm_plane *plane = crtc->primary;
529 int ret = 0;
530 struct vc4_async_flip_state *flip_state;
531 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
532 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
533
534 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
535 if (!flip_state)
536 return -ENOMEM;
537
538 drm_framebuffer_reference(fb);
539 flip_state->fb = fb;
540 flip_state->crtc = crtc;
541 flip_state->event = event;
542
543 /* Make sure all other async modesetes have landed. */
544 ret = down_interruptible(&vc4->async_modeset);
545 if (ret) {
546 drm_framebuffer_unreference(fb);
547 kfree(flip_state);
548 return ret;
549 }
550
551 /* Immediately update the plane's legacy fb pointer, so that later
552 * modeset prep sees the state that will be present when the semaphore
553 * is released.
554 */
555 drm_atomic_set_fb_for_plane(plane->state, fb);
556 plane->fb = fb;
557
558 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
559 vc4_async_page_flip_complete);
560
561 /* Driver takes ownership of state on successful async commit. */
562 return 0;
563}
564
565static int vc4_page_flip(struct drm_crtc *crtc,
566 struct drm_framebuffer *fb,
567 struct drm_pending_vblank_event *event,
568 uint32_t flags)
569{
570 if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
571 return vc4_async_page_flip(crtc, fb, event, flags);
572 else
573 return drm_atomic_helper_page_flip(crtc, fb, event, flags);
574}
575
576static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
577{
578 struct vc4_crtc_state *vc4_state;
579
580 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
581 if (!vc4_state)
582 return NULL;
583
584 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
585 return &vc4_state->base;
586}
587
588static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
589 struct drm_crtc_state *state)
590{
591 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
592 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
593
594 if (vc4_state->mm.allocated) {
595 unsigned long flags;
596
597 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
598 drm_mm_remove_node(&vc4_state->mm);
599 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
600
601 }
602
603 __drm_atomic_helper_crtc_destroy_state(crtc, state);
604}
605
606static const struct drm_crtc_funcs vc4_crtc_funcs = {
607 .set_config = drm_atomic_helper_set_config,
608 .destroy = vc4_crtc_destroy,
609 .page_flip = vc4_page_flip,
610 .set_property = NULL,
611 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
612 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
613 .reset = drm_atomic_helper_crtc_reset,
614 .atomic_duplicate_state = vc4_crtc_duplicate_state,
615 .atomic_destroy_state = vc4_crtc_destroy_state,
616};
617
618static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
619 .mode_set_nofb = vc4_crtc_mode_set_nofb,
620 .disable = vc4_crtc_disable,
621 .enable = vc4_crtc_enable,
622 .atomic_check = vc4_crtc_atomic_check,
623 .atomic_flush = vc4_crtc_atomic_flush,
624};
625
626static const struct vc4_crtc_data pv0_data = {
627 .hvs_channel = 0,
628 .encoder0_type = VC4_ENCODER_TYPE_DSI0,
629 .encoder1_type = VC4_ENCODER_TYPE_DPI,
630};
631
632static const struct vc4_crtc_data pv1_data = {
633 .hvs_channel = 2,
634 .encoder0_type = VC4_ENCODER_TYPE_DSI1,
635 .encoder1_type = VC4_ENCODER_TYPE_SMI,
636};
637
638static const struct vc4_crtc_data pv2_data = {
639 .hvs_channel = 1,
640 .encoder0_type = VC4_ENCODER_TYPE_VEC,
641 .encoder1_type = VC4_ENCODER_TYPE_HDMI,
642};
643
644static const struct of_device_id vc4_crtc_dt_match[] = {
645 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
646 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
647 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
648 {}
649};
650
651static void vc4_set_crtc_possible_masks(struct drm_device *drm,
652 struct drm_crtc *crtc)
653{
654 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
655 struct drm_encoder *encoder;
656
657 drm_for_each_encoder(encoder, drm) {
658 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
659
660 if (vc4_encoder->type == vc4_crtc->data->encoder0_type) {
661 vc4_encoder->clock_select = 0;
662 encoder->possible_crtcs |= drm_crtc_mask(crtc);
663 } else if (vc4_encoder->type == vc4_crtc->data->encoder1_type) {
664 vc4_encoder->clock_select = 1;
665 encoder->possible_crtcs |= drm_crtc_mask(crtc);
666 }
667 }
668}
669
670static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
671{
672 struct platform_device *pdev = to_platform_device(dev);
673 struct drm_device *drm = dev_get_drvdata(master);
674 struct vc4_dev *vc4 = to_vc4_dev(drm);
675 struct vc4_crtc *vc4_crtc;
676 struct drm_crtc *crtc;
677 struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
678 const struct of_device_id *match;
679 int ret, i;
680
681 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
682 if (!vc4_crtc)
683 return -ENOMEM;
684 crtc = &vc4_crtc->base;
685
686 match = of_match_device(vc4_crtc_dt_match, dev);
687 if (!match)
688 return -ENODEV;
689 vc4_crtc->data = match->data;
690
691 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
692 if (IS_ERR(vc4_crtc->regs))
693 return PTR_ERR(vc4_crtc->regs);
694
695 /* For now, we create just the primary and the legacy cursor
696 * planes. We should be able to stack more planes on easily,
697 * but to do that we would need to compute the bandwidth
698 * requirement of the plane configuration, and reject ones
699 * that will take too much.
700 */
701 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
702 if (IS_ERR(primary_plane)) {
703 dev_err(dev, "failed to construct primary plane\n");
704 ret = PTR_ERR(primary_plane);
705 goto err;
706 }
707
708 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
709 &vc4_crtc_funcs, NULL);
710 drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
711 primary_plane->crtc = crtc;
712 vc4->crtc[drm_crtc_index(crtc)] = vc4_crtc;
713 vc4_crtc->channel = vc4_crtc->data->hvs_channel;
714
715 /* Set up some arbitrary number of planes. We're not limited
716 * by a set number of physical registers, just the space in
717 * the HVS (16k) and how small an plane can be (28 bytes).
718 * However, each plane we set up takes up some memory, and
719 * increases the cost of looping over planes, which atomic
720 * modesetting does quite a bit. As a result, we pick a
721 * modest number of planes to expose, that should hopefully
722 * still cover any sane usecase.
723 */
724 for (i = 0; i < 8; i++) {
725 struct drm_plane *plane =
726 vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
727
728 if (IS_ERR(plane))
729 continue;
730
731 plane->possible_crtcs = 1 << drm_crtc_index(crtc);
732 }
733
734 /* Set up the legacy cursor after overlay initialization,
735 * since we overlay planes on the CRTC in the order they were
736 * initialized.
737 */
738 cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
739 if (!IS_ERR(cursor_plane)) {
740 cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc);
741 cursor_plane->crtc = crtc;
742 crtc->cursor = cursor_plane;
743 }
744
745 CRTC_WRITE(PV_INTEN, 0);
746 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
747 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
748 vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
749 if (ret)
750 goto err_destroy_planes;
751
752 vc4_set_crtc_possible_masks(drm, crtc);
753
754 platform_set_drvdata(pdev, vc4_crtc);
755
756 return 0;
757
758err_destroy_planes:
759 list_for_each_entry_safe(destroy_plane, temp,
760 &drm->mode_config.plane_list, head) {
761 if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
762 destroy_plane->funcs->destroy(destroy_plane);
763 }
764err:
765 return ret;
766}
767
768static void vc4_crtc_unbind(struct device *dev, struct device *master,
769 void *data)
770{
771 struct platform_device *pdev = to_platform_device(dev);
772 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
773
774 vc4_crtc_destroy(&vc4_crtc->base);
775
776 CRTC_WRITE(PV_INTEN, 0);
777
778 platform_set_drvdata(pdev, NULL);
779}
780
781static const struct component_ops vc4_crtc_ops = {
782 .bind = vc4_crtc_bind,
783 .unbind = vc4_crtc_unbind,
784};
785
786static int vc4_crtc_dev_probe(struct platform_device *pdev)
787{
788 return component_add(&pdev->dev, &vc4_crtc_ops);
789}
790
791static int vc4_crtc_dev_remove(struct platform_device *pdev)
792{
793 component_del(&pdev->dev, &vc4_crtc_ops);
794 return 0;
795}
796
797struct platform_driver vc4_crtc_driver = {
798 .probe = vc4_crtc_dev_probe,
799 .remove = vc4_crtc_dev_remove,
800 .driver = {
801 .name = "vc4_crtc",
802 .of_match_table = vc4_crtc_dt_match,
803 },
804};
1/*
2 * Copyright (C) 2015 Broadcom
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/**
10 * DOC: VC4 CRTC module
11 *
12 * In VC4, the Pixel Valve is what most closely corresponds to the
13 * DRM's concept of a CRTC. The PV generates video timings from the
14 * encoder's clock plus its configuration. It pulls scaled pixels from
15 * the HVS at that timing, and feeds it to the encoder.
16 *
17 * However, the DRM CRTC also collects the configuration of all the
18 * DRM planes attached to it. As a result, the CRTC is also
19 * responsible for writing the display list for the HVS channel that
20 * the CRTC will use.
21 *
22 * The 2835 has 3 different pixel valves. pv0 in the audio power
23 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
24 * image domain can feed either HDMI or the SDTV controller. The
25 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
26 * SDTV, etc.) according to which output type is chosen in the mux.
27 *
28 * For power management, the pixel valve's registers are all clocked
29 * by the AXI clock, while the timings and FIFOs make use of the
30 * output-specific clock. Since the encoders also directly consume
31 * the CPRMAN clocks, and know what timings they need, they are the
32 * ones that set the clock.
33 */
34
35#include <drm/drm_atomic.h>
36#include <drm/drm_atomic_helper.h>
37#include <drm/drm_crtc_helper.h>
38#include <linux/clk.h>
39#include <drm/drm_fb_cma_helper.h>
40#include <linux/component.h>
41#include <linux/of_device.h>
42#include "vc4_drv.h"
43#include "vc4_regs.h"
44
45struct vc4_crtc {
46 struct drm_crtc base;
47 const struct vc4_crtc_data *data;
48 void __iomem *regs;
49
50 /* Timestamp at start of vblank irq - unaffected by lock delays. */
51 ktime_t t_vblank;
52
53 /* Which HVS channel we're using for our CRTC. */
54 int channel;
55
56 u8 lut_r[256];
57 u8 lut_g[256];
58 u8 lut_b[256];
59 /* Size in pixels of the COB memory allocated to this CRTC. */
60 u32 cob_size;
61
62 struct drm_pending_vblank_event *event;
63};
64
65struct vc4_crtc_state {
66 struct drm_crtc_state base;
67 /* Dlist area for this CRTC configuration. */
68 struct drm_mm_node mm;
69};
70
71static inline struct vc4_crtc *
72to_vc4_crtc(struct drm_crtc *crtc)
73{
74 return (struct vc4_crtc *)crtc;
75}
76
77static inline struct vc4_crtc_state *
78to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
79{
80 return (struct vc4_crtc_state *)crtc_state;
81}
82
83struct vc4_crtc_data {
84 /* Which channel of the HVS this pixelvalve sources from. */
85 int hvs_channel;
86
87 enum vc4_encoder_type encoder_types[4];
88};
89
90#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
91#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
92
93#define CRTC_REG(reg) { reg, #reg }
94static const struct {
95 u32 reg;
96 const char *name;
97} crtc_regs[] = {
98 CRTC_REG(PV_CONTROL),
99 CRTC_REG(PV_V_CONTROL),
100 CRTC_REG(PV_VSYNCD_EVEN),
101 CRTC_REG(PV_HORZA),
102 CRTC_REG(PV_HORZB),
103 CRTC_REG(PV_VERTA),
104 CRTC_REG(PV_VERTB),
105 CRTC_REG(PV_VERTA_EVEN),
106 CRTC_REG(PV_VERTB_EVEN),
107 CRTC_REG(PV_INTEN),
108 CRTC_REG(PV_INTSTAT),
109 CRTC_REG(PV_STAT),
110 CRTC_REG(PV_HACT_ACT),
111};
112
113static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
114{
115 int i;
116
117 for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
118 DRM_INFO("0x%04x (%s): 0x%08x\n",
119 crtc_regs[i].reg, crtc_regs[i].name,
120 CRTC_READ(crtc_regs[i].reg));
121 }
122}
123
124#ifdef CONFIG_DEBUG_FS
125int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
126{
127 struct drm_info_node *node = (struct drm_info_node *)m->private;
128 struct drm_device *dev = node->minor->dev;
129 int crtc_index = (uintptr_t)node->info_ent->data;
130 struct drm_crtc *crtc;
131 struct vc4_crtc *vc4_crtc;
132 int i;
133
134 i = 0;
135 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
136 if (i == crtc_index)
137 break;
138 i++;
139 }
140 if (!crtc)
141 return 0;
142 vc4_crtc = to_vc4_crtc(crtc);
143
144 for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
145 seq_printf(m, "%s (0x%04x): 0x%08x\n",
146 crtc_regs[i].name, crtc_regs[i].reg,
147 CRTC_READ(crtc_regs[i].reg));
148 }
149
150 return 0;
151}
152#endif
153
154bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
155 bool in_vblank_irq, int *vpos, int *hpos,
156 ktime_t *stime, ktime_t *etime,
157 const struct drm_display_mode *mode)
158{
159 struct vc4_dev *vc4 = to_vc4_dev(dev);
160 struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
161 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
162 u32 val;
163 int fifo_lines;
164 int vblank_lines;
165 bool ret = false;
166
167 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
168
169 /* Get optional system timestamp before query. */
170 if (stime)
171 *stime = ktime_get();
172
173 /*
174 * Read vertical scanline which is currently composed for our
175 * pixelvalve by the HVS, and also the scaler status.
176 */
177 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
178
179 /* Get optional system timestamp after query. */
180 if (etime)
181 *etime = ktime_get();
182
183 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
184
185 /* Vertical position of hvs composed scanline. */
186 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
187 *hpos = 0;
188
189 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
190 *vpos /= 2;
191
192 /* Use hpos to correct for field offset in interlaced mode. */
193 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
194 *hpos += mode->crtc_htotal / 2;
195 }
196
197 /* This is the offset we need for translating hvs -> pv scanout pos. */
198 fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
199
200 if (fifo_lines > 0)
201 ret = true;
202
203 /* HVS more than fifo_lines into frame for compositing? */
204 if (*vpos > fifo_lines) {
205 /*
206 * We are in active scanout and can get some meaningful results
207 * from HVS. The actual PV scanout can not trail behind more
208 * than fifo_lines as that is the fifo's capacity. Assume that
209 * in active scanout the HVS and PV work in lockstep wrt. HVS
210 * refilling the fifo and PV consuming from the fifo, ie.
211 * whenever the PV consumes and frees up a scanline in the
212 * fifo, the HVS will immediately refill it, therefore
213 * incrementing vpos. Therefore we choose HVS read position -
214 * fifo size in scanlines as a estimate of the real scanout
215 * position of the PV.
216 */
217 *vpos -= fifo_lines + 1;
218
219 return ret;
220 }
221
222 /*
223 * Less: This happens when we are in vblank and the HVS, after getting
224 * the VSTART restart signal from the PV, just started refilling its
225 * fifo with new lines from the top-most lines of the new framebuffers.
226 * The PV does not scan out in vblank, so does not remove lines from
227 * the fifo, so the fifo will be full quickly and the HVS has to pause.
228 * We can't get meaningful readings wrt. scanline position of the PV
229 * and need to make things up in a approximative but consistent way.
230 */
231 vblank_lines = mode->vtotal - mode->vdisplay;
232
233 if (in_vblank_irq) {
234 /*
235 * Assume the irq handler got called close to first
236 * line of vblank, so PV has about a full vblank
237 * scanlines to go, and as a base timestamp use the
238 * one taken at entry into vblank irq handler, so it
239 * is not affected by random delays due to lock
240 * contention on event_lock or vblank_time lock in
241 * the core.
242 */
243 *vpos = -vblank_lines;
244
245 if (stime)
246 *stime = vc4_crtc->t_vblank;
247 if (etime)
248 *etime = vc4_crtc->t_vblank;
249
250 /*
251 * If the HVS fifo is not yet full then we know for certain
252 * we are at the very beginning of vblank, as the hvs just
253 * started refilling, and the stime and etime timestamps
254 * truly correspond to start of vblank.
255 *
256 * Unfortunately there's no way to report this to upper levels
257 * and make it more useful.
258 */
259 } else {
260 /*
261 * No clue where we are inside vblank. Return a vpos of zero,
262 * which will cause calling code to just return the etime
263 * timestamp uncorrected. At least this is no worse than the
264 * standard fallback.
265 */
266 *vpos = 0;
267 }
268
269 return ret;
270}
271
272static void vc4_crtc_destroy(struct drm_crtc *crtc)
273{
274 drm_crtc_cleanup(crtc);
275}
276
277static void
278vc4_crtc_lut_load(struct drm_crtc *crtc)
279{
280 struct drm_device *dev = crtc->dev;
281 struct vc4_dev *vc4 = to_vc4_dev(dev);
282 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
283 u32 i;
284
285 /* The LUT memory is laid out with each HVS channel in order,
286 * each of which takes 256 writes for R, 256 for G, then 256
287 * for B.
288 */
289 HVS_WRITE(SCALER_GAMADDR,
290 SCALER_GAMADDR_AUTOINC |
291 (vc4_crtc->channel * 3 * crtc->gamma_size));
292
293 for (i = 0; i < crtc->gamma_size; i++)
294 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
295 for (i = 0; i < crtc->gamma_size; i++)
296 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
297 for (i = 0; i < crtc->gamma_size; i++)
298 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
299}
300
301static int
302vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
303 uint32_t size,
304 struct drm_modeset_acquire_ctx *ctx)
305{
306 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
307 u32 i;
308
309 for (i = 0; i < size; i++) {
310 vc4_crtc->lut_r[i] = r[i] >> 8;
311 vc4_crtc->lut_g[i] = g[i] >> 8;
312 vc4_crtc->lut_b[i] = b[i] >> 8;
313 }
314
315 vc4_crtc_lut_load(crtc);
316
317 return 0;
318}
319
320static u32 vc4_get_fifo_full_level(u32 format)
321{
322 static const u32 fifo_len_bytes = 64;
323 static const u32 hvs_latency_pix = 6;
324
325 switch (format) {
326 case PV_CONTROL_FORMAT_DSIV_16:
327 case PV_CONTROL_FORMAT_DSIC_16:
328 return fifo_len_bytes - 2 * hvs_latency_pix;
329 case PV_CONTROL_FORMAT_DSIV_18:
330 return fifo_len_bytes - 14;
331 case PV_CONTROL_FORMAT_24:
332 case PV_CONTROL_FORMAT_DSIV_24:
333 default:
334 return fifo_len_bytes - 3 * hvs_latency_pix;
335 }
336}
337
338/*
339 * Returns the encoder attached to the CRTC.
340 *
341 * VC4 can only scan out to one encoder at a time, while the DRM core
342 * allows drivers to push pixels to more than one encoder from the
343 * same CRTC.
344 */
345static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
346{
347 struct drm_connector *connector;
348 struct drm_connector_list_iter conn_iter;
349
350 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
351 drm_for_each_connector_iter(connector, &conn_iter) {
352 if (connector->state->crtc == crtc) {
353 drm_connector_list_iter_end(&conn_iter);
354 return connector->encoder;
355 }
356 }
357 drm_connector_list_iter_end(&conn_iter);
358
359 return NULL;
360}
361
362static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
363{
364 struct drm_device *dev = crtc->dev;
365 struct vc4_dev *vc4 = to_vc4_dev(dev);
366 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
367 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
368 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
369 struct drm_crtc_state *state = crtc->state;
370 struct drm_display_mode *mode = &state->adjusted_mode;
371 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
372 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
373 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
374 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
375 u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
376 bool debug_dump_regs = false;
377
378 if (debug_dump_regs) {
379 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
380 vc4_crtc_dump_regs(vc4_crtc);
381 }
382
383 /* Reset the PV fifo. */
384 CRTC_WRITE(PV_CONTROL, 0);
385 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
386 CRTC_WRITE(PV_CONTROL, 0);
387
388 CRTC_WRITE(PV_HORZA,
389 VC4_SET_FIELD((mode->htotal -
390 mode->hsync_end) * pixel_rep,
391 PV_HORZA_HBP) |
392 VC4_SET_FIELD((mode->hsync_end -
393 mode->hsync_start) * pixel_rep,
394 PV_HORZA_HSYNC));
395 CRTC_WRITE(PV_HORZB,
396 VC4_SET_FIELD((mode->hsync_start -
397 mode->hdisplay) * pixel_rep,
398 PV_HORZB_HFP) |
399 VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
400
401 CRTC_WRITE(PV_VERTA,
402 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
403 PV_VERTA_VBP) |
404 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
405 PV_VERTA_VSYNC));
406 CRTC_WRITE(PV_VERTB,
407 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
408 PV_VERTB_VFP) |
409 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
410
411 if (interlace) {
412 CRTC_WRITE(PV_VERTA_EVEN,
413 VC4_SET_FIELD(mode->crtc_vtotal -
414 mode->crtc_vsync_end - 1,
415 PV_VERTA_VBP) |
416 VC4_SET_FIELD(mode->crtc_vsync_end -
417 mode->crtc_vsync_start,
418 PV_VERTA_VSYNC));
419 CRTC_WRITE(PV_VERTB_EVEN,
420 VC4_SET_FIELD(mode->crtc_vsync_start -
421 mode->crtc_vdisplay,
422 PV_VERTB_VFP) |
423 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
424
425 /* We set up first field even mode for HDMI. VEC's
426 * NTSC mode would want first field odd instead, once
427 * we support it (to do so, set ODD_FIRST and put the
428 * delay in VSYNCD_EVEN instead).
429 */
430 CRTC_WRITE(PV_V_CONTROL,
431 PV_VCONTROL_CONTINUOUS |
432 (is_dsi ? PV_VCONTROL_DSI : 0) |
433 PV_VCONTROL_INTERLACE |
434 VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
435 PV_VCONTROL_ODD_DELAY));
436 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
437 } else {
438 CRTC_WRITE(PV_V_CONTROL,
439 PV_VCONTROL_CONTINUOUS |
440 (is_dsi ? PV_VCONTROL_DSI : 0));
441 }
442
443 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
444
445 CRTC_WRITE(PV_CONTROL,
446 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
447 VC4_SET_FIELD(vc4_get_fifo_full_level(format),
448 PV_CONTROL_FIFO_LEVEL) |
449 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
450 PV_CONTROL_CLR_AT_START |
451 PV_CONTROL_TRIGGER_UNDERFLOW |
452 PV_CONTROL_WAIT_HSTART |
453 VC4_SET_FIELD(vc4_encoder->clock_select,
454 PV_CONTROL_CLK_SELECT) |
455 PV_CONTROL_FIFO_CLR |
456 PV_CONTROL_EN);
457
458 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
459 SCALER_DISPBKGND_AUTOHS |
460 SCALER_DISPBKGND_GAMMA |
461 (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
462
463 /* Reload the LUT, since the SRAMs would have been disabled if
464 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
465 */
466 vc4_crtc_lut_load(crtc);
467
468 if (debug_dump_regs) {
469 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
470 vc4_crtc_dump_regs(vc4_crtc);
471 }
472}
473
474static void require_hvs_enabled(struct drm_device *dev)
475{
476 struct vc4_dev *vc4 = to_vc4_dev(dev);
477
478 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
479 SCALER_DISPCTRL_ENABLE);
480}
481
482static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
483 struct drm_crtc_state *old_state)
484{
485 struct drm_device *dev = crtc->dev;
486 struct vc4_dev *vc4 = to_vc4_dev(dev);
487 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
488 u32 chan = vc4_crtc->channel;
489 int ret;
490 require_hvs_enabled(dev);
491
492 /* Disable vblank irq handling before crtc is disabled. */
493 drm_crtc_vblank_off(crtc);
494
495 CRTC_WRITE(PV_V_CONTROL,
496 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
497 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
498 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
499
500 if (HVS_READ(SCALER_DISPCTRLX(chan)) &
501 SCALER_DISPCTRLX_ENABLE) {
502 HVS_WRITE(SCALER_DISPCTRLX(chan),
503 SCALER_DISPCTRLX_RESET);
504
505 /* While the docs say that reset is self-clearing, it
506 * seems it doesn't actually.
507 */
508 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
509 }
510
511 /* Once we leave, the scaler should be disabled and its fifo empty. */
512
513 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
514
515 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
516 SCALER_DISPSTATX_MODE) !=
517 SCALER_DISPSTATX_MODE_DISABLED);
518
519 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
520 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
521 SCALER_DISPSTATX_EMPTY);
522
523 /*
524 * Make sure we issue a vblank event after disabling the CRTC if
525 * someone was waiting it.
526 */
527 if (crtc->state->event) {
528 unsigned long flags;
529
530 spin_lock_irqsave(&dev->event_lock, flags);
531 drm_crtc_send_vblank_event(crtc, crtc->state->event);
532 crtc->state->event = NULL;
533 spin_unlock_irqrestore(&dev->event_lock, flags);
534 }
535}
536
537static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
538{
539 struct drm_device *dev = crtc->dev;
540 struct vc4_dev *vc4 = to_vc4_dev(dev);
541 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
542 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
543
544 if (crtc->state->event) {
545 unsigned long flags;
546
547 crtc->state->event->pipe = drm_crtc_index(crtc);
548
549 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
550
551 spin_lock_irqsave(&dev->event_lock, flags);
552 vc4_crtc->event = crtc->state->event;
553 crtc->state->event = NULL;
554
555 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
556 vc4_state->mm.start);
557
558 spin_unlock_irqrestore(&dev->event_lock, flags);
559 } else {
560 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
561 vc4_state->mm.start);
562 }
563}
564
565static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
566 struct drm_crtc_state *old_state)
567{
568 struct drm_device *dev = crtc->dev;
569 struct vc4_dev *vc4 = to_vc4_dev(dev);
570 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
571 struct drm_crtc_state *state = crtc->state;
572 struct drm_display_mode *mode = &state->adjusted_mode;
573
574 require_hvs_enabled(dev);
575
576 /* Enable vblank irq handling before crtc is started otherwise
577 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
578 */
579 drm_crtc_vblank_on(crtc);
580 vc4_crtc_update_dlist(crtc);
581
582 /* Turn on the scaler, which will wait for vstart to start
583 * compositing.
584 */
585 HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
586 VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
587 VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
588 SCALER_DISPCTRLX_ENABLE);
589
590 /* Turn on the pixel valve, which will emit the vstart signal. */
591 CRTC_WRITE(PV_V_CONTROL,
592 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
593}
594
595static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
596 const struct drm_display_mode *mode)
597{
598 /* Do not allow doublescan modes from user space */
599 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
600 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
601 crtc->base.id);
602 return MODE_NO_DBLESCAN;
603 }
604
605 return MODE_OK;
606}
607
608static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
609 struct drm_crtc_state *state)
610{
611 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
612 struct drm_device *dev = crtc->dev;
613 struct vc4_dev *vc4 = to_vc4_dev(dev);
614 struct drm_plane *plane;
615 unsigned long flags;
616 const struct drm_plane_state *plane_state;
617 u32 dlist_count = 0;
618 int ret;
619
620 /* The pixelvalve can only feed one encoder (and encoders are
621 * 1:1 with connectors.)
622 */
623 if (hweight32(state->connector_mask) > 1)
624 return -EINVAL;
625
626 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
627 dlist_count += vc4_plane_dlist_size(plane_state);
628
629 dlist_count++; /* Account for SCALER_CTL0_END. */
630
631 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
632 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
633 dlist_count);
634 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
635 if (ret)
636 return ret;
637
638 return 0;
639}
640
641static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
642 struct drm_crtc_state *old_state)
643{
644 struct drm_device *dev = crtc->dev;
645 struct vc4_dev *vc4 = to_vc4_dev(dev);
646 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
647 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
648 struct drm_plane *plane;
649 struct vc4_plane_state *vc4_plane_state;
650 bool debug_dump_regs = false;
651 bool enable_bg_fill = false;
652 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
653 u32 __iomem *dlist_next = dlist_start;
654
655 if (debug_dump_regs) {
656 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
657 vc4_hvs_dump_state(dev);
658 }
659
660 /* Copy all the active planes' dlist contents to the hardware dlist. */
661 drm_atomic_crtc_for_each_plane(plane, crtc) {
662 /* Is this the first active plane? */
663 if (dlist_next == dlist_start) {
664 /* We need to enable background fill when a plane
665 * could be alpha blending from the background, i.e.
666 * where no other plane is underneath. It suffices to
667 * consider the first active plane here since we set
668 * needs_bg_fill such that either the first plane
669 * already needs it or all planes on top blend from
670 * the first or a lower plane.
671 */
672 vc4_plane_state = to_vc4_plane_state(plane->state);
673 enable_bg_fill = vc4_plane_state->needs_bg_fill;
674 }
675
676 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
677 }
678
679 writel(SCALER_CTL0_END, dlist_next);
680 dlist_next++;
681
682 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
683
684 if (enable_bg_fill)
685 /* This sets a black background color fill, as is the case
686 * with other DRM drivers.
687 */
688 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
689 HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
690 SCALER_DISPBKGND_FILL);
691
692 /* Only update DISPLIST if the CRTC was already running and is not
693 * being disabled.
694 * vc4_crtc_enable() takes care of updating the dlist just after
695 * re-enabling VBLANK interrupts and before enabling the engine.
696 * If the CRTC is being disabled, there's no point in updating this
697 * information.
698 */
699 if (crtc->state->active && old_state->active)
700 vc4_crtc_update_dlist(crtc);
701
702 if (debug_dump_regs) {
703 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
704 vc4_hvs_dump_state(dev);
705 }
706}
707
708static int vc4_enable_vblank(struct drm_crtc *crtc)
709{
710 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
711
712 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
713
714 return 0;
715}
716
717static void vc4_disable_vblank(struct drm_crtc *crtc)
718{
719 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
720
721 CRTC_WRITE(PV_INTEN, 0);
722}
723
724static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
725{
726 struct drm_crtc *crtc = &vc4_crtc->base;
727 struct drm_device *dev = crtc->dev;
728 struct vc4_dev *vc4 = to_vc4_dev(dev);
729 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
730 u32 chan = vc4_crtc->channel;
731 unsigned long flags;
732
733 spin_lock_irqsave(&dev->event_lock, flags);
734 if (vc4_crtc->event &&
735 (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
736 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
737 vc4_crtc->event = NULL;
738 drm_crtc_vblank_put(crtc);
739 }
740 spin_unlock_irqrestore(&dev->event_lock, flags);
741}
742
743static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
744{
745 struct vc4_crtc *vc4_crtc = data;
746 u32 stat = CRTC_READ(PV_INTSTAT);
747 irqreturn_t ret = IRQ_NONE;
748
749 if (stat & PV_INT_VFP_START) {
750 vc4_crtc->t_vblank = ktime_get();
751 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
752 drm_crtc_handle_vblank(&vc4_crtc->base);
753 vc4_crtc_handle_page_flip(vc4_crtc);
754 ret = IRQ_HANDLED;
755 }
756
757 return ret;
758}
759
760struct vc4_async_flip_state {
761 struct drm_crtc *crtc;
762 struct drm_framebuffer *fb;
763 struct drm_framebuffer *old_fb;
764 struct drm_pending_vblank_event *event;
765
766 struct vc4_seqno_cb cb;
767};
768
769/* Called when the V3D execution for the BO being flipped to is done, so that
770 * we can actually update the plane's address to point to it.
771 */
772static void
773vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
774{
775 struct vc4_async_flip_state *flip_state =
776 container_of(cb, struct vc4_async_flip_state, cb);
777 struct drm_crtc *crtc = flip_state->crtc;
778 struct drm_device *dev = crtc->dev;
779 struct vc4_dev *vc4 = to_vc4_dev(dev);
780 struct drm_plane *plane = crtc->primary;
781
782 vc4_plane_async_set_fb(plane, flip_state->fb);
783 if (flip_state->event) {
784 unsigned long flags;
785
786 spin_lock_irqsave(&dev->event_lock, flags);
787 drm_crtc_send_vblank_event(crtc, flip_state->event);
788 spin_unlock_irqrestore(&dev->event_lock, flags);
789 }
790
791 drm_crtc_vblank_put(crtc);
792 drm_framebuffer_put(flip_state->fb);
793
794 /* Decrement the BO usecnt in order to keep the inc/dec calls balanced
795 * when the planes are updated through the async update path.
796 * FIXME: we should move to generic async-page-flip when it's
797 * available, so that we can get rid of this hand-made cleanup_fb()
798 * logic.
799 */
800 if (flip_state->old_fb) {
801 struct drm_gem_cma_object *cma_bo;
802 struct vc4_bo *bo;
803
804 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
805 bo = to_vc4_bo(&cma_bo->base);
806 vc4_bo_dec_usecnt(bo);
807 drm_framebuffer_put(flip_state->old_fb);
808 }
809
810 kfree(flip_state);
811
812 up(&vc4->async_modeset);
813}
814
815/* Implements async (non-vblank-synced) page flips.
816 *
817 * The page flip ioctl needs to return immediately, so we grab the
818 * modeset semaphore on the pipe, and queue the address update for
819 * when V3D is done with the BO being flipped to.
820 */
821static int vc4_async_page_flip(struct drm_crtc *crtc,
822 struct drm_framebuffer *fb,
823 struct drm_pending_vblank_event *event,
824 uint32_t flags)
825{
826 struct drm_device *dev = crtc->dev;
827 struct vc4_dev *vc4 = to_vc4_dev(dev);
828 struct drm_plane *plane = crtc->primary;
829 int ret = 0;
830 struct vc4_async_flip_state *flip_state;
831 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
832 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
833
834 /* Increment the BO usecnt here, so that we never end up with an
835 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
836 * plane is later updated through the non-async path.
837 * FIXME: we should move to generic async-page-flip when it's
838 * available, so that we can get rid of this hand-made prepare_fb()
839 * logic.
840 */
841 ret = vc4_bo_inc_usecnt(bo);
842 if (ret)
843 return ret;
844
845 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
846 if (!flip_state) {
847 vc4_bo_dec_usecnt(bo);
848 return -ENOMEM;
849 }
850
851 drm_framebuffer_get(fb);
852 flip_state->fb = fb;
853 flip_state->crtc = crtc;
854 flip_state->event = event;
855
856 /* Make sure all other async modesetes have landed. */
857 ret = down_interruptible(&vc4->async_modeset);
858 if (ret) {
859 drm_framebuffer_put(fb);
860 vc4_bo_dec_usecnt(bo);
861 kfree(flip_state);
862 return ret;
863 }
864
865 /* Save the current FB before it's replaced by the new one in
866 * drm_atomic_set_fb_for_plane(). We'll need the old FB in
867 * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
868 * it consistent.
869 * FIXME: we should move to generic async-page-flip when it's
870 * available, so that we can get rid of this hand-made cleanup_fb()
871 * logic.
872 */
873 flip_state->old_fb = plane->state->fb;
874 if (flip_state->old_fb)
875 drm_framebuffer_get(flip_state->old_fb);
876
877 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
878
879 /* Immediately update the plane's legacy fb pointer, so that later
880 * modeset prep sees the state that will be present when the semaphore
881 * is released.
882 */
883 drm_atomic_set_fb_for_plane(plane->state, fb);
884 plane->fb = fb;
885
886 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
887 vc4_async_page_flip_complete);
888
889 /* Driver takes ownership of state on successful async commit. */
890 return 0;
891}
892
893static int vc4_page_flip(struct drm_crtc *crtc,
894 struct drm_framebuffer *fb,
895 struct drm_pending_vblank_event *event,
896 uint32_t flags,
897 struct drm_modeset_acquire_ctx *ctx)
898{
899 if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
900 return vc4_async_page_flip(crtc, fb, event, flags);
901 else
902 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
903}
904
905static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
906{
907 struct vc4_crtc_state *vc4_state;
908
909 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
910 if (!vc4_state)
911 return NULL;
912
913 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
914 return &vc4_state->base;
915}
916
917static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
918 struct drm_crtc_state *state)
919{
920 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
921 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
922
923 if (vc4_state->mm.allocated) {
924 unsigned long flags;
925
926 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
927 drm_mm_remove_node(&vc4_state->mm);
928 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
929
930 }
931
932 drm_atomic_helper_crtc_destroy_state(crtc, state);
933}
934
935static void
936vc4_crtc_reset(struct drm_crtc *crtc)
937{
938 if (crtc->state)
939 __drm_atomic_helper_crtc_destroy_state(crtc->state);
940
941 crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
942 if (crtc->state)
943 crtc->state->crtc = crtc;
944}
945
946static const struct drm_crtc_funcs vc4_crtc_funcs = {
947 .set_config = drm_atomic_helper_set_config,
948 .destroy = vc4_crtc_destroy,
949 .page_flip = vc4_page_flip,
950 .set_property = NULL,
951 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
952 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
953 .reset = vc4_crtc_reset,
954 .atomic_duplicate_state = vc4_crtc_duplicate_state,
955 .atomic_destroy_state = vc4_crtc_destroy_state,
956 .gamma_set = vc4_crtc_gamma_set,
957 .enable_vblank = vc4_enable_vblank,
958 .disable_vblank = vc4_disable_vblank,
959};
960
961static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
962 .mode_set_nofb = vc4_crtc_mode_set_nofb,
963 .mode_valid = vc4_crtc_mode_valid,
964 .atomic_check = vc4_crtc_atomic_check,
965 .atomic_flush = vc4_crtc_atomic_flush,
966 .atomic_enable = vc4_crtc_atomic_enable,
967 .atomic_disable = vc4_crtc_atomic_disable,
968};
969
970static const struct vc4_crtc_data pv0_data = {
971 .hvs_channel = 0,
972 .encoder_types = {
973 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
974 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
975 },
976};
977
978static const struct vc4_crtc_data pv1_data = {
979 .hvs_channel = 2,
980 .encoder_types = {
981 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
982 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
983 },
984};
985
986static const struct vc4_crtc_data pv2_data = {
987 .hvs_channel = 1,
988 .encoder_types = {
989 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
990 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
991 },
992};
993
994static const struct of_device_id vc4_crtc_dt_match[] = {
995 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
996 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
997 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
998 {}
999};
1000
1001static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1002 struct drm_crtc *crtc)
1003{
1004 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1005 const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
1006 const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
1007 struct drm_encoder *encoder;
1008
1009 drm_for_each_encoder(encoder, drm) {
1010 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
1011 int i;
1012
1013 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
1014 if (vc4_encoder->type == encoder_types[i]) {
1015 vc4_encoder->clock_select = i;
1016 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1017 break;
1018 }
1019 }
1020 }
1021}
1022
1023static void
1024vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
1025{
1026 struct drm_device *drm = vc4_crtc->base.dev;
1027 struct vc4_dev *vc4 = to_vc4_dev(drm);
1028 u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
1029 /* Top/base are supposed to be 4-pixel aligned, but the
1030 * Raspberry Pi firmware fills the low bits (which are
1031 * presumably ignored).
1032 */
1033 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
1034 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
1035
1036 vc4_crtc->cob_size = top - base + 4;
1037}
1038
1039static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1040{
1041 struct platform_device *pdev = to_platform_device(dev);
1042 struct drm_device *drm = dev_get_drvdata(master);
1043 struct vc4_crtc *vc4_crtc;
1044 struct drm_crtc *crtc;
1045 struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
1046 const struct of_device_id *match;
1047 int ret, i;
1048
1049 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1050 if (!vc4_crtc)
1051 return -ENOMEM;
1052 crtc = &vc4_crtc->base;
1053
1054 match = of_match_device(vc4_crtc_dt_match, dev);
1055 if (!match)
1056 return -ENODEV;
1057 vc4_crtc->data = match->data;
1058
1059 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1060 if (IS_ERR(vc4_crtc->regs))
1061 return PTR_ERR(vc4_crtc->regs);
1062
1063 /* For now, we create just the primary and the legacy cursor
1064 * planes. We should be able to stack more planes on easily,
1065 * but to do that we would need to compute the bandwidth
1066 * requirement of the plane configuration, and reject ones
1067 * that will take too much.
1068 */
1069 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1070 if (IS_ERR(primary_plane)) {
1071 dev_err(dev, "failed to construct primary plane\n");
1072 ret = PTR_ERR(primary_plane);
1073 goto err;
1074 }
1075
1076 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1077 &vc4_crtc_funcs, NULL);
1078 drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
1079 primary_plane->crtc = crtc;
1080 vc4_crtc->channel = vc4_crtc->data->hvs_channel;
1081 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1082
1083 /* Set up some arbitrary number of planes. We're not limited
1084 * by a set number of physical registers, just the space in
1085 * the HVS (16k) and how small an plane can be (28 bytes).
1086 * However, each plane we set up takes up some memory, and
1087 * increases the cost of looping over planes, which atomic
1088 * modesetting does quite a bit. As a result, we pick a
1089 * modest number of planes to expose, that should hopefully
1090 * still cover any sane usecase.
1091 */
1092 for (i = 0; i < 8; i++) {
1093 struct drm_plane *plane =
1094 vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
1095
1096 if (IS_ERR(plane))
1097 continue;
1098
1099 plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1100 }
1101
1102 /* Set up the legacy cursor after overlay initialization,
1103 * since we overlay planes on the CRTC in the order they were
1104 * initialized.
1105 */
1106 cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1107 if (!IS_ERR(cursor_plane)) {
1108 cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1109 cursor_plane->crtc = crtc;
1110 crtc->cursor = cursor_plane;
1111 }
1112
1113 vc4_crtc_get_cob_allocation(vc4_crtc);
1114
1115 CRTC_WRITE(PV_INTEN, 0);
1116 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1117 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1118 vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1119 if (ret)
1120 goto err_destroy_planes;
1121
1122 vc4_set_crtc_possible_masks(drm, crtc);
1123
1124 for (i = 0; i < crtc->gamma_size; i++) {
1125 vc4_crtc->lut_r[i] = i;
1126 vc4_crtc->lut_g[i] = i;
1127 vc4_crtc->lut_b[i] = i;
1128 }
1129
1130 platform_set_drvdata(pdev, vc4_crtc);
1131
1132 return 0;
1133
1134err_destroy_planes:
1135 list_for_each_entry_safe(destroy_plane, temp,
1136 &drm->mode_config.plane_list, head) {
1137 if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
1138 destroy_plane->funcs->destroy(destroy_plane);
1139 }
1140err:
1141 return ret;
1142}
1143
1144static void vc4_crtc_unbind(struct device *dev, struct device *master,
1145 void *data)
1146{
1147 struct platform_device *pdev = to_platform_device(dev);
1148 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1149
1150 vc4_crtc_destroy(&vc4_crtc->base);
1151
1152 CRTC_WRITE(PV_INTEN, 0);
1153
1154 platform_set_drvdata(pdev, NULL);
1155}
1156
1157static const struct component_ops vc4_crtc_ops = {
1158 .bind = vc4_crtc_bind,
1159 .unbind = vc4_crtc_unbind,
1160};
1161
1162static int vc4_crtc_dev_probe(struct platform_device *pdev)
1163{
1164 return component_add(&pdev->dev, &vc4_crtc_ops);
1165}
1166
1167static int vc4_crtc_dev_remove(struct platform_device *pdev)
1168{
1169 component_del(&pdev->dev, &vc4_crtc_ops);
1170 return 0;
1171}
1172
1173struct platform_driver vc4_crtc_driver = {
1174 .probe = vc4_crtc_dev_probe,
1175 .remove = vc4_crtc_dev_remove,
1176 .driver = {
1177 .name = "vc4_crtc",
1178 .of_match_table = vc4_crtc_dt_match,
1179 },
1180};