1/* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  2 *
  3 * This program is free software; you can redistribute it and/or modify
  4 * it under the terms of the GNU General Public License version 2 and
  5 * only version 2 as published by the Free Software Foundation.
  6 *
  7 * This program is distributed in the hope that it will be useful,
  8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 10 * GNU General Public License for more details.
 11 *
 12 */
 13#ifndef __A5XX_GPU_H__
 14#define __A5XX_GPU_H__
 15
 16#include "adreno_gpu.h"
 17
 18/* Bringing over the hack from the previous targets */
 19#undef ROP_COPY
 20#undef ROP_XOR
 21
 22#include "a5xx.xml.h"
 23
 24struct a5xx_gpu {
 25	struct adreno_gpu base;
 26
 27	struct drm_gem_object *pm4_bo;
 28	uint64_t pm4_iova;
 29
 30	struct drm_gem_object *pfp_bo;
 31	uint64_t pfp_iova;
 32
 33	struct drm_gem_object *gpmu_bo;
 34	uint64_t gpmu_iova;
 35	uint32_t gpmu_dwords;
 36
 37	uint32_t lm_leakage;
 38
 39	struct msm_ringbuffer *cur_ring;
 40	struct msm_ringbuffer *next_ring;
 41
 42	struct drm_gem_object *preempt_bo[MSM_GPU_MAX_RINGS];
 43	struct a5xx_preempt_record *preempt[MSM_GPU_MAX_RINGS];
 44	uint64_t preempt_iova[MSM_GPU_MAX_RINGS];
 45
 46	atomic_t preempt_state;
 47	struct timer_list preempt_timer;
 48};
 49
 50#define to_a5xx_gpu(x) container_of(x, struct a5xx_gpu, base)
 51
 52#ifdef CONFIG_DEBUG_FS
 53int a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor);
 54#endif
 55
 56/*
 57 * In order to do lockless preemption we use a simple state machine to progress
 58 * through the process.
 59 *
 60 * PREEMPT_NONE - no preemption in progress.  Next state START.
 61 * PREEMPT_START - The trigger is evaulating if preemption is possible. Next
 62 * states: TRIGGERED, NONE
 63 * PREEMPT_ABORT - An intermediate state before moving back to NONE. Next
 64 * state: NONE.
 65 * PREEMPT_TRIGGERED: A preemption has been executed on the hardware. Next
 66 * states: FAULTED, PENDING
 67 * PREEMPT_FAULTED: A preemption timed out (never completed). This will trigger
 68 * recovery.  Next state: N/A
 69 * PREEMPT_PENDING: Preemption complete interrupt fired - the callback is
 70 * checking the success of the operation. Next state: FAULTED, NONE.
 71 */
 72
 73enum preempt_state {
 74	PREEMPT_NONE = 0,
 75	PREEMPT_START,
 76	PREEMPT_ABORT,
 77	PREEMPT_TRIGGERED,
 78	PREEMPT_FAULTED,
 79	PREEMPT_PENDING,
 80};
 81
 82/*
 83 * struct a5xx_preempt_record is a shared buffer between the microcode and the
 84 * CPU to store the state for preemption. The record itself is much larger
 85 * (64k) but most of that is used by the CP for storage.
 86 *
 87 * There is a preemption record assigned per ringbuffer. When the CPU triggers a
 88 * preemption, it fills out the record with the useful information (wptr, ring
 89 * base, etc) and the microcode uses that information to set up the CP following
 90 * the preemption.  When a ring is switched out, the CP will save the ringbuffer
 91 * state back to the record. In this way, once the records are properly set up
 92 * the CPU can quickly switch back and forth between ringbuffers by only
 93 * updating a few registers (often only the wptr).
 94 *
 95 * These are the CPU aware registers in the record:
 96 * @magic: Must always be 0x27C4BAFC
 97 * @info: Type of the record - written 0 by the CPU, updated by the CP
 98 * @data: Data field from SET_RENDER_MODE or a checkpoint. Written and used by
 99 * the CP
100 * @cntl: Value of RB_CNTL written by CPU, save/restored by CP
101 * @rptr: Value of RB_RPTR written by CPU, save/restored by CP
102 * @wptr: Value of RB_WPTR written by CPU, save/restored by CP
103 * @rptr_addr: Value of RB_RPTR_ADDR written by CPU, save/restored by CP
104 * @rbase: Value of RB_BASE written by CPU, save/restored by CP
105 * @counter: GPU address of the storage area for the performance counters
106 */
107struct a5xx_preempt_record {
108	uint32_t magic;
109	uint32_t info;
110	uint32_t data;
111	uint32_t cntl;
112	uint32_t rptr;
113	uint32_t wptr;
114	uint64_t rptr_addr;
115	uint64_t rbase;
116	uint64_t counter;
117};
118
119/* Magic identifier for the preemption record */
120#define A5XX_PREEMPT_RECORD_MAGIC 0x27C4BAFCUL
121
122/*
123 * Even though the structure above is only a few bytes, we need a full 64k to
124 * store the entire preemption record from the CP
125 */
126#define A5XX_PREEMPT_RECORD_SIZE (64 * 1024)
127
128/*
129 * The preemption counter block is a storage area for the value of the
130 * preemption counters that are saved immediately before context switch. We
131 * append it on to the end of the allocation for the preemption record.
132 */
133#define A5XX_PREEMPT_COUNTER_SIZE (16 * 4)
134
135
136int a5xx_power_init(struct msm_gpu *gpu);
137void a5xx_gpmu_ucode_init(struct msm_gpu *gpu);
138
139static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs,
140		uint32_t reg, uint32_t mask, uint32_t value)
141{
142	while (usecs--) {
143		udelay(1);
144		if ((gpu_read(gpu, reg) & mask) == value)
145			return 0;
146		cpu_relax();
147	}
148
149	return -ETIMEDOUT;
150}
151
152bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
153void a5xx_set_hwcg(struct msm_gpu *gpu, bool state);
154
155void a5xx_preempt_init(struct msm_gpu *gpu);
156void a5xx_preempt_hw_init(struct msm_gpu *gpu);
157void a5xx_preempt_trigger(struct msm_gpu *gpu);
158void a5xx_preempt_irq(struct msm_gpu *gpu);
159void a5xx_preempt_fini(struct msm_gpu *gpu);
160
161/* Return true if we are in a preempt state */
162static inline bool a5xx_in_preempt(struct a5xx_gpu *a5xx_gpu)
163{
164	int preempt_state = atomic_read(&a5xx_gpu->preempt_state);
165
166	return !(preempt_state == PREEMPT_NONE ||
167			preempt_state == PREEMPT_ABORT);
168}
169
170#endif /* __A5XX_GPU_H__ */