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1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include <linux/cpufreq.h>
29#include "i915_drv.h"
30#include "intel_drv.h"
31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
33
34/**
35 * DOC: RC6
36 *
37 * RC6 is a special power stage which allows the GPU to enter an very
38 * low-voltage mode when idle, using down to 0V while at this stage. This
39 * stage is entered automatically when the GPU is idle when RC6 support is
40 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
41 *
42 * There are different RC6 modes available in Intel GPU, which differentiate
43 * among each other with the latency required to enter and leave RC6 and
44 * voltage consumed by the GPU in different states.
45 *
46 * The combination of the following flags define which states GPU is allowed
47 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
48 * RC6pp is deepest RC6. Their support by hardware varies according to the
49 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
50 * which brings the most power savings; deeper states save more power, but
51 * require higher latency to switch to and wake up.
52 */
53#define INTEL_RC6_ENABLE (1<<0)
54#define INTEL_RC6p_ENABLE (1<<1)
55#define INTEL_RC6pp_ENABLE (1<<2)
56
57static void bxt_init_clock_gating(struct drm_device *dev)
58{
59 struct drm_i915_private *dev_priv = dev->dev_private;
60
61 /* WaDisableSDEUnitClockGating:bxt */
62 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
63 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
64
65 /*
66 * FIXME:
67 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
68 */
69 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
70 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
71
72 /*
73 * Wa: Backlight PWM may stop in the asserted state, causing backlight
74 * to stay fully on.
75 */
76 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
77 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
78 PWM1_GATING_DIS | PWM2_GATING_DIS);
79}
80
81static void i915_pineview_get_mem_freq(struct drm_device *dev)
82{
83 struct drm_i915_private *dev_priv = dev->dev_private;
84 u32 tmp;
85
86 tmp = I915_READ(CLKCFG);
87
88 switch (tmp & CLKCFG_FSB_MASK) {
89 case CLKCFG_FSB_533:
90 dev_priv->fsb_freq = 533; /* 133*4 */
91 break;
92 case CLKCFG_FSB_800:
93 dev_priv->fsb_freq = 800; /* 200*4 */
94 break;
95 case CLKCFG_FSB_667:
96 dev_priv->fsb_freq = 667; /* 167*4 */
97 break;
98 case CLKCFG_FSB_400:
99 dev_priv->fsb_freq = 400; /* 100*4 */
100 break;
101 }
102
103 switch (tmp & CLKCFG_MEM_MASK) {
104 case CLKCFG_MEM_533:
105 dev_priv->mem_freq = 533;
106 break;
107 case CLKCFG_MEM_667:
108 dev_priv->mem_freq = 667;
109 break;
110 case CLKCFG_MEM_800:
111 dev_priv->mem_freq = 800;
112 break;
113 }
114
115 /* detect pineview DDR3 setting */
116 tmp = I915_READ(CSHRDDR3CTL);
117 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
118}
119
120static void i915_ironlake_get_mem_freq(struct drm_device *dev)
121{
122 struct drm_i915_private *dev_priv = dev->dev_private;
123 u16 ddrpll, csipll;
124
125 ddrpll = I915_READ16(DDRMPLL1);
126 csipll = I915_READ16(CSIPLL0);
127
128 switch (ddrpll & 0xff) {
129 case 0xc:
130 dev_priv->mem_freq = 800;
131 break;
132 case 0x10:
133 dev_priv->mem_freq = 1066;
134 break;
135 case 0x14:
136 dev_priv->mem_freq = 1333;
137 break;
138 case 0x18:
139 dev_priv->mem_freq = 1600;
140 break;
141 default:
142 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
143 ddrpll & 0xff);
144 dev_priv->mem_freq = 0;
145 break;
146 }
147
148 dev_priv->ips.r_t = dev_priv->mem_freq;
149
150 switch (csipll & 0x3ff) {
151 case 0x00c:
152 dev_priv->fsb_freq = 3200;
153 break;
154 case 0x00e:
155 dev_priv->fsb_freq = 3733;
156 break;
157 case 0x010:
158 dev_priv->fsb_freq = 4266;
159 break;
160 case 0x012:
161 dev_priv->fsb_freq = 4800;
162 break;
163 case 0x014:
164 dev_priv->fsb_freq = 5333;
165 break;
166 case 0x016:
167 dev_priv->fsb_freq = 5866;
168 break;
169 case 0x018:
170 dev_priv->fsb_freq = 6400;
171 break;
172 default:
173 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
174 csipll & 0x3ff);
175 dev_priv->fsb_freq = 0;
176 break;
177 }
178
179 if (dev_priv->fsb_freq == 3200) {
180 dev_priv->ips.c_m = 0;
181 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
182 dev_priv->ips.c_m = 1;
183 } else {
184 dev_priv->ips.c_m = 2;
185 }
186}
187
188static const struct cxsr_latency cxsr_latency_table[] = {
189 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
190 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
191 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
192 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
193 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
194
195 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
196 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
197 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
198 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
199 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
200
201 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
202 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
203 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
204 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
205 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
206
207 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
208 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
209 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
210 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
211 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
212
213 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
214 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
215 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
216 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
217 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
218
219 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
220 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
221 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
222 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
223 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
224};
225
226static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
227 int is_ddr3,
228 int fsb,
229 int mem)
230{
231 const struct cxsr_latency *latency;
232 int i;
233
234 if (fsb == 0 || mem == 0)
235 return NULL;
236
237 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
238 latency = &cxsr_latency_table[i];
239 if (is_desktop == latency->is_desktop &&
240 is_ddr3 == latency->is_ddr3 &&
241 fsb == latency->fsb_freq && mem == latency->mem_freq)
242 return latency;
243 }
244
245 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
246
247 return NULL;
248}
249
250static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
251{
252 u32 val;
253
254 mutex_lock(&dev_priv->rps.hw_lock);
255
256 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
257 if (enable)
258 val &= ~FORCE_DDR_HIGH_FREQ;
259 else
260 val |= FORCE_DDR_HIGH_FREQ;
261 val &= ~FORCE_DDR_LOW_FREQ;
262 val |= FORCE_DDR_FREQ_REQ_ACK;
263 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
264
265 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
266 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
267 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
268
269 mutex_unlock(&dev_priv->rps.hw_lock);
270}
271
272static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
273{
274 u32 val;
275
276 mutex_lock(&dev_priv->rps.hw_lock);
277
278 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
279 if (enable)
280 val |= DSP_MAXFIFO_PM5_ENABLE;
281 else
282 val &= ~DSP_MAXFIFO_PM5_ENABLE;
283 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
284
285 mutex_unlock(&dev_priv->rps.hw_lock);
286}
287
288#define FW_WM(value, plane) \
289 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
290
291void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
292{
293 struct drm_device *dev = dev_priv->dev;
294 u32 val;
295
296 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
297 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
298 POSTING_READ(FW_BLC_SELF_VLV);
299 dev_priv->wm.vlv.cxsr = enable;
300 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
301 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
302 POSTING_READ(FW_BLC_SELF);
303 } else if (IS_PINEVIEW(dev)) {
304 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
305 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
306 I915_WRITE(DSPFW3, val);
307 POSTING_READ(DSPFW3);
308 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
309 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
310 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
311 I915_WRITE(FW_BLC_SELF, val);
312 POSTING_READ(FW_BLC_SELF);
313 } else if (IS_I915GM(dev)) {
314 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
315 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
316 I915_WRITE(INSTPM, val);
317 POSTING_READ(INSTPM);
318 } else {
319 return;
320 }
321
322 DRM_DEBUG_KMS("memory self-refresh is %s\n",
323 enable ? "enabled" : "disabled");
324}
325
326
327/*
328 * Latency for FIFO fetches is dependent on several factors:
329 * - memory configuration (speed, channels)
330 * - chipset
331 * - current MCH state
332 * It can be fairly high in some situations, so here we assume a fairly
333 * pessimal value. It's a tradeoff between extra memory fetches (if we
334 * set this value too high, the FIFO will fetch frequently to stay full)
335 * and power consumption (set it too low to save power and we might see
336 * FIFO underruns and display "flicker").
337 *
338 * A value of 5us seems to be a good balance; safe for very low end
339 * platforms but not overly aggressive on lower latency configs.
340 */
341static const int pessimal_latency_ns = 5000;
342
343#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
344 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
345
346static int vlv_get_fifo_size(struct drm_device *dev,
347 enum pipe pipe, int plane)
348{
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 int sprite0_start, sprite1_start, size;
351
352 switch (pipe) {
353 uint32_t dsparb, dsparb2, dsparb3;
354 case PIPE_A:
355 dsparb = I915_READ(DSPARB);
356 dsparb2 = I915_READ(DSPARB2);
357 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
358 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
359 break;
360 case PIPE_B:
361 dsparb = I915_READ(DSPARB);
362 dsparb2 = I915_READ(DSPARB2);
363 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
364 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
365 break;
366 case PIPE_C:
367 dsparb2 = I915_READ(DSPARB2);
368 dsparb3 = I915_READ(DSPARB3);
369 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
370 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
371 break;
372 default:
373 return 0;
374 }
375
376 switch (plane) {
377 case 0:
378 size = sprite0_start;
379 break;
380 case 1:
381 size = sprite1_start - sprite0_start;
382 break;
383 case 2:
384 size = 512 - 1 - sprite1_start;
385 break;
386 default:
387 return 0;
388 }
389
390 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
391 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
392 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
393 size);
394
395 return size;
396}
397
398static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
399{
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t dsparb = I915_READ(DSPARB);
402 int size;
403
404 size = dsparb & 0x7f;
405 if (plane)
406 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
407
408 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
409 plane ? "B" : "A", size);
410
411 return size;
412}
413
414static int i830_get_fifo_size(struct drm_device *dev, int plane)
415{
416 struct drm_i915_private *dev_priv = dev->dev_private;
417 uint32_t dsparb = I915_READ(DSPARB);
418 int size;
419
420 size = dsparb & 0x1ff;
421 if (plane)
422 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
423 size >>= 1; /* Convert to cachelines */
424
425 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
426 plane ? "B" : "A", size);
427
428 return size;
429}
430
431static int i845_get_fifo_size(struct drm_device *dev, int plane)
432{
433 struct drm_i915_private *dev_priv = dev->dev_private;
434 uint32_t dsparb = I915_READ(DSPARB);
435 int size;
436
437 size = dsparb & 0x7f;
438 size >>= 2; /* Convert to cachelines */
439
440 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
441 plane ? "B" : "A",
442 size);
443
444 return size;
445}
446
447/* Pineview has different values for various configs */
448static const struct intel_watermark_params pineview_display_wm = {
449 .fifo_size = PINEVIEW_DISPLAY_FIFO,
450 .max_wm = PINEVIEW_MAX_WM,
451 .default_wm = PINEVIEW_DFT_WM,
452 .guard_size = PINEVIEW_GUARD_WM,
453 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
454};
455static const struct intel_watermark_params pineview_display_hplloff_wm = {
456 .fifo_size = PINEVIEW_DISPLAY_FIFO,
457 .max_wm = PINEVIEW_MAX_WM,
458 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
459 .guard_size = PINEVIEW_GUARD_WM,
460 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
461};
462static const struct intel_watermark_params pineview_cursor_wm = {
463 .fifo_size = PINEVIEW_CURSOR_FIFO,
464 .max_wm = PINEVIEW_CURSOR_MAX_WM,
465 .default_wm = PINEVIEW_CURSOR_DFT_WM,
466 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
467 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
468};
469static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
470 .fifo_size = PINEVIEW_CURSOR_FIFO,
471 .max_wm = PINEVIEW_CURSOR_MAX_WM,
472 .default_wm = PINEVIEW_CURSOR_DFT_WM,
473 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
474 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
475};
476static const struct intel_watermark_params g4x_wm_info = {
477 .fifo_size = G4X_FIFO_SIZE,
478 .max_wm = G4X_MAX_WM,
479 .default_wm = G4X_MAX_WM,
480 .guard_size = 2,
481 .cacheline_size = G4X_FIFO_LINE_SIZE,
482};
483static const struct intel_watermark_params g4x_cursor_wm_info = {
484 .fifo_size = I965_CURSOR_FIFO,
485 .max_wm = I965_CURSOR_MAX_WM,
486 .default_wm = I965_CURSOR_DFT_WM,
487 .guard_size = 2,
488 .cacheline_size = G4X_FIFO_LINE_SIZE,
489};
490static const struct intel_watermark_params valleyview_wm_info = {
491 .fifo_size = VALLEYVIEW_FIFO_SIZE,
492 .max_wm = VALLEYVIEW_MAX_WM,
493 .default_wm = VALLEYVIEW_MAX_WM,
494 .guard_size = 2,
495 .cacheline_size = G4X_FIFO_LINE_SIZE,
496};
497static const struct intel_watermark_params valleyview_cursor_wm_info = {
498 .fifo_size = I965_CURSOR_FIFO,
499 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
500 .default_wm = I965_CURSOR_DFT_WM,
501 .guard_size = 2,
502 .cacheline_size = G4X_FIFO_LINE_SIZE,
503};
504static const struct intel_watermark_params i965_cursor_wm_info = {
505 .fifo_size = I965_CURSOR_FIFO,
506 .max_wm = I965_CURSOR_MAX_WM,
507 .default_wm = I965_CURSOR_DFT_WM,
508 .guard_size = 2,
509 .cacheline_size = I915_FIFO_LINE_SIZE,
510};
511static const struct intel_watermark_params i945_wm_info = {
512 .fifo_size = I945_FIFO_SIZE,
513 .max_wm = I915_MAX_WM,
514 .default_wm = 1,
515 .guard_size = 2,
516 .cacheline_size = I915_FIFO_LINE_SIZE,
517};
518static const struct intel_watermark_params i915_wm_info = {
519 .fifo_size = I915_FIFO_SIZE,
520 .max_wm = I915_MAX_WM,
521 .default_wm = 1,
522 .guard_size = 2,
523 .cacheline_size = I915_FIFO_LINE_SIZE,
524};
525static const struct intel_watermark_params i830_a_wm_info = {
526 .fifo_size = I855GM_FIFO_SIZE,
527 .max_wm = I915_MAX_WM,
528 .default_wm = 1,
529 .guard_size = 2,
530 .cacheline_size = I830_FIFO_LINE_SIZE,
531};
532static const struct intel_watermark_params i830_bc_wm_info = {
533 .fifo_size = I855GM_FIFO_SIZE,
534 .max_wm = I915_MAX_WM/2,
535 .default_wm = 1,
536 .guard_size = 2,
537 .cacheline_size = I830_FIFO_LINE_SIZE,
538};
539static const struct intel_watermark_params i845_wm_info = {
540 .fifo_size = I830_FIFO_SIZE,
541 .max_wm = I915_MAX_WM,
542 .default_wm = 1,
543 .guard_size = 2,
544 .cacheline_size = I830_FIFO_LINE_SIZE,
545};
546
547/**
548 * intel_calculate_wm - calculate watermark level
549 * @clock_in_khz: pixel clock
550 * @wm: chip FIFO params
551 * @cpp: bytes per pixel
552 * @latency_ns: memory latency for the platform
553 *
554 * Calculate the watermark level (the level at which the display plane will
555 * start fetching from memory again). Each chip has a different display
556 * FIFO size and allocation, so the caller needs to figure that out and pass
557 * in the correct intel_watermark_params structure.
558 *
559 * As the pixel clock runs, the FIFO will be drained at a rate that depends
560 * on the pixel size. When it reaches the watermark level, it'll start
561 * fetching FIFO line sized based chunks from memory until the FIFO fills
562 * past the watermark point. If the FIFO drains completely, a FIFO underrun
563 * will occur, and a display engine hang could result.
564 */
565static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
566 const struct intel_watermark_params *wm,
567 int fifo_size, int cpp,
568 unsigned long latency_ns)
569{
570 long entries_required, wm_size;
571
572 /*
573 * Note: we need to make sure we don't overflow for various clock &
574 * latency values.
575 * clocks go from a few thousand to several hundred thousand.
576 * latency is usually a few thousand
577 */
578 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
579 1000;
580 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
581
582 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
583
584 wm_size = fifo_size - (entries_required + wm->guard_size);
585
586 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
587
588 /* Don't promote wm_size to unsigned... */
589 if (wm_size > (long)wm->max_wm)
590 wm_size = wm->max_wm;
591 if (wm_size <= 0)
592 wm_size = wm->default_wm;
593
594 /*
595 * Bspec seems to indicate that the value shouldn't be lower than
596 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
597 * Lets go for 8 which is the burst size since certain platforms
598 * already use a hardcoded 8 (which is what the spec says should be
599 * done).
600 */
601 if (wm_size <= 8)
602 wm_size = 8;
603
604 return wm_size;
605}
606
607static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
608{
609 struct drm_crtc *crtc, *enabled = NULL;
610
611 for_each_crtc(dev, crtc) {
612 if (intel_crtc_active(crtc)) {
613 if (enabled)
614 return NULL;
615 enabled = crtc;
616 }
617 }
618
619 return enabled;
620}
621
622static void pineview_update_wm(struct drm_crtc *unused_crtc)
623{
624 struct drm_device *dev = unused_crtc->dev;
625 struct drm_i915_private *dev_priv = dev->dev_private;
626 struct drm_crtc *crtc;
627 const struct cxsr_latency *latency;
628 u32 reg;
629 unsigned long wm;
630
631 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
632 dev_priv->fsb_freq, dev_priv->mem_freq);
633 if (!latency) {
634 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
635 intel_set_memory_cxsr(dev_priv, false);
636 return;
637 }
638
639 crtc = single_enabled_crtc(dev);
640 if (crtc) {
641 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
642 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
643 int clock = adjusted_mode->crtc_clock;
644
645 /* Display SR */
646 wm = intel_calculate_wm(clock, &pineview_display_wm,
647 pineview_display_wm.fifo_size,
648 cpp, latency->display_sr);
649 reg = I915_READ(DSPFW1);
650 reg &= ~DSPFW_SR_MASK;
651 reg |= FW_WM(wm, SR);
652 I915_WRITE(DSPFW1, reg);
653 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
654
655 /* cursor SR */
656 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
657 pineview_display_wm.fifo_size,
658 cpp, latency->cursor_sr);
659 reg = I915_READ(DSPFW3);
660 reg &= ~DSPFW_CURSOR_SR_MASK;
661 reg |= FW_WM(wm, CURSOR_SR);
662 I915_WRITE(DSPFW3, reg);
663
664 /* Display HPLL off SR */
665 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
666 pineview_display_hplloff_wm.fifo_size,
667 cpp, latency->display_hpll_disable);
668 reg = I915_READ(DSPFW3);
669 reg &= ~DSPFW_HPLL_SR_MASK;
670 reg |= FW_WM(wm, HPLL_SR);
671 I915_WRITE(DSPFW3, reg);
672
673 /* cursor HPLL off SR */
674 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
675 pineview_display_hplloff_wm.fifo_size,
676 cpp, latency->cursor_hpll_disable);
677 reg = I915_READ(DSPFW3);
678 reg &= ~DSPFW_HPLL_CURSOR_MASK;
679 reg |= FW_WM(wm, HPLL_CURSOR);
680 I915_WRITE(DSPFW3, reg);
681 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
682
683 intel_set_memory_cxsr(dev_priv, true);
684 } else {
685 intel_set_memory_cxsr(dev_priv, false);
686 }
687}
688
689static bool g4x_compute_wm0(struct drm_device *dev,
690 int plane,
691 const struct intel_watermark_params *display,
692 int display_latency_ns,
693 const struct intel_watermark_params *cursor,
694 int cursor_latency_ns,
695 int *plane_wm,
696 int *cursor_wm)
697{
698 struct drm_crtc *crtc;
699 const struct drm_display_mode *adjusted_mode;
700 int htotal, hdisplay, clock, cpp;
701 int line_time_us, line_count;
702 int entries, tlb_miss;
703
704 crtc = intel_get_crtc_for_plane(dev, plane);
705 if (!intel_crtc_active(crtc)) {
706 *cursor_wm = cursor->guard_size;
707 *plane_wm = display->guard_size;
708 return false;
709 }
710
711 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
712 clock = adjusted_mode->crtc_clock;
713 htotal = adjusted_mode->crtc_htotal;
714 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
715 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
716
717 /* Use the small buffer method to calculate plane watermark */
718 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
719 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
720 if (tlb_miss > 0)
721 entries += tlb_miss;
722 entries = DIV_ROUND_UP(entries, display->cacheline_size);
723 *plane_wm = entries + display->guard_size;
724 if (*plane_wm > (int)display->max_wm)
725 *plane_wm = display->max_wm;
726
727 /* Use the large buffer method to calculate cursor watermark */
728 line_time_us = max(htotal * 1000 / clock, 1);
729 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
730 entries = line_count * crtc->cursor->state->crtc_w * cpp;
731 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
732 if (tlb_miss > 0)
733 entries += tlb_miss;
734 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
735 *cursor_wm = entries + cursor->guard_size;
736 if (*cursor_wm > (int)cursor->max_wm)
737 *cursor_wm = (int)cursor->max_wm;
738
739 return true;
740}
741
742/*
743 * Check the wm result.
744 *
745 * If any calculated watermark values is larger than the maximum value that
746 * can be programmed into the associated watermark register, that watermark
747 * must be disabled.
748 */
749static bool g4x_check_srwm(struct drm_device *dev,
750 int display_wm, int cursor_wm,
751 const struct intel_watermark_params *display,
752 const struct intel_watermark_params *cursor)
753{
754 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
755 display_wm, cursor_wm);
756
757 if (display_wm > display->max_wm) {
758 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
759 display_wm, display->max_wm);
760 return false;
761 }
762
763 if (cursor_wm > cursor->max_wm) {
764 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
765 cursor_wm, cursor->max_wm);
766 return false;
767 }
768
769 if (!(display_wm || cursor_wm)) {
770 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
771 return false;
772 }
773
774 return true;
775}
776
777static bool g4x_compute_srwm(struct drm_device *dev,
778 int plane,
779 int latency_ns,
780 const struct intel_watermark_params *display,
781 const struct intel_watermark_params *cursor,
782 int *display_wm, int *cursor_wm)
783{
784 struct drm_crtc *crtc;
785 const struct drm_display_mode *adjusted_mode;
786 int hdisplay, htotal, cpp, clock;
787 unsigned long line_time_us;
788 int line_count, line_size;
789 int small, large;
790 int entries;
791
792 if (!latency_ns) {
793 *display_wm = *cursor_wm = 0;
794 return false;
795 }
796
797 crtc = intel_get_crtc_for_plane(dev, plane);
798 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
799 clock = adjusted_mode->crtc_clock;
800 htotal = adjusted_mode->crtc_htotal;
801 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
802 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
803
804 line_time_us = max(htotal * 1000 / clock, 1);
805 line_count = (latency_ns / line_time_us + 1000) / 1000;
806 line_size = hdisplay * cpp;
807
808 /* Use the minimum of the small and large buffer method for primary */
809 small = ((clock * cpp / 1000) * latency_ns) / 1000;
810 large = line_count * line_size;
811
812 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
813 *display_wm = entries + display->guard_size;
814
815 /* calculate the self-refresh watermark for display cursor */
816 entries = line_count * cpp * crtc->cursor->state->crtc_w;
817 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
818 *cursor_wm = entries + cursor->guard_size;
819
820 return g4x_check_srwm(dev,
821 *display_wm, *cursor_wm,
822 display, cursor);
823}
824
825#define FW_WM_VLV(value, plane) \
826 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
827
828static void vlv_write_wm_values(struct intel_crtc *crtc,
829 const struct vlv_wm_values *wm)
830{
831 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
832 enum pipe pipe = crtc->pipe;
833
834 I915_WRITE(VLV_DDL(pipe),
835 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
836 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
837 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
838 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
839
840 I915_WRITE(DSPFW1,
841 FW_WM(wm->sr.plane, SR) |
842 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
843 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
844 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
845 I915_WRITE(DSPFW2,
846 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
847 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
848 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
849 I915_WRITE(DSPFW3,
850 FW_WM(wm->sr.cursor, CURSOR_SR));
851
852 if (IS_CHERRYVIEW(dev_priv)) {
853 I915_WRITE(DSPFW7_CHV,
854 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
855 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
856 I915_WRITE(DSPFW8_CHV,
857 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
858 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
859 I915_WRITE(DSPFW9_CHV,
860 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
861 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
862 I915_WRITE(DSPHOWM,
863 FW_WM(wm->sr.plane >> 9, SR_HI) |
864 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
865 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
866 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
867 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
868 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
869 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
870 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
871 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
872 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
873 } else {
874 I915_WRITE(DSPFW7,
875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
876 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
877 I915_WRITE(DSPHOWM,
878 FW_WM(wm->sr.plane >> 9, SR_HI) |
879 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
880 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
881 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
882 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
883 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
884 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
885 }
886
887 /* zero (unused) WM1 watermarks */
888 I915_WRITE(DSPFW4, 0);
889 I915_WRITE(DSPFW5, 0);
890 I915_WRITE(DSPFW6, 0);
891 I915_WRITE(DSPHOWM1, 0);
892
893 POSTING_READ(DSPFW1);
894}
895
896#undef FW_WM_VLV
897
898enum vlv_wm_level {
899 VLV_WM_LEVEL_PM2,
900 VLV_WM_LEVEL_PM5,
901 VLV_WM_LEVEL_DDR_DVFS,
902};
903
904/* latency must be in 0.1us units. */
905static unsigned int vlv_wm_method2(unsigned int pixel_rate,
906 unsigned int pipe_htotal,
907 unsigned int horiz_pixels,
908 unsigned int cpp,
909 unsigned int latency)
910{
911 unsigned int ret;
912
913 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
914 ret = (ret + 1) * horiz_pixels * cpp;
915 ret = DIV_ROUND_UP(ret, 64);
916
917 return ret;
918}
919
920static void vlv_setup_wm_latency(struct drm_device *dev)
921{
922 struct drm_i915_private *dev_priv = dev->dev_private;
923
924 /* all latencies in usec */
925 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
926
927 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
928
929 if (IS_CHERRYVIEW(dev_priv)) {
930 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
931 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
932
933 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
934 }
935}
936
937static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
938 struct intel_crtc *crtc,
939 const struct intel_plane_state *state,
940 int level)
941{
942 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
943 int clock, htotal, cpp, width, wm;
944
945 if (dev_priv->wm.pri_latency[level] == 0)
946 return USHRT_MAX;
947
948 if (!state->visible)
949 return 0;
950
951 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
952 clock = crtc->config->base.adjusted_mode.crtc_clock;
953 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
954 width = crtc->config->pipe_src_w;
955 if (WARN_ON(htotal == 0))
956 htotal = 1;
957
958 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
959 /*
960 * FIXME the formula gives values that are
961 * too big for the cursor FIFO, and hence we
962 * would never be able to use cursors. For
963 * now just hardcode the watermark.
964 */
965 wm = 63;
966 } else {
967 wm = vlv_wm_method2(clock, htotal, width, cpp,
968 dev_priv->wm.pri_latency[level] * 10);
969 }
970
971 return min_t(int, wm, USHRT_MAX);
972}
973
974static void vlv_compute_fifo(struct intel_crtc *crtc)
975{
976 struct drm_device *dev = crtc->base.dev;
977 struct vlv_wm_state *wm_state = &crtc->wm_state;
978 struct intel_plane *plane;
979 unsigned int total_rate = 0;
980 const int fifo_size = 512 - 1;
981 int fifo_extra, fifo_left = fifo_size;
982
983 for_each_intel_plane_on_crtc(dev, crtc, plane) {
984 struct intel_plane_state *state =
985 to_intel_plane_state(plane->base.state);
986
987 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
988 continue;
989
990 if (state->visible) {
991 wm_state->num_active_planes++;
992 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
993 }
994 }
995
996 for_each_intel_plane_on_crtc(dev, crtc, plane) {
997 struct intel_plane_state *state =
998 to_intel_plane_state(plane->base.state);
999 unsigned int rate;
1000
1001 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1002 plane->wm.fifo_size = 63;
1003 continue;
1004 }
1005
1006 if (!state->visible) {
1007 plane->wm.fifo_size = 0;
1008 continue;
1009 }
1010
1011 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1012 plane->wm.fifo_size = fifo_size * rate / total_rate;
1013 fifo_left -= plane->wm.fifo_size;
1014 }
1015
1016 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1017
1018 /* spread the remainder evenly */
1019 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1020 int plane_extra;
1021
1022 if (fifo_left == 0)
1023 break;
1024
1025 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1026 continue;
1027
1028 /* give it all to the first plane if none are active */
1029 if (plane->wm.fifo_size == 0 &&
1030 wm_state->num_active_planes)
1031 continue;
1032
1033 plane_extra = min(fifo_extra, fifo_left);
1034 plane->wm.fifo_size += plane_extra;
1035 fifo_left -= plane_extra;
1036 }
1037
1038 WARN_ON(fifo_left != 0);
1039}
1040
1041static void vlv_invert_wms(struct intel_crtc *crtc)
1042{
1043 struct vlv_wm_state *wm_state = &crtc->wm_state;
1044 int level;
1045
1046 for (level = 0; level < wm_state->num_levels; level++) {
1047 struct drm_device *dev = crtc->base.dev;
1048 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1049 struct intel_plane *plane;
1050
1051 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1052 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1053
1054 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1055 switch (plane->base.type) {
1056 int sprite;
1057 case DRM_PLANE_TYPE_CURSOR:
1058 wm_state->wm[level].cursor = plane->wm.fifo_size -
1059 wm_state->wm[level].cursor;
1060 break;
1061 case DRM_PLANE_TYPE_PRIMARY:
1062 wm_state->wm[level].primary = plane->wm.fifo_size -
1063 wm_state->wm[level].primary;
1064 break;
1065 case DRM_PLANE_TYPE_OVERLAY:
1066 sprite = plane->plane;
1067 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1068 wm_state->wm[level].sprite[sprite];
1069 break;
1070 }
1071 }
1072 }
1073}
1074
1075static void vlv_compute_wm(struct intel_crtc *crtc)
1076{
1077 struct drm_device *dev = crtc->base.dev;
1078 struct vlv_wm_state *wm_state = &crtc->wm_state;
1079 struct intel_plane *plane;
1080 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1081 int level;
1082
1083 memset(wm_state, 0, sizeof(*wm_state));
1084
1085 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1086 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1087
1088 wm_state->num_active_planes = 0;
1089
1090 vlv_compute_fifo(crtc);
1091
1092 if (wm_state->num_active_planes != 1)
1093 wm_state->cxsr = false;
1094
1095 if (wm_state->cxsr) {
1096 for (level = 0; level < wm_state->num_levels; level++) {
1097 wm_state->sr[level].plane = sr_fifo_size;
1098 wm_state->sr[level].cursor = 63;
1099 }
1100 }
1101
1102 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1103 struct intel_plane_state *state =
1104 to_intel_plane_state(plane->base.state);
1105
1106 if (!state->visible)
1107 continue;
1108
1109 /* normal watermarks */
1110 for (level = 0; level < wm_state->num_levels; level++) {
1111 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1112 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1113
1114 /* hack */
1115 if (WARN_ON(level == 0 && wm > max_wm))
1116 wm = max_wm;
1117
1118 if (wm > plane->wm.fifo_size)
1119 break;
1120
1121 switch (plane->base.type) {
1122 int sprite;
1123 case DRM_PLANE_TYPE_CURSOR:
1124 wm_state->wm[level].cursor = wm;
1125 break;
1126 case DRM_PLANE_TYPE_PRIMARY:
1127 wm_state->wm[level].primary = wm;
1128 break;
1129 case DRM_PLANE_TYPE_OVERLAY:
1130 sprite = plane->plane;
1131 wm_state->wm[level].sprite[sprite] = wm;
1132 break;
1133 }
1134 }
1135
1136 wm_state->num_levels = level;
1137
1138 if (!wm_state->cxsr)
1139 continue;
1140
1141 /* maxfifo watermarks */
1142 switch (plane->base.type) {
1143 int sprite, level;
1144 case DRM_PLANE_TYPE_CURSOR:
1145 for (level = 0; level < wm_state->num_levels; level++)
1146 wm_state->sr[level].cursor =
1147 wm_state->wm[level].cursor;
1148 break;
1149 case DRM_PLANE_TYPE_PRIMARY:
1150 for (level = 0; level < wm_state->num_levels; level++)
1151 wm_state->sr[level].plane =
1152 min(wm_state->sr[level].plane,
1153 wm_state->wm[level].primary);
1154 break;
1155 case DRM_PLANE_TYPE_OVERLAY:
1156 sprite = plane->plane;
1157 for (level = 0; level < wm_state->num_levels; level++)
1158 wm_state->sr[level].plane =
1159 min(wm_state->sr[level].plane,
1160 wm_state->wm[level].sprite[sprite]);
1161 break;
1162 }
1163 }
1164
1165 /* clear any (partially) filled invalid levels */
1166 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1167 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1168 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1169 }
1170
1171 vlv_invert_wms(crtc);
1172}
1173
1174#define VLV_FIFO(plane, value) \
1175 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1176
1177static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1178{
1179 struct drm_device *dev = crtc->base.dev;
1180 struct drm_i915_private *dev_priv = to_i915(dev);
1181 struct intel_plane *plane;
1182 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1183
1184 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1185 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1186 WARN_ON(plane->wm.fifo_size != 63);
1187 continue;
1188 }
1189
1190 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1191 sprite0_start = plane->wm.fifo_size;
1192 else if (plane->plane == 0)
1193 sprite1_start = sprite0_start + plane->wm.fifo_size;
1194 else
1195 fifo_size = sprite1_start + plane->wm.fifo_size;
1196 }
1197
1198 WARN_ON(fifo_size != 512 - 1);
1199
1200 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1201 pipe_name(crtc->pipe), sprite0_start,
1202 sprite1_start, fifo_size);
1203
1204 switch (crtc->pipe) {
1205 uint32_t dsparb, dsparb2, dsparb3;
1206 case PIPE_A:
1207 dsparb = I915_READ(DSPARB);
1208 dsparb2 = I915_READ(DSPARB2);
1209
1210 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1211 VLV_FIFO(SPRITEB, 0xff));
1212 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1213 VLV_FIFO(SPRITEB, sprite1_start));
1214
1215 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1216 VLV_FIFO(SPRITEB_HI, 0x1));
1217 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1218 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1219
1220 I915_WRITE(DSPARB, dsparb);
1221 I915_WRITE(DSPARB2, dsparb2);
1222 break;
1223 case PIPE_B:
1224 dsparb = I915_READ(DSPARB);
1225 dsparb2 = I915_READ(DSPARB2);
1226
1227 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1228 VLV_FIFO(SPRITED, 0xff));
1229 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1230 VLV_FIFO(SPRITED, sprite1_start));
1231
1232 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1233 VLV_FIFO(SPRITED_HI, 0xff));
1234 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1235 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1236
1237 I915_WRITE(DSPARB, dsparb);
1238 I915_WRITE(DSPARB2, dsparb2);
1239 break;
1240 case PIPE_C:
1241 dsparb3 = I915_READ(DSPARB3);
1242 dsparb2 = I915_READ(DSPARB2);
1243
1244 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1245 VLV_FIFO(SPRITEF, 0xff));
1246 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1247 VLV_FIFO(SPRITEF, sprite1_start));
1248
1249 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1250 VLV_FIFO(SPRITEF_HI, 0xff));
1251 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1252 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1253
1254 I915_WRITE(DSPARB3, dsparb3);
1255 I915_WRITE(DSPARB2, dsparb2);
1256 break;
1257 default:
1258 break;
1259 }
1260}
1261
1262#undef VLV_FIFO
1263
1264static void vlv_merge_wm(struct drm_device *dev,
1265 struct vlv_wm_values *wm)
1266{
1267 struct intel_crtc *crtc;
1268 int num_active_crtcs = 0;
1269
1270 wm->level = to_i915(dev)->wm.max_level;
1271 wm->cxsr = true;
1272
1273 for_each_intel_crtc(dev, crtc) {
1274 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1275
1276 if (!crtc->active)
1277 continue;
1278
1279 if (!wm_state->cxsr)
1280 wm->cxsr = false;
1281
1282 num_active_crtcs++;
1283 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1284 }
1285
1286 if (num_active_crtcs != 1)
1287 wm->cxsr = false;
1288
1289 if (num_active_crtcs > 1)
1290 wm->level = VLV_WM_LEVEL_PM2;
1291
1292 for_each_intel_crtc(dev, crtc) {
1293 struct vlv_wm_state *wm_state = &crtc->wm_state;
1294 enum pipe pipe = crtc->pipe;
1295
1296 if (!crtc->active)
1297 continue;
1298
1299 wm->pipe[pipe] = wm_state->wm[wm->level];
1300 if (wm->cxsr)
1301 wm->sr = wm_state->sr[wm->level];
1302
1303 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1304 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1305 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1306 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1307 }
1308}
1309
1310static void vlv_update_wm(struct drm_crtc *crtc)
1311{
1312 struct drm_device *dev = crtc->dev;
1313 struct drm_i915_private *dev_priv = dev->dev_private;
1314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1315 enum pipe pipe = intel_crtc->pipe;
1316 struct vlv_wm_values wm = {};
1317
1318 vlv_compute_wm(intel_crtc);
1319 vlv_merge_wm(dev, &wm);
1320
1321 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1322 /* FIXME should be part of crtc atomic commit */
1323 vlv_pipe_set_fifo_size(intel_crtc);
1324 return;
1325 }
1326
1327 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1328 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1329 chv_set_memory_dvfs(dev_priv, false);
1330
1331 if (wm.level < VLV_WM_LEVEL_PM5 &&
1332 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1333 chv_set_memory_pm5(dev_priv, false);
1334
1335 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1336 intel_set_memory_cxsr(dev_priv, false);
1337
1338 /* FIXME should be part of crtc atomic commit */
1339 vlv_pipe_set_fifo_size(intel_crtc);
1340
1341 vlv_write_wm_values(intel_crtc, &wm);
1342
1343 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1344 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1345 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1346 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1347 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1348
1349 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1350 intel_set_memory_cxsr(dev_priv, true);
1351
1352 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1353 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1354 chv_set_memory_pm5(dev_priv, true);
1355
1356 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1357 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1358 chv_set_memory_dvfs(dev_priv, true);
1359
1360 dev_priv->wm.vlv = wm;
1361}
1362
1363#define single_plane_enabled(mask) is_power_of_2(mask)
1364
1365static void g4x_update_wm(struct drm_crtc *crtc)
1366{
1367 struct drm_device *dev = crtc->dev;
1368 static const int sr_latency_ns = 12000;
1369 struct drm_i915_private *dev_priv = dev->dev_private;
1370 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1371 int plane_sr, cursor_sr;
1372 unsigned int enabled = 0;
1373 bool cxsr_enabled;
1374
1375 if (g4x_compute_wm0(dev, PIPE_A,
1376 &g4x_wm_info, pessimal_latency_ns,
1377 &g4x_cursor_wm_info, pessimal_latency_ns,
1378 &planea_wm, &cursora_wm))
1379 enabled |= 1 << PIPE_A;
1380
1381 if (g4x_compute_wm0(dev, PIPE_B,
1382 &g4x_wm_info, pessimal_latency_ns,
1383 &g4x_cursor_wm_info, pessimal_latency_ns,
1384 &planeb_wm, &cursorb_wm))
1385 enabled |= 1 << PIPE_B;
1386
1387 if (single_plane_enabled(enabled) &&
1388 g4x_compute_srwm(dev, ffs(enabled) - 1,
1389 sr_latency_ns,
1390 &g4x_wm_info,
1391 &g4x_cursor_wm_info,
1392 &plane_sr, &cursor_sr)) {
1393 cxsr_enabled = true;
1394 } else {
1395 cxsr_enabled = false;
1396 intel_set_memory_cxsr(dev_priv, false);
1397 plane_sr = cursor_sr = 0;
1398 }
1399
1400 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1401 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1402 planea_wm, cursora_wm,
1403 planeb_wm, cursorb_wm,
1404 plane_sr, cursor_sr);
1405
1406 I915_WRITE(DSPFW1,
1407 FW_WM(plane_sr, SR) |
1408 FW_WM(cursorb_wm, CURSORB) |
1409 FW_WM(planeb_wm, PLANEB) |
1410 FW_WM(planea_wm, PLANEA));
1411 I915_WRITE(DSPFW2,
1412 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1413 FW_WM(cursora_wm, CURSORA));
1414 /* HPLL off in SR has some issues on G4x... disable it */
1415 I915_WRITE(DSPFW3,
1416 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1417 FW_WM(cursor_sr, CURSOR_SR));
1418
1419 if (cxsr_enabled)
1420 intel_set_memory_cxsr(dev_priv, true);
1421}
1422
1423static void i965_update_wm(struct drm_crtc *unused_crtc)
1424{
1425 struct drm_device *dev = unused_crtc->dev;
1426 struct drm_i915_private *dev_priv = dev->dev_private;
1427 struct drm_crtc *crtc;
1428 int srwm = 1;
1429 int cursor_sr = 16;
1430 bool cxsr_enabled;
1431
1432 /* Calc sr entries for one plane configs */
1433 crtc = single_enabled_crtc(dev);
1434 if (crtc) {
1435 /* self-refresh has much higher latency */
1436 static const int sr_latency_ns = 12000;
1437 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1438 int clock = adjusted_mode->crtc_clock;
1439 int htotal = adjusted_mode->crtc_htotal;
1440 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1441 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1442 unsigned long line_time_us;
1443 int entries;
1444
1445 line_time_us = max(htotal * 1000 / clock, 1);
1446
1447 /* Use ns/us then divide to preserve precision */
1448 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1449 cpp * hdisplay;
1450 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1451 srwm = I965_FIFO_SIZE - entries;
1452 if (srwm < 0)
1453 srwm = 1;
1454 srwm &= 0x1ff;
1455 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1456 entries, srwm);
1457
1458 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1459 cpp * crtc->cursor->state->crtc_w;
1460 entries = DIV_ROUND_UP(entries,
1461 i965_cursor_wm_info.cacheline_size);
1462 cursor_sr = i965_cursor_wm_info.fifo_size -
1463 (entries + i965_cursor_wm_info.guard_size);
1464
1465 if (cursor_sr > i965_cursor_wm_info.max_wm)
1466 cursor_sr = i965_cursor_wm_info.max_wm;
1467
1468 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1469 "cursor %d\n", srwm, cursor_sr);
1470
1471 cxsr_enabled = true;
1472 } else {
1473 cxsr_enabled = false;
1474 /* Turn off self refresh if both pipes are enabled */
1475 intel_set_memory_cxsr(dev_priv, false);
1476 }
1477
1478 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1479 srwm);
1480
1481 /* 965 has limitations... */
1482 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1483 FW_WM(8, CURSORB) |
1484 FW_WM(8, PLANEB) |
1485 FW_WM(8, PLANEA));
1486 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1487 FW_WM(8, PLANEC_OLD));
1488 /* update cursor SR watermark */
1489 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1490
1491 if (cxsr_enabled)
1492 intel_set_memory_cxsr(dev_priv, true);
1493}
1494
1495#undef FW_WM
1496
1497static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1498{
1499 struct drm_device *dev = unused_crtc->dev;
1500 struct drm_i915_private *dev_priv = dev->dev_private;
1501 const struct intel_watermark_params *wm_info;
1502 uint32_t fwater_lo;
1503 uint32_t fwater_hi;
1504 int cwm, srwm = 1;
1505 int fifo_size;
1506 int planea_wm, planeb_wm;
1507 struct drm_crtc *crtc, *enabled = NULL;
1508
1509 if (IS_I945GM(dev))
1510 wm_info = &i945_wm_info;
1511 else if (!IS_GEN2(dev))
1512 wm_info = &i915_wm_info;
1513 else
1514 wm_info = &i830_a_wm_info;
1515
1516 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1517 crtc = intel_get_crtc_for_plane(dev, 0);
1518 if (intel_crtc_active(crtc)) {
1519 const struct drm_display_mode *adjusted_mode;
1520 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1521 if (IS_GEN2(dev))
1522 cpp = 4;
1523
1524 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1525 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1526 wm_info, fifo_size, cpp,
1527 pessimal_latency_ns);
1528 enabled = crtc;
1529 } else {
1530 planea_wm = fifo_size - wm_info->guard_size;
1531 if (planea_wm > (long)wm_info->max_wm)
1532 planea_wm = wm_info->max_wm;
1533 }
1534
1535 if (IS_GEN2(dev))
1536 wm_info = &i830_bc_wm_info;
1537
1538 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1539 crtc = intel_get_crtc_for_plane(dev, 1);
1540 if (intel_crtc_active(crtc)) {
1541 const struct drm_display_mode *adjusted_mode;
1542 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1543 if (IS_GEN2(dev))
1544 cpp = 4;
1545
1546 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1547 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1548 wm_info, fifo_size, cpp,
1549 pessimal_latency_ns);
1550 if (enabled == NULL)
1551 enabled = crtc;
1552 else
1553 enabled = NULL;
1554 } else {
1555 planeb_wm = fifo_size - wm_info->guard_size;
1556 if (planeb_wm > (long)wm_info->max_wm)
1557 planeb_wm = wm_info->max_wm;
1558 }
1559
1560 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1561
1562 if (IS_I915GM(dev) && enabled) {
1563 struct drm_i915_gem_object *obj;
1564
1565 obj = intel_fb_obj(enabled->primary->state->fb);
1566
1567 /* self-refresh seems busted with untiled */
1568 if (obj->tiling_mode == I915_TILING_NONE)
1569 enabled = NULL;
1570 }
1571
1572 /*
1573 * Overlay gets an aggressive default since video jitter is bad.
1574 */
1575 cwm = 2;
1576
1577 /* Play safe and disable self-refresh before adjusting watermarks. */
1578 intel_set_memory_cxsr(dev_priv, false);
1579
1580 /* Calc sr entries for one plane configs */
1581 if (HAS_FW_BLC(dev) && enabled) {
1582 /* self-refresh has much higher latency */
1583 static const int sr_latency_ns = 6000;
1584 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1585 int clock = adjusted_mode->crtc_clock;
1586 int htotal = adjusted_mode->crtc_htotal;
1587 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1588 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1589 unsigned long line_time_us;
1590 int entries;
1591
1592 line_time_us = max(htotal * 1000 / clock, 1);
1593
1594 /* Use ns/us then divide to preserve precision */
1595 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1596 cpp * hdisplay;
1597 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1598 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1599 srwm = wm_info->fifo_size - entries;
1600 if (srwm < 0)
1601 srwm = 1;
1602
1603 if (IS_I945G(dev) || IS_I945GM(dev))
1604 I915_WRITE(FW_BLC_SELF,
1605 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1606 else if (IS_I915GM(dev))
1607 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1608 }
1609
1610 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1611 planea_wm, planeb_wm, cwm, srwm);
1612
1613 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1614 fwater_hi = (cwm & 0x1f);
1615
1616 /* Set request length to 8 cachelines per fetch */
1617 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1618 fwater_hi = fwater_hi | (1 << 8);
1619
1620 I915_WRITE(FW_BLC, fwater_lo);
1621 I915_WRITE(FW_BLC2, fwater_hi);
1622
1623 if (enabled)
1624 intel_set_memory_cxsr(dev_priv, true);
1625}
1626
1627static void i845_update_wm(struct drm_crtc *unused_crtc)
1628{
1629 struct drm_device *dev = unused_crtc->dev;
1630 struct drm_i915_private *dev_priv = dev->dev_private;
1631 struct drm_crtc *crtc;
1632 const struct drm_display_mode *adjusted_mode;
1633 uint32_t fwater_lo;
1634 int planea_wm;
1635
1636 crtc = single_enabled_crtc(dev);
1637 if (crtc == NULL)
1638 return;
1639
1640 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1641 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1642 &i845_wm_info,
1643 dev_priv->display.get_fifo_size(dev, 0),
1644 4, pessimal_latency_ns);
1645 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1646 fwater_lo |= (3<<8) | planea_wm;
1647
1648 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1649
1650 I915_WRITE(FW_BLC, fwater_lo);
1651}
1652
1653uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1654{
1655 uint32_t pixel_rate;
1656
1657 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1658
1659 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1660 * adjust the pixel_rate here. */
1661
1662 if (pipe_config->pch_pfit.enabled) {
1663 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1664 uint32_t pfit_size = pipe_config->pch_pfit.size;
1665
1666 pipe_w = pipe_config->pipe_src_w;
1667 pipe_h = pipe_config->pipe_src_h;
1668
1669 pfit_w = (pfit_size >> 16) & 0xFFFF;
1670 pfit_h = pfit_size & 0xFFFF;
1671 if (pipe_w < pfit_w)
1672 pipe_w = pfit_w;
1673 if (pipe_h < pfit_h)
1674 pipe_h = pfit_h;
1675
1676 if (WARN_ON(!pfit_w || !pfit_h))
1677 return pixel_rate;
1678
1679 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1680 pfit_w * pfit_h);
1681 }
1682
1683 return pixel_rate;
1684}
1685
1686/* latency must be in 0.1us units. */
1687static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1688{
1689 uint64_t ret;
1690
1691 if (WARN(latency == 0, "Latency value missing\n"))
1692 return UINT_MAX;
1693
1694 ret = (uint64_t) pixel_rate * cpp * latency;
1695 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1696
1697 return ret;
1698}
1699
1700/* latency must be in 0.1us units. */
1701static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1702 uint32_t horiz_pixels, uint8_t cpp,
1703 uint32_t latency)
1704{
1705 uint32_t ret;
1706
1707 if (WARN(latency == 0, "Latency value missing\n"))
1708 return UINT_MAX;
1709 if (WARN_ON(!pipe_htotal))
1710 return UINT_MAX;
1711
1712 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1713 ret = (ret + 1) * horiz_pixels * cpp;
1714 ret = DIV_ROUND_UP(ret, 64) + 2;
1715 return ret;
1716}
1717
1718static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1719 uint8_t cpp)
1720{
1721 /*
1722 * Neither of these should be possible since this function shouldn't be
1723 * called if the CRTC is off or the plane is invisible. But let's be
1724 * extra paranoid to avoid a potential divide-by-zero if we screw up
1725 * elsewhere in the driver.
1726 */
1727 if (WARN_ON(!cpp))
1728 return 0;
1729 if (WARN_ON(!horiz_pixels))
1730 return 0;
1731
1732 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1733}
1734
1735struct ilk_wm_maximums {
1736 uint16_t pri;
1737 uint16_t spr;
1738 uint16_t cur;
1739 uint16_t fbc;
1740};
1741
1742/*
1743 * For both WM_PIPE and WM_LP.
1744 * mem_value must be in 0.1us units.
1745 */
1746static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1747 const struct intel_plane_state *pstate,
1748 uint32_t mem_value,
1749 bool is_lp)
1750{
1751 int cpp = pstate->base.fb ?
1752 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1753 uint32_t method1, method2;
1754
1755 if (!cstate->base.active || !pstate->visible)
1756 return 0;
1757
1758 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1759
1760 if (!is_lp)
1761 return method1;
1762
1763 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1764 cstate->base.adjusted_mode.crtc_htotal,
1765 drm_rect_width(&pstate->dst),
1766 cpp, mem_value);
1767
1768 return min(method1, method2);
1769}
1770
1771/*
1772 * For both WM_PIPE and WM_LP.
1773 * mem_value must be in 0.1us units.
1774 */
1775static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1776 const struct intel_plane_state *pstate,
1777 uint32_t mem_value)
1778{
1779 int cpp = pstate->base.fb ?
1780 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1781 uint32_t method1, method2;
1782
1783 if (!cstate->base.active || !pstate->visible)
1784 return 0;
1785
1786 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1787 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1788 cstate->base.adjusted_mode.crtc_htotal,
1789 drm_rect_width(&pstate->dst),
1790 cpp, mem_value);
1791 return min(method1, method2);
1792}
1793
1794/*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
1798static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1799 const struct intel_plane_state *pstate,
1800 uint32_t mem_value)
1801{
1802 /*
1803 * We treat the cursor plane as always-on for the purposes of watermark
1804 * calculation. Until we have two-stage watermark programming merged,
1805 * this is necessary to avoid flickering.
1806 */
1807 int cpp = 4;
1808 int width = pstate->visible ? pstate->base.crtc_w : 64;
1809
1810 if (!cstate->base.active)
1811 return 0;
1812
1813 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1814 cstate->base.adjusted_mode.crtc_htotal,
1815 width, cpp, mem_value);
1816}
1817
1818/* Only for WM_LP. */
1819static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1820 const struct intel_plane_state *pstate,
1821 uint32_t pri_val)
1822{
1823 int cpp = pstate->base.fb ?
1824 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1825
1826 if (!cstate->base.active || !pstate->visible)
1827 return 0;
1828
1829 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
1830}
1831
1832static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1833{
1834 if (INTEL_INFO(dev)->gen >= 8)
1835 return 3072;
1836 else if (INTEL_INFO(dev)->gen >= 7)
1837 return 768;
1838 else
1839 return 512;
1840}
1841
1842static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1843 int level, bool is_sprite)
1844{
1845 if (INTEL_INFO(dev)->gen >= 8)
1846 /* BDW primary/sprite plane watermarks */
1847 return level == 0 ? 255 : 2047;
1848 else if (INTEL_INFO(dev)->gen >= 7)
1849 /* IVB/HSW primary/sprite plane watermarks */
1850 return level == 0 ? 127 : 1023;
1851 else if (!is_sprite)
1852 /* ILK/SNB primary plane watermarks */
1853 return level == 0 ? 127 : 511;
1854 else
1855 /* ILK/SNB sprite plane watermarks */
1856 return level == 0 ? 63 : 255;
1857}
1858
1859static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1860 int level)
1861{
1862 if (INTEL_INFO(dev)->gen >= 7)
1863 return level == 0 ? 63 : 255;
1864 else
1865 return level == 0 ? 31 : 63;
1866}
1867
1868static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1869{
1870 if (INTEL_INFO(dev)->gen >= 8)
1871 return 31;
1872 else
1873 return 15;
1874}
1875
1876/* Calculate the maximum primary/sprite plane watermark */
1877static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1878 int level,
1879 const struct intel_wm_config *config,
1880 enum intel_ddb_partitioning ddb_partitioning,
1881 bool is_sprite)
1882{
1883 unsigned int fifo_size = ilk_display_fifo_size(dev);
1884
1885 /* if sprites aren't enabled, sprites get nothing */
1886 if (is_sprite && !config->sprites_enabled)
1887 return 0;
1888
1889 /* HSW allows LP1+ watermarks even with multiple pipes */
1890 if (level == 0 || config->num_pipes_active > 1) {
1891 fifo_size /= INTEL_INFO(dev)->num_pipes;
1892
1893 /*
1894 * For some reason the non self refresh
1895 * FIFO size is only half of the self
1896 * refresh FIFO size on ILK/SNB.
1897 */
1898 if (INTEL_INFO(dev)->gen <= 6)
1899 fifo_size /= 2;
1900 }
1901
1902 if (config->sprites_enabled) {
1903 /* level 0 is always calculated with 1:1 split */
1904 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1905 if (is_sprite)
1906 fifo_size *= 5;
1907 fifo_size /= 6;
1908 } else {
1909 fifo_size /= 2;
1910 }
1911 }
1912
1913 /* clamp to max that the registers can hold */
1914 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1915}
1916
1917/* Calculate the maximum cursor plane watermark */
1918static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1919 int level,
1920 const struct intel_wm_config *config)
1921{
1922 /* HSW LP1+ watermarks w/ multiple pipes */
1923 if (level > 0 && config->num_pipes_active > 1)
1924 return 64;
1925
1926 /* otherwise just report max that registers can hold */
1927 return ilk_cursor_wm_reg_max(dev, level);
1928}
1929
1930static void ilk_compute_wm_maximums(const struct drm_device *dev,
1931 int level,
1932 const struct intel_wm_config *config,
1933 enum intel_ddb_partitioning ddb_partitioning,
1934 struct ilk_wm_maximums *max)
1935{
1936 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1937 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1938 max->cur = ilk_cursor_wm_max(dev, level, config);
1939 max->fbc = ilk_fbc_wm_reg_max(dev);
1940}
1941
1942static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1943 int level,
1944 struct ilk_wm_maximums *max)
1945{
1946 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1947 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1948 max->cur = ilk_cursor_wm_reg_max(dev, level);
1949 max->fbc = ilk_fbc_wm_reg_max(dev);
1950}
1951
1952static bool ilk_validate_wm_level(int level,
1953 const struct ilk_wm_maximums *max,
1954 struct intel_wm_level *result)
1955{
1956 bool ret;
1957
1958 /* already determined to be invalid? */
1959 if (!result->enable)
1960 return false;
1961
1962 result->enable = result->pri_val <= max->pri &&
1963 result->spr_val <= max->spr &&
1964 result->cur_val <= max->cur;
1965
1966 ret = result->enable;
1967
1968 /*
1969 * HACK until we can pre-compute everything,
1970 * and thus fail gracefully if LP0 watermarks
1971 * are exceeded...
1972 */
1973 if (level == 0 && !result->enable) {
1974 if (result->pri_val > max->pri)
1975 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1976 level, result->pri_val, max->pri);
1977 if (result->spr_val > max->spr)
1978 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1979 level, result->spr_val, max->spr);
1980 if (result->cur_val > max->cur)
1981 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1982 level, result->cur_val, max->cur);
1983
1984 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1985 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1986 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1987 result->enable = true;
1988 }
1989
1990 return ret;
1991}
1992
1993static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1994 const struct intel_crtc *intel_crtc,
1995 int level,
1996 struct intel_crtc_state *cstate,
1997 struct intel_plane_state *pristate,
1998 struct intel_plane_state *sprstate,
1999 struct intel_plane_state *curstate,
2000 struct intel_wm_level *result)
2001{
2002 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2003 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2004 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2005
2006 /* WM1+ latency values stored in 0.5us units */
2007 if (level > 0) {
2008 pri_latency *= 5;
2009 spr_latency *= 5;
2010 cur_latency *= 5;
2011 }
2012
2013 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2014 pri_latency, level);
2015 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2016 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2017 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2018 result->enable = true;
2019}
2020
2021static uint32_t
2022hsw_compute_linetime_wm(struct drm_device *dev,
2023 struct intel_crtc_state *cstate)
2024{
2025 struct drm_i915_private *dev_priv = dev->dev_private;
2026 const struct drm_display_mode *adjusted_mode =
2027 &cstate->base.adjusted_mode;
2028 u32 linetime, ips_linetime;
2029
2030 if (!cstate->base.active)
2031 return 0;
2032 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2033 return 0;
2034 if (WARN_ON(dev_priv->cdclk_freq == 0))
2035 return 0;
2036
2037 /* The WM are computed with base on how long it takes to fill a single
2038 * row at the given clock rate, multiplied by 8.
2039 * */
2040 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2041 adjusted_mode->crtc_clock);
2042 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2043 dev_priv->cdclk_freq);
2044
2045 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2046 PIPE_WM_LINETIME_TIME(linetime);
2047}
2048
2049static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2050{
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2052
2053 if (IS_GEN9(dev)) {
2054 uint32_t val;
2055 int ret, i;
2056 int level, max_level = ilk_wm_max_level(dev);
2057
2058 /* read the first set of memory latencies[0:3] */
2059 val = 0; /* data0 to be programmed to 0 for first set */
2060 mutex_lock(&dev_priv->rps.hw_lock);
2061 ret = sandybridge_pcode_read(dev_priv,
2062 GEN9_PCODE_READ_MEM_LATENCY,
2063 &val);
2064 mutex_unlock(&dev_priv->rps.hw_lock);
2065
2066 if (ret) {
2067 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2068 return;
2069 }
2070
2071 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2072 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2073 GEN9_MEM_LATENCY_LEVEL_MASK;
2074 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2075 GEN9_MEM_LATENCY_LEVEL_MASK;
2076 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2077 GEN9_MEM_LATENCY_LEVEL_MASK;
2078
2079 /* read the second set of memory latencies[4:7] */
2080 val = 1; /* data0 to be programmed to 1 for second set */
2081 mutex_lock(&dev_priv->rps.hw_lock);
2082 ret = sandybridge_pcode_read(dev_priv,
2083 GEN9_PCODE_READ_MEM_LATENCY,
2084 &val);
2085 mutex_unlock(&dev_priv->rps.hw_lock);
2086 if (ret) {
2087 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2088 return;
2089 }
2090
2091 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2092 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2093 GEN9_MEM_LATENCY_LEVEL_MASK;
2094 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2095 GEN9_MEM_LATENCY_LEVEL_MASK;
2096 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2097 GEN9_MEM_LATENCY_LEVEL_MASK;
2098
2099 /*
2100 * WaWmMemoryReadLatency:skl
2101 *
2102 * punit doesn't take into account the read latency so we need
2103 * to add 2us to the various latency levels we retrieve from
2104 * the punit.
2105 * - W0 is a bit special in that it's the only level that
2106 * can't be disabled if we want to have display working, so
2107 * we always add 2us there.
2108 * - For levels >=1, punit returns 0us latency when they are
2109 * disabled, so we respect that and don't add 2us then
2110 *
2111 * Additionally, if a level n (n > 1) has a 0us latency, all
2112 * levels m (m >= n) need to be disabled. We make sure to
2113 * sanitize the values out of the punit to satisfy this
2114 * requirement.
2115 */
2116 wm[0] += 2;
2117 for (level = 1; level <= max_level; level++)
2118 if (wm[level] != 0)
2119 wm[level] += 2;
2120 else {
2121 for (i = level + 1; i <= max_level; i++)
2122 wm[i] = 0;
2123
2124 break;
2125 }
2126 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2127 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2128
2129 wm[0] = (sskpd >> 56) & 0xFF;
2130 if (wm[0] == 0)
2131 wm[0] = sskpd & 0xF;
2132 wm[1] = (sskpd >> 4) & 0xFF;
2133 wm[2] = (sskpd >> 12) & 0xFF;
2134 wm[3] = (sskpd >> 20) & 0x1FF;
2135 wm[4] = (sskpd >> 32) & 0x1FF;
2136 } else if (INTEL_INFO(dev)->gen >= 6) {
2137 uint32_t sskpd = I915_READ(MCH_SSKPD);
2138
2139 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2140 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2141 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2142 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2143 } else if (INTEL_INFO(dev)->gen >= 5) {
2144 uint32_t mltr = I915_READ(MLTR_ILK);
2145
2146 /* ILK primary LP0 latency is 700 ns */
2147 wm[0] = 7;
2148 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2149 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2150 }
2151}
2152
2153static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2154{
2155 /* ILK sprite LP0 latency is 1300 ns */
2156 if (INTEL_INFO(dev)->gen == 5)
2157 wm[0] = 13;
2158}
2159
2160static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2161{
2162 /* ILK cursor LP0 latency is 1300 ns */
2163 if (INTEL_INFO(dev)->gen == 5)
2164 wm[0] = 13;
2165
2166 /* WaDoubleCursorLP3Latency:ivb */
2167 if (IS_IVYBRIDGE(dev))
2168 wm[3] *= 2;
2169}
2170
2171int ilk_wm_max_level(const struct drm_device *dev)
2172{
2173 /* how many WM levels are we expecting */
2174 if (INTEL_INFO(dev)->gen >= 9)
2175 return 7;
2176 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2177 return 4;
2178 else if (INTEL_INFO(dev)->gen >= 6)
2179 return 3;
2180 else
2181 return 2;
2182}
2183
2184static void intel_print_wm_latency(struct drm_device *dev,
2185 const char *name,
2186 const uint16_t wm[8])
2187{
2188 int level, max_level = ilk_wm_max_level(dev);
2189
2190 for (level = 0; level <= max_level; level++) {
2191 unsigned int latency = wm[level];
2192
2193 if (latency == 0) {
2194 DRM_ERROR("%s WM%d latency not provided\n",
2195 name, level);
2196 continue;
2197 }
2198
2199 /*
2200 * - latencies are in us on gen9.
2201 * - before then, WM1+ latency values are in 0.5us units
2202 */
2203 if (IS_GEN9(dev))
2204 latency *= 10;
2205 else if (level > 0)
2206 latency *= 5;
2207
2208 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2209 name, level, wm[level],
2210 latency / 10, latency % 10);
2211 }
2212}
2213
2214static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2215 uint16_t wm[5], uint16_t min)
2216{
2217 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2218
2219 if (wm[0] >= min)
2220 return false;
2221
2222 wm[0] = max(wm[0], min);
2223 for (level = 1; level <= max_level; level++)
2224 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2225
2226 return true;
2227}
2228
2229static void snb_wm_latency_quirk(struct drm_device *dev)
2230{
2231 struct drm_i915_private *dev_priv = dev->dev_private;
2232 bool changed;
2233
2234 /*
2235 * The BIOS provided WM memory latency values are often
2236 * inadequate for high resolution displays. Adjust them.
2237 */
2238 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2239 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2240 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2241
2242 if (!changed)
2243 return;
2244
2245 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2246 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2247 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2248 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2249}
2250
2251static void ilk_setup_wm_latency(struct drm_device *dev)
2252{
2253 struct drm_i915_private *dev_priv = dev->dev_private;
2254
2255 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2256
2257 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2258 sizeof(dev_priv->wm.pri_latency));
2259 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2260 sizeof(dev_priv->wm.pri_latency));
2261
2262 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2263 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2264
2265 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2266 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2267 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2268
2269 if (IS_GEN6(dev))
2270 snb_wm_latency_quirk(dev);
2271}
2272
2273static void skl_setup_wm_latency(struct drm_device *dev)
2274{
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276
2277 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2278 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2279}
2280
2281/* Compute new watermarks for the pipe */
2282static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2283 struct drm_atomic_state *state)
2284{
2285 struct intel_pipe_wm *pipe_wm;
2286 struct drm_device *dev = intel_crtc->base.dev;
2287 const struct drm_i915_private *dev_priv = dev->dev_private;
2288 struct intel_crtc_state *cstate = NULL;
2289 struct intel_plane *intel_plane;
2290 struct drm_plane_state *ps;
2291 struct intel_plane_state *pristate = NULL;
2292 struct intel_plane_state *sprstate = NULL;
2293 struct intel_plane_state *curstate = NULL;
2294 int level, max_level = ilk_wm_max_level(dev);
2295 /* LP0 watermark maximums depend on this pipe alone */
2296 struct intel_wm_config config = {
2297 .num_pipes_active = 1,
2298 };
2299 struct ilk_wm_maximums max;
2300
2301 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
2302 if (IS_ERR(cstate))
2303 return PTR_ERR(cstate);
2304
2305 pipe_wm = &cstate->wm.optimal.ilk;
2306 memset(pipe_wm, 0, sizeof(*pipe_wm));
2307
2308 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2309 ps = drm_atomic_get_plane_state(state,
2310 &intel_plane->base);
2311 if (IS_ERR(ps))
2312 return PTR_ERR(ps);
2313
2314 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2315 pristate = to_intel_plane_state(ps);
2316 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2317 sprstate = to_intel_plane_state(ps);
2318 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2319 curstate = to_intel_plane_state(ps);
2320 }
2321
2322 config.sprites_enabled = sprstate->visible;
2323 config.sprites_scaled = sprstate->visible &&
2324 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2325 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2326
2327 pipe_wm->pipe_enabled = cstate->base.active;
2328 pipe_wm->sprites_enabled = config.sprites_enabled;
2329 pipe_wm->sprites_scaled = config.sprites_scaled;
2330
2331 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2332 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
2333 max_level = 1;
2334
2335 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2336 if (config.sprites_scaled)
2337 max_level = 0;
2338
2339 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2340 pristate, sprstate, curstate, &pipe_wm->wm[0]);
2341
2342 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2343 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
2344
2345 /* LP0 watermarks always use 1/2 DDB partitioning */
2346 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2347
2348 /* At least LP0 must be valid */
2349 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2350 return -EINVAL;
2351
2352 ilk_compute_wm_reg_maximums(dev, 1, &max);
2353
2354 for (level = 1; level <= max_level; level++) {
2355 struct intel_wm_level wm = {};
2356
2357 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2358 pristate, sprstate, curstate, &wm);
2359
2360 /*
2361 * Disable any watermark level that exceeds the
2362 * register maximums since such watermarks are
2363 * always invalid.
2364 */
2365 if (!ilk_validate_wm_level(level, &max, &wm))
2366 break;
2367
2368 pipe_wm->wm[level] = wm;
2369 }
2370
2371 return 0;
2372}
2373
2374/*
2375 * Merge the watermarks from all active pipes for a specific level.
2376 */
2377static void ilk_merge_wm_level(struct drm_device *dev,
2378 int level,
2379 struct intel_wm_level *ret_wm)
2380{
2381 const struct intel_crtc *intel_crtc;
2382
2383 ret_wm->enable = true;
2384
2385 for_each_intel_crtc(dev, intel_crtc) {
2386 const struct intel_crtc_state *cstate =
2387 to_intel_crtc_state(intel_crtc->base.state);
2388 const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
2389 const struct intel_wm_level *wm = &active->wm[level];
2390
2391 if (!active->pipe_enabled)
2392 continue;
2393
2394 /*
2395 * The watermark values may have been used in the past,
2396 * so we must maintain them in the registers for some
2397 * time even if the level is now disabled.
2398 */
2399 if (!wm->enable)
2400 ret_wm->enable = false;
2401
2402 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2403 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2404 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2405 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2406 }
2407}
2408
2409/*
2410 * Merge all low power watermarks for all active pipes.
2411 */
2412static void ilk_wm_merge(struct drm_device *dev,
2413 const struct intel_wm_config *config,
2414 const struct ilk_wm_maximums *max,
2415 struct intel_pipe_wm *merged)
2416{
2417 struct drm_i915_private *dev_priv = dev->dev_private;
2418 int level, max_level = ilk_wm_max_level(dev);
2419 int last_enabled_level = max_level;
2420
2421 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2422 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2423 config->num_pipes_active > 1)
2424 return;
2425
2426 /* ILK: FBC WM must be disabled always */
2427 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2428
2429 /* merge each WM1+ level */
2430 for (level = 1; level <= max_level; level++) {
2431 struct intel_wm_level *wm = &merged->wm[level];
2432
2433 ilk_merge_wm_level(dev, level, wm);
2434
2435 if (level > last_enabled_level)
2436 wm->enable = false;
2437 else if (!ilk_validate_wm_level(level, max, wm))
2438 /* make sure all following levels get disabled */
2439 last_enabled_level = level - 1;
2440
2441 /*
2442 * The spec says it is preferred to disable
2443 * FBC WMs instead of disabling a WM level.
2444 */
2445 if (wm->fbc_val > max->fbc) {
2446 if (wm->enable)
2447 merged->fbc_wm_enabled = false;
2448 wm->fbc_val = 0;
2449 }
2450 }
2451
2452 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2453 /*
2454 * FIXME this is racy. FBC might get enabled later.
2455 * What we should check here is whether FBC can be
2456 * enabled sometime later.
2457 */
2458 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2459 intel_fbc_is_active(dev_priv)) {
2460 for (level = 2; level <= max_level; level++) {
2461 struct intel_wm_level *wm = &merged->wm[level];
2462
2463 wm->enable = false;
2464 }
2465 }
2466}
2467
2468static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2469{
2470 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2471 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2472}
2473
2474/* The value we need to program into the WM_LPx latency field */
2475static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2476{
2477 struct drm_i915_private *dev_priv = dev->dev_private;
2478
2479 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2480 return 2 * level;
2481 else
2482 return dev_priv->wm.pri_latency[level];
2483}
2484
2485static void ilk_compute_wm_results(struct drm_device *dev,
2486 const struct intel_pipe_wm *merged,
2487 enum intel_ddb_partitioning partitioning,
2488 struct ilk_wm_values *results)
2489{
2490 struct intel_crtc *intel_crtc;
2491 int level, wm_lp;
2492
2493 results->enable_fbc_wm = merged->fbc_wm_enabled;
2494 results->partitioning = partitioning;
2495
2496 /* LP1+ register values */
2497 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2498 const struct intel_wm_level *r;
2499
2500 level = ilk_wm_lp_to_level(wm_lp, merged);
2501
2502 r = &merged->wm[level];
2503
2504 /*
2505 * Maintain the watermark values even if the level is
2506 * disabled. Doing otherwise could cause underruns.
2507 */
2508 results->wm_lp[wm_lp - 1] =
2509 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2510 (r->pri_val << WM1_LP_SR_SHIFT) |
2511 r->cur_val;
2512
2513 if (r->enable)
2514 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2515
2516 if (INTEL_INFO(dev)->gen >= 8)
2517 results->wm_lp[wm_lp - 1] |=
2518 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2519 else
2520 results->wm_lp[wm_lp - 1] |=
2521 r->fbc_val << WM1_LP_FBC_SHIFT;
2522
2523 /*
2524 * Always set WM1S_LP_EN when spr_val != 0, even if the
2525 * level is disabled. Doing otherwise could cause underruns.
2526 */
2527 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2528 WARN_ON(wm_lp != 1);
2529 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2530 } else
2531 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2532 }
2533
2534 /* LP0 register values */
2535 for_each_intel_crtc(dev, intel_crtc) {
2536 const struct intel_crtc_state *cstate =
2537 to_intel_crtc_state(intel_crtc->base.state);
2538 enum pipe pipe = intel_crtc->pipe;
2539 const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0];
2540
2541 if (WARN_ON(!r->enable))
2542 continue;
2543
2544 results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime;
2545
2546 results->wm_pipe[pipe] =
2547 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2548 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2549 r->cur_val;
2550 }
2551}
2552
2553/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2554 * case both are at the same level. Prefer r1 in case they're the same. */
2555static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2556 struct intel_pipe_wm *r1,
2557 struct intel_pipe_wm *r2)
2558{
2559 int level, max_level = ilk_wm_max_level(dev);
2560 int level1 = 0, level2 = 0;
2561
2562 for (level = 1; level <= max_level; level++) {
2563 if (r1->wm[level].enable)
2564 level1 = level;
2565 if (r2->wm[level].enable)
2566 level2 = level;
2567 }
2568
2569 if (level1 == level2) {
2570 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2571 return r2;
2572 else
2573 return r1;
2574 } else if (level1 > level2) {
2575 return r1;
2576 } else {
2577 return r2;
2578 }
2579}
2580
2581/* dirty bits used to track which watermarks need changes */
2582#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2583#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2584#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2585#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2586#define WM_DIRTY_FBC (1 << 24)
2587#define WM_DIRTY_DDB (1 << 25)
2588
2589static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2590 const struct ilk_wm_values *old,
2591 const struct ilk_wm_values *new)
2592{
2593 unsigned int dirty = 0;
2594 enum pipe pipe;
2595 int wm_lp;
2596
2597 for_each_pipe(dev_priv, pipe) {
2598 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2599 dirty |= WM_DIRTY_LINETIME(pipe);
2600 /* Must disable LP1+ watermarks too */
2601 dirty |= WM_DIRTY_LP_ALL;
2602 }
2603
2604 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2605 dirty |= WM_DIRTY_PIPE(pipe);
2606 /* Must disable LP1+ watermarks too */
2607 dirty |= WM_DIRTY_LP_ALL;
2608 }
2609 }
2610
2611 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2612 dirty |= WM_DIRTY_FBC;
2613 /* Must disable LP1+ watermarks too */
2614 dirty |= WM_DIRTY_LP_ALL;
2615 }
2616
2617 if (old->partitioning != new->partitioning) {
2618 dirty |= WM_DIRTY_DDB;
2619 /* Must disable LP1+ watermarks too */
2620 dirty |= WM_DIRTY_LP_ALL;
2621 }
2622
2623 /* LP1+ watermarks already deemed dirty, no need to continue */
2624 if (dirty & WM_DIRTY_LP_ALL)
2625 return dirty;
2626
2627 /* Find the lowest numbered LP1+ watermark in need of an update... */
2628 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2629 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2630 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2631 break;
2632 }
2633
2634 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2635 for (; wm_lp <= 3; wm_lp++)
2636 dirty |= WM_DIRTY_LP(wm_lp);
2637
2638 return dirty;
2639}
2640
2641static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2642 unsigned int dirty)
2643{
2644 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2645 bool changed = false;
2646
2647 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2648 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2649 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2650 changed = true;
2651 }
2652 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2653 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2654 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2655 changed = true;
2656 }
2657 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2658 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2659 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2660 changed = true;
2661 }
2662
2663 /*
2664 * Don't touch WM1S_LP_EN here.
2665 * Doing so could cause underruns.
2666 */
2667
2668 return changed;
2669}
2670
2671/*
2672 * The spec says we shouldn't write when we don't need, because every write
2673 * causes WMs to be re-evaluated, expending some power.
2674 */
2675static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2676 struct ilk_wm_values *results)
2677{
2678 struct drm_device *dev = dev_priv->dev;
2679 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2680 unsigned int dirty;
2681 uint32_t val;
2682
2683 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2684 if (!dirty)
2685 return;
2686
2687 _ilk_disable_lp_wm(dev_priv, dirty);
2688
2689 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2690 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2691 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2692 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2693 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2694 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2695
2696 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2697 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2698 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2699 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2700 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2701 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2702
2703 if (dirty & WM_DIRTY_DDB) {
2704 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2705 val = I915_READ(WM_MISC);
2706 if (results->partitioning == INTEL_DDB_PART_1_2)
2707 val &= ~WM_MISC_DATA_PARTITION_5_6;
2708 else
2709 val |= WM_MISC_DATA_PARTITION_5_6;
2710 I915_WRITE(WM_MISC, val);
2711 } else {
2712 val = I915_READ(DISP_ARB_CTL2);
2713 if (results->partitioning == INTEL_DDB_PART_1_2)
2714 val &= ~DISP_DATA_PARTITION_5_6;
2715 else
2716 val |= DISP_DATA_PARTITION_5_6;
2717 I915_WRITE(DISP_ARB_CTL2, val);
2718 }
2719 }
2720
2721 if (dirty & WM_DIRTY_FBC) {
2722 val = I915_READ(DISP_ARB_CTL);
2723 if (results->enable_fbc_wm)
2724 val &= ~DISP_FBC_WM_DIS;
2725 else
2726 val |= DISP_FBC_WM_DIS;
2727 I915_WRITE(DISP_ARB_CTL, val);
2728 }
2729
2730 if (dirty & WM_DIRTY_LP(1) &&
2731 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2732 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2733
2734 if (INTEL_INFO(dev)->gen >= 7) {
2735 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2736 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2737 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2738 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2739 }
2740
2741 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2742 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2743 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2744 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2745 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2746 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2747
2748 dev_priv->wm.hw = *results;
2749}
2750
2751static bool ilk_disable_lp_wm(struct drm_device *dev)
2752{
2753 struct drm_i915_private *dev_priv = dev->dev_private;
2754
2755 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2756}
2757
2758/*
2759 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2760 * different active planes.
2761 */
2762
2763#define SKL_DDB_SIZE 896 /* in blocks */
2764#define BXT_DDB_SIZE 512
2765
2766/*
2767 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2768 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2769 * other universal planes are in indices 1..n. Note that this may leave unused
2770 * indices between the top "sprite" plane and the cursor.
2771 */
2772static int
2773skl_wm_plane_id(const struct intel_plane *plane)
2774{
2775 switch (plane->base.type) {
2776 case DRM_PLANE_TYPE_PRIMARY:
2777 return 0;
2778 case DRM_PLANE_TYPE_CURSOR:
2779 return PLANE_CURSOR;
2780 case DRM_PLANE_TYPE_OVERLAY:
2781 return plane->plane + 1;
2782 default:
2783 MISSING_CASE(plane->base.type);
2784 return plane->plane;
2785 }
2786}
2787
2788static void
2789skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2790 const struct intel_crtc_state *cstate,
2791 const struct intel_wm_config *config,
2792 struct skl_ddb_entry *alloc /* out */)
2793{
2794 struct drm_crtc *for_crtc = cstate->base.crtc;
2795 struct drm_crtc *crtc;
2796 unsigned int pipe_size, ddb_size;
2797 int nth_active_pipe;
2798
2799 if (!cstate->base.active) {
2800 alloc->start = 0;
2801 alloc->end = 0;
2802 return;
2803 }
2804
2805 if (IS_BROXTON(dev))
2806 ddb_size = BXT_DDB_SIZE;
2807 else
2808 ddb_size = SKL_DDB_SIZE;
2809
2810 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2811
2812 nth_active_pipe = 0;
2813 for_each_crtc(dev, crtc) {
2814 if (!to_intel_crtc(crtc)->active)
2815 continue;
2816
2817 if (crtc == for_crtc)
2818 break;
2819
2820 nth_active_pipe++;
2821 }
2822
2823 pipe_size = ddb_size / config->num_pipes_active;
2824 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2825 alloc->end = alloc->start + pipe_size;
2826}
2827
2828static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2829{
2830 if (config->num_pipes_active == 1)
2831 return 32;
2832
2833 return 8;
2834}
2835
2836static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2837{
2838 entry->start = reg & 0x3ff;
2839 entry->end = (reg >> 16) & 0x3ff;
2840 if (entry->end)
2841 entry->end += 1;
2842}
2843
2844void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2845 struct skl_ddb_allocation *ddb /* out */)
2846{
2847 enum pipe pipe;
2848 int plane;
2849 u32 val;
2850
2851 memset(ddb, 0, sizeof(*ddb));
2852
2853 for_each_pipe(dev_priv, pipe) {
2854 enum intel_display_power_domain power_domain;
2855
2856 power_domain = POWER_DOMAIN_PIPE(pipe);
2857 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2858 continue;
2859
2860 for_each_plane(dev_priv, pipe, plane) {
2861 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2862 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2863 val);
2864 }
2865
2866 val = I915_READ(CUR_BUF_CFG(pipe));
2867 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2868 val);
2869
2870 intel_display_power_put(dev_priv, power_domain);
2871 }
2872}
2873
2874static unsigned int
2875skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2876 const struct drm_plane_state *pstate,
2877 int y)
2878{
2879 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
2880 struct drm_framebuffer *fb = pstate->fb;
2881 uint32_t width = 0, height = 0;
2882
2883 width = drm_rect_width(&intel_pstate->src) >> 16;
2884 height = drm_rect_height(&intel_pstate->src) >> 16;
2885
2886 if (intel_rotation_90_or_270(pstate->rotation))
2887 swap(width, height);
2888
2889 /* for planar format */
2890 if (fb->pixel_format == DRM_FORMAT_NV12) {
2891 if (y) /* y-plane data rate */
2892 return width * height *
2893 drm_format_plane_cpp(fb->pixel_format, 0);
2894 else /* uv-plane data rate */
2895 return (width / 2) * (height / 2) *
2896 drm_format_plane_cpp(fb->pixel_format, 1);
2897 }
2898
2899 /* for packed formats */
2900 return width * height * drm_format_plane_cpp(fb->pixel_format, 0);
2901}
2902
2903/*
2904 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2905 * a 8192x4096@32bpp framebuffer:
2906 * 3 * 4096 * 8192 * 4 < 2^32
2907 */
2908static unsigned int
2909skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
2910{
2911 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2912 struct drm_device *dev = intel_crtc->base.dev;
2913 const struct intel_plane *intel_plane;
2914 unsigned int total_data_rate = 0;
2915
2916 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2917 const struct drm_plane_state *pstate = intel_plane->base.state;
2918
2919 if (pstate->fb == NULL)
2920 continue;
2921
2922 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2923 continue;
2924
2925 /* packed/uv */
2926 total_data_rate += skl_plane_relative_data_rate(cstate,
2927 pstate,
2928 0);
2929
2930 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2931 /* y-plane */
2932 total_data_rate += skl_plane_relative_data_rate(cstate,
2933 pstate,
2934 1);
2935 }
2936
2937 return total_data_rate;
2938}
2939
2940static void
2941skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
2942 struct skl_ddb_allocation *ddb /* out */)
2943{
2944 struct drm_crtc *crtc = cstate->base.crtc;
2945 struct drm_device *dev = crtc->dev;
2946 struct drm_i915_private *dev_priv = to_i915(dev);
2947 struct intel_wm_config *config = &dev_priv->wm.config;
2948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2949 struct intel_plane *intel_plane;
2950 enum pipe pipe = intel_crtc->pipe;
2951 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2952 uint16_t alloc_size, start, cursor_blocks;
2953 uint16_t minimum[I915_MAX_PLANES];
2954 uint16_t y_minimum[I915_MAX_PLANES];
2955 unsigned int total_data_rate;
2956
2957 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
2958 alloc_size = skl_ddb_entry_size(alloc);
2959 if (alloc_size == 0) {
2960 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2961 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2962 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
2963 return;
2964 }
2965
2966 cursor_blocks = skl_cursor_allocation(config);
2967 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2968 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
2969
2970 alloc_size -= cursor_blocks;
2971 alloc->end -= cursor_blocks;
2972
2973 /* 1. Allocate the mininum required blocks for each active plane */
2974 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2975 struct drm_plane *plane = &intel_plane->base;
2976 struct drm_framebuffer *fb = plane->state->fb;
2977 int id = skl_wm_plane_id(intel_plane);
2978
2979 if (!to_intel_plane_state(plane->state)->visible)
2980 continue;
2981
2982 if (plane->type == DRM_PLANE_TYPE_CURSOR)
2983 continue;
2984
2985 minimum[id] = 8;
2986 alloc_size -= minimum[id];
2987 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
2988 alloc_size -= y_minimum[id];
2989 }
2990
2991 /*
2992 * 2. Distribute the remaining space in proportion to the amount of
2993 * data each plane needs to fetch from memory.
2994 *
2995 * FIXME: we may not allocate every single block here.
2996 */
2997 total_data_rate = skl_get_total_relative_data_rate(cstate);
2998
2999 start = alloc->start;
3000 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3001 struct drm_plane *plane = &intel_plane->base;
3002 struct drm_plane_state *pstate = intel_plane->base.state;
3003 unsigned int data_rate, y_data_rate;
3004 uint16_t plane_blocks, y_plane_blocks = 0;
3005 int id = skl_wm_plane_id(intel_plane);
3006
3007 if (!to_intel_plane_state(pstate)->visible)
3008 continue;
3009 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3010 continue;
3011
3012 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
3013
3014 /*
3015 * allocation for (packed formats) or (uv-plane part of planar format):
3016 * promote the expression to 64 bits to avoid overflowing, the
3017 * result is < available as data_rate / total_data_rate < 1
3018 */
3019 plane_blocks = minimum[id];
3020 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3021 total_data_rate);
3022
3023 ddb->plane[pipe][id].start = start;
3024 ddb->plane[pipe][id].end = start + plane_blocks;
3025
3026 start += plane_blocks;
3027
3028 /*
3029 * allocation for y_plane part of planar format:
3030 */
3031 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3032 y_data_rate = skl_plane_relative_data_rate(cstate,
3033 pstate,
3034 1);
3035 y_plane_blocks = y_minimum[id];
3036 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3037 total_data_rate);
3038
3039 ddb->y_plane[pipe][id].start = start;
3040 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3041
3042 start += y_plane_blocks;
3043 }
3044
3045 }
3046
3047}
3048
3049static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3050{
3051 /* TODO: Take into account the scalers once we support them */
3052 return config->base.adjusted_mode.crtc_clock;
3053}
3054
3055/*
3056 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3057 * for the read latency) and cpp should always be <= 8, so that
3058 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3059 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3060*/
3061static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3062{
3063 uint32_t wm_intermediate_val, ret;
3064
3065 if (latency == 0)
3066 return UINT_MAX;
3067
3068 wm_intermediate_val = latency * pixel_rate * cpp / 512;
3069 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3070
3071 return ret;
3072}
3073
3074static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3075 uint32_t horiz_pixels, uint8_t cpp,
3076 uint64_t tiling, uint32_t latency)
3077{
3078 uint32_t ret;
3079 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3080 uint32_t wm_intermediate_val;
3081
3082 if (latency == 0)
3083 return UINT_MAX;
3084
3085 plane_bytes_per_line = horiz_pixels * cpp;
3086
3087 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3088 tiling == I915_FORMAT_MOD_Yf_TILED) {
3089 plane_bytes_per_line *= 4;
3090 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3091 plane_blocks_per_line /= 4;
3092 } else {
3093 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3094 }
3095
3096 wm_intermediate_val = latency * pixel_rate;
3097 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3098 plane_blocks_per_line;
3099
3100 return ret;
3101}
3102
3103static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3104 const struct intel_crtc *intel_crtc)
3105{
3106 struct drm_device *dev = intel_crtc->base.dev;
3107 struct drm_i915_private *dev_priv = dev->dev_private;
3108 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3109
3110 /*
3111 * If ddb allocation of pipes changed, it may require recalculation of
3112 * watermarks
3113 */
3114 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
3115 return true;
3116
3117 return false;
3118}
3119
3120static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3121 struct intel_crtc_state *cstate,
3122 struct intel_plane *intel_plane,
3123 uint16_t ddb_allocation,
3124 int level,
3125 uint16_t *out_blocks, /* out */
3126 uint8_t *out_lines /* out */)
3127{
3128 struct drm_plane *plane = &intel_plane->base;
3129 struct drm_framebuffer *fb = plane->state->fb;
3130 struct intel_plane_state *intel_pstate =
3131 to_intel_plane_state(plane->state);
3132 uint32_t latency = dev_priv->wm.skl_latency[level];
3133 uint32_t method1, method2;
3134 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3135 uint32_t res_blocks, res_lines;
3136 uint32_t selected_result;
3137 uint8_t cpp;
3138 uint32_t width = 0, height = 0;
3139
3140 if (latency == 0 || !cstate->base.active || !intel_pstate->visible)
3141 return false;
3142
3143 width = drm_rect_width(&intel_pstate->src) >> 16;
3144 height = drm_rect_height(&intel_pstate->src) >> 16;
3145
3146 if (intel_rotation_90_or_270(plane->state->rotation))
3147 swap(width, height);
3148
3149 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3150 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
3151 cpp, latency);
3152 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3153 cstate->base.adjusted_mode.crtc_htotal,
3154 width,
3155 cpp,
3156 fb->modifier[0],
3157 latency);
3158
3159 plane_bytes_per_line = width * cpp;
3160 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3161
3162 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3163 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3164 uint32_t min_scanlines = 4;
3165 uint32_t y_tile_minimum;
3166 if (intel_rotation_90_or_270(plane->state->rotation)) {
3167 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3168 drm_format_plane_cpp(fb->pixel_format, 1) :
3169 drm_format_plane_cpp(fb->pixel_format, 0);
3170
3171 switch (cpp) {
3172 case 1:
3173 min_scanlines = 16;
3174 break;
3175 case 2:
3176 min_scanlines = 8;
3177 break;
3178 case 8:
3179 WARN(1, "Unsupported pixel depth for rotation");
3180 }
3181 }
3182 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3183 selected_result = max(method2, y_tile_minimum);
3184 } else {
3185 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3186 selected_result = min(method1, method2);
3187 else
3188 selected_result = method1;
3189 }
3190
3191 res_blocks = selected_result + 1;
3192 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3193
3194 if (level >= 1 && level <= 7) {
3195 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3196 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3197 res_lines += 4;
3198 else
3199 res_blocks++;
3200 }
3201
3202 if (res_blocks >= ddb_allocation || res_lines > 31)
3203 return false;
3204
3205 *out_blocks = res_blocks;
3206 *out_lines = res_lines;
3207
3208 return true;
3209}
3210
3211static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3212 struct skl_ddb_allocation *ddb,
3213 struct intel_crtc_state *cstate,
3214 int level,
3215 struct skl_wm_level *result)
3216{
3217 struct drm_device *dev = dev_priv->dev;
3218 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3219 struct intel_plane *intel_plane;
3220 uint16_t ddb_blocks;
3221 enum pipe pipe = intel_crtc->pipe;
3222
3223 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3224 int i = skl_wm_plane_id(intel_plane);
3225
3226 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3227
3228 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3229 cstate,
3230 intel_plane,
3231 ddb_blocks,
3232 level,
3233 &result->plane_res_b[i],
3234 &result->plane_res_l[i]);
3235 }
3236}
3237
3238static uint32_t
3239skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3240{
3241 if (!cstate->base.active)
3242 return 0;
3243
3244 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3245 return 0;
3246
3247 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3248 skl_pipe_pixel_rate(cstate));
3249}
3250
3251static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3252 struct skl_wm_level *trans_wm /* out */)
3253{
3254 struct drm_crtc *crtc = cstate->base.crtc;
3255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3256 struct intel_plane *intel_plane;
3257
3258 if (!cstate->base.active)
3259 return;
3260
3261 /* Until we know more, just disable transition WMs */
3262 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3263 int i = skl_wm_plane_id(intel_plane);
3264
3265 trans_wm->plane_en[i] = false;
3266 }
3267}
3268
3269static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
3270 struct skl_ddb_allocation *ddb,
3271 struct skl_pipe_wm *pipe_wm)
3272{
3273 struct drm_device *dev = cstate->base.crtc->dev;
3274 const struct drm_i915_private *dev_priv = dev->dev_private;
3275 int level, max_level = ilk_wm_max_level(dev);
3276
3277 for (level = 0; level <= max_level; level++) {
3278 skl_compute_wm_level(dev_priv, ddb, cstate,
3279 level, &pipe_wm->wm[level]);
3280 }
3281 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3282
3283 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3284}
3285
3286static void skl_compute_wm_results(struct drm_device *dev,
3287 struct skl_pipe_wm *p_wm,
3288 struct skl_wm_values *r,
3289 struct intel_crtc *intel_crtc)
3290{
3291 int level, max_level = ilk_wm_max_level(dev);
3292 enum pipe pipe = intel_crtc->pipe;
3293 uint32_t temp;
3294 int i;
3295
3296 for (level = 0; level <= max_level; level++) {
3297 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3298 temp = 0;
3299
3300 temp |= p_wm->wm[level].plane_res_l[i] <<
3301 PLANE_WM_LINES_SHIFT;
3302 temp |= p_wm->wm[level].plane_res_b[i];
3303 if (p_wm->wm[level].plane_en[i])
3304 temp |= PLANE_WM_EN;
3305
3306 r->plane[pipe][i][level] = temp;
3307 }
3308
3309 temp = 0;
3310
3311 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3312 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3313
3314 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3315 temp |= PLANE_WM_EN;
3316
3317 r->plane[pipe][PLANE_CURSOR][level] = temp;
3318
3319 }
3320
3321 /* transition WMs */
3322 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3323 temp = 0;
3324 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3325 temp |= p_wm->trans_wm.plane_res_b[i];
3326 if (p_wm->trans_wm.plane_en[i])
3327 temp |= PLANE_WM_EN;
3328
3329 r->plane_trans[pipe][i] = temp;
3330 }
3331
3332 temp = 0;
3333 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3334 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3335 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3336 temp |= PLANE_WM_EN;
3337
3338 r->plane_trans[pipe][PLANE_CURSOR] = temp;
3339
3340 r->wm_linetime[pipe] = p_wm->linetime;
3341}
3342
3343static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3344 i915_reg_t reg,
3345 const struct skl_ddb_entry *entry)
3346{
3347 if (entry->end)
3348 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3349 else
3350 I915_WRITE(reg, 0);
3351}
3352
3353static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3354 const struct skl_wm_values *new)
3355{
3356 struct drm_device *dev = dev_priv->dev;
3357 struct intel_crtc *crtc;
3358
3359 for_each_intel_crtc(dev, crtc) {
3360 int i, level, max_level = ilk_wm_max_level(dev);
3361 enum pipe pipe = crtc->pipe;
3362
3363 if (!new->dirty[pipe])
3364 continue;
3365
3366 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3367
3368 for (level = 0; level <= max_level; level++) {
3369 for (i = 0; i < intel_num_planes(crtc); i++)
3370 I915_WRITE(PLANE_WM(pipe, i, level),
3371 new->plane[pipe][i][level]);
3372 I915_WRITE(CUR_WM(pipe, level),
3373 new->plane[pipe][PLANE_CURSOR][level]);
3374 }
3375 for (i = 0; i < intel_num_planes(crtc); i++)
3376 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3377 new->plane_trans[pipe][i]);
3378 I915_WRITE(CUR_WM_TRANS(pipe),
3379 new->plane_trans[pipe][PLANE_CURSOR]);
3380
3381 for (i = 0; i < intel_num_planes(crtc); i++) {
3382 skl_ddb_entry_write(dev_priv,
3383 PLANE_BUF_CFG(pipe, i),
3384 &new->ddb.plane[pipe][i]);
3385 skl_ddb_entry_write(dev_priv,
3386 PLANE_NV12_BUF_CFG(pipe, i),
3387 &new->ddb.y_plane[pipe][i]);
3388 }
3389
3390 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3391 &new->ddb.plane[pipe][PLANE_CURSOR]);
3392 }
3393}
3394
3395/*
3396 * When setting up a new DDB allocation arrangement, we need to correctly
3397 * sequence the times at which the new allocations for the pipes are taken into
3398 * account or we'll have pipes fetching from space previously allocated to
3399 * another pipe.
3400 *
3401 * Roughly the sequence looks like:
3402 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3403 * overlapping with a previous light-up pipe (another way to put it is:
3404 * pipes with their new allocation strickly included into their old ones).
3405 * 2. re-allocate the other pipes that get their allocation reduced
3406 * 3. allocate the pipes having their allocation increased
3407 *
3408 * Steps 1. and 2. are here to take care of the following case:
3409 * - Initially DDB looks like this:
3410 * | B | C |
3411 * - enable pipe A.
3412 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3413 * allocation
3414 * | A | B | C |
3415 *
3416 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3417 */
3418
3419static void
3420skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3421{
3422 int plane;
3423
3424 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3425
3426 for_each_plane(dev_priv, pipe, plane) {
3427 I915_WRITE(PLANE_SURF(pipe, plane),
3428 I915_READ(PLANE_SURF(pipe, plane)));
3429 }
3430 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3431}
3432
3433static bool
3434skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3435 const struct skl_ddb_allocation *new,
3436 enum pipe pipe)
3437{
3438 uint16_t old_size, new_size;
3439
3440 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3441 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3442
3443 return old_size != new_size &&
3444 new->pipe[pipe].start >= old->pipe[pipe].start &&
3445 new->pipe[pipe].end <= old->pipe[pipe].end;
3446}
3447
3448static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3449 struct skl_wm_values *new_values)
3450{
3451 struct drm_device *dev = dev_priv->dev;
3452 struct skl_ddb_allocation *cur_ddb, *new_ddb;
3453 bool reallocated[I915_MAX_PIPES] = {};
3454 struct intel_crtc *crtc;
3455 enum pipe pipe;
3456
3457 new_ddb = &new_values->ddb;
3458 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3459
3460 /*
3461 * First pass: flush the pipes with the new allocation contained into
3462 * the old space.
3463 *
3464 * We'll wait for the vblank on those pipes to ensure we can safely
3465 * re-allocate the freed space without this pipe fetching from it.
3466 */
3467 for_each_intel_crtc(dev, crtc) {
3468 if (!crtc->active)
3469 continue;
3470
3471 pipe = crtc->pipe;
3472
3473 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3474 continue;
3475
3476 skl_wm_flush_pipe(dev_priv, pipe, 1);
3477 intel_wait_for_vblank(dev, pipe);
3478
3479 reallocated[pipe] = true;
3480 }
3481
3482
3483 /*
3484 * Second pass: flush the pipes that are having their allocation
3485 * reduced, but overlapping with a previous allocation.
3486 *
3487 * Here as well we need to wait for the vblank to make sure the freed
3488 * space is not used anymore.
3489 */
3490 for_each_intel_crtc(dev, crtc) {
3491 if (!crtc->active)
3492 continue;
3493
3494 pipe = crtc->pipe;
3495
3496 if (reallocated[pipe])
3497 continue;
3498
3499 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3500 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3501 skl_wm_flush_pipe(dev_priv, pipe, 2);
3502 intel_wait_for_vblank(dev, pipe);
3503 reallocated[pipe] = true;
3504 }
3505 }
3506
3507 /*
3508 * Third pass: flush the pipes that got more space allocated.
3509 *
3510 * We don't need to actively wait for the update here, next vblank
3511 * will just get more DDB space with the correct WM values.
3512 */
3513 for_each_intel_crtc(dev, crtc) {
3514 if (!crtc->active)
3515 continue;
3516
3517 pipe = crtc->pipe;
3518
3519 /*
3520 * At this point, only the pipes more space than before are
3521 * left to re-allocate.
3522 */
3523 if (reallocated[pipe])
3524 continue;
3525
3526 skl_wm_flush_pipe(dev_priv, pipe, 3);
3527 }
3528}
3529
3530static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3531 struct skl_ddb_allocation *ddb, /* out */
3532 struct skl_pipe_wm *pipe_wm /* out */)
3533{
3534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3535 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3536
3537 skl_allocate_pipe_ddb(cstate, ddb);
3538 skl_compute_pipe_wm(cstate, ddb, pipe_wm);
3539
3540 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3541 return false;
3542
3543 intel_crtc->wm.active.skl = *pipe_wm;
3544
3545 return true;
3546}
3547
3548static void skl_update_other_pipe_wm(struct drm_device *dev,
3549 struct drm_crtc *crtc,
3550 struct skl_wm_values *r)
3551{
3552 struct intel_crtc *intel_crtc;
3553 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3554
3555 /*
3556 * If the WM update hasn't changed the allocation for this_crtc (the
3557 * crtc we are currently computing the new WM values for), other
3558 * enabled crtcs will keep the same allocation and we don't need to
3559 * recompute anything for them.
3560 */
3561 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3562 return;
3563
3564 /*
3565 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3566 * other active pipes need new DDB allocation and WM values.
3567 */
3568 for_each_intel_crtc(dev, intel_crtc) {
3569 struct skl_pipe_wm pipe_wm = {};
3570 bool wm_changed;
3571
3572 if (this_crtc->pipe == intel_crtc->pipe)
3573 continue;
3574
3575 if (!intel_crtc->active)
3576 continue;
3577
3578 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3579 &r->ddb, &pipe_wm);
3580
3581 /*
3582 * If we end up re-computing the other pipe WM values, it's
3583 * because it was really needed, so we expect the WM values to
3584 * be different.
3585 */
3586 WARN_ON(!wm_changed);
3587
3588 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
3589 r->dirty[intel_crtc->pipe] = true;
3590 }
3591}
3592
3593static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3594{
3595 watermarks->wm_linetime[pipe] = 0;
3596 memset(watermarks->plane[pipe], 0,
3597 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3598 memset(watermarks->plane_trans[pipe],
3599 0, sizeof(uint32_t) * I915_MAX_PLANES);
3600 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3601
3602 /* Clear ddb entries for pipe */
3603 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3604 memset(&watermarks->ddb.plane[pipe], 0,
3605 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3606 memset(&watermarks->ddb.y_plane[pipe], 0,
3607 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3608 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3609 sizeof(struct skl_ddb_entry));
3610
3611}
3612
3613static void skl_update_wm(struct drm_crtc *crtc)
3614{
3615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3616 struct drm_device *dev = crtc->dev;
3617 struct drm_i915_private *dev_priv = dev->dev_private;
3618 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3619 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3620 struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
3621
3622
3623 /* Clear all dirty flags */
3624 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3625
3626 skl_clear_wm(results, intel_crtc->pipe);
3627
3628 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
3629 return;
3630
3631 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
3632 results->dirty[intel_crtc->pipe] = true;
3633
3634 skl_update_other_pipe_wm(dev, crtc, results);
3635 skl_write_wm_values(dev_priv, results);
3636 skl_flush_wm_values(dev_priv, results);
3637
3638 /* store the new configuration */
3639 dev_priv->wm.skl_hw = *results;
3640}
3641
3642static void ilk_compute_wm_config(struct drm_device *dev,
3643 struct intel_wm_config *config)
3644{
3645 struct intel_crtc *crtc;
3646
3647 /* Compute the currently _active_ config */
3648 for_each_intel_crtc(dev, crtc) {
3649 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3650
3651 if (!wm->pipe_enabled)
3652 continue;
3653
3654 config->sprites_enabled |= wm->sprites_enabled;
3655 config->sprites_scaled |= wm->sprites_scaled;
3656 config->num_pipes_active++;
3657 }
3658}
3659
3660static void ilk_program_watermarks(struct intel_crtc_state *cstate)
3661{
3662 struct drm_crtc *crtc = cstate->base.crtc;
3663 struct drm_device *dev = crtc->dev;
3664 struct drm_i915_private *dev_priv = to_i915(dev);
3665 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3666 struct ilk_wm_maximums max;
3667 struct intel_wm_config config = {};
3668 struct ilk_wm_values results = {};
3669 enum intel_ddb_partitioning partitioning;
3670
3671 ilk_compute_wm_config(dev, &config);
3672
3673 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3674 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3675
3676 /* 5/6 split only in single pipe config on IVB+ */
3677 if (INTEL_INFO(dev)->gen >= 7 &&
3678 config.num_pipes_active == 1 && config.sprites_enabled) {
3679 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3680 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3681
3682 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3683 } else {
3684 best_lp_wm = &lp_wm_1_2;
3685 }
3686
3687 partitioning = (best_lp_wm == &lp_wm_1_2) ?
3688 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3689
3690 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3691
3692 ilk_write_wm_values(dev_priv, &results);
3693}
3694
3695static void ilk_update_wm(struct drm_crtc *crtc)
3696{
3697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3698 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3699
3700 WARN_ON(cstate->base.active != intel_crtc->active);
3701
3702 /*
3703 * IVB workaround: must disable low power watermarks for at least
3704 * one frame before enabling scaling. LP watermarks can be re-enabled
3705 * when scaling is disabled.
3706 *
3707 * WaCxSRDisabledForSpriteScaling:ivb
3708 */
3709 if (cstate->disable_lp_wm) {
3710 ilk_disable_lp_wm(crtc->dev);
3711 intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
3712 }
3713
3714 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3715
3716 ilk_program_watermarks(cstate);
3717}
3718
3719static void skl_pipe_wm_active_state(uint32_t val,
3720 struct skl_pipe_wm *active,
3721 bool is_transwm,
3722 bool is_cursor,
3723 int i,
3724 int level)
3725{
3726 bool is_enabled = (val & PLANE_WM_EN) != 0;
3727
3728 if (!is_transwm) {
3729 if (!is_cursor) {
3730 active->wm[level].plane_en[i] = is_enabled;
3731 active->wm[level].plane_res_b[i] =
3732 val & PLANE_WM_BLOCKS_MASK;
3733 active->wm[level].plane_res_l[i] =
3734 (val >> PLANE_WM_LINES_SHIFT) &
3735 PLANE_WM_LINES_MASK;
3736 } else {
3737 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3738 active->wm[level].plane_res_b[PLANE_CURSOR] =
3739 val & PLANE_WM_BLOCKS_MASK;
3740 active->wm[level].plane_res_l[PLANE_CURSOR] =
3741 (val >> PLANE_WM_LINES_SHIFT) &
3742 PLANE_WM_LINES_MASK;
3743 }
3744 } else {
3745 if (!is_cursor) {
3746 active->trans_wm.plane_en[i] = is_enabled;
3747 active->trans_wm.plane_res_b[i] =
3748 val & PLANE_WM_BLOCKS_MASK;
3749 active->trans_wm.plane_res_l[i] =
3750 (val >> PLANE_WM_LINES_SHIFT) &
3751 PLANE_WM_LINES_MASK;
3752 } else {
3753 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3754 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3755 val & PLANE_WM_BLOCKS_MASK;
3756 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3757 (val >> PLANE_WM_LINES_SHIFT) &
3758 PLANE_WM_LINES_MASK;
3759 }
3760 }
3761}
3762
3763static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3764{
3765 struct drm_device *dev = crtc->dev;
3766 struct drm_i915_private *dev_priv = dev->dev_private;
3767 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3769 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3770 struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3771 enum pipe pipe = intel_crtc->pipe;
3772 int level, i, max_level;
3773 uint32_t temp;
3774
3775 max_level = ilk_wm_max_level(dev);
3776
3777 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3778
3779 for (level = 0; level <= max_level; level++) {
3780 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3781 hw->plane[pipe][i][level] =
3782 I915_READ(PLANE_WM(pipe, i, level));
3783 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3784 }
3785
3786 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3787 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3788 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3789
3790 if (!intel_crtc->active)
3791 return;
3792
3793 hw->dirty[pipe] = true;
3794
3795 active->linetime = hw->wm_linetime[pipe];
3796
3797 for (level = 0; level <= max_level; level++) {
3798 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3799 temp = hw->plane[pipe][i][level];
3800 skl_pipe_wm_active_state(temp, active, false,
3801 false, i, level);
3802 }
3803 temp = hw->plane[pipe][PLANE_CURSOR][level];
3804 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3805 }
3806
3807 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3808 temp = hw->plane_trans[pipe][i];
3809 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3810 }
3811
3812 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3813 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3814
3815 intel_crtc->wm.active.skl = *active;
3816}
3817
3818void skl_wm_get_hw_state(struct drm_device *dev)
3819{
3820 struct drm_i915_private *dev_priv = dev->dev_private;
3821 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3822 struct drm_crtc *crtc;
3823
3824 skl_ddb_get_hw_state(dev_priv, ddb);
3825 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3826 skl_pipe_wm_get_hw_state(crtc);
3827}
3828
3829static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3830{
3831 struct drm_device *dev = crtc->dev;
3832 struct drm_i915_private *dev_priv = dev->dev_private;
3833 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3835 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3836 struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
3837 enum pipe pipe = intel_crtc->pipe;
3838 static const i915_reg_t wm0_pipe_reg[] = {
3839 [PIPE_A] = WM0_PIPEA_ILK,
3840 [PIPE_B] = WM0_PIPEB_ILK,
3841 [PIPE_C] = WM0_PIPEC_IVB,
3842 };
3843
3844 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3845 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3846 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3847
3848 active->pipe_enabled = intel_crtc->active;
3849
3850 if (active->pipe_enabled) {
3851 u32 tmp = hw->wm_pipe[pipe];
3852
3853 /*
3854 * For active pipes LP0 watermark is marked as
3855 * enabled, and LP1+ watermaks as disabled since
3856 * we can't really reverse compute them in case
3857 * multiple pipes are active.
3858 */
3859 active->wm[0].enable = true;
3860 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3861 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3862 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3863 active->linetime = hw->wm_linetime[pipe];
3864 } else {
3865 int level, max_level = ilk_wm_max_level(dev);
3866
3867 /*
3868 * For inactive pipes, all watermark levels
3869 * should be marked as enabled but zeroed,
3870 * which is what we'd compute them to.
3871 */
3872 for (level = 0; level <= max_level; level++)
3873 active->wm[level].enable = true;
3874 }
3875
3876 intel_crtc->wm.active.ilk = *active;
3877}
3878
3879#define _FW_WM(value, plane) \
3880 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3881#define _FW_WM_VLV(value, plane) \
3882 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3883
3884static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3885 struct vlv_wm_values *wm)
3886{
3887 enum pipe pipe;
3888 uint32_t tmp;
3889
3890 for_each_pipe(dev_priv, pipe) {
3891 tmp = I915_READ(VLV_DDL(pipe));
3892
3893 wm->ddl[pipe].primary =
3894 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3895 wm->ddl[pipe].cursor =
3896 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3897 wm->ddl[pipe].sprite[0] =
3898 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3899 wm->ddl[pipe].sprite[1] =
3900 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3901 }
3902
3903 tmp = I915_READ(DSPFW1);
3904 wm->sr.plane = _FW_WM(tmp, SR);
3905 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3906 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3907 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3908
3909 tmp = I915_READ(DSPFW2);
3910 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3911 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3912 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3913
3914 tmp = I915_READ(DSPFW3);
3915 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3916
3917 if (IS_CHERRYVIEW(dev_priv)) {
3918 tmp = I915_READ(DSPFW7_CHV);
3919 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3920 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3921
3922 tmp = I915_READ(DSPFW8_CHV);
3923 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3924 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3925
3926 tmp = I915_READ(DSPFW9_CHV);
3927 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3928 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3929
3930 tmp = I915_READ(DSPHOWM);
3931 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3932 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3933 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3934 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3935 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3936 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3937 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3938 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3939 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3940 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3941 } else {
3942 tmp = I915_READ(DSPFW7);
3943 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3944 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3945
3946 tmp = I915_READ(DSPHOWM);
3947 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3948 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3949 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3950 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3951 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3952 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3953 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3954 }
3955}
3956
3957#undef _FW_WM
3958#undef _FW_WM_VLV
3959
3960void vlv_wm_get_hw_state(struct drm_device *dev)
3961{
3962 struct drm_i915_private *dev_priv = to_i915(dev);
3963 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3964 struct intel_plane *plane;
3965 enum pipe pipe;
3966 u32 val;
3967
3968 vlv_read_wm_values(dev_priv, wm);
3969
3970 for_each_intel_plane(dev, plane) {
3971 switch (plane->base.type) {
3972 int sprite;
3973 case DRM_PLANE_TYPE_CURSOR:
3974 plane->wm.fifo_size = 63;
3975 break;
3976 case DRM_PLANE_TYPE_PRIMARY:
3977 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
3978 break;
3979 case DRM_PLANE_TYPE_OVERLAY:
3980 sprite = plane->plane;
3981 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
3982 break;
3983 }
3984 }
3985
3986 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
3987 wm->level = VLV_WM_LEVEL_PM2;
3988
3989 if (IS_CHERRYVIEW(dev_priv)) {
3990 mutex_lock(&dev_priv->rps.hw_lock);
3991
3992 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3993 if (val & DSP_MAXFIFO_PM5_ENABLE)
3994 wm->level = VLV_WM_LEVEL_PM5;
3995
3996 /*
3997 * If DDR DVFS is disabled in the BIOS, Punit
3998 * will never ack the request. So if that happens
3999 * assume we don't have to enable/disable DDR DVFS
4000 * dynamically. To test that just set the REQ_ACK
4001 * bit to poke the Punit, but don't change the
4002 * HIGH/LOW bits so that we don't actually change
4003 * the current state.
4004 */
4005 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4006 val |= FORCE_DDR_FREQ_REQ_ACK;
4007 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4008
4009 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4010 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4011 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4012 "assuming DDR DVFS is disabled\n");
4013 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4014 } else {
4015 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4016 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4017 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4018 }
4019
4020 mutex_unlock(&dev_priv->rps.hw_lock);
4021 }
4022
4023 for_each_pipe(dev_priv, pipe)
4024 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4025 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4026 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4027
4028 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4029 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4030}
4031
4032void ilk_wm_get_hw_state(struct drm_device *dev)
4033{
4034 struct drm_i915_private *dev_priv = dev->dev_private;
4035 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4036 struct drm_crtc *crtc;
4037
4038 for_each_crtc(dev, crtc)
4039 ilk_pipe_wm_get_hw_state(crtc);
4040
4041 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4042 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4043 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4044
4045 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4046 if (INTEL_INFO(dev)->gen >= 7) {
4047 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4048 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4049 }
4050
4051 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4052 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4053 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4054 else if (IS_IVYBRIDGE(dev))
4055 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4056 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4057
4058 hw->enable_fbc_wm =
4059 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4060}
4061
4062/**
4063 * intel_update_watermarks - update FIFO watermark values based on current modes
4064 *
4065 * Calculate watermark values for the various WM regs based on current mode
4066 * and plane configuration.
4067 *
4068 * There are several cases to deal with here:
4069 * - normal (i.e. non-self-refresh)
4070 * - self-refresh (SR) mode
4071 * - lines are large relative to FIFO size (buffer can hold up to 2)
4072 * - lines are small relative to FIFO size (buffer can hold more than 2
4073 * lines), so need to account for TLB latency
4074 *
4075 * The normal calculation is:
4076 * watermark = dotclock * bytes per pixel * latency
4077 * where latency is platform & configuration dependent (we assume pessimal
4078 * values here).
4079 *
4080 * The SR calculation is:
4081 * watermark = (trunc(latency/line time)+1) * surface width *
4082 * bytes per pixel
4083 * where
4084 * line time = htotal / dotclock
4085 * surface width = hdisplay for normal plane and 64 for cursor
4086 * and latency is assumed to be high, as above.
4087 *
4088 * The final value programmed to the register should always be rounded up,
4089 * and include an extra 2 entries to account for clock crossings.
4090 *
4091 * We don't use the sprite, so we can ignore that. And on Crestline we have
4092 * to set the non-SR watermarks to 8.
4093 */
4094void intel_update_watermarks(struct drm_crtc *crtc)
4095{
4096 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4097
4098 if (dev_priv->display.update_wm)
4099 dev_priv->display.update_wm(crtc);
4100}
4101
4102/*
4103 * Lock protecting IPS related data structures
4104 */
4105DEFINE_SPINLOCK(mchdev_lock);
4106
4107/* Global for IPS driver to get at the current i915 device. Protected by
4108 * mchdev_lock. */
4109static struct drm_i915_private *i915_mch_dev;
4110
4111bool ironlake_set_drps(struct drm_device *dev, u8 val)
4112{
4113 struct drm_i915_private *dev_priv = dev->dev_private;
4114 u16 rgvswctl;
4115
4116 assert_spin_locked(&mchdev_lock);
4117
4118 rgvswctl = I915_READ16(MEMSWCTL);
4119 if (rgvswctl & MEMCTL_CMD_STS) {
4120 DRM_DEBUG("gpu busy, RCS change rejected\n");
4121 return false; /* still busy with another command */
4122 }
4123
4124 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4125 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4126 I915_WRITE16(MEMSWCTL, rgvswctl);
4127 POSTING_READ16(MEMSWCTL);
4128
4129 rgvswctl |= MEMCTL_CMD_STS;
4130 I915_WRITE16(MEMSWCTL, rgvswctl);
4131
4132 return true;
4133}
4134
4135static void ironlake_enable_drps(struct drm_device *dev)
4136{
4137 struct drm_i915_private *dev_priv = dev->dev_private;
4138 u32 rgvmodectl;
4139 u8 fmax, fmin, fstart, vstart;
4140
4141 spin_lock_irq(&mchdev_lock);
4142
4143 rgvmodectl = I915_READ(MEMMODECTL);
4144
4145 /* Enable temp reporting */
4146 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4147 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4148
4149 /* 100ms RC evaluation intervals */
4150 I915_WRITE(RCUPEI, 100000);
4151 I915_WRITE(RCDNEI, 100000);
4152
4153 /* Set max/min thresholds to 90ms and 80ms respectively */
4154 I915_WRITE(RCBMAXAVG, 90000);
4155 I915_WRITE(RCBMINAVG, 80000);
4156
4157 I915_WRITE(MEMIHYST, 1);
4158
4159 /* Set up min, max, and cur for interrupt handling */
4160 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4161 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4162 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4163 MEMMODE_FSTART_SHIFT;
4164
4165 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4166 PXVFREQ_PX_SHIFT;
4167
4168 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4169 dev_priv->ips.fstart = fstart;
4170
4171 dev_priv->ips.max_delay = fstart;
4172 dev_priv->ips.min_delay = fmin;
4173 dev_priv->ips.cur_delay = fstart;
4174
4175 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4176 fmax, fmin, fstart);
4177
4178 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4179
4180 /*
4181 * Interrupts will be enabled in ironlake_irq_postinstall
4182 */
4183
4184 I915_WRITE(VIDSTART, vstart);
4185 POSTING_READ(VIDSTART);
4186
4187 rgvmodectl |= MEMMODE_SWMODE_EN;
4188 I915_WRITE(MEMMODECTL, rgvmodectl);
4189
4190 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4191 DRM_ERROR("stuck trying to change perf mode\n");
4192 mdelay(1);
4193
4194 ironlake_set_drps(dev, fstart);
4195
4196 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4197 I915_READ(DDREC) + I915_READ(CSIEC);
4198 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4199 dev_priv->ips.last_count2 = I915_READ(GFXEC);
4200 dev_priv->ips.last_time2 = ktime_get_raw_ns();
4201
4202 spin_unlock_irq(&mchdev_lock);
4203}
4204
4205static void ironlake_disable_drps(struct drm_device *dev)
4206{
4207 struct drm_i915_private *dev_priv = dev->dev_private;
4208 u16 rgvswctl;
4209
4210 spin_lock_irq(&mchdev_lock);
4211
4212 rgvswctl = I915_READ16(MEMSWCTL);
4213
4214 /* Ack interrupts, disable EFC interrupt */
4215 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4216 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4217 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4218 I915_WRITE(DEIIR, DE_PCU_EVENT);
4219 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4220
4221 /* Go back to the starting frequency */
4222 ironlake_set_drps(dev, dev_priv->ips.fstart);
4223 mdelay(1);
4224 rgvswctl |= MEMCTL_CMD_STS;
4225 I915_WRITE(MEMSWCTL, rgvswctl);
4226 mdelay(1);
4227
4228 spin_unlock_irq(&mchdev_lock);
4229}
4230
4231/* There's a funny hw issue where the hw returns all 0 when reading from
4232 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4233 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4234 * all limits and the gpu stuck at whatever frequency it is at atm).
4235 */
4236static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4237{
4238 u32 limits;
4239
4240 /* Only set the down limit when we've reached the lowest level to avoid
4241 * getting more interrupts, otherwise leave this clear. This prevents a
4242 * race in the hw when coming out of rc6: There's a tiny window where
4243 * the hw runs at the minimal clock before selecting the desired
4244 * frequency, if the down threshold expires in that window we will not
4245 * receive a down interrupt. */
4246 if (IS_GEN9(dev_priv->dev)) {
4247 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4248 if (val <= dev_priv->rps.min_freq_softlimit)
4249 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4250 } else {
4251 limits = dev_priv->rps.max_freq_softlimit << 24;
4252 if (val <= dev_priv->rps.min_freq_softlimit)
4253 limits |= dev_priv->rps.min_freq_softlimit << 16;
4254 }
4255
4256 return limits;
4257}
4258
4259static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4260{
4261 int new_power;
4262 u32 threshold_up = 0, threshold_down = 0; /* in % */
4263 u32 ei_up = 0, ei_down = 0;
4264
4265 new_power = dev_priv->rps.power;
4266 switch (dev_priv->rps.power) {
4267 case LOW_POWER:
4268 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4269 new_power = BETWEEN;
4270 break;
4271
4272 case BETWEEN:
4273 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4274 new_power = LOW_POWER;
4275 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4276 new_power = HIGH_POWER;
4277 break;
4278
4279 case HIGH_POWER:
4280 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4281 new_power = BETWEEN;
4282 break;
4283 }
4284 /* Max/min bins are special */
4285 if (val <= dev_priv->rps.min_freq_softlimit)
4286 new_power = LOW_POWER;
4287 if (val >= dev_priv->rps.max_freq_softlimit)
4288 new_power = HIGH_POWER;
4289 if (new_power == dev_priv->rps.power)
4290 return;
4291
4292 /* Note the units here are not exactly 1us, but 1280ns. */
4293 switch (new_power) {
4294 case LOW_POWER:
4295 /* Upclock if more than 95% busy over 16ms */
4296 ei_up = 16000;
4297 threshold_up = 95;
4298
4299 /* Downclock if less than 85% busy over 32ms */
4300 ei_down = 32000;
4301 threshold_down = 85;
4302 break;
4303
4304 case BETWEEN:
4305 /* Upclock if more than 90% busy over 13ms */
4306 ei_up = 13000;
4307 threshold_up = 90;
4308
4309 /* Downclock if less than 75% busy over 32ms */
4310 ei_down = 32000;
4311 threshold_down = 75;
4312 break;
4313
4314 case HIGH_POWER:
4315 /* Upclock if more than 85% busy over 10ms */
4316 ei_up = 10000;
4317 threshold_up = 85;
4318
4319 /* Downclock if less than 60% busy over 32ms */
4320 ei_down = 32000;
4321 threshold_down = 60;
4322 break;
4323 }
4324
4325 I915_WRITE(GEN6_RP_UP_EI,
4326 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4327 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4328 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4329
4330 I915_WRITE(GEN6_RP_DOWN_EI,
4331 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4332 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4333 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4334
4335 I915_WRITE(GEN6_RP_CONTROL,
4336 GEN6_RP_MEDIA_TURBO |
4337 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4338 GEN6_RP_MEDIA_IS_GFX |
4339 GEN6_RP_ENABLE |
4340 GEN6_RP_UP_BUSY_AVG |
4341 GEN6_RP_DOWN_IDLE_AVG);
4342
4343 dev_priv->rps.power = new_power;
4344 dev_priv->rps.up_threshold = threshold_up;
4345 dev_priv->rps.down_threshold = threshold_down;
4346 dev_priv->rps.last_adj = 0;
4347}
4348
4349static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4350{
4351 u32 mask = 0;
4352
4353 if (val > dev_priv->rps.min_freq_softlimit)
4354 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4355 if (val < dev_priv->rps.max_freq_softlimit)
4356 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4357
4358 mask &= dev_priv->pm_rps_events;
4359
4360 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4361}
4362
4363/* gen6_set_rps is called to update the frequency request, but should also be
4364 * called when the range (min_delay and max_delay) is modified so that we can
4365 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4366static void gen6_set_rps(struct drm_device *dev, u8 val)
4367{
4368 struct drm_i915_private *dev_priv = dev->dev_private;
4369
4370 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4371 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
4372 return;
4373
4374 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4375 WARN_ON(val > dev_priv->rps.max_freq);
4376 WARN_ON(val < dev_priv->rps.min_freq);
4377
4378 /* min/max delay may still have been modified so be sure to
4379 * write the limits value.
4380 */
4381 if (val != dev_priv->rps.cur_freq) {
4382 gen6_set_rps_thresholds(dev_priv, val);
4383
4384 if (IS_GEN9(dev))
4385 I915_WRITE(GEN6_RPNSWREQ,
4386 GEN9_FREQUENCY(val));
4387 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4388 I915_WRITE(GEN6_RPNSWREQ,
4389 HSW_FREQUENCY(val));
4390 else
4391 I915_WRITE(GEN6_RPNSWREQ,
4392 GEN6_FREQUENCY(val) |
4393 GEN6_OFFSET(0) |
4394 GEN6_AGGRESSIVE_TURBO);
4395 }
4396
4397 /* Make sure we continue to get interrupts
4398 * until we hit the minimum or maximum frequencies.
4399 */
4400 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4401 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4402
4403 POSTING_READ(GEN6_RPNSWREQ);
4404
4405 dev_priv->rps.cur_freq = val;
4406 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4407}
4408
4409static void valleyview_set_rps(struct drm_device *dev, u8 val)
4410{
4411 struct drm_i915_private *dev_priv = dev->dev_private;
4412
4413 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4414 WARN_ON(val > dev_priv->rps.max_freq);
4415 WARN_ON(val < dev_priv->rps.min_freq);
4416
4417 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4418 "Odd GPU freq value\n"))
4419 val &= ~1;
4420
4421 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4422
4423 if (val != dev_priv->rps.cur_freq) {
4424 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4425 if (!IS_CHERRYVIEW(dev_priv))
4426 gen6_set_rps_thresholds(dev_priv, val);
4427 }
4428
4429 dev_priv->rps.cur_freq = val;
4430 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4431}
4432
4433/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4434 *
4435 * * If Gfx is Idle, then
4436 * 1. Forcewake Media well.
4437 * 2. Request idle freq.
4438 * 3. Release Forcewake of Media well.
4439*/
4440static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4441{
4442 u32 val = dev_priv->rps.idle_freq;
4443
4444 if (dev_priv->rps.cur_freq <= val)
4445 return;
4446
4447 /* Wake up the media well, as that takes a lot less
4448 * power than the Render well. */
4449 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4450 valleyview_set_rps(dev_priv->dev, val);
4451 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4452}
4453
4454void gen6_rps_busy(struct drm_i915_private *dev_priv)
4455{
4456 mutex_lock(&dev_priv->rps.hw_lock);
4457 if (dev_priv->rps.enabled) {
4458 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4459 gen6_rps_reset_ei(dev_priv);
4460 I915_WRITE(GEN6_PMINTRMSK,
4461 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4462 }
4463 mutex_unlock(&dev_priv->rps.hw_lock);
4464}
4465
4466void gen6_rps_idle(struct drm_i915_private *dev_priv)
4467{
4468 struct drm_device *dev = dev_priv->dev;
4469
4470 mutex_lock(&dev_priv->rps.hw_lock);
4471 if (dev_priv->rps.enabled) {
4472 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4473 vlv_set_rps_idle(dev_priv);
4474 else
4475 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4476 dev_priv->rps.last_adj = 0;
4477 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4478 }
4479 mutex_unlock(&dev_priv->rps.hw_lock);
4480
4481 spin_lock(&dev_priv->rps.client_lock);
4482 while (!list_empty(&dev_priv->rps.clients))
4483 list_del_init(dev_priv->rps.clients.next);
4484 spin_unlock(&dev_priv->rps.client_lock);
4485}
4486
4487void gen6_rps_boost(struct drm_i915_private *dev_priv,
4488 struct intel_rps_client *rps,
4489 unsigned long submitted)
4490{
4491 /* This is intentionally racy! We peek at the state here, then
4492 * validate inside the RPS worker.
4493 */
4494 if (!(dev_priv->mm.busy &&
4495 dev_priv->rps.enabled &&
4496 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4497 return;
4498
4499 /* Force a RPS boost (and don't count it against the client) if
4500 * the GPU is severely congested.
4501 */
4502 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4503 rps = NULL;
4504
4505 spin_lock(&dev_priv->rps.client_lock);
4506 if (rps == NULL || list_empty(&rps->link)) {
4507 spin_lock_irq(&dev_priv->irq_lock);
4508 if (dev_priv->rps.interrupts_enabled) {
4509 dev_priv->rps.client_boost = true;
4510 queue_work(dev_priv->wq, &dev_priv->rps.work);
4511 }
4512 spin_unlock_irq(&dev_priv->irq_lock);
4513
4514 if (rps != NULL) {
4515 list_add(&rps->link, &dev_priv->rps.clients);
4516 rps->boosts++;
4517 } else
4518 dev_priv->rps.boosts++;
4519 }
4520 spin_unlock(&dev_priv->rps.client_lock);
4521}
4522
4523void intel_set_rps(struct drm_device *dev, u8 val)
4524{
4525 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4526 valleyview_set_rps(dev, val);
4527 else
4528 gen6_set_rps(dev, val);
4529}
4530
4531static void gen9_disable_rps(struct drm_device *dev)
4532{
4533 struct drm_i915_private *dev_priv = dev->dev_private;
4534
4535 I915_WRITE(GEN6_RC_CONTROL, 0);
4536 I915_WRITE(GEN9_PG_ENABLE, 0);
4537}
4538
4539static void gen6_disable_rps(struct drm_device *dev)
4540{
4541 struct drm_i915_private *dev_priv = dev->dev_private;
4542
4543 I915_WRITE(GEN6_RC_CONTROL, 0);
4544 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4545}
4546
4547static void cherryview_disable_rps(struct drm_device *dev)
4548{
4549 struct drm_i915_private *dev_priv = dev->dev_private;
4550
4551 I915_WRITE(GEN6_RC_CONTROL, 0);
4552}
4553
4554static void valleyview_disable_rps(struct drm_device *dev)
4555{
4556 struct drm_i915_private *dev_priv = dev->dev_private;
4557
4558 /* we're doing forcewake before Disabling RC6,
4559 * This what the BIOS expects when going into suspend */
4560 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4561
4562 I915_WRITE(GEN6_RC_CONTROL, 0);
4563
4564 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4565}
4566
4567static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4568{
4569 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
4570 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4571 mode = GEN6_RC_CTL_RC6_ENABLE;
4572 else
4573 mode = 0;
4574 }
4575 if (HAS_RC6p(dev))
4576 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4577 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4578 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4579 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
4580
4581 else
4582 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4583 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
4584}
4585
4586static bool bxt_check_bios_rc6_setup(const struct drm_device *dev)
4587{
4588 struct drm_i915_private *dev_priv = dev->dev_private;
4589 bool enable_rc6 = true;
4590 unsigned long rc6_ctx_base;
4591
4592 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4593 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4594 enable_rc6 = false;
4595 }
4596
4597 /*
4598 * The exact context size is not known for BXT, so assume a page size
4599 * for this check.
4600 */
4601 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
4602 if (!((rc6_ctx_base >= dev_priv->gtt.stolen_reserved_base) &&
4603 (rc6_ctx_base + PAGE_SIZE <= dev_priv->gtt.stolen_reserved_base +
4604 dev_priv->gtt.stolen_reserved_size))) {
4605 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4606 enable_rc6 = false;
4607 }
4608
4609 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4610 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4611 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4612 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4613 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4614 enable_rc6 = false;
4615 }
4616
4617 if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4618 GEN6_RC_CTL_HW_ENABLE)) &&
4619 ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4620 !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4621 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4622 enable_rc6 = false;
4623 }
4624
4625 return enable_rc6;
4626}
4627
4628int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4629{
4630 /* No RC6 before Ironlake and code is gone for ilk. */
4631 if (INTEL_INFO(dev)->gen < 6)
4632 return 0;
4633
4634 if (!enable_rc6)
4635 return 0;
4636
4637 if (IS_BROXTON(dev) && !bxt_check_bios_rc6_setup(dev)) {
4638 DRM_INFO("RC6 disabled by BIOS\n");
4639 return 0;
4640 }
4641
4642 /* Respect the kernel parameter if it is set */
4643 if (enable_rc6 >= 0) {
4644 int mask;
4645
4646 if (HAS_RC6p(dev))
4647 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4648 INTEL_RC6pp_ENABLE;
4649 else
4650 mask = INTEL_RC6_ENABLE;
4651
4652 if ((enable_rc6 & mask) != enable_rc6)
4653 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4654 enable_rc6 & mask, enable_rc6, mask);
4655
4656 return enable_rc6 & mask;
4657 }
4658
4659 if (IS_IVYBRIDGE(dev))
4660 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4661
4662 return INTEL_RC6_ENABLE;
4663}
4664
4665int intel_enable_rc6(const struct drm_device *dev)
4666{
4667 return i915.enable_rc6;
4668}
4669
4670static void gen6_init_rps_frequencies(struct drm_device *dev)
4671{
4672 struct drm_i915_private *dev_priv = dev->dev_private;
4673 uint32_t rp_state_cap;
4674 u32 ddcc_status = 0;
4675 int ret;
4676
4677 /* All of these values are in units of 50MHz */
4678 dev_priv->rps.cur_freq = 0;
4679 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4680 if (IS_BROXTON(dev)) {
4681 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4682 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4683 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4684 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4685 } else {
4686 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4687 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4688 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4689 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4690 }
4691
4692 /* hw_max = RP0 until we check for overclocking */
4693 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4694
4695 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4696 if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4697 IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4698 ret = sandybridge_pcode_read(dev_priv,
4699 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4700 &ddcc_status);
4701 if (0 == ret)
4702 dev_priv->rps.efficient_freq =
4703 clamp_t(u8,
4704 ((ddcc_status >> 8) & 0xff),
4705 dev_priv->rps.min_freq,
4706 dev_priv->rps.max_freq);
4707 }
4708
4709 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4710 /* Store the frequency values in 16.66 MHZ units, which is
4711 the natural hardware unit for SKL */
4712 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4713 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4714 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4715 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4716 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4717 }
4718
4719 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4720
4721 /* Preserve min/max settings in case of re-init */
4722 if (dev_priv->rps.max_freq_softlimit == 0)
4723 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4724
4725 if (dev_priv->rps.min_freq_softlimit == 0) {
4726 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4727 dev_priv->rps.min_freq_softlimit =
4728 max_t(int, dev_priv->rps.efficient_freq,
4729 intel_freq_opcode(dev_priv, 450));
4730 else
4731 dev_priv->rps.min_freq_softlimit =
4732 dev_priv->rps.min_freq;
4733 }
4734}
4735
4736/* See the Gen9_GT_PM_Programming_Guide doc for the below */
4737static void gen9_enable_rps(struct drm_device *dev)
4738{
4739 struct drm_i915_private *dev_priv = dev->dev_private;
4740
4741 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4742
4743 gen6_init_rps_frequencies(dev);
4744
4745 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4746 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4747 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4748 return;
4749 }
4750
4751 /* Program defaults and thresholds for RPS*/
4752 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4753 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4754
4755 /* 1 second timeout*/
4756 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4757 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4758
4759 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4760
4761 /* Leaning on the below call to gen6_set_rps to program/setup the
4762 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4763 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4764 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4765 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4766
4767 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4768}
4769
4770static void gen9_enable_rc6(struct drm_device *dev)
4771{
4772 struct drm_i915_private *dev_priv = dev->dev_private;
4773 struct intel_engine_cs *ring;
4774 uint32_t rc6_mask = 0;
4775 int unused;
4776
4777 /* 1a: Software RC state - RC0 */
4778 I915_WRITE(GEN6_RC_STATE, 0);
4779
4780 /* 1b: Get forcewake during program sequence. Although the driver
4781 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4782 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4783
4784 /* 2a: Disable RC states. */
4785 I915_WRITE(GEN6_RC_CONTROL, 0);
4786
4787 /* 2b: Program RC6 thresholds.*/
4788
4789 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4790 if (IS_SKYLAKE(dev))
4791 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4792 else
4793 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4794 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4795 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4796 for_each_ring(ring, dev_priv, unused)
4797 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4798
4799 if (HAS_GUC_UCODE(dev))
4800 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4801
4802 I915_WRITE(GEN6_RC_SLEEP, 0);
4803
4804 /* 2c: Program Coarse Power Gating Policies. */
4805 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4806 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4807
4808 /* 3a: Enable RC6 */
4809 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4810 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4811 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4812 /* WaRsUseTimeoutMode */
4813 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
4814 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4815 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4816 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4817 GEN7_RC_CTL_TO_MODE |
4818 rc6_mask);
4819 } else {
4820 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4821 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4822 GEN6_RC_CTL_EI_MODE(1) |
4823 rc6_mask);
4824 }
4825
4826 /*
4827 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4828 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4829 */
4830 if (NEEDS_WaRsDisableCoarsePowerGating(dev))
4831 I915_WRITE(GEN9_PG_ENABLE, 0);
4832 else
4833 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4834 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4835
4836 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4837
4838}
4839
4840static void gen8_enable_rps(struct drm_device *dev)
4841{
4842 struct drm_i915_private *dev_priv = dev->dev_private;
4843 struct intel_engine_cs *ring;
4844 uint32_t rc6_mask = 0;
4845 int unused;
4846
4847 /* 1a: Software RC state - RC0 */
4848 I915_WRITE(GEN6_RC_STATE, 0);
4849
4850 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4851 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4852 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4853
4854 /* 2a: Disable RC states. */
4855 I915_WRITE(GEN6_RC_CONTROL, 0);
4856
4857 /* Initialize rps frequencies */
4858 gen6_init_rps_frequencies(dev);
4859
4860 /* 2b: Program RC6 thresholds.*/
4861 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4862 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4863 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4864 for_each_ring(ring, dev_priv, unused)
4865 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4866 I915_WRITE(GEN6_RC_SLEEP, 0);
4867 if (IS_BROADWELL(dev))
4868 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4869 else
4870 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4871
4872 /* 3: Enable RC6 */
4873 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4874 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4875 intel_print_rc6_info(dev, rc6_mask);
4876 if (IS_BROADWELL(dev))
4877 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4878 GEN7_RC_CTL_TO_MODE |
4879 rc6_mask);
4880 else
4881 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4882 GEN6_RC_CTL_EI_MODE(1) |
4883 rc6_mask);
4884
4885 /* 4 Program defaults and thresholds for RPS*/
4886 I915_WRITE(GEN6_RPNSWREQ,
4887 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4888 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4889 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4890 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4891 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4892
4893 /* Docs recommend 900MHz, and 300 MHz respectively */
4894 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4895 dev_priv->rps.max_freq_softlimit << 24 |
4896 dev_priv->rps.min_freq_softlimit << 16);
4897
4898 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4899 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4900 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4901 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4902
4903 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4904
4905 /* 5: Enable RPS */
4906 I915_WRITE(GEN6_RP_CONTROL,
4907 GEN6_RP_MEDIA_TURBO |
4908 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4909 GEN6_RP_MEDIA_IS_GFX |
4910 GEN6_RP_ENABLE |
4911 GEN6_RP_UP_BUSY_AVG |
4912 GEN6_RP_DOWN_IDLE_AVG);
4913
4914 /* 6: Ring frequency + overclocking (our driver does this later */
4915
4916 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4917 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4918
4919 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4920}
4921
4922static void gen6_enable_rps(struct drm_device *dev)
4923{
4924 struct drm_i915_private *dev_priv = dev->dev_private;
4925 struct intel_engine_cs *ring;
4926 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4927 u32 gtfifodbg;
4928 int rc6_mode;
4929 int i, ret;
4930
4931 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4932
4933 /* Here begins a magic sequence of register writes to enable
4934 * auto-downclocking.
4935 *
4936 * Perhaps there might be some value in exposing these to
4937 * userspace...
4938 */
4939 I915_WRITE(GEN6_RC_STATE, 0);
4940
4941 /* Clear the DBG now so we don't confuse earlier errors */
4942 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4943 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4944 I915_WRITE(GTFIFODBG, gtfifodbg);
4945 }
4946
4947 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4948
4949 /* Initialize rps frequencies */
4950 gen6_init_rps_frequencies(dev);
4951
4952 /* disable the counters and set deterministic thresholds */
4953 I915_WRITE(GEN6_RC_CONTROL, 0);
4954
4955 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4956 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4957 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4958 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4959 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4960
4961 for_each_ring(ring, dev_priv, i)
4962 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4963
4964 I915_WRITE(GEN6_RC_SLEEP, 0);
4965 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4966 if (IS_IVYBRIDGE(dev))
4967 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4968 else
4969 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4970 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4971 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4972
4973 /* Check if we are enabling RC6 */
4974 rc6_mode = intel_enable_rc6(dev_priv->dev);
4975 if (rc6_mode & INTEL_RC6_ENABLE)
4976 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4977
4978 /* We don't use those on Haswell */
4979 if (!IS_HASWELL(dev)) {
4980 if (rc6_mode & INTEL_RC6p_ENABLE)
4981 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4982
4983 if (rc6_mode & INTEL_RC6pp_ENABLE)
4984 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4985 }
4986
4987 intel_print_rc6_info(dev, rc6_mask);
4988
4989 I915_WRITE(GEN6_RC_CONTROL,
4990 rc6_mask |
4991 GEN6_RC_CTL_EI_MODE(1) |
4992 GEN6_RC_CTL_HW_ENABLE);
4993
4994 /* Power down if completely idle for over 50ms */
4995 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4996 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4997
4998 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4999 if (ret)
5000 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5001
5002 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5003 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5004 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5005 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5006 (pcu_mbox & 0xff) * 50);
5007 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5008 }
5009
5010 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5011 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5012
5013 rc6vids = 0;
5014 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5015 if (IS_GEN6(dev) && ret) {
5016 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5017 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5018 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5019 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5020 rc6vids &= 0xffff00;
5021 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5022 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5023 if (ret)
5024 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5025 }
5026
5027 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5028}
5029
5030static void __gen6_update_ring_freq(struct drm_device *dev)
5031{
5032 struct drm_i915_private *dev_priv = dev->dev_private;
5033 int min_freq = 15;
5034 unsigned int gpu_freq;
5035 unsigned int max_ia_freq, min_ring_freq;
5036 unsigned int max_gpu_freq, min_gpu_freq;
5037 int scaling_factor = 180;
5038 struct cpufreq_policy *policy;
5039
5040 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5041
5042 policy = cpufreq_cpu_get(0);
5043 if (policy) {
5044 max_ia_freq = policy->cpuinfo.max_freq;
5045 cpufreq_cpu_put(policy);
5046 } else {
5047 /*
5048 * Default to measured freq if none found, PCU will ensure we
5049 * don't go over
5050 */
5051 max_ia_freq = tsc_khz;
5052 }
5053
5054 /* Convert from kHz to MHz */
5055 max_ia_freq /= 1000;
5056
5057 min_ring_freq = I915_READ(DCLK) & 0xf;
5058 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5059 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5060
5061 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5062 /* Convert GT frequency to 50 HZ units */
5063 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5064 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5065 } else {
5066 min_gpu_freq = dev_priv->rps.min_freq;
5067 max_gpu_freq = dev_priv->rps.max_freq;
5068 }
5069
5070 /*
5071 * For each potential GPU frequency, load a ring frequency we'd like
5072 * to use for memory access. We do this by specifying the IA frequency
5073 * the PCU should use as a reference to determine the ring frequency.
5074 */
5075 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5076 int diff = max_gpu_freq - gpu_freq;
5077 unsigned int ia_freq = 0, ring_freq = 0;
5078
5079 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5080 /*
5081 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5082 * No floor required for ring frequency on SKL.
5083 */
5084 ring_freq = gpu_freq;
5085 } else if (INTEL_INFO(dev)->gen >= 8) {
5086 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5087 ring_freq = max(min_ring_freq, gpu_freq);
5088 } else if (IS_HASWELL(dev)) {
5089 ring_freq = mult_frac(gpu_freq, 5, 4);
5090 ring_freq = max(min_ring_freq, ring_freq);
5091 /* leave ia_freq as the default, chosen by cpufreq */
5092 } else {
5093 /* On older processors, there is no separate ring
5094 * clock domain, so in order to boost the bandwidth
5095 * of the ring, we need to upclock the CPU (ia_freq).
5096 *
5097 * For GPU frequencies less than 750MHz,
5098 * just use the lowest ring freq.
5099 */
5100 if (gpu_freq < min_freq)
5101 ia_freq = 800;
5102 else
5103 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5104 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5105 }
5106
5107 sandybridge_pcode_write(dev_priv,
5108 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5109 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5110 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5111 gpu_freq);
5112 }
5113}
5114
5115void gen6_update_ring_freq(struct drm_device *dev)
5116{
5117 struct drm_i915_private *dev_priv = dev->dev_private;
5118
5119 if (!HAS_CORE_RING_FREQ(dev))
5120 return;
5121
5122 mutex_lock(&dev_priv->rps.hw_lock);
5123 __gen6_update_ring_freq(dev);
5124 mutex_unlock(&dev_priv->rps.hw_lock);
5125}
5126
5127static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5128{
5129 struct drm_device *dev = dev_priv->dev;
5130 u32 val, rp0;
5131
5132 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5133
5134 switch (INTEL_INFO(dev)->eu_total) {
5135 case 8:
5136 /* (2 * 4) config */
5137 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5138 break;
5139 case 12:
5140 /* (2 * 6) config */
5141 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5142 break;
5143 case 16:
5144 /* (2 * 8) config */
5145 default:
5146 /* Setting (2 * 8) Min RP0 for any other combination */
5147 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5148 break;
5149 }
5150
5151 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5152
5153 return rp0;
5154}
5155
5156static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5157{
5158 u32 val, rpe;
5159
5160 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5161 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5162
5163 return rpe;
5164}
5165
5166static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5167{
5168 u32 val, rp1;
5169
5170 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5171 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5172
5173 return rp1;
5174}
5175
5176static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5177{
5178 u32 val, rp1;
5179
5180 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5181
5182 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5183
5184 return rp1;
5185}
5186
5187static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5188{
5189 u32 val, rp0;
5190
5191 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5192
5193 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5194 /* Clamp to max */
5195 rp0 = min_t(u32, rp0, 0xea);
5196
5197 return rp0;
5198}
5199
5200static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5201{
5202 u32 val, rpe;
5203
5204 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5205 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5206 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5207 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5208
5209 return rpe;
5210}
5211
5212static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5213{
5214 u32 val;
5215
5216 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5217 /*
5218 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5219 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5220 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5221 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5222 * to make sure it matches what Punit accepts.
5223 */
5224 return max_t(u32, val, 0xc0);
5225}
5226
5227/* Check that the pctx buffer wasn't move under us. */
5228static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5229{
5230 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5231
5232 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5233 dev_priv->vlv_pctx->stolen->start);
5234}
5235
5236
5237/* Check that the pcbr address is not empty. */
5238static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5239{
5240 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5241
5242 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5243}
5244
5245static void cherryview_setup_pctx(struct drm_device *dev)
5246{
5247 struct drm_i915_private *dev_priv = dev->dev_private;
5248 unsigned long pctx_paddr, paddr;
5249 struct i915_gtt *gtt = &dev_priv->gtt;
5250 u32 pcbr;
5251 int pctx_size = 32*1024;
5252
5253 pcbr = I915_READ(VLV_PCBR);
5254 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5255 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5256 paddr = (dev_priv->mm.stolen_base +
5257 (gtt->stolen_size - pctx_size));
5258
5259 pctx_paddr = (paddr & (~4095));
5260 I915_WRITE(VLV_PCBR, pctx_paddr);
5261 }
5262
5263 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5264}
5265
5266static void valleyview_setup_pctx(struct drm_device *dev)
5267{
5268 struct drm_i915_private *dev_priv = dev->dev_private;
5269 struct drm_i915_gem_object *pctx;
5270 unsigned long pctx_paddr;
5271 u32 pcbr;
5272 int pctx_size = 24*1024;
5273
5274 mutex_lock(&dev->struct_mutex);
5275
5276 pcbr = I915_READ(VLV_PCBR);
5277 if (pcbr) {
5278 /* BIOS set it up already, grab the pre-alloc'd space */
5279 int pcbr_offset;
5280
5281 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5282 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5283 pcbr_offset,
5284 I915_GTT_OFFSET_NONE,
5285 pctx_size);
5286 goto out;
5287 }
5288
5289 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5290
5291 /*
5292 * From the Gunit register HAS:
5293 * The Gfx driver is expected to program this register and ensure
5294 * proper allocation within Gfx stolen memory. For example, this
5295 * register should be programmed such than the PCBR range does not
5296 * overlap with other ranges, such as the frame buffer, protected
5297 * memory, or any other relevant ranges.
5298 */
5299 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5300 if (!pctx) {
5301 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5302 goto out;
5303 }
5304
5305 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5306 I915_WRITE(VLV_PCBR, pctx_paddr);
5307
5308out:
5309 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5310 dev_priv->vlv_pctx = pctx;
5311 mutex_unlock(&dev->struct_mutex);
5312}
5313
5314static void valleyview_cleanup_pctx(struct drm_device *dev)
5315{
5316 struct drm_i915_private *dev_priv = dev->dev_private;
5317
5318 if (WARN_ON(!dev_priv->vlv_pctx))
5319 return;
5320
5321 drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
5322 dev_priv->vlv_pctx = NULL;
5323}
5324
5325static void valleyview_init_gt_powersave(struct drm_device *dev)
5326{
5327 struct drm_i915_private *dev_priv = dev->dev_private;
5328 u32 val;
5329
5330 valleyview_setup_pctx(dev);
5331
5332 mutex_lock(&dev_priv->rps.hw_lock);
5333
5334 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5335 switch ((val >> 6) & 3) {
5336 case 0:
5337 case 1:
5338 dev_priv->mem_freq = 800;
5339 break;
5340 case 2:
5341 dev_priv->mem_freq = 1066;
5342 break;
5343 case 3:
5344 dev_priv->mem_freq = 1333;
5345 break;
5346 }
5347 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5348
5349 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5350 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5351 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5352 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5353 dev_priv->rps.max_freq);
5354
5355 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5356 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5357 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5358 dev_priv->rps.efficient_freq);
5359
5360 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5361 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5362 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5363 dev_priv->rps.rp1_freq);
5364
5365 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5366 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5367 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5368 dev_priv->rps.min_freq);
5369
5370 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5371
5372 /* Preserve min/max settings in case of re-init */
5373 if (dev_priv->rps.max_freq_softlimit == 0)
5374 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5375
5376 if (dev_priv->rps.min_freq_softlimit == 0)
5377 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5378
5379 mutex_unlock(&dev_priv->rps.hw_lock);
5380}
5381
5382static void cherryview_init_gt_powersave(struct drm_device *dev)
5383{
5384 struct drm_i915_private *dev_priv = dev->dev_private;
5385 u32 val;
5386
5387 cherryview_setup_pctx(dev);
5388
5389 mutex_lock(&dev_priv->rps.hw_lock);
5390
5391 mutex_lock(&dev_priv->sb_lock);
5392 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5393 mutex_unlock(&dev_priv->sb_lock);
5394
5395 switch ((val >> 2) & 0x7) {
5396 case 3:
5397 dev_priv->mem_freq = 2000;
5398 break;
5399 default:
5400 dev_priv->mem_freq = 1600;
5401 break;
5402 }
5403 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5404
5405 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5406 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5407 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5408 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5409 dev_priv->rps.max_freq);
5410
5411 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5412 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5413 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5414 dev_priv->rps.efficient_freq);
5415
5416 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5417 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5418 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5419 dev_priv->rps.rp1_freq);
5420
5421 /* PUnit validated range is only [RPe, RP0] */
5422 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5423 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5424 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5425 dev_priv->rps.min_freq);
5426
5427 WARN_ONCE((dev_priv->rps.max_freq |
5428 dev_priv->rps.efficient_freq |
5429 dev_priv->rps.rp1_freq |
5430 dev_priv->rps.min_freq) & 1,
5431 "Odd GPU freq values\n");
5432
5433 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5434
5435 /* Preserve min/max settings in case of re-init */
5436 if (dev_priv->rps.max_freq_softlimit == 0)
5437 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5438
5439 if (dev_priv->rps.min_freq_softlimit == 0)
5440 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5441
5442 mutex_unlock(&dev_priv->rps.hw_lock);
5443}
5444
5445static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5446{
5447 valleyview_cleanup_pctx(dev);
5448}
5449
5450static void cherryview_enable_rps(struct drm_device *dev)
5451{
5452 struct drm_i915_private *dev_priv = dev->dev_private;
5453 struct intel_engine_cs *ring;
5454 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5455 int i;
5456
5457 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5458
5459 gtfifodbg = I915_READ(GTFIFODBG);
5460 if (gtfifodbg) {
5461 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5462 gtfifodbg);
5463 I915_WRITE(GTFIFODBG, gtfifodbg);
5464 }
5465
5466 cherryview_check_pctx(dev_priv);
5467
5468 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5469 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5470 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5471
5472 /* Disable RC states. */
5473 I915_WRITE(GEN6_RC_CONTROL, 0);
5474
5475 /* 2a: Program RC6 thresholds.*/
5476 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5477 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5478 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5479
5480 for_each_ring(ring, dev_priv, i)
5481 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5482 I915_WRITE(GEN6_RC_SLEEP, 0);
5483
5484 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5485 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5486
5487 /* allows RC6 residency counter to work */
5488 I915_WRITE(VLV_COUNTER_CONTROL,
5489 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5490 VLV_MEDIA_RC6_COUNT_EN |
5491 VLV_RENDER_RC6_COUNT_EN));
5492
5493 /* For now we assume BIOS is allocating and populating the PCBR */
5494 pcbr = I915_READ(VLV_PCBR);
5495
5496 /* 3: Enable RC6 */
5497 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5498 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5499 rc6_mode = GEN7_RC_CTL_TO_MODE;
5500
5501 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5502
5503 /* 4 Program defaults and thresholds for RPS*/
5504 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5505 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5506 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5507 I915_WRITE(GEN6_RP_UP_EI, 66000);
5508 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5509
5510 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5511
5512 /* 5: Enable RPS */
5513 I915_WRITE(GEN6_RP_CONTROL,
5514 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5515 GEN6_RP_MEDIA_IS_GFX |
5516 GEN6_RP_ENABLE |
5517 GEN6_RP_UP_BUSY_AVG |
5518 GEN6_RP_DOWN_IDLE_AVG);
5519
5520 /* Setting Fixed Bias */
5521 val = VLV_OVERRIDE_EN |
5522 VLV_SOC_TDP_EN |
5523 CHV_BIAS_CPU_50_SOC_50;
5524 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5525
5526 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5527
5528 /* RPS code assumes GPLL is used */
5529 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5530
5531 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5532 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5533
5534 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5535 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5536 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5537 dev_priv->rps.cur_freq);
5538
5539 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5540 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5541 dev_priv->rps.efficient_freq);
5542
5543 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5544
5545 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5546}
5547
5548static void valleyview_enable_rps(struct drm_device *dev)
5549{
5550 struct drm_i915_private *dev_priv = dev->dev_private;
5551 struct intel_engine_cs *ring;
5552 u32 gtfifodbg, val, rc6_mode = 0;
5553 int i;
5554
5555 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5556
5557 valleyview_check_pctx(dev_priv);
5558
5559 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5560 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5561 gtfifodbg);
5562 I915_WRITE(GTFIFODBG, gtfifodbg);
5563 }
5564
5565 /* If VLV, Forcewake all wells, else re-direct to regular path */
5566 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5567
5568 /* Disable RC states. */
5569 I915_WRITE(GEN6_RC_CONTROL, 0);
5570
5571 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5572 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5573 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5574 I915_WRITE(GEN6_RP_UP_EI, 66000);
5575 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5576
5577 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5578
5579 I915_WRITE(GEN6_RP_CONTROL,
5580 GEN6_RP_MEDIA_TURBO |
5581 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5582 GEN6_RP_MEDIA_IS_GFX |
5583 GEN6_RP_ENABLE |
5584 GEN6_RP_UP_BUSY_AVG |
5585 GEN6_RP_DOWN_IDLE_CONT);
5586
5587 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5588 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5589 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5590
5591 for_each_ring(ring, dev_priv, i)
5592 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5593
5594 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5595
5596 /* allows RC6 residency counter to work */
5597 I915_WRITE(VLV_COUNTER_CONTROL,
5598 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5599 VLV_RENDER_RC0_COUNT_EN |
5600 VLV_MEDIA_RC6_COUNT_EN |
5601 VLV_RENDER_RC6_COUNT_EN));
5602
5603 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5604 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5605
5606 intel_print_rc6_info(dev, rc6_mode);
5607
5608 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5609
5610 /* Setting Fixed Bias */
5611 val = VLV_OVERRIDE_EN |
5612 VLV_SOC_TDP_EN |
5613 VLV_BIAS_CPU_125_SOC_875;
5614 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5615
5616 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5617
5618 /* RPS code assumes GPLL is used */
5619 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5620
5621 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5622 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5623
5624 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5625 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5626 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5627 dev_priv->rps.cur_freq);
5628
5629 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5630 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5631 dev_priv->rps.efficient_freq);
5632
5633 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5634
5635 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5636}
5637
5638static unsigned long intel_pxfreq(u32 vidfreq)
5639{
5640 unsigned long freq;
5641 int div = (vidfreq & 0x3f0000) >> 16;
5642 int post = (vidfreq & 0x3000) >> 12;
5643 int pre = (vidfreq & 0x7);
5644
5645 if (!pre)
5646 return 0;
5647
5648 freq = ((div * 133333) / ((1<<post) * pre));
5649
5650 return freq;
5651}
5652
5653static const struct cparams {
5654 u16 i;
5655 u16 t;
5656 u16 m;
5657 u16 c;
5658} cparams[] = {
5659 { 1, 1333, 301, 28664 },
5660 { 1, 1066, 294, 24460 },
5661 { 1, 800, 294, 25192 },
5662 { 0, 1333, 276, 27605 },
5663 { 0, 1066, 276, 27605 },
5664 { 0, 800, 231, 23784 },
5665};
5666
5667static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5668{
5669 u64 total_count, diff, ret;
5670 u32 count1, count2, count3, m = 0, c = 0;
5671 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5672 int i;
5673
5674 assert_spin_locked(&mchdev_lock);
5675
5676 diff1 = now - dev_priv->ips.last_time1;
5677
5678 /* Prevent division-by-zero if we are asking too fast.
5679 * Also, we don't get interesting results if we are polling
5680 * faster than once in 10ms, so just return the saved value
5681 * in such cases.
5682 */
5683 if (diff1 <= 10)
5684 return dev_priv->ips.chipset_power;
5685
5686 count1 = I915_READ(DMIEC);
5687 count2 = I915_READ(DDREC);
5688 count3 = I915_READ(CSIEC);
5689
5690 total_count = count1 + count2 + count3;
5691
5692 /* FIXME: handle per-counter overflow */
5693 if (total_count < dev_priv->ips.last_count1) {
5694 diff = ~0UL - dev_priv->ips.last_count1;
5695 diff += total_count;
5696 } else {
5697 diff = total_count - dev_priv->ips.last_count1;
5698 }
5699
5700 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5701 if (cparams[i].i == dev_priv->ips.c_m &&
5702 cparams[i].t == dev_priv->ips.r_t) {
5703 m = cparams[i].m;
5704 c = cparams[i].c;
5705 break;
5706 }
5707 }
5708
5709 diff = div_u64(diff, diff1);
5710 ret = ((m * diff) + c);
5711 ret = div_u64(ret, 10);
5712
5713 dev_priv->ips.last_count1 = total_count;
5714 dev_priv->ips.last_time1 = now;
5715
5716 dev_priv->ips.chipset_power = ret;
5717
5718 return ret;
5719}
5720
5721unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5722{
5723 struct drm_device *dev = dev_priv->dev;
5724 unsigned long val;
5725
5726 if (INTEL_INFO(dev)->gen != 5)
5727 return 0;
5728
5729 spin_lock_irq(&mchdev_lock);
5730
5731 val = __i915_chipset_val(dev_priv);
5732
5733 spin_unlock_irq(&mchdev_lock);
5734
5735 return val;
5736}
5737
5738unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5739{
5740 unsigned long m, x, b;
5741 u32 tsfs;
5742
5743 tsfs = I915_READ(TSFS);
5744
5745 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5746 x = I915_READ8(TR1);
5747
5748 b = tsfs & TSFS_INTR_MASK;
5749
5750 return ((m * x) / 127) - b;
5751}
5752
5753static int _pxvid_to_vd(u8 pxvid)
5754{
5755 if (pxvid == 0)
5756 return 0;
5757
5758 if (pxvid >= 8 && pxvid < 31)
5759 pxvid = 31;
5760
5761 return (pxvid + 2) * 125;
5762}
5763
5764static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5765{
5766 struct drm_device *dev = dev_priv->dev;
5767 const int vd = _pxvid_to_vd(pxvid);
5768 const int vm = vd - 1125;
5769
5770 if (INTEL_INFO(dev)->is_mobile)
5771 return vm > 0 ? vm : 0;
5772
5773 return vd;
5774}
5775
5776static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5777{
5778 u64 now, diff, diffms;
5779 u32 count;
5780
5781 assert_spin_locked(&mchdev_lock);
5782
5783 now = ktime_get_raw_ns();
5784 diffms = now - dev_priv->ips.last_time2;
5785 do_div(diffms, NSEC_PER_MSEC);
5786
5787 /* Don't divide by 0 */
5788 if (!diffms)
5789 return;
5790
5791 count = I915_READ(GFXEC);
5792
5793 if (count < dev_priv->ips.last_count2) {
5794 diff = ~0UL - dev_priv->ips.last_count2;
5795 diff += count;
5796 } else {
5797 diff = count - dev_priv->ips.last_count2;
5798 }
5799
5800 dev_priv->ips.last_count2 = count;
5801 dev_priv->ips.last_time2 = now;
5802
5803 /* More magic constants... */
5804 diff = diff * 1181;
5805 diff = div_u64(diff, diffms * 10);
5806 dev_priv->ips.gfx_power = diff;
5807}
5808
5809void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5810{
5811 struct drm_device *dev = dev_priv->dev;
5812
5813 if (INTEL_INFO(dev)->gen != 5)
5814 return;
5815
5816 spin_lock_irq(&mchdev_lock);
5817
5818 __i915_update_gfx_val(dev_priv);
5819
5820 spin_unlock_irq(&mchdev_lock);
5821}
5822
5823static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5824{
5825 unsigned long t, corr, state1, corr2, state2;
5826 u32 pxvid, ext_v;
5827
5828 assert_spin_locked(&mchdev_lock);
5829
5830 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5831 pxvid = (pxvid >> 24) & 0x7f;
5832 ext_v = pvid_to_extvid(dev_priv, pxvid);
5833
5834 state1 = ext_v;
5835
5836 t = i915_mch_val(dev_priv);
5837
5838 /* Revel in the empirically derived constants */
5839
5840 /* Correction factor in 1/100000 units */
5841 if (t > 80)
5842 corr = ((t * 2349) + 135940);
5843 else if (t >= 50)
5844 corr = ((t * 964) + 29317);
5845 else /* < 50 */
5846 corr = ((t * 301) + 1004);
5847
5848 corr = corr * ((150142 * state1) / 10000 - 78642);
5849 corr /= 100000;
5850 corr2 = (corr * dev_priv->ips.corr);
5851
5852 state2 = (corr2 * state1) / 10000;
5853 state2 /= 100; /* convert to mW */
5854
5855 __i915_update_gfx_val(dev_priv);
5856
5857 return dev_priv->ips.gfx_power + state2;
5858}
5859
5860unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5861{
5862 struct drm_device *dev = dev_priv->dev;
5863 unsigned long val;
5864
5865 if (INTEL_INFO(dev)->gen != 5)
5866 return 0;
5867
5868 spin_lock_irq(&mchdev_lock);
5869
5870 val = __i915_gfx_val(dev_priv);
5871
5872 spin_unlock_irq(&mchdev_lock);
5873
5874 return val;
5875}
5876
5877/**
5878 * i915_read_mch_val - return value for IPS use
5879 *
5880 * Calculate and return a value for the IPS driver to use when deciding whether
5881 * we have thermal and power headroom to increase CPU or GPU power budget.
5882 */
5883unsigned long i915_read_mch_val(void)
5884{
5885 struct drm_i915_private *dev_priv;
5886 unsigned long chipset_val, graphics_val, ret = 0;
5887
5888 spin_lock_irq(&mchdev_lock);
5889 if (!i915_mch_dev)
5890 goto out_unlock;
5891 dev_priv = i915_mch_dev;
5892
5893 chipset_val = __i915_chipset_val(dev_priv);
5894 graphics_val = __i915_gfx_val(dev_priv);
5895
5896 ret = chipset_val + graphics_val;
5897
5898out_unlock:
5899 spin_unlock_irq(&mchdev_lock);
5900
5901 return ret;
5902}
5903EXPORT_SYMBOL_GPL(i915_read_mch_val);
5904
5905/**
5906 * i915_gpu_raise - raise GPU frequency limit
5907 *
5908 * Raise the limit; IPS indicates we have thermal headroom.
5909 */
5910bool i915_gpu_raise(void)
5911{
5912 struct drm_i915_private *dev_priv;
5913 bool ret = true;
5914
5915 spin_lock_irq(&mchdev_lock);
5916 if (!i915_mch_dev) {
5917 ret = false;
5918 goto out_unlock;
5919 }
5920 dev_priv = i915_mch_dev;
5921
5922 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5923 dev_priv->ips.max_delay--;
5924
5925out_unlock:
5926 spin_unlock_irq(&mchdev_lock);
5927
5928 return ret;
5929}
5930EXPORT_SYMBOL_GPL(i915_gpu_raise);
5931
5932/**
5933 * i915_gpu_lower - lower GPU frequency limit
5934 *
5935 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5936 * frequency maximum.
5937 */
5938bool i915_gpu_lower(void)
5939{
5940 struct drm_i915_private *dev_priv;
5941 bool ret = true;
5942
5943 spin_lock_irq(&mchdev_lock);
5944 if (!i915_mch_dev) {
5945 ret = false;
5946 goto out_unlock;
5947 }
5948 dev_priv = i915_mch_dev;
5949
5950 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5951 dev_priv->ips.max_delay++;
5952
5953out_unlock:
5954 spin_unlock_irq(&mchdev_lock);
5955
5956 return ret;
5957}
5958EXPORT_SYMBOL_GPL(i915_gpu_lower);
5959
5960/**
5961 * i915_gpu_busy - indicate GPU business to IPS
5962 *
5963 * Tell the IPS driver whether or not the GPU is busy.
5964 */
5965bool i915_gpu_busy(void)
5966{
5967 struct drm_i915_private *dev_priv;
5968 struct intel_engine_cs *ring;
5969 bool ret = false;
5970 int i;
5971
5972 spin_lock_irq(&mchdev_lock);
5973 if (!i915_mch_dev)
5974 goto out_unlock;
5975 dev_priv = i915_mch_dev;
5976
5977 for_each_ring(ring, dev_priv, i)
5978 ret |= !list_empty(&ring->request_list);
5979
5980out_unlock:
5981 spin_unlock_irq(&mchdev_lock);
5982
5983 return ret;
5984}
5985EXPORT_SYMBOL_GPL(i915_gpu_busy);
5986
5987/**
5988 * i915_gpu_turbo_disable - disable graphics turbo
5989 *
5990 * Disable graphics turbo by resetting the max frequency and setting the
5991 * current frequency to the default.
5992 */
5993bool i915_gpu_turbo_disable(void)
5994{
5995 struct drm_i915_private *dev_priv;
5996 bool ret = true;
5997
5998 spin_lock_irq(&mchdev_lock);
5999 if (!i915_mch_dev) {
6000 ret = false;
6001 goto out_unlock;
6002 }
6003 dev_priv = i915_mch_dev;
6004
6005 dev_priv->ips.max_delay = dev_priv->ips.fstart;
6006
6007 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
6008 ret = false;
6009
6010out_unlock:
6011 spin_unlock_irq(&mchdev_lock);
6012
6013 return ret;
6014}
6015EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6016
6017/**
6018 * Tells the intel_ips driver that the i915 driver is now loaded, if
6019 * IPS got loaded first.
6020 *
6021 * This awkward dance is so that neither module has to depend on the
6022 * other in order for IPS to do the appropriate communication of
6023 * GPU turbo limits to i915.
6024 */
6025static void
6026ips_ping_for_i915_load(void)
6027{
6028 void (*link)(void);
6029
6030 link = symbol_get(ips_link_to_i915_driver);
6031 if (link) {
6032 link();
6033 symbol_put(ips_link_to_i915_driver);
6034 }
6035}
6036
6037void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6038{
6039 /* We only register the i915 ips part with intel-ips once everything is
6040 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6041 spin_lock_irq(&mchdev_lock);
6042 i915_mch_dev = dev_priv;
6043 spin_unlock_irq(&mchdev_lock);
6044
6045 ips_ping_for_i915_load();
6046}
6047
6048void intel_gpu_ips_teardown(void)
6049{
6050 spin_lock_irq(&mchdev_lock);
6051 i915_mch_dev = NULL;
6052 spin_unlock_irq(&mchdev_lock);
6053}
6054
6055static void intel_init_emon(struct drm_device *dev)
6056{
6057 struct drm_i915_private *dev_priv = dev->dev_private;
6058 u32 lcfuse;
6059 u8 pxw[16];
6060 int i;
6061
6062 /* Disable to program */
6063 I915_WRITE(ECR, 0);
6064 POSTING_READ(ECR);
6065
6066 /* Program energy weights for various events */
6067 I915_WRITE(SDEW, 0x15040d00);
6068 I915_WRITE(CSIEW0, 0x007f0000);
6069 I915_WRITE(CSIEW1, 0x1e220004);
6070 I915_WRITE(CSIEW2, 0x04000004);
6071
6072 for (i = 0; i < 5; i++)
6073 I915_WRITE(PEW(i), 0);
6074 for (i = 0; i < 3; i++)
6075 I915_WRITE(DEW(i), 0);
6076
6077 /* Program P-state weights to account for frequency power adjustment */
6078 for (i = 0; i < 16; i++) {
6079 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6080 unsigned long freq = intel_pxfreq(pxvidfreq);
6081 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6082 PXVFREQ_PX_SHIFT;
6083 unsigned long val;
6084
6085 val = vid * vid;
6086 val *= (freq / 1000);
6087 val *= 255;
6088 val /= (127*127*900);
6089 if (val > 0xff)
6090 DRM_ERROR("bad pxval: %ld\n", val);
6091 pxw[i] = val;
6092 }
6093 /* Render standby states get 0 weight */
6094 pxw[14] = 0;
6095 pxw[15] = 0;
6096
6097 for (i = 0; i < 4; i++) {
6098 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6099 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6100 I915_WRITE(PXW(i), val);
6101 }
6102
6103 /* Adjust magic regs to magic values (more experimental results) */
6104 I915_WRITE(OGW0, 0);
6105 I915_WRITE(OGW1, 0);
6106 I915_WRITE(EG0, 0x00007f00);
6107 I915_WRITE(EG1, 0x0000000e);
6108 I915_WRITE(EG2, 0x000e0000);
6109 I915_WRITE(EG3, 0x68000300);
6110 I915_WRITE(EG4, 0x42000000);
6111 I915_WRITE(EG5, 0x00140031);
6112 I915_WRITE(EG6, 0);
6113 I915_WRITE(EG7, 0);
6114
6115 for (i = 0; i < 8; i++)
6116 I915_WRITE(PXWL(i), 0);
6117
6118 /* Enable PMON + select events */
6119 I915_WRITE(ECR, 0x80000019);
6120
6121 lcfuse = I915_READ(LCFUSE02);
6122
6123 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6124}
6125
6126void intel_init_gt_powersave(struct drm_device *dev)
6127{
6128 struct drm_i915_private *dev_priv = dev->dev_private;
6129
6130 /*
6131 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6132 * requirement.
6133 */
6134 if (!i915.enable_rc6) {
6135 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6136 intel_runtime_pm_get(dev_priv);
6137 }
6138
6139 if (IS_CHERRYVIEW(dev))
6140 cherryview_init_gt_powersave(dev);
6141 else if (IS_VALLEYVIEW(dev))
6142 valleyview_init_gt_powersave(dev);
6143}
6144
6145void intel_cleanup_gt_powersave(struct drm_device *dev)
6146{
6147 struct drm_i915_private *dev_priv = dev->dev_private;
6148
6149 if (IS_CHERRYVIEW(dev))
6150 return;
6151 else if (IS_VALLEYVIEW(dev))
6152 valleyview_cleanup_gt_powersave(dev);
6153
6154 if (!i915.enable_rc6)
6155 intel_runtime_pm_put(dev_priv);
6156}
6157
6158static void gen6_suspend_rps(struct drm_device *dev)
6159{
6160 struct drm_i915_private *dev_priv = dev->dev_private;
6161
6162 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6163
6164 gen6_disable_rps_interrupts(dev);
6165}
6166
6167/**
6168 * intel_suspend_gt_powersave - suspend PM work and helper threads
6169 * @dev: drm device
6170 *
6171 * We don't want to disable RC6 or other features here, we just want
6172 * to make sure any work we've queued has finished and won't bother
6173 * us while we're suspended.
6174 */
6175void intel_suspend_gt_powersave(struct drm_device *dev)
6176{
6177 struct drm_i915_private *dev_priv = dev->dev_private;
6178
6179 if (INTEL_INFO(dev)->gen < 6)
6180 return;
6181
6182 gen6_suspend_rps(dev);
6183
6184 /* Force GPU to min freq during suspend */
6185 gen6_rps_idle(dev_priv);
6186}
6187
6188void intel_disable_gt_powersave(struct drm_device *dev)
6189{
6190 struct drm_i915_private *dev_priv = dev->dev_private;
6191
6192 if (IS_IRONLAKE_M(dev)) {
6193 ironlake_disable_drps(dev);
6194 } else if (INTEL_INFO(dev)->gen >= 6) {
6195 intel_suspend_gt_powersave(dev);
6196
6197 mutex_lock(&dev_priv->rps.hw_lock);
6198 if (INTEL_INFO(dev)->gen >= 9)
6199 gen9_disable_rps(dev);
6200 else if (IS_CHERRYVIEW(dev))
6201 cherryview_disable_rps(dev);
6202 else if (IS_VALLEYVIEW(dev))
6203 valleyview_disable_rps(dev);
6204 else
6205 gen6_disable_rps(dev);
6206
6207 dev_priv->rps.enabled = false;
6208 mutex_unlock(&dev_priv->rps.hw_lock);
6209 }
6210}
6211
6212static void intel_gen6_powersave_work(struct work_struct *work)
6213{
6214 struct drm_i915_private *dev_priv =
6215 container_of(work, struct drm_i915_private,
6216 rps.delayed_resume_work.work);
6217 struct drm_device *dev = dev_priv->dev;
6218
6219 mutex_lock(&dev_priv->rps.hw_lock);
6220
6221 gen6_reset_rps_interrupts(dev);
6222
6223 if (IS_CHERRYVIEW(dev)) {
6224 cherryview_enable_rps(dev);
6225 } else if (IS_VALLEYVIEW(dev)) {
6226 valleyview_enable_rps(dev);
6227 } else if (INTEL_INFO(dev)->gen >= 9) {
6228 gen9_enable_rc6(dev);
6229 gen9_enable_rps(dev);
6230 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
6231 __gen6_update_ring_freq(dev);
6232 } else if (IS_BROADWELL(dev)) {
6233 gen8_enable_rps(dev);
6234 __gen6_update_ring_freq(dev);
6235 } else {
6236 gen6_enable_rps(dev);
6237 __gen6_update_ring_freq(dev);
6238 }
6239
6240 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6241 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6242
6243 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6244 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6245
6246 dev_priv->rps.enabled = true;
6247
6248 gen6_enable_rps_interrupts(dev);
6249
6250 mutex_unlock(&dev_priv->rps.hw_lock);
6251
6252 intel_runtime_pm_put(dev_priv);
6253}
6254
6255void intel_enable_gt_powersave(struct drm_device *dev)
6256{
6257 struct drm_i915_private *dev_priv = dev->dev_private;
6258
6259 /* Powersaving is controlled by the host when inside a VM */
6260 if (intel_vgpu_active(dev))
6261 return;
6262
6263 if (IS_IRONLAKE_M(dev)) {
6264 ironlake_enable_drps(dev);
6265 mutex_lock(&dev->struct_mutex);
6266 intel_init_emon(dev);
6267 mutex_unlock(&dev->struct_mutex);
6268 } else if (INTEL_INFO(dev)->gen >= 6) {
6269 /*
6270 * PCU communication is slow and this doesn't need to be
6271 * done at any specific time, so do this out of our fast path
6272 * to make resume and init faster.
6273 *
6274 * We depend on the HW RC6 power context save/restore
6275 * mechanism when entering D3 through runtime PM suspend. So
6276 * disable RPM until RPS/RC6 is properly setup. We can only
6277 * get here via the driver load/system resume/runtime resume
6278 * paths, so the _noresume version is enough (and in case of
6279 * runtime resume it's necessary).
6280 */
6281 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6282 round_jiffies_up_relative(HZ)))
6283 intel_runtime_pm_get_noresume(dev_priv);
6284 }
6285}
6286
6287void intel_reset_gt_powersave(struct drm_device *dev)
6288{
6289 struct drm_i915_private *dev_priv = dev->dev_private;
6290
6291 if (INTEL_INFO(dev)->gen < 6)
6292 return;
6293
6294 gen6_suspend_rps(dev);
6295 dev_priv->rps.enabled = false;
6296}
6297
6298static void ibx_init_clock_gating(struct drm_device *dev)
6299{
6300 struct drm_i915_private *dev_priv = dev->dev_private;
6301
6302 /*
6303 * On Ibex Peak and Cougar Point, we need to disable clock
6304 * gating for the panel power sequencer or it will fail to
6305 * start up when no ports are active.
6306 */
6307 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6308}
6309
6310static void g4x_disable_trickle_feed(struct drm_device *dev)
6311{
6312 struct drm_i915_private *dev_priv = dev->dev_private;
6313 enum pipe pipe;
6314
6315 for_each_pipe(dev_priv, pipe) {
6316 I915_WRITE(DSPCNTR(pipe),
6317 I915_READ(DSPCNTR(pipe)) |
6318 DISPPLANE_TRICKLE_FEED_DISABLE);
6319
6320 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6321 POSTING_READ(DSPSURF(pipe));
6322 }
6323}
6324
6325static void ilk_init_lp_watermarks(struct drm_device *dev)
6326{
6327 struct drm_i915_private *dev_priv = dev->dev_private;
6328
6329 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6330 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6331 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6332
6333 /*
6334 * Don't touch WM1S_LP_EN here.
6335 * Doing so could cause underruns.
6336 */
6337}
6338
6339static void ironlake_init_clock_gating(struct drm_device *dev)
6340{
6341 struct drm_i915_private *dev_priv = dev->dev_private;
6342 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6343
6344 /*
6345 * Required for FBC
6346 * WaFbcDisableDpfcClockGating:ilk
6347 */
6348 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6349 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6350 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6351
6352 I915_WRITE(PCH_3DCGDIS0,
6353 MARIUNIT_CLOCK_GATE_DISABLE |
6354 SVSMUNIT_CLOCK_GATE_DISABLE);
6355 I915_WRITE(PCH_3DCGDIS1,
6356 VFMUNIT_CLOCK_GATE_DISABLE);
6357
6358 /*
6359 * According to the spec the following bits should be set in
6360 * order to enable memory self-refresh
6361 * The bit 22/21 of 0x42004
6362 * The bit 5 of 0x42020
6363 * The bit 15 of 0x45000
6364 */
6365 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6366 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6367 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6368 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6369 I915_WRITE(DISP_ARB_CTL,
6370 (I915_READ(DISP_ARB_CTL) |
6371 DISP_FBC_WM_DIS));
6372
6373 ilk_init_lp_watermarks(dev);
6374
6375 /*
6376 * Based on the document from hardware guys the following bits
6377 * should be set unconditionally in order to enable FBC.
6378 * The bit 22 of 0x42000
6379 * The bit 22 of 0x42004
6380 * The bit 7,8,9 of 0x42020.
6381 */
6382 if (IS_IRONLAKE_M(dev)) {
6383 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6384 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6385 I915_READ(ILK_DISPLAY_CHICKEN1) |
6386 ILK_FBCQ_DIS);
6387 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6388 I915_READ(ILK_DISPLAY_CHICKEN2) |
6389 ILK_DPARB_GATE);
6390 }
6391
6392 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6393
6394 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6395 I915_READ(ILK_DISPLAY_CHICKEN2) |
6396 ILK_ELPIN_409_SELECT);
6397 I915_WRITE(_3D_CHICKEN2,
6398 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6399 _3D_CHICKEN2_WM_READ_PIPELINED);
6400
6401 /* WaDisableRenderCachePipelinedFlush:ilk */
6402 I915_WRITE(CACHE_MODE_0,
6403 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6404
6405 /* WaDisable_RenderCache_OperationalFlush:ilk */
6406 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6407
6408 g4x_disable_trickle_feed(dev);
6409
6410 ibx_init_clock_gating(dev);
6411}
6412
6413static void cpt_init_clock_gating(struct drm_device *dev)
6414{
6415 struct drm_i915_private *dev_priv = dev->dev_private;
6416 int pipe;
6417 uint32_t val;
6418
6419 /*
6420 * On Ibex Peak and Cougar Point, we need to disable clock
6421 * gating for the panel power sequencer or it will fail to
6422 * start up when no ports are active.
6423 */
6424 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6425 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6426 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6427 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6428 DPLS_EDP_PPS_FIX_DIS);
6429 /* The below fixes the weird display corruption, a few pixels shifted
6430 * downward, on (only) LVDS of some HP laptops with IVY.
6431 */
6432 for_each_pipe(dev_priv, pipe) {
6433 val = I915_READ(TRANS_CHICKEN2(pipe));
6434 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6435 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6436 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6437 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6438 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6439 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6440 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6441 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6442 }
6443 /* WADP0ClockGatingDisable */
6444 for_each_pipe(dev_priv, pipe) {
6445 I915_WRITE(TRANS_CHICKEN1(pipe),
6446 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6447 }
6448}
6449
6450static void gen6_check_mch_setup(struct drm_device *dev)
6451{
6452 struct drm_i915_private *dev_priv = dev->dev_private;
6453 uint32_t tmp;
6454
6455 tmp = I915_READ(MCH_SSKPD);
6456 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6457 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6458 tmp);
6459}
6460
6461static void gen6_init_clock_gating(struct drm_device *dev)
6462{
6463 struct drm_i915_private *dev_priv = dev->dev_private;
6464 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6465
6466 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6467
6468 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6469 I915_READ(ILK_DISPLAY_CHICKEN2) |
6470 ILK_ELPIN_409_SELECT);
6471
6472 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6473 I915_WRITE(_3D_CHICKEN,
6474 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6475
6476 /* WaDisable_RenderCache_OperationalFlush:snb */
6477 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6478
6479 /*
6480 * BSpec recoomends 8x4 when MSAA is used,
6481 * however in practice 16x4 seems fastest.
6482 *
6483 * Note that PS/WM thread counts depend on the WIZ hashing
6484 * disable bit, which we don't touch here, but it's good
6485 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6486 */
6487 I915_WRITE(GEN6_GT_MODE,
6488 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6489
6490 ilk_init_lp_watermarks(dev);
6491
6492 I915_WRITE(CACHE_MODE_0,
6493 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6494
6495 I915_WRITE(GEN6_UCGCTL1,
6496 I915_READ(GEN6_UCGCTL1) |
6497 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6498 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6499
6500 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6501 * gating disable must be set. Failure to set it results in
6502 * flickering pixels due to Z write ordering failures after
6503 * some amount of runtime in the Mesa "fire" demo, and Unigine
6504 * Sanctuary and Tropics, and apparently anything else with
6505 * alpha test or pixel discard.
6506 *
6507 * According to the spec, bit 11 (RCCUNIT) must also be set,
6508 * but we didn't debug actual testcases to find it out.
6509 *
6510 * WaDisableRCCUnitClockGating:snb
6511 * WaDisableRCPBUnitClockGating:snb
6512 */
6513 I915_WRITE(GEN6_UCGCTL2,
6514 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6515 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6516
6517 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6518 I915_WRITE(_3D_CHICKEN3,
6519 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6520
6521 /*
6522 * Bspec says:
6523 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6524 * 3DSTATE_SF number of SF output attributes is more than 16."
6525 */
6526 I915_WRITE(_3D_CHICKEN3,
6527 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6528
6529 /*
6530 * According to the spec the following bits should be
6531 * set in order to enable memory self-refresh and fbc:
6532 * The bit21 and bit22 of 0x42000
6533 * The bit21 and bit22 of 0x42004
6534 * The bit5 and bit7 of 0x42020
6535 * The bit14 of 0x70180
6536 * The bit14 of 0x71180
6537 *
6538 * WaFbcAsynchFlipDisableFbcQueue:snb
6539 */
6540 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6541 I915_READ(ILK_DISPLAY_CHICKEN1) |
6542 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6543 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6544 I915_READ(ILK_DISPLAY_CHICKEN2) |
6545 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6546 I915_WRITE(ILK_DSPCLK_GATE_D,
6547 I915_READ(ILK_DSPCLK_GATE_D) |
6548 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6549 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6550
6551 g4x_disable_trickle_feed(dev);
6552
6553 cpt_init_clock_gating(dev);
6554
6555 gen6_check_mch_setup(dev);
6556}
6557
6558static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6559{
6560 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6561
6562 /*
6563 * WaVSThreadDispatchOverride:ivb,vlv
6564 *
6565 * This actually overrides the dispatch
6566 * mode for all thread types.
6567 */
6568 reg &= ~GEN7_FF_SCHED_MASK;
6569 reg |= GEN7_FF_TS_SCHED_HW;
6570 reg |= GEN7_FF_VS_SCHED_HW;
6571 reg |= GEN7_FF_DS_SCHED_HW;
6572
6573 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6574}
6575
6576static void lpt_init_clock_gating(struct drm_device *dev)
6577{
6578 struct drm_i915_private *dev_priv = dev->dev_private;
6579
6580 /*
6581 * TODO: this bit should only be enabled when really needed, then
6582 * disabled when not needed anymore in order to save power.
6583 */
6584 if (HAS_PCH_LPT_LP(dev))
6585 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6586 I915_READ(SOUTH_DSPCLK_GATE_D) |
6587 PCH_LP_PARTITION_LEVEL_DISABLE);
6588
6589 /* WADPOClockGatingDisable:hsw */
6590 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6591 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6592 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6593}
6594
6595static void lpt_suspend_hw(struct drm_device *dev)
6596{
6597 struct drm_i915_private *dev_priv = dev->dev_private;
6598
6599 if (HAS_PCH_LPT_LP(dev)) {
6600 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6601
6602 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6603 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6604 }
6605}
6606
6607static void broadwell_init_clock_gating(struct drm_device *dev)
6608{
6609 struct drm_i915_private *dev_priv = dev->dev_private;
6610 enum pipe pipe;
6611 uint32_t misccpctl;
6612
6613 ilk_init_lp_watermarks(dev);
6614
6615 /* WaSwitchSolVfFArbitrationPriority:bdw */
6616 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6617
6618 /* WaPsrDPAMaskVBlankInSRD:bdw */
6619 I915_WRITE(CHICKEN_PAR1_1,
6620 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6621
6622 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6623 for_each_pipe(dev_priv, pipe) {
6624 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6625 I915_READ(CHICKEN_PIPESL_1(pipe)) |
6626 BDW_DPRS_MASK_VBLANK_SRD);
6627 }
6628
6629 /* WaVSRefCountFullforceMissDisable:bdw */
6630 /* WaDSRefCountFullforceMissDisable:bdw */
6631 I915_WRITE(GEN7_FF_THREAD_MODE,
6632 I915_READ(GEN7_FF_THREAD_MODE) &
6633 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6634
6635 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6636 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6637
6638 /* WaDisableSDEUnitClockGating:bdw */
6639 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6640 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6641
6642 /*
6643 * WaProgramL3SqcReg1Default:bdw
6644 * WaTempDisableDOPClkGating:bdw
6645 */
6646 misccpctl = I915_READ(GEN7_MISCCPCTL);
6647 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6648 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6649 /*
6650 * Wait at least 100 clocks before re-enabling clock gating. See
6651 * the definition of L3SQCREG1 in BSpec.
6652 */
6653 POSTING_READ(GEN8_L3SQCREG1);
6654 udelay(1);
6655 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6656
6657 /*
6658 * WaGttCachingOffByDefault:bdw
6659 * GTT cache may not work with big pages, so if those
6660 * are ever enabled GTT cache may need to be disabled.
6661 */
6662 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6663
6664 lpt_init_clock_gating(dev);
6665}
6666
6667static void haswell_init_clock_gating(struct drm_device *dev)
6668{
6669 struct drm_i915_private *dev_priv = dev->dev_private;
6670
6671 ilk_init_lp_watermarks(dev);
6672
6673 /* L3 caching of data atomics doesn't work -- disable it. */
6674 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6675 I915_WRITE(HSW_ROW_CHICKEN3,
6676 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6677
6678 /* This is required by WaCatErrorRejectionIssue:hsw */
6679 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6680 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6681 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6682
6683 /* WaVSRefCountFullforceMissDisable:hsw */
6684 I915_WRITE(GEN7_FF_THREAD_MODE,
6685 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6686
6687 /* WaDisable_RenderCache_OperationalFlush:hsw */
6688 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6689
6690 /* enable HiZ Raw Stall Optimization */
6691 I915_WRITE(CACHE_MODE_0_GEN7,
6692 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6693
6694 /* WaDisable4x2SubspanOptimization:hsw */
6695 I915_WRITE(CACHE_MODE_1,
6696 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6697
6698 /*
6699 * BSpec recommends 8x4 when MSAA is used,
6700 * however in practice 16x4 seems fastest.
6701 *
6702 * Note that PS/WM thread counts depend on the WIZ hashing
6703 * disable bit, which we don't touch here, but it's good
6704 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6705 */
6706 I915_WRITE(GEN7_GT_MODE,
6707 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6708
6709 /* WaSampleCChickenBitEnable:hsw */
6710 I915_WRITE(HALF_SLICE_CHICKEN3,
6711 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6712
6713 /* WaSwitchSolVfFArbitrationPriority:hsw */
6714 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6715
6716 /* WaRsPkgCStateDisplayPMReq:hsw */
6717 I915_WRITE(CHICKEN_PAR1_1,
6718 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6719
6720 lpt_init_clock_gating(dev);
6721}
6722
6723static void ivybridge_init_clock_gating(struct drm_device *dev)
6724{
6725 struct drm_i915_private *dev_priv = dev->dev_private;
6726 uint32_t snpcr;
6727
6728 ilk_init_lp_watermarks(dev);
6729
6730 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6731
6732 /* WaDisableEarlyCull:ivb */
6733 I915_WRITE(_3D_CHICKEN3,
6734 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6735
6736 /* WaDisableBackToBackFlipFix:ivb */
6737 I915_WRITE(IVB_CHICKEN3,
6738 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6739 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6740
6741 /* WaDisablePSDDualDispatchEnable:ivb */
6742 if (IS_IVB_GT1(dev))
6743 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6744 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6745
6746 /* WaDisable_RenderCache_OperationalFlush:ivb */
6747 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6748
6749 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6750 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6751 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6752
6753 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6754 I915_WRITE(GEN7_L3CNTLREG1,
6755 GEN7_WA_FOR_GEN7_L3_CONTROL);
6756 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6757 GEN7_WA_L3_CHICKEN_MODE);
6758 if (IS_IVB_GT1(dev))
6759 I915_WRITE(GEN7_ROW_CHICKEN2,
6760 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6761 else {
6762 /* must write both registers */
6763 I915_WRITE(GEN7_ROW_CHICKEN2,
6764 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6765 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6766 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6767 }
6768
6769 /* WaForceL3Serialization:ivb */
6770 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6771 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6772
6773 /*
6774 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6775 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6776 */
6777 I915_WRITE(GEN6_UCGCTL2,
6778 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6779
6780 /* This is required by WaCatErrorRejectionIssue:ivb */
6781 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6782 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6783 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6784
6785 g4x_disable_trickle_feed(dev);
6786
6787 gen7_setup_fixed_func_scheduler(dev_priv);
6788
6789 if (0) { /* causes HiZ corruption on ivb:gt1 */
6790 /* enable HiZ Raw Stall Optimization */
6791 I915_WRITE(CACHE_MODE_0_GEN7,
6792 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6793 }
6794
6795 /* WaDisable4x2SubspanOptimization:ivb */
6796 I915_WRITE(CACHE_MODE_1,
6797 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6798
6799 /*
6800 * BSpec recommends 8x4 when MSAA is used,
6801 * however in practice 16x4 seems fastest.
6802 *
6803 * Note that PS/WM thread counts depend on the WIZ hashing
6804 * disable bit, which we don't touch here, but it's good
6805 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6806 */
6807 I915_WRITE(GEN7_GT_MODE,
6808 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6809
6810 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6811 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6812 snpcr |= GEN6_MBC_SNPCR_MED;
6813 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6814
6815 if (!HAS_PCH_NOP(dev))
6816 cpt_init_clock_gating(dev);
6817
6818 gen6_check_mch_setup(dev);
6819}
6820
6821static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6822{
6823 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6824
6825 /*
6826 * Disable trickle feed and enable pnd deadline calculation
6827 */
6828 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6829 I915_WRITE(CBR1_VLV, 0);
6830}
6831
6832static void valleyview_init_clock_gating(struct drm_device *dev)
6833{
6834 struct drm_i915_private *dev_priv = dev->dev_private;
6835
6836 vlv_init_display_clock_gating(dev_priv);
6837
6838 /* WaDisableEarlyCull:vlv */
6839 I915_WRITE(_3D_CHICKEN3,
6840 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6841
6842 /* WaDisableBackToBackFlipFix:vlv */
6843 I915_WRITE(IVB_CHICKEN3,
6844 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6845 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6846
6847 /* WaPsdDispatchEnable:vlv */
6848 /* WaDisablePSDDualDispatchEnable:vlv */
6849 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6850 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6851 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6852
6853 /* WaDisable_RenderCache_OperationalFlush:vlv */
6854 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6855
6856 /* WaForceL3Serialization:vlv */
6857 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6858 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6859
6860 /* WaDisableDopClockGating:vlv */
6861 I915_WRITE(GEN7_ROW_CHICKEN2,
6862 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6863
6864 /* This is required by WaCatErrorRejectionIssue:vlv */
6865 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6866 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6867 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6868
6869 gen7_setup_fixed_func_scheduler(dev_priv);
6870
6871 /*
6872 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6873 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6874 */
6875 I915_WRITE(GEN6_UCGCTL2,
6876 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6877
6878 /* WaDisableL3Bank2xClockGate:vlv
6879 * Disabling L3 clock gating- MMIO 940c[25] = 1
6880 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6881 I915_WRITE(GEN7_UCGCTL4,
6882 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6883
6884 /*
6885 * BSpec says this must be set, even though
6886 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6887 */
6888 I915_WRITE(CACHE_MODE_1,
6889 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6890
6891 /*
6892 * BSpec recommends 8x4 when MSAA is used,
6893 * however in practice 16x4 seems fastest.
6894 *
6895 * Note that PS/WM thread counts depend on the WIZ hashing
6896 * disable bit, which we don't touch here, but it's good
6897 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6898 */
6899 I915_WRITE(GEN7_GT_MODE,
6900 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6901
6902 /*
6903 * WaIncreaseL3CreditsForVLVB0:vlv
6904 * This is the hardware default actually.
6905 */
6906 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6907
6908 /*
6909 * WaDisableVLVClockGating_VBIIssue:vlv
6910 * Disable clock gating on th GCFG unit to prevent a delay
6911 * in the reporting of vblank events.
6912 */
6913 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6914}
6915
6916static void cherryview_init_clock_gating(struct drm_device *dev)
6917{
6918 struct drm_i915_private *dev_priv = dev->dev_private;
6919
6920 vlv_init_display_clock_gating(dev_priv);
6921
6922 /* WaVSRefCountFullforceMissDisable:chv */
6923 /* WaDSRefCountFullforceMissDisable:chv */
6924 I915_WRITE(GEN7_FF_THREAD_MODE,
6925 I915_READ(GEN7_FF_THREAD_MODE) &
6926 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6927
6928 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6929 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6930 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6931
6932 /* WaDisableCSUnitClockGating:chv */
6933 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6934 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6935
6936 /* WaDisableSDEUnitClockGating:chv */
6937 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6938 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6939
6940 /*
6941 * GTT cache may not work with big pages, so if those
6942 * are ever enabled GTT cache may need to be disabled.
6943 */
6944 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6945}
6946
6947static void g4x_init_clock_gating(struct drm_device *dev)
6948{
6949 struct drm_i915_private *dev_priv = dev->dev_private;
6950 uint32_t dspclk_gate;
6951
6952 I915_WRITE(RENCLK_GATE_D1, 0);
6953 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6954 GS_UNIT_CLOCK_GATE_DISABLE |
6955 CL_UNIT_CLOCK_GATE_DISABLE);
6956 I915_WRITE(RAMCLK_GATE_D, 0);
6957 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6958 OVRUNIT_CLOCK_GATE_DISABLE |
6959 OVCUNIT_CLOCK_GATE_DISABLE;
6960 if (IS_GM45(dev))
6961 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6962 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6963
6964 /* WaDisableRenderCachePipelinedFlush */
6965 I915_WRITE(CACHE_MODE_0,
6966 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6967
6968 /* WaDisable_RenderCache_OperationalFlush:g4x */
6969 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6970
6971 g4x_disable_trickle_feed(dev);
6972}
6973
6974static void crestline_init_clock_gating(struct drm_device *dev)
6975{
6976 struct drm_i915_private *dev_priv = dev->dev_private;
6977
6978 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6979 I915_WRITE(RENCLK_GATE_D2, 0);
6980 I915_WRITE(DSPCLK_GATE_D, 0);
6981 I915_WRITE(RAMCLK_GATE_D, 0);
6982 I915_WRITE16(DEUC, 0);
6983 I915_WRITE(MI_ARB_STATE,
6984 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6985
6986 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6987 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6988}
6989
6990static void broadwater_init_clock_gating(struct drm_device *dev)
6991{
6992 struct drm_i915_private *dev_priv = dev->dev_private;
6993
6994 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6995 I965_RCC_CLOCK_GATE_DISABLE |
6996 I965_RCPB_CLOCK_GATE_DISABLE |
6997 I965_ISC_CLOCK_GATE_DISABLE |
6998 I965_FBC_CLOCK_GATE_DISABLE);
6999 I915_WRITE(RENCLK_GATE_D2, 0);
7000 I915_WRITE(MI_ARB_STATE,
7001 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7002
7003 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7004 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7005}
7006
7007static void gen3_init_clock_gating(struct drm_device *dev)
7008{
7009 struct drm_i915_private *dev_priv = dev->dev_private;
7010 u32 dstate = I915_READ(D_STATE);
7011
7012 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7013 DSTATE_DOT_CLOCK_GATING;
7014 I915_WRITE(D_STATE, dstate);
7015
7016 if (IS_PINEVIEW(dev))
7017 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7018
7019 /* IIR "flip pending" means done if this bit is set */
7020 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7021
7022 /* interrupts should cause a wake up from C3 */
7023 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7024
7025 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7026 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7027
7028 I915_WRITE(MI_ARB_STATE,
7029 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7030}
7031
7032static void i85x_init_clock_gating(struct drm_device *dev)
7033{
7034 struct drm_i915_private *dev_priv = dev->dev_private;
7035
7036 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7037
7038 /* interrupts should cause a wake up from C3 */
7039 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7040 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7041
7042 I915_WRITE(MEM_MODE,
7043 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7044}
7045
7046static void i830_init_clock_gating(struct drm_device *dev)
7047{
7048 struct drm_i915_private *dev_priv = dev->dev_private;
7049
7050 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7051
7052 I915_WRITE(MEM_MODE,
7053 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7054 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7055}
7056
7057void intel_init_clock_gating(struct drm_device *dev)
7058{
7059 struct drm_i915_private *dev_priv = dev->dev_private;
7060
7061 if (dev_priv->display.init_clock_gating)
7062 dev_priv->display.init_clock_gating(dev);
7063}
7064
7065void intel_suspend_hw(struct drm_device *dev)
7066{
7067 if (HAS_PCH_LPT(dev))
7068 lpt_suspend_hw(dev);
7069}
7070
7071/* Set up chip specific power management-related functions */
7072void intel_init_pm(struct drm_device *dev)
7073{
7074 struct drm_i915_private *dev_priv = dev->dev_private;
7075
7076 intel_fbc_init(dev_priv);
7077
7078 /* For cxsr */
7079 if (IS_PINEVIEW(dev))
7080 i915_pineview_get_mem_freq(dev);
7081 else if (IS_GEN5(dev))
7082 i915_ironlake_get_mem_freq(dev);
7083
7084 /* For FIFO watermark updates */
7085 if (INTEL_INFO(dev)->gen >= 9) {
7086 skl_setup_wm_latency(dev);
7087
7088 if (IS_BROXTON(dev))
7089 dev_priv->display.init_clock_gating =
7090 bxt_init_clock_gating;
7091 dev_priv->display.update_wm = skl_update_wm;
7092 } else if (HAS_PCH_SPLIT(dev)) {
7093 ilk_setup_wm_latency(dev);
7094
7095 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7096 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7097 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7098 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7099 dev_priv->display.update_wm = ilk_update_wm;
7100 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7101 dev_priv->display.program_watermarks = ilk_program_watermarks;
7102 } else {
7103 DRM_DEBUG_KMS("Failed to read display plane latency. "
7104 "Disable CxSR\n");
7105 }
7106
7107 if (IS_GEN5(dev))
7108 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7109 else if (IS_GEN6(dev))
7110 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7111 else if (IS_IVYBRIDGE(dev))
7112 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7113 else if (IS_HASWELL(dev))
7114 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7115 else if (INTEL_INFO(dev)->gen == 8)
7116 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7117 } else if (IS_CHERRYVIEW(dev)) {
7118 vlv_setup_wm_latency(dev);
7119
7120 dev_priv->display.update_wm = vlv_update_wm;
7121 dev_priv->display.init_clock_gating =
7122 cherryview_init_clock_gating;
7123 } else if (IS_VALLEYVIEW(dev)) {
7124 vlv_setup_wm_latency(dev);
7125
7126 dev_priv->display.update_wm = vlv_update_wm;
7127 dev_priv->display.init_clock_gating =
7128 valleyview_init_clock_gating;
7129 } else if (IS_PINEVIEW(dev)) {
7130 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7131 dev_priv->is_ddr3,
7132 dev_priv->fsb_freq,
7133 dev_priv->mem_freq)) {
7134 DRM_INFO("failed to find known CxSR latency "
7135 "(found ddr%s fsb freq %d, mem freq %d), "
7136 "disabling CxSR\n",
7137 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7138 dev_priv->fsb_freq, dev_priv->mem_freq);
7139 /* Disable CxSR and never update its watermark again */
7140 intel_set_memory_cxsr(dev_priv, false);
7141 dev_priv->display.update_wm = NULL;
7142 } else
7143 dev_priv->display.update_wm = pineview_update_wm;
7144 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7145 } else if (IS_G4X(dev)) {
7146 dev_priv->display.update_wm = g4x_update_wm;
7147 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7148 } else if (IS_GEN4(dev)) {
7149 dev_priv->display.update_wm = i965_update_wm;
7150 if (IS_CRESTLINE(dev))
7151 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7152 else if (IS_BROADWATER(dev))
7153 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7154 } else if (IS_GEN3(dev)) {
7155 dev_priv->display.update_wm = i9xx_update_wm;
7156 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7157 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7158 } else if (IS_GEN2(dev)) {
7159 if (INTEL_INFO(dev)->num_pipes == 1) {
7160 dev_priv->display.update_wm = i845_update_wm;
7161 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7162 } else {
7163 dev_priv->display.update_wm = i9xx_update_wm;
7164 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7165 }
7166
7167 if (IS_I85X(dev) || IS_I865G(dev))
7168 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7169 else
7170 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7171 } else {
7172 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7173 }
7174}
7175
7176int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7177{
7178 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7179
7180 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7181 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7182 return -EAGAIN;
7183 }
7184
7185 I915_WRITE(GEN6_PCODE_DATA, *val);
7186 I915_WRITE(GEN6_PCODE_DATA1, 0);
7187 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7188
7189 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7190 500)) {
7191 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7192 return -ETIMEDOUT;
7193 }
7194
7195 *val = I915_READ(GEN6_PCODE_DATA);
7196 I915_WRITE(GEN6_PCODE_DATA, 0);
7197
7198 return 0;
7199}
7200
7201int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7202{
7203 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7204
7205 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7206 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7207 return -EAGAIN;
7208 }
7209
7210 I915_WRITE(GEN6_PCODE_DATA, val);
7211 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7212
7213 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7214 500)) {
7215 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7216 return -ETIMEDOUT;
7217 }
7218
7219 I915_WRITE(GEN6_PCODE_DATA, 0);
7220
7221 return 0;
7222}
7223
7224static int vlv_gpu_freq_div(unsigned int czclk_freq)
7225{
7226 switch (czclk_freq) {
7227 case 200:
7228 return 10;
7229 case 267:
7230 return 12;
7231 case 320:
7232 case 333:
7233 return 16;
7234 case 400:
7235 return 20;
7236 default:
7237 return -1;
7238 }
7239}
7240
7241static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7242{
7243 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7244
7245 div = vlv_gpu_freq_div(czclk_freq);
7246 if (div < 0)
7247 return div;
7248
7249 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7250}
7251
7252static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7253{
7254 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7255
7256 mul = vlv_gpu_freq_div(czclk_freq);
7257 if (mul < 0)
7258 return mul;
7259
7260 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7261}
7262
7263static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7264{
7265 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7266
7267 div = vlv_gpu_freq_div(czclk_freq);
7268 if (div < 0)
7269 return div;
7270 div /= 2;
7271
7272 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7273}
7274
7275static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7276{
7277 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7278
7279 mul = vlv_gpu_freq_div(czclk_freq);
7280 if (mul < 0)
7281 return mul;
7282 mul /= 2;
7283
7284 /* CHV needs even values */
7285 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7286}
7287
7288int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7289{
7290 if (IS_GEN9(dev_priv->dev))
7291 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7292 GEN9_FREQ_SCALER);
7293 else if (IS_CHERRYVIEW(dev_priv->dev))
7294 return chv_gpu_freq(dev_priv, val);
7295 else if (IS_VALLEYVIEW(dev_priv->dev))
7296 return byt_gpu_freq(dev_priv, val);
7297 else
7298 return val * GT_FREQUENCY_MULTIPLIER;
7299}
7300
7301int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7302{
7303 if (IS_GEN9(dev_priv->dev))
7304 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7305 GT_FREQUENCY_MULTIPLIER);
7306 else if (IS_CHERRYVIEW(dev_priv->dev))
7307 return chv_freq_opcode(dev_priv, val);
7308 else if (IS_VALLEYVIEW(dev_priv->dev))
7309 return byt_freq_opcode(dev_priv, val);
7310 else
7311 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7312}
7313
7314struct request_boost {
7315 struct work_struct work;
7316 struct drm_i915_gem_request *req;
7317};
7318
7319static void __intel_rps_boost_work(struct work_struct *work)
7320{
7321 struct request_boost *boost = container_of(work, struct request_boost, work);
7322 struct drm_i915_gem_request *req = boost->req;
7323
7324 if (!i915_gem_request_completed(req, true))
7325 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7326 req->emitted_jiffies);
7327
7328 i915_gem_request_unreference__unlocked(req);
7329 kfree(boost);
7330}
7331
7332void intel_queue_rps_boost_for_request(struct drm_device *dev,
7333 struct drm_i915_gem_request *req)
7334{
7335 struct request_boost *boost;
7336
7337 if (req == NULL || INTEL_INFO(dev)->gen < 6)
7338 return;
7339
7340 if (i915_gem_request_completed(req, true))
7341 return;
7342
7343 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7344 if (boost == NULL)
7345 return;
7346
7347 i915_gem_request_reference(req);
7348 boost->req = req;
7349
7350 INIT_WORK(&boost->work, __intel_rps_boost_work);
7351 queue_work(to_i915(dev)->wq, &boost->work);
7352}
7353
7354void intel_pm_setup(struct drm_device *dev)
7355{
7356 struct drm_i915_private *dev_priv = dev->dev_private;
7357
7358 mutex_init(&dev_priv->rps.hw_lock);
7359 spin_lock_init(&dev_priv->rps.client_lock);
7360
7361 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7362 intel_gen6_powersave_work);
7363 INIT_LIST_HEAD(&dev_priv->rps.clients);
7364 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7365 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7366
7367 dev_priv->pm.suspended = false;
7368 atomic_set(&dev_priv->pm.wakeref_count, 0);
7369 atomic_set(&dev_priv->pm.atomic_seq, 0);
7370}
1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include <linux/cpufreq.h>
29#include <drm/drm_plane_helper.h>
30#include "i915_drv.h"
31#include "intel_drv.h"
32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
34#include <drm/drm_atomic_helper.h>
35
36/**
37 * DOC: RC6
38 *
39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 *
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
47 *
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
54 */
55#define INTEL_RC6_ENABLE (1<<0)
56#define INTEL_RC6p_ENABLE (1<<1)
57#define INTEL_RC6pp_ENABLE (1<<2)
58
59static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
60{
61 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
62 I915_WRITE(CHICKEN_PAR1_1,
63 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
64
65 I915_WRITE(GEN8_CONFIG0,
66 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
67
68 /* WaEnableChickenDCPR:skl,bxt,kbl */
69 I915_WRITE(GEN8_CHICKEN_DCPR_1,
70 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
71
72 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
73 /* WaFbcWakeMemOn:skl,bxt,kbl */
74 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
75 DISP_FBC_WM_DIS |
76 DISP_FBC_MEMORY_WAKE);
77
78 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
79 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
80 ILK_DPFC_DISABLE_DUMMY0);
81}
82
83static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
84{
85 gen9_init_clock_gating(dev_priv);
86
87 /* WaDisableSDEUnitClockGating:bxt */
88 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
89 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
90
91 /*
92 * FIXME:
93 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
94 */
95 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
96 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
97
98 /*
99 * Wa: Backlight PWM may stop in the asserted state, causing backlight
100 * to stay fully on.
101 */
102 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
103 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
104 PWM1_GATING_DIS | PWM2_GATING_DIS);
105}
106
107static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
108{
109 u32 tmp;
110
111 tmp = I915_READ(CLKCFG);
112
113 switch (tmp & CLKCFG_FSB_MASK) {
114 case CLKCFG_FSB_533:
115 dev_priv->fsb_freq = 533; /* 133*4 */
116 break;
117 case CLKCFG_FSB_800:
118 dev_priv->fsb_freq = 800; /* 200*4 */
119 break;
120 case CLKCFG_FSB_667:
121 dev_priv->fsb_freq = 667; /* 167*4 */
122 break;
123 case CLKCFG_FSB_400:
124 dev_priv->fsb_freq = 400; /* 100*4 */
125 break;
126 }
127
128 switch (tmp & CLKCFG_MEM_MASK) {
129 case CLKCFG_MEM_533:
130 dev_priv->mem_freq = 533;
131 break;
132 case CLKCFG_MEM_667:
133 dev_priv->mem_freq = 667;
134 break;
135 case CLKCFG_MEM_800:
136 dev_priv->mem_freq = 800;
137 break;
138 }
139
140 /* detect pineview DDR3 setting */
141 tmp = I915_READ(CSHRDDR3CTL);
142 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
143}
144
145static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
146{
147 u16 ddrpll, csipll;
148
149 ddrpll = I915_READ16(DDRMPLL1);
150 csipll = I915_READ16(CSIPLL0);
151
152 switch (ddrpll & 0xff) {
153 case 0xc:
154 dev_priv->mem_freq = 800;
155 break;
156 case 0x10:
157 dev_priv->mem_freq = 1066;
158 break;
159 case 0x14:
160 dev_priv->mem_freq = 1333;
161 break;
162 case 0x18:
163 dev_priv->mem_freq = 1600;
164 break;
165 default:
166 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
167 ddrpll & 0xff);
168 dev_priv->mem_freq = 0;
169 break;
170 }
171
172 dev_priv->ips.r_t = dev_priv->mem_freq;
173
174 switch (csipll & 0x3ff) {
175 case 0x00c:
176 dev_priv->fsb_freq = 3200;
177 break;
178 case 0x00e:
179 dev_priv->fsb_freq = 3733;
180 break;
181 case 0x010:
182 dev_priv->fsb_freq = 4266;
183 break;
184 case 0x012:
185 dev_priv->fsb_freq = 4800;
186 break;
187 case 0x014:
188 dev_priv->fsb_freq = 5333;
189 break;
190 case 0x016:
191 dev_priv->fsb_freq = 5866;
192 break;
193 case 0x018:
194 dev_priv->fsb_freq = 6400;
195 break;
196 default:
197 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
198 csipll & 0x3ff);
199 dev_priv->fsb_freq = 0;
200 break;
201 }
202
203 if (dev_priv->fsb_freq == 3200) {
204 dev_priv->ips.c_m = 0;
205 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
206 dev_priv->ips.c_m = 1;
207 } else {
208 dev_priv->ips.c_m = 2;
209 }
210}
211
212static const struct cxsr_latency cxsr_latency_table[] = {
213 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
214 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
215 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
216 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
217 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
218
219 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
220 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
221 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
222 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
223 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
224
225 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
226 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
227 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
228 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
229 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
230
231 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
232 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
233 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
234 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
235 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
236
237 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
238 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
239 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
240 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
241 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
242
243 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
244 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
245 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
246 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
247 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
248};
249
250static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
251 bool is_ddr3,
252 int fsb,
253 int mem)
254{
255 const struct cxsr_latency *latency;
256 int i;
257
258 if (fsb == 0 || mem == 0)
259 return NULL;
260
261 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
262 latency = &cxsr_latency_table[i];
263 if (is_desktop == latency->is_desktop &&
264 is_ddr3 == latency->is_ddr3 &&
265 fsb == latency->fsb_freq && mem == latency->mem_freq)
266 return latency;
267 }
268
269 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
270
271 return NULL;
272}
273
274static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
275{
276 u32 val;
277
278 mutex_lock(&dev_priv->rps.hw_lock);
279
280 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
281 if (enable)
282 val &= ~FORCE_DDR_HIGH_FREQ;
283 else
284 val |= FORCE_DDR_HIGH_FREQ;
285 val &= ~FORCE_DDR_LOW_FREQ;
286 val |= FORCE_DDR_FREQ_REQ_ACK;
287 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
288
289 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
290 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
291 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
292
293 mutex_unlock(&dev_priv->rps.hw_lock);
294}
295
296static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
297{
298 u32 val;
299
300 mutex_lock(&dev_priv->rps.hw_lock);
301
302 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
303 if (enable)
304 val |= DSP_MAXFIFO_PM5_ENABLE;
305 else
306 val &= ~DSP_MAXFIFO_PM5_ENABLE;
307 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
308
309 mutex_unlock(&dev_priv->rps.hw_lock);
310}
311
312#define FW_WM(value, plane) \
313 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
314
315void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
316{
317 u32 val;
318
319 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
320 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
321 POSTING_READ(FW_BLC_SELF_VLV);
322 dev_priv->wm.vlv.cxsr = enable;
323 } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
324 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
325 POSTING_READ(FW_BLC_SELF);
326 } else if (IS_PINEVIEW(dev_priv)) {
327 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
328 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
329 I915_WRITE(DSPFW3, val);
330 POSTING_READ(DSPFW3);
331 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
332 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
333 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
334 I915_WRITE(FW_BLC_SELF, val);
335 POSTING_READ(FW_BLC_SELF);
336 } else if (IS_I915GM(dev_priv)) {
337 /*
338 * FIXME can't find a bit like this for 915G, and
339 * and yet it does have the related watermark in
340 * FW_BLC_SELF. What's going on?
341 */
342 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
343 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
344 I915_WRITE(INSTPM, val);
345 POSTING_READ(INSTPM);
346 } else {
347 return;
348 }
349
350 DRM_DEBUG_KMS("memory self-refresh is %s\n", enableddisabled(enable));
351}
352
353
354/*
355 * Latency for FIFO fetches is dependent on several factors:
356 * - memory configuration (speed, channels)
357 * - chipset
358 * - current MCH state
359 * It can be fairly high in some situations, so here we assume a fairly
360 * pessimal value. It's a tradeoff between extra memory fetches (if we
361 * set this value too high, the FIFO will fetch frequently to stay full)
362 * and power consumption (set it too low to save power and we might see
363 * FIFO underruns and display "flicker").
364 *
365 * A value of 5us seems to be a good balance; safe for very low end
366 * platforms but not overly aggressive on lower latency configs.
367 */
368static const int pessimal_latency_ns = 5000;
369
370#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
371 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
372
373static int vlv_get_fifo_size(struct drm_i915_private *dev_priv,
374 enum pipe pipe, int plane)
375{
376 int sprite0_start, sprite1_start, size;
377
378 switch (pipe) {
379 uint32_t dsparb, dsparb2, dsparb3;
380 case PIPE_A:
381 dsparb = I915_READ(DSPARB);
382 dsparb2 = I915_READ(DSPARB2);
383 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
384 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
385 break;
386 case PIPE_B:
387 dsparb = I915_READ(DSPARB);
388 dsparb2 = I915_READ(DSPARB2);
389 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
390 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
391 break;
392 case PIPE_C:
393 dsparb2 = I915_READ(DSPARB2);
394 dsparb3 = I915_READ(DSPARB3);
395 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
396 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
397 break;
398 default:
399 return 0;
400 }
401
402 switch (plane) {
403 case 0:
404 size = sprite0_start;
405 break;
406 case 1:
407 size = sprite1_start - sprite0_start;
408 break;
409 case 2:
410 size = 512 - 1 - sprite1_start;
411 break;
412 default:
413 return 0;
414 }
415
416 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
417 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
418 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
419 size);
420
421 return size;
422}
423
424static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
425{
426 uint32_t dsparb = I915_READ(DSPARB);
427 int size;
428
429 size = dsparb & 0x7f;
430 if (plane)
431 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
432
433 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
434 plane ? "B" : "A", size);
435
436 return size;
437}
438
439static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
440{
441 uint32_t dsparb = I915_READ(DSPARB);
442 int size;
443
444 size = dsparb & 0x1ff;
445 if (plane)
446 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
447 size >>= 1; /* Convert to cachelines */
448
449 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
450 plane ? "B" : "A", size);
451
452 return size;
453}
454
455static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
456{
457 uint32_t dsparb = I915_READ(DSPARB);
458 int size;
459
460 size = dsparb & 0x7f;
461 size >>= 2; /* Convert to cachelines */
462
463 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
464 plane ? "B" : "A",
465 size);
466
467 return size;
468}
469
470/* Pineview has different values for various configs */
471static const struct intel_watermark_params pineview_display_wm = {
472 .fifo_size = PINEVIEW_DISPLAY_FIFO,
473 .max_wm = PINEVIEW_MAX_WM,
474 .default_wm = PINEVIEW_DFT_WM,
475 .guard_size = PINEVIEW_GUARD_WM,
476 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
477};
478static const struct intel_watermark_params pineview_display_hplloff_wm = {
479 .fifo_size = PINEVIEW_DISPLAY_FIFO,
480 .max_wm = PINEVIEW_MAX_WM,
481 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
482 .guard_size = PINEVIEW_GUARD_WM,
483 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
484};
485static const struct intel_watermark_params pineview_cursor_wm = {
486 .fifo_size = PINEVIEW_CURSOR_FIFO,
487 .max_wm = PINEVIEW_CURSOR_MAX_WM,
488 .default_wm = PINEVIEW_CURSOR_DFT_WM,
489 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
490 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
491};
492static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
493 .fifo_size = PINEVIEW_CURSOR_FIFO,
494 .max_wm = PINEVIEW_CURSOR_MAX_WM,
495 .default_wm = PINEVIEW_CURSOR_DFT_WM,
496 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
497 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
498};
499static const struct intel_watermark_params g4x_wm_info = {
500 .fifo_size = G4X_FIFO_SIZE,
501 .max_wm = G4X_MAX_WM,
502 .default_wm = G4X_MAX_WM,
503 .guard_size = 2,
504 .cacheline_size = G4X_FIFO_LINE_SIZE,
505};
506static const struct intel_watermark_params g4x_cursor_wm_info = {
507 .fifo_size = I965_CURSOR_FIFO,
508 .max_wm = I965_CURSOR_MAX_WM,
509 .default_wm = I965_CURSOR_DFT_WM,
510 .guard_size = 2,
511 .cacheline_size = G4X_FIFO_LINE_SIZE,
512};
513static const struct intel_watermark_params i965_cursor_wm_info = {
514 .fifo_size = I965_CURSOR_FIFO,
515 .max_wm = I965_CURSOR_MAX_WM,
516 .default_wm = I965_CURSOR_DFT_WM,
517 .guard_size = 2,
518 .cacheline_size = I915_FIFO_LINE_SIZE,
519};
520static const struct intel_watermark_params i945_wm_info = {
521 .fifo_size = I945_FIFO_SIZE,
522 .max_wm = I915_MAX_WM,
523 .default_wm = 1,
524 .guard_size = 2,
525 .cacheline_size = I915_FIFO_LINE_SIZE,
526};
527static const struct intel_watermark_params i915_wm_info = {
528 .fifo_size = I915_FIFO_SIZE,
529 .max_wm = I915_MAX_WM,
530 .default_wm = 1,
531 .guard_size = 2,
532 .cacheline_size = I915_FIFO_LINE_SIZE,
533};
534static const struct intel_watermark_params i830_a_wm_info = {
535 .fifo_size = I855GM_FIFO_SIZE,
536 .max_wm = I915_MAX_WM,
537 .default_wm = 1,
538 .guard_size = 2,
539 .cacheline_size = I830_FIFO_LINE_SIZE,
540};
541static const struct intel_watermark_params i830_bc_wm_info = {
542 .fifo_size = I855GM_FIFO_SIZE,
543 .max_wm = I915_MAX_WM/2,
544 .default_wm = 1,
545 .guard_size = 2,
546 .cacheline_size = I830_FIFO_LINE_SIZE,
547};
548static const struct intel_watermark_params i845_wm_info = {
549 .fifo_size = I830_FIFO_SIZE,
550 .max_wm = I915_MAX_WM,
551 .default_wm = 1,
552 .guard_size = 2,
553 .cacheline_size = I830_FIFO_LINE_SIZE,
554};
555
556/**
557 * intel_calculate_wm - calculate watermark level
558 * @clock_in_khz: pixel clock
559 * @wm: chip FIFO params
560 * @cpp: bytes per pixel
561 * @latency_ns: memory latency for the platform
562 *
563 * Calculate the watermark level (the level at which the display plane will
564 * start fetching from memory again). Each chip has a different display
565 * FIFO size and allocation, so the caller needs to figure that out and pass
566 * in the correct intel_watermark_params structure.
567 *
568 * As the pixel clock runs, the FIFO will be drained at a rate that depends
569 * on the pixel size. When it reaches the watermark level, it'll start
570 * fetching FIFO line sized based chunks from memory until the FIFO fills
571 * past the watermark point. If the FIFO drains completely, a FIFO underrun
572 * will occur, and a display engine hang could result.
573 */
574static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
575 const struct intel_watermark_params *wm,
576 int fifo_size, int cpp,
577 unsigned long latency_ns)
578{
579 long entries_required, wm_size;
580
581 /*
582 * Note: we need to make sure we don't overflow for various clock &
583 * latency values.
584 * clocks go from a few thousand to several hundred thousand.
585 * latency is usually a few thousand
586 */
587 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
588 1000;
589 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
590
591 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
592
593 wm_size = fifo_size - (entries_required + wm->guard_size);
594
595 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
596
597 /* Don't promote wm_size to unsigned... */
598 if (wm_size > (long)wm->max_wm)
599 wm_size = wm->max_wm;
600 if (wm_size <= 0)
601 wm_size = wm->default_wm;
602
603 /*
604 * Bspec seems to indicate that the value shouldn't be lower than
605 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
606 * Lets go for 8 which is the burst size since certain platforms
607 * already use a hardcoded 8 (which is what the spec says should be
608 * done).
609 */
610 if (wm_size <= 8)
611 wm_size = 8;
612
613 return wm_size;
614}
615
616static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
617{
618 struct intel_crtc *crtc, *enabled = NULL;
619
620 for_each_intel_crtc(&dev_priv->drm, crtc) {
621 if (intel_crtc_active(crtc)) {
622 if (enabled)
623 return NULL;
624 enabled = crtc;
625 }
626 }
627
628 return enabled;
629}
630
631static void pineview_update_wm(struct intel_crtc *unused_crtc)
632{
633 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
634 struct intel_crtc *crtc;
635 const struct cxsr_latency *latency;
636 u32 reg;
637 unsigned long wm;
638
639 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
640 dev_priv->is_ddr3,
641 dev_priv->fsb_freq,
642 dev_priv->mem_freq);
643 if (!latency) {
644 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
645 intel_set_memory_cxsr(dev_priv, false);
646 return;
647 }
648
649 crtc = single_enabled_crtc(dev_priv);
650 if (crtc) {
651 const struct drm_display_mode *adjusted_mode =
652 &crtc->config->base.adjusted_mode;
653 const struct drm_framebuffer *fb =
654 crtc->base.primary->state->fb;
655 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
656 int clock = adjusted_mode->crtc_clock;
657
658 /* Display SR */
659 wm = intel_calculate_wm(clock, &pineview_display_wm,
660 pineview_display_wm.fifo_size,
661 cpp, latency->display_sr);
662 reg = I915_READ(DSPFW1);
663 reg &= ~DSPFW_SR_MASK;
664 reg |= FW_WM(wm, SR);
665 I915_WRITE(DSPFW1, reg);
666 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
667
668 /* cursor SR */
669 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
670 pineview_display_wm.fifo_size,
671 cpp, latency->cursor_sr);
672 reg = I915_READ(DSPFW3);
673 reg &= ~DSPFW_CURSOR_SR_MASK;
674 reg |= FW_WM(wm, CURSOR_SR);
675 I915_WRITE(DSPFW3, reg);
676
677 /* Display HPLL off SR */
678 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
679 pineview_display_hplloff_wm.fifo_size,
680 cpp, latency->display_hpll_disable);
681 reg = I915_READ(DSPFW3);
682 reg &= ~DSPFW_HPLL_SR_MASK;
683 reg |= FW_WM(wm, HPLL_SR);
684 I915_WRITE(DSPFW3, reg);
685
686 /* cursor HPLL off SR */
687 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
688 pineview_display_hplloff_wm.fifo_size,
689 cpp, latency->cursor_hpll_disable);
690 reg = I915_READ(DSPFW3);
691 reg &= ~DSPFW_HPLL_CURSOR_MASK;
692 reg |= FW_WM(wm, HPLL_CURSOR);
693 I915_WRITE(DSPFW3, reg);
694 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
695
696 intel_set_memory_cxsr(dev_priv, true);
697 } else {
698 intel_set_memory_cxsr(dev_priv, false);
699 }
700}
701
702static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
703 int plane,
704 const struct intel_watermark_params *display,
705 int display_latency_ns,
706 const struct intel_watermark_params *cursor,
707 int cursor_latency_ns,
708 int *plane_wm,
709 int *cursor_wm)
710{
711 struct intel_crtc *crtc;
712 const struct drm_display_mode *adjusted_mode;
713 const struct drm_framebuffer *fb;
714 int htotal, hdisplay, clock, cpp;
715 int line_time_us, line_count;
716 int entries, tlb_miss;
717
718 crtc = intel_get_crtc_for_plane(dev_priv, plane);
719 if (!intel_crtc_active(crtc)) {
720 *cursor_wm = cursor->guard_size;
721 *plane_wm = display->guard_size;
722 return false;
723 }
724
725 adjusted_mode = &crtc->config->base.adjusted_mode;
726 fb = crtc->base.primary->state->fb;
727 clock = adjusted_mode->crtc_clock;
728 htotal = adjusted_mode->crtc_htotal;
729 hdisplay = crtc->config->pipe_src_w;
730 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
731
732 /* Use the small buffer method to calculate plane watermark */
733 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
734 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
735 if (tlb_miss > 0)
736 entries += tlb_miss;
737 entries = DIV_ROUND_UP(entries, display->cacheline_size);
738 *plane_wm = entries + display->guard_size;
739 if (*plane_wm > (int)display->max_wm)
740 *plane_wm = display->max_wm;
741
742 /* Use the large buffer method to calculate cursor watermark */
743 line_time_us = max(htotal * 1000 / clock, 1);
744 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
745 entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
746 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
747 if (tlb_miss > 0)
748 entries += tlb_miss;
749 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
750 *cursor_wm = entries + cursor->guard_size;
751 if (*cursor_wm > (int)cursor->max_wm)
752 *cursor_wm = (int)cursor->max_wm;
753
754 return true;
755}
756
757/*
758 * Check the wm result.
759 *
760 * If any calculated watermark values is larger than the maximum value that
761 * can be programmed into the associated watermark register, that watermark
762 * must be disabled.
763 */
764static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
765 int display_wm, int cursor_wm,
766 const struct intel_watermark_params *display,
767 const struct intel_watermark_params *cursor)
768{
769 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
770 display_wm, cursor_wm);
771
772 if (display_wm > display->max_wm) {
773 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
774 display_wm, display->max_wm);
775 return false;
776 }
777
778 if (cursor_wm > cursor->max_wm) {
779 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
780 cursor_wm, cursor->max_wm);
781 return false;
782 }
783
784 if (!(display_wm || cursor_wm)) {
785 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
786 return false;
787 }
788
789 return true;
790}
791
792static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
793 int plane,
794 int latency_ns,
795 const struct intel_watermark_params *display,
796 const struct intel_watermark_params *cursor,
797 int *display_wm, int *cursor_wm)
798{
799 struct intel_crtc *crtc;
800 const struct drm_display_mode *adjusted_mode;
801 const struct drm_framebuffer *fb;
802 int hdisplay, htotal, cpp, clock;
803 unsigned long line_time_us;
804 int line_count, line_size;
805 int small, large;
806 int entries;
807
808 if (!latency_ns) {
809 *display_wm = *cursor_wm = 0;
810 return false;
811 }
812
813 crtc = intel_get_crtc_for_plane(dev_priv, plane);
814 adjusted_mode = &crtc->config->base.adjusted_mode;
815 fb = crtc->base.primary->state->fb;
816 clock = adjusted_mode->crtc_clock;
817 htotal = adjusted_mode->crtc_htotal;
818 hdisplay = crtc->config->pipe_src_w;
819 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
820
821 line_time_us = max(htotal * 1000 / clock, 1);
822 line_count = (latency_ns / line_time_us + 1000) / 1000;
823 line_size = hdisplay * cpp;
824
825 /* Use the minimum of the small and large buffer method for primary */
826 small = ((clock * cpp / 1000) * latency_ns) / 1000;
827 large = line_count * line_size;
828
829 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
830 *display_wm = entries + display->guard_size;
831
832 /* calculate the self-refresh watermark for display cursor */
833 entries = line_count * cpp * crtc->base.cursor->state->crtc_w;
834 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
835 *cursor_wm = entries + cursor->guard_size;
836
837 return g4x_check_srwm(dev_priv,
838 *display_wm, *cursor_wm,
839 display, cursor);
840}
841
842#define FW_WM_VLV(value, plane) \
843 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
844
845static void vlv_write_wm_values(struct intel_crtc *crtc,
846 const struct vlv_wm_values *wm)
847{
848 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
849 enum pipe pipe = crtc->pipe;
850
851 I915_WRITE(VLV_DDL(pipe),
852 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
853 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
854 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
855 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
856
857 I915_WRITE(DSPFW1,
858 FW_WM(wm->sr.plane, SR) |
859 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
860 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
861 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
862 I915_WRITE(DSPFW2,
863 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
864 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
865 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
866 I915_WRITE(DSPFW3,
867 FW_WM(wm->sr.cursor, CURSOR_SR));
868
869 if (IS_CHERRYVIEW(dev_priv)) {
870 I915_WRITE(DSPFW7_CHV,
871 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
872 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
873 I915_WRITE(DSPFW8_CHV,
874 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
875 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
876 I915_WRITE(DSPFW9_CHV,
877 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
878 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
879 I915_WRITE(DSPHOWM,
880 FW_WM(wm->sr.plane >> 9, SR_HI) |
881 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
882 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
883 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
884 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
885 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
886 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
887 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
888 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
889 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
890 } else {
891 I915_WRITE(DSPFW7,
892 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
893 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
894 I915_WRITE(DSPHOWM,
895 FW_WM(wm->sr.plane >> 9, SR_HI) |
896 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
897 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
898 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
899 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
900 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
901 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
902 }
903
904 /* zero (unused) WM1 watermarks */
905 I915_WRITE(DSPFW4, 0);
906 I915_WRITE(DSPFW5, 0);
907 I915_WRITE(DSPFW6, 0);
908 I915_WRITE(DSPHOWM1, 0);
909
910 POSTING_READ(DSPFW1);
911}
912
913#undef FW_WM_VLV
914
915enum vlv_wm_level {
916 VLV_WM_LEVEL_PM2,
917 VLV_WM_LEVEL_PM5,
918 VLV_WM_LEVEL_DDR_DVFS,
919};
920
921/* latency must be in 0.1us units. */
922static unsigned int vlv_wm_method2(unsigned int pixel_rate,
923 unsigned int pipe_htotal,
924 unsigned int horiz_pixels,
925 unsigned int cpp,
926 unsigned int latency)
927{
928 unsigned int ret;
929
930 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
931 ret = (ret + 1) * horiz_pixels * cpp;
932 ret = DIV_ROUND_UP(ret, 64);
933
934 return ret;
935}
936
937static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
938{
939 /* all latencies in usec */
940 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
941
942 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
943
944 if (IS_CHERRYVIEW(dev_priv)) {
945 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
946 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
947
948 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
949 }
950}
951
952static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
953 struct intel_crtc *crtc,
954 const struct intel_plane_state *state,
955 int level)
956{
957 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
958 int clock, htotal, cpp, width, wm;
959
960 if (dev_priv->wm.pri_latency[level] == 0)
961 return USHRT_MAX;
962
963 if (!state->base.visible)
964 return 0;
965
966 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
967 clock = crtc->config->base.adjusted_mode.crtc_clock;
968 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
969 width = crtc->config->pipe_src_w;
970 if (WARN_ON(htotal == 0))
971 htotal = 1;
972
973 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
974 /*
975 * FIXME the formula gives values that are
976 * too big for the cursor FIFO, and hence we
977 * would never be able to use cursors. For
978 * now just hardcode the watermark.
979 */
980 wm = 63;
981 } else {
982 wm = vlv_wm_method2(clock, htotal, width, cpp,
983 dev_priv->wm.pri_latency[level] * 10);
984 }
985
986 return min_t(int, wm, USHRT_MAX);
987}
988
989static void vlv_compute_fifo(struct intel_crtc *crtc)
990{
991 struct drm_device *dev = crtc->base.dev;
992 struct vlv_wm_state *wm_state = &crtc->wm_state;
993 struct intel_plane *plane;
994 unsigned int total_rate = 0;
995 const int fifo_size = 512 - 1;
996 int fifo_extra, fifo_left = fifo_size;
997
998 for_each_intel_plane_on_crtc(dev, crtc, plane) {
999 struct intel_plane_state *state =
1000 to_intel_plane_state(plane->base.state);
1001
1002 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1003 continue;
1004
1005 if (state->base.visible) {
1006 wm_state->num_active_planes++;
1007 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1008 }
1009 }
1010
1011 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1012 struct intel_plane_state *state =
1013 to_intel_plane_state(plane->base.state);
1014 unsigned int rate;
1015
1016 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1017 plane->wm.fifo_size = 63;
1018 continue;
1019 }
1020
1021 if (!state->base.visible) {
1022 plane->wm.fifo_size = 0;
1023 continue;
1024 }
1025
1026 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1027 plane->wm.fifo_size = fifo_size * rate / total_rate;
1028 fifo_left -= plane->wm.fifo_size;
1029 }
1030
1031 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1032
1033 /* spread the remainder evenly */
1034 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1035 int plane_extra;
1036
1037 if (fifo_left == 0)
1038 break;
1039
1040 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1041 continue;
1042
1043 /* give it all to the first plane if none are active */
1044 if (plane->wm.fifo_size == 0 &&
1045 wm_state->num_active_planes)
1046 continue;
1047
1048 plane_extra = min(fifo_extra, fifo_left);
1049 plane->wm.fifo_size += plane_extra;
1050 fifo_left -= plane_extra;
1051 }
1052
1053 WARN_ON(fifo_left != 0);
1054}
1055
1056static void vlv_invert_wms(struct intel_crtc *crtc)
1057{
1058 struct vlv_wm_state *wm_state = &crtc->wm_state;
1059 int level;
1060
1061 for (level = 0; level < wm_state->num_levels; level++) {
1062 struct drm_device *dev = crtc->base.dev;
1063 const int sr_fifo_size =
1064 INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
1065 struct intel_plane *plane;
1066
1067 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1068 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1069
1070 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1071 switch (plane->base.type) {
1072 int sprite;
1073 case DRM_PLANE_TYPE_CURSOR:
1074 wm_state->wm[level].cursor = plane->wm.fifo_size -
1075 wm_state->wm[level].cursor;
1076 break;
1077 case DRM_PLANE_TYPE_PRIMARY:
1078 wm_state->wm[level].primary = plane->wm.fifo_size -
1079 wm_state->wm[level].primary;
1080 break;
1081 case DRM_PLANE_TYPE_OVERLAY:
1082 sprite = plane->plane;
1083 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1084 wm_state->wm[level].sprite[sprite];
1085 break;
1086 }
1087 }
1088 }
1089}
1090
1091static void vlv_compute_wm(struct intel_crtc *crtc)
1092{
1093 struct drm_device *dev = crtc->base.dev;
1094 struct drm_i915_private *dev_priv = to_i915(dev);
1095 struct vlv_wm_state *wm_state = &crtc->wm_state;
1096 struct intel_plane *plane;
1097 int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1098 int level;
1099
1100 memset(wm_state, 0, sizeof(*wm_state));
1101
1102 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1103 wm_state->num_levels = dev_priv->wm.max_level + 1;
1104
1105 wm_state->num_active_planes = 0;
1106
1107 vlv_compute_fifo(crtc);
1108
1109 if (wm_state->num_active_planes != 1)
1110 wm_state->cxsr = false;
1111
1112 if (wm_state->cxsr) {
1113 for (level = 0; level < wm_state->num_levels; level++) {
1114 wm_state->sr[level].plane = sr_fifo_size;
1115 wm_state->sr[level].cursor = 63;
1116 }
1117 }
1118
1119 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1120 struct intel_plane_state *state =
1121 to_intel_plane_state(plane->base.state);
1122
1123 if (!state->base.visible)
1124 continue;
1125
1126 /* normal watermarks */
1127 for (level = 0; level < wm_state->num_levels; level++) {
1128 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1129 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1130
1131 /* hack */
1132 if (WARN_ON(level == 0 && wm > max_wm))
1133 wm = max_wm;
1134
1135 if (wm > plane->wm.fifo_size)
1136 break;
1137
1138 switch (plane->base.type) {
1139 int sprite;
1140 case DRM_PLANE_TYPE_CURSOR:
1141 wm_state->wm[level].cursor = wm;
1142 break;
1143 case DRM_PLANE_TYPE_PRIMARY:
1144 wm_state->wm[level].primary = wm;
1145 break;
1146 case DRM_PLANE_TYPE_OVERLAY:
1147 sprite = plane->plane;
1148 wm_state->wm[level].sprite[sprite] = wm;
1149 break;
1150 }
1151 }
1152
1153 wm_state->num_levels = level;
1154
1155 if (!wm_state->cxsr)
1156 continue;
1157
1158 /* maxfifo watermarks */
1159 switch (plane->base.type) {
1160 int sprite, level;
1161 case DRM_PLANE_TYPE_CURSOR:
1162 for (level = 0; level < wm_state->num_levels; level++)
1163 wm_state->sr[level].cursor =
1164 wm_state->wm[level].cursor;
1165 break;
1166 case DRM_PLANE_TYPE_PRIMARY:
1167 for (level = 0; level < wm_state->num_levels; level++)
1168 wm_state->sr[level].plane =
1169 min(wm_state->sr[level].plane,
1170 wm_state->wm[level].primary);
1171 break;
1172 case DRM_PLANE_TYPE_OVERLAY:
1173 sprite = plane->plane;
1174 for (level = 0; level < wm_state->num_levels; level++)
1175 wm_state->sr[level].plane =
1176 min(wm_state->sr[level].plane,
1177 wm_state->wm[level].sprite[sprite]);
1178 break;
1179 }
1180 }
1181
1182 /* clear any (partially) filled invalid levels */
1183 for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
1184 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1185 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1186 }
1187
1188 vlv_invert_wms(crtc);
1189}
1190
1191#define VLV_FIFO(plane, value) \
1192 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1193
1194static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1195{
1196 struct drm_device *dev = crtc->base.dev;
1197 struct drm_i915_private *dev_priv = to_i915(dev);
1198 struct intel_plane *plane;
1199 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1200
1201 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1202 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1203 WARN_ON(plane->wm.fifo_size != 63);
1204 continue;
1205 }
1206
1207 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1208 sprite0_start = plane->wm.fifo_size;
1209 else if (plane->plane == 0)
1210 sprite1_start = sprite0_start + plane->wm.fifo_size;
1211 else
1212 fifo_size = sprite1_start + plane->wm.fifo_size;
1213 }
1214
1215 WARN_ON(fifo_size != 512 - 1);
1216
1217 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1218 pipe_name(crtc->pipe), sprite0_start,
1219 sprite1_start, fifo_size);
1220
1221 switch (crtc->pipe) {
1222 uint32_t dsparb, dsparb2, dsparb3;
1223 case PIPE_A:
1224 dsparb = I915_READ(DSPARB);
1225 dsparb2 = I915_READ(DSPARB2);
1226
1227 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1228 VLV_FIFO(SPRITEB, 0xff));
1229 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1230 VLV_FIFO(SPRITEB, sprite1_start));
1231
1232 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1233 VLV_FIFO(SPRITEB_HI, 0x1));
1234 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1235 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1236
1237 I915_WRITE(DSPARB, dsparb);
1238 I915_WRITE(DSPARB2, dsparb2);
1239 break;
1240 case PIPE_B:
1241 dsparb = I915_READ(DSPARB);
1242 dsparb2 = I915_READ(DSPARB2);
1243
1244 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1245 VLV_FIFO(SPRITED, 0xff));
1246 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1247 VLV_FIFO(SPRITED, sprite1_start));
1248
1249 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1250 VLV_FIFO(SPRITED_HI, 0xff));
1251 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1252 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1253
1254 I915_WRITE(DSPARB, dsparb);
1255 I915_WRITE(DSPARB2, dsparb2);
1256 break;
1257 case PIPE_C:
1258 dsparb3 = I915_READ(DSPARB3);
1259 dsparb2 = I915_READ(DSPARB2);
1260
1261 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1262 VLV_FIFO(SPRITEF, 0xff));
1263 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1264 VLV_FIFO(SPRITEF, sprite1_start));
1265
1266 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1267 VLV_FIFO(SPRITEF_HI, 0xff));
1268 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1269 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1270
1271 I915_WRITE(DSPARB3, dsparb3);
1272 I915_WRITE(DSPARB2, dsparb2);
1273 break;
1274 default:
1275 break;
1276 }
1277}
1278
1279#undef VLV_FIFO
1280
1281static void vlv_merge_wm(struct drm_device *dev,
1282 struct vlv_wm_values *wm)
1283{
1284 struct intel_crtc *crtc;
1285 int num_active_crtcs = 0;
1286
1287 wm->level = to_i915(dev)->wm.max_level;
1288 wm->cxsr = true;
1289
1290 for_each_intel_crtc(dev, crtc) {
1291 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1292
1293 if (!crtc->active)
1294 continue;
1295
1296 if (!wm_state->cxsr)
1297 wm->cxsr = false;
1298
1299 num_active_crtcs++;
1300 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1301 }
1302
1303 if (num_active_crtcs != 1)
1304 wm->cxsr = false;
1305
1306 if (num_active_crtcs > 1)
1307 wm->level = VLV_WM_LEVEL_PM2;
1308
1309 for_each_intel_crtc(dev, crtc) {
1310 struct vlv_wm_state *wm_state = &crtc->wm_state;
1311 enum pipe pipe = crtc->pipe;
1312
1313 if (!crtc->active)
1314 continue;
1315
1316 wm->pipe[pipe] = wm_state->wm[wm->level];
1317 if (wm->cxsr)
1318 wm->sr = wm_state->sr[wm->level];
1319
1320 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1321 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1322 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1323 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1324 }
1325}
1326
1327static void vlv_update_wm(struct intel_crtc *crtc)
1328{
1329 struct drm_device *dev = crtc->base.dev;
1330 struct drm_i915_private *dev_priv = to_i915(dev);
1331 enum pipe pipe = crtc->pipe;
1332 struct vlv_wm_values wm = {};
1333
1334 vlv_compute_wm(crtc);
1335 vlv_merge_wm(dev, &wm);
1336
1337 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1338 /* FIXME should be part of crtc atomic commit */
1339 vlv_pipe_set_fifo_size(crtc);
1340 return;
1341 }
1342
1343 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1344 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1345 chv_set_memory_dvfs(dev_priv, false);
1346
1347 if (wm.level < VLV_WM_LEVEL_PM5 &&
1348 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1349 chv_set_memory_pm5(dev_priv, false);
1350
1351 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1352 intel_set_memory_cxsr(dev_priv, false);
1353
1354 /* FIXME should be part of crtc atomic commit */
1355 vlv_pipe_set_fifo_size(crtc);
1356
1357 vlv_write_wm_values(crtc, &wm);
1358
1359 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1360 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1361 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1362 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1363 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1364
1365 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1366 intel_set_memory_cxsr(dev_priv, true);
1367
1368 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1369 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1370 chv_set_memory_pm5(dev_priv, true);
1371
1372 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1373 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1374 chv_set_memory_dvfs(dev_priv, true);
1375
1376 dev_priv->wm.vlv = wm;
1377}
1378
1379#define single_plane_enabled(mask) is_power_of_2(mask)
1380
1381static void g4x_update_wm(struct intel_crtc *crtc)
1382{
1383 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1384 static const int sr_latency_ns = 12000;
1385 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1386 int plane_sr, cursor_sr;
1387 unsigned int enabled = 0;
1388 bool cxsr_enabled;
1389
1390 if (g4x_compute_wm0(dev_priv, PIPE_A,
1391 &g4x_wm_info, pessimal_latency_ns,
1392 &g4x_cursor_wm_info, pessimal_latency_ns,
1393 &planea_wm, &cursora_wm))
1394 enabled |= 1 << PIPE_A;
1395
1396 if (g4x_compute_wm0(dev_priv, PIPE_B,
1397 &g4x_wm_info, pessimal_latency_ns,
1398 &g4x_cursor_wm_info, pessimal_latency_ns,
1399 &planeb_wm, &cursorb_wm))
1400 enabled |= 1 << PIPE_B;
1401
1402 if (single_plane_enabled(enabled) &&
1403 g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
1404 sr_latency_ns,
1405 &g4x_wm_info,
1406 &g4x_cursor_wm_info,
1407 &plane_sr, &cursor_sr)) {
1408 cxsr_enabled = true;
1409 } else {
1410 cxsr_enabled = false;
1411 intel_set_memory_cxsr(dev_priv, false);
1412 plane_sr = cursor_sr = 0;
1413 }
1414
1415 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1416 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1417 planea_wm, cursora_wm,
1418 planeb_wm, cursorb_wm,
1419 plane_sr, cursor_sr);
1420
1421 I915_WRITE(DSPFW1,
1422 FW_WM(plane_sr, SR) |
1423 FW_WM(cursorb_wm, CURSORB) |
1424 FW_WM(planeb_wm, PLANEB) |
1425 FW_WM(planea_wm, PLANEA));
1426 I915_WRITE(DSPFW2,
1427 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1428 FW_WM(cursora_wm, CURSORA));
1429 /* HPLL off in SR has some issues on G4x... disable it */
1430 I915_WRITE(DSPFW3,
1431 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1432 FW_WM(cursor_sr, CURSOR_SR));
1433
1434 if (cxsr_enabled)
1435 intel_set_memory_cxsr(dev_priv, true);
1436}
1437
1438static void i965_update_wm(struct intel_crtc *unused_crtc)
1439{
1440 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1441 struct intel_crtc *crtc;
1442 int srwm = 1;
1443 int cursor_sr = 16;
1444 bool cxsr_enabled;
1445
1446 /* Calc sr entries for one plane configs */
1447 crtc = single_enabled_crtc(dev_priv);
1448 if (crtc) {
1449 /* self-refresh has much higher latency */
1450 static const int sr_latency_ns = 12000;
1451 const struct drm_display_mode *adjusted_mode =
1452 &crtc->config->base.adjusted_mode;
1453 const struct drm_framebuffer *fb =
1454 crtc->base.primary->state->fb;
1455 int clock = adjusted_mode->crtc_clock;
1456 int htotal = adjusted_mode->crtc_htotal;
1457 int hdisplay = crtc->config->pipe_src_w;
1458 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1459 unsigned long line_time_us;
1460 int entries;
1461
1462 line_time_us = max(htotal * 1000 / clock, 1);
1463
1464 /* Use ns/us then divide to preserve precision */
1465 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1466 cpp * hdisplay;
1467 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1468 srwm = I965_FIFO_SIZE - entries;
1469 if (srwm < 0)
1470 srwm = 1;
1471 srwm &= 0x1ff;
1472 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1473 entries, srwm);
1474
1475 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1476 cpp * crtc->base.cursor->state->crtc_w;
1477 entries = DIV_ROUND_UP(entries,
1478 i965_cursor_wm_info.cacheline_size);
1479 cursor_sr = i965_cursor_wm_info.fifo_size -
1480 (entries + i965_cursor_wm_info.guard_size);
1481
1482 if (cursor_sr > i965_cursor_wm_info.max_wm)
1483 cursor_sr = i965_cursor_wm_info.max_wm;
1484
1485 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1486 "cursor %d\n", srwm, cursor_sr);
1487
1488 cxsr_enabled = true;
1489 } else {
1490 cxsr_enabled = false;
1491 /* Turn off self refresh if both pipes are enabled */
1492 intel_set_memory_cxsr(dev_priv, false);
1493 }
1494
1495 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1496 srwm);
1497
1498 /* 965 has limitations... */
1499 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1500 FW_WM(8, CURSORB) |
1501 FW_WM(8, PLANEB) |
1502 FW_WM(8, PLANEA));
1503 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1504 FW_WM(8, PLANEC_OLD));
1505 /* update cursor SR watermark */
1506 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1507
1508 if (cxsr_enabled)
1509 intel_set_memory_cxsr(dev_priv, true);
1510}
1511
1512#undef FW_WM
1513
1514static void i9xx_update_wm(struct intel_crtc *unused_crtc)
1515{
1516 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1517 const struct intel_watermark_params *wm_info;
1518 uint32_t fwater_lo;
1519 uint32_t fwater_hi;
1520 int cwm, srwm = 1;
1521 int fifo_size;
1522 int planea_wm, planeb_wm;
1523 struct intel_crtc *crtc, *enabled = NULL;
1524
1525 if (IS_I945GM(dev_priv))
1526 wm_info = &i945_wm_info;
1527 else if (!IS_GEN2(dev_priv))
1528 wm_info = &i915_wm_info;
1529 else
1530 wm_info = &i830_a_wm_info;
1531
1532 fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
1533 crtc = intel_get_crtc_for_plane(dev_priv, 0);
1534 if (intel_crtc_active(crtc)) {
1535 const struct drm_display_mode *adjusted_mode =
1536 &crtc->config->base.adjusted_mode;
1537 const struct drm_framebuffer *fb =
1538 crtc->base.primary->state->fb;
1539 int cpp;
1540
1541 if (IS_GEN2(dev_priv))
1542 cpp = 4;
1543 else
1544 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1545
1546 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1547 wm_info, fifo_size, cpp,
1548 pessimal_latency_ns);
1549 enabled = crtc;
1550 } else {
1551 planea_wm = fifo_size - wm_info->guard_size;
1552 if (planea_wm > (long)wm_info->max_wm)
1553 planea_wm = wm_info->max_wm;
1554 }
1555
1556 if (IS_GEN2(dev_priv))
1557 wm_info = &i830_bc_wm_info;
1558
1559 fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
1560 crtc = intel_get_crtc_for_plane(dev_priv, 1);
1561 if (intel_crtc_active(crtc)) {
1562 const struct drm_display_mode *adjusted_mode =
1563 &crtc->config->base.adjusted_mode;
1564 const struct drm_framebuffer *fb =
1565 crtc->base.primary->state->fb;
1566 int cpp;
1567
1568 if (IS_GEN2(dev_priv))
1569 cpp = 4;
1570 else
1571 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1572
1573 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1574 wm_info, fifo_size, cpp,
1575 pessimal_latency_ns);
1576 if (enabled == NULL)
1577 enabled = crtc;
1578 else
1579 enabled = NULL;
1580 } else {
1581 planeb_wm = fifo_size - wm_info->guard_size;
1582 if (planeb_wm > (long)wm_info->max_wm)
1583 planeb_wm = wm_info->max_wm;
1584 }
1585
1586 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1587
1588 if (IS_I915GM(dev_priv) && enabled) {
1589 struct drm_i915_gem_object *obj;
1590
1591 obj = intel_fb_obj(enabled->base.primary->state->fb);
1592
1593 /* self-refresh seems busted with untiled */
1594 if (!i915_gem_object_is_tiled(obj))
1595 enabled = NULL;
1596 }
1597
1598 /*
1599 * Overlay gets an aggressive default since video jitter is bad.
1600 */
1601 cwm = 2;
1602
1603 /* Play safe and disable self-refresh before adjusting watermarks. */
1604 intel_set_memory_cxsr(dev_priv, false);
1605
1606 /* Calc sr entries for one plane configs */
1607 if (HAS_FW_BLC(dev_priv) && enabled) {
1608 /* self-refresh has much higher latency */
1609 static const int sr_latency_ns = 6000;
1610 const struct drm_display_mode *adjusted_mode =
1611 &enabled->config->base.adjusted_mode;
1612 const struct drm_framebuffer *fb =
1613 enabled->base.primary->state->fb;
1614 int clock = adjusted_mode->crtc_clock;
1615 int htotal = adjusted_mode->crtc_htotal;
1616 int hdisplay = enabled->config->pipe_src_w;
1617 int cpp;
1618 unsigned long line_time_us;
1619 int entries;
1620
1621 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
1622 cpp = 4;
1623 else
1624 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1625
1626 line_time_us = max(htotal * 1000 / clock, 1);
1627
1628 /* Use ns/us then divide to preserve precision */
1629 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1630 cpp * hdisplay;
1631 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1632 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1633 srwm = wm_info->fifo_size - entries;
1634 if (srwm < 0)
1635 srwm = 1;
1636
1637 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1638 I915_WRITE(FW_BLC_SELF,
1639 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1640 else
1641 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1642 }
1643
1644 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1645 planea_wm, planeb_wm, cwm, srwm);
1646
1647 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1648 fwater_hi = (cwm & 0x1f);
1649
1650 /* Set request length to 8 cachelines per fetch */
1651 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1652 fwater_hi = fwater_hi | (1 << 8);
1653
1654 I915_WRITE(FW_BLC, fwater_lo);
1655 I915_WRITE(FW_BLC2, fwater_hi);
1656
1657 if (enabled)
1658 intel_set_memory_cxsr(dev_priv, true);
1659}
1660
1661static void i845_update_wm(struct intel_crtc *unused_crtc)
1662{
1663 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1664 struct intel_crtc *crtc;
1665 const struct drm_display_mode *adjusted_mode;
1666 uint32_t fwater_lo;
1667 int planea_wm;
1668
1669 crtc = single_enabled_crtc(dev_priv);
1670 if (crtc == NULL)
1671 return;
1672
1673 adjusted_mode = &crtc->config->base.adjusted_mode;
1674 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1675 &i845_wm_info,
1676 dev_priv->display.get_fifo_size(dev_priv, 0),
1677 4, pessimal_latency_ns);
1678 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1679 fwater_lo |= (3<<8) | planea_wm;
1680
1681 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1682
1683 I915_WRITE(FW_BLC, fwater_lo);
1684}
1685
1686uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1687{
1688 uint32_t pixel_rate;
1689
1690 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1691
1692 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1693 * adjust the pixel_rate here. */
1694
1695 if (pipe_config->pch_pfit.enabled) {
1696 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1697 uint32_t pfit_size = pipe_config->pch_pfit.size;
1698
1699 pipe_w = pipe_config->pipe_src_w;
1700 pipe_h = pipe_config->pipe_src_h;
1701
1702 pfit_w = (pfit_size >> 16) & 0xFFFF;
1703 pfit_h = pfit_size & 0xFFFF;
1704 if (pipe_w < pfit_w)
1705 pipe_w = pfit_w;
1706 if (pipe_h < pfit_h)
1707 pipe_h = pfit_h;
1708
1709 if (WARN_ON(!pfit_w || !pfit_h))
1710 return pixel_rate;
1711
1712 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1713 pfit_w * pfit_h);
1714 }
1715
1716 return pixel_rate;
1717}
1718
1719/* latency must be in 0.1us units. */
1720static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1721{
1722 uint64_t ret;
1723
1724 if (WARN(latency == 0, "Latency value missing\n"))
1725 return UINT_MAX;
1726
1727 ret = (uint64_t) pixel_rate * cpp * latency;
1728 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1729
1730 return ret;
1731}
1732
1733/* latency must be in 0.1us units. */
1734static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1735 uint32_t horiz_pixels, uint8_t cpp,
1736 uint32_t latency)
1737{
1738 uint32_t ret;
1739
1740 if (WARN(latency == 0, "Latency value missing\n"))
1741 return UINT_MAX;
1742 if (WARN_ON(!pipe_htotal))
1743 return UINT_MAX;
1744
1745 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1746 ret = (ret + 1) * horiz_pixels * cpp;
1747 ret = DIV_ROUND_UP(ret, 64) + 2;
1748 return ret;
1749}
1750
1751static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1752 uint8_t cpp)
1753{
1754 /*
1755 * Neither of these should be possible since this function shouldn't be
1756 * called if the CRTC is off or the plane is invisible. But let's be
1757 * extra paranoid to avoid a potential divide-by-zero if we screw up
1758 * elsewhere in the driver.
1759 */
1760 if (WARN_ON(!cpp))
1761 return 0;
1762 if (WARN_ON(!horiz_pixels))
1763 return 0;
1764
1765 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1766}
1767
1768struct ilk_wm_maximums {
1769 uint16_t pri;
1770 uint16_t spr;
1771 uint16_t cur;
1772 uint16_t fbc;
1773};
1774
1775/*
1776 * For both WM_PIPE and WM_LP.
1777 * mem_value must be in 0.1us units.
1778 */
1779static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1780 const struct intel_plane_state *pstate,
1781 uint32_t mem_value,
1782 bool is_lp)
1783{
1784 int cpp = pstate->base.fb ?
1785 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1786 uint32_t method1, method2;
1787
1788 if (!cstate->base.active || !pstate->base.visible)
1789 return 0;
1790
1791 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1792
1793 if (!is_lp)
1794 return method1;
1795
1796 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1797 cstate->base.adjusted_mode.crtc_htotal,
1798 drm_rect_width(&pstate->base.dst),
1799 cpp, mem_value);
1800
1801 return min(method1, method2);
1802}
1803
1804/*
1805 * For both WM_PIPE and WM_LP.
1806 * mem_value must be in 0.1us units.
1807 */
1808static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1809 const struct intel_plane_state *pstate,
1810 uint32_t mem_value)
1811{
1812 int cpp = pstate->base.fb ?
1813 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1814 uint32_t method1, method2;
1815
1816 if (!cstate->base.active || !pstate->base.visible)
1817 return 0;
1818
1819 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1820 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1821 cstate->base.adjusted_mode.crtc_htotal,
1822 drm_rect_width(&pstate->base.dst),
1823 cpp, mem_value);
1824 return min(method1, method2);
1825}
1826
1827/*
1828 * For both WM_PIPE and WM_LP.
1829 * mem_value must be in 0.1us units.
1830 */
1831static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1832 const struct intel_plane_state *pstate,
1833 uint32_t mem_value)
1834{
1835 /*
1836 * We treat the cursor plane as always-on for the purposes of watermark
1837 * calculation. Until we have two-stage watermark programming merged,
1838 * this is necessary to avoid flickering.
1839 */
1840 int cpp = 4;
1841 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
1842
1843 if (!cstate->base.active)
1844 return 0;
1845
1846 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1847 cstate->base.adjusted_mode.crtc_htotal,
1848 width, cpp, mem_value);
1849}
1850
1851/* Only for WM_LP. */
1852static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1853 const struct intel_plane_state *pstate,
1854 uint32_t pri_val)
1855{
1856 int cpp = pstate->base.fb ?
1857 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1858
1859 if (!cstate->base.active || !pstate->base.visible)
1860 return 0;
1861
1862 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
1863}
1864
1865static unsigned int
1866ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
1867{
1868 if (INTEL_GEN(dev_priv) >= 8)
1869 return 3072;
1870 else if (INTEL_GEN(dev_priv) >= 7)
1871 return 768;
1872 else
1873 return 512;
1874}
1875
1876static unsigned int
1877ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
1878 int level, bool is_sprite)
1879{
1880 if (INTEL_GEN(dev_priv) >= 8)
1881 /* BDW primary/sprite plane watermarks */
1882 return level == 0 ? 255 : 2047;
1883 else if (INTEL_GEN(dev_priv) >= 7)
1884 /* IVB/HSW primary/sprite plane watermarks */
1885 return level == 0 ? 127 : 1023;
1886 else if (!is_sprite)
1887 /* ILK/SNB primary plane watermarks */
1888 return level == 0 ? 127 : 511;
1889 else
1890 /* ILK/SNB sprite plane watermarks */
1891 return level == 0 ? 63 : 255;
1892}
1893
1894static unsigned int
1895ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
1896{
1897 if (INTEL_GEN(dev_priv) >= 7)
1898 return level == 0 ? 63 : 255;
1899 else
1900 return level == 0 ? 31 : 63;
1901}
1902
1903static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
1904{
1905 if (INTEL_GEN(dev_priv) >= 8)
1906 return 31;
1907 else
1908 return 15;
1909}
1910
1911/* Calculate the maximum primary/sprite plane watermark */
1912static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1913 int level,
1914 const struct intel_wm_config *config,
1915 enum intel_ddb_partitioning ddb_partitioning,
1916 bool is_sprite)
1917{
1918 struct drm_i915_private *dev_priv = to_i915(dev);
1919 unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
1920
1921 /* if sprites aren't enabled, sprites get nothing */
1922 if (is_sprite && !config->sprites_enabled)
1923 return 0;
1924
1925 /* HSW allows LP1+ watermarks even with multiple pipes */
1926 if (level == 0 || config->num_pipes_active > 1) {
1927 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
1928
1929 /*
1930 * For some reason the non self refresh
1931 * FIFO size is only half of the self
1932 * refresh FIFO size on ILK/SNB.
1933 */
1934 if (INTEL_GEN(dev_priv) <= 6)
1935 fifo_size /= 2;
1936 }
1937
1938 if (config->sprites_enabled) {
1939 /* level 0 is always calculated with 1:1 split */
1940 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1941 if (is_sprite)
1942 fifo_size *= 5;
1943 fifo_size /= 6;
1944 } else {
1945 fifo_size /= 2;
1946 }
1947 }
1948
1949 /* clamp to max that the registers can hold */
1950 return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
1951}
1952
1953/* Calculate the maximum cursor plane watermark */
1954static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1955 int level,
1956 const struct intel_wm_config *config)
1957{
1958 /* HSW LP1+ watermarks w/ multiple pipes */
1959 if (level > 0 && config->num_pipes_active > 1)
1960 return 64;
1961
1962 /* otherwise just report max that registers can hold */
1963 return ilk_cursor_wm_reg_max(to_i915(dev), level);
1964}
1965
1966static void ilk_compute_wm_maximums(const struct drm_device *dev,
1967 int level,
1968 const struct intel_wm_config *config,
1969 enum intel_ddb_partitioning ddb_partitioning,
1970 struct ilk_wm_maximums *max)
1971{
1972 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1973 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1974 max->cur = ilk_cursor_wm_max(dev, level, config);
1975 max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
1976}
1977
1978static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
1979 int level,
1980 struct ilk_wm_maximums *max)
1981{
1982 max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
1983 max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
1984 max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
1985 max->fbc = ilk_fbc_wm_reg_max(dev_priv);
1986}
1987
1988static bool ilk_validate_wm_level(int level,
1989 const struct ilk_wm_maximums *max,
1990 struct intel_wm_level *result)
1991{
1992 bool ret;
1993
1994 /* already determined to be invalid? */
1995 if (!result->enable)
1996 return false;
1997
1998 result->enable = result->pri_val <= max->pri &&
1999 result->spr_val <= max->spr &&
2000 result->cur_val <= max->cur;
2001
2002 ret = result->enable;
2003
2004 /*
2005 * HACK until we can pre-compute everything,
2006 * and thus fail gracefully if LP0 watermarks
2007 * are exceeded...
2008 */
2009 if (level == 0 && !result->enable) {
2010 if (result->pri_val > max->pri)
2011 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2012 level, result->pri_val, max->pri);
2013 if (result->spr_val > max->spr)
2014 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2015 level, result->spr_val, max->spr);
2016 if (result->cur_val > max->cur)
2017 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2018 level, result->cur_val, max->cur);
2019
2020 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2021 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2022 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2023 result->enable = true;
2024 }
2025
2026 return ret;
2027}
2028
2029static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2030 const struct intel_crtc *intel_crtc,
2031 int level,
2032 struct intel_crtc_state *cstate,
2033 struct intel_plane_state *pristate,
2034 struct intel_plane_state *sprstate,
2035 struct intel_plane_state *curstate,
2036 struct intel_wm_level *result)
2037{
2038 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2039 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2040 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2041
2042 /* WM1+ latency values stored in 0.5us units */
2043 if (level > 0) {
2044 pri_latency *= 5;
2045 spr_latency *= 5;
2046 cur_latency *= 5;
2047 }
2048
2049 if (pristate) {
2050 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2051 pri_latency, level);
2052 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2053 }
2054
2055 if (sprstate)
2056 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2057
2058 if (curstate)
2059 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2060
2061 result->enable = true;
2062}
2063
2064static uint32_t
2065hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2066{
2067 const struct intel_atomic_state *intel_state =
2068 to_intel_atomic_state(cstate->base.state);
2069 const struct drm_display_mode *adjusted_mode =
2070 &cstate->base.adjusted_mode;
2071 u32 linetime, ips_linetime;
2072
2073 if (!cstate->base.active)
2074 return 0;
2075 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2076 return 0;
2077 if (WARN_ON(intel_state->cdclk == 0))
2078 return 0;
2079
2080 /* The WM are computed with base on how long it takes to fill a single
2081 * row at the given clock rate, multiplied by 8.
2082 * */
2083 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2084 adjusted_mode->crtc_clock);
2085 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2086 intel_state->cdclk);
2087
2088 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2089 PIPE_WM_LINETIME_TIME(linetime);
2090}
2091
2092static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2093 uint16_t wm[8])
2094{
2095 if (IS_GEN9(dev_priv)) {
2096 uint32_t val;
2097 int ret, i;
2098 int level, max_level = ilk_wm_max_level(dev_priv);
2099
2100 /* read the first set of memory latencies[0:3] */
2101 val = 0; /* data0 to be programmed to 0 for first set */
2102 mutex_lock(&dev_priv->rps.hw_lock);
2103 ret = sandybridge_pcode_read(dev_priv,
2104 GEN9_PCODE_READ_MEM_LATENCY,
2105 &val);
2106 mutex_unlock(&dev_priv->rps.hw_lock);
2107
2108 if (ret) {
2109 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2110 return;
2111 }
2112
2113 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2114 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2115 GEN9_MEM_LATENCY_LEVEL_MASK;
2116 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2117 GEN9_MEM_LATENCY_LEVEL_MASK;
2118 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2119 GEN9_MEM_LATENCY_LEVEL_MASK;
2120
2121 /* read the second set of memory latencies[4:7] */
2122 val = 1; /* data0 to be programmed to 1 for second set */
2123 mutex_lock(&dev_priv->rps.hw_lock);
2124 ret = sandybridge_pcode_read(dev_priv,
2125 GEN9_PCODE_READ_MEM_LATENCY,
2126 &val);
2127 mutex_unlock(&dev_priv->rps.hw_lock);
2128 if (ret) {
2129 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2130 return;
2131 }
2132
2133 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2134 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2135 GEN9_MEM_LATENCY_LEVEL_MASK;
2136 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2137 GEN9_MEM_LATENCY_LEVEL_MASK;
2138 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2139 GEN9_MEM_LATENCY_LEVEL_MASK;
2140
2141 /*
2142 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2143 * need to be disabled. We make sure to sanitize the values out
2144 * of the punit to satisfy this requirement.
2145 */
2146 for (level = 1; level <= max_level; level++) {
2147 if (wm[level] == 0) {
2148 for (i = level + 1; i <= max_level; i++)
2149 wm[i] = 0;
2150 break;
2151 }
2152 }
2153
2154 /*
2155 * WaWmMemoryReadLatency:skl
2156 *
2157 * punit doesn't take into account the read latency so we need
2158 * to add 2us to the various latency levels we retrieve from the
2159 * punit when level 0 response data us 0us.
2160 */
2161 if (wm[0] == 0) {
2162 wm[0] += 2;
2163 for (level = 1; level <= max_level; level++) {
2164 if (wm[level] == 0)
2165 break;
2166 wm[level] += 2;
2167 }
2168 }
2169
2170 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2171 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2172
2173 wm[0] = (sskpd >> 56) & 0xFF;
2174 if (wm[0] == 0)
2175 wm[0] = sskpd & 0xF;
2176 wm[1] = (sskpd >> 4) & 0xFF;
2177 wm[2] = (sskpd >> 12) & 0xFF;
2178 wm[3] = (sskpd >> 20) & 0x1FF;
2179 wm[4] = (sskpd >> 32) & 0x1FF;
2180 } else if (INTEL_GEN(dev_priv) >= 6) {
2181 uint32_t sskpd = I915_READ(MCH_SSKPD);
2182
2183 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2184 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2185 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2186 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2187 } else if (INTEL_GEN(dev_priv) >= 5) {
2188 uint32_t mltr = I915_READ(MLTR_ILK);
2189
2190 /* ILK primary LP0 latency is 700 ns */
2191 wm[0] = 7;
2192 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2193 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2194 }
2195}
2196
2197static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2198 uint16_t wm[5])
2199{
2200 /* ILK sprite LP0 latency is 1300 ns */
2201 if (IS_GEN5(dev_priv))
2202 wm[0] = 13;
2203}
2204
2205static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2206 uint16_t wm[5])
2207{
2208 /* ILK cursor LP0 latency is 1300 ns */
2209 if (IS_GEN5(dev_priv))
2210 wm[0] = 13;
2211
2212 /* WaDoubleCursorLP3Latency:ivb */
2213 if (IS_IVYBRIDGE(dev_priv))
2214 wm[3] *= 2;
2215}
2216
2217int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2218{
2219 /* how many WM levels are we expecting */
2220 if (INTEL_GEN(dev_priv) >= 9)
2221 return 7;
2222 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2223 return 4;
2224 else if (INTEL_GEN(dev_priv) >= 6)
2225 return 3;
2226 else
2227 return 2;
2228}
2229
2230static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2231 const char *name,
2232 const uint16_t wm[8])
2233{
2234 int level, max_level = ilk_wm_max_level(dev_priv);
2235
2236 for (level = 0; level <= max_level; level++) {
2237 unsigned int latency = wm[level];
2238
2239 if (latency == 0) {
2240 DRM_ERROR("%s WM%d latency not provided\n",
2241 name, level);
2242 continue;
2243 }
2244
2245 /*
2246 * - latencies are in us on gen9.
2247 * - before then, WM1+ latency values are in 0.5us units
2248 */
2249 if (IS_GEN9(dev_priv))
2250 latency *= 10;
2251 else if (level > 0)
2252 latency *= 5;
2253
2254 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2255 name, level, wm[level],
2256 latency / 10, latency % 10);
2257 }
2258}
2259
2260static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2261 uint16_t wm[5], uint16_t min)
2262{
2263 int level, max_level = ilk_wm_max_level(dev_priv);
2264
2265 if (wm[0] >= min)
2266 return false;
2267
2268 wm[0] = max(wm[0], min);
2269 for (level = 1; level <= max_level; level++)
2270 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2271
2272 return true;
2273}
2274
2275static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
2276{
2277 bool changed;
2278
2279 /*
2280 * The BIOS provided WM memory latency values are often
2281 * inadequate for high resolution displays. Adjust them.
2282 */
2283 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2284 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2285 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2286
2287 if (!changed)
2288 return;
2289
2290 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2291 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2292 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2293 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2294}
2295
2296static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
2297{
2298 intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
2299
2300 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2301 sizeof(dev_priv->wm.pri_latency));
2302 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2303 sizeof(dev_priv->wm.pri_latency));
2304
2305 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2306 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
2307
2308 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2309 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2310 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2311
2312 if (IS_GEN6(dev_priv))
2313 snb_wm_latency_quirk(dev_priv);
2314}
2315
2316static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
2317{
2318 intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
2319 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2320}
2321
2322static bool ilk_validate_pipe_wm(struct drm_device *dev,
2323 struct intel_pipe_wm *pipe_wm)
2324{
2325 /* LP0 watermark maximums depend on this pipe alone */
2326 const struct intel_wm_config config = {
2327 .num_pipes_active = 1,
2328 .sprites_enabled = pipe_wm->sprites_enabled,
2329 .sprites_scaled = pipe_wm->sprites_scaled,
2330 };
2331 struct ilk_wm_maximums max;
2332
2333 /* LP0 watermarks always use 1/2 DDB partitioning */
2334 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2335
2336 /* At least LP0 must be valid */
2337 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2338 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2339 return false;
2340 }
2341
2342 return true;
2343}
2344
2345/* Compute new watermarks for the pipe */
2346static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2347{
2348 struct drm_atomic_state *state = cstate->base.state;
2349 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2350 struct intel_pipe_wm *pipe_wm;
2351 struct drm_device *dev = state->dev;
2352 const struct drm_i915_private *dev_priv = to_i915(dev);
2353 struct intel_plane *intel_plane;
2354 struct intel_plane_state *pristate = NULL;
2355 struct intel_plane_state *sprstate = NULL;
2356 struct intel_plane_state *curstate = NULL;
2357 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
2358 struct ilk_wm_maximums max;
2359
2360 pipe_wm = &cstate->wm.ilk.optimal;
2361
2362 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2363 struct intel_plane_state *ps;
2364
2365 ps = intel_atomic_get_existing_plane_state(state,
2366 intel_plane);
2367 if (!ps)
2368 continue;
2369
2370 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2371 pristate = ps;
2372 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2373 sprstate = ps;
2374 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2375 curstate = ps;
2376 }
2377
2378 pipe_wm->pipe_enabled = cstate->base.active;
2379 if (sprstate) {
2380 pipe_wm->sprites_enabled = sprstate->base.visible;
2381 pipe_wm->sprites_scaled = sprstate->base.visible &&
2382 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2383 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2384 }
2385
2386 usable_level = max_level;
2387
2388 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2389 if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
2390 usable_level = 1;
2391
2392 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2393 if (pipe_wm->sprites_scaled)
2394 usable_level = 0;
2395
2396 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2397 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2398
2399 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2400 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2401
2402 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2403 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2404
2405 if (!ilk_validate_pipe_wm(dev, pipe_wm))
2406 return -EINVAL;
2407
2408 ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
2409
2410 for (level = 1; level <= max_level; level++) {
2411 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2412
2413 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2414 pristate, sprstate, curstate, wm);
2415
2416 /*
2417 * Disable any watermark level that exceeds the
2418 * register maximums since such watermarks are
2419 * always invalid.
2420 */
2421 if (level > usable_level)
2422 continue;
2423
2424 if (ilk_validate_wm_level(level, &max, wm))
2425 pipe_wm->wm[level] = *wm;
2426 else
2427 usable_level = level;
2428 }
2429
2430 return 0;
2431}
2432
2433/*
2434 * Build a set of 'intermediate' watermark values that satisfy both the old
2435 * state and the new state. These can be programmed to the hardware
2436 * immediately.
2437 */
2438static int ilk_compute_intermediate_wm(struct drm_device *dev,
2439 struct intel_crtc *intel_crtc,
2440 struct intel_crtc_state *newstate)
2441{
2442 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2443 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2444 int level, max_level = ilk_wm_max_level(to_i915(dev));
2445
2446 /*
2447 * Start with the final, target watermarks, then combine with the
2448 * currently active watermarks to get values that are safe both before
2449 * and after the vblank.
2450 */
2451 *a = newstate->wm.ilk.optimal;
2452 a->pipe_enabled |= b->pipe_enabled;
2453 a->sprites_enabled |= b->sprites_enabled;
2454 a->sprites_scaled |= b->sprites_scaled;
2455
2456 for (level = 0; level <= max_level; level++) {
2457 struct intel_wm_level *a_wm = &a->wm[level];
2458 const struct intel_wm_level *b_wm = &b->wm[level];
2459
2460 a_wm->enable &= b_wm->enable;
2461 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2462 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2463 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2464 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2465 }
2466
2467 /*
2468 * We need to make sure that these merged watermark values are
2469 * actually a valid configuration themselves. If they're not,
2470 * there's no safe way to transition from the old state to
2471 * the new state, so we need to fail the atomic transaction.
2472 */
2473 if (!ilk_validate_pipe_wm(dev, a))
2474 return -EINVAL;
2475
2476 /*
2477 * If our intermediate WM are identical to the final WM, then we can
2478 * omit the post-vblank programming; only update if it's different.
2479 */
2480 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2481 newstate->wm.need_postvbl_update = false;
2482
2483 return 0;
2484}
2485
2486/*
2487 * Merge the watermarks from all active pipes for a specific level.
2488 */
2489static void ilk_merge_wm_level(struct drm_device *dev,
2490 int level,
2491 struct intel_wm_level *ret_wm)
2492{
2493 const struct intel_crtc *intel_crtc;
2494
2495 ret_wm->enable = true;
2496
2497 for_each_intel_crtc(dev, intel_crtc) {
2498 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2499 const struct intel_wm_level *wm = &active->wm[level];
2500
2501 if (!active->pipe_enabled)
2502 continue;
2503
2504 /*
2505 * The watermark values may have been used in the past,
2506 * so we must maintain them in the registers for some
2507 * time even if the level is now disabled.
2508 */
2509 if (!wm->enable)
2510 ret_wm->enable = false;
2511
2512 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2513 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2514 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2515 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2516 }
2517}
2518
2519/*
2520 * Merge all low power watermarks for all active pipes.
2521 */
2522static void ilk_wm_merge(struct drm_device *dev,
2523 const struct intel_wm_config *config,
2524 const struct ilk_wm_maximums *max,
2525 struct intel_pipe_wm *merged)
2526{
2527 struct drm_i915_private *dev_priv = to_i915(dev);
2528 int level, max_level = ilk_wm_max_level(dev_priv);
2529 int last_enabled_level = max_level;
2530
2531 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2532 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
2533 config->num_pipes_active > 1)
2534 last_enabled_level = 0;
2535
2536 /* ILK: FBC WM must be disabled always */
2537 merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
2538
2539 /* merge each WM1+ level */
2540 for (level = 1; level <= max_level; level++) {
2541 struct intel_wm_level *wm = &merged->wm[level];
2542
2543 ilk_merge_wm_level(dev, level, wm);
2544
2545 if (level > last_enabled_level)
2546 wm->enable = false;
2547 else if (!ilk_validate_wm_level(level, max, wm))
2548 /* make sure all following levels get disabled */
2549 last_enabled_level = level - 1;
2550
2551 /*
2552 * The spec says it is preferred to disable
2553 * FBC WMs instead of disabling a WM level.
2554 */
2555 if (wm->fbc_val > max->fbc) {
2556 if (wm->enable)
2557 merged->fbc_wm_enabled = false;
2558 wm->fbc_val = 0;
2559 }
2560 }
2561
2562 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2563 /*
2564 * FIXME this is racy. FBC might get enabled later.
2565 * What we should check here is whether FBC can be
2566 * enabled sometime later.
2567 */
2568 if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
2569 intel_fbc_is_active(dev_priv)) {
2570 for (level = 2; level <= max_level; level++) {
2571 struct intel_wm_level *wm = &merged->wm[level];
2572
2573 wm->enable = false;
2574 }
2575 }
2576}
2577
2578static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2579{
2580 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2581 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2582}
2583
2584/* The value we need to program into the WM_LPx latency field */
2585static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2586{
2587 struct drm_i915_private *dev_priv = to_i915(dev);
2588
2589 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2590 return 2 * level;
2591 else
2592 return dev_priv->wm.pri_latency[level];
2593}
2594
2595static void ilk_compute_wm_results(struct drm_device *dev,
2596 const struct intel_pipe_wm *merged,
2597 enum intel_ddb_partitioning partitioning,
2598 struct ilk_wm_values *results)
2599{
2600 struct drm_i915_private *dev_priv = to_i915(dev);
2601 struct intel_crtc *intel_crtc;
2602 int level, wm_lp;
2603
2604 results->enable_fbc_wm = merged->fbc_wm_enabled;
2605 results->partitioning = partitioning;
2606
2607 /* LP1+ register values */
2608 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2609 const struct intel_wm_level *r;
2610
2611 level = ilk_wm_lp_to_level(wm_lp, merged);
2612
2613 r = &merged->wm[level];
2614
2615 /*
2616 * Maintain the watermark values even if the level is
2617 * disabled. Doing otherwise could cause underruns.
2618 */
2619 results->wm_lp[wm_lp - 1] =
2620 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2621 (r->pri_val << WM1_LP_SR_SHIFT) |
2622 r->cur_val;
2623
2624 if (r->enable)
2625 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2626
2627 if (INTEL_GEN(dev_priv) >= 8)
2628 results->wm_lp[wm_lp - 1] |=
2629 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2630 else
2631 results->wm_lp[wm_lp - 1] |=
2632 r->fbc_val << WM1_LP_FBC_SHIFT;
2633
2634 /*
2635 * Always set WM1S_LP_EN when spr_val != 0, even if the
2636 * level is disabled. Doing otherwise could cause underruns.
2637 */
2638 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
2639 WARN_ON(wm_lp != 1);
2640 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2641 } else
2642 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2643 }
2644
2645 /* LP0 register values */
2646 for_each_intel_crtc(dev, intel_crtc) {
2647 enum pipe pipe = intel_crtc->pipe;
2648 const struct intel_wm_level *r =
2649 &intel_crtc->wm.active.ilk.wm[0];
2650
2651 if (WARN_ON(!r->enable))
2652 continue;
2653
2654 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2655
2656 results->wm_pipe[pipe] =
2657 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2658 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2659 r->cur_val;
2660 }
2661}
2662
2663/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2664 * case both are at the same level. Prefer r1 in case they're the same. */
2665static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2666 struct intel_pipe_wm *r1,
2667 struct intel_pipe_wm *r2)
2668{
2669 int level, max_level = ilk_wm_max_level(to_i915(dev));
2670 int level1 = 0, level2 = 0;
2671
2672 for (level = 1; level <= max_level; level++) {
2673 if (r1->wm[level].enable)
2674 level1 = level;
2675 if (r2->wm[level].enable)
2676 level2 = level;
2677 }
2678
2679 if (level1 == level2) {
2680 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2681 return r2;
2682 else
2683 return r1;
2684 } else if (level1 > level2) {
2685 return r1;
2686 } else {
2687 return r2;
2688 }
2689}
2690
2691/* dirty bits used to track which watermarks need changes */
2692#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2693#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2694#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2695#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2696#define WM_DIRTY_FBC (1 << 24)
2697#define WM_DIRTY_DDB (1 << 25)
2698
2699static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2700 const struct ilk_wm_values *old,
2701 const struct ilk_wm_values *new)
2702{
2703 unsigned int dirty = 0;
2704 enum pipe pipe;
2705 int wm_lp;
2706
2707 for_each_pipe(dev_priv, pipe) {
2708 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2709 dirty |= WM_DIRTY_LINETIME(pipe);
2710 /* Must disable LP1+ watermarks too */
2711 dirty |= WM_DIRTY_LP_ALL;
2712 }
2713
2714 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2715 dirty |= WM_DIRTY_PIPE(pipe);
2716 /* Must disable LP1+ watermarks too */
2717 dirty |= WM_DIRTY_LP_ALL;
2718 }
2719 }
2720
2721 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2722 dirty |= WM_DIRTY_FBC;
2723 /* Must disable LP1+ watermarks too */
2724 dirty |= WM_DIRTY_LP_ALL;
2725 }
2726
2727 if (old->partitioning != new->partitioning) {
2728 dirty |= WM_DIRTY_DDB;
2729 /* Must disable LP1+ watermarks too */
2730 dirty |= WM_DIRTY_LP_ALL;
2731 }
2732
2733 /* LP1+ watermarks already deemed dirty, no need to continue */
2734 if (dirty & WM_DIRTY_LP_ALL)
2735 return dirty;
2736
2737 /* Find the lowest numbered LP1+ watermark in need of an update... */
2738 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2739 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2740 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2741 break;
2742 }
2743
2744 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2745 for (; wm_lp <= 3; wm_lp++)
2746 dirty |= WM_DIRTY_LP(wm_lp);
2747
2748 return dirty;
2749}
2750
2751static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2752 unsigned int dirty)
2753{
2754 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2755 bool changed = false;
2756
2757 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2758 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2759 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2760 changed = true;
2761 }
2762 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2763 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2764 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2765 changed = true;
2766 }
2767 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2768 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2769 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2770 changed = true;
2771 }
2772
2773 /*
2774 * Don't touch WM1S_LP_EN here.
2775 * Doing so could cause underruns.
2776 */
2777
2778 return changed;
2779}
2780
2781/*
2782 * The spec says we shouldn't write when we don't need, because every write
2783 * causes WMs to be re-evaluated, expending some power.
2784 */
2785static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2786 struct ilk_wm_values *results)
2787{
2788 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2789 unsigned int dirty;
2790 uint32_t val;
2791
2792 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2793 if (!dirty)
2794 return;
2795
2796 _ilk_disable_lp_wm(dev_priv, dirty);
2797
2798 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2799 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2800 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2801 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2802 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2803 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2804
2805 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2806 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2807 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2808 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2809 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2810 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2811
2812 if (dirty & WM_DIRTY_DDB) {
2813 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2814 val = I915_READ(WM_MISC);
2815 if (results->partitioning == INTEL_DDB_PART_1_2)
2816 val &= ~WM_MISC_DATA_PARTITION_5_6;
2817 else
2818 val |= WM_MISC_DATA_PARTITION_5_6;
2819 I915_WRITE(WM_MISC, val);
2820 } else {
2821 val = I915_READ(DISP_ARB_CTL2);
2822 if (results->partitioning == INTEL_DDB_PART_1_2)
2823 val &= ~DISP_DATA_PARTITION_5_6;
2824 else
2825 val |= DISP_DATA_PARTITION_5_6;
2826 I915_WRITE(DISP_ARB_CTL2, val);
2827 }
2828 }
2829
2830 if (dirty & WM_DIRTY_FBC) {
2831 val = I915_READ(DISP_ARB_CTL);
2832 if (results->enable_fbc_wm)
2833 val &= ~DISP_FBC_WM_DIS;
2834 else
2835 val |= DISP_FBC_WM_DIS;
2836 I915_WRITE(DISP_ARB_CTL, val);
2837 }
2838
2839 if (dirty & WM_DIRTY_LP(1) &&
2840 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2841 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2842
2843 if (INTEL_GEN(dev_priv) >= 7) {
2844 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2845 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2846 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2847 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2848 }
2849
2850 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2851 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2852 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2853 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2854 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2855 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2856
2857 dev_priv->wm.hw = *results;
2858}
2859
2860bool ilk_disable_lp_wm(struct drm_device *dev)
2861{
2862 struct drm_i915_private *dev_priv = to_i915(dev);
2863
2864 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2865}
2866
2867#define SKL_SAGV_BLOCK_TIME 30 /* µs */
2868
2869/*
2870 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2871 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2872 * other universal planes are in indices 1..n. Note that this may leave unused
2873 * indices between the top "sprite" plane and the cursor.
2874 */
2875static int
2876skl_wm_plane_id(const struct intel_plane *plane)
2877{
2878 switch (plane->base.type) {
2879 case DRM_PLANE_TYPE_PRIMARY:
2880 return 0;
2881 case DRM_PLANE_TYPE_CURSOR:
2882 return PLANE_CURSOR;
2883 case DRM_PLANE_TYPE_OVERLAY:
2884 return plane->plane + 1;
2885 default:
2886 MISSING_CASE(plane->base.type);
2887 return plane->plane;
2888 }
2889}
2890
2891/*
2892 * FIXME: We still don't have the proper code detect if we need to apply the WA,
2893 * so assume we'll always need it in order to avoid underruns.
2894 */
2895static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2896{
2897 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2898
2899 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2900 IS_KABYLAKE(dev_priv))
2901 return true;
2902
2903 return false;
2904}
2905
2906static bool
2907intel_has_sagv(struct drm_i915_private *dev_priv)
2908{
2909 if (IS_KABYLAKE(dev_priv))
2910 return true;
2911
2912 if (IS_SKYLAKE(dev_priv) &&
2913 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2914 return true;
2915
2916 return false;
2917}
2918
2919/*
2920 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2921 * depending on power and performance requirements. The display engine access
2922 * to system memory is blocked during the adjustment time. Because of the
2923 * blocking time, having this enabled can cause full system hangs and/or pipe
2924 * underruns if we don't meet all of the following requirements:
2925 *
2926 * - <= 1 pipe enabled
2927 * - All planes can enable watermarks for latencies >= SAGV engine block time
2928 * - We're not using an interlaced display configuration
2929 */
2930int
2931intel_enable_sagv(struct drm_i915_private *dev_priv)
2932{
2933 int ret;
2934
2935 if (!intel_has_sagv(dev_priv))
2936 return 0;
2937
2938 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
2939 return 0;
2940
2941 DRM_DEBUG_KMS("Enabling the SAGV\n");
2942 mutex_lock(&dev_priv->rps.hw_lock);
2943
2944 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2945 GEN9_SAGV_ENABLE);
2946
2947 /* We don't need to wait for the SAGV when enabling */
2948 mutex_unlock(&dev_priv->rps.hw_lock);
2949
2950 /*
2951 * Some skl systems, pre-release machines in particular,
2952 * don't actually have an SAGV.
2953 */
2954 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2955 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2956 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2957 return 0;
2958 } else if (ret < 0) {
2959 DRM_ERROR("Failed to enable the SAGV\n");
2960 return ret;
2961 }
2962
2963 dev_priv->sagv_status = I915_SAGV_ENABLED;
2964 return 0;
2965}
2966
2967int
2968intel_disable_sagv(struct drm_i915_private *dev_priv)
2969{
2970 int ret;
2971
2972 if (!intel_has_sagv(dev_priv))
2973 return 0;
2974
2975 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
2976 return 0;
2977
2978 DRM_DEBUG_KMS("Disabling the SAGV\n");
2979 mutex_lock(&dev_priv->rps.hw_lock);
2980
2981 /* bspec says to keep retrying for at least 1 ms */
2982 ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2983 GEN9_SAGV_DISABLE,
2984 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
2985 1);
2986 mutex_unlock(&dev_priv->rps.hw_lock);
2987
2988 /*
2989 * Some skl systems, pre-release machines in particular,
2990 * don't actually have an SAGV.
2991 */
2992 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2993 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2994 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2995 return 0;
2996 } else if (ret < 0) {
2997 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret);
2998 return ret;
2999 }
3000
3001 dev_priv->sagv_status = I915_SAGV_DISABLED;
3002 return 0;
3003}
3004
3005bool intel_can_enable_sagv(struct drm_atomic_state *state)
3006{
3007 struct drm_device *dev = state->dev;
3008 struct drm_i915_private *dev_priv = to_i915(dev);
3009 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3010 struct intel_crtc *crtc;
3011 struct intel_plane *plane;
3012 struct intel_crtc_state *cstate;
3013 struct skl_plane_wm *wm;
3014 enum pipe pipe;
3015 int level, latency;
3016
3017 if (!intel_has_sagv(dev_priv))
3018 return false;
3019
3020 /*
3021 * SKL workaround: bspec recommends we disable the SAGV when we have
3022 * more then one pipe enabled
3023 *
3024 * If there are no active CRTCs, no additional checks need be performed
3025 */
3026 if (hweight32(intel_state->active_crtcs) == 0)
3027 return true;
3028 else if (hweight32(intel_state->active_crtcs) > 1)
3029 return false;
3030
3031 /* Since we're now guaranteed to only have one active CRTC... */
3032 pipe = ffs(intel_state->active_crtcs) - 1;
3033 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3034 cstate = to_intel_crtc_state(crtc->base.state);
3035
3036 if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3037 return false;
3038
3039 for_each_intel_plane_on_crtc(dev, crtc, plane) {
3040 wm = &cstate->wm.skl.optimal.planes[skl_wm_plane_id(plane)];
3041
3042 /* Skip this plane if it's not enabled */
3043 if (!wm->wm[0].plane_en)
3044 continue;
3045
3046 /* Find the highest enabled wm level for this plane */
3047 for (level = ilk_wm_max_level(dev_priv);
3048 !wm->wm[level].plane_en; --level)
3049 { }
3050
3051 latency = dev_priv->wm.skl_latency[level];
3052
3053 if (skl_needs_memory_bw_wa(intel_state) &&
3054 plane->base.state->fb->modifier ==
3055 I915_FORMAT_MOD_X_TILED)
3056 latency += 15;
3057
3058 /*
3059 * If any of the planes on this pipe don't enable wm levels
3060 * that incur memory latencies higher then 30µs we can't enable
3061 * the SAGV
3062 */
3063 if (latency < SKL_SAGV_BLOCK_TIME)
3064 return false;
3065 }
3066
3067 return true;
3068}
3069
3070static void
3071skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3072 const struct intel_crtc_state *cstate,
3073 struct skl_ddb_entry *alloc, /* out */
3074 int *num_active /* out */)
3075{
3076 struct drm_atomic_state *state = cstate->base.state;
3077 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3078 struct drm_i915_private *dev_priv = to_i915(dev);
3079 struct drm_crtc *for_crtc = cstate->base.crtc;
3080 unsigned int pipe_size, ddb_size;
3081 int nth_active_pipe;
3082
3083 if (WARN_ON(!state) || !cstate->base.active) {
3084 alloc->start = 0;
3085 alloc->end = 0;
3086 *num_active = hweight32(dev_priv->active_crtcs);
3087 return;
3088 }
3089
3090 if (intel_state->active_pipe_changes)
3091 *num_active = hweight32(intel_state->active_crtcs);
3092 else
3093 *num_active = hweight32(dev_priv->active_crtcs);
3094
3095 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3096 WARN_ON(ddb_size == 0);
3097
3098 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3099
3100 /*
3101 * If the state doesn't change the active CRTC's, then there's
3102 * no need to recalculate; the existing pipe allocation limits
3103 * should remain unchanged. Note that we're safe from racing
3104 * commits since any racing commit that changes the active CRTC
3105 * list would need to grab _all_ crtc locks, including the one
3106 * we currently hold.
3107 */
3108 if (!intel_state->active_pipe_changes) {
3109 /*
3110 * alloc may be cleared by clear_intel_crtc_state,
3111 * copy from old state to be sure
3112 */
3113 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3114 return;
3115 }
3116
3117 nth_active_pipe = hweight32(intel_state->active_crtcs &
3118 (drm_crtc_mask(for_crtc) - 1));
3119 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3120 alloc->start = nth_active_pipe * ddb_size / *num_active;
3121 alloc->end = alloc->start + pipe_size;
3122}
3123
3124static unsigned int skl_cursor_allocation(int num_active)
3125{
3126 if (num_active == 1)
3127 return 32;
3128
3129 return 8;
3130}
3131
3132static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3133{
3134 entry->start = reg & 0x3ff;
3135 entry->end = (reg >> 16) & 0x3ff;
3136 if (entry->end)
3137 entry->end += 1;
3138}
3139
3140void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3141 struct skl_ddb_allocation *ddb /* out */)
3142{
3143 enum pipe pipe;
3144 int plane;
3145 u32 val;
3146
3147 memset(ddb, 0, sizeof(*ddb));
3148
3149 for_each_pipe(dev_priv, pipe) {
3150 enum intel_display_power_domain power_domain;
3151
3152 power_domain = POWER_DOMAIN_PIPE(pipe);
3153 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3154 continue;
3155
3156 for_each_universal_plane(dev_priv, pipe, plane) {
3157 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3158 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3159 val);
3160 }
3161
3162 val = I915_READ(CUR_BUF_CFG(pipe));
3163 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3164 val);
3165
3166 intel_display_power_put(dev_priv, power_domain);
3167 }
3168}
3169
3170/*
3171 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3172 * The bspec defines downscale amount as:
3173 *
3174 * """
3175 * Horizontal down scale amount = maximum[1, Horizontal source size /
3176 * Horizontal destination size]
3177 * Vertical down scale amount = maximum[1, Vertical source size /
3178 * Vertical destination size]
3179 * Total down scale amount = Horizontal down scale amount *
3180 * Vertical down scale amount
3181 * """
3182 *
3183 * Return value is provided in 16.16 fixed point form to retain fractional part.
3184 * Caller should take care of dividing & rounding off the value.
3185 */
3186static uint32_t
3187skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3188{
3189 uint32_t downscale_h, downscale_w;
3190 uint32_t src_w, src_h, dst_w, dst_h;
3191
3192 if (WARN_ON(!pstate->base.visible))
3193 return DRM_PLANE_HELPER_NO_SCALING;
3194
3195 /* n.b., src is 16.16 fixed point, dst is whole integer */
3196 src_w = drm_rect_width(&pstate->base.src);
3197 src_h = drm_rect_height(&pstate->base.src);
3198 dst_w = drm_rect_width(&pstate->base.dst);
3199 dst_h = drm_rect_height(&pstate->base.dst);
3200 if (drm_rotation_90_or_270(pstate->base.rotation))
3201 swap(dst_w, dst_h);
3202
3203 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3204 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3205
3206 /* Provide result in 16.16 fixed point */
3207 return (uint64_t)downscale_w * downscale_h >> 16;
3208}
3209
3210static unsigned int
3211skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3212 const struct drm_plane_state *pstate,
3213 int y)
3214{
3215 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3216 struct drm_framebuffer *fb = pstate->fb;
3217 uint32_t down_scale_amount, data_rate;
3218 uint32_t width = 0, height = 0;
3219 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3220
3221 if (!intel_pstate->base.visible)
3222 return 0;
3223 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3224 return 0;
3225 if (y && format != DRM_FORMAT_NV12)
3226 return 0;
3227
3228 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3229 height = drm_rect_height(&intel_pstate->base.src) >> 16;
3230
3231 if (drm_rotation_90_or_270(pstate->rotation))
3232 swap(width, height);
3233
3234 /* for planar format */
3235 if (format == DRM_FORMAT_NV12) {
3236 if (y) /* y-plane data rate */
3237 data_rate = width * height *
3238 drm_format_plane_cpp(format, 0);
3239 else /* uv-plane data rate */
3240 data_rate = (width / 2) * (height / 2) *
3241 drm_format_plane_cpp(format, 1);
3242 } else {
3243 /* for packed formats */
3244 data_rate = width * height * drm_format_plane_cpp(format, 0);
3245 }
3246
3247 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3248
3249 return (uint64_t)data_rate * down_scale_amount >> 16;
3250}
3251
3252/*
3253 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3254 * a 8192x4096@32bpp framebuffer:
3255 * 3 * 4096 * 8192 * 4 < 2^32
3256 */
3257static unsigned int
3258skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3259 unsigned *plane_data_rate,
3260 unsigned *plane_y_data_rate)
3261{
3262 struct drm_crtc_state *cstate = &intel_cstate->base;
3263 struct drm_atomic_state *state = cstate->state;
3264 struct drm_plane *plane;
3265 const struct intel_plane *intel_plane;
3266 const struct drm_plane_state *pstate;
3267 unsigned int rate, total_data_rate = 0;
3268 int id;
3269
3270 if (WARN_ON(!state))
3271 return 0;
3272
3273 /* Calculate and cache data rate for each plane */
3274 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
3275 id = skl_wm_plane_id(to_intel_plane(plane));
3276 intel_plane = to_intel_plane(plane);
3277
3278 /* packed/uv */
3279 rate = skl_plane_relative_data_rate(intel_cstate,
3280 pstate, 0);
3281 plane_data_rate[id] = rate;
3282
3283 total_data_rate += rate;
3284
3285 /* y-plane */
3286 rate = skl_plane_relative_data_rate(intel_cstate,
3287 pstate, 1);
3288 plane_y_data_rate[id] = rate;
3289
3290 total_data_rate += rate;
3291 }
3292
3293 return total_data_rate;
3294}
3295
3296static uint16_t
3297skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3298 const int y)
3299{
3300 struct drm_framebuffer *fb = pstate->fb;
3301 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3302 uint32_t src_w, src_h;
3303 uint32_t min_scanlines = 8;
3304 uint8_t plane_bpp;
3305
3306 if (WARN_ON(!fb))
3307 return 0;
3308
3309 /* For packed formats, no y-plane, return 0 */
3310 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3311 return 0;
3312
3313 /* For Non Y-tile return 8-blocks */
3314 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
3315 fb->modifier != I915_FORMAT_MOD_Yf_TILED)
3316 return 8;
3317
3318 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3319 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3320
3321 if (drm_rotation_90_or_270(pstate->rotation))
3322 swap(src_w, src_h);
3323
3324 /* Halve UV plane width and height for NV12 */
3325 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3326 src_w /= 2;
3327 src_h /= 2;
3328 }
3329
3330 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3331 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3332 else
3333 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3334
3335 if (drm_rotation_90_or_270(pstate->rotation)) {
3336 switch (plane_bpp) {
3337 case 1:
3338 min_scanlines = 32;
3339 break;
3340 case 2:
3341 min_scanlines = 16;
3342 break;
3343 case 4:
3344 min_scanlines = 8;
3345 break;
3346 case 8:
3347 min_scanlines = 4;
3348 break;
3349 default:
3350 WARN(1, "Unsupported pixel depth %u for rotation",
3351 plane_bpp);
3352 min_scanlines = 32;
3353 }
3354 }
3355
3356 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3357}
3358
3359static void
3360skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3361 uint16_t *minimum, uint16_t *y_minimum)
3362{
3363 const struct drm_plane_state *pstate;
3364 struct drm_plane *plane;
3365
3366 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
3367 struct intel_plane *intel_plane = to_intel_plane(plane);
3368 int id = skl_wm_plane_id(intel_plane);
3369
3370 if (id == PLANE_CURSOR)
3371 continue;
3372
3373 if (!pstate->visible)
3374 continue;
3375
3376 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3377 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3378 }
3379
3380 minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3381}
3382
3383static int
3384skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3385 struct skl_ddb_allocation *ddb /* out */)
3386{
3387 struct drm_atomic_state *state = cstate->base.state;
3388 struct drm_crtc *crtc = cstate->base.crtc;
3389 struct drm_device *dev = crtc->dev;
3390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3391 enum pipe pipe = intel_crtc->pipe;
3392 struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
3393 uint16_t alloc_size, start;
3394 uint16_t minimum[I915_MAX_PLANES] = {};
3395 uint16_t y_minimum[I915_MAX_PLANES] = {};
3396 unsigned int total_data_rate;
3397 int num_active;
3398 int id, i;
3399 unsigned plane_data_rate[I915_MAX_PLANES] = {};
3400 unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
3401
3402 /* Clear the partitioning for disabled planes. */
3403 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3404 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3405
3406 if (WARN_ON(!state))
3407 return 0;
3408
3409 if (!cstate->base.active) {
3410 alloc->start = alloc->end = 0;
3411 return 0;
3412 }
3413
3414 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3415 alloc_size = skl_ddb_entry_size(alloc);
3416 if (alloc_size == 0) {
3417 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3418 return 0;
3419 }
3420
3421 skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
3422
3423 /*
3424 * 1. Allocate the mininum required blocks for each active plane
3425 * and allocate the cursor, it doesn't require extra allocation
3426 * proportional to the data rate.
3427 */
3428
3429 for (i = 0; i < I915_MAX_PLANES; i++) {
3430 alloc_size -= minimum[i];
3431 alloc_size -= y_minimum[i];
3432 }
3433
3434 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3435 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3436
3437 /*
3438 * 2. Distribute the remaining space in proportion to the amount of
3439 * data each plane needs to fetch from memory.
3440 *
3441 * FIXME: we may not allocate every single block here.
3442 */
3443 total_data_rate = skl_get_total_relative_data_rate(cstate,
3444 plane_data_rate,
3445 plane_y_data_rate);
3446 if (total_data_rate == 0)
3447 return 0;
3448
3449 start = alloc->start;
3450 for (id = 0; id < I915_MAX_PLANES; id++) {
3451 unsigned int data_rate, y_data_rate;
3452 uint16_t plane_blocks, y_plane_blocks = 0;
3453
3454 if (id == PLANE_CURSOR)
3455 continue;
3456
3457 data_rate = plane_data_rate[id];
3458
3459 /*
3460 * allocation for (packed formats) or (uv-plane part of planar format):
3461 * promote the expression to 64 bits to avoid overflowing, the
3462 * result is < available as data_rate / total_data_rate < 1
3463 */
3464 plane_blocks = minimum[id];
3465 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3466 total_data_rate);
3467
3468 /* Leave disabled planes at (0,0) */
3469 if (data_rate) {
3470 ddb->plane[pipe][id].start = start;
3471 ddb->plane[pipe][id].end = start + plane_blocks;
3472 }
3473
3474 start += plane_blocks;
3475
3476 /*
3477 * allocation for y_plane part of planar format:
3478 */
3479 y_data_rate = plane_y_data_rate[id];
3480
3481 y_plane_blocks = y_minimum[id];
3482 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3483 total_data_rate);
3484
3485 if (y_data_rate) {
3486 ddb->y_plane[pipe][id].start = start;
3487 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3488 }
3489
3490 start += y_plane_blocks;
3491 }
3492
3493 return 0;
3494}
3495
3496/*
3497 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3498 * for the read latency) and cpp should always be <= 8, so that
3499 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3500 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3501*/
3502static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3503{
3504 uint32_t wm_intermediate_val, ret;
3505
3506 if (latency == 0)
3507 return UINT_MAX;
3508
3509 wm_intermediate_val = latency * pixel_rate * cpp / 512;
3510 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3511
3512 return ret;
3513}
3514
3515static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3516 uint32_t latency, uint32_t plane_blocks_per_line)
3517{
3518 uint32_t ret;
3519 uint32_t wm_intermediate_val;
3520
3521 if (latency == 0)
3522 return UINT_MAX;
3523
3524 wm_intermediate_val = latency * pixel_rate;
3525 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3526 plane_blocks_per_line;
3527
3528 return ret;
3529}
3530
3531static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3532 struct intel_plane_state *pstate)
3533{
3534 uint64_t adjusted_pixel_rate;
3535 uint64_t downscale_amount;
3536 uint64_t pixel_rate;
3537
3538 /* Shouldn't reach here on disabled planes... */
3539 if (WARN_ON(!pstate->base.visible))
3540 return 0;
3541
3542 /*
3543 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3544 * with additional adjustments for plane-specific scaling.
3545 */
3546 adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
3547 downscale_amount = skl_plane_downscale_amount(pstate);
3548
3549 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3550 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3551
3552 return pixel_rate;
3553}
3554
3555static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3556 struct intel_crtc_state *cstate,
3557 struct intel_plane_state *intel_pstate,
3558 uint16_t ddb_allocation,
3559 int level,
3560 uint16_t *out_blocks, /* out */
3561 uint8_t *out_lines, /* out */
3562 bool *enabled /* out */)
3563{
3564 struct drm_plane_state *pstate = &intel_pstate->base;
3565 struct drm_framebuffer *fb = pstate->fb;
3566 uint32_t latency = dev_priv->wm.skl_latency[level];
3567 uint32_t method1, method2;
3568 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3569 uint32_t res_blocks, res_lines;
3570 uint32_t selected_result;
3571 uint8_t cpp;
3572 uint32_t width = 0, height = 0;
3573 uint32_t plane_pixel_rate;
3574 uint32_t y_tile_minimum, y_min_scanlines;
3575 struct intel_atomic_state *state =
3576 to_intel_atomic_state(cstate->base.state);
3577 bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
3578
3579 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
3580 *enabled = false;
3581 return 0;
3582 }
3583
3584 if (apply_memory_bw_wa && fb->modifier == I915_FORMAT_MOD_X_TILED)
3585 latency += 15;
3586
3587 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3588 height = drm_rect_height(&intel_pstate->base.src) >> 16;
3589
3590 if (drm_rotation_90_or_270(pstate->rotation))
3591 swap(width, height);
3592
3593 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3594 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3595
3596 if (drm_rotation_90_or_270(pstate->rotation)) {
3597 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3598 drm_format_plane_cpp(fb->pixel_format, 1) :
3599 drm_format_plane_cpp(fb->pixel_format, 0);
3600
3601 switch (cpp) {
3602 case 1:
3603 y_min_scanlines = 16;
3604 break;
3605 case 2:
3606 y_min_scanlines = 8;
3607 break;
3608 case 4:
3609 y_min_scanlines = 4;
3610 break;
3611 default:
3612 MISSING_CASE(cpp);
3613 return -EINVAL;
3614 }
3615 } else {
3616 y_min_scanlines = 4;
3617 }
3618
3619 if (apply_memory_bw_wa)
3620 y_min_scanlines *= 2;
3621
3622 plane_bytes_per_line = width * cpp;
3623 if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
3624 fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
3625 plane_blocks_per_line =
3626 DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3627 plane_blocks_per_line /= y_min_scanlines;
3628 } else if (fb->modifier == DRM_FORMAT_MOD_NONE) {
3629 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3630 + 1;
3631 } else {
3632 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3633 }
3634
3635 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3636 method2 = skl_wm_method2(plane_pixel_rate,
3637 cstate->base.adjusted_mode.crtc_htotal,
3638 latency,
3639 plane_blocks_per_line);
3640
3641 y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
3642
3643 if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
3644 fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
3645 selected_result = max(method2, y_tile_minimum);
3646 } else {
3647 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3648 (plane_bytes_per_line / 512 < 1))
3649 selected_result = method2;
3650 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
3651 selected_result = min(method1, method2);
3652 else
3653 selected_result = method1;
3654 }
3655
3656 res_blocks = selected_result + 1;
3657 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3658
3659 if (level >= 1 && level <= 7) {
3660 if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
3661 fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
3662 res_blocks += y_tile_minimum;
3663 res_lines += y_min_scanlines;
3664 } else {
3665 res_blocks++;
3666 }
3667 }
3668
3669 if (res_blocks >= ddb_allocation || res_lines > 31) {
3670 *enabled = false;
3671
3672 /*
3673 * If there are no valid level 0 watermarks, then we can't
3674 * support this display configuration.
3675 */
3676 if (level) {
3677 return 0;
3678 } else {
3679 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3680 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3681 to_intel_crtc(cstate->base.crtc)->pipe,
3682 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3683 res_blocks, ddb_allocation, res_lines);
3684
3685 return -EINVAL;
3686 }
3687 }
3688
3689 *out_blocks = res_blocks;
3690 *out_lines = res_lines;
3691 *enabled = true;
3692
3693 return 0;
3694}
3695
3696static int
3697skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3698 struct skl_ddb_allocation *ddb,
3699 struct intel_crtc_state *cstate,
3700 struct intel_plane *intel_plane,
3701 int level,
3702 struct skl_wm_level *result)
3703{
3704 struct drm_atomic_state *state = cstate->base.state;
3705 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3706 struct drm_plane *plane = &intel_plane->base;
3707 struct intel_plane_state *intel_pstate = NULL;
3708 uint16_t ddb_blocks;
3709 enum pipe pipe = intel_crtc->pipe;
3710 int ret;
3711 int i = skl_wm_plane_id(intel_plane);
3712
3713 if (state)
3714 intel_pstate =
3715 intel_atomic_get_existing_plane_state(state,
3716 intel_plane);
3717
3718 /*
3719 * Note: If we start supporting multiple pending atomic commits against
3720 * the same planes/CRTC's in the future, plane->state will no longer be
3721 * the correct pre-state to use for the calculations here and we'll
3722 * need to change where we get the 'unchanged' plane data from.
3723 *
3724 * For now this is fine because we only allow one queued commit against
3725 * a CRTC. Even if the plane isn't modified by this transaction and we
3726 * don't have a plane lock, we still have the CRTC's lock, so we know
3727 * that no other transactions are racing with us to update it.
3728 */
3729 if (!intel_pstate)
3730 intel_pstate = to_intel_plane_state(plane->state);
3731
3732 WARN_ON(!intel_pstate->base.fb);
3733
3734 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3735
3736 ret = skl_compute_plane_wm(dev_priv,
3737 cstate,
3738 intel_pstate,
3739 ddb_blocks,
3740 level,
3741 &result->plane_res_b,
3742 &result->plane_res_l,
3743 &result->plane_en);
3744 if (ret)
3745 return ret;
3746
3747 return 0;
3748}
3749
3750static uint32_t
3751skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3752{
3753 uint32_t pixel_rate;
3754
3755 if (!cstate->base.active)
3756 return 0;
3757
3758 pixel_rate = ilk_pipe_pixel_rate(cstate);
3759
3760 if (WARN_ON(pixel_rate == 0))
3761 return 0;
3762
3763 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3764 pixel_rate);
3765}
3766
3767static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3768 struct skl_wm_level *trans_wm /* out */)
3769{
3770 if (!cstate->base.active)
3771 return;
3772
3773 /* Until we know more, just disable transition WMs */
3774 trans_wm->plane_en = false;
3775}
3776
3777static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3778 struct skl_ddb_allocation *ddb,
3779 struct skl_pipe_wm *pipe_wm)
3780{
3781 struct drm_device *dev = cstate->base.crtc->dev;
3782 const struct drm_i915_private *dev_priv = to_i915(dev);
3783 struct intel_plane *intel_plane;
3784 struct skl_plane_wm *wm;
3785 int level, max_level = ilk_wm_max_level(dev_priv);
3786 int ret;
3787
3788 /*
3789 * We'll only calculate watermarks for planes that are actually
3790 * enabled, so make sure all other planes are set as disabled.
3791 */
3792 memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3793
3794 for_each_intel_plane_mask(&dev_priv->drm,
3795 intel_plane,
3796 cstate->base.plane_mask) {
3797 wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
3798
3799 for (level = 0; level <= max_level; level++) {
3800 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3801 intel_plane, level,
3802 &wm->wm[level]);
3803 if (ret)
3804 return ret;
3805 }
3806 skl_compute_transition_wm(cstate, &wm->trans_wm);
3807 }
3808 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3809
3810 return 0;
3811}
3812
3813static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3814 i915_reg_t reg,
3815 const struct skl_ddb_entry *entry)
3816{
3817 if (entry->end)
3818 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3819 else
3820 I915_WRITE(reg, 0);
3821}
3822
3823static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3824 i915_reg_t reg,
3825 const struct skl_wm_level *level)
3826{
3827 uint32_t val = 0;
3828
3829 if (level->plane_en) {
3830 val |= PLANE_WM_EN;
3831 val |= level->plane_res_b;
3832 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3833 }
3834
3835 I915_WRITE(reg, val);
3836}
3837
3838static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3839 const struct skl_plane_wm *wm,
3840 const struct skl_ddb_allocation *ddb,
3841 int plane)
3842{
3843 struct drm_crtc *crtc = &intel_crtc->base;
3844 struct drm_device *dev = crtc->dev;
3845 struct drm_i915_private *dev_priv = to_i915(dev);
3846 int level, max_level = ilk_wm_max_level(dev_priv);
3847 enum pipe pipe = intel_crtc->pipe;
3848
3849 for (level = 0; level <= max_level; level++) {
3850 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane, level),
3851 &wm->wm[level]);
3852 }
3853 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane),
3854 &wm->trans_wm);
3855
3856 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3857 &ddb->plane[pipe][plane]);
3858 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3859 &ddb->y_plane[pipe][plane]);
3860}
3861
3862static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3863 const struct skl_plane_wm *wm,
3864 const struct skl_ddb_allocation *ddb)
3865{
3866 struct drm_crtc *crtc = &intel_crtc->base;
3867 struct drm_device *dev = crtc->dev;
3868 struct drm_i915_private *dev_priv = to_i915(dev);
3869 int level, max_level = ilk_wm_max_level(dev_priv);
3870 enum pipe pipe = intel_crtc->pipe;
3871
3872 for (level = 0; level <= max_level; level++) {
3873 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3874 &wm->wm[level]);
3875 }
3876 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
3877
3878 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3879 &ddb->plane[pipe][PLANE_CURSOR]);
3880}
3881
3882bool skl_wm_level_equals(const struct skl_wm_level *l1,
3883 const struct skl_wm_level *l2)
3884{
3885 if (l1->plane_en != l2->plane_en)
3886 return false;
3887
3888 /* If both planes aren't enabled, the rest shouldn't matter */
3889 if (!l1->plane_en)
3890 return true;
3891
3892 return (l1->plane_res_l == l2->plane_res_l &&
3893 l1->plane_res_b == l2->plane_res_b);
3894}
3895
3896static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3897 const struct skl_ddb_entry *b)
3898{
3899 return a->start < b->end && b->start < a->end;
3900}
3901
3902bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
3903 const struct skl_ddb_entry *ddb,
3904 int ignore)
3905{
3906 int i;
3907
3908 for (i = 0; i < I915_MAX_PIPES; i++)
3909 if (i != ignore && entries[i] &&
3910 skl_ddb_entries_overlap(ddb, entries[i]))
3911 return true;
3912
3913 return false;
3914}
3915
3916static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3917 const struct skl_pipe_wm *old_pipe_wm,
3918 struct skl_pipe_wm *pipe_wm, /* out */
3919 struct skl_ddb_allocation *ddb, /* out */
3920 bool *changed /* out */)
3921{
3922 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3923 int ret;
3924
3925 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3926 if (ret)
3927 return ret;
3928
3929 if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
3930 *changed = false;
3931 else
3932 *changed = true;
3933
3934 return 0;
3935}
3936
3937static uint32_t
3938pipes_modified(struct drm_atomic_state *state)
3939{
3940 struct drm_crtc *crtc;
3941 struct drm_crtc_state *cstate;
3942 uint32_t i, ret = 0;
3943
3944 for_each_crtc_in_state(state, crtc, cstate, i)
3945 ret |= drm_crtc_mask(crtc);
3946
3947 return ret;
3948}
3949
3950static int
3951skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3952{
3953 struct drm_atomic_state *state = cstate->base.state;
3954 struct drm_device *dev = state->dev;
3955 struct drm_crtc *crtc = cstate->base.crtc;
3956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3957 struct drm_i915_private *dev_priv = to_i915(dev);
3958 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3959 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3960 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3961 struct drm_plane_state *plane_state;
3962 struct drm_plane *plane;
3963 enum pipe pipe = intel_crtc->pipe;
3964 int id;
3965
3966 WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3967
3968 drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
3969 id = skl_wm_plane_id(to_intel_plane(plane));
3970
3971 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
3972 &new_ddb->plane[pipe][id]) &&
3973 skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
3974 &new_ddb->y_plane[pipe][id]))
3975 continue;
3976
3977 plane_state = drm_atomic_get_plane_state(state, plane);
3978 if (IS_ERR(plane_state))
3979 return PTR_ERR(plane_state);
3980 }
3981
3982 return 0;
3983}
3984
3985static int
3986skl_compute_ddb(struct drm_atomic_state *state)
3987{
3988 struct drm_device *dev = state->dev;
3989 struct drm_i915_private *dev_priv = to_i915(dev);
3990 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3991 struct intel_crtc *intel_crtc;
3992 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
3993 uint32_t realloc_pipes = pipes_modified(state);
3994 int ret;
3995
3996 /*
3997 * If this is our first atomic update following hardware readout,
3998 * we can't trust the DDB that the BIOS programmed for us. Let's
3999 * pretend that all pipes switched active status so that we'll
4000 * ensure a full DDB recompute.
4001 */
4002 if (dev_priv->wm.distrust_bios_wm) {
4003 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4004 state->acquire_ctx);
4005 if (ret)
4006 return ret;
4007
4008 intel_state->active_pipe_changes = ~0;
4009
4010 /*
4011 * We usually only initialize intel_state->active_crtcs if we
4012 * we're doing a modeset; make sure this field is always
4013 * initialized during the sanitization process that happens
4014 * on the first commit too.
4015 */
4016 if (!intel_state->modeset)
4017 intel_state->active_crtcs = dev_priv->active_crtcs;
4018 }
4019
4020 /*
4021 * If the modeset changes which CRTC's are active, we need to
4022 * recompute the DDB allocation for *all* active pipes, even
4023 * those that weren't otherwise being modified in any way by this
4024 * atomic commit. Due to the shrinking of the per-pipe allocations
4025 * when new active CRTC's are added, it's possible for a pipe that
4026 * we were already using and aren't changing at all here to suddenly
4027 * become invalid if its DDB needs exceeds its new allocation.
4028 *
4029 * Note that if we wind up doing a full DDB recompute, we can't let
4030 * any other display updates race with this transaction, so we need
4031 * to grab the lock on *all* CRTC's.
4032 */
4033 if (intel_state->active_pipe_changes) {
4034 realloc_pipes = ~0;
4035 intel_state->wm_results.dirty_pipes = ~0;
4036 }
4037
4038 /*
4039 * We're not recomputing for the pipes not included in the commit, so
4040 * make sure we start with the current state.
4041 */
4042 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4043
4044 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4045 struct intel_crtc_state *cstate;
4046
4047 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4048 if (IS_ERR(cstate))
4049 return PTR_ERR(cstate);
4050
4051 ret = skl_allocate_pipe_ddb(cstate, ddb);
4052 if (ret)
4053 return ret;
4054
4055 ret = skl_ddb_add_affected_planes(cstate);
4056 if (ret)
4057 return ret;
4058 }
4059
4060 return 0;
4061}
4062
4063static void
4064skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4065 struct skl_wm_values *src,
4066 enum pipe pipe)
4067{
4068 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4069 sizeof(dst->ddb.y_plane[pipe]));
4070 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4071 sizeof(dst->ddb.plane[pipe]));
4072}
4073
4074static void
4075skl_print_wm_changes(const struct drm_atomic_state *state)
4076{
4077 const struct drm_device *dev = state->dev;
4078 const struct drm_i915_private *dev_priv = to_i915(dev);
4079 const struct intel_atomic_state *intel_state =
4080 to_intel_atomic_state(state);
4081 const struct drm_crtc *crtc;
4082 const struct drm_crtc_state *cstate;
4083 const struct intel_plane *intel_plane;
4084 const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4085 const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4086 int id;
4087 int i;
4088
4089 for_each_crtc_in_state(state, crtc, cstate, i) {
4090 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4091 enum pipe pipe = intel_crtc->pipe;
4092
4093 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4094 const struct skl_ddb_entry *old, *new;
4095
4096 id = skl_wm_plane_id(intel_plane);
4097 old = &old_ddb->plane[pipe][id];
4098 new = &new_ddb->plane[pipe][id];
4099
4100 if (skl_ddb_entry_equal(old, new))
4101 continue;
4102
4103 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4104 intel_plane->base.base.id,
4105 intel_plane->base.name,
4106 old->start, old->end,
4107 new->start, new->end);
4108 }
4109 }
4110}
4111
4112static int
4113skl_compute_wm(struct drm_atomic_state *state)
4114{
4115 struct drm_crtc *crtc;
4116 struct drm_crtc_state *cstate;
4117 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4118 struct skl_wm_values *results = &intel_state->wm_results;
4119 struct skl_pipe_wm *pipe_wm;
4120 bool changed = false;
4121 int ret, i;
4122
4123 /*
4124 * If this transaction isn't actually touching any CRTC's, don't
4125 * bother with watermark calculation. Note that if we pass this
4126 * test, we're guaranteed to hold at least one CRTC state mutex,
4127 * which means we can safely use values like dev_priv->active_crtcs
4128 * since any racing commits that want to update them would need to
4129 * hold _all_ CRTC state mutexes.
4130 */
4131 for_each_crtc_in_state(state, crtc, cstate, i)
4132 changed = true;
4133 if (!changed)
4134 return 0;
4135
4136 /* Clear all dirty flags */
4137 results->dirty_pipes = 0;
4138
4139 ret = skl_compute_ddb(state);
4140 if (ret)
4141 return ret;
4142
4143 /*
4144 * Calculate WM's for all pipes that are part of this transaction.
4145 * Note that the DDB allocation above may have added more CRTC's that
4146 * weren't otherwise being modified (and set bits in dirty_pipes) if
4147 * pipe allocations had to change.
4148 *
4149 * FIXME: Now that we're doing this in the atomic check phase, we
4150 * should allow skl_update_pipe_wm() to return failure in cases where
4151 * no suitable watermark values can be found.
4152 */
4153 for_each_crtc_in_state(state, crtc, cstate, i) {
4154 struct intel_crtc_state *intel_cstate =
4155 to_intel_crtc_state(cstate);
4156 const struct skl_pipe_wm *old_pipe_wm =
4157 &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
4158
4159 pipe_wm = &intel_cstate->wm.skl.optimal;
4160 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4161 &results->ddb, &changed);
4162 if (ret)
4163 return ret;
4164
4165 if (changed)
4166 results->dirty_pipes |= drm_crtc_mask(crtc);
4167
4168 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4169 /* This pipe's WM's did not change */
4170 continue;
4171
4172 intel_cstate->update_wm_pre = true;
4173 }
4174
4175 skl_print_wm_changes(state);
4176
4177 return 0;
4178}
4179
4180static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
4181 struct intel_crtc_state *cstate)
4182{
4183 struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
4184 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4185 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4186 const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
4187 enum pipe pipe = crtc->pipe;
4188 int plane;
4189
4190 if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
4191 return;
4192
4193 I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
4194
4195 for_each_universal_plane(dev_priv, pipe, plane)
4196 skl_write_plane_wm(crtc, &pipe_wm->planes[plane], ddb, plane);
4197
4198 skl_write_cursor_wm(crtc, &pipe_wm->planes[PLANE_CURSOR], ddb);
4199}
4200
4201static void skl_initial_wm(struct intel_atomic_state *state,
4202 struct intel_crtc_state *cstate)
4203{
4204 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4205 struct drm_device *dev = intel_crtc->base.dev;
4206 struct drm_i915_private *dev_priv = to_i915(dev);
4207 struct skl_wm_values *results = &state->wm_results;
4208 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4209 enum pipe pipe = intel_crtc->pipe;
4210
4211 if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
4212 return;
4213
4214 mutex_lock(&dev_priv->wm.wm_mutex);
4215
4216 if (cstate->base.active_changed)
4217 skl_atomic_update_crtc_wm(state, cstate);
4218
4219 skl_copy_wm_for_pipe(hw_vals, results, pipe);
4220
4221 mutex_unlock(&dev_priv->wm.wm_mutex);
4222}
4223
4224static void ilk_compute_wm_config(struct drm_device *dev,
4225 struct intel_wm_config *config)
4226{
4227 struct intel_crtc *crtc;
4228
4229 /* Compute the currently _active_ config */
4230 for_each_intel_crtc(dev, crtc) {
4231 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4232
4233 if (!wm->pipe_enabled)
4234 continue;
4235
4236 config->sprites_enabled |= wm->sprites_enabled;
4237 config->sprites_scaled |= wm->sprites_scaled;
4238 config->num_pipes_active++;
4239 }
4240}
4241
4242static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4243{
4244 struct drm_device *dev = &dev_priv->drm;
4245 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4246 struct ilk_wm_maximums max;
4247 struct intel_wm_config config = {};
4248 struct ilk_wm_values results = {};
4249 enum intel_ddb_partitioning partitioning;
4250
4251 ilk_compute_wm_config(dev, &config);
4252
4253 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4254 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4255
4256 /* 5/6 split only in single pipe config on IVB+ */
4257 if (INTEL_GEN(dev_priv) >= 7 &&
4258 config.num_pipes_active == 1 && config.sprites_enabled) {
4259 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4260 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4261
4262 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4263 } else {
4264 best_lp_wm = &lp_wm_1_2;
4265 }
4266
4267 partitioning = (best_lp_wm == &lp_wm_1_2) ?
4268 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4269
4270 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4271
4272 ilk_write_wm_values(dev_priv, &results);
4273}
4274
4275static void ilk_initial_watermarks(struct intel_atomic_state *state,
4276 struct intel_crtc_state *cstate)
4277{
4278 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4279 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4280
4281 mutex_lock(&dev_priv->wm.wm_mutex);
4282 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4283 ilk_program_watermarks(dev_priv);
4284 mutex_unlock(&dev_priv->wm.wm_mutex);
4285}
4286
4287static void ilk_optimize_watermarks(struct intel_atomic_state *state,
4288 struct intel_crtc_state *cstate)
4289{
4290 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4291 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4292
4293 mutex_lock(&dev_priv->wm.wm_mutex);
4294 if (cstate->wm.need_postvbl_update) {
4295 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4296 ilk_program_watermarks(dev_priv);
4297 }
4298 mutex_unlock(&dev_priv->wm.wm_mutex);
4299}
4300
4301static inline void skl_wm_level_from_reg_val(uint32_t val,
4302 struct skl_wm_level *level)
4303{
4304 level->plane_en = val & PLANE_WM_EN;
4305 level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4306 level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4307 PLANE_WM_LINES_MASK;
4308}
4309
4310void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4311 struct skl_pipe_wm *out)
4312{
4313 struct drm_device *dev = crtc->dev;
4314 struct drm_i915_private *dev_priv = to_i915(dev);
4315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4316 struct intel_plane *intel_plane;
4317 struct skl_plane_wm *wm;
4318 enum pipe pipe = intel_crtc->pipe;
4319 int level, id, max_level;
4320 uint32_t val;
4321
4322 max_level = ilk_wm_max_level(dev_priv);
4323
4324 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4325 id = skl_wm_plane_id(intel_plane);
4326 wm = &out->planes[id];
4327
4328 for (level = 0; level <= max_level; level++) {
4329 if (id != PLANE_CURSOR)
4330 val = I915_READ(PLANE_WM(pipe, id, level));
4331 else
4332 val = I915_READ(CUR_WM(pipe, level));
4333
4334 skl_wm_level_from_reg_val(val, &wm->wm[level]);
4335 }
4336
4337 if (id != PLANE_CURSOR)
4338 val = I915_READ(PLANE_WM_TRANS(pipe, id));
4339 else
4340 val = I915_READ(CUR_WM_TRANS(pipe));
4341
4342 skl_wm_level_from_reg_val(val, &wm->trans_wm);
4343 }
4344
4345 if (!intel_crtc->active)
4346 return;
4347
4348 out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
4349}
4350
4351void skl_wm_get_hw_state(struct drm_device *dev)
4352{
4353 struct drm_i915_private *dev_priv = to_i915(dev);
4354 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4355 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4356 struct drm_crtc *crtc;
4357 struct intel_crtc *intel_crtc;
4358 struct intel_crtc_state *cstate;
4359
4360 skl_ddb_get_hw_state(dev_priv, ddb);
4361 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4362 intel_crtc = to_intel_crtc(crtc);
4363 cstate = to_intel_crtc_state(crtc->state);
4364
4365 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4366
4367 if (intel_crtc->active)
4368 hw->dirty_pipes |= drm_crtc_mask(crtc);
4369 }
4370
4371 if (dev_priv->active_crtcs) {
4372 /* Fully recompute DDB on first atomic commit */
4373 dev_priv->wm.distrust_bios_wm = true;
4374 } else {
4375 /* Easy/common case; just sanitize DDB now if everything off */
4376 memset(ddb, 0, sizeof(*ddb));
4377 }
4378}
4379
4380static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4381{
4382 struct drm_device *dev = crtc->dev;
4383 struct drm_i915_private *dev_priv = to_i915(dev);
4384 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4386 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4387 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4388 enum pipe pipe = intel_crtc->pipe;
4389 static const i915_reg_t wm0_pipe_reg[] = {
4390 [PIPE_A] = WM0_PIPEA_ILK,
4391 [PIPE_B] = WM0_PIPEB_ILK,
4392 [PIPE_C] = WM0_PIPEC_IVB,
4393 };
4394
4395 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4396 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4397 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4398
4399 memset(active, 0, sizeof(*active));
4400
4401 active->pipe_enabled = intel_crtc->active;
4402
4403 if (active->pipe_enabled) {
4404 u32 tmp = hw->wm_pipe[pipe];
4405
4406 /*
4407 * For active pipes LP0 watermark is marked as
4408 * enabled, and LP1+ watermaks as disabled since
4409 * we can't really reverse compute them in case
4410 * multiple pipes are active.
4411 */
4412 active->wm[0].enable = true;
4413 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4414 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4415 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4416 active->linetime = hw->wm_linetime[pipe];
4417 } else {
4418 int level, max_level = ilk_wm_max_level(dev_priv);
4419
4420 /*
4421 * For inactive pipes, all watermark levels
4422 * should be marked as enabled but zeroed,
4423 * which is what we'd compute them to.
4424 */
4425 for (level = 0; level <= max_level; level++)
4426 active->wm[level].enable = true;
4427 }
4428
4429 intel_crtc->wm.active.ilk = *active;
4430}
4431
4432#define _FW_WM(value, plane) \
4433 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4434#define _FW_WM_VLV(value, plane) \
4435 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4436
4437static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4438 struct vlv_wm_values *wm)
4439{
4440 enum pipe pipe;
4441 uint32_t tmp;
4442
4443 for_each_pipe(dev_priv, pipe) {
4444 tmp = I915_READ(VLV_DDL(pipe));
4445
4446 wm->ddl[pipe].primary =
4447 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4448 wm->ddl[pipe].cursor =
4449 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4450 wm->ddl[pipe].sprite[0] =
4451 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4452 wm->ddl[pipe].sprite[1] =
4453 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4454 }
4455
4456 tmp = I915_READ(DSPFW1);
4457 wm->sr.plane = _FW_WM(tmp, SR);
4458 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4459 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4460 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4461
4462 tmp = I915_READ(DSPFW2);
4463 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4464 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4465 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4466
4467 tmp = I915_READ(DSPFW3);
4468 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4469
4470 if (IS_CHERRYVIEW(dev_priv)) {
4471 tmp = I915_READ(DSPFW7_CHV);
4472 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4473 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4474
4475 tmp = I915_READ(DSPFW8_CHV);
4476 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4477 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4478
4479 tmp = I915_READ(DSPFW9_CHV);
4480 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4481 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4482
4483 tmp = I915_READ(DSPHOWM);
4484 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4485 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4486 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4487 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4488 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4489 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4490 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4491 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4492 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4493 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4494 } else {
4495 tmp = I915_READ(DSPFW7);
4496 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4497 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4498
4499 tmp = I915_READ(DSPHOWM);
4500 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4501 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4502 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4503 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4504 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4505 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4506 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4507 }
4508}
4509
4510#undef _FW_WM
4511#undef _FW_WM_VLV
4512
4513void vlv_wm_get_hw_state(struct drm_device *dev)
4514{
4515 struct drm_i915_private *dev_priv = to_i915(dev);
4516 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4517 struct intel_plane *plane;
4518 enum pipe pipe;
4519 u32 val;
4520
4521 vlv_read_wm_values(dev_priv, wm);
4522
4523 for_each_intel_plane(dev, plane) {
4524 switch (plane->base.type) {
4525 int sprite;
4526 case DRM_PLANE_TYPE_CURSOR:
4527 plane->wm.fifo_size = 63;
4528 break;
4529 case DRM_PLANE_TYPE_PRIMARY:
4530 plane->wm.fifo_size = vlv_get_fifo_size(dev_priv, plane->pipe, 0);
4531 break;
4532 case DRM_PLANE_TYPE_OVERLAY:
4533 sprite = plane->plane;
4534 plane->wm.fifo_size = vlv_get_fifo_size(dev_priv, plane->pipe, sprite + 1);
4535 break;
4536 }
4537 }
4538
4539 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4540 wm->level = VLV_WM_LEVEL_PM2;
4541
4542 if (IS_CHERRYVIEW(dev_priv)) {
4543 mutex_lock(&dev_priv->rps.hw_lock);
4544
4545 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4546 if (val & DSP_MAXFIFO_PM5_ENABLE)
4547 wm->level = VLV_WM_LEVEL_PM5;
4548
4549 /*
4550 * If DDR DVFS is disabled in the BIOS, Punit
4551 * will never ack the request. So if that happens
4552 * assume we don't have to enable/disable DDR DVFS
4553 * dynamically. To test that just set the REQ_ACK
4554 * bit to poke the Punit, but don't change the
4555 * HIGH/LOW bits so that we don't actually change
4556 * the current state.
4557 */
4558 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4559 val |= FORCE_DDR_FREQ_REQ_ACK;
4560 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4561
4562 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4563 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4564 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4565 "assuming DDR DVFS is disabled\n");
4566 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4567 } else {
4568 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4569 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4570 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4571 }
4572
4573 mutex_unlock(&dev_priv->rps.hw_lock);
4574 }
4575
4576 for_each_pipe(dev_priv, pipe)
4577 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4578 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4579 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4580
4581 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4582 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4583}
4584
4585void ilk_wm_get_hw_state(struct drm_device *dev)
4586{
4587 struct drm_i915_private *dev_priv = to_i915(dev);
4588 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4589 struct drm_crtc *crtc;
4590
4591 for_each_crtc(dev, crtc)
4592 ilk_pipe_wm_get_hw_state(crtc);
4593
4594 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4595 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4596 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4597
4598 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4599 if (INTEL_GEN(dev_priv) >= 7) {
4600 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4601 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4602 }
4603
4604 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4605 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4606 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4607 else if (IS_IVYBRIDGE(dev_priv))
4608 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4609 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4610
4611 hw->enable_fbc_wm =
4612 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4613}
4614
4615/**
4616 * intel_update_watermarks - update FIFO watermark values based on current modes
4617 *
4618 * Calculate watermark values for the various WM regs based on current mode
4619 * and plane configuration.
4620 *
4621 * There are several cases to deal with here:
4622 * - normal (i.e. non-self-refresh)
4623 * - self-refresh (SR) mode
4624 * - lines are large relative to FIFO size (buffer can hold up to 2)
4625 * - lines are small relative to FIFO size (buffer can hold more than 2
4626 * lines), so need to account for TLB latency
4627 *
4628 * The normal calculation is:
4629 * watermark = dotclock * bytes per pixel * latency
4630 * where latency is platform & configuration dependent (we assume pessimal
4631 * values here).
4632 *
4633 * The SR calculation is:
4634 * watermark = (trunc(latency/line time)+1) * surface width *
4635 * bytes per pixel
4636 * where
4637 * line time = htotal / dotclock
4638 * surface width = hdisplay for normal plane and 64 for cursor
4639 * and latency is assumed to be high, as above.
4640 *
4641 * The final value programmed to the register should always be rounded up,
4642 * and include an extra 2 entries to account for clock crossings.
4643 *
4644 * We don't use the sprite, so we can ignore that. And on Crestline we have
4645 * to set the non-SR watermarks to 8.
4646 */
4647void intel_update_watermarks(struct intel_crtc *crtc)
4648{
4649 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4650
4651 if (dev_priv->display.update_wm)
4652 dev_priv->display.update_wm(crtc);
4653}
4654
4655/*
4656 * Lock protecting IPS related data structures
4657 */
4658DEFINE_SPINLOCK(mchdev_lock);
4659
4660/* Global for IPS driver to get at the current i915 device. Protected by
4661 * mchdev_lock. */
4662static struct drm_i915_private *i915_mch_dev;
4663
4664bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4665{
4666 u16 rgvswctl;
4667
4668 assert_spin_locked(&mchdev_lock);
4669
4670 rgvswctl = I915_READ16(MEMSWCTL);
4671 if (rgvswctl & MEMCTL_CMD_STS) {
4672 DRM_DEBUG("gpu busy, RCS change rejected\n");
4673 return false; /* still busy with another command */
4674 }
4675
4676 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4677 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4678 I915_WRITE16(MEMSWCTL, rgvswctl);
4679 POSTING_READ16(MEMSWCTL);
4680
4681 rgvswctl |= MEMCTL_CMD_STS;
4682 I915_WRITE16(MEMSWCTL, rgvswctl);
4683
4684 return true;
4685}
4686
4687static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4688{
4689 u32 rgvmodectl;
4690 u8 fmax, fmin, fstart, vstart;
4691
4692 spin_lock_irq(&mchdev_lock);
4693
4694 rgvmodectl = I915_READ(MEMMODECTL);
4695
4696 /* Enable temp reporting */
4697 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4698 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4699
4700 /* 100ms RC evaluation intervals */
4701 I915_WRITE(RCUPEI, 100000);
4702 I915_WRITE(RCDNEI, 100000);
4703
4704 /* Set max/min thresholds to 90ms and 80ms respectively */
4705 I915_WRITE(RCBMAXAVG, 90000);
4706 I915_WRITE(RCBMINAVG, 80000);
4707
4708 I915_WRITE(MEMIHYST, 1);
4709
4710 /* Set up min, max, and cur for interrupt handling */
4711 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4712 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4713 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4714 MEMMODE_FSTART_SHIFT;
4715
4716 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4717 PXVFREQ_PX_SHIFT;
4718
4719 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4720 dev_priv->ips.fstart = fstart;
4721
4722 dev_priv->ips.max_delay = fstart;
4723 dev_priv->ips.min_delay = fmin;
4724 dev_priv->ips.cur_delay = fstart;
4725
4726 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4727 fmax, fmin, fstart);
4728
4729 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4730
4731 /*
4732 * Interrupts will be enabled in ironlake_irq_postinstall
4733 */
4734
4735 I915_WRITE(VIDSTART, vstart);
4736 POSTING_READ(VIDSTART);
4737
4738 rgvmodectl |= MEMMODE_SWMODE_EN;
4739 I915_WRITE(MEMMODECTL, rgvmodectl);
4740
4741 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4742 DRM_ERROR("stuck trying to change perf mode\n");
4743 mdelay(1);
4744
4745 ironlake_set_drps(dev_priv, fstart);
4746
4747 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4748 I915_READ(DDREC) + I915_READ(CSIEC);
4749 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4750 dev_priv->ips.last_count2 = I915_READ(GFXEC);
4751 dev_priv->ips.last_time2 = ktime_get_raw_ns();
4752
4753 spin_unlock_irq(&mchdev_lock);
4754}
4755
4756static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4757{
4758 u16 rgvswctl;
4759
4760 spin_lock_irq(&mchdev_lock);
4761
4762 rgvswctl = I915_READ16(MEMSWCTL);
4763
4764 /* Ack interrupts, disable EFC interrupt */
4765 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4766 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4767 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4768 I915_WRITE(DEIIR, DE_PCU_EVENT);
4769 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4770
4771 /* Go back to the starting frequency */
4772 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4773 mdelay(1);
4774 rgvswctl |= MEMCTL_CMD_STS;
4775 I915_WRITE(MEMSWCTL, rgvswctl);
4776 mdelay(1);
4777
4778 spin_unlock_irq(&mchdev_lock);
4779}
4780
4781/* There's a funny hw issue where the hw returns all 0 when reading from
4782 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4783 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4784 * all limits and the gpu stuck at whatever frequency it is at atm).
4785 */
4786static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4787{
4788 u32 limits;
4789
4790 /* Only set the down limit when we've reached the lowest level to avoid
4791 * getting more interrupts, otherwise leave this clear. This prevents a
4792 * race in the hw when coming out of rc6: There's a tiny window where
4793 * the hw runs at the minimal clock before selecting the desired
4794 * frequency, if the down threshold expires in that window we will not
4795 * receive a down interrupt. */
4796 if (IS_GEN9(dev_priv)) {
4797 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4798 if (val <= dev_priv->rps.min_freq_softlimit)
4799 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4800 } else {
4801 limits = dev_priv->rps.max_freq_softlimit << 24;
4802 if (val <= dev_priv->rps.min_freq_softlimit)
4803 limits |= dev_priv->rps.min_freq_softlimit << 16;
4804 }
4805
4806 return limits;
4807}
4808
4809static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4810{
4811 int new_power;
4812 u32 threshold_up = 0, threshold_down = 0; /* in % */
4813 u32 ei_up = 0, ei_down = 0;
4814
4815 new_power = dev_priv->rps.power;
4816 switch (dev_priv->rps.power) {
4817 case LOW_POWER:
4818 if (val > dev_priv->rps.efficient_freq + 1 &&
4819 val > dev_priv->rps.cur_freq)
4820 new_power = BETWEEN;
4821 break;
4822
4823 case BETWEEN:
4824 if (val <= dev_priv->rps.efficient_freq &&
4825 val < dev_priv->rps.cur_freq)
4826 new_power = LOW_POWER;
4827 else if (val >= dev_priv->rps.rp0_freq &&
4828 val > dev_priv->rps.cur_freq)
4829 new_power = HIGH_POWER;
4830 break;
4831
4832 case HIGH_POWER:
4833 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4834 val < dev_priv->rps.cur_freq)
4835 new_power = BETWEEN;
4836 break;
4837 }
4838 /* Max/min bins are special */
4839 if (val <= dev_priv->rps.min_freq_softlimit)
4840 new_power = LOW_POWER;
4841 if (val >= dev_priv->rps.max_freq_softlimit)
4842 new_power = HIGH_POWER;
4843 if (new_power == dev_priv->rps.power)
4844 return;
4845
4846 /* Note the units here are not exactly 1us, but 1280ns. */
4847 switch (new_power) {
4848 case LOW_POWER:
4849 /* Upclock if more than 95% busy over 16ms */
4850 ei_up = 16000;
4851 threshold_up = 95;
4852
4853 /* Downclock if less than 85% busy over 32ms */
4854 ei_down = 32000;
4855 threshold_down = 85;
4856 break;
4857
4858 case BETWEEN:
4859 /* Upclock if more than 90% busy over 13ms */
4860 ei_up = 13000;
4861 threshold_up = 90;
4862
4863 /* Downclock if less than 75% busy over 32ms */
4864 ei_down = 32000;
4865 threshold_down = 75;
4866 break;
4867
4868 case HIGH_POWER:
4869 /* Upclock if more than 85% busy over 10ms */
4870 ei_up = 10000;
4871 threshold_up = 85;
4872
4873 /* Downclock if less than 60% busy over 32ms */
4874 ei_down = 32000;
4875 threshold_down = 60;
4876 break;
4877 }
4878
4879 /* When byt can survive without system hang with dynamic
4880 * sw freq adjustments, this restriction can be lifted.
4881 */
4882 if (IS_VALLEYVIEW(dev_priv))
4883 goto skip_hw_write;
4884
4885 I915_WRITE(GEN6_RP_UP_EI,
4886 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4887 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4888 GT_INTERVAL_FROM_US(dev_priv,
4889 ei_up * threshold_up / 100));
4890
4891 I915_WRITE(GEN6_RP_DOWN_EI,
4892 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4893 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4894 GT_INTERVAL_FROM_US(dev_priv,
4895 ei_down * threshold_down / 100));
4896
4897 I915_WRITE(GEN6_RP_CONTROL,
4898 GEN6_RP_MEDIA_TURBO |
4899 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4900 GEN6_RP_MEDIA_IS_GFX |
4901 GEN6_RP_ENABLE |
4902 GEN6_RP_UP_BUSY_AVG |
4903 GEN6_RP_DOWN_IDLE_AVG);
4904
4905skip_hw_write:
4906 dev_priv->rps.power = new_power;
4907 dev_priv->rps.up_threshold = threshold_up;
4908 dev_priv->rps.down_threshold = threshold_down;
4909 dev_priv->rps.last_adj = 0;
4910}
4911
4912static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4913{
4914 u32 mask = 0;
4915
4916 /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
4917 if (val > dev_priv->rps.min_freq_softlimit)
4918 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4919 if (val < dev_priv->rps.max_freq_softlimit)
4920 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4921
4922 mask &= dev_priv->pm_rps_events;
4923
4924 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4925}
4926
4927/* gen6_set_rps is called to update the frequency request, but should also be
4928 * called when the range (min_delay and max_delay) is modified so that we can
4929 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4930static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4931{
4932 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4933 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4934 return;
4935
4936 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4937 WARN_ON(val > dev_priv->rps.max_freq);
4938 WARN_ON(val < dev_priv->rps.min_freq);
4939
4940 /* min/max delay may still have been modified so be sure to
4941 * write the limits value.
4942 */
4943 if (val != dev_priv->rps.cur_freq) {
4944 gen6_set_rps_thresholds(dev_priv, val);
4945
4946 if (IS_GEN9(dev_priv))
4947 I915_WRITE(GEN6_RPNSWREQ,
4948 GEN9_FREQUENCY(val));
4949 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4950 I915_WRITE(GEN6_RPNSWREQ,
4951 HSW_FREQUENCY(val));
4952 else
4953 I915_WRITE(GEN6_RPNSWREQ,
4954 GEN6_FREQUENCY(val) |
4955 GEN6_OFFSET(0) |
4956 GEN6_AGGRESSIVE_TURBO);
4957 }
4958
4959 /* Make sure we continue to get interrupts
4960 * until we hit the minimum or maximum frequencies.
4961 */
4962 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4963 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4964
4965 POSTING_READ(GEN6_RPNSWREQ);
4966
4967 dev_priv->rps.cur_freq = val;
4968 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4969}
4970
4971static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4972{
4973 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4974 WARN_ON(val > dev_priv->rps.max_freq);
4975 WARN_ON(val < dev_priv->rps.min_freq);
4976
4977 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4978 "Odd GPU freq value\n"))
4979 val &= ~1;
4980
4981 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4982
4983 if (val != dev_priv->rps.cur_freq) {
4984 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4985 if (!IS_CHERRYVIEW(dev_priv))
4986 gen6_set_rps_thresholds(dev_priv, val);
4987 }
4988
4989 dev_priv->rps.cur_freq = val;
4990 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4991}
4992
4993/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4994 *
4995 * * If Gfx is Idle, then
4996 * 1. Forcewake Media well.
4997 * 2. Request idle freq.
4998 * 3. Release Forcewake of Media well.
4999*/
5000static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5001{
5002 u32 val = dev_priv->rps.idle_freq;
5003
5004 if (dev_priv->rps.cur_freq <= val)
5005 return;
5006
5007 /* Wake up the media well, as that takes a lot less
5008 * power than the Render well. */
5009 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
5010 valleyview_set_rps(dev_priv, val);
5011 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
5012}
5013
5014void gen6_rps_busy(struct drm_i915_private *dev_priv)
5015{
5016 mutex_lock(&dev_priv->rps.hw_lock);
5017 if (dev_priv->rps.enabled) {
5018 if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
5019 gen6_rps_reset_ei(dev_priv);
5020 I915_WRITE(GEN6_PMINTRMSK,
5021 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
5022
5023 gen6_enable_rps_interrupts(dev_priv);
5024
5025 /* Ensure we start at the user's desired frequency */
5026 intel_set_rps(dev_priv,
5027 clamp(dev_priv->rps.cur_freq,
5028 dev_priv->rps.min_freq_softlimit,
5029 dev_priv->rps.max_freq_softlimit));
5030 }
5031 mutex_unlock(&dev_priv->rps.hw_lock);
5032}
5033
5034void gen6_rps_idle(struct drm_i915_private *dev_priv)
5035{
5036 /* Flush our bottom-half so that it does not race with us
5037 * setting the idle frequency and so that it is bounded by
5038 * our rpm wakeref. And then disable the interrupts to stop any
5039 * futher RPS reclocking whilst we are asleep.
5040 */
5041 gen6_disable_rps_interrupts(dev_priv);
5042
5043 mutex_lock(&dev_priv->rps.hw_lock);
5044 if (dev_priv->rps.enabled) {
5045 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5046 vlv_set_rps_idle(dev_priv);
5047 else
5048 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5049 dev_priv->rps.last_adj = 0;
5050 I915_WRITE(GEN6_PMINTRMSK,
5051 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
5052 }
5053 mutex_unlock(&dev_priv->rps.hw_lock);
5054
5055 spin_lock(&dev_priv->rps.client_lock);
5056 while (!list_empty(&dev_priv->rps.clients))
5057 list_del_init(dev_priv->rps.clients.next);
5058 spin_unlock(&dev_priv->rps.client_lock);
5059}
5060
5061void gen6_rps_boost(struct drm_i915_private *dev_priv,
5062 struct intel_rps_client *rps,
5063 unsigned long submitted)
5064{
5065 /* This is intentionally racy! We peek at the state here, then
5066 * validate inside the RPS worker.
5067 */
5068 if (!(dev_priv->gt.awake &&
5069 dev_priv->rps.enabled &&
5070 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5071 return;
5072
5073 /* Force a RPS boost (and don't count it against the client) if
5074 * the GPU is severely congested.
5075 */
5076 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5077 rps = NULL;
5078
5079 spin_lock(&dev_priv->rps.client_lock);
5080 if (rps == NULL || list_empty(&rps->link)) {
5081 spin_lock_irq(&dev_priv->irq_lock);
5082 if (dev_priv->rps.interrupts_enabled) {
5083 dev_priv->rps.client_boost = true;
5084 schedule_work(&dev_priv->rps.work);
5085 }
5086 spin_unlock_irq(&dev_priv->irq_lock);
5087
5088 if (rps != NULL) {
5089 list_add(&rps->link, &dev_priv->rps.clients);
5090 rps->boosts++;
5091 } else
5092 dev_priv->rps.boosts++;
5093 }
5094 spin_unlock(&dev_priv->rps.client_lock);
5095}
5096
5097void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5098{
5099 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5100 valleyview_set_rps(dev_priv, val);
5101 else
5102 gen6_set_rps(dev_priv, val);
5103}
5104
5105static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5106{
5107 I915_WRITE(GEN6_RC_CONTROL, 0);
5108 I915_WRITE(GEN9_PG_ENABLE, 0);
5109}
5110
5111static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5112{
5113 I915_WRITE(GEN6_RP_CONTROL, 0);
5114}
5115
5116static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5117{
5118 I915_WRITE(GEN6_RC_CONTROL, 0);
5119 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5120 I915_WRITE(GEN6_RP_CONTROL, 0);
5121}
5122
5123static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5124{
5125 I915_WRITE(GEN6_RC_CONTROL, 0);
5126}
5127
5128static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5129{
5130 /* we're doing forcewake before Disabling RC6,
5131 * This what the BIOS expects when going into suspend */
5132 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5133
5134 I915_WRITE(GEN6_RC_CONTROL, 0);
5135
5136 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5137}
5138
5139static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5140{
5141 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5142 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5143 mode = GEN6_RC_CTL_RC6_ENABLE;
5144 else
5145 mode = 0;
5146 }
5147 if (HAS_RC6p(dev_priv))
5148 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5149 "RC6 %s RC6p %s RC6pp %s\n",
5150 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5151 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5152 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5153
5154 else
5155 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5156 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5157}
5158
5159static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5160{
5161 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5162 bool enable_rc6 = true;
5163 unsigned long rc6_ctx_base;
5164 u32 rc_ctl;
5165 int rc_sw_target;
5166
5167 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5168 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5169 RC_SW_TARGET_STATE_SHIFT;
5170 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5171 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5172 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5173 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5174 rc_sw_target);
5175
5176 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5177 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5178 enable_rc6 = false;
5179 }
5180
5181 /*
5182 * The exact context size is not known for BXT, so assume a page size
5183 * for this check.
5184 */
5185 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5186 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5187 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5188 ggtt->stolen_reserved_size))) {
5189 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5190 enable_rc6 = false;
5191 }
5192
5193 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5194 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5195 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5196 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5197 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5198 enable_rc6 = false;
5199 }
5200
5201 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5202 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5203 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5204 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5205 enable_rc6 = false;
5206 }
5207
5208 if (!I915_READ(GEN6_GFXPAUSE)) {
5209 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5210 enable_rc6 = false;
5211 }
5212
5213 if (!I915_READ(GEN8_MISC_CTRL0)) {
5214 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5215 enable_rc6 = false;
5216 }
5217
5218 return enable_rc6;
5219}
5220
5221int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5222{
5223 /* No RC6 before Ironlake and code is gone for ilk. */
5224 if (INTEL_INFO(dev_priv)->gen < 6)
5225 return 0;
5226
5227 if (!enable_rc6)
5228 return 0;
5229
5230 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5231 DRM_INFO("RC6 disabled by BIOS\n");
5232 return 0;
5233 }
5234
5235 /* Respect the kernel parameter if it is set */
5236 if (enable_rc6 >= 0) {
5237 int mask;
5238
5239 if (HAS_RC6p(dev_priv))
5240 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5241 INTEL_RC6pp_ENABLE;
5242 else
5243 mask = INTEL_RC6_ENABLE;
5244
5245 if ((enable_rc6 & mask) != enable_rc6)
5246 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5247 "(requested %d, valid %d)\n",
5248 enable_rc6 & mask, enable_rc6, mask);
5249
5250 return enable_rc6 & mask;
5251 }
5252
5253 if (IS_IVYBRIDGE(dev_priv))
5254 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5255
5256 return INTEL_RC6_ENABLE;
5257}
5258
5259static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5260{
5261 /* All of these values are in units of 50MHz */
5262
5263 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5264 if (IS_BROXTON(dev_priv)) {
5265 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5266 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5267 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5268 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5269 } else {
5270 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5271 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5272 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5273 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5274 }
5275 /* hw_max = RP0 until we check for overclocking */
5276 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5277
5278 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5279 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5280 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5281 u32 ddcc_status = 0;
5282
5283 if (sandybridge_pcode_read(dev_priv,
5284 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5285 &ddcc_status) == 0)
5286 dev_priv->rps.efficient_freq =
5287 clamp_t(u8,
5288 ((ddcc_status >> 8) & 0xff),
5289 dev_priv->rps.min_freq,
5290 dev_priv->rps.max_freq);
5291 }
5292
5293 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5294 /* Store the frequency values in 16.66 MHZ units, which is
5295 * the natural hardware unit for SKL
5296 */
5297 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5298 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5299 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5300 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5301 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5302 }
5303}
5304
5305static void reset_rps(struct drm_i915_private *dev_priv,
5306 void (*set)(struct drm_i915_private *, u8))
5307{
5308 u8 freq = dev_priv->rps.cur_freq;
5309
5310 /* force a reset */
5311 dev_priv->rps.power = -1;
5312 dev_priv->rps.cur_freq = -1;
5313
5314 set(dev_priv, freq);
5315}
5316
5317/* See the Gen9_GT_PM_Programming_Guide doc for the below */
5318static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5319{
5320 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5321
5322 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5323 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5324 /*
5325 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5326 * clear out the Control register just to avoid inconsitency
5327 * with debugfs interface, which will show Turbo as enabled
5328 * only and that is not expected by the User after adding the
5329 * WaGsvDisableTurbo. Apart from this there is no problem even
5330 * if the Turbo is left enabled in the Control register, as the
5331 * Up/Down interrupts would remain masked.
5332 */
5333 gen9_disable_rps(dev_priv);
5334 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5335 return;
5336 }
5337
5338 /* Program defaults and thresholds for RPS*/
5339 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5340 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5341
5342 /* 1 second timeout*/
5343 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5344 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5345
5346 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5347
5348 /* Leaning on the below call to gen6_set_rps to program/setup the
5349 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5350 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5351 reset_rps(dev_priv, gen6_set_rps);
5352
5353 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5354}
5355
5356static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5357{
5358 struct intel_engine_cs *engine;
5359 enum intel_engine_id id;
5360 uint32_t rc6_mask = 0;
5361
5362 /* 1a: Software RC state - RC0 */
5363 I915_WRITE(GEN6_RC_STATE, 0);
5364
5365 /* 1b: Get forcewake during program sequence. Although the driver
5366 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5367 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5368
5369 /* 2a: Disable RC states. */
5370 I915_WRITE(GEN6_RC_CONTROL, 0);
5371
5372 /* 2b: Program RC6 thresholds.*/
5373
5374 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5375 if (IS_SKYLAKE(dev_priv))
5376 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5377 else
5378 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5379 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5380 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5381 for_each_engine(engine, dev_priv, id)
5382 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5383
5384 if (HAS_GUC(dev_priv))
5385 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5386
5387 I915_WRITE(GEN6_RC_SLEEP, 0);
5388
5389 /* 2c: Program Coarse Power Gating Policies. */
5390 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5391 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5392
5393 /* 3a: Enable RC6 */
5394 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5395 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5396 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5397 /* WaRsUseTimeoutMode:bxt */
5398 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5399 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5400 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5401 GEN7_RC_CTL_TO_MODE |
5402 rc6_mask);
5403 } else {
5404 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5405 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5406 GEN6_RC_CTL_EI_MODE(1) |
5407 rc6_mask);
5408 }
5409
5410 /*
5411 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5412 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5413 */
5414 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5415 I915_WRITE(GEN9_PG_ENABLE, 0);
5416 else
5417 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5418 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5419
5420 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5421}
5422
5423static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5424{
5425 struct intel_engine_cs *engine;
5426 enum intel_engine_id id;
5427 uint32_t rc6_mask = 0;
5428
5429 /* 1a: Software RC state - RC0 */
5430 I915_WRITE(GEN6_RC_STATE, 0);
5431
5432 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5433 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5434 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5435
5436 /* 2a: Disable RC states. */
5437 I915_WRITE(GEN6_RC_CONTROL, 0);
5438
5439 /* 2b: Program RC6 thresholds.*/
5440 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5441 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5442 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5443 for_each_engine(engine, dev_priv, id)
5444 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5445 I915_WRITE(GEN6_RC_SLEEP, 0);
5446 if (IS_BROADWELL(dev_priv))
5447 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5448 else
5449 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5450
5451 /* 3: Enable RC6 */
5452 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5453 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5454 intel_print_rc6_info(dev_priv, rc6_mask);
5455 if (IS_BROADWELL(dev_priv))
5456 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5457 GEN7_RC_CTL_TO_MODE |
5458 rc6_mask);
5459 else
5460 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5461 GEN6_RC_CTL_EI_MODE(1) |
5462 rc6_mask);
5463
5464 /* 4 Program defaults and thresholds for RPS*/
5465 I915_WRITE(GEN6_RPNSWREQ,
5466 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5467 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5468 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5469 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5470 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5471
5472 /* Docs recommend 900MHz, and 300 MHz respectively */
5473 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5474 dev_priv->rps.max_freq_softlimit << 24 |
5475 dev_priv->rps.min_freq_softlimit << 16);
5476
5477 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5478 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5479 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5480 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5481
5482 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5483
5484 /* 5: Enable RPS */
5485 I915_WRITE(GEN6_RP_CONTROL,
5486 GEN6_RP_MEDIA_TURBO |
5487 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5488 GEN6_RP_MEDIA_IS_GFX |
5489 GEN6_RP_ENABLE |
5490 GEN6_RP_UP_BUSY_AVG |
5491 GEN6_RP_DOWN_IDLE_AVG);
5492
5493 /* 6: Ring frequency + overclocking (our driver does this later */
5494
5495 reset_rps(dev_priv, gen6_set_rps);
5496
5497 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5498}
5499
5500static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5501{
5502 struct intel_engine_cs *engine;
5503 enum intel_engine_id id;
5504 u32 rc6vids, rc6_mask = 0;
5505 u32 gtfifodbg;
5506 int rc6_mode;
5507 int ret;
5508
5509 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5510
5511 /* Here begins a magic sequence of register writes to enable
5512 * auto-downclocking.
5513 *
5514 * Perhaps there might be some value in exposing these to
5515 * userspace...
5516 */
5517 I915_WRITE(GEN6_RC_STATE, 0);
5518
5519 /* Clear the DBG now so we don't confuse earlier errors */
5520 gtfifodbg = I915_READ(GTFIFODBG);
5521 if (gtfifodbg) {
5522 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5523 I915_WRITE(GTFIFODBG, gtfifodbg);
5524 }
5525
5526 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5527
5528 /* disable the counters and set deterministic thresholds */
5529 I915_WRITE(GEN6_RC_CONTROL, 0);
5530
5531 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5532 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5533 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5534 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5535 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5536
5537 for_each_engine(engine, dev_priv, id)
5538 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5539
5540 I915_WRITE(GEN6_RC_SLEEP, 0);
5541 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5542 if (IS_IVYBRIDGE(dev_priv))
5543 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5544 else
5545 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5546 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5547 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5548
5549 /* Check if we are enabling RC6 */
5550 rc6_mode = intel_enable_rc6();
5551 if (rc6_mode & INTEL_RC6_ENABLE)
5552 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5553
5554 /* We don't use those on Haswell */
5555 if (!IS_HASWELL(dev_priv)) {
5556 if (rc6_mode & INTEL_RC6p_ENABLE)
5557 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5558
5559 if (rc6_mode & INTEL_RC6pp_ENABLE)
5560 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5561 }
5562
5563 intel_print_rc6_info(dev_priv, rc6_mask);
5564
5565 I915_WRITE(GEN6_RC_CONTROL,
5566 rc6_mask |
5567 GEN6_RC_CTL_EI_MODE(1) |
5568 GEN6_RC_CTL_HW_ENABLE);
5569
5570 /* Power down if completely idle for over 50ms */
5571 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5572 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5573
5574 reset_rps(dev_priv, gen6_set_rps);
5575
5576 rc6vids = 0;
5577 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5578 if (IS_GEN6(dev_priv) && ret) {
5579 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5580 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5581 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5582 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5583 rc6vids &= 0xffff00;
5584 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5585 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5586 if (ret)
5587 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5588 }
5589
5590 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5591}
5592
5593static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5594{
5595 int min_freq = 15;
5596 unsigned int gpu_freq;
5597 unsigned int max_ia_freq, min_ring_freq;
5598 unsigned int max_gpu_freq, min_gpu_freq;
5599 int scaling_factor = 180;
5600 struct cpufreq_policy *policy;
5601
5602 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5603
5604 policy = cpufreq_cpu_get(0);
5605 if (policy) {
5606 max_ia_freq = policy->cpuinfo.max_freq;
5607 cpufreq_cpu_put(policy);
5608 } else {
5609 /*
5610 * Default to measured freq if none found, PCU will ensure we
5611 * don't go over
5612 */
5613 max_ia_freq = tsc_khz;
5614 }
5615
5616 /* Convert from kHz to MHz */
5617 max_ia_freq /= 1000;
5618
5619 min_ring_freq = I915_READ(DCLK) & 0xf;
5620 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5621 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5622
5623 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5624 /* Convert GT frequency to 50 HZ units */
5625 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5626 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5627 } else {
5628 min_gpu_freq = dev_priv->rps.min_freq;
5629 max_gpu_freq = dev_priv->rps.max_freq;
5630 }
5631
5632 /*
5633 * For each potential GPU frequency, load a ring frequency we'd like
5634 * to use for memory access. We do this by specifying the IA frequency
5635 * the PCU should use as a reference to determine the ring frequency.
5636 */
5637 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5638 int diff = max_gpu_freq - gpu_freq;
5639 unsigned int ia_freq = 0, ring_freq = 0;
5640
5641 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5642 /*
5643 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5644 * No floor required for ring frequency on SKL.
5645 */
5646 ring_freq = gpu_freq;
5647 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5648 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5649 ring_freq = max(min_ring_freq, gpu_freq);
5650 } else if (IS_HASWELL(dev_priv)) {
5651 ring_freq = mult_frac(gpu_freq, 5, 4);
5652 ring_freq = max(min_ring_freq, ring_freq);
5653 /* leave ia_freq as the default, chosen by cpufreq */
5654 } else {
5655 /* On older processors, there is no separate ring
5656 * clock domain, so in order to boost the bandwidth
5657 * of the ring, we need to upclock the CPU (ia_freq).
5658 *
5659 * For GPU frequencies less than 750MHz,
5660 * just use the lowest ring freq.
5661 */
5662 if (gpu_freq < min_freq)
5663 ia_freq = 800;
5664 else
5665 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5666 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5667 }
5668
5669 sandybridge_pcode_write(dev_priv,
5670 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5671 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5672 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5673 gpu_freq);
5674 }
5675}
5676
5677static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5678{
5679 u32 val, rp0;
5680
5681 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5682
5683 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5684 case 8:
5685 /* (2 * 4) config */
5686 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5687 break;
5688 case 12:
5689 /* (2 * 6) config */
5690 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5691 break;
5692 case 16:
5693 /* (2 * 8) config */
5694 default:
5695 /* Setting (2 * 8) Min RP0 for any other combination */
5696 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5697 break;
5698 }
5699
5700 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5701
5702 return rp0;
5703}
5704
5705static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5706{
5707 u32 val, rpe;
5708
5709 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5710 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5711
5712 return rpe;
5713}
5714
5715static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5716{
5717 u32 val, rp1;
5718
5719 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5720 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5721
5722 return rp1;
5723}
5724
5725static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5726{
5727 u32 val, rp1;
5728
5729 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5730
5731 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5732
5733 return rp1;
5734}
5735
5736static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5737{
5738 u32 val, rp0;
5739
5740 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5741
5742 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5743 /* Clamp to max */
5744 rp0 = min_t(u32, rp0, 0xea);
5745
5746 return rp0;
5747}
5748
5749static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5750{
5751 u32 val, rpe;
5752
5753 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5754 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5755 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5756 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5757
5758 return rpe;
5759}
5760
5761static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5762{
5763 u32 val;
5764
5765 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5766 /*
5767 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5768 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5769 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5770 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5771 * to make sure it matches what Punit accepts.
5772 */
5773 return max_t(u32, val, 0xc0);
5774}
5775
5776/* Check that the pctx buffer wasn't move under us. */
5777static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5778{
5779 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5780
5781 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5782 dev_priv->vlv_pctx->stolen->start);
5783}
5784
5785
5786/* Check that the pcbr address is not empty. */
5787static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5788{
5789 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5790
5791 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5792}
5793
5794static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5795{
5796 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5797 unsigned long pctx_paddr, paddr;
5798 u32 pcbr;
5799 int pctx_size = 32*1024;
5800
5801 pcbr = I915_READ(VLV_PCBR);
5802 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5803 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5804 paddr = (dev_priv->mm.stolen_base +
5805 (ggtt->stolen_size - pctx_size));
5806
5807 pctx_paddr = (paddr & (~4095));
5808 I915_WRITE(VLV_PCBR, pctx_paddr);
5809 }
5810
5811 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5812}
5813
5814static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5815{
5816 struct drm_i915_gem_object *pctx;
5817 unsigned long pctx_paddr;
5818 u32 pcbr;
5819 int pctx_size = 24*1024;
5820
5821 pcbr = I915_READ(VLV_PCBR);
5822 if (pcbr) {
5823 /* BIOS set it up already, grab the pre-alloc'd space */
5824 int pcbr_offset;
5825
5826 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5827 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
5828 pcbr_offset,
5829 I915_GTT_OFFSET_NONE,
5830 pctx_size);
5831 goto out;
5832 }
5833
5834 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5835
5836 /*
5837 * From the Gunit register HAS:
5838 * The Gfx driver is expected to program this register and ensure
5839 * proper allocation within Gfx stolen memory. For example, this
5840 * register should be programmed such than the PCBR range does not
5841 * overlap with other ranges, such as the frame buffer, protected
5842 * memory, or any other relevant ranges.
5843 */
5844 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
5845 if (!pctx) {
5846 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5847 goto out;
5848 }
5849
5850 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5851 I915_WRITE(VLV_PCBR, pctx_paddr);
5852
5853out:
5854 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5855 dev_priv->vlv_pctx = pctx;
5856}
5857
5858static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5859{
5860 if (WARN_ON(!dev_priv->vlv_pctx))
5861 return;
5862
5863 i915_gem_object_put(dev_priv->vlv_pctx);
5864 dev_priv->vlv_pctx = NULL;
5865}
5866
5867static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5868{
5869 dev_priv->rps.gpll_ref_freq =
5870 vlv_get_cck_clock(dev_priv, "GPLL ref",
5871 CCK_GPLL_CLOCK_CONTROL,
5872 dev_priv->czclk_freq);
5873
5874 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5875 dev_priv->rps.gpll_ref_freq);
5876}
5877
5878static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5879{
5880 u32 val;
5881
5882 valleyview_setup_pctx(dev_priv);
5883
5884 vlv_init_gpll_ref_freq(dev_priv);
5885
5886 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5887 switch ((val >> 6) & 3) {
5888 case 0:
5889 case 1:
5890 dev_priv->mem_freq = 800;
5891 break;
5892 case 2:
5893 dev_priv->mem_freq = 1066;
5894 break;
5895 case 3:
5896 dev_priv->mem_freq = 1333;
5897 break;
5898 }
5899 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5900
5901 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5902 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5903 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5904 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5905 dev_priv->rps.max_freq);
5906
5907 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5908 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5909 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5910 dev_priv->rps.efficient_freq);
5911
5912 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5913 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5914 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5915 dev_priv->rps.rp1_freq);
5916
5917 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5918 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5919 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5920 dev_priv->rps.min_freq);
5921}
5922
5923static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5924{
5925 u32 val;
5926
5927 cherryview_setup_pctx(dev_priv);
5928
5929 vlv_init_gpll_ref_freq(dev_priv);
5930
5931 mutex_lock(&dev_priv->sb_lock);
5932 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5933 mutex_unlock(&dev_priv->sb_lock);
5934
5935 switch ((val >> 2) & 0x7) {
5936 case 3:
5937 dev_priv->mem_freq = 2000;
5938 break;
5939 default:
5940 dev_priv->mem_freq = 1600;
5941 break;
5942 }
5943 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5944
5945 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5946 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5947 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5948 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5949 dev_priv->rps.max_freq);
5950
5951 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5952 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5953 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5954 dev_priv->rps.efficient_freq);
5955
5956 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5957 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5958 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5959 dev_priv->rps.rp1_freq);
5960
5961 /* PUnit validated range is only [RPe, RP0] */
5962 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5963 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5964 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5965 dev_priv->rps.min_freq);
5966
5967 WARN_ONCE((dev_priv->rps.max_freq |
5968 dev_priv->rps.efficient_freq |
5969 dev_priv->rps.rp1_freq |
5970 dev_priv->rps.min_freq) & 1,
5971 "Odd GPU freq values\n");
5972}
5973
5974static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5975{
5976 valleyview_cleanup_pctx(dev_priv);
5977}
5978
5979static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5980{
5981 struct intel_engine_cs *engine;
5982 enum intel_engine_id id;
5983 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5984
5985 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5986
5987 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5988 GT_FIFO_FREE_ENTRIES_CHV);
5989 if (gtfifodbg) {
5990 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5991 gtfifodbg);
5992 I915_WRITE(GTFIFODBG, gtfifodbg);
5993 }
5994
5995 cherryview_check_pctx(dev_priv);
5996
5997 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5998 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5999 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6000
6001 /* Disable RC states. */
6002 I915_WRITE(GEN6_RC_CONTROL, 0);
6003
6004 /* 2a: Program RC6 thresholds.*/
6005 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6006 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6007 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6008
6009 for_each_engine(engine, dev_priv, id)
6010 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6011 I915_WRITE(GEN6_RC_SLEEP, 0);
6012
6013 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6014 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
6015
6016 /* allows RC6 residency counter to work */
6017 I915_WRITE(VLV_COUNTER_CONTROL,
6018 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6019 VLV_MEDIA_RC6_COUNT_EN |
6020 VLV_RENDER_RC6_COUNT_EN));
6021
6022 /* For now we assume BIOS is allocating and populating the PCBR */
6023 pcbr = I915_READ(VLV_PCBR);
6024
6025 /* 3: Enable RC6 */
6026 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6027 (pcbr >> VLV_PCBR_ADDR_SHIFT))
6028 rc6_mode = GEN7_RC_CTL_TO_MODE;
6029
6030 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6031
6032 /* 4 Program defaults and thresholds for RPS*/
6033 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6034 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6035 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6036 I915_WRITE(GEN6_RP_UP_EI, 66000);
6037 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6038
6039 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6040
6041 /* 5: Enable RPS */
6042 I915_WRITE(GEN6_RP_CONTROL,
6043 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6044 GEN6_RP_MEDIA_IS_GFX |
6045 GEN6_RP_ENABLE |
6046 GEN6_RP_UP_BUSY_AVG |
6047 GEN6_RP_DOWN_IDLE_AVG);
6048
6049 /* Setting Fixed Bias */
6050 val = VLV_OVERRIDE_EN |
6051 VLV_SOC_TDP_EN |
6052 CHV_BIAS_CPU_50_SOC_50;
6053 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6054
6055 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6056
6057 /* RPS code assumes GPLL is used */
6058 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6059
6060 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6061 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6062
6063 reset_rps(dev_priv, valleyview_set_rps);
6064
6065 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6066}
6067
6068static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6069{
6070 struct intel_engine_cs *engine;
6071 enum intel_engine_id id;
6072 u32 gtfifodbg, val, rc6_mode = 0;
6073
6074 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6075
6076 valleyview_check_pctx(dev_priv);
6077
6078 gtfifodbg = I915_READ(GTFIFODBG);
6079 if (gtfifodbg) {
6080 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6081 gtfifodbg);
6082 I915_WRITE(GTFIFODBG, gtfifodbg);
6083 }
6084
6085 /* If VLV, Forcewake all wells, else re-direct to regular path */
6086 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6087
6088 /* Disable RC states. */
6089 I915_WRITE(GEN6_RC_CONTROL, 0);
6090
6091 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6092 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6093 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6094 I915_WRITE(GEN6_RP_UP_EI, 66000);
6095 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6096
6097 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6098
6099 I915_WRITE(GEN6_RP_CONTROL,
6100 GEN6_RP_MEDIA_TURBO |
6101 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6102 GEN6_RP_MEDIA_IS_GFX |
6103 GEN6_RP_ENABLE |
6104 GEN6_RP_UP_BUSY_AVG |
6105 GEN6_RP_DOWN_IDLE_CONT);
6106
6107 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6108 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6109 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6110
6111 for_each_engine(engine, dev_priv, id)
6112 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6113
6114 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6115
6116 /* allows RC6 residency counter to work */
6117 I915_WRITE(VLV_COUNTER_CONTROL,
6118 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6119 VLV_RENDER_RC0_COUNT_EN |
6120 VLV_MEDIA_RC6_COUNT_EN |
6121 VLV_RENDER_RC6_COUNT_EN));
6122
6123 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6124 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6125
6126 intel_print_rc6_info(dev_priv, rc6_mode);
6127
6128 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6129
6130 /* Setting Fixed Bias */
6131 val = VLV_OVERRIDE_EN |
6132 VLV_SOC_TDP_EN |
6133 VLV_BIAS_CPU_125_SOC_875;
6134 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6135
6136 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6137
6138 /* RPS code assumes GPLL is used */
6139 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6140
6141 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6142 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6143
6144 reset_rps(dev_priv, valleyview_set_rps);
6145
6146 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6147}
6148
6149static unsigned long intel_pxfreq(u32 vidfreq)
6150{
6151 unsigned long freq;
6152 int div = (vidfreq & 0x3f0000) >> 16;
6153 int post = (vidfreq & 0x3000) >> 12;
6154 int pre = (vidfreq & 0x7);
6155
6156 if (!pre)
6157 return 0;
6158
6159 freq = ((div * 133333) / ((1<<post) * pre));
6160
6161 return freq;
6162}
6163
6164static const struct cparams {
6165 u16 i;
6166 u16 t;
6167 u16 m;
6168 u16 c;
6169} cparams[] = {
6170 { 1, 1333, 301, 28664 },
6171 { 1, 1066, 294, 24460 },
6172 { 1, 800, 294, 25192 },
6173 { 0, 1333, 276, 27605 },
6174 { 0, 1066, 276, 27605 },
6175 { 0, 800, 231, 23784 },
6176};
6177
6178static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6179{
6180 u64 total_count, diff, ret;
6181 u32 count1, count2, count3, m = 0, c = 0;
6182 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6183 int i;
6184
6185 assert_spin_locked(&mchdev_lock);
6186
6187 diff1 = now - dev_priv->ips.last_time1;
6188
6189 /* Prevent division-by-zero if we are asking too fast.
6190 * Also, we don't get interesting results if we are polling
6191 * faster than once in 10ms, so just return the saved value
6192 * in such cases.
6193 */
6194 if (diff1 <= 10)
6195 return dev_priv->ips.chipset_power;
6196
6197 count1 = I915_READ(DMIEC);
6198 count2 = I915_READ(DDREC);
6199 count3 = I915_READ(CSIEC);
6200
6201 total_count = count1 + count2 + count3;
6202
6203 /* FIXME: handle per-counter overflow */
6204 if (total_count < dev_priv->ips.last_count1) {
6205 diff = ~0UL - dev_priv->ips.last_count1;
6206 diff += total_count;
6207 } else {
6208 diff = total_count - dev_priv->ips.last_count1;
6209 }
6210
6211 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6212 if (cparams[i].i == dev_priv->ips.c_m &&
6213 cparams[i].t == dev_priv->ips.r_t) {
6214 m = cparams[i].m;
6215 c = cparams[i].c;
6216 break;
6217 }
6218 }
6219
6220 diff = div_u64(diff, diff1);
6221 ret = ((m * diff) + c);
6222 ret = div_u64(ret, 10);
6223
6224 dev_priv->ips.last_count1 = total_count;
6225 dev_priv->ips.last_time1 = now;
6226
6227 dev_priv->ips.chipset_power = ret;
6228
6229 return ret;
6230}
6231
6232unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6233{
6234 unsigned long val;
6235
6236 if (INTEL_INFO(dev_priv)->gen != 5)
6237 return 0;
6238
6239 spin_lock_irq(&mchdev_lock);
6240
6241 val = __i915_chipset_val(dev_priv);
6242
6243 spin_unlock_irq(&mchdev_lock);
6244
6245 return val;
6246}
6247
6248unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6249{
6250 unsigned long m, x, b;
6251 u32 tsfs;
6252
6253 tsfs = I915_READ(TSFS);
6254
6255 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6256 x = I915_READ8(TR1);
6257
6258 b = tsfs & TSFS_INTR_MASK;
6259
6260 return ((m * x) / 127) - b;
6261}
6262
6263static int _pxvid_to_vd(u8 pxvid)
6264{
6265 if (pxvid == 0)
6266 return 0;
6267
6268 if (pxvid >= 8 && pxvid < 31)
6269 pxvid = 31;
6270
6271 return (pxvid + 2) * 125;
6272}
6273
6274static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6275{
6276 const int vd = _pxvid_to_vd(pxvid);
6277 const int vm = vd - 1125;
6278
6279 if (INTEL_INFO(dev_priv)->is_mobile)
6280 return vm > 0 ? vm : 0;
6281
6282 return vd;
6283}
6284
6285static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6286{
6287 u64 now, diff, diffms;
6288 u32 count;
6289
6290 assert_spin_locked(&mchdev_lock);
6291
6292 now = ktime_get_raw_ns();
6293 diffms = now - dev_priv->ips.last_time2;
6294 do_div(diffms, NSEC_PER_MSEC);
6295
6296 /* Don't divide by 0 */
6297 if (!diffms)
6298 return;
6299
6300 count = I915_READ(GFXEC);
6301
6302 if (count < dev_priv->ips.last_count2) {
6303 diff = ~0UL - dev_priv->ips.last_count2;
6304 diff += count;
6305 } else {
6306 diff = count - dev_priv->ips.last_count2;
6307 }
6308
6309 dev_priv->ips.last_count2 = count;
6310 dev_priv->ips.last_time2 = now;
6311
6312 /* More magic constants... */
6313 diff = diff * 1181;
6314 diff = div_u64(diff, diffms * 10);
6315 dev_priv->ips.gfx_power = diff;
6316}
6317
6318void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6319{
6320 if (INTEL_INFO(dev_priv)->gen != 5)
6321 return;
6322
6323 spin_lock_irq(&mchdev_lock);
6324
6325 __i915_update_gfx_val(dev_priv);
6326
6327 spin_unlock_irq(&mchdev_lock);
6328}
6329
6330static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6331{
6332 unsigned long t, corr, state1, corr2, state2;
6333 u32 pxvid, ext_v;
6334
6335 assert_spin_locked(&mchdev_lock);
6336
6337 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6338 pxvid = (pxvid >> 24) & 0x7f;
6339 ext_v = pvid_to_extvid(dev_priv, pxvid);
6340
6341 state1 = ext_v;
6342
6343 t = i915_mch_val(dev_priv);
6344
6345 /* Revel in the empirically derived constants */
6346
6347 /* Correction factor in 1/100000 units */
6348 if (t > 80)
6349 corr = ((t * 2349) + 135940);
6350 else if (t >= 50)
6351 corr = ((t * 964) + 29317);
6352 else /* < 50 */
6353 corr = ((t * 301) + 1004);
6354
6355 corr = corr * ((150142 * state1) / 10000 - 78642);
6356 corr /= 100000;
6357 corr2 = (corr * dev_priv->ips.corr);
6358
6359 state2 = (corr2 * state1) / 10000;
6360 state2 /= 100; /* convert to mW */
6361
6362 __i915_update_gfx_val(dev_priv);
6363
6364 return dev_priv->ips.gfx_power + state2;
6365}
6366
6367unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6368{
6369 unsigned long val;
6370
6371 if (INTEL_INFO(dev_priv)->gen != 5)
6372 return 0;
6373
6374 spin_lock_irq(&mchdev_lock);
6375
6376 val = __i915_gfx_val(dev_priv);
6377
6378 spin_unlock_irq(&mchdev_lock);
6379
6380 return val;
6381}
6382
6383/**
6384 * i915_read_mch_val - return value for IPS use
6385 *
6386 * Calculate and return a value for the IPS driver to use when deciding whether
6387 * we have thermal and power headroom to increase CPU or GPU power budget.
6388 */
6389unsigned long i915_read_mch_val(void)
6390{
6391 struct drm_i915_private *dev_priv;
6392 unsigned long chipset_val, graphics_val, ret = 0;
6393
6394 spin_lock_irq(&mchdev_lock);
6395 if (!i915_mch_dev)
6396 goto out_unlock;
6397 dev_priv = i915_mch_dev;
6398
6399 chipset_val = __i915_chipset_val(dev_priv);
6400 graphics_val = __i915_gfx_val(dev_priv);
6401
6402 ret = chipset_val + graphics_val;
6403
6404out_unlock:
6405 spin_unlock_irq(&mchdev_lock);
6406
6407 return ret;
6408}
6409EXPORT_SYMBOL_GPL(i915_read_mch_val);
6410
6411/**
6412 * i915_gpu_raise - raise GPU frequency limit
6413 *
6414 * Raise the limit; IPS indicates we have thermal headroom.
6415 */
6416bool i915_gpu_raise(void)
6417{
6418 struct drm_i915_private *dev_priv;
6419 bool ret = true;
6420
6421 spin_lock_irq(&mchdev_lock);
6422 if (!i915_mch_dev) {
6423 ret = false;
6424 goto out_unlock;
6425 }
6426 dev_priv = i915_mch_dev;
6427
6428 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6429 dev_priv->ips.max_delay--;
6430
6431out_unlock:
6432 spin_unlock_irq(&mchdev_lock);
6433
6434 return ret;
6435}
6436EXPORT_SYMBOL_GPL(i915_gpu_raise);
6437
6438/**
6439 * i915_gpu_lower - lower GPU frequency limit
6440 *
6441 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6442 * frequency maximum.
6443 */
6444bool i915_gpu_lower(void)
6445{
6446 struct drm_i915_private *dev_priv;
6447 bool ret = true;
6448
6449 spin_lock_irq(&mchdev_lock);
6450 if (!i915_mch_dev) {
6451 ret = false;
6452 goto out_unlock;
6453 }
6454 dev_priv = i915_mch_dev;
6455
6456 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6457 dev_priv->ips.max_delay++;
6458
6459out_unlock:
6460 spin_unlock_irq(&mchdev_lock);
6461
6462 return ret;
6463}
6464EXPORT_SYMBOL_GPL(i915_gpu_lower);
6465
6466/**
6467 * i915_gpu_busy - indicate GPU business to IPS
6468 *
6469 * Tell the IPS driver whether or not the GPU is busy.
6470 */
6471bool i915_gpu_busy(void)
6472{
6473 bool ret = false;
6474
6475 spin_lock_irq(&mchdev_lock);
6476 if (i915_mch_dev)
6477 ret = i915_mch_dev->gt.awake;
6478 spin_unlock_irq(&mchdev_lock);
6479
6480 return ret;
6481}
6482EXPORT_SYMBOL_GPL(i915_gpu_busy);
6483
6484/**
6485 * i915_gpu_turbo_disable - disable graphics turbo
6486 *
6487 * Disable graphics turbo by resetting the max frequency and setting the
6488 * current frequency to the default.
6489 */
6490bool i915_gpu_turbo_disable(void)
6491{
6492 struct drm_i915_private *dev_priv;
6493 bool ret = true;
6494
6495 spin_lock_irq(&mchdev_lock);
6496 if (!i915_mch_dev) {
6497 ret = false;
6498 goto out_unlock;
6499 }
6500 dev_priv = i915_mch_dev;
6501
6502 dev_priv->ips.max_delay = dev_priv->ips.fstart;
6503
6504 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6505 ret = false;
6506
6507out_unlock:
6508 spin_unlock_irq(&mchdev_lock);
6509
6510 return ret;
6511}
6512EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6513
6514/**
6515 * Tells the intel_ips driver that the i915 driver is now loaded, if
6516 * IPS got loaded first.
6517 *
6518 * This awkward dance is so that neither module has to depend on the
6519 * other in order for IPS to do the appropriate communication of
6520 * GPU turbo limits to i915.
6521 */
6522static void
6523ips_ping_for_i915_load(void)
6524{
6525 void (*link)(void);
6526
6527 link = symbol_get(ips_link_to_i915_driver);
6528 if (link) {
6529 link();
6530 symbol_put(ips_link_to_i915_driver);
6531 }
6532}
6533
6534void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6535{
6536 /* We only register the i915 ips part with intel-ips once everything is
6537 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6538 spin_lock_irq(&mchdev_lock);
6539 i915_mch_dev = dev_priv;
6540 spin_unlock_irq(&mchdev_lock);
6541
6542 ips_ping_for_i915_load();
6543}
6544
6545void intel_gpu_ips_teardown(void)
6546{
6547 spin_lock_irq(&mchdev_lock);
6548 i915_mch_dev = NULL;
6549 spin_unlock_irq(&mchdev_lock);
6550}
6551
6552static void intel_init_emon(struct drm_i915_private *dev_priv)
6553{
6554 u32 lcfuse;
6555 u8 pxw[16];
6556 int i;
6557
6558 /* Disable to program */
6559 I915_WRITE(ECR, 0);
6560 POSTING_READ(ECR);
6561
6562 /* Program energy weights for various events */
6563 I915_WRITE(SDEW, 0x15040d00);
6564 I915_WRITE(CSIEW0, 0x007f0000);
6565 I915_WRITE(CSIEW1, 0x1e220004);
6566 I915_WRITE(CSIEW2, 0x04000004);
6567
6568 for (i = 0; i < 5; i++)
6569 I915_WRITE(PEW(i), 0);
6570 for (i = 0; i < 3; i++)
6571 I915_WRITE(DEW(i), 0);
6572
6573 /* Program P-state weights to account for frequency power adjustment */
6574 for (i = 0; i < 16; i++) {
6575 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6576 unsigned long freq = intel_pxfreq(pxvidfreq);
6577 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6578 PXVFREQ_PX_SHIFT;
6579 unsigned long val;
6580
6581 val = vid * vid;
6582 val *= (freq / 1000);
6583 val *= 255;
6584 val /= (127*127*900);
6585 if (val > 0xff)
6586 DRM_ERROR("bad pxval: %ld\n", val);
6587 pxw[i] = val;
6588 }
6589 /* Render standby states get 0 weight */
6590 pxw[14] = 0;
6591 pxw[15] = 0;
6592
6593 for (i = 0; i < 4; i++) {
6594 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6595 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6596 I915_WRITE(PXW(i), val);
6597 }
6598
6599 /* Adjust magic regs to magic values (more experimental results) */
6600 I915_WRITE(OGW0, 0);
6601 I915_WRITE(OGW1, 0);
6602 I915_WRITE(EG0, 0x00007f00);
6603 I915_WRITE(EG1, 0x0000000e);
6604 I915_WRITE(EG2, 0x000e0000);
6605 I915_WRITE(EG3, 0x68000300);
6606 I915_WRITE(EG4, 0x42000000);
6607 I915_WRITE(EG5, 0x00140031);
6608 I915_WRITE(EG6, 0);
6609 I915_WRITE(EG7, 0);
6610
6611 for (i = 0; i < 8; i++)
6612 I915_WRITE(PXWL(i), 0);
6613
6614 /* Enable PMON + select events */
6615 I915_WRITE(ECR, 0x80000019);
6616
6617 lcfuse = I915_READ(LCFUSE02);
6618
6619 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6620}
6621
6622void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6623{
6624 /*
6625 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6626 * requirement.
6627 */
6628 if (!i915.enable_rc6) {
6629 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6630 intel_runtime_pm_get(dev_priv);
6631 }
6632
6633 mutex_lock(&dev_priv->drm.struct_mutex);
6634 mutex_lock(&dev_priv->rps.hw_lock);
6635
6636 /* Initialize RPS limits (for userspace) */
6637 if (IS_CHERRYVIEW(dev_priv))
6638 cherryview_init_gt_powersave(dev_priv);
6639 else if (IS_VALLEYVIEW(dev_priv))
6640 valleyview_init_gt_powersave(dev_priv);
6641 else if (INTEL_GEN(dev_priv) >= 6)
6642 gen6_init_rps_frequencies(dev_priv);
6643
6644 /* Derive initial user preferences/limits from the hardware limits */
6645 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6646 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6647
6648 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6649 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6650
6651 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6652 dev_priv->rps.min_freq_softlimit =
6653 max_t(int,
6654 dev_priv->rps.efficient_freq,
6655 intel_freq_opcode(dev_priv, 450));
6656
6657 /* After setting max-softlimit, find the overclock max freq */
6658 if (IS_GEN6(dev_priv) ||
6659 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6660 u32 params = 0;
6661
6662 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, ¶ms);
6663 if (params & BIT(31)) { /* OC supported */
6664 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6665 (dev_priv->rps.max_freq & 0xff) * 50,
6666 (params & 0xff) * 50);
6667 dev_priv->rps.max_freq = params & 0xff;
6668 }
6669 }
6670
6671 /* Finally allow us to boost to max by default */
6672 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6673
6674 mutex_unlock(&dev_priv->rps.hw_lock);
6675 mutex_unlock(&dev_priv->drm.struct_mutex);
6676
6677 intel_autoenable_gt_powersave(dev_priv);
6678}
6679
6680void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6681{
6682 if (IS_VALLEYVIEW(dev_priv))
6683 valleyview_cleanup_gt_powersave(dev_priv);
6684
6685 if (!i915.enable_rc6)
6686 intel_runtime_pm_put(dev_priv);
6687}
6688
6689/**
6690 * intel_suspend_gt_powersave - suspend PM work and helper threads
6691 * @dev_priv: i915 device
6692 *
6693 * We don't want to disable RC6 or other features here, we just want
6694 * to make sure any work we've queued has finished and won't bother
6695 * us while we're suspended.
6696 */
6697void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6698{
6699 if (INTEL_GEN(dev_priv) < 6)
6700 return;
6701
6702 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6703 intel_runtime_pm_put(dev_priv);
6704
6705 /* gen6_rps_idle() will be called later to disable interrupts */
6706}
6707
6708void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6709{
6710 dev_priv->rps.enabled = true; /* force disabling */
6711 intel_disable_gt_powersave(dev_priv);
6712
6713 gen6_reset_rps_interrupts(dev_priv);
6714}
6715
6716void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6717{
6718 if (!READ_ONCE(dev_priv->rps.enabled))
6719 return;
6720
6721 mutex_lock(&dev_priv->rps.hw_lock);
6722
6723 if (INTEL_GEN(dev_priv) >= 9) {
6724 gen9_disable_rc6(dev_priv);
6725 gen9_disable_rps(dev_priv);
6726 } else if (IS_CHERRYVIEW(dev_priv)) {
6727 cherryview_disable_rps(dev_priv);
6728 } else if (IS_VALLEYVIEW(dev_priv)) {
6729 valleyview_disable_rps(dev_priv);
6730 } else if (INTEL_GEN(dev_priv) >= 6) {
6731 gen6_disable_rps(dev_priv);
6732 } else if (IS_IRONLAKE_M(dev_priv)) {
6733 ironlake_disable_drps(dev_priv);
6734 }
6735
6736 dev_priv->rps.enabled = false;
6737 mutex_unlock(&dev_priv->rps.hw_lock);
6738}
6739
6740void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6741{
6742 /* We shouldn't be disabling as we submit, so this should be less
6743 * racy than it appears!
6744 */
6745 if (READ_ONCE(dev_priv->rps.enabled))
6746 return;
6747
6748 /* Powersaving is controlled by the host when inside a VM */
6749 if (intel_vgpu_active(dev_priv))
6750 return;
6751
6752 mutex_lock(&dev_priv->rps.hw_lock);
6753
6754 if (IS_CHERRYVIEW(dev_priv)) {
6755 cherryview_enable_rps(dev_priv);
6756 } else if (IS_VALLEYVIEW(dev_priv)) {
6757 valleyview_enable_rps(dev_priv);
6758 } else if (INTEL_GEN(dev_priv) >= 9) {
6759 gen9_enable_rc6(dev_priv);
6760 gen9_enable_rps(dev_priv);
6761 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6762 gen6_update_ring_freq(dev_priv);
6763 } else if (IS_BROADWELL(dev_priv)) {
6764 gen8_enable_rps(dev_priv);
6765 gen6_update_ring_freq(dev_priv);
6766 } else if (INTEL_GEN(dev_priv) >= 6) {
6767 gen6_enable_rps(dev_priv);
6768 gen6_update_ring_freq(dev_priv);
6769 } else if (IS_IRONLAKE_M(dev_priv)) {
6770 ironlake_enable_drps(dev_priv);
6771 intel_init_emon(dev_priv);
6772 }
6773
6774 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6775 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6776
6777 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6778 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6779
6780 dev_priv->rps.enabled = true;
6781 mutex_unlock(&dev_priv->rps.hw_lock);
6782}
6783
6784static void __intel_autoenable_gt_powersave(struct work_struct *work)
6785{
6786 struct drm_i915_private *dev_priv =
6787 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6788 struct intel_engine_cs *rcs;
6789 struct drm_i915_gem_request *req;
6790
6791 if (READ_ONCE(dev_priv->rps.enabled))
6792 goto out;
6793
6794 rcs = dev_priv->engine[RCS];
6795 if (rcs->last_context)
6796 goto out;
6797
6798 if (!rcs->init_context)
6799 goto out;
6800
6801 mutex_lock(&dev_priv->drm.struct_mutex);
6802
6803 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6804 if (IS_ERR(req))
6805 goto unlock;
6806
6807 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6808 rcs->init_context(req);
6809
6810 /* Mark the device busy, calling intel_enable_gt_powersave() */
6811 i915_add_request_no_flush(req);
6812
6813unlock:
6814 mutex_unlock(&dev_priv->drm.struct_mutex);
6815out:
6816 intel_runtime_pm_put(dev_priv);
6817}
6818
6819void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6820{
6821 if (READ_ONCE(dev_priv->rps.enabled))
6822 return;
6823
6824 if (IS_IRONLAKE_M(dev_priv)) {
6825 ironlake_enable_drps(dev_priv);
6826 intel_init_emon(dev_priv);
6827 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6828 /*
6829 * PCU communication is slow and this doesn't need to be
6830 * done at any specific time, so do this out of our fast path
6831 * to make resume and init faster.
6832 *
6833 * We depend on the HW RC6 power context save/restore
6834 * mechanism when entering D3 through runtime PM suspend. So
6835 * disable RPM until RPS/RC6 is properly setup. We can only
6836 * get here via the driver load/system resume/runtime resume
6837 * paths, so the _noresume version is enough (and in case of
6838 * runtime resume it's necessary).
6839 */
6840 if (queue_delayed_work(dev_priv->wq,
6841 &dev_priv->rps.autoenable_work,
6842 round_jiffies_up_relative(HZ)))
6843 intel_runtime_pm_get_noresume(dev_priv);
6844 }
6845}
6846
6847static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
6848{
6849 /*
6850 * On Ibex Peak and Cougar Point, we need to disable clock
6851 * gating for the panel power sequencer or it will fail to
6852 * start up when no ports are active.
6853 */
6854 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6855}
6856
6857static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
6858{
6859 enum pipe pipe;
6860
6861 for_each_pipe(dev_priv, pipe) {
6862 I915_WRITE(DSPCNTR(pipe),
6863 I915_READ(DSPCNTR(pipe)) |
6864 DISPPLANE_TRICKLE_FEED_DISABLE);
6865
6866 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6867 POSTING_READ(DSPSURF(pipe));
6868 }
6869}
6870
6871static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
6872{
6873 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6874 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6875 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6876
6877 /*
6878 * Don't touch WM1S_LP_EN here.
6879 * Doing so could cause underruns.
6880 */
6881}
6882
6883static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
6884{
6885 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6886
6887 /*
6888 * Required for FBC
6889 * WaFbcDisableDpfcClockGating:ilk
6890 */
6891 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6892 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6893 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6894
6895 I915_WRITE(PCH_3DCGDIS0,
6896 MARIUNIT_CLOCK_GATE_DISABLE |
6897 SVSMUNIT_CLOCK_GATE_DISABLE);
6898 I915_WRITE(PCH_3DCGDIS1,
6899 VFMUNIT_CLOCK_GATE_DISABLE);
6900
6901 /*
6902 * According to the spec the following bits should be set in
6903 * order to enable memory self-refresh
6904 * The bit 22/21 of 0x42004
6905 * The bit 5 of 0x42020
6906 * The bit 15 of 0x45000
6907 */
6908 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6909 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6910 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6911 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6912 I915_WRITE(DISP_ARB_CTL,
6913 (I915_READ(DISP_ARB_CTL) |
6914 DISP_FBC_WM_DIS));
6915
6916 ilk_init_lp_watermarks(dev_priv);
6917
6918 /*
6919 * Based on the document from hardware guys the following bits
6920 * should be set unconditionally in order to enable FBC.
6921 * The bit 22 of 0x42000
6922 * The bit 22 of 0x42004
6923 * The bit 7,8,9 of 0x42020.
6924 */
6925 if (IS_IRONLAKE_M(dev_priv)) {
6926 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6927 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6928 I915_READ(ILK_DISPLAY_CHICKEN1) |
6929 ILK_FBCQ_DIS);
6930 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6931 I915_READ(ILK_DISPLAY_CHICKEN2) |
6932 ILK_DPARB_GATE);
6933 }
6934
6935 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6936
6937 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6938 I915_READ(ILK_DISPLAY_CHICKEN2) |
6939 ILK_ELPIN_409_SELECT);
6940 I915_WRITE(_3D_CHICKEN2,
6941 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6942 _3D_CHICKEN2_WM_READ_PIPELINED);
6943
6944 /* WaDisableRenderCachePipelinedFlush:ilk */
6945 I915_WRITE(CACHE_MODE_0,
6946 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6947
6948 /* WaDisable_RenderCache_OperationalFlush:ilk */
6949 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6950
6951 g4x_disable_trickle_feed(dev_priv);
6952
6953 ibx_init_clock_gating(dev_priv);
6954}
6955
6956static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
6957{
6958 int pipe;
6959 uint32_t val;
6960
6961 /*
6962 * On Ibex Peak and Cougar Point, we need to disable clock
6963 * gating for the panel power sequencer or it will fail to
6964 * start up when no ports are active.
6965 */
6966 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6967 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6968 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6969 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6970 DPLS_EDP_PPS_FIX_DIS);
6971 /* The below fixes the weird display corruption, a few pixels shifted
6972 * downward, on (only) LVDS of some HP laptops with IVY.
6973 */
6974 for_each_pipe(dev_priv, pipe) {
6975 val = I915_READ(TRANS_CHICKEN2(pipe));
6976 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6977 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6978 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6979 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6980 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6981 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6982 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6983 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6984 }
6985 /* WADP0ClockGatingDisable */
6986 for_each_pipe(dev_priv, pipe) {
6987 I915_WRITE(TRANS_CHICKEN1(pipe),
6988 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6989 }
6990}
6991
6992static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
6993{
6994 uint32_t tmp;
6995
6996 tmp = I915_READ(MCH_SSKPD);
6997 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6998 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6999 tmp);
7000}
7001
7002static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
7003{
7004 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7005
7006 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
7007
7008 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7009 I915_READ(ILK_DISPLAY_CHICKEN2) |
7010 ILK_ELPIN_409_SELECT);
7011
7012 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7013 I915_WRITE(_3D_CHICKEN,
7014 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7015
7016 /* WaDisable_RenderCache_OperationalFlush:snb */
7017 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7018
7019 /*
7020 * BSpec recoomends 8x4 when MSAA is used,
7021 * however in practice 16x4 seems fastest.
7022 *
7023 * Note that PS/WM thread counts depend on the WIZ hashing
7024 * disable bit, which we don't touch here, but it's good
7025 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7026 */
7027 I915_WRITE(GEN6_GT_MODE,
7028 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7029
7030 ilk_init_lp_watermarks(dev_priv);
7031
7032 I915_WRITE(CACHE_MODE_0,
7033 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
7034
7035 I915_WRITE(GEN6_UCGCTL1,
7036 I915_READ(GEN6_UCGCTL1) |
7037 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7038 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7039
7040 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7041 * gating disable must be set. Failure to set it results in
7042 * flickering pixels due to Z write ordering failures after
7043 * some amount of runtime in the Mesa "fire" demo, and Unigine
7044 * Sanctuary and Tropics, and apparently anything else with
7045 * alpha test or pixel discard.
7046 *
7047 * According to the spec, bit 11 (RCCUNIT) must also be set,
7048 * but we didn't debug actual testcases to find it out.
7049 *
7050 * WaDisableRCCUnitClockGating:snb
7051 * WaDisableRCPBUnitClockGating:snb
7052 */
7053 I915_WRITE(GEN6_UCGCTL2,
7054 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7055 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7056
7057 /* WaStripsFansDisableFastClipPerformanceFix:snb */
7058 I915_WRITE(_3D_CHICKEN3,
7059 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7060
7061 /*
7062 * Bspec says:
7063 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7064 * 3DSTATE_SF number of SF output attributes is more than 16."
7065 */
7066 I915_WRITE(_3D_CHICKEN3,
7067 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7068
7069 /*
7070 * According to the spec the following bits should be
7071 * set in order to enable memory self-refresh and fbc:
7072 * The bit21 and bit22 of 0x42000
7073 * The bit21 and bit22 of 0x42004
7074 * The bit5 and bit7 of 0x42020
7075 * The bit14 of 0x70180
7076 * The bit14 of 0x71180
7077 *
7078 * WaFbcAsynchFlipDisableFbcQueue:snb
7079 */
7080 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7081 I915_READ(ILK_DISPLAY_CHICKEN1) |
7082 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7083 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7084 I915_READ(ILK_DISPLAY_CHICKEN2) |
7085 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7086 I915_WRITE(ILK_DSPCLK_GATE_D,
7087 I915_READ(ILK_DSPCLK_GATE_D) |
7088 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7089 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7090
7091 g4x_disable_trickle_feed(dev_priv);
7092
7093 cpt_init_clock_gating(dev_priv);
7094
7095 gen6_check_mch_setup(dev_priv);
7096}
7097
7098static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7099{
7100 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7101
7102 /*
7103 * WaVSThreadDispatchOverride:ivb,vlv
7104 *
7105 * This actually overrides the dispatch
7106 * mode for all thread types.
7107 */
7108 reg &= ~GEN7_FF_SCHED_MASK;
7109 reg |= GEN7_FF_TS_SCHED_HW;
7110 reg |= GEN7_FF_VS_SCHED_HW;
7111 reg |= GEN7_FF_DS_SCHED_HW;
7112
7113 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7114}
7115
7116static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
7117{
7118 /*
7119 * TODO: this bit should only be enabled when really needed, then
7120 * disabled when not needed anymore in order to save power.
7121 */
7122 if (HAS_PCH_LPT_LP(dev_priv))
7123 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7124 I915_READ(SOUTH_DSPCLK_GATE_D) |
7125 PCH_LP_PARTITION_LEVEL_DISABLE);
7126
7127 /* WADPOClockGatingDisable:hsw */
7128 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7129 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7130 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7131}
7132
7133static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7134{
7135 if (HAS_PCH_LPT_LP(dev_priv)) {
7136 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7137
7138 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7139 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7140 }
7141}
7142
7143static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7144 int general_prio_credits,
7145 int high_prio_credits)
7146{
7147 u32 misccpctl;
7148
7149 /* WaTempDisableDOPClkGating:bdw */
7150 misccpctl = I915_READ(GEN7_MISCCPCTL);
7151 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7152
7153 I915_WRITE(GEN8_L3SQCREG1,
7154 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7155 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7156
7157 /*
7158 * Wait at least 100 clocks before re-enabling clock gating.
7159 * See the definition of L3SQCREG1 in BSpec.
7160 */
7161 POSTING_READ(GEN8_L3SQCREG1);
7162 udelay(1);
7163 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7164}
7165
7166static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
7167{
7168 gen9_init_clock_gating(dev_priv);
7169
7170 /* WaDisableSDEUnitClockGating:kbl */
7171 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7172 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7173 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7174
7175 /* WaDisableGamClockGating:kbl */
7176 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7177 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7178 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7179
7180 /* WaFbcNukeOnHostModify:kbl */
7181 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7182 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7183}
7184
7185static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
7186{
7187 gen9_init_clock_gating(dev_priv);
7188
7189 /* WAC6entrylatency:skl */
7190 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7191 FBC_LLC_FULLY_OPEN);
7192
7193 /* WaFbcNukeOnHostModify:skl */
7194 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7195 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7196}
7197
7198static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
7199{
7200 enum pipe pipe;
7201
7202 ilk_init_lp_watermarks(dev_priv);
7203
7204 /* WaSwitchSolVfFArbitrationPriority:bdw */
7205 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7206
7207 /* WaPsrDPAMaskVBlankInSRD:bdw */
7208 I915_WRITE(CHICKEN_PAR1_1,
7209 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7210
7211 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7212 for_each_pipe(dev_priv, pipe) {
7213 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7214 I915_READ(CHICKEN_PIPESL_1(pipe)) |
7215 BDW_DPRS_MASK_VBLANK_SRD);
7216 }
7217
7218 /* WaVSRefCountFullforceMissDisable:bdw */
7219 /* WaDSRefCountFullforceMissDisable:bdw */
7220 I915_WRITE(GEN7_FF_THREAD_MODE,
7221 I915_READ(GEN7_FF_THREAD_MODE) &
7222 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7223
7224 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7225 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7226
7227 /* WaDisableSDEUnitClockGating:bdw */
7228 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7229 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7230
7231 /* WaProgramL3SqcReg1Default:bdw */
7232 gen8_set_l3sqc_credits(dev_priv, 30, 2);
7233
7234 /*
7235 * WaGttCachingOffByDefault:bdw
7236 * GTT cache may not work with big pages, so if those
7237 * are ever enabled GTT cache may need to be disabled.
7238 */
7239 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7240
7241 /* WaKVMNotificationOnConfigChange:bdw */
7242 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7243 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7244
7245 lpt_init_clock_gating(dev_priv);
7246}
7247
7248static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
7249{
7250 ilk_init_lp_watermarks(dev_priv);
7251
7252 /* L3 caching of data atomics doesn't work -- disable it. */
7253 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7254 I915_WRITE(HSW_ROW_CHICKEN3,
7255 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7256
7257 /* This is required by WaCatErrorRejectionIssue:hsw */
7258 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7259 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7260 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7261
7262 /* WaVSRefCountFullforceMissDisable:hsw */
7263 I915_WRITE(GEN7_FF_THREAD_MODE,
7264 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7265
7266 /* WaDisable_RenderCache_OperationalFlush:hsw */
7267 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7268
7269 /* enable HiZ Raw Stall Optimization */
7270 I915_WRITE(CACHE_MODE_0_GEN7,
7271 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7272
7273 /* WaDisable4x2SubspanOptimization:hsw */
7274 I915_WRITE(CACHE_MODE_1,
7275 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7276
7277 /*
7278 * BSpec recommends 8x4 when MSAA is used,
7279 * however in practice 16x4 seems fastest.
7280 *
7281 * Note that PS/WM thread counts depend on the WIZ hashing
7282 * disable bit, which we don't touch here, but it's good
7283 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7284 */
7285 I915_WRITE(GEN7_GT_MODE,
7286 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7287
7288 /* WaSampleCChickenBitEnable:hsw */
7289 I915_WRITE(HALF_SLICE_CHICKEN3,
7290 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7291
7292 /* WaSwitchSolVfFArbitrationPriority:hsw */
7293 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7294
7295 /* WaRsPkgCStateDisplayPMReq:hsw */
7296 I915_WRITE(CHICKEN_PAR1_1,
7297 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7298
7299 lpt_init_clock_gating(dev_priv);
7300}
7301
7302static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
7303{
7304 uint32_t snpcr;
7305
7306 ilk_init_lp_watermarks(dev_priv);
7307
7308 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7309
7310 /* WaDisableEarlyCull:ivb */
7311 I915_WRITE(_3D_CHICKEN3,
7312 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7313
7314 /* WaDisableBackToBackFlipFix:ivb */
7315 I915_WRITE(IVB_CHICKEN3,
7316 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7317 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7318
7319 /* WaDisablePSDDualDispatchEnable:ivb */
7320 if (IS_IVB_GT1(dev_priv))
7321 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7322 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7323
7324 /* WaDisable_RenderCache_OperationalFlush:ivb */
7325 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7326
7327 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7328 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7329 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7330
7331 /* WaApplyL3ControlAndL3ChickenMode:ivb */
7332 I915_WRITE(GEN7_L3CNTLREG1,
7333 GEN7_WA_FOR_GEN7_L3_CONTROL);
7334 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7335 GEN7_WA_L3_CHICKEN_MODE);
7336 if (IS_IVB_GT1(dev_priv))
7337 I915_WRITE(GEN7_ROW_CHICKEN2,
7338 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7339 else {
7340 /* must write both registers */
7341 I915_WRITE(GEN7_ROW_CHICKEN2,
7342 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7343 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7344 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7345 }
7346
7347 /* WaForceL3Serialization:ivb */
7348 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7349 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7350
7351 /*
7352 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7353 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7354 */
7355 I915_WRITE(GEN6_UCGCTL2,
7356 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7357
7358 /* This is required by WaCatErrorRejectionIssue:ivb */
7359 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7360 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7361 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7362
7363 g4x_disable_trickle_feed(dev_priv);
7364
7365 gen7_setup_fixed_func_scheduler(dev_priv);
7366
7367 if (0) { /* causes HiZ corruption on ivb:gt1 */
7368 /* enable HiZ Raw Stall Optimization */
7369 I915_WRITE(CACHE_MODE_0_GEN7,
7370 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7371 }
7372
7373 /* WaDisable4x2SubspanOptimization:ivb */
7374 I915_WRITE(CACHE_MODE_1,
7375 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7376
7377 /*
7378 * BSpec recommends 8x4 when MSAA is used,
7379 * however in practice 16x4 seems fastest.
7380 *
7381 * Note that PS/WM thread counts depend on the WIZ hashing
7382 * disable bit, which we don't touch here, but it's good
7383 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7384 */
7385 I915_WRITE(GEN7_GT_MODE,
7386 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7387
7388 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7389 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7390 snpcr |= GEN6_MBC_SNPCR_MED;
7391 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7392
7393 if (!HAS_PCH_NOP(dev_priv))
7394 cpt_init_clock_gating(dev_priv);
7395
7396 gen6_check_mch_setup(dev_priv);
7397}
7398
7399static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
7400{
7401 /* WaDisableEarlyCull:vlv */
7402 I915_WRITE(_3D_CHICKEN3,
7403 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7404
7405 /* WaDisableBackToBackFlipFix:vlv */
7406 I915_WRITE(IVB_CHICKEN3,
7407 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7408 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7409
7410 /* WaPsdDispatchEnable:vlv */
7411 /* WaDisablePSDDualDispatchEnable:vlv */
7412 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7413 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7414 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7415
7416 /* WaDisable_RenderCache_OperationalFlush:vlv */
7417 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7418
7419 /* WaForceL3Serialization:vlv */
7420 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7421 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7422
7423 /* WaDisableDopClockGating:vlv */
7424 I915_WRITE(GEN7_ROW_CHICKEN2,
7425 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7426
7427 /* This is required by WaCatErrorRejectionIssue:vlv */
7428 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7429 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7430 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7431
7432 gen7_setup_fixed_func_scheduler(dev_priv);
7433
7434 /*
7435 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7436 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7437 */
7438 I915_WRITE(GEN6_UCGCTL2,
7439 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7440
7441 /* WaDisableL3Bank2xClockGate:vlv
7442 * Disabling L3 clock gating- MMIO 940c[25] = 1
7443 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7444 I915_WRITE(GEN7_UCGCTL4,
7445 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7446
7447 /*
7448 * BSpec says this must be set, even though
7449 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7450 */
7451 I915_WRITE(CACHE_MODE_1,
7452 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7453
7454 /*
7455 * BSpec recommends 8x4 when MSAA is used,
7456 * however in practice 16x4 seems fastest.
7457 *
7458 * Note that PS/WM thread counts depend on the WIZ hashing
7459 * disable bit, which we don't touch here, but it's good
7460 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7461 */
7462 I915_WRITE(GEN7_GT_MODE,
7463 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7464
7465 /*
7466 * WaIncreaseL3CreditsForVLVB0:vlv
7467 * This is the hardware default actually.
7468 */
7469 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7470
7471 /*
7472 * WaDisableVLVClockGating_VBIIssue:vlv
7473 * Disable clock gating on th GCFG unit to prevent a delay
7474 * in the reporting of vblank events.
7475 */
7476 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7477}
7478
7479static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
7480{
7481 /* WaVSRefCountFullforceMissDisable:chv */
7482 /* WaDSRefCountFullforceMissDisable:chv */
7483 I915_WRITE(GEN7_FF_THREAD_MODE,
7484 I915_READ(GEN7_FF_THREAD_MODE) &
7485 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7486
7487 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7488 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7489 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7490
7491 /* WaDisableCSUnitClockGating:chv */
7492 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7493 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7494
7495 /* WaDisableSDEUnitClockGating:chv */
7496 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7497 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7498
7499 /*
7500 * WaProgramL3SqcReg1Default:chv
7501 * See gfxspecs/Related Documents/Performance Guide/
7502 * LSQC Setting Recommendations.
7503 */
7504 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7505
7506 /*
7507 * GTT cache may not work with big pages, so if those
7508 * are ever enabled GTT cache may need to be disabled.
7509 */
7510 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7511}
7512
7513static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
7514{
7515 uint32_t dspclk_gate;
7516
7517 I915_WRITE(RENCLK_GATE_D1, 0);
7518 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7519 GS_UNIT_CLOCK_GATE_DISABLE |
7520 CL_UNIT_CLOCK_GATE_DISABLE);
7521 I915_WRITE(RAMCLK_GATE_D, 0);
7522 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7523 OVRUNIT_CLOCK_GATE_DISABLE |
7524 OVCUNIT_CLOCK_GATE_DISABLE;
7525 if (IS_GM45(dev_priv))
7526 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7527 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7528
7529 /* WaDisableRenderCachePipelinedFlush */
7530 I915_WRITE(CACHE_MODE_0,
7531 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7532
7533 /* WaDisable_RenderCache_OperationalFlush:g4x */
7534 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7535
7536 g4x_disable_trickle_feed(dev_priv);
7537}
7538
7539static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
7540{
7541 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7542 I915_WRITE(RENCLK_GATE_D2, 0);
7543 I915_WRITE(DSPCLK_GATE_D, 0);
7544 I915_WRITE(RAMCLK_GATE_D, 0);
7545 I915_WRITE16(DEUC, 0);
7546 I915_WRITE(MI_ARB_STATE,
7547 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7548
7549 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7550 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7551}
7552
7553static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
7554{
7555 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7556 I965_RCC_CLOCK_GATE_DISABLE |
7557 I965_RCPB_CLOCK_GATE_DISABLE |
7558 I965_ISC_CLOCK_GATE_DISABLE |
7559 I965_FBC_CLOCK_GATE_DISABLE);
7560 I915_WRITE(RENCLK_GATE_D2, 0);
7561 I915_WRITE(MI_ARB_STATE,
7562 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7563
7564 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7565 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7566}
7567
7568static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
7569{
7570 u32 dstate = I915_READ(D_STATE);
7571
7572 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7573 DSTATE_DOT_CLOCK_GATING;
7574 I915_WRITE(D_STATE, dstate);
7575
7576 if (IS_PINEVIEW(dev_priv))
7577 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7578
7579 /* IIR "flip pending" means done if this bit is set */
7580 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7581
7582 /* interrupts should cause a wake up from C3 */
7583 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7584
7585 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7586 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7587
7588 I915_WRITE(MI_ARB_STATE,
7589 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7590}
7591
7592static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
7593{
7594 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7595
7596 /* interrupts should cause a wake up from C3 */
7597 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7598 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7599
7600 I915_WRITE(MEM_MODE,
7601 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7602}
7603
7604static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
7605{
7606 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7607
7608 I915_WRITE(MEM_MODE,
7609 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7610 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7611}
7612
7613void intel_init_clock_gating(struct drm_i915_private *dev_priv)
7614{
7615 dev_priv->display.init_clock_gating(dev_priv);
7616}
7617
7618void intel_suspend_hw(struct drm_i915_private *dev_priv)
7619{
7620 if (HAS_PCH_LPT(dev_priv))
7621 lpt_suspend_hw(dev_priv);
7622}
7623
7624static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
7625{
7626 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7627}
7628
7629/**
7630 * intel_init_clock_gating_hooks - setup the clock gating hooks
7631 * @dev_priv: device private
7632 *
7633 * Setup the hooks that configure which clocks of a given platform can be
7634 * gated and also apply various GT and display specific workarounds for these
7635 * platforms. Note that some GT specific workarounds are applied separately
7636 * when GPU contexts or batchbuffers start their execution.
7637 */
7638void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7639{
7640 if (IS_SKYLAKE(dev_priv))
7641 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7642 else if (IS_KABYLAKE(dev_priv))
7643 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7644 else if (IS_BROXTON(dev_priv))
7645 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7646 else if (IS_BROADWELL(dev_priv))
7647 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7648 else if (IS_CHERRYVIEW(dev_priv))
7649 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7650 else if (IS_HASWELL(dev_priv))
7651 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7652 else if (IS_IVYBRIDGE(dev_priv))
7653 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7654 else if (IS_VALLEYVIEW(dev_priv))
7655 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7656 else if (IS_GEN6(dev_priv))
7657 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7658 else if (IS_GEN5(dev_priv))
7659 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7660 else if (IS_G4X(dev_priv))
7661 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7662 else if (IS_CRESTLINE(dev_priv))
7663 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7664 else if (IS_BROADWATER(dev_priv))
7665 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7666 else if (IS_GEN3(dev_priv))
7667 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7668 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7669 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7670 else if (IS_GEN2(dev_priv))
7671 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7672 else {
7673 MISSING_CASE(INTEL_DEVID(dev_priv));
7674 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7675 }
7676}
7677
7678/* Set up chip specific power management-related functions */
7679void intel_init_pm(struct drm_i915_private *dev_priv)
7680{
7681 intel_fbc_init(dev_priv);
7682
7683 /* For cxsr */
7684 if (IS_PINEVIEW(dev_priv))
7685 i915_pineview_get_mem_freq(dev_priv);
7686 else if (IS_GEN5(dev_priv))
7687 i915_ironlake_get_mem_freq(dev_priv);
7688
7689 /* For FIFO watermark updates */
7690 if (INTEL_GEN(dev_priv) >= 9) {
7691 skl_setup_wm_latency(dev_priv);
7692 dev_priv->display.initial_watermarks = skl_initial_wm;
7693 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
7694 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7695 } else if (HAS_PCH_SPLIT(dev_priv)) {
7696 ilk_setup_wm_latency(dev_priv);
7697
7698 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
7699 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7700 (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
7701 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7702 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7703 dev_priv->display.compute_intermediate_wm =
7704 ilk_compute_intermediate_wm;
7705 dev_priv->display.initial_watermarks =
7706 ilk_initial_watermarks;
7707 dev_priv->display.optimize_watermarks =
7708 ilk_optimize_watermarks;
7709 } else {
7710 DRM_DEBUG_KMS("Failed to read display plane latency. "
7711 "Disable CxSR\n");
7712 }
7713 } else if (IS_CHERRYVIEW(dev_priv)) {
7714 vlv_setup_wm_latency(dev_priv);
7715 dev_priv->display.update_wm = vlv_update_wm;
7716 } else if (IS_VALLEYVIEW(dev_priv)) {
7717 vlv_setup_wm_latency(dev_priv);
7718 dev_priv->display.update_wm = vlv_update_wm;
7719 } else if (IS_PINEVIEW(dev_priv)) {
7720 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
7721 dev_priv->is_ddr3,
7722 dev_priv->fsb_freq,
7723 dev_priv->mem_freq)) {
7724 DRM_INFO("failed to find known CxSR latency "
7725 "(found ddr%s fsb freq %d, mem freq %d), "
7726 "disabling CxSR\n",
7727 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7728 dev_priv->fsb_freq, dev_priv->mem_freq);
7729 /* Disable CxSR and never update its watermark again */
7730 intel_set_memory_cxsr(dev_priv, false);
7731 dev_priv->display.update_wm = NULL;
7732 } else
7733 dev_priv->display.update_wm = pineview_update_wm;
7734 } else if (IS_G4X(dev_priv)) {
7735 dev_priv->display.update_wm = g4x_update_wm;
7736 } else if (IS_GEN4(dev_priv)) {
7737 dev_priv->display.update_wm = i965_update_wm;
7738 } else if (IS_GEN3(dev_priv)) {
7739 dev_priv->display.update_wm = i9xx_update_wm;
7740 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7741 } else if (IS_GEN2(dev_priv)) {
7742 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
7743 dev_priv->display.update_wm = i845_update_wm;
7744 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7745 } else {
7746 dev_priv->display.update_wm = i9xx_update_wm;
7747 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7748 }
7749 } else {
7750 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7751 }
7752}
7753
7754static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7755{
7756 uint32_t flags =
7757 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7758
7759 switch (flags) {
7760 case GEN6_PCODE_SUCCESS:
7761 return 0;
7762 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7763 case GEN6_PCODE_ILLEGAL_CMD:
7764 return -ENXIO;
7765 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7766 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7767 return -EOVERFLOW;
7768 case GEN6_PCODE_TIMEOUT:
7769 return -ETIMEDOUT;
7770 default:
7771 MISSING_CASE(flags)
7772 return 0;
7773 }
7774}
7775
7776static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7777{
7778 uint32_t flags =
7779 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7780
7781 switch (flags) {
7782 case GEN6_PCODE_SUCCESS:
7783 return 0;
7784 case GEN6_PCODE_ILLEGAL_CMD:
7785 return -ENXIO;
7786 case GEN7_PCODE_TIMEOUT:
7787 return -ETIMEDOUT;
7788 case GEN7_PCODE_ILLEGAL_DATA:
7789 return -EINVAL;
7790 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7791 return -EOVERFLOW;
7792 default:
7793 MISSING_CASE(flags);
7794 return 0;
7795 }
7796}
7797
7798int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7799{
7800 int status;
7801
7802 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7803
7804 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7805 * use te fw I915_READ variants to reduce the amount of work
7806 * required when reading/writing.
7807 */
7808
7809 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7810 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7811 return -EAGAIN;
7812 }
7813
7814 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7815 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7816 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7817
7818 if (intel_wait_for_register_fw(dev_priv,
7819 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7820 500)) {
7821 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7822 return -ETIMEDOUT;
7823 }
7824
7825 *val = I915_READ_FW(GEN6_PCODE_DATA);
7826 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7827
7828 if (INTEL_GEN(dev_priv) > 6)
7829 status = gen7_check_mailbox_status(dev_priv);
7830 else
7831 status = gen6_check_mailbox_status(dev_priv);
7832
7833 if (status) {
7834 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7835 status);
7836 return status;
7837 }
7838
7839 return 0;
7840}
7841
7842int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7843 u32 mbox, u32 val)
7844{
7845 int status;
7846
7847 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7848
7849 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7850 * use te fw I915_READ variants to reduce the amount of work
7851 * required when reading/writing.
7852 */
7853
7854 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7855 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7856 return -EAGAIN;
7857 }
7858
7859 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7860 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7861
7862 if (intel_wait_for_register_fw(dev_priv,
7863 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7864 500)) {
7865 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7866 return -ETIMEDOUT;
7867 }
7868
7869 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7870
7871 if (INTEL_GEN(dev_priv) > 6)
7872 status = gen7_check_mailbox_status(dev_priv);
7873 else
7874 status = gen6_check_mailbox_status(dev_priv);
7875
7876 if (status) {
7877 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7878 status);
7879 return status;
7880 }
7881
7882 return 0;
7883}
7884
7885static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
7886 u32 request, u32 reply_mask, u32 reply,
7887 u32 *status)
7888{
7889 u32 val = request;
7890
7891 *status = sandybridge_pcode_read(dev_priv, mbox, &val);
7892
7893 return *status || ((val & reply_mask) == reply);
7894}
7895
7896/**
7897 * skl_pcode_request - send PCODE request until acknowledgment
7898 * @dev_priv: device private
7899 * @mbox: PCODE mailbox ID the request is targeted for
7900 * @request: request ID
7901 * @reply_mask: mask used to check for request acknowledgment
7902 * @reply: value used to check for request acknowledgment
7903 * @timeout_base_ms: timeout for polling with preemption enabled
7904 *
7905 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
7906 * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
7907 * The request is acknowledged once the PCODE reply dword equals @reply after
7908 * applying @reply_mask. Polling is first attempted with preemption enabled
7909 * for @timeout_base_ms and if this times out for another 50 ms with
7910 * preemption disabled.
7911 *
7912 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
7913 * other error as reported by PCODE.
7914 */
7915int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
7916 u32 reply_mask, u32 reply, int timeout_base_ms)
7917{
7918 u32 status;
7919 int ret;
7920
7921 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7922
7923#define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
7924 &status)
7925
7926 /*
7927 * Prime the PCODE by doing a request first. Normally it guarantees
7928 * that a subsequent request, at most @timeout_base_ms later, succeeds.
7929 * _wait_for() doesn't guarantee when its passed condition is evaluated
7930 * first, so send the first request explicitly.
7931 */
7932 if (COND) {
7933 ret = 0;
7934 goto out;
7935 }
7936 ret = _wait_for(COND, timeout_base_ms * 1000, 10);
7937 if (!ret)
7938 goto out;
7939
7940 /*
7941 * The above can time out if the number of requests was low (2 in the
7942 * worst case) _and_ PCODE was busy for some reason even after a
7943 * (queued) request and @timeout_base_ms delay. As a workaround retry
7944 * the poll with preemption disabled to maximize the number of
7945 * requests. Increase the timeout from @timeout_base_ms to 50ms to
7946 * account for interrupts that could reduce the number of these
7947 * requests, and for any quirks of the PCODE firmware that delays
7948 * the request completion.
7949 */
7950 DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
7951 WARN_ON_ONCE(timeout_base_ms > 3);
7952 preempt_disable();
7953 ret = wait_for_atomic(COND, 50);
7954 preempt_enable();
7955
7956out:
7957 return ret ? ret : status;
7958#undef COND
7959}
7960
7961static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7962{
7963 /*
7964 * N = val - 0xb7
7965 * Slow = Fast = GPLL ref * N
7966 */
7967 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7968}
7969
7970static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7971{
7972 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7973}
7974
7975static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7976{
7977 /*
7978 * N = val / 2
7979 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7980 */
7981 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7982}
7983
7984static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7985{
7986 /* CHV needs even values */
7987 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7988}
7989
7990int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7991{
7992 if (IS_GEN9(dev_priv))
7993 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7994 GEN9_FREQ_SCALER);
7995 else if (IS_CHERRYVIEW(dev_priv))
7996 return chv_gpu_freq(dev_priv, val);
7997 else if (IS_VALLEYVIEW(dev_priv))
7998 return byt_gpu_freq(dev_priv, val);
7999 else
8000 return val * GT_FREQUENCY_MULTIPLIER;
8001}
8002
8003int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
8004{
8005 if (IS_GEN9(dev_priv))
8006 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
8007 GT_FREQUENCY_MULTIPLIER);
8008 else if (IS_CHERRYVIEW(dev_priv))
8009 return chv_freq_opcode(dev_priv, val);
8010 else if (IS_VALLEYVIEW(dev_priv))
8011 return byt_freq_opcode(dev_priv, val);
8012 else
8013 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
8014}
8015
8016struct request_boost {
8017 struct work_struct work;
8018 struct drm_i915_gem_request *req;
8019};
8020
8021static void __intel_rps_boost_work(struct work_struct *work)
8022{
8023 struct request_boost *boost = container_of(work, struct request_boost, work);
8024 struct drm_i915_gem_request *req = boost->req;
8025
8026 if (!i915_gem_request_completed(req))
8027 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
8028
8029 i915_gem_request_put(req);
8030 kfree(boost);
8031}
8032
8033void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
8034{
8035 struct request_boost *boost;
8036
8037 if (req == NULL || INTEL_GEN(req->i915) < 6)
8038 return;
8039
8040 if (i915_gem_request_completed(req))
8041 return;
8042
8043 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8044 if (boost == NULL)
8045 return;
8046
8047 boost->req = i915_gem_request_get(req);
8048
8049 INIT_WORK(&boost->work, __intel_rps_boost_work);
8050 queue_work(req->i915->wq, &boost->work);
8051}
8052
8053void intel_pm_setup(struct drm_device *dev)
8054{
8055 struct drm_i915_private *dev_priv = to_i915(dev);
8056
8057 mutex_init(&dev_priv->rps.hw_lock);
8058 spin_lock_init(&dev_priv->rps.client_lock);
8059
8060 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8061 __intel_autoenable_gt_powersave);
8062 INIT_LIST_HEAD(&dev_priv->rps.clients);
8063
8064 dev_priv->pm.suspended = false;
8065 atomic_set(&dev_priv->pm.wakeref_count, 0);
8066}