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1#include <linux/init.h>
2
3#include <linux/mm.h>
4#include <linux/spinlock.h>
5#include <linux/smp.h>
6#include <linux/interrupt.h>
7#include <linux/module.h>
8#include <linux/cpu.h>
9
10#include <asm/tlbflush.h>
11#include <asm/mmu_context.h>
12#include <asm/cache.h>
13#include <asm/apic.h>
14#include <asm/uv/uv.h>
15#include <linux/debugfs.h>
16
17/*
18 * Smarter SMP flushing macros.
19 * c/o Linus Torvalds.
20 *
21 * These mean you can really definitely utterly forget about
22 * writing to user space from interrupts. (Its not allowed anyway).
23 *
24 * Optimizations Manfred Spraul <manfred@colorfullife.com>
25 *
26 * More scalable flush, from Andi Kleen
27 *
28 * Implement flush IPI by CALL_FUNCTION_VECTOR, Alex Shi
29 */
30
31struct flush_tlb_info {
32 struct mm_struct *flush_mm;
33 unsigned long flush_start;
34 unsigned long flush_end;
35};
36
37/*
38 * We cannot call mmdrop() because we are in interrupt context,
39 * instead update mm->cpu_vm_mask.
40 */
41void leave_mm(int cpu)
42{
43 struct mm_struct *active_mm = this_cpu_read(cpu_tlbstate.active_mm);
44 if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
45 BUG();
46 if (cpumask_test_cpu(cpu, mm_cpumask(active_mm))) {
47 cpumask_clear_cpu(cpu, mm_cpumask(active_mm));
48 load_cr3(swapper_pg_dir);
49 /*
50 * This gets called in the idle path where RCU
51 * functions differently. Tracing normally
52 * uses RCU, so we have to call the tracepoint
53 * specially here.
54 */
55 trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
56 }
57}
58EXPORT_SYMBOL_GPL(leave_mm);
59
60/*
61 * The flush IPI assumes that a thread switch happens in this order:
62 * [cpu0: the cpu that switches]
63 * 1) switch_mm() either 1a) or 1b)
64 * 1a) thread switch to a different mm
65 * 1a1) set cpu_tlbstate to TLBSTATE_OK
66 * Now the tlb flush NMI handler flush_tlb_func won't call leave_mm
67 * if cpu0 was in lazy tlb mode.
68 * 1a2) update cpu active_mm
69 * Now cpu0 accepts tlb flushes for the new mm.
70 * 1a3) cpu_set(cpu, new_mm->cpu_vm_mask);
71 * Now the other cpus will send tlb flush ipis.
72 * 1a4) change cr3.
73 * 1a5) cpu_clear(cpu, old_mm->cpu_vm_mask);
74 * Stop ipi delivery for the old mm. This is not synchronized with
75 * the other cpus, but flush_tlb_func ignore flush ipis for the wrong
76 * mm, and in the worst case we perform a superfluous tlb flush.
77 * 1b) thread switch without mm change
78 * cpu active_mm is correct, cpu0 already handles flush ipis.
79 * 1b1) set cpu_tlbstate to TLBSTATE_OK
80 * 1b2) test_and_set the cpu bit in cpu_vm_mask.
81 * Atomically set the bit [other cpus will start sending flush ipis],
82 * and test the bit.
83 * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
84 * 2) switch %%esp, ie current
85 *
86 * The interrupt must handle 2 special cases:
87 * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
88 * - the cpu performs speculative tlb reads, i.e. even if the cpu only
89 * runs in kernel space, the cpu could load tlb entries for user space
90 * pages.
91 *
92 * The good news is that cpu_tlbstate is local to each cpu, no
93 * write/read ordering problems.
94 */
95
96/*
97 * TLB flush funcation:
98 * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
99 * 2) Leave the mm if we are in the lazy tlb mode.
100 */
101static void flush_tlb_func(void *info)
102{
103 struct flush_tlb_info *f = info;
104
105 inc_irq_stat(irq_tlb_count);
106
107 if (f->flush_mm && f->flush_mm != this_cpu_read(cpu_tlbstate.active_mm))
108 return;
109
110 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
111 if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
112 if (f->flush_end == TLB_FLUSH_ALL) {
113 local_flush_tlb();
114 trace_tlb_flush(TLB_REMOTE_SHOOTDOWN, TLB_FLUSH_ALL);
115 } else {
116 unsigned long addr;
117 unsigned long nr_pages =
118 (f->flush_end - f->flush_start) / PAGE_SIZE;
119 addr = f->flush_start;
120 while (addr < f->flush_end) {
121 __flush_tlb_single(addr);
122 addr += PAGE_SIZE;
123 }
124 trace_tlb_flush(TLB_REMOTE_SHOOTDOWN, nr_pages);
125 }
126 } else
127 leave_mm(smp_processor_id());
128
129}
130
131void native_flush_tlb_others(const struct cpumask *cpumask,
132 struct mm_struct *mm, unsigned long start,
133 unsigned long end)
134{
135 struct flush_tlb_info info;
136
137 if (end == 0)
138 end = start + PAGE_SIZE;
139 info.flush_mm = mm;
140 info.flush_start = start;
141 info.flush_end = end;
142
143 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
144 if (end == TLB_FLUSH_ALL)
145 trace_tlb_flush(TLB_REMOTE_SEND_IPI, TLB_FLUSH_ALL);
146 else
147 trace_tlb_flush(TLB_REMOTE_SEND_IPI,
148 (end - start) >> PAGE_SHIFT);
149
150 if (is_uv_system()) {
151 unsigned int cpu;
152
153 cpu = smp_processor_id();
154 cpumask = uv_flush_tlb_others(cpumask, mm, start, end, cpu);
155 if (cpumask)
156 smp_call_function_many(cpumask, flush_tlb_func,
157 &info, 1);
158 return;
159 }
160 smp_call_function_many(cpumask, flush_tlb_func, &info, 1);
161}
162
163void flush_tlb_current_task(void)
164{
165 struct mm_struct *mm = current->mm;
166
167 preempt_disable();
168
169 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
170
171 /* This is an implicit full barrier that synchronizes with switch_mm. */
172 local_flush_tlb();
173
174 trace_tlb_flush(TLB_LOCAL_SHOOTDOWN, TLB_FLUSH_ALL);
175 if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
176 flush_tlb_others(mm_cpumask(mm), mm, 0UL, TLB_FLUSH_ALL);
177 preempt_enable();
178}
179
180/*
181 * See Documentation/x86/tlb.txt for details. We choose 33
182 * because it is large enough to cover the vast majority (at
183 * least 95%) of allocations, and is small enough that we are
184 * confident it will not cause too much overhead. Each single
185 * flush is about 100 ns, so this caps the maximum overhead at
186 * _about_ 3,000 ns.
187 *
188 * This is in units of pages.
189 */
190static unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
191
192void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
193 unsigned long end, unsigned long vmflag)
194{
195 unsigned long addr;
196 /* do a global flush by default */
197 unsigned long base_pages_to_flush = TLB_FLUSH_ALL;
198
199 preempt_disable();
200 if (current->active_mm != mm) {
201 /* Synchronize with switch_mm. */
202 smp_mb();
203
204 goto out;
205 }
206
207 if (!current->mm) {
208 leave_mm(smp_processor_id());
209
210 /* Synchronize with switch_mm. */
211 smp_mb();
212
213 goto out;
214 }
215
216 if ((end != TLB_FLUSH_ALL) && !(vmflag & VM_HUGETLB))
217 base_pages_to_flush = (end - start) >> PAGE_SHIFT;
218
219 /*
220 * Both branches below are implicit full barriers (MOV to CR or
221 * INVLPG) that synchronize with switch_mm.
222 */
223 if (base_pages_to_flush > tlb_single_page_flush_ceiling) {
224 base_pages_to_flush = TLB_FLUSH_ALL;
225 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
226 local_flush_tlb();
227 } else {
228 /* flush range by one by one 'invlpg' */
229 for (addr = start; addr < end; addr += PAGE_SIZE) {
230 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
231 __flush_tlb_single(addr);
232 }
233 }
234 trace_tlb_flush(TLB_LOCAL_MM_SHOOTDOWN, base_pages_to_flush);
235out:
236 if (base_pages_to_flush == TLB_FLUSH_ALL) {
237 start = 0UL;
238 end = TLB_FLUSH_ALL;
239 }
240 if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
241 flush_tlb_others(mm_cpumask(mm), mm, start, end);
242 preempt_enable();
243}
244
245void flush_tlb_page(struct vm_area_struct *vma, unsigned long start)
246{
247 struct mm_struct *mm = vma->vm_mm;
248
249 preempt_disable();
250
251 if (current->active_mm == mm) {
252 if (current->mm) {
253 /*
254 * Implicit full barrier (INVLPG) that synchronizes
255 * with switch_mm.
256 */
257 __flush_tlb_one(start);
258 } else {
259 leave_mm(smp_processor_id());
260
261 /* Synchronize with switch_mm. */
262 smp_mb();
263 }
264 }
265
266 if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
267 flush_tlb_others(mm_cpumask(mm), mm, start, 0UL);
268
269 preempt_enable();
270}
271
272static void do_flush_tlb_all(void *info)
273{
274 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
275 __flush_tlb_all();
276 if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_LAZY)
277 leave_mm(smp_processor_id());
278}
279
280void flush_tlb_all(void)
281{
282 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
283 on_each_cpu(do_flush_tlb_all, NULL, 1);
284}
285
286static void do_kernel_range_flush(void *info)
287{
288 struct flush_tlb_info *f = info;
289 unsigned long addr;
290
291 /* flush range by one by one 'invlpg' */
292 for (addr = f->flush_start; addr < f->flush_end; addr += PAGE_SIZE)
293 __flush_tlb_single(addr);
294}
295
296void flush_tlb_kernel_range(unsigned long start, unsigned long end)
297{
298
299 /* Balance as user space task's flush, a bit conservative */
300 if (end == TLB_FLUSH_ALL ||
301 (end - start) > tlb_single_page_flush_ceiling * PAGE_SIZE) {
302 on_each_cpu(do_flush_tlb_all, NULL, 1);
303 } else {
304 struct flush_tlb_info info;
305 info.flush_start = start;
306 info.flush_end = end;
307 on_each_cpu(do_kernel_range_flush, &info, 1);
308 }
309}
310
311static ssize_t tlbflush_read_file(struct file *file, char __user *user_buf,
312 size_t count, loff_t *ppos)
313{
314 char buf[32];
315 unsigned int len;
316
317 len = sprintf(buf, "%ld\n", tlb_single_page_flush_ceiling);
318 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
319}
320
321static ssize_t tlbflush_write_file(struct file *file,
322 const char __user *user_buf, size_t count, loff_t *ppos)
323{
324 char buf[32];
325 ssize_t len;
326 int ceiling;
327
328 len = min(count, sizeof(buf) - 1);
329 if (copy_from_user(buf, user_buf, len))
330 return -EFAULT;
331
332 buf[len] = '\0';
333 if (kstrtoint(buf, 0, &ceiling))
334 return -EINVAL;
335
336 if (ceiling < 0)
337 return -EINVAL;
338
339 tlb_single_page_flush_ceiling = ceiling;
340 return count;
341}
342
343static const struct file_operations fops_tlbflush = {
344 .read = tlbflush_read_file,
345 .write = tlbflush_write_file,
346 .llseek = default_llseek,
347};
348
349static int __init create_tlb_single_page_flush_ceiling(void)
350{
351 debugfs_create_file("tlb_single_page_flush_ceiling", S_IRUSR | S_IWUSR,
352 arch_debugfs_dir, NULL, &fops_tlbflush);
353 return 0;
354}
355late_initcall(create_tlb_single_page_flush_ceiling);
1#include <linux/init.h>
2
3#include <linux/mm.h>
4#include <linux/spinlock.h>
5#include <linux/smp.h>
6#include <linux/interrupt.h>
7#include <linux/module.h>
8#include <linux/cpu.h>
9
10#include <asm/tlbflush.h>
11#include <asm/mmu_context.h>
12#include <asm/cache.h>
13#include <asm/apic.h>
14#include <asm/uv/uv.h>
15
16DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate)
17 = { &init_mm, 0, };
18
19/*
20 * Smarter SMP flushing macros.
21 * c/o Linus Torvalds.
22 *
23 * These mean you can really definitely utterly forget about
24 * writing to user space from interrupts. (Its not allowed anyway).
25 *
26 * Optimizations Manfred Spraul <manfred@colorfullife.com>
27 *
28 * More scalable flush, from Andi Kleen
29 *
30 * To avoid global state use 8 different call vectors.
31 * Each CPU uses a specific vector to trigger flushes on other
32 * CPUs. Depending on the received vector the target CPUs look into
33 * the right array slot for the flush data.
34 *
35 * With more than 8 CPUs they are hashed to the 8 available
36 * vectors. The limited global vector space forces us to this right now.
37 * In future when interrupts are split into per CPU domains this could be
38 * fixed, at the cost of triggering multiple IPIs in some cases.
39 */
40
41union smp_flush_state {
42 struct {
43 struct mm_struct *flush_mm;
44 unsigned long flush_va;
45 raw_spinlock_t tlbstate_lock;
46 DECLARE_BITMAP(flush_cpumask, NR_CPUS);
47 };
48 char pad[INTERNODE_CACHE_BYTES];
49} ____cacheline_internodealigned_in_smp;
50
51/* State is put into the per CPU data section, but padded
52 to a full cache line because other CPUs can access it and we don't
53 want false sharing in the per cpu data segment. */
54static union smp_flush_state flush_state[NUM_INVALIDATE_TLB_VECTORS];
55
56static DEFINE_PER_CPU_READ_MOSTLY(int, tlb_vector_offset);
57
58/*
59 * We cannot call mmdrop() because we are in interrupt context,
60 * instead update mm->cpu_vm_mask.
61 */
62void leave_mm(int cpu)
63{
64 struct mm_struct *active_mm = this_cpu_read(cpu_tlbstate.active_mm);
65 if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
66 BUG();
67 if (cpumask_test_cpu(cpu, mm_cpumask(active_mm))) {
68 cpumask_clear_cpu(cpu, mm_cpumask(active_mm));
69 load_cr3(swapper_pg_dir);
70 }
71}
72EXPORT_SYMBOL_GPL(leave_mm);
73
74/*
75 *
76 * The flush IPI assumes that a thread switch happens in this order:
77 * [cpu0: the cpu that switches]
78 * 1) switch_mm() either 1a) or 1b)
79 * 1a) thread switch to a different mm
80 * 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
81 * Stop ipi delivery for the old mm. This is not synchronized with
82 * the other cpus, but smp_invalidate_interrupt ignore flush ipis
83 * for the wrong mm, and in the worst case we perform a superfluous
84 * tlb flush.
85 * 1a2) set cpu mmu_state to TLBSTATE_OK
86 * Now the smp_invalidate_interrupt won't call leave_mm if cpu0
87 * was in lazy tlb mode.
88 * 1a3) update cpu active_mm
89 * Now cpu0 accepts tlb flushes for the new mm.
90 * 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
91 * Now the other cpus will send tlb flush ipis.
92 * 1a4) change cr3.
93 * 1b) thread switch without mm change
94 * cpu active_mm is correct, cpu0 already handles
95 * flush ipis.
96 * 1b1) set cpu mmu_state to TLBSTATE_OK
97 * 1b2) test_and_set the cpu bit in cpu_vm_mask.
98 * Atomically set the bit [other cpus will start sending flush ipis],
99 * and test the bit.
100 * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
101 * 2) switch %%esp, ie current
102 *
103 * The interrupt must handle 2 special cases:
104 * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
105 * - the cpu performs speculative tlb reads, i.e. even if the cpu only
106 * runs in kernel space, the cpu could load tlb entries for user space
107 * pages.
108 *
109 * The good news is that cpu mmu_state is local to each cpu, no
110 * write/read ordering problems.
111 */
112
113/*
114 * TLB flush IPI:
115 *
116 * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
117 * 2) Leave the mm if we are in the lazy tlb mode.
118 *
119 * Interrupts are disabled.
120 */
121
122/*
123 * FIXME: use of asmlinkage is not consistent. On x86_64 it's noop
124 * but still used for documentation purpose but the usage is slightly
125 * inconsistent. On x86_32, asmlinkage is regparm(0) but interrupt
126 * entry calls in with the first parameter in %eax. Maybe define
127 * intrlinkage?
128 */
129#ifdef CONFIG_X86_64
130asmlinkage
131#endif
132void smp_invalidate_interrupt(struct pt_regs *regs)
133{
134 unsigned int cpu;
135 unsigned int sender;
136 union smp_flush_state *f;
137
138 cpu = smp_processor_id();
139 /*
140 * orig_rax contains the negated interrupt vector.
141 * Use that to determine where the sender put the data.
142 */
143 sender = ~regs->orig_ax - INVALIDATE_TLB_VECTOR_START;
144 f = &flush_state[sender];
145
146 if (!cpumask_test_cpu(cpu, to_cpumask(f->flush_cpumask)))
147 goto out;
148 /*
149 * This was a BUG() but until someone can quote me the
150 * line from the intel manual that guarantees an IPI to
151 * multiple CPUs is retried _only_ on the erroring CPUs
152 * its staying as a return
153 *
154 * BUG();
155 */
156
157 if (f->flush_mm == this_cpu_read(cpu_tlbstate.active_mm)) {
158 if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
159 if (f->flush_va == TLB_FLUSH_ALL)
160 local_flush_tlb();
161 else
162 __flush_tlb_one(f->flush_va);
163 } else
164 leave_mm(cpu);
165 }
166out:
167 ack_APIC_irq();
168 smp_mb__before_clear_bit();
169 cpumask_clear_cpu(cpu, to_cpumask(f->flush_cpumask));
170 smp_mb__after_clear_bit();
171 inc_irq_stat(irq_tlb_count);
172}
173
174static void flush_tlb_others_ipi(const struct cpumask *cpumask,
175 struct mm_struct *mm, unsigned long va)
176{
177 unsigned int sender;
178 union smp_flush_state *f;
179
180 /* Caller has disabled preemption */
181 sender = this_cpu_read(tlb_vector_offset);
182 f = &flush_state[sender];
183
184 if (nr_cpu_ids > NUM_INVALIDATE_TLB_VECTORS)
185 raw_spin_lock(&f->tlbstate_lock);
186
187 f->flush_mm = mm;
188 f->flush_va = va;
189 if (cpumask_andnot(to_cpumask(f->flush_cpumask), cpumask, cpumask_of(smp_processor_id()))) {
190 /*
191 * We have to send the IPI only to
192 * CPUs affected.
193 */
194 apic->send_IPI_mask(to_cpumask(f->flush_cpumask),
195 INVALIDATE_TLB_VECTOR_START + sender);
196
197 while (!cpumask_empty(to_cpumask(f->flush_cpumask)))
198 cpu_relax();
199 }
200
201 f->flush_mm = NULL;
202 f->flush_va = 0;
203 if (nr_cpu_ids > NUM_INVALIDATE_TLB_VECTORS)
204 raw_spin_unlock(&f->tlbstate_lock);
205}
206
207void native_flush_tlb_others(const struct cpumask *cpumask,
208 struct mm_struct *mm, unsigned long va)
209{
210 if (is_uv_system()) {
211 unsigned int cpu;
212
213 cpu = smp_processor_id();
214 cpumask = uv_flush_tlb_others(cpumask, mm, va, cpu);
215 if (cpumask)
216 flush_tlb_others_ipi(cpumask, mm, va);
217 return;
218 }
219 flush_tlb_others_ipi(cpumask, mm, va);
220}
221
222static void __cpuinit calculate_tlb_offset(void)
223{
224 int cpu, node, nr_node_vecs, idx = 0;
225 /*
226 * we are changing tlb_vector_offset for each CPU in runtime, but this
227 * will not cause inconsistency, as the write is atomic under X86. we
228 * might see more lock contentions in a short time, but after all CPU's
229 * tlb_vector_offset are changed, everything should go normal
230 *
231 * Note: if NUM_INVALIDATE_TLB_VECTORS % nr_online_nodes !=0, we might
232 * waste some vectors.
233 **/
234 if (nr_online_nodes > NUM_INVALIDATE_TLB_VECTORS)
235 nr_node_vecs = 1;
236 else
237 nr_node_vecs = NUM_INVALIDATE_TLB_VECTORS/nr_online_nodes;
238
239 for_each_online_node(node) {
240 int node_offset = (idx % NUM_INVALIDATE_TLB_VECTORS) *
241 nr_node_vecs;
242 int cpu_offset = 0;
243 for_each_cpu(cpu, cpumask_of_node(node)) {
244 per_cpu(tlb_vector_offset, cpu) = node_offset +
245 cpu_offset;
246 cpu_offset++;
247 cpu_offset = cpu_offset % nr_node_vecs;
248 }
249 idx++;
250 }
251}
252
253static int __cpuinit tlb_cpuhp_notify(struct notifier_block *n,
254 unsigned long action, void *hcpu)
255{
256 switch (action & 0xf) {
257 case CPU_ONLINE:
258 case CPU_DEAD:
259 calculate_tlb_offset();
260 }
261 return NOTIFY_OK;
262}
263
264static int __cpuinit init_smp_flush(void)
265{
266 int i;
267
268 for (i = 0; i < ARRAY_SIZE(flush_state); i++)
269 raw_spin_lock_init(&flush_state[i].tlbstate_lock);
270
271 calculate_tlb_offset();
272 hotcpu_notifier(tlb_cpuhp_notify, 0);
273 return 0;
274}
275core_initcall(init_smp_flush);
276
277void flush_tlb_current_task(void)
278{
279 struct mm_struct *mm = current->mm;
280
281 preempt_disable();
282
283 local_flush_tlb();
284 if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
285 flush_tlb_others(mm_cpumask(mm), mm, TLB_FLUSH_ALL);
286 preempt_enable();
287}
288
289void flush_tlb_mm(struct mm_struct *mm)
290{
291 preempt_disable();
292
293 if (current->active_mm == mm) {
294 if (current->mm)
295 local_flush_tlb();
296 else
297 leave_mm(smp_processor_id());
298 }
299 if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
300 flush_tlb_others(mm_cpumask(mm), mm, TLB_FLUSH_ALL);
301
302 preempt_enable();
303}
304
305void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
306{
307 struct mm_struct *mm = vma->vm_mm;
308
309 preempt_disable();
310
311 if (current->active_mm == mm) {
312 if (current->mm)
313 __flush_tlb_one(va);
314 else
315 leave_mm(smp_processor_id());
316 }
317
318 if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
319 flush_tlb_others(mm_cpumask(mm), mm, va);
320
321 preempt_enable();
322}
323
324static void do_flush_tlb_all(void *info)
325{
326 __flush_tlb_all();
327 if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_LAZY)
328 leave_mm(smp_processor_id());
329}
330
331void flush_tlb_all(void)
332{
333 on_each_cpu(do_flush_tlb_all, NULL, 1);
334}