1config IRQCHIP
  2	def_bool y
  3	depends on OF_IRQ
  4
  5config ARM_GIC
  6	bool
  7	select IRQ_DOMAIN
  8	select IRQ_DOMAIN_HIERARCHY
  9	select MULTI_IRQ_HANDLER
 10
 11config ARM_GIC_MAX_NR
 12	int
 13	default 2 if ARCH_REALVIEW
 14	default 1
 15
 16config ARM_GIC_V2M
 17	bool
 18	depends on ARM_GIC
 19	depends on PCI && PCI_MSI
 20	select PCI_MSI_IRQ_DOMAIN
 21
 22config GIC_NON_BANKED
 23	bool
 24
 25config ARM_GIC_V3
 26	bool
 27	select IRQ_DOMAIN
 28	select MULTI_IRQ_HANDLER
 29	select IRQ_DOMAIN_HIERARCHY
 30
 31config ARM_GIC_V3_ITS
 32	bool
 33	select PCI_MSI_IRQ_DOMAIN
 34
 35config ARM_NVIC
 36	bool
 37	select IRQ_DOMAIN
 38	select IRQ_DOMAIN_HIERARCHY
 39	select GENERIC_IRQ_CHIP
 40
 41config ARM_VIC
 42	bool
 43	select IRQ_DOMAIN
 44	select MULTI_IRQ_HANDLER
 45
 46config ARM_VIC_NR
 47	int
 48	default 4 if ARCH_S5PV210
 49	default 2
 50	depends on ARM_VIC
 51	help
 52	  The maximum number of VICs available in the system, for
 53	  power management.
 54
 55config ARMADA_370_XP_IRQ
 56	bool
 57	select GENERIC_IRQ_CHIP
 58	select PCI_MSI_IRQ_DOMAIN if PCI_MSI
 59
 60config ALPINE_MSI
 61	bool
 62	depends on PCI && PCI_MSI
 63	select GENERIC_IRQ_CHIP
 64	select PCI_MSI_IRQ_DOMAIN
 65
 66config ATMEL_AIC_IRQ
 67	bool
 68	select GENERIC_IRQ_CHIP
 69	select IRQ_DOMAIN
 70	select MULTI_IRQ_HANDLER
 71	select SPARSE_IRQ
 72
 73config ATMEL_AIC5_IRQ
 74	bool
 75	select GENERIC_IRQ_CHIP
 76	select IRQ_DOMAIN
 77	select MULTI_IRQ_HANDLER
 78	select SPARSE_IRQ
 79
 80config I8259
 81	bool
 82	select IRQ_DOMAIN
 83
 84config BCM6345_L1_IRQ
 85	bool
 86	select GENERIC_IRQ_CHIP
 87	select IRQ_DOMAIN
 88
 89config BCM7038_L1_IRQ
 90	bool
 91	select GENERIC_IRQ_CHIP
 92	select IRQ_DOMAIN
 93
 94config BCM7120_L2_IRQ
 95	bool
 96	select GENERIC_IRQ_CHIP
 97	select IRQ_DOMAIN
 98
 99config BRCMSTB_L2_IRQ
100	bool
101	select GENERIC_IRQ_CHIP
102	select IRQ_DOMAIN
103
104config DW_APB_ICTL
105	bool
106	select GENERIC_IRQ_CHIP
107	select IRQ_DOMAIN
108
109config HISILICON_IRQ_MBIGEN
110	bool
111	select ARM_GIC_V3
112	select ARM_GIC_V3_ITS
113	select GENERIC_MSI_IRQ_DOMAIN
114
115config IMGPDC_IRQ
116	bool
117	select GENERIC_IRQ_CHIP
118	select IRQ_DOMAIN
119
120config IRQ_MIPS_CPU
121	bool
122	select GENERIC_IRQ_CHIP
123	select IRQ_DOMAIN
124
125config CLPS711X_IRQCHIP
126	bool
127	depends on ARCH_CLPS711X
128	select IRQ_DOMAIN
129	select MULTI_IRQ_HANDLER
130	select SPARSE_IRQ
131	default y
132
133config OR1K_PIC
134	bool
135	select IRQ_DOMAIN
136
137config OMAP_IRQCHIP
138	bool
139	select GENERIC_IRQ_CHIP
140	select IRQ_DOMAIN
141
142config ORION_IRQCHIP
143	bool
144	select IRQ_DOMAIN
145	select MULTI_IRQ_HANDLER
146
147config PIC32_EVIC
148	bool
149	select GENERIC_IRQ_CHIP
150	select IRQ_DOMAIN
151
152config RENESAS_INTC_IRQPIN
153	bool
154	select IRQ_DOMAIN
155
156config RENESAS_IRQC
157	bool
158	select GENERIC_IRQ_CHIP
159	select IRQ_DOMAIN
160
161config ST_IRQCHIP
162	bool
163	select REGMAP
164	select MFD_SYSCON
165	help
166	  Enables SysCfg Controlled IRQs on STi based platforms.
167
168config TANGO_IRQ
169	bool
170	select IRQ_DOMAIN
171	select GENERIC_IRQ_CHIP
172
173config TB10X_IRQC
174	bool
175	select IRQ_DOMAIN
176	select GENERIC_IRQ_CHIP
177
178config TS4800_IRQ
179	tristate "TS-4800 IRQ controller"
180	select IRQ_DOMAIN
181	depends on HAS_IOMEM
182	depends on SOC_IMX51 || COMPILE_TEST
183	help
184	  Support for the TS-4800 FPGA IRQ controller
185
186config VERSATILE_FPGA_IRQ
187	bool
188	select IRQ_DOMAIN
189
190config VERSATILE_FPGA_IRQ_NR
191       int
192       default 4
193       depends on VERSATILE_FPGA_IRQ
194
195config XTENSA_MX
196	bool
197	select IRQ_DOMAIN
198
199config IRQ_CROSSBAR
200	bool
201	help
202	  Support for a CROSSBAR ip that precedes the main interrupt controller.
203	  The primary irqchip invokes the crossbar's callback which inturn allocates
204	  a free irq and configures the IP. Thus the peripheral interrupts are
205	  routed to one of the free irqchip interrupt lines.
206
207config KEYSTONE_IRQ
208	tristate "Keystone 2 IRQ controller IP"
209	depends on ARCH_KEYSTONE
210	help
211		Support for Texas Instruments Keystone 2 IRQ controller IP which
212		is part of the Keystone 2 IPC mechanism
213
214config MIPS_GIC
215	bool
216	select GENERIC_IRQ_IPI
217	select IRQ_DOMAIN_HIERARCHY
218	select MIPS_CM
219
220config INGENIC_IRQ
221	bool
222	depends on MACH_INGENIC
223	default y
224
225config RENESAS_H8300H_INTC
226        bool
227	select IRQ_DOMAIN
228
229config RENESAS_H8S_INTC
230        bool
231	select IRQ_DOMAIN
232
233config IMX_GPCV2
234	bool
235	select IRQ_DOMAIN
236	help
237	  Enables the wakeup IRQs for IMX platforms with GPCv2 block
238
239config IRQ_MXS
240	def_bool y if MACH_ASM9260 || ARCH_MXS
241	select IRQ_DOMAIN
242	select STMP_DEVICE
243
244config MVEBU_ODMI
245	bool
246	select GENERIC_MSI_IRQ_DOMAIN