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1config IRQCHIP
2 def_bool y
3 depends on OF_IRQ
4
5config ARM_GIC
6 bool
7 select IRQ_DOMAIN
8 select IRQ_DOMAIN_HIERARCHY
9 select MULTI_IRQ_HANDLER
10
11config ARM_GIC_MAX_NR
12 int
13 default 2 if ARCH_REALVIEW
14 default 1
15
16config ARM_GIC_V2M
17 bool
18 depends on ARM_GIC
19 depends on PCI && PCI_MSI
20 select PCI_MSI_IRQ_DOMAIN
21
22config GIC_NON_BANKED
23 bool
24
25config ARM_GIC_V3
26 bool
27 select IRQ_DOMAIN
28 select MULTI_IRQ_HANDLER
29 select IRQ_DOMAIN_HIERARCHY
30
31config ARM_GIC_V3_ITS
32 bool
33 select PCI_MSI_IRQ_DOMAIN
34
35config ARM_NVIC
36 bool
37 select IRQ_DOMAIN
38 select IRQ_DOMAIN_HIERARCHY
39 select GENERIC_IRQ_CHIP
40
41config ARM_VIC
42 bool
43 select IRQ_DOMAIN
44 select MULTI_IRQ_HANDLER
45
46config ARM_VIC_NR
47 int
48 default 4 if ARCH_S5PV210
49 default 2
50 depends on ARM_VIC
51 help
52 The maximum number of VICs available in the system, for
53 power management.
54
55config ARMADA_370_XP_IRQ
56 bool
57 select GENERIC_IRQ_CHIP
58 select PCI_MSI_IRQ_DOMAIN if PCI_MSI
59
60config ALPINE_MSI
61 bool
62 depends on PCI && PCI_MSI
63 select GENERIC_IRQ_CHIP
64 select PCI_MSI_IRQ_DOMAIN
65
66config ATMEL_AIC_IRQ
67 bool
68 select GENERIC_IRQ_CHIP
69 select IRQ_DOMAIN
70 select MULTI_IRQ_HANDLER
71 select SPARSE_IRQ
72
73config ATMEL_AIC5_IRQ
74 bool
75 select GENERIC_IRQ_CHIP
76 select IRQ_DOMAIN
77 select MULTI_IRQ_HANDLER
78 select SPARSE_IRQ
79
80config I8259
81 bool
82 select IRQ_DOMAIN
83
84config BCM6345_L1_IRQ
85 bool
86 select GENERIC_IRQ_CHIP
87 select IRQ_DOMAIN
88
89config BCM7038_L1_IRQ
90 bool
91 select GENERIC_IRQ_CHIP
92 select IRQ_DOMAIN
93
94config BCM7120_L2_IRQ
95 bool
96 select GENERIC_IRQ_CHIP
97 select IRQ_DOMAIN
98
99config BRCMSTB_L2_IRQ
100 bool
101 select GENERIC_IRQ_CHIP
102 select IRQ_DOMAIN
103
104config DW_APB_ICTL
105 bool
106 select GENERIC_IRQ_CHIP
107 select IRQ_DOMAIN
108
109config HISILICON_IRQ_MBIGEN
110 bool
111 select ARM_GIC_V3
112 select ARM_GIC_V3_ITS
113 select GENERIC_MSI_IRQ_DOMAIN
114
115config IMGPDC_IRQ
116 bool
117 select GENERIC_IRQ_CHIP
118 select IRQ_DOMAIN
119
120config IRQ_MIPS_CPU
121 bool
122 select GENERIC_IRQ_CHIP
123 select IRQ_DOMAIN
124
125config CLPS711X_IRQCHIP
126 bool
127 depends on ARCH_CLPS711X
128 select IRQ_DOMAIN
129 select MULTI_IRQ_HANDLER
130 select SPARSE_IRQ
131 default y
132
133config OR1K_PIC
134 bool
135 select IRQ_DOMAIN
136
137config OMAP_IRQCHIP
138 bool
139 select GENERIC_IRQ_CHIP
140 select IRQ_DOMAIN
141
142config ORION_IRQCHIP
143 bool
144 select IRQ_DOMAIN
145 select MULTI_IRQ_HANDLER
146
147config PIC32_EVIC
148 bool
149 select GENERIC_IRQ_CHIP
150 select IRQ_DOMAIN
151
152config RENESAS_INTC_IRQPIN
153 bool
154 select IRQ_DOMAIN
155
156config RENESAS_IRQC
157 bool
158 select GENERIC_IRQ_CHIP
159 select IRQ_DOMAIN
160
161config ST_IRQCHIP
162 bool
163 select REGMAP
164 select MFD_SYSCON
165 help
166 Enables SysCfg Controlled IRQs on STi based platforms.
167
168config TANGO_IRQ
169 bool
170 select IRQ_DOMAIN
171 select GENERIC_IRQ_CHIP
172
173config TB10X_IRQC
174 bool
175 select IRQ_DOMAIN
176 select GENERIC_IRQ_CHIP
177
178config TS4800_IRQ
179 tristate "TS-4800 IRQ controller"
180 select IRQ_DOMAIN
181 depends on HAS_IOMEM
182 depends on SOC_IMX51 || COMPILE_TEST
183 help
184 Support for the TS-4800 FPGA IRQ controller
185
186config VERSATILE_FPGA_IRQ
187 bool
188 select IRQ_DOMAIN
189
190config VERSATILE_FPGA_IRQ_NR
191 int
192 default 4
193 depends on VERSATILE_FPGA_IRQ
194
195config XTENSA_MX
196 bool
197 select IRQ_DOMAIN
198
199config IRQ_CROSSBAR
200 bool
201 help
202 Support for a CROSSBAR ip that precedes the main interrupt controller.
203 The primary irqchip invokes the crossbar's callback which inturn allocates
204 a free irq and configures the IP. Thus the peripheral interrupts are
205 routed to one of the free irqchip interrupt lines.
206
207config KEYSTONE_IRQ
208 tristate "Keystone 2 IRQ controller IP"
209 depends on ARCH_KEYSTONE
210 help
211 Support for Texas Instruments Keystone 2 IRQ controller IP which
212 is part of the Keystone 2 IPC mechanism
213
214config MIPS_GIC
215 bool
216 select GENERIC_IRQ_IPI
217 select IRQ_DOMAIN_HIERARCHY
218 select MIPS_CM
219
220config INGENIC_IRQ
221 bool
222 depends on MACH_INGENIC
223 default y
224
225config RENESAS_H8300H_INTC
226 bool
227 select IRQ_DOMAIN
228
229config RENESAS_H8S_INTC
230 bool
231 select IRQ_DOMAIN
232
233config IMX_GPCV2
234 bool
235 select IRQ_DOMAIN
236 help
237 Enables the wakeup IRQs for IMX platforms with GPCv2 block
238
239config IRQ_MXS
240 def_bool y if MACH_ASM9260 || ARCH_MXS
241 select IRQ_DOMAIN
242 select STMP_DEVICE
243
244config MVEBU_ODMI
245 bool
246 select GENERIC_MSI_IRQ_DOMAIN
1# SPDX-License-Identifier: GPL-2.0-only
2menu "IRQ chip support"
3
4config IRQCHIP
5 def_bool y
6 depends on (OF_IRQ || ACPI_GENERIC_GSI)
7
8config ARM_GIC
9 bool
10 select IRQ_DOMAIN_HIERARCHY
11 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
12
13config ARM_GIC_PM
14 bool
15 depends on PM
16 select ARM_GIC
17
18config ARM_GIC_MAX_NR
19 int
20 depends on ARM_GIC
21 default 2 if ARCH_REALVIEW
22 default 1
23
24config ARM_GIC_V2M
25 bool
26 depends on PCI
27 select ARM_GIC
28 select PCI_MSI
29
30config GIC_NON_BANKED
31 bool
32
33config ARM_GIC_V3
34 bool
35 select IRQ_DOMAIN_HIERARCHY
36 select PARTITION_PERCPU
37 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
38
39config ARM_GIC_V3_ITS
40 bool
41 select GENERIC_MSI_IRQ
42 default ARM_GIC_V3
43
44config ARM_GIC_V3_ITS_PCI
45 bool
46 depends on ARM_GIC_V3_ITS
47 depends on PCI
48 depends on PCI_MSI
49 default ARM_GIC_V3_ITS
50
51config ARM_GIC_V3_ITS_FSL_MC
52 bool
53 depends on ARM_GIC_V3_ITS
54 depends on FSL_MC_BUS
55 default ARM_GIC_V3_ITS
56
57config ARM_NVIC
58 bool
59 select IRQ_DOMAIN_HIERARCHY
60 select GENERIC_IRQ_CHIP
61
62config ARM_VIC
63 bool
64 select IRQ_DOMAIN
65
66config ARM_VIC_NR
67 int
68 default 4 if ARCH_S5PV210
69 default 2
70 depends on ARM_VIC
71 help
72 The maximum number of VICs available in the system, for
73 power management.
74
75config ARMADA_370_XP_IRQ
76 bool
77 select GENERIC_IRQ_CHIP
78 select PCI_MSI if PCI
79 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
80
81config ALPINE_MSI
82 bool
83 depends on PCI
84 select PCI_MSI
85 select GENERIC_IRQ_CHIP
86
87config AL_FIC
88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
89 depends on OF
90 select GENERIC_IRQ_CHIP
91 select IRQ_DOMAIN
92 help
93 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
94
95config ATMEL_AIC_IRQ
96 bool
97 select GENERIC_IRQ_CHIP
98 select IRQ_DOMAIN
99 select SPARSE_IRQ
100
101config ATMEL_AIC5_IRQ
102 bool
103 select GENERIC_IRQ_CHIP
104 select IRQ_DOMAIN
105 select SPARSE_IRQ
106
107config I8259
108 bool
109 select IRQ_DOMAIN
110
111config BCM6345_L1_IRQ
112 bool
113 select GENERIC_IRQ_CHIP
114 select IRQ_DOMAIN
115 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
116
117config BCM7038_L1_IRQ
118 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
119 depends on ARCH_BRCMSTB || BMIPS_GENERIC
120 default ARCH_BRCMSTB || BMIPS_GENERIC
121 select GENERIC_IRQ_CHIP
122 select IRQ_DOMAIN
123 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
124
125config BCM7120_L2_IRQ
126 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
127 depends on ARCH_BRCMSTB || BMIPS_GENERIC
128 default ARCH_BRCMSTB || BMIPS_GENERIC
129 select GENERIC_IRQ_CHIP
130 select IRQ_DOMAIN
131
132config BRCMSTB_L2_IRQ
133 tristate "Broadcom STB generic L2 interrupt controller driver"
134 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
135 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
136 select GENERIC_IRQ_CHIP
137 select IRQ_DOMAIN
138
139config DAVINCI_AINTC
140 bool
141 select GENERIC_IRQ_CHIP
142 select IRQ_DOMAIN
143
144config DAVINCI_CP_INTC
145 bool
146 select GENERIC_IRQ_CHIP
147 select IRQ_DOMAIN
148
149config DW_APB_ICTL
150 bool
151 select GENERIC_IRQ_CHIP
152 select IRQ_DOMAIN_HIERARCHY
153
154config FARADAY_FTINTC010
155 bool
156 select IRQ_DOMAIN
157 select SPARSE_IRQ
158
159config HISILICON_IRQ_MBIGEN
160 bool
161 select ARM_GIC_V3
162 select ARM_GIC_V3_ITS
163
164config IMGPDC_IRQ
165 bool
166 select GENERIC_IRQ_CHIP
167 select IRQ_DOMAIN
168
169config IXP4XX_IRQ
170 bool
171 select IRQ_DOMAIN
172 select SPARSE_IRQ
173
174config MADERA_IRQ
175 tristate
176
177config IRQ_MIPS_CPU
178 bool
179 select GENERIC_IRQ_CHIP
180 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING
181 select IRQ_DOMAIN
182 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
183
184config CLPS711X_IRQCHIP
185 bool
186 depends on ARCH_CLPS711X
187 select IRQ_DOMAIN
188 select SPARSE_IRQ
189 default y
190
191config OMPIC
192 bool
193
194config OR1K_PIC
195 bool
196 select IRQ_DOMAIN
197
198config OMAP_IRQCHIP
199 bool
200 select GENERIC_IRQ_CHIP
201 select IRQ_DOMAIN
202
203config ORION_IRQCHIP
204 bool
205 select IRQ_DOMAIN
206
207config PIC32_EVIC
208 bool
209 select GENERIC_IRQ_CHIP
210 select IRQ_DOMAIN
211
212config JCORE_AIC
213 bool "J-Core integrated AIC" if COMPILE_TEST
214 depends on OF
215 select IRQ_DOMAIN
216 help
217 Support for the J-Core integrated AIC.
218
219config RDA_INTC
220 bool
221 select IRQ_DOMAIN
222
223config RENESAS_INTC_IRQPIN
224 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
225 select IRQ_DOMAIN
226 help
227 Enable support for the Renesas Interrupt Controller for external
228 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
229
230config RENESAS_IRQC
231 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
232 select GENERIC_IRQ_CHIP
233 select IRQ_DOMAIN
234 help
235 Enable support for the Renesas Interrupt Controller for external
236 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
237
238config RENESAS_RZA1_IRQC
239 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
240 select IRQ_DOMAIN_HIERARCHY
241 help
242 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
243 to 8 external interrupts with configurable sense select.
244
245config RENESAS_RZG2L_IRQC
246 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST
247 select GENERIC_IRQ_CHIP
248 select IRQ_DOMAIN_HIERARCHY
249 help
250 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller
251 for external devices.
252
253config SL28CPLD_INTC
254 bool "Kontron sl28cpld IRQ controller"
255 depends on MFD_SL28CPLD=y || COMPILE_TEST
256 select REGMAP_IRQ
257 help
258 Interrupt controller driver for the board management controller
259 found on the Kontron sl28 CPLD.
260
261config ST_IRQCHIP
262 bool
263 select REGMAP
264 select MFD_SYSCON
265 help
266 Enables SysCfg Controlled IRQs on STi based platforms.
267
268config SUN4I_INTC
269 bool
270
271config SUN6I_R_INTC
272 bool
273 select IRQ_DOMAIN_HIERARCHY
274 select IRQ_FASTEOI_HIERARCHY_HANDLERS
275
276config SUNXI_NMI_INTC
277 bool
278 select GENERIC_IRQ_CHIP
279
280config TB10X_IRQC
281 bool
282 select IRQ_DOMAIN
283 select GENERIC_IRQ_CHIP
284
285config TS4800_IRQ
286 tristate "TS-4800 IRQ controller"
287 select IRQ_DOMAIN
288 depends on HAS_IOMEM
289 depends on SOC_IMX51 || COMPILE_TEST
290 help
291 Support for the TS-4800 FPGA IRQ controller
292
293config VERSATILE_FPGA_IRQ
294 bool
295 select IRQ_DOMAIN
296
297config VERSATILE_FPGA_IRQ_NR
298 int
299 default 4
300 depends on VERSATILE_FPGA_IRQ
301
302config XTENSA_MX
303 bool
304 select IRQ_DOMAIN
305 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
306
307config XILINX_INTC
308 bool "Xilinx Interrupt Controller IP"
309 depends on OF_ADDRESS
310 select IRQ_DOMAIN
311 help
312 Support for the Xilinx Interrupt Controller IP core.
313 This is used as a primary controller with MicroBlaze and can also
314 be used as a secondary chained controller on other platforms.
315
316config IRQ_CROSSBAR
317 bool
318 help
319 Support for a CROSSBAR ip that precedes the main interrupt controller.
320 The primary irqchip invokes the crossbar's callback which inturn allocates
321 a free irq and configures the IP. Thus the peripheral interrupts are
322 routed to one of the free irqchip interrupt lines.
323
324config KEYSTONE_IRQ
325 tristate "Keystone 2 IRQ controller IP"
326 depends on ARCH_KEYSTONE
327 help
328 Support for Texas Instruments Keystone 2 IRQ controller IP which
329 is part of the Keystone 2 IPC mechanism
330
331config MIPS_GIC
332 bool
333 select GENERIC_IRQ_IPI if SMP
334 select IRQ_DOMAIN_HIERARCHY
335 select MIPS_CM
336
337config INGENIC_IRQ
338 bool
339 depends on MACH_INGENIC
340 default y
341
342config INGENIC_TCU_IRQ
343 bool "Ingenic JZ47xx TCU interrupt controller"
344 default MACH_INGENIC
345 depends on MIPS || COMPILE_TEST
346 select MFD_SYSCON
347 select GENERIC_IRQ_CHIP
348 help
349 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
350 JZ47xx SoCs.
351
352 If unsure, say N.
353
354config IMX_GPCV2
355 bool
356 select IRQ_DOMAIN
357 help
358 Enables the wakeup IRQs for IMX platforms with GPCv2 block
359
360config IRQ_MXS
361 def_bool y if MACH_ASM9260 || ARCH_MXS
362 select IRQ_DOMAIN
363 select STMP_DEVICE
364
365config MSCC_OCELOT_IRQ
366 bool
367 select IRQ_DOMAIN
368 select GENERIC_IRQ_CHIP
369
370config MVEBU_GICP
371 bool
372
373config MVEBU_ICU
374 bool
375
376config MVEBU_ODMI
377 bool
378 select GENERIC_MSI_IRQ
379
380config MVEBU_PIC
381 bool
382
383config MVEBU_SEI
384 bool
385
386config LS_EXTIRQ
387 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
388 select MFD_SYSCON
389
390config LS_SCFG_MSI
391 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
392 depends on PCI && PCI_MSI
393
394config PARTITION_PERCPU
395 bool
396
397config STM32_EXTI
398 bool
399 select IRQ_DOMAIN
400 select GENERIC_IRQ_CHIP
401
402config QCOM_IRQ_COMBINER
403 bool "QCOM IRQ combiner support"
404 depends on ARCH_QCOM && ACPI
405 select IRQ_DOMAIN_HIERARCHY
406 help
407 Say yes here to add support for the IRQ combiner devices embedded
408 in Qualcomm Technologies chips.
409
410config IRQ_UNIPHIER_AIDET
411 bool "UniPhier AIDET support" if COMPILE_TEST
412 depends on ARCH_UNIPHIER || COMPILE_TEST
413 default ARCH_UNIPHIER
414 select IRQ_DOMAIN_HIERARCHY
415 help
416 Support for the UniPhier AIDET (ARM Interrupt Detector).
417
418config MESON_IRQ_GPIO
419 tristate "Meson GPIO Interrupt Multiplexer"
420 depends on ARCH_MESON || COMPILE_TEST
421 default ARCH_MESON
422 select IRQ_DOMAIN_HIERARCHY
423 help
424 Support Meson SoC Family GPIO Interrupt Multiplexer
425
426config GOLDFISH_PIC
427 bool "Goldfish programmable interrupt controller"
428 depends on MIPS && (GOLDFISH || COMPILE_TEST)
429 select GENERIC_IRQ_CHIP
430 select IRQ_DOMAIN
431 help
432 Say yes here to enable Goldfish interrupt controller driver used
433 for Goldfish based virtual platforms.
434
435config QCOM_PDC
436 tristate "QCOM PDC"
437 depends on ARCH_QCOM
438 select IRQ_DOMAIN_HIERARCHY
439 help
440 Power Domain Controller driver to manage and configure wakeup
441 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
442
443config QCOM_MPM
444 tristate "QCOM MPM"
445 depends on ARCH_QCOM
446 depends on MAILBOX
447 select IRQ_DOMAIN_HIERARCHY
448 help
449 MSM Power Manager driver to manage and configure wakeup
450 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
451
452config CSKY_MPINTC
453 bool
454 depends on CSKY
455 help
456 Say yes here to enable C-SKY SMP interrupt controller driver used
457 for C-SKY SMP system.
458 In fact it's not mmio map in hardware and it uses ld/st to visit the
459 controller's register inside CPU.
460
461config CSKY_APB_INTC
462 bool "C-SKY APB Interrupt Controller"
463 depends on CSKY
464 help
465 Say yes here to enable C-SKY APB interrupt controller driver used
466 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
467 the controller's register.
468
469config IMX_IRQSTEER
470 bool "i.MX IRQSTEER support"
471 depends on ARCH_MXC || COMPILE_TEST
472 default ARCH_MXC
473 select IRQ_DOMAIN
474 help
475 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
476
477config IMX_INTMUX
478 bool "i.MX INTMUX support" if COMPILE_TEST
479 default y if ARCH_MXC
480 select IRQ_DOMAIN
481 help
482 Support for the i.MX INTMUX interrupt multiplexer.
483
484config IMX_MU_MSI
485 tristate "i.MX MU used as MSI controller"
486 depends on OF && HAS_IOMEM
487 depends on ARCH_MXC || COMPILE_TEST
488 default m if ARCH_MXC
489 select IRQ_DOMAIN
490 select IRQ_DOMAIN_HIERARCHY
491 select GENERIC_MSI_IRQ
492 help
493 Provide a driver for the i.MX Messaging Unit block used as a
494 CPU-to-CPU MSI controller. This requires a specially crafted DT
495 to make use of this driver.
496
497 If unsure, say N
498
499config LS1X_IRQ
500 bool "Loongson-1 Interrupt Controller"
501 depends on MACH_LOONGSON32
502 default y
503 select IRQ_DOMAIN
504 select GENERIC_IRQ_CHIP
505 help
506 Support for the Loongson-1 platform Interrupt Controller.
507
508config TI_SCI_INTR_IRQCHIP
509 bool
510 depends on TI_SCI_PROTOCOL
511 select IRQ_DOMAIN_HIERARCHY
512 help
513 This enables the irqchip driver support for K3 Interrupt router
514 over TI System Control Interface available on some new TI's SoCs.
515 If you wish to use interrupt router irq resources managed by the
516 TI System Controller, say Y here. Otherwise, say N.
517
518config TI_SCI_INTA_IRQCHIP
519 bool
520 depends on TI_SCI_PROTOCOL
521 select IRQ_DOMAIN_HIERARCHY
522 select TI_SCI_INTA_MSI_DOMAIN
523 help
524 This enables the irqchip driver support for K3 Interrupt aggregator
525 over TI System Control Interface available on some new TI's SoCs.
526 If you wish to use interrupt aggregator irq resources managed by the
527 TI System Controller, say Y here. Otherwise, say N.
528
529config TI_PRUSS_INTC
530 tristate
531 depends on TI_PRUSS
532 default TI_PRUSS
533 select IRQ_DOMAIN
534 help
535 This enables support for the PRU-ICSS Local Interrupt Controller
536 present within a PRU-ICSS subsystem present on various TI SoCs.
537 The PRUSS INTC enables various interrupts to be routed to multiple
538 different processors within the SoC.
539
540config RISCV_INTC
541 bool
542 depends on RISCV
543
544config SIFIVE_PLIC
545 bool
546 depends on RISCV
547 select IRQ_DOMAIN_HIERARCHY
548 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
549
550config EXYNOS_IRQ_COMBINER
551 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
552 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
553 help
554 Say yes here to add support for the IRQ combiner devices embedded
555 in Samsung Exynos chips.
556
557config IRQ_LOONGARCH_CPU
558 bool
559 select GENERIC_IRQ_CHIP
560 select IRQ_DOMAIN
561 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
562 select LOONGSON_HTVEC
563 select LOONGSON_LIOINTC
564 select LOONGSON_EIOINTC
565 select LOONGSON_PCH_PIC
566 select LOONGSON_PCH_MSI
567 select LOONGSON_PCH_LPC
568 help
569 Support for the LoongArch CPU Interrupt Controller. For details of
570 irq chip hierarchy on LoongArch platforms please read the document
571 Documentation/loongarch/irq-chip-model.rst.
572
573config LOONGSON_LIOINTC
574 bool "Loongson Local I/O Interrupt Controller"
575 depends on MACH_LOONGSON64
576 default y
577 select IRQ_DOMAIN
578 select GENERIC_IRQ_CHIP
579 help
580 Support for the Loongson Local I/O Interrupt Controller.
581
582config LOONGSON_EIOINTC
583 bool "Loongson Extend I/O Interrupt Controller"
584 depends on LOONGARCH
585 depends on MACH_LOONGSON64
586 default MACH_LOONGSON64
587 select IRQ_DOMAIN_HIERARCHY
588 select GENERIC_IRQ_CHIP
589 help
590 Support for the Loongson3 Extend I/O Interrupt Vector Controller.
591
592config LOONGSON_HTPIC
593 bool "Loongson3 HyperTransport PIC Controller"
594 depends on MACH_LOONGSON64 && MIPS
595 default y
596 select IRQ_DOMAIN
597 select GENERIC_IRQ_CHIP
598 help
599 Support for the Loongson-3 HyperTransport PIC Controller.
600
601config LOONGSON_HTVEC
602 bool "Loongson HyperTransport Interrupt Vector Controller"
603 depends on MACH_LOONGSON64
604 default MACH_LOONGSON64
605 select IRQ_DOMAIN_HIERARCHY
606 help
607 Support for the Loongson HyperTransport Interrupt Vector Controller.
608
609config LOONGSON_PCH_PIC
610 bool "Loongson PCH PIC Controller"
611 depends on MACH_LOONGSON64
612 default MACH_LOONGSON64
613 select IRQ_DOMAIN_HIERARCHY
614 select IRQ_FASTEOI_HIERARCHY_HANDLERS
615 help
616 Support for the Loongson PCH PIC Controller.
617
618config LOONGSON_PCH_MSI
619 bool "Loongson PCH MSI Controller"
620 depends on MACH_LOONGSON64
621 depends on PCI
622 default MACH_LOONGSON64
623 select IRQ_DOMAIN_HIERARCHY
624 select PCI_MSI
625 help
626 Support for the Loongson PCH MSI Controller.
627
628config LOONGSON_PCH_LPC
629 bool "Loongson PCH LPC Controller"
630 depends on LOONGARCH
631 depends on MACH_LOONGSON64
632 default MACH_LOONGSON64
633 select IRQ_DOMAIN_HIERARCHY
634 help
635 Support for the Loongson PCH LPC Controller.
636
637config MST_IRQ
638 bool "MStar Interrupt Controller"
639 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
640 default ARCH_MEDIATEK
641 select IRQ_DOMAIN
642 select IRQ_DOMAIN_HIERARCHY
643 help
644 Support MStar Interrupt Controller.
645
646config WPCM450_AIC
647 bool "Nuvoton WPCM450 Advanced Interrupt Controller"
648 depends on ARCH_WPCM450
649 help
650 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
651
652config IRQ_IDT3243X
653 bool
654 select GENERIC_IRQ_CHIP
655 select IRQ_DOMAIN
656
657config APPLE_AIC
658 bool "Apple Interrupt Controller (AIC)"
659 depends on ARM64
660 depends on ARCH_APPLE || COMPILE_TEST
661 help
662 Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
663 such as the M1.
664
665config MCHP_EIC
666 bool "Microchip External Interrupt Controller"
667 depends on ARCH_AT91 || COMPILE_TEST
668 select IRQ_DOMAIN
669 select IRQ_DOMAIN_HIERARCHY
670 help
671 Support for Microchip External Interrupt Controller.
672
673config SUNPLUS_SP7021_INTC
674 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST
675 default SOC_SP7021
676 help
677 Support for the Sunplus SP7021 Interrupt Controller IP core.
678 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
679 chained controller, routing all interrupt source in P-Chip to
680 the primary controller on C-Chip.
681
682endmenu