1config IRQCHIP
  2	def_bool y
  3	depends on OF_IRQ
  4
  5config ARM_GIC
  6	bool
  7	select IRQ_DOMAIN
  8	select IRQ_DOMAIN_HIERARCHY
  9	select MULTI_IRQ_HANDLER
 10
 11config ARM_GIC_PM
 12	bool
 13	depends on PM
 14	select ARM_GIC
 15	select PM_CLK
 16
 17config ARM_GIC_MAX_NR
 18	int
 19	default 2 if ARCH_REALVIEW
 20	default 1
 21
 22config ARM_GIC_V2M
 23	bool
 24	depends on PCI
 25	select ARM_GIC
 26	select PCI_MSI
 27
 28config GIC_NON_BANKED
 29	bool
 30
 31config ARM_GIC_V3
 32	bool
 33	select IRQ_DOMAIN
 34	select MULTI_IRQ_HANDLER
 35	select IRQ_DOMAIN_HIERARCHY
 36	select PARTITION_PERCPU
 37
 38config ARM_GIC_V3_ITS
 39	bool
 40	depends on PCI
 41	depends on PCI_MSI
 42	select ACPI_IORT if ACPI
 43
 44config ARM_NVIC
 45	bool
 46	select IRQ_DOMAIN
 47	select IRQ_DOMAIN_HIERARCHY
 48	select GENERIC_IRQ_CHIP
 49
 50config ARM_VIC
 51	bool
 52	select IRQ_DOMAIN
 53	select MULTI_IRQ_HANDLER
 54
 55config ARM_VIC_NR
 56	int
 57	default 4 if ARCH_S5PV210
 58	default 2
 59	depends on ARM_VIC
 60	help
 61	  The maximum number of VICs available in the system, for
 62	  power management.
 63
 64config ARMADA_370_XP_IRQ
 65	bool
 66	select GENERIC_IRQ_CHIP
 67	select PCI_MSI if PCI
 68
 69config ALPINE_MSI
 70	bool
 71	depends on PCI
 72	select PCI_MSI
 73	select GENERIC_IRQ_CHIP
 74
 75config ATMEL_AIC_IRQ
 76	bool
 77	select GENERIC_IRQ_CHIP
 78	select IRQ_DOMAIN
 79	select MULTI_IRQ_HANDLER
 80	select SPARSE_IRQ
 81
 82config ATMEL_AIC5_IRQ
 83	bool
 84	select GENERIC_IRQ_CHIP
 85	select IRQ_DOMAIN
 86	select MULTI_IRQ_HANDLER
 87	select SPARSE_IRQ
 88
 89config I8259
 90	bool
 91	select IRQ_DOMAIN
 92
 93config BCM6345_L1_IRQ
 94	bool
 95	select GENERIC_IRQ_CHIP
 96	select IRQ_DOMAIN
 97
 98config BCM7038_L1_IRQ
 99	bool
100	select GENERIC_IRQ_CHIP
101	select IRQ_DOMAIN
102
103config BCM7120_L2_IRQ
104	bool
105	select GENERIC_IRQ_CHIP
106	select IRQ_DOMAIN
107
108config BRCMSTB_L2_IRQ
109	bool
110	select GENERIC_IRQ_CHIP
111	select IRQ_DOMAIN
112
113config DW_APB_ICTL
114	bool
115	select GENERIC_IRQ_CHIP
116	select IRQ_DOMAIN
117
118config HISILICON_IRQ_MBIGEN
119	bool
120	select ARM_GIC_V3
121	select ARM_GIC_V3_ITS
122
123config IMGPDC_IRQ
124	bool
125	select GENERIC_IRQ_CHIP
126	select IRQ_DOMAIN
127
128config IRQ_MIPS_CPU
129	bool
130	select GENERIC_IRQ_CHIP
131	select IRQ_DOMAIN
132
133config CLPS711X_IRQCHIP
134	bool
135	depends on ARCH_CLPS711X
136	select IRQ_DOMAIN
137	select MULTI_IRQ_HANDLER
138	select SPARSE_IRQ
139	default y
140
141config OR1K_PIC
142	bool
143	select IRQ_DOMAIN
144
145config OMAP_IRQCHIP
146	bool
147	select GENERIC_IRQ_CHIP
148	select IRQ_DOMAIN
149
150config ORION_IRQCHIP
151	bool
152	select IRQ_DOMAIN
153	select MULTI_IRQ_HANDLER
154
155config PIC32_EVIC
156	bool
157	select GENERIC_IRQ_CHIP
158	select IRQ_DOMAIN
159
160config JCORE_AIC
161	bool "J-Core integrated AIC" if COMPILE_TEST
162	depends on OF
163	select IRQ_DOMAIN
164	help
165	  Support for the J-Core integrated AIC.
166
167config RENESAS_INTC_IRQPIN
168	bool
169	select IRQ_DOMAIN
170
171config RENESAS_IRQC
172	bool
173	select GENERIC_IRQ_CHIP
174	select IRQ_DOMAIN
175
176config ST_IRQCHIP
177	bool
178	select REGMAP
179	select MFD_SYSCON
180	help
181	  Enables SysCfg Controlled IRQs on STi based platforms.
182
183config TANGO_IRQ
184	bool
185	select IRQ_DOMAIN
186	select GENERIC_IRQ_CHIP
187
188config TB10X_IRQC
189	bool
190	select IRQ_DOMAIN
191	select GENERIC_IRQ_CHIP
192
193config TS4800_IRQ
194	tristate "TS-4800 IRQ controller"
195	select IRQ_DOMAIN
196	depends on HAS_IOMEM
197	depends on SOC_IMX51 || COMPILE_TEST
198	help
199	  Support for the TS-4800 FPGA IRQ controller
200
201config VERSATILE_FPGA_IRQ
202	bool
203	select IRQ_DOMAIN
204
205config VERSATILE_FPGA_IRQ_NR
206       int
207       default 4
208       depends on VERSATILE_FPGA_IRQ
209
210config XTENSA_MX
211	bool
212	select IRQ_DOMAIN
213
214config XILINX_INTC
215	bool
216	select IRQ_DOMAIN
217
218config IRQ_CROSSBAR
219	bool
220	help
221	  Support for a CROSSBAR ip that precedes the main interrupt controller.
222	  The primary irqchip invokes the crossbar's callback which inturn allocates
223	  a free irq and configures the IP. Thus the peripheral interrupts are
224	  routed to one of the free irqchip interrupt lines.
225
226config KEYSTONE_IRQ
227	tristate "Keystone 2 IRQ controller IP"
228	depends on ARCH_KEYSTONE
229	help
230		Support for Texas Instruments Keystone 2 IRQ controller IP which
231		is part of the Keystone 2 IPC mechanism
232
233config MIPS_GIC
234	bool
235	select GENERIC_IRQ_IPI
236	select IRQ_DOMAIN_HIERARCHY
237	select MIPS_CM
238
239config INGENIC_IRQ
240	bool
241	depends on MACH_INGENIC
242	default y
243
244config RENESAS_H8300H_INTC
245        bool
246	select IRQ_DOMAIN
247
248config RENESAS_H8S_INTC
249        bool
250	select IRQ_DOMAIN
251
252config IMX_GPCV2
253	bool
254	select IRQ_DOMAIN
255	help
256	  Enables the wakeup IRQs for IMX platforms with GPCv2 block
257
258config IRQ_MXS
259	def_bool y if MACH_ASM9260 || ARCH_MXS
260	select IRQ_DOMAIN
261	select STMP_DEVICE
262
263config MVEBU_ODMI
264	bool
265
266config MVEBU_PIC
267	bool
268
269config LS_SCFG_MSI
270	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
271	depends on PCI && PCI_MSI
272
273config PARTITION_PERCPU
274	bool
275
276config EZNPS_GIC
277	bool "NPS400 Global Interrupt Manager (GIM)"
278	depends on ARC || (COMPILE_TEST && !64BIT)
279	select IRQ_DOMAIN
280	help
281	  Support the EZchip NPS400 global interrupt controller
282
283config STM32_EXTI
284	bool
285	select IRQ_DOMAIN