1/*
  2 * Copyright (C) 2013 Red Hat
  3 * Author: Rob Clark <robdclark@gmail.com>
  4 *
  5 * This program is free software; you can redistribute it and/or modify it
  6 * under the terms of the GNU General Public License version 2 as published by
  7 * the Free Software Foundation.
  8 *
  9 * This program is distributed in the hope that it will be useful, but WITHOUT
 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 12 * more details.
 13 *
 14 * You should have received a copy of the GNU General Public License along with
 15 * this program.  If not, see <http://www.gnu.org/licenses/>.
 16 */
 17
 18#ifndef __MSM_DRV_H__
 19#define __MSM_DRV_H__
 20
 21#include <linux/kernel.h>
 22#include <linux/clk.h>
 23#include <linux/cpufreq.h>
 24#include <linux/module.h>
 25#include <linux/component.h>
 26#include <linux/platform_device.h>
 27#include <linux/pm.h>
 28#include <linux/pm_runtime.h>
 29#include <linux/slab.h>
 30#include <linux/list.h>
 31#include <linux/iommu.h>
 32#include <linux/types.h>
 33#include <linux/of_graph.h>
 34#include <linux/of_device.h>
 35#include <asm/sizes.h>
 36
 37#include <drm/drmP.h>
 38#include <drm/drm_atomic.h>
 39#include <drm/drm_atomic_helper.h>
 40#include <drm/drm_crtc_helper.h>
 41#include <drm/drm_plane_helper.h>
 42#include <drm/drm_fb_helper.h>
 43#include <drm/msm_drm.h>
 44#include <drm/drm_gem.h>
 45
 46struct msm_kms;
 47struct msm_gpu;
 48struct msm_mmu;
 49struct msm_rd_state;
 50struct msm_perf_state;
 51struct msm_gem_submit;
 52
 53#define NUM_DOMAINS 2    /* one for KMS, then one per gpu core (?) */
 54
 55struct msm_file_private {
 56	/* currently we don't do anything useful with this.. but when
 57	 * per-context address spaces are supported we'd keep track of
 58	 * the context's page-tables here.
 59	 */
 60	int dummy;
 61};
 62
 63enum msm_mdp_plane_property {
 64	PLANE_PROP_ZPOS,
 65	PLANE_PROP_ALPHA,
 66	PLANE_PROP_PREMULTIPLIED,
 67	PLANE_PROP_MAX_NUM
 68};
 69
 70struct msm_vblank_ctrl {
 71	struct work_struct work;
 72	struct list_head event_list;
 73	spinlock_t lock;
 74};
 75
 76struct msm_drm_private {
 77
 78	struct msm_kms *kms;
 79
 80	/* subordinate devices, if present: */
 81	struct platform_device *gpu_pdev;
 82
 83	/* possibly this should be in the kms component, but it is
 84	 * shared by both mdp4 and mdp5..
 85	 */
 86	struct hdmi *hdmi;
 87
 88	/* eDP is for mdp5 only, but kms has not been created
 89	 * when edp_bind() and edp_init() are called. Here is the only
 90	 * place to keep the edp instance.
 91	 */
 92	struct msm_edp *edp;
 93
 94	/* DSI is shared by mdp4 and mdp5 */
 95	struct msm_dsi *dsi[2];
 96
 97	/* when we have more than one 'msm_gpu' these need to be an array: */
 98	struct msm_gpu *gpu;
 99	struct msm_file_private *lastctx;
100
101	struct drm_fb_helper *fbdev;
102
103	uint32_t next_fence, completed_fence;
104	wait_queue_head_t fence_event;
105
106	struct msm_rd_state *rd;
107	struct msm_perf_state *perf;
108
109	/* list of GEM objects: */
110	struct list_head inactive_list;
111
112	struct workqueue_struct *wq;
113
114	/* callbacks deferred until bo is inactive: */
115	struct list_head fence_cbs;
116
117	/* crtcs pending async atomic updates: */
118	uint32_t pending_crtcs;
119	wait_queue_head_t pending_crtcs_event;
120
121	/* registered MMUs: */
122	unsigned int num_mmus;
123	struct msm_mmu *mmus[NUM_DOMAINS];
124
125	unsigned int num_planes;
126	struct drm_plane *planes[8];
127
128	unsigned int num_crtcs;
129	struct drm_crtc *crtcs[8];
130
131	unsigned int num_encoders;
132	struct drm_encoder *encoders[8];
133
134	unsigned int num_bridges;
135	struct drm_bridge *bridges[8];
136
137	unsigned int num_connectors;
138	struct drm_connector *connectors[8];
139
140	/* Properties */
141	struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
142
143	/* VRAM carveout, used when no IOMMU: */
144	struct {
145		unsigned long size;
146		dma_addr_t paddr;
147		/* NOTE: mm managed at the page level, size is in # of pages
148		 * and position mm_node->start is in # of pages:
149		 */
150		struct drm_mm mm;
151	} vram;
152
153	struct msm_vblank_ctrl vblank_ctrl;
154};
155
156struct msm_format {
157	uint32_t pixel_format;
158};
159
160/* callback from wq once fence has passed: */
161struct msm_fence_cb {
162	struct work_struct work;
163	uint32_t fence;
164	void (*func)(struct msm_fence_cb *cb);
165};
166
167void __msm_fence_worker(struct work_struct *work);
168
169#define INIT_FENCE_CB(_cb, _func)  do {                     \
170		INIT_WORK(&(_cb)->work, __msm_fence_worker); \
171		(_cb)->func = _func;                         \
172	} while (0)
173
174int msm_atomic_check(struct drm_device *dev,
175		     struct drm_atomic_state *state);
176int msm_atomic_commit(struct drm_device *dev,
177		struct drm_atomic_state *state, bool async);
178
179int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
180
181int msm_wait_fence(struct drm_device *dev, uint32_t fence,
182		ktime_t *timeout, bool interruptible);
183int msm_queue_fence_cb(struct drm_device *dev,
184		struct msm_fence_cb *cb, uint32_t fence);
185void msm_update_fence(struct drm_device *dev, uint32_t fence);
186
187int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
188		struct drm_file *file);
189
190int msm_gem_mmap_obj(struct drm_gem_object *obj,
191			struct vm_area_struct *vma);
192int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
193int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
194uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
195int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
196		uint32_t *iova);
197int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova);
198uint32_t msm_gem_iova(struct drm_gem_object *obj, int id);
199struct page **msm_gem_get_pages(struct drm_gem_object *obj);
200void msm_gem_put_pages(struct drm_gem_object *obj);
201void msm_gem_put_iova(struct drm_gem_object *obj, int id);
202int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
203		struct drm_mode_create_dumb *args);
204int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
205		uint32_t handle, uint64_t *offset);
206struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
207void *msm_gem_prime_vmap(struct drm_gem_object *obj);
208void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
209int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
210struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
211		struct dma_buf_attachment *attach, struct sg_table *sg);
212int msm_gem_prime_pin(struct drm_gem_object *obj);
213void msm_gem_prime_unpin(struct drm_gem_object *obj);
214void *msm_gem_vaddr_locked(struct drm_gem_object *obj);
215void *msm_gem_vaddr(struct drm_gem_object *obj);
216int msm_gem_queue_inactive_cb(struct drm_gem_object *obj,
217		struct msm_fence_cb *cb);
218void msm_gem_move_to_active(struct drm_gem_object *obj,
219		struct msm_gpu *gpu, bool write, uint32_t fence);
220void msm_gem_move_to_inactive(struct drm_gem_object *obj);
221int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
222		ktime_t *timeout);
223int msm_gem_cpu_fini(struct drm_gem_object *obj);
224void msm_gem_free_object(struct drm_gem_object *obj);
225int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
226		uint32_t size, uint32_t flags, uint32_t *handle);
227struct drm_gem_object *msm_gem_new(struct drm_device *dev,
228		uint32_t size, uint32_t flags);
229struct drm_gem_object *msm_gem_import(struct drm_device *dev,
230		uint32_t size, struct sg_table *sgt);
231
232int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id);
233void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id);
234uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane);
235struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
236const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
237struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
238		const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
239struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
240		struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
241
242struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
243void msm_fbdev_free(struct drm_device *dev);
244
245struct hdmi;
246int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
247		struct drm_encoder *encoder);
248void __init msm_hdmi_register(void);
249void __exit msm_hdmi_unregister(void);
250
251struct msm_edp;
252void __init msm_edp_register(void);
253void __exit msm_edp_unregister(void);
254int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
255		struct drm_encoder *encoder);
256
257struct msm_dsi;
258enum msm_dsi_encoder_id {
259	MSM_DSI_VIDEO_ENCODER_ID = 0,
260	MSM_DSI_CMD_ENCODER_ID = 1,
261	MSM_DSI_ENCODER_NUM = 2
262};
263#ifdef CONFIG_DRM_MSM_DSI
264void __init msm_dsi_register(void);
265void __exit msm_dsi_unregister(void);
266int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
267		struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]);
268#else
269static inline void __init msm_dsi_register(void)
270{
271}
272static inline void __exit msm_dsi_unregister(void)
273{
274}
275static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
276		struct drm_device *dev,
277		struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM])
278{
279	return -EINVAL;
280}
281#endif
282
283#ifdef CONFIG_DEBUG_FS
284void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
285void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
286void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
287int msm_debugfs_late_init(struct drm_device *dev);
288int msm_rd_debugfs_init(struct drm_minor *minor);
289void msm_rd_debugfs_cleanup(struct drm_minor *minor);
290void msm_rd_dump_submit(struct msm_gem_submit *submit);
291int msm_perf_debugfs_init(struct drm_minor *minor);
292void msm_perf_debugfs_cleanup(struct drm_minor *minor);
293#else
294static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
295static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {}
296#endif
297
298void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
299		const char *dbgname);
300void msm_writel(u32 data, void __iomem *addr);
301u32 msm_readl(const void __iomem *addr);
302
303#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
304#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
305
306static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
307{
308	struct msm_drm_private *priv = dev->dev_private;
309	return priv->completed_fence >= fence;
310}
311
312static inline int align_pitch(int width, int bpp)
313{
314	int bytespp = (bpp + 7) / 8;
315	/* adreno needs pitch aligned to 32 pixels: */
316	return bytespp * ALIGN(width, 32);
317}
318
319/* for the generated headers: */
320#define INVALID_IDX(idx) ({BUG(); 0;})
321#define fui(x)                ({BUG(); 0;})
322#define util_float_to_half(x) ({BUG(); 0;})
323
324
325#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
326
327/* for conditionally setting boolean flag(s): */
328#define COND(bool, val) ((bool) ? (val) : 0)
329
330
331#endif /* __MSM_DRV_H__ */