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1#include <linux/bootmem.h>
2#include <linux/linkage.h>
3#include <linux/bitops.h>
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/percpu.h>
7#include <linux/string.h>
8#include <linux/ctype.h>
9#include <linux/delay.h>
10#include <linux/sched.h>
11#include <linux/init.h>
12#include <linux/kprobes.h>
13#include <linux/kgdb.h>
14#include <linux/smp.h>
15#include <linux/io.h>
16#include <linux/syscore_ops.h>
17
18#include <asm/stackprotector.h>
19#include <asm/perf_event.h>
20#include <asm/mmu_context.h>
21#include <asm/archrandom.h>
22#include <asm/hypervisor.h>
23#include <asm/processor.h>
24#include <asm/tlbflush.h>
25#include <asm/debugreg.h>
26#include <asm/sections.h>
27#include <asm/vsyscall.h>
28#include <linux/topology.h>
29#include <linux/cpumask.h>
30#include <asm/pgtable.h>
31#include <linux/atomic.h>
32#include <asm/proto.h>
33#include <asm/setup.h>
34#include <asm/apic.h>
35#include <asm/desc.h>
36#include <asm/fpu/internal.h>
37#include <asm/mtrr.h>
38#include <linux/numa.h>
39#include <asm/asm.h>
40#include <asm/cpu.h>
41#include <asm/mce.h>
42#include <asm/msr.h>
43#include <asm/pat.h>
44#include <asm/microcode.h>
45#include <asm/microcode_intel.h>
46
47#ifdef CONFIG_X86_LOCAL_APIC
48#include <asm/uv/uv.h>
49#endif
50
51#include "cpu.h"
52
53/* all of these masks are initialized in setup_cpu_local_masks() */
54cpumask_var_t cpu_initialized_mask;
55cpumask_var_t cpu_callout_mask;
56cpumask_var_t cpu_callin_mask;
57
58/* representing cpus for which sibling maps can be computed */
59cpumask_var_t cpu_sibling_setup_mask;
60
61/* correctly size the local cpu masks */
62void __init setup_cpu_local_masks(void)
63{
64 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
65 alloc_bootmem_cpumask_var(&cpu_callin_mask);
66 alloc_bootmem_cpumask_var(&cpu_callout_mask);
67 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
68}
69
70static void default_init(struct cpuinfo_x86 *c)
71{
72#ifdef CONFIG_X86_64
73 cpu_detect_cache_sizes(c);
74#else
75 /* Not much we can do here... */
76 /* Check if at least it has cpuid */
77 if (c->cpuid_level == -1) {
78 /* No cpuid. It must be an ancient CPU */
79 if (c->x86 == 4)
80 strcpy(c->x86_model_id, "486");
81 else if (c->x86 == 3)
82 strcpy(c->x86_model_id, "386");
83 }
84#endif
85}
86
87static const struct cpu_dev default_cpu = {
88 .c_init = default_init,
89 .c_vendor = "Unknown",
90 .c_x86_vendor = X86_VENDOR_UNKNOWN,
91};
92
93static const struct cpu_dev *this_cpu = &default_cpu;
94
95DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
96#ifdef CONFIG_X86_64
97 /*
98 * We need valid kernel segments for data and code in long mode too
99 * IRET will check the segment types kkeil 2000/10/28
100 * Also sysret mandates a special GDT layout
101 *
102 * TLS descriptors are currently at a different place compared to i386.
103 * Hopefully nobody expects them at a fixed place (Wine?)
104 */
105 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
106 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
107 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
108 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
109 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
110 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
111#else
112 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
113 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
114 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
115 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
116 /*
117 * Segments used for calling PnP BIOS have byte granularity.
118 * They code segments and data segments have fixed 64k limits,
119 * the transfer segment sizes are set at run time.
120 */
121 /* 32-bit code */
122 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
123 /* 16-bit code */
124 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
125 /* 16-bit data */
126 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
127 /* 16-bit data */
128 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
129 /* 16-bit data */
130 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
131 /*
132 * The APM segments have byte granularity and their bases
133 * are set at run time. All have 64k limits.
134 */
135 /* 32-bit code */
136 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
137 /* 16-bit code */
138 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
139 /* data */
140 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
141
142 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
143 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
144 GDT_STACK_CANARY_INIT
145#endif
146} };
147EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
148
149static int __init x86_mpx_setup(char *s)
150{
151 /* require an exact match without trailing characters */
152 if (strlen(s))
153 return 0;
154
155 /* do not emit a message if the feature is not present */
156 if (!boot_cpu_has(X86_FEATURE_MPX))
157 return 1;
158
159 setup_clear_cpu_cap(X86_FEATURE_MPX);
160 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
161 return 1;
162}
163__setup("nompx", x86_mpx_setup);
164
165static int __init x86_noinvpcid_setup(char *s)
166{
167 /* noinvpcid doesn't accept parameters */
168 if (s)
169 return -EINVAL;
170
171 /* do not emit a message if the feature is not present */
172 if (!boot_cpu_has(X86_FEATURE_INVPCID))
173 return 0;
174
175 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
176 pr_info("noinvpcid: INVPCID feature disabled\n");
177 return 0;
178}
179early_param("noinvpcid", x86_noinvpcid_setup);
180
181#ifdef CONFIG_X86_32
182static int cachesize_override = -1;
183static int disable_x86_serial_nr = 1;
184
185static int __init cachesize_setup(char *str)
186{
187 get_option(&str, &cachesize_override);
188 return 1;
189}
190__setup("cachesize=", cachesize_setup);
191
192static int __init x86_sep_setup(char *s)
193{
194 setup_clear_cpu_cap(X86_FEATURE_SEP);
195 return 1;
196}
197__setup("nosep", x86_sep_setup);
198
199/* Standard macro to see if a specific flag is changeable */
200static inline int flag_is_changeable_p(u32 flag)
201{
202 u32 f1, f2;
203
204 /*
205 * Cyrix and IDT cpus allow disabling of CPUID
206 * so the code below may return different results
207 * when it is executed before and after enabling
208 * the CPUID. Add "volatile" to not allow gcc to
209 * optimize the subsequent calls to this function.
210 */
211 asm volatile ("pushfl \n\t"
212 "pushfl \n\t"
213 "popl %0 \n\t"
214 "movl %0, %1 \n\t"
215 "xorl %2, %0 \n\t"
216 "pushl %0 \n\t"
217 "popfl \n\t"
218 "pushfl \n\t"
219 "popl %0 \n\t"
220 "popfl \n\t"
221
222 : "=&r" (f1), "=&r" (f2)
223 : "ir" (flag));
224
225 return ((f1^f2) & flag) != 0;
226}
227
228/* Probe for the CPUID instruction */
229int have_cpuid_p(void)
230{
231 return flag_is_changeable_p(X86_EFLAGS_ID);
232}
233
234static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
235{
236 unsigned long lo, hi;
237
238 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
239 return;
240
241 /* Disable processor serial number: */
242
243 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
244 lo |= 0x200000;
245 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
246
247 pr_notice("CPU serial number disabled.\n");
248 clear_cpu_cap(c, X86_FEATURE_PN);
249
250 /* Disabling the serial number may affect the cpuid level */
251 c->cpuid_level = cpuid_eax(0);
252}
253
254static int __init x86_serial_nr_setup(char *s)
255{
256 disable_x86_serial_nr = 0;
257 return 1;
258}
259__setup("serialnumber", x86_serial_nr_setup);
260#else
261static inline int flag_is_changeable_p(u32 flag)
262{
263 return 1;
264}
265static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
266{
267}
268#endif
269
270static __init int setup_disable_smep(char *arg)
271{
272 setup_clear_cpu_cap(X86_FEATURE_SMEP);
273 return 1;
274}
275__setup("nosmep", setup_disable_smep);
276
277static __always_inline void setup_smep(struct cpuinfo_x86 *c)
278{
279 if (cpu_has(c, X86_FEATURE_SMEP))
280 cr4_set_bits(X86_CR4_SMEP);
281}
282
283static __init int setup_disable_smap(char *arg)
284{
285 setup_clear_cpu_cap(X86_FEATURE_SMAP);
286 return 1;
287}
288__setup("nosmap", setup_disable_smap);
289
290static __always_inline void setup_smap(struct cpuinfo_x86 *c)
291{
292 unsigned long eflags = native_save_fl();
293
294 /* This should have been cleared long ago */
295 BUG_ON(eflags & X86_EFLAGS_AC);
296
297 if (cpu_has(c, X86_FEATURE_SMAP)) {
298#ifdef CONFIG_X86_SMAP
299 cr4_set_bits(X86_CR4_SMAP);
300#else
301 cr4_clear_bits(X86_CR4_SMAP);
302#endif
303 }
304}
305
306/*
307 * Protection Keys are not available in 32-bit mode.
308 */
309static bool pku_disabled;
310
311static __always_inline void setup_pku(struct cpuinfo_x86 *c)
312{
313 if (!cpu_has(c, X86_FEATURE_PKU))
314 return;
315 if (pku_disabled)
316 return;
317
318 cr4_set_bits(X86_CR4_PKE);
319 /*
320 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
321 * cpuid bit to be set. We need to ensure that we
322 * update that bit in this CPU's "cpu_info".
323 */
324 get_cpu_cap(c);
325}
326
327#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
328static __init int setup_disable_pku(char *arg)
329{
330 /*
331 * Do not clear the X86_FEATURE_PKU bit. All of the
332 * runtime checks are against OSPKE so clearing the
333 * bit does nothing.
334 *
335 * This way, we will see "pku" in cpuinfo, but not
336 * "ospke", which is exactly what we want. It shows
337 * that the CPU has PKU, but the OS has not enabled it.
338 * This happens to be exactly how a system would look
339 * if we disabled the config option.
340 */
341 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
342 pku_disabled = true;
343 return 1;
344}
345__setup("nopku", setup_disable_pku);
346#endif /* CONFIG_X86_64 */
347
348/*
349 * Some CPU features depend on higher CPUID levels, which may not always
350 * be available due to CPUID level capping or broken virtualization
351 * software. Add those features to this table to auto-disable them.
352 */
353struct cpuid_dependent_feature {
354 u32 feature;
355 u32 level;
356};
357
358static const struct cpuid_dependent_feature
359cpuid_dependent_features[] = {
360 { X86_FEATURE_MWAIT, 0x00000005 },
361 { X86_FEATURE_DCA, 0x00000009 },
362 { X86_FEATURE_XSAVE, 0x0000000d },
363 { 0, 0 }
364};
365
366static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
367{
368 const struct cpuid_dependent_feature *df;
369
370 for (df = cpuid_dependent_features; df->feature; df++) {
371
372 if (!cpu_has(c, df->feature))
373 continue;
374 /*
375 * Note: cpuid_level is set to -1 if unavailable, but
376 * extended_extended_level is set to 0 if unavailable
377 * and the legitimate extended levels are all negative
378 * when signed; hence the weird messing around with
379 * signs here...
380 */
381 if (!((s32)df->level < 0 ?
382 (u32)df->level > (u32)c->extended_cpuid_level :
383 (s32)df->level > (s32)c->cpuid_level))
384 continue;
385
386 clear_cpu_cap(c, df->feature);
387 if (!warn)
388 continue;
389
390 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
391 x86_cap_flag(df->feature), df->level);
392 }
393}
394
395/*
396 * Naming convention should be: <Name> [(<Codename>)]
397 * This table only is used unless init_<vendor>() below doesn't set it;
398 * in particular, if CPUID levels 0x80000002..4 are supported, this
399 * isn't used
400 */
401
402/* Look up CPU names by table lookup. */
403static const char *table_lookup_model(struct cpuinfo_x86 *c)
404{
405#ifdef CONFIG_X86_32
406 const struct legacy_cpu_model_info *info;
407
408 if (c->x86_model >= 16)
409 return NULL; /* Range check */
410
411 if (!this_cpu)
412 return NULL;
413
414 info = this_cpu->legacy_models;
415
416 while (info->family) {
417 if (info->family == c->x86)
418 return info->model_names[c->x86_model];
419 info++;
420 }
421#endif
422 return NULL; /* Not found */
423}
424
425__u32 cpu_caps_cleared[NCAPINTS];
426__u32 cpu_caps_set[NCAPINTS];
427
428void load_percpu_segment(int cpu)
429{
430#ifdef CONFIG_X86_32
431 loadsegment(fs, __KERNEL_PERCPU);
432#else
433 loadsegment(gs, 0);
434 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
435#endif
436 load_stack_canary_segment();
437}
438
439/*
440 * Current gdt points %fs at the "master" per-cpu area: after this,
441 * it's on the real one.
442 */
443void switch_to_new_gdt(int cpu)
444{
445 struct desc_ptr gdt_descr;
446
447 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
448 gdt_descr.size = GDT_SIZE - 1;
449 load_gdt(&gdt_descr);
450 /* Reload the per-cpu base */
451
452 load_percpu_segment(cpu);
453}
454
455static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
456
457static void get_model_name(struct cpuinfo_x86 *c)
458{
459 unsigned int *v;
460 char *p, *q, *s;
461
462 if (c->extended_cpuid_level < 0x80000004)
463 return;
464
465 v = (unsigned int *)c->x86_model_id;
466 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
467 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
468 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
469 c->x86_model_id[48] = 0;
470
471 /* Trim whitespace */
472 p = q = s = &c->x86_model_id[0];
473
474 while (*p == ' ')
475 p++;
476
477 while (*p) {
478 /* Note the last non-whitespace index */
479 if (!isspace(*p))
480 s = q;
481
482 *q++ = *p++;
483 }
484
485 *(s + 1) = '\0';
486}
487
488void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
489{
490 unsigned int n, dummy, ebx, ecx, edx, l2size;
491
492 n = c->extended_cpuid_level;
493
494 if (n >= 0x80000005) {
495 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
496 c->x86_cache_size = (ecx>>24) + (edx>>24);
497#ifdef CONFIG_X86_64
498 /* On K8 L1 TLB is inclusive, so don't count it */
499 c->x86_tlbsize = 0;
500#endif
501 }
502
503 if (n < 0x80000006) /* Some chips just has a large L1. */
504 return;
505
506 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
507 l2size = ecx >> 16;
508
509#ifdef CONFIG_X86_64
510 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
511#else
512 /* do processor-specific cache resizing */
513 if (this_cpu->legacy_cache_size)
514 l2size = this_cpu->legacy_cache_size(c, l2size);
515
516 /* Allow user to override all this if necessary. */
517 if (cachesize_override != -1)
518 l2size = cachesize_override;
519
520 if (l2size == 0)
521 return; /* Again, no L2 cache is possible */
522#endif
523
524 c->x86_cache_size = l2size;
525}
526
527u16 __read_mostly tlb_lli_4k[NR_INFO];
528u16 __read_mostly tlb_lli_2m[NR_INFO];
529u16 __read_mostly tlb_lli_4m[NR_INFO];
530u16 __read_mostly tlb_lld_4k[NR_INFO];
531u16 __read_mostly tlb_lld_2m[NR_INFO];
532u16 __read_mostly tlb_lld_4m[NR_INFO];
533u16 __read_mostly tlb_lld_1g[NR_INFO];
534
535static void cpu_detect_tlb(struct cpuinfo_x86 *c)
536{
537 if (this_cpu->c_detect_tlb)
538 this_cpu->c_detect_tlb(c);
539
540 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
541 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
542 tlb_lli_4m[ENTRIES]);
543
544 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
545 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
546 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
547}
548
549void detect_ht(struct cpuinfo_x86 *c)
550{
551#ifdef CONFIG_SMP
552 u32 eax, ebx, ecx, edx;
553 int index_msb, core_bits;
554 static bool printed;
555
556 if (!cpu_has(c, X86_FEATURE_HT))
557 return;
558
559 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
560 goto out;
561
562 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
563 return;
564
565 cpuid(1, &eax, &ebx, &ecx, &edx);
566
567 smp_num_siblings = (ebx & 0xff0000) >> 16;
568
569 if (smp_num_siblings == 1) {
570 pr_info_once("CPU0: Hyper-Threading is disabled\n");
571 goto out;
572 }
573
574 if (smp_num_siblings <= 1)
575 goto out;
576
577 index_msb = get_count_order(smp_num_siblings);
578 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
579
580 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
581
582 index_msb = get_count_order(smp_num_siblings);
583
584 core_bits = get_count_order(c->x86_max_cores);
585
586 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
587 ((1 << core_bits) - 1);
588
589out:
590 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
591 pr_info("CPU: Physical Processor ID: %d\n",
592 c->phys_proc_id);
593 pr_info("CPU: Processor Core ID: %d\n",
594 c->cpu_core_id);
595 printed = 1;
596 }
597#endif
598}
599
600static void get_cpu_vendor(struct cpuinfo_x86 *c)
601{
602 char *v = c->x86_vendor_id;
603 int i;
604
605 for (i = 0; i < X86_VENDOR_NUM; i++) {
606 if (!cpu_devs[i])
607 break;
608
609 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
610 (cpu_devs[i]->c_ident[1] &&
611 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
612
613 this_cpu = cpu_devs[i];
614 c->x86_vendor = this_cpu->c_x86_vendor;
615 return;
616 }
617 }
618
619 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
620 "CPU: Your system may be unstable.\n", v);
621
622 c->x86_vendor = X86_VENDOR_UNKNOWN;
623 this_cpu = &default_cpu;
624}
625
626void cpu_detect(struct cpuinfo_x86 *c)
627{
628 /* Get vendor name */
629 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
630 (unsigned int *)&c->x86_vendor_id[0],
631 (unsigned int *)&c->x86_vendor_id[8],
632 (unsigned int *)&c->x86_vendor_id[4]);
633
634 c->x86 = 4;
635 /* Intel-defined flags: level 0x00000001 */
636 if (c->cpuid_level >= 0x00000001) {
637 u32 junk, tfms, cap0, misc;
638
639 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
640 c->x86 = x86_family(tfms);
641 c->x86_model = x86_model(tfms);
642 c->x86_mask = x86_stepping(tfms);
643
644 if (cap0 & (1<<19)) {
645 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
646 c->x86_cache_alignment = c->x86_clflush_size;
647 }
648 }
649}
650
651void get_cpu_cap(struct cpuinfo_x86 *c)
652{
653 u32 eax, ebx, ecx, edx;
654
655 /* Intel-defined flags: level 0x00000001 */
656 if (c->cpuid_level >= 0x00000001) {
657 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
658
659 c->x86_capability[CPUID_1_ECX] = ecx;
660 c->x86_capability[CPUID_1_EDX] = edx;
661 }
662
663 /* Additional Intel-defined flags: level 0x00000007 */
664 if (c->cpuid_level >= 0x00000007) {
665 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
666
667 c->x86_capability[CPUID_7_0_EBX] = ebx;
668
669 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
670 c->x86_capability[CPUID_7_ECX] = ecx;
671 }
672
673 /* Extended state features: level 0x0000000d */
674 if (c->cpuid_level >= 0x0000000d) {
675 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
676
677 c->x86_capability[CPUID_D_1_EAX] = eax;
678 }
679
680 /* Additional Intel-defined flags: level 0x0000000F */
681 if (c->cpuid_level >= 0x0000000F) {
682
683 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
684 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
685 c->x86_capability[CPUID_F_0_EDX] = edx;
686
687 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
688 /* will be overridden if occupancy monitoring exists */
689 c->x86_cache_max_rmid = ebx;
690
691 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
692 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
693 c->x86_capability[CPUID_F_1_EDX] = edx;
694
695 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
696 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
697 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
698 c->x86_cache_max_rmid = ecx;
699 c->x86_cache_occ_scale = ebx;
700 }
701 } else {
702 c->x86_cache_max_rmid = -1;
703 c->x86_cache_occ_scale = -1;
704 }
705 }
706
707 /* AMD-defined flags: level 0x80000001 */
708 eax = cpuid_eax(0x80000000);
709 c->extended_cpuid_level = eax;
710
711 if ((eax & 0xffff0000) == 0x80000000) {
712 if (eax >= 0x80000001) {
713 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
714
715 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
716 c->x86_capability[CPUID_8000_0001_EDX] = edx;
717 }
718 }
719
720 if (c->extended_cpuid_level >= 0x80000008) {
721 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
722
723 c->x86_virt_bits = (eax >> 8) & 0xff;
724 c->x86_phys_bits = eax & 0xff;
725 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
726 }
727#ifdef CONFIG_X86_32
728 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
729 c->x86_phys_bits = 36;
730#endif
731
732 if (c->extended_cpuid_level >= 0x80000007)
733 c->x86_power = cpuid_edx(0x80000007);
734
735 if (c->extended_cpuid_level >= 0x8000000a)
736 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
737
738 init_scattered_cpuid_features(c);
739}
740
741static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
742{
743#ifdef CONFIG_X86_32
744 int i;
745
746 /*
747 * First of all, decide if this is a 486 or higher
748 * It's a 486 if we can modify the AC flag
749 */
750 if (flag_is_changeable_p(X86_EFLAGS_AC))
751 c->x86 = 4;
752 else
753 c->x86 = 3;
754
755 for (i = 0; i < X86_VENDOR_NUM; i++)
756 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
757 c->x86_vendor_id[0] = 0;
758 cpu_devs[i]->c_identify(c);
759 if (c->x86_vendor_id[0]) {
760 get_cpu_vendor(c);
761 break;
762 }
763 }
764#endif
765}
766
767/*
768 * Do minimum CPU detection early.
769 * Fields really needed: vendor, cpuid_level, family, model, mask,
770 * cache alignment.
771 * The others are not touched to avoid unwanted side effects.
772 *
773 * WARNING: this function is only called on the BP. Don't add code here
774 * that is supposed to run on all CPUs.
775 */
776static void __init early_identify_cpu(struct cpuinfo_x86 *c)
777{
778#ifdef CONFIG_X86_64
779 c->x86_clflush_size = 64;
780 c->x86_phys_bits = 36;
781 c->x86_virt_bits = 48;
782#else
783 c->x86_clflush_size = 32;
784 c->x86_phys_bits = 32;
785 c->x86_virt_bits = 32;
786#endif
787 c->x86_cache_alignment = c->x86_clflush_size;
788
789 memset(&c->x86_capability, 0, sizeof c->x86_capability);
790 c->extended_cpuid_level = 0;
791
792 if (!have_cpuid_p())
793 identify_cpu_without_cpuid(c);
794
795 /* cyrix could have cpuid enabled via c_identify()*/
796 if (!have_cpuid_p())
797 return;
798
799 cpu_detect(c);
800 get_cpu_vendor(c);
801 get_cpu_cap(c);
802
803 if (this_cpu->c_early_init)
804 this_cpu->c_early_init(c);
805
806 c->cpu_index = 0;
807 filter_cpuid_features(c, false);
808
809 if (this_cpu->c_bsp_init)
810 this_cpu->c_bsp_init(c);
811
812 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
813 fpu__init_system(c);
814}
815
816void __init early_cpu_init(void)
817{
818 const struct cpu_dev *const *cdev;
819 int count = 0;
820
821#ifdef CONFIG_PROCESSOR_SELECT
822 pr_info("KERNEL supported cpus:\n");
823#endif
824
825 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
826 const struct cpu_dev *cpudev = *cdev;
827
828 if (count >= X86_VENDOR_NUM)
829 break;
830 cpu_devs[count] = cpudev;
831 count++;
832
833#ifdef CONFIG_PROCESSOR_SELECT
834 {
835 unsigned int j;
836
837 for (j = 0; j < 2; j++) {
838 if (!cpudev->c_ident[j])
839 continue;
840 pr_info(" %s %s\n", cpudev->c_vendor,
841 cpudev->c_ident[j]);
842 }
843 }
844#endif
845 }
846 early_identify_cpu(&boot_cpu_data);
847}
848
849/*
850 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
851 * unfortunately, that's not true in practice because of early VIA
852 * chips and (more importantly) broken virtualizers that are not easy
853 * to detect. In the latter case it doesn't even *fail* reliably, so
854 * probing for it doesn't even work. Disable it completely on 32-bit
855 * unless we can find a reliable way to detect all the broken cases.
856 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
857 */
858static void detect_nopl(struct cpuinfo_x86 *c)
859{
860#ifdef CONFIG_X86_32
861 clear_cpu_cap(c, X86_FEATURE_NOPL);
862#else
863 set_cpu_cap(c, X86_FEATURE_NOPL);
864#endif
865
866 /*
867 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
868 * systems that run Linux at CPL > 0 may or may not have the
869 * issue, but, even if they have the issue, there's absolutely
870 * nothing we can do about it because we can't use the real IRET
871 * instruction.
872 *
873 * NB: For the time being, only 32-bit kernels support
874 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
875 * whether to apply espfix using paravirt hooks. If any
876 * non-paravirt system ever shows up that does *not* have the
877 * ESPFIX issue, we can change this.
878 */
879#ifdef CONFIG_X86_32
880#ifdef CONFIG_PARAVIRT
881 do {
882 extern void native_iret(void);
883 if (pv_cpu_ops.iret == native_iret)
884 set_cpu_bug(c, X86_BUG_ESPFIX);
885 } while (0);
886#else
887 set_cpu_bug(c, X86_BUG_ESPFIX);
888#endif
889#endif
890}
891
892static void generic_identify(struct cpuinfo_x86 *c)
893{
894 c->extended_cpuid_level = 0;
895
896 if (!have_cpuid_p())
897 identify_cpu_without_cpuid(c);
898
899 /* cyrix could have cpuid enabled via c_identify()*/
900 if (!have_cpuid_p())
901 return;
902
903 cpu_detect(c);
904
905 get_cpu_vendor(c);
906
907 get_cpu_cap(c);
908
909 if (c->cpuid_level >= 0x00000001) {
910 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
911#ifdef CONFIG_X86_32
912# ifdef CONFIG_SMP
913 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
914# else
915 c->apicid = c->initial_apicid;
916# endif
917#endif
918 c->phys_proc_id = c->initial_apicid;
919 }
920
921 get_model_name(c); /* Default name */
922
923 detect_nopl(c);
924}
925
926static void x86_init_cache_qos(struct cpuinfo_x86 *c)
927{
928 /*
929 * The heavy lifting of max_rmid and cache_occ_scale are handled
930 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
931 * in case CQM bits really aren't there in this CPU.
932 */
933 if (c != &boot_cpu_data) {
934 boot_cpu_data.x86_cache_max_rmid =
935 min(boot_cpu_data.x86_cache_max_rmid,
936 c->x86_cache_max_rmid);
937 }
938}
939
940/*
941 * This does the hard work of actually picking apart the CPU stuff...
942 */
943static void identify_cpu(struct cpuinfo_x86 *c)
944{
945 int i;
946
947 c->loops_per_jiffy = loops_per_jiffy;
948 c->x86_cache_size = -1;
949 c->x86_vendor = X86_VENDOR_UNKNOWN;
950 c->x86_model = c->x86_mask = 0; /* So far unknown... */
951 c->x86_vendor_id[0] = '\0'; /* Unset */
952 c->x86_model_id[0] = '\0'; /* Unset */
953 c->x86_max_cores = 1;
954 c->x86_coreid_bits = 0;
955#ifdef CONFIG_X86_64
956 c->x86_clflush_size = 64;
957 c->x86_phys_bits = 36;
958 c->x86_virt_bits = 48;
959#else
960 c->cpuid_level = -1; /* CPUID not detected */
961 c->x86_clflush_size = 32;
962 c->x86_phys_bits = 32;
963 c->x86_virt_bits = 32;
964#endif
965 c->x86_cache_alignment = c->x86_clflush_size;
966 memset(&c->x86_capability, 0, sizeof c->x86_capability);
967
968 generic_identify(c);
969
970 if (this_cpu->c_identify)
971 this_cpu->c_identify(c);
972
973 /* Clear/Set all flags overridden by options, after probe */
974 for (i = 0; i < NCAPINTS; i++) {
975 c->x86_capability[i] &= ~cpu_caps_cleared[i];
976 c->x86_capability[i] |= cpu_caps_set[i];
977 }
978
979#ifdef CONFIG_X86_64
980 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
981#endif
982
983 /*
984 * Vendor-specific initialization. In this section we
985 * canonicalize the feature flags, meaning if there are
986 * features a certain CPU supports which CPUID doesn't
987 * tell us, CPUID claiming incorrect flags, or other bugs,
988 * we handle them here.
989 *
990 * At the end of this section, c->x86_capability better
991 * indicate the features this CPU genuinely supports!
992 */
993 if (this_cpu->c_init)
994 this_cpu->c_init(c);
995
996 /* Disable the PN if appropriate */
997 squash_the_stupid_serial_number(c);
998
999 /* Set up SMEP/SMAP */
1000 setup_smep(c);
1001 setup_smap(c);
1002
1003 /*
1004 * The vendor-specific functions might have changed features.
1005 * Now we do "generic changes."
1006 */
1007
1008 /* Filter out anything that depends on CPUID levels we don't have */
1009 filter_cpuid_features(c, true);
1010
1011 /* If the model name is still unset, do table lookup. */
1012 if (!c->x86_model_id[0]) {
1013 const char *p;
1014 p = table_lookup_model(c);
1015 if (p)
1016 strcpy(c->x86_model_id, p);
1017 else
1018 /* Last resort... */
1019 sprintf(c->x86_model_id, "%02x/%02x",
1020 c->x86, c->x86_model);
1021 }
1022
1023#ifdef CONFIG_X86_64
1024 detect_ht(c);
1025#endif
1026
1027 init_hypervisor(c);
1028 x86_init_rdrand(c);
1029 x86_init_cache_qos(c);
1030 setup_pku(c);
1031
1032 /*
1033 * Clear/Set all flags overridden by options, need do it
1034 * before following smp all cpus cap AND.
1035 */
1036 for (i = 0; i < NCAPINTS; i++) {
1037 c->x86_capability[i] &= ~cpu_caps_cleared[i];
1038 c->x86_capability[i] |= cpu_caps_set[i];
1039 }
1040
1041 /*
1042 * On SMP, boot_cpu_data holds the common feature set between
1043 * all CPUs; so make sure that we indicate which features are
1044 * common between the CPUs. The first time this routine gets
1045 * executed, c == &boot_cpu_data.
1046 */
1047 if (c != &boot_cpu_data) {
1048 /* AND the already accumulated flags with these */
1049 for (i = 0; i < NCAPINTS; i++)
1050 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1051
1052 /* OR, i.e. replicate the bug flags */
1053 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1054 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1055 }
1056
1057 /* Init Machine Check Exception if available. */
1058 mcheck_cpu_init(c);
1059
1060 select_idle_routine(c);
1061
1062#ifdef CONFIG_NUMA
1063 numa_add_cpu(smp_processor_id());
1064#endif
1065 /* The boot/hotplug time assigment got cleared, restore it */
1066 c->logical_proc_id = topology_phys_to_logical_pkg(c->phys_proc_id);
1067}
1068
1069/*
1070 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1071 * on 32-bit kernels:
1072 */
1073#ifdef CONFIG_X86_32
1074void enable_sep_cpu(void)
1075{
1076 struct tss_struct *tss;
1077 int cpu;
1078
1079 cpu = get_cpu();
1080 tss = &per_cpu(cpu_tss, cpu);
1081
1082 if (!boot_cpu_has(X86_FEATURE_SEP))
1083 goto out;
1084
1085 /*
1086 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1087 * see the big comment in struct x86_hw_tss's definition.
1088 */
1089
1090 tss->x86_tss.ss1 = __KERNEL_CS;
1091 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1092
1093 wrmsr(MSR_IA32_SYSENTER_ESP,
1094 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack),
1095 0);
1096
1097 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1098
1099out:
1100 put_cpu();
1101}
1102#endif
1103
1104void __init identify_boot_cpu(void)
1105{
1106 identify_cpu(&boot_cpu_data);
1107 init_amd_e400_c1e_mask();
1108#ifdef CONFIG_X86_32
1109 sysenter_setup();
1110 enable_sep_cpu();
1111#endif
1112 cpu_detect_tlb(&boot_cpu_data);
1113}
1114
1115void identify_secondary_cpu(struct cpuinfo_x86 *c)
1116{
1117 BUG_ON(c == &boot_cpu_data);
1118 identify_cpu(c);
1119#ifdef CONFIG_X86_32
1120 enable_sep_cpu();
1121#endif
1122 mtrr_ap_init();
1123}
1124
1125struct msr_range {
1126 unsigned min;
1127 unsigned max;
1128};
1129
1130static const struct msr_range msr_range_array[] = {
1131 { 0x00000000, 0x00000418},
1132 { 0xc0000000, 0xc000040b},
1133 { 0xc0010000, 0xc0010142},
1134 { 0xc0011000, 0xc001103b},
1135};
1136
1137static void __print_cpu_msr(void)
1138{
1139 unsigned index_min, index_max;
1140 unsigned index;
1141 u64 val;
1142 int i;
1143
1144 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1145 index_min = msr_range_array[i].min;
1146 index_max = msr_range_array[i].max;
1147
1148 for (index = index_min; index < index_max; index++) {
1149 if (rdmsrl_safe(index, &val))
1150 continue;
1151 pr_info(" MSR%08x: %016llx\n", index, val);
1152 }
1153 }
1154}
1155
1156static int show_msr;
1157
1158static __init int setup_show_msr(char *arg)
1159{
1160 int num;
1161
1162 get_option(&arg, &num);
1163
1164 if (num > 0)
1165 show_msr = num;
1166 return 1;
1167}
1168__setup("show_msr=", setup_show_msr);
1169
1170static __init int setup_noclflush(char *arg)
1171{
1172 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1173 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1174 return 1;
1175}
1176__setup("noclflush", setup_noclflush);
1177
1178void print_cpu_info(struct cpuinfo_x86 *c)
1179{
1180 const char *vendor = NULL;
1181
1182 if (c->x86_vendor < X86_VENDOR_NUM) {
1183 vendor = this_cpu->c_vendor;
1184 } else {
1185 if (c->cpuid_level >= 0)
1186 vendor = c->x86_vendor_id;
1187 }
1188
1189 if (vendor && !strstr(c->x86_model_id, vendor))
1190 pr_cont("%s ", vendor);
1191
1192 if (c->x86_model_id[0])
1193 pr_cont("%s", c->x86_model_id);
1194 else
1195 pr_cont("%d86", c->x86);
1196
1197 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1198
1199 if (c->x86_mask || c->cpuid_level >= 0)
1200 pr_cont(", stepping: 0x%x)\n", c->x86_mask);
1201 else
1202 pr_cont(")\n");
1203
1204 print_cpu_msr(c);
1205}
1206
1207void print_cpu_msr(struct cpuinfo_x86 *c)
1208{
1209 if (c->cpu_index < show_msr)
1210 __print_cpu_msr();
1211}
1212
1213static __init int setup_disablecpuid(char *arg)
1214{
1215 int bit;
1216
1217 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1218 setup_clear_cpu_cap(bit);
1219 else
1220 return 0;
1221
1222 return 1;
1223}
1224__setup("clearcpuid=", setup_disablecpuid);
1225
1226#ifdef CONFIG_X86_64
1227struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1228struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1,
1229 (unsigned long) debug_idt_table };
1230
1231DEFINE_PER_CPU_FIRST(union irq_stack_union,
1232 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1233
1234/*
1235 * The following percpu variables are hot. Align current_task to
1236 * cacheline size such that they fall in the same cacheline.
1237 */
1238DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1239 &init_task;
1240EXPORT_PER_CPU_SYMBOL(current_task);
1241
1242DEFINE_PER_CPU(char *, irq_stack_ptr) =
1243 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1244
1245DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1246
1247DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1248EXPORT_PER_CPU_SYMBOL(__preempt_count);
1249
1250/*
1251 * Special IST stacks which the CPU switches to when it calls
1252 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1253 * limit), all of them are 4K, except the debug stack which
1254 * is 8K.
1255 */
1256static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1257 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1258 [DEBUG_STACK - 1] = DEBUG_STKSZ
1259};
1260
1261static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1262 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1263
1264/* May not be marked __init: used by software suspend */
1265void syscall_init(void)
1266{
1267 /*
1268 * LSTAR and STAR live in a bit strange symbiosis.
1269 * They both write to the same internal register. STAR allows to
1270 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1271 */
1272 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1273 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1274
1275#ifdef CONFIG_IA32_EMULATION
1276 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1277 /*
1278 * This only works on Intel CPUs.
1279 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1280 * This does not cause SYSENTER to jump to the wrong location, because
1281 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1282 */
1283 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1284 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1285 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1286#else
1287 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1288 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1289 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1290 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1291#endif
1292
1293 /* Flags to clear on syscall */
1294 wrmsrl(MSR_SYSCALL_MASK,
1295 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1296 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1297}
1298
1299/*
1300 * Copies of the original ist values from the tss are only accessed during
1301 * debugging, no special alignment required.
1302 */
1303DEFINE_PER_CPU(struct orig_ist, orig_ist);
1304
1305static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1306DEFINE_PER_CPU(int, debug_stack_usage);
1307
1308int is_debug_stack(unsigned long addr)
1309{
1310 return __this_cpu_read(debug_stack_usage) ||
1311 (addr <= __this_cpu_read(debug_stack_addr) &&
1312 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1313}
1314NOKPROBE_SYMBOL(is_debug_stack);
1315
1316DEFINE_PER_CPU(u32, debug_idt_ctr);
1317
1318void debug_stack_set_zero(void)
1319{
1320 this_cpu_inc(debug_idt_ctr);
1321 load_current_idt();
1322}
1323NOKPROBE_SYMBOL(debug_stack_set_zero);
1324
1325void debug_stack_reset(void)
1326{
1327 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1328 return;
1329 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1330 load_current_idt();
1331}
1332NOKPROBE_SYMBOL(debug_stack_reset);
1333
1334#else /* CONFIG_X86_64 */
1335
1336DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1337EXPORT_PER_CPU_SYMBOL(current_task);
1338DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1339EXPORT_PER_CPU_SYMBOL(__preempt_count);
1340
1341/*
1342 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1343 * the top of the kernel stack. Use an extra percpu variable to track the
1344 * top of the kernel stack directly.
1345 */
1346DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1347 (unsigned long)&init_thread_union + THREAD_SIZE;
1348EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1349
1350#ifdef CONFIG_CC_STACKPROTECTOR
1351DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1352#endif
1353
1354#endif /* CONFIG_X86_64 */
1355
1356/*
1357 * Clear all 6 debug registers:
1358 */
1359static void clear_all_debug_regs(void)
1360{
1361 int i;
1362
1363 for (i = 0; i < 8; i++) {
1364 /* Ignore db4, db5 */
1365 if ((i == 4) || (i == 5))
1366 continue;
1367
1368 set_debugreg(0, i);
1369 }
1370}
1371
1372#ifdef CONFIG_KGDB
1373/*
1374 * Restore debug regs if using kgdbwait and you have a kernel debugger
1375 * connection established.
1376 */
1377static void dbg_restore_debug_regs(void)
1378{
1379 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1380 arch_kgdb_ops.correct_hw_break();
1381}
1382#else /* ! CONFIG_KGDB */
1383#define dbg_restore_debug_regs()
1384#endif /* ! CONFIG_KGDB */
1385
1386static void wait_for_master_cpu(int cpu)
1387{
1388#ifdef CONFIG_SMP
1389 /*
1390 * wait for ACK from master CPU before continuing
1391 * with AP initialization
1392 */
1393 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1394 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1395 cpu_relax();
1396#endif
1397}
1398
1399/*
1400 * cpu_init() initializes state that is per-CPU. Some data is already
1401 * initialized (naturally) in the bootstrap process, such as the GDT
1402 * and IDT. We reload them nevertheless, this function acts as a
1403 * 'CPU state barrier', nothing should get across.
1404 * A lot of state is already set up in PDA init for 64 bit
1405 */
1406#ifdef CONFIG_X86_64
1407
1408void cpu_init(void)
1409{
1410 struct orig_ist *oist;
1411 struct task_struct *me;
1412 struct tss_struct *t;
1413 unsigned long v;
1414 int cpu = stack_smp_processor_id();
1415 int i;
1416
1417 wait_for_master_cpu(cpu);
1418
1419 /*
1420 * Initialize the CR4 shadow before doing anything that could
1421 * try to read it.
1422 */
1423 cr4_init_shadow();
1424
1425 /*
1426 * Load microcode on this cpu if a valid microcode is available.
1427 * This is early microcode loading procedure.
1428 */
1429 load_ucode_ap();
1430
1431 t = &per_cpu(cpu_tss, cpu);
1432 oist = &per_cpu(orig_ist, cpu);
1433
1434#ifdef CONFIG_NUMA
1435 if (this_cpu_read(numa_node) == 0 &&
1436 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1437 set_numa_node(early_cpu_to_node(cpu));
1438#endif
1439
1440 me = current;
1441
1442 pr_debug("Initializing CPU#%d\n", cpu);
1443
1444 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1445
1446 /*
1447 * Initialize the per-CPU GDT with the boot GDT,
1448 * and set up the GDT descriptor:
1449 */
1450
1451 switch_to_new_gdt(cpu);
1452 loadsegment(fs, 0);
1453
1454 load_current_idt();
1455
1456 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1457 syscall_init();
1458
1459 wrmsrl(MSR_FS_BASE, 0);
1460 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1461 barrier();
1462
1463 x86_configure_nx();
1464 x2apic_setup();
1465
1466 /*
1467 * set up and load the per-CPU TSS
1468 */
1469 if (!oist->ist[0]) {
1470 char *estacks = per_cpu(exception_stacks, cpu);
1471
1472 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1473 estacks += exception_stack_sizes[v];
1474 oist->ist[v] = t->x86_tss.ist[v] =
1475 (unsigned long)estacks;
1476 if (v == DEBUG_STACK-1)
1477 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1478 }
1479 }
1480
1481 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1482
1483 /*
1484 * <= is required because the CPU will access up to
1485 * 8 bits beyond the end of the IO permission bitmap.
1486 */
1487 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1488 t->io_bitmap[i] = ~0UL;
1489
1490 atomic_inc(&init_mm.mm_count);
1491 me->active_mm = &init_mm;
1492 BUG_ON(me->mm);
1493 enter_lazy_tlb(&init_mm, me);
1494
1495 load_sp0(t, ¤t->thread);
1496 set_tss_desc(cpu, t);
1497 load_TR_desc();
1498 load_mm_ldt(&init_mm);
1499
1500 clear_all_debug_regs();
1501 dbg_restore_debug_regs();
1502
1503 fpu__init_cpu();
1504
1505 if (is_uv_system())
1506 uv_cpu_init();
1507}
1508
1509#else
1510
1511void cpu_init(void)
1512{
1513 int cpu = smp_processor_id();
1514 struct task_struct *curr = current;
1515 struct tss_struct *t = &per_cpu(cpu_tss, cpu);
1516 struct thread_struct *thread = &curr->thread;
1517
1518 wait_for_master_cpu(cpu);
1519
1520 /*
1521 * Initialize the CR4 shadow before doing anything that could
1522 * try to read it.
1523 */
1524 cr4_init_shadow();
1525
1526 show_ucode_info_early();
1527
1528 pr_info("Initializing CPU#%d\n", cpu);
1529
1530 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1531 cpu_has_tsc ||
1532 boot_cpu_has(X86_FEATURE_DE))
1533 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1534
1535 load_current_idt();
1536 switch_to_new_gdt(cpu);
1537
1538 /*
1539 * Set up and load the per-CPU TSS and LDT
1540 */
1541 atomic_inc(&init_mm.mm_count);
1542 curr->active_mm = &init_mm;
1543 BUG_ON(curr->mm);
1544 enter_lazy_tlb(&init_mm, curr);
1545
1546 load_sp0(t, thread);
1547 set_tss_desc(cpu, t);
1548 load_TR_desc();
1549 load_mm_ldt(&init_mm);
1550
1551 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1552
1553#ifdef CONFIG_DOUBLEFAULT
1554 /* Set up doublefault TSS pointer in the GDT */
1555 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1556#endif
1557
1558 clear_all_debug_regs();
1559 dbg_restore_debug_regs();
1560
1561 fpu__init_cpu();
1562}
1563#endif
1564
1565static void bsp_resume(void)
1566{
1567 if (this_cpu->c_bsp_resume)
1568 this_cpu->c_bsp_resume(&boot_cpu_data);
1569}
1570
1571static struct syscore_ops cpu_syscore_ops = {
1572 .resume = bsp_resume,
1573};
1574
1575static int __init init_cpu_syscore(void)
1576{
1577 register_syscore_ops(&cpu_syscore_ops);
1578 return 0;
1579}
1580core_initcall(init_cpu_syscore);
1#include <linux/bootmem.h>
2#include <linux/linkage.h>
3#include <linux/bitops.h>
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/percpu.h>
7#include <linux/string.h>
8#include <linux/delay.h>
9#include <linux/sched.h>
10#include <linux/init.h>
11#include <linux/kgdb.h>
12#include <linux/smp.h>
13#include <linux/io.h>
14
15#include <asm/stackprotector.h>
16#include <asm/perf_event.h>
17#include <asm/mmu_context.h>
18#include <asm/hypervisor.h>
19#include <asm/processor.h>
20#include <asm/sections.h>
21#include <linux/topology.h>
22#include <linux/cpumask.h>
23#include <asm/pgtable.h>
24#include <linux/atomic.h>
25#include <asm/proto.h>
26#include <asm/setup.h>
27#include <asm/apic.h>
28#include <asm/desc.h>
29#include <asm/i387.h>
30#include <asm/mtrr.h>
31#include <linux/numa.h>
32#include <asm/asm.h>
33#include <asm/cpu.h>
34#include <asm/mce.h>
35#include <asm/msr.h>
36#include <asm/pat.h>
37
38#ifdef CONFIG_X86_LOCAL_APIC
39#include <asm/uv/uv.h>
40#endif
41
42#include "cpu.h"
43
44/* all of these masks are initialized in setup_cpu_local_masks() */
45cpumask_var_t cpu_initialized_mask;
46cpumask_var_t cpu_callout_mask;
47cpumask_var_t cpu_callin_mask;
48
49/* representing cpus for which sibling maps can be computed */
50cpumask_var_t cpu_sibling_setup_mask;
51
52/* correctly size the local cpu masks */
53void __init setup_cpu_local_masks(void)
54{
55 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
56 alloc_bootmem_cpumask_var(&cpu_callin_mask);
57 alloc_bootmem_cpumask_var(&cpu_callout_mask);
58 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
59}
60
61static void __cpuinit default_init(struct cpuinfo_x86 *c)
62{
63#ifdef CONFIG_X86_64
64 cpu_detect_cache_sizes(c);
65#else
66 /* Not much we can do here... */
67 /* Check if at least it has cpuid */
68 if (c->cpuid_level == -1) {
69 /* No cpuid. It must be an ancient CPU */
70 if (c->x86 == 4)
71 strcpy(c->x86_model_id, "486");
72 else if (c->x86 == 3)
73 strcpy(c->x86_model_id, "386");
74 }
75#endif
76}
77
78static const struct cpu_dev __cpuinitconst default_cpu = {
79 .c_init = default_init,
80 .c_vendor = "Unknown",
81 .c_x86_vendor = X86_VENDOR_UNKNOWN,
82};
83
84static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
85
86DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
87#ifdef CONFIG_X86_64
88 /*
89 * We need valid kernel segments for data and code in long mode too
90 * IRET will check the segment types kkeil 2000/10/28
91 * Also sysret mandates a special GDT layout
92 *
93 * TLS descriptors are currently at a different place compared to i386.
94 * Hopefully nobody expects them at a fixed place (Wine?)
95 */
96 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
97 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
98 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
99 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
100 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
101 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
102#else
103 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
104 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
105 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
106 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
107 /*
108 * Segments used for calling PnP BIOS have byte granularity.
109 * They code segments and data segments have fixed 64k limits,
110 * the transfer segment sizes are set at run time.
111 */
112 /* 32-bit code */
113 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
114 /* 16-bit code */
115 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
116 /* 16-bit data */
117 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
118 /* 16-bit data */
119 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
120 /* 16-bit data */
121 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
122 /*
123 * The APM segments have byte granularity and their bases
124 * are set at run time. All have 64k limits.
125 */
126 /* 32-bit code */
127 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
128 /* 16-bit code */
129 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
130 /* data */
131 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
132
133 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
134 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
135 GDT_STACK_CANARY_INIT
136#endif
137} };
138EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
139
140static int __init x86_xsave_setup(char *s)
141{
142 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
143 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
144 return 1;
145}
146__setup("noxsave", x86_xsave_setup);
147
148static int __init x86_xsaveopt_setup(char *s)
149{
150 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
151 return 1;
152}
153__setup("noxsaveopt", x86_xsaveopt_setup);
154
155#ifdef CONFIG_X86_32
156static int cachesize_override __cpuinitdata = -1;
157static int disable_x86_serial_nr __cpuinitdata = 1;
158
159static int __init cachesize_setup(char *str)
160{
161 get_option(&str, &cachesize_override);
162 return 1;
163}
164__setup("cachesize=", cachesize_setup);
165
166static int __init x86_fxsr_setup(char *s)
167{
168 setup_clear_cpu_cap(X86_FEATURE_FXSR);
169 setup_clear_cpu_cap(X86_FEATURE_XMM);
170 return 1;
171}
172__setup("nofxsr", x86_fxsr_setup);
173
174static int __init x86_sep_setup(char *s)
175{
176 setup_clear_cpu_cap(X86_FEATURE_SEP);
177 return 1;
178}
179__setup("nosep", x86_sep_setup);
180
181/* Standard macro to see if a specific flag is changeable */
182static inline int flag_is_changeable_p(u32 flag)
183{
184 u32 f1, f2;
185
186 /*
187 * Cyrix and IDT cpus allow disabling of CPUID
188 * so the code below may return different results
189 * when it is executed before and after enabling
190 * the CPUID. Add "volatile" to not allow gcc to
191 * optimize the subsequent calls to this function.
192 */
193 asm volatile ("pushfl \n\t"
194 "pushfl \n\t"
195 "popl %0 \n\t"
196 "movl %0, %1 \n\t"
197 "xorl %2, %0 \n\t"
198 "pushl %0 \n\t"
199 "popfl \n\t"
200 "pushfl \n\t"
201 "popl %0 \n\t"
202 "popfl \n\t"
203
204 : "=&r" (f1), "=&r" (f2)
205 : "ir" (flag));
206
207 return ((f1^f2) & flag) != 0;
208}
209
210/* Probe for the CPUID instruction */
211static int __cpuinit have_cpuid_p(void)
212{
213 return flag_is_changeable_p(X86_EFLAGS_ID);
214}
215
216static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
217{
218 unsigned long lo, hi;
219
220 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
221 return;
222
223 /* Disable processor serial number: */
224
225 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
226 lo |= 0x200000;
227 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
228
229 printk(KERN_NOTICE "CPU serial number disabled.\n");
230 clear_cpu_cap(c, X86_FEATURE_PN);
231
232 /* Disabling the serial number may affect the cpuid level */
233 c->cpuid_level = cpuid_eax(0);
234}
235
236static int __init x86_serial_nr_setup(char *s)
237{
238 disable_x86_serial_nr = 0;
239 return 1;
240}
241__setup("serialnumber", x86_serial_nr_setup);
242#else
243static inline int flag_is_changeable_p(u32 flag)
244{
245 return 1;
246}
247/* Probe for the CPUID instruction */
248static inline int have_cpuid_p(void)
249{
250 return 1;
251}
252static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
253{
254}
255#endif
256
257static int disable_smep __cpuinitdata;
258static __init int setup_disable_smep(char *arg)
259{
260 disable_smep = 1;
261 return 1;
262}
263__setup("nosmep", setup_disable_smep);
264
265static __cpuinit void setup_smep(struct cpuinfo_x86 *c)
266{
267 if (cpu_has(c, X86_FEATURE_SMEP)) {
268 if (unlikely(disable_smep)) {
269 setup_clear_cpu_cap(X86_FEATURE_SMEP);
270 clear_in_cr4(X86_CR4_SMEP);
271 } else
272 set_in_cr4(X86_CR4_SMEP);
273 }
274}
275
276/*
277 * Some CPU features depend on higher CPUID levels, which may not always
278 * be available due to CPUID level capping or broken virtualization
279 * software. Add those features to this table to auto-disable them.
280 */
281struct cpuid_dependent_feature {
282 u32 feature;
283 u32 level;
284};
285
286static const struct cpuid_dependent_feature __cpuinitconst
287cpuid_dependent_features[] = {
288 { X86_FEATURE_MWAIT, 0x00000005 },
289 { X86_FEATURE_DCA, 0x00000009 },
290 { X86_FEATURE_XSAVE, 0x0000000d },
291 { 0, 0 }
292};
293
294static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
295{
296 const struct cpuid_dependent_feature *df;
297
298 for (df = cpuid_dependent_features; df->feature; df++) {
299
300 if (!cpu_has(c, df->feature))
301 continue;
302 /*
303 * Note: cpuid_level is set to -1 if unavailable, but
304 * extended_extended_level is set to 0 if unavailable
305 * and the legitimate extended levels are all negative
306 * when signed; hence the weird messing around with
307 * signs here...
308 */
309 if (!((s32)df->level < 0 ?
310 (u32)df->level > (u32)c->extended_cpuid_level :
311 (s32)df->level > (s32)c->cpuid_level))
312 continue;
313
314 clear_cpu_cap(c, df->feature);
315 if (!warn)
316 continue;
317
318 printk(KERN_WARNING
319 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
320 x86_cap_flags[df->feature], df->level);
321 }
322}
323
324/*
325 * Naming convention should be: <Name> [(<Codename>)]
326 * This table only is used unless init_<vendor>() below doesn't set it;
327 * in particular, if CPUID levels 0x80000002..4 are supported, this
328 * isn't used
329 */
330
331/* Look up CPU names by table lookup. */
332static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c)
333{
334 const struct cpu_model_info *info;
335
336 if (c->x86_model >= 16)
337 return NULL; /* Range check */
338
339 if (!this_cpu)
340 return NULL;
341
342 info = this_cpu->c_models;
343
344 while (info && info->family) {
345 if (info->family == c->x86)
346 return info->model_names[c->x86_model];
347 info++;
348 }
349 return NULL; /* Not found */
350}
351
352__u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata;
353__u32 cpu_caps_set[NCAPINTS] __cpuinitdata;
354
355void load_percpu_segment(int cpu)
356{
357#ifdef CONFIG_X86_32
358 loadsegment(fs, __KERNEL_PERCPU);
359#else
360 loadsegment(gs, 0);
361 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
362#endif
363 load_stack_canary_segment();
364}
365
366/*
367 * Current gdt points %fs at the "master" per-cpu area: after this,
368 * it's on the real one.
369 */
370void switch_to_new_gdt(int cpu)
371{
372 struct desc_ptr gdt_descr;
373
374 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
375 gdt_descr.size = GDT_SIZE - 1;
376 load_gdt(&gdt_descr);
377 /* Reload the per-cpu base */
378
379 load_percpu_segment(cpu);
380}
381
382static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {};
383
384static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
385{
386 unsigned int *v;
387 char *p, *q;
388
389 if (c->extended_cpuid_level < 0x80000004)
390 return;
391
392 v = (unsigned int *)c->x86_model_id;
393 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
394 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
395 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
396 c->x86_model_id[48] = 0;
397
398 /*
399 * Intel chips right-justify this string for some dumb reason;
400 * undo that brain damage:
401 */
402 p = q = &c->x86_model_id[0];
403 while (*p == ' ')
404 p++;
405 if (p != q) {
406 while (*p)
407 *q++ = *p++;
408 while (q <= &c->x86_model_id[48])
409 *q++ = '\0'; /* Zero-pad the rest */
410 }
411}
412
413void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
414{
415 unsigned int n, dummy, ebx, ecx, edx, l2size;
416
417 n = c->extended_cpuid_level;
418
419 if (n >= 0x80000005) {
420 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
421 c->x86_cache_size = (ecx>>24) + (edx>>24);
422#ifdef CONFIG_X86_64
423 /* On K8 L1 TLB is inclusive, so don't count it */
424 c->x86_tlbsize = 0;
425#endif
426 }
427
428 if (n < 0x80000006) /* Some chips just has a large L1. */
429 return;
430
431 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
432 l2size = ecx >> 16;
433
434#ifdef CONFIG_X86_64
435 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
436#else
437 /* do processor-specific cache resizing */
438 if (this_cpu->c_size_cache)
439 l2size = this_cpu->c_size_cache(c, l2size);
440
441 /* Allow user to override all this if necessary. */
442 if (cachesize_override != -1)
443 l2size = cachesize_override;
444
445 if (l2size == 0)
446 return; /* Again, no L2 cache is possible */
447#endif
448
449 c->x86_cache_size = l2size;
450}
451
452void __cpuinit detect_ht(struct cpuinfo_x86 *c)
453{
454#ifdef CONFIG_X86_HT
455 u32 eax, ebx, ecx, edx;
456 int index_msb, core_bits;
457 static bool printed;
458
459 if (!cpu_has(c, X86_FEATURE_HT))
460 return;
461
462 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
463 goto out;
464
465 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
466 return;
467
468 cpuid(1, &eax, &ebx, &ecx, &edx);
469
470 smp_num_siblings = (ebx & 0xff0000) >> 16;
471
472 if (smp_num_siblings == 1) {
473 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
474 goto out;
475 }
476
477 if (smp_num_siblings <= 1)
478 goto out;
479
480 index_msb = get_count_order(smp_num_siblings);
481 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
482
483 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
484
485 index_msb = get_count_order(smp_num_siblings);
486
487 core_bits = get_count_order(c->x86_max_cores);
488
489 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
490 ((1 << core_bits) - 1);
491
492out:
493 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
494 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
495 c->phys_proc_id);
496 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
497 c->cpu_core_id);
498 printed = 1;
499 }
500#endif
501}
502
503static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
504{
505 char *v = c->x86_vendor_id;
506 int i;
507
508 for (i = 0; i < X86_VENDOR_NUM; i++) {
509 if (!cpu_devs[i])
510 break;
511
512 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
513 (cpu_devs[i]->c_ident[1] &&
514 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
515
516 this_cpu = cpu_devs[i];
517 c->x86_vendor = this_cpu->c_x86_vendor;
518 return;
519 }
520 }
521
522 printk_once(KERN_ERR
523 "CPU: vendor_id '%s' unknown, using generic init.\n" \
524 "CPU: Your system may be unstable.\n", v);
525
526 c->x86_vendor = X86_VENDOR_UNKNOWN;
527 this_cpu = &default_cpu;
528}
529
530void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
531{
532 /* Get vendor name */
533 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
534 (unsigned int *)&c->x86_vendor_id[0],
535 (unsigned int *)&c->x86_vendor_id[8],
536 (unsigned int *)&c->x86_vendor_id[4]);
537
538 c->x86 = 4;
539 /* Intel-defined flags: level 0x00000001 */
540 if (c->cpuid_level >= 0x00000001) {
541 u32 junk, tfms, cap0, misc;
542
543 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
544 c->x86 = (tfms >> 8) & 0xf;
545 c->x86_model = (tfms >> 4) & 0xf;
546 c->x86_mask = tfms & 0xf;
547
548 if (c->x86 == 0xf)
549 c->x86 += (tfms >> 20) & 0xff;
550 if (c->x86 >= 0x6)
551 c->x86_model += ((tfms >> 16) & 0xf) << 4;
552
553 if (cap0 & (1<<19)) {
554 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
555 c->x86_cache_alignment = c->x86_clflush_size;
556 }
557 }
558}
559
560void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
561{
562 u32 tfms, xlvl;
563 u32 ebx;
564
565 /* Intel-defined flags: level 0x00000001 */
566 if (c->cpuid_level >= 0x00000001) {
567 u32 capability, excap;
568
569 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
570 c->x86_capability[0] = capability;
571 c->x86_capability[4] = excap;
572 }
573
574 /* Additional Intel-defined flags: level 0x00000007 */
575 if (c->cpuid_level >= 0x00000007) {
576 u32 eax, ebx, ecx, edx;
577
578 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
579
580 c->x86_capability[9] = ebx;
581 }
582
583 /* AMD-defined flags: level 0x80000001 */
584 xlvl = cpuid_eax(0x80000000);
585 c->extended_cpuid_level = xlvl;
586
587 if ((xlvl & 0xffff0000) == 0x80000000) {
588 if (xlvl >= 0x80000001) {
589 c->x86_capability[1] = cpuid_edx(0x80000001);
590 c->x86_capability[6] = cpuid_ecx(0x80000001);
591 }
592 }
593
594 if (c->extended_cpuid_level >= 0x80000008) {
595 u32 eax = cpuid_eax(0x80000008);
596
597 c->x86_virt_bits = (eax >> 8) & 0xff;
598 c->x86_phys_bits = eax & 0xff;
599 }
600#ifdef CONFIG_X86_32
601 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
602 c->x86_phys_bits = 36;
603#endif
604
605 if (c->extended_cpuid_level >= 0x80000007)
606 c->x86_power = cpuid_edx(0x80000007);
607
608 init_scattered_cpuid_features(c);
609}
610
611static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
612{
613#ifdef CONFIG_X86_32
614 int i;
615
616 /*
617 * First of all, decide if this is a 486 or higher
618 * It's a 486 if we can modify the AC flag
619 */
620 if (flag_is_changeable_p(X86_EFLAGS_AC))
621 c->x86 = 4;
622 else
623 c->x86 = 3;
624
625 for (i = 0; i < X86_VENDOR_NUM; i++)
626 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
627 c->x86_vendor_id[0] = 0;
628 cpu_devs[i]->c_identify(c);
629 if (c->x86_vendor_id[0]) {
630 get_cpu_vendor(c);
631 break;
632 }
633 }
634#endif
635}
636
637/*
638 * Do minimum CPU detection early.
639 * Fields really needed: vendor, cpuid_level, family, model, mask,
640 * cache alignment.
641 * The others are not touched to avoid unwanted side effects.
642 *
643 * WARNING: this function is only called on the BP. Don't add code here
644 * that is supposed to run on all CPUs.
645 */
646static void __init early_identify_cpu(struct cpuinfo_x86 *c)
647{
648#ifdef CONFIG_X86_64
649 c->x86_clflush_size = 64;
650 c->x86_phys_bits = 36;
651 c->x86_virt_bits = 48;
652#else
653 c->x86_clflush_size = 32;
654 c->x86_phys_bits = 32;
655 c->x86_virt_bits = 32;
656#endif
657 c->x86_cache_alignment = c->x86_clflush_size;
658
659 memset(&c->x86_capability, 0, sizeof c->x86_capability);
660 c->extended_cpuid_level = 0;
661
662 if (!have_cpuid_p())
663 identify_cpu_without_cpuid(c);
664
665 /* cyrix could have cpuid enabled via c_identify()*/
666 if (!have_cpuid_p())
667 return;
668
669 cpu_detect(c);
670
671 get_cpu_vendor(c);
672
673 get_cpu_cap(c);
674
675 if (this_cpu->c_early_init)
676 this_cpu->c_early_init(c);
677
678#ifdef CONFIG_SMP
679 c->cpu_index = 0;
680#endif
681 filter_cpuid_features(c, false);
682
683 setup_smep(c);
684}
685
686void __init early_cpu_init(void)
687{
688 const struct cpu_dev *const *cdev;
689 int count = 0;
690
691#ifdef CONFIG_PROCESSOR_SELECT
692 printk(KERN_INFO "KERNEL supported cpus:\n");
693#endif
694
695 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
696 const struct cpu_dev *cpudev = *cdev;
697
698 if (count >= X86_VENDOR_NUM)
699 break;
700 cpu_devs[count] = cpudev;
701 count++;
702
703#ifdef CONFIG_PROCESSOR_SELECT
704 {
705 unsigned int j;
706
707 for (j = 0; j < 2; j++) {
708 if (!cpudev->c_ident[j])
709 continue;
710 printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
711 cpudev->c_ident[j]);
712 }
713 }
714#endif
715 }
716 early_identify_cpu(&boot_cpu_data);
717}
718
719/*
720 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
721 * unfortunately, that's not true in practice because of early VIA
722 * chips and (more importantly) broken virtualizers that are not easy
723 * to detect. In the latter case it doesn't even *fail* reliably, so
724 * probing for it doesn't even work. Disable it completely on 32-bit
725 * unless we can find a reliable way to detect all the broken cases.
726 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
727 */
728static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
729{
730#ifdef CONFIG_X86_32
731 clear_cpu_cap(c, X86_FEATURE_NOPL);
732#else
733 set_cpu_cap(c, X86_FEATURE_NOPL);
734#endif
735}
736
737static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
738{
739 c->extended_cpuid_level = 0;
740
741 if (!have_cpuid_p())
742 identify_cpu_without_cpuid(c);
743
744 /* cyrix could have cpuid enabled via c_identify()*/
745 if (!have_cpuid_p())
746 return;
747
748 cpu_detect(c);
749
750 get_cpu_vendor(c);
751
752 get_cpu_cap(c);
753
754 if (c->cpuid_level >= 0x00000001) {
755 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
756#ifdef CONFIG_X86_32
757# ifdef CONFIG_X86_HT
758 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
759# else
760 c->apicid = c->initial_apicid;
761# endif
762#endif
763
764#ifdef CONFIG_X86_HT
765 c->phys_proc_id = c->initial_apicid;
766#endif
767 }
768
769 setup_smep(c);
770
771 get_model_name(c); /* Default name */
772
773 detect_nopl(c);
774}
775
776/*
777 * This does the hard work of actually picking apart the CPU stuff...
778 */
779static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
780{
781 int i;
782
783 c->loops_per_jiffy = loops_per_jiffy;
784 c->x86_cache_size = -1;
785 c->x86_vendor = X86_VENDOR_UNKNOWN;
786 c->x86_model = c->x86_mask = 0; /* So far unknown... */
787 c->x86_vendor_id[0] = '\0'; /* Unset */
788 c->x86_model_id[0] = '\0'; /* Unset */
789 c->x86_max_cores = 1;
790 c->x86_coreid_bits = 0;
791#ifdef CONFIG_X86_64
792 c->x86_clflush_size = 64;
793 c->x86_phys_bits = 36;
794 c->x86_virt_bits = 48;
795#else
796 c->cpuid_level = -1; /* CPUID not detected */
797 c->x86_clflush_size = 32;
798 c->x86_phys_bits = 32;
799 c->x86_virt_bits = 32;
800#endif
801 c->x86_cache_alignment = c->x86_clflush_size;
802 memset(&c->x86_capability, 0, sizeof c->x86_capability);
803
804 generic_identify(c);
805
806 if (this_cpu->c_identify)
807 this_cpu->c_identify(c);
808
809 /* Clear/Set all flags overriden by options, after probe */
810 for (i = 0; i < NCAPINTS; i++) {
811 c->x86_capability[i] &= ~cpu_caps_cleared[i];
812 c->x86_capability[i] |= cpu_caps_set[i];
813 }
814
815#ifdef CONFIG_X86_64
816 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
817#endif
818
819 /*
820 * Vendor-specific initialization. In this section we
821 * canonicalize the feature flags, meaning if there are
822 * features a certain CPU supports which CPUID doesn't
823 * tell us, CPUID claiming incorrect flags, or other bugs,
824 * we handle them here.
825 *
826 * At the end of this section, c->x86_capability better
827 * indicate the features this CPU genuinely supports!
828 */
829 if (this_cpu->c_init)
830 this_cpu->c_init(c);
831
832 /* Disable the PN if appropriate */
833 squash_the_stupid_serial_number(c);
834
835 /*
836 * The vendor-specific functions might have changed features.
837 * Now we do "generic changes."
838 */
839
840 /* Filter out anything that depends on CPUID levels we don't have */
841 filter_cpuid_features(c, true);
842
843 /* If the model name is still unset, do table lookup. */
844 if (!c->x86_model_id[0]) {
845 const char *p;
846 p = table_lookup_model(c);
847 if (p)
848 strcpy(c->x86_model_id, p);
849 else
850 /* Last resort... */
851 sprintf(c->x86_model_id, "%02x/%02x",
852 c->x86, c->x86_model);
853 }
854
855#ifdef CONFIG_X86_64
856 detect_ht(c);
857#endif
858
859 init_hypervisor(c);
860
861 /*
862 * Clear/Set all flags overriden by options, need do it
863 * before following smp all cpus cap AND.
864 */
865 for (i = 0; i < NCAPINTS; i++) {
866 c->x86_capability[i] &= ~cpu_caps_cleared[i];
867 c->x86_capability[i] |= cpu_caps_set[i];
868 }
869
870 /*
871 * On SMP, boot_cpu_data holds the common feature set between
872 * all CPUs; so make sure that we indicate which features are
873 * common between the CPUs. The first time this routine gets
874 * executed, c == &boot_cpu_data.
875 */
876 if (c != &boot_cpu_data) {
877 /* AND the already accumulated flags with these */
878 for (i = 0; i < NCAPINTS; i++)
879 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
880 }
881
882 /* Init Machine Check Exception if available. */
883 mcheck_cpu_init(c);
884
885 select_idle_routine(c);
886
887#ifdef CONFIG_NUMA
888 numa_add_cpu(smp_processor_id());
889#endif
890}
891
892#ifdef CONFIG_X86_64
893static void vgetcpu_set_mode(void)
894{
895 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
896 vgetcpu_mode = VGETCPU_RDTSCP;
897 else
898 vgetcpu_mode = VGETCPU_LSL;
899}
900#endif
901
902void __init identify_boot_cpu(void)
903{
904 identify_cpu(&boot_cpu_data);
905 init_amd_e400_c1e_mask();
906#ifdef CONFIG_X86_32
907 sysenter_setup();
908 enable_sep_cpu();
909#else
910 vgetcpu_set_mode();
911#endif
912}
913
914void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
915{
916 BUG_ON(c == &boot_cpu_data);
917 identify_cpu(c);
918#ifdef CONFIG_X86_32
919 enable_sep_cpu();
920#endif
921 mtrr_ap_init();
922}
923
924struct msr_range {
925 unsigned min;
926 unsigned max;
927};
928
929static const struct msr_range msr_range_array[] __cpuinitconst = {
930 { 0x00000000, 0x00000418},
931 { 0xc0000000, 0xc000040b},
932 { 0xc0010000, 0xc0010142},
933 { 0xc0011000, 0xc001103b},
934};
935
936static void __cpuinit print_cpu_msr(void)
937{
938 unsigned index_min, index_max;
939 unsigned index;
940 u64 val;
941 int i;
942
943 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
944 index_min = msr_range_array[i].min;
945 index_max = msr_range_array[i].max;
946
947 for (index = index_min; index < index_max; index++) {
948 if (rdmsrl_amd_safe(index, &val))
949 continue;
950 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
951 }
952 }
953}
954
955static int show_msr __cpuinitdata;
956
957static __init int setup_show_msr(char *arg)
958{
959 int num;
960
961 get_option(&arg, &num);
962
963 if (num > 0)
964 show_msr = num;
965 return 1;
966}
967__setup("show_msr=", setup_show_msr);
968
969static __init int setup_noclflush(char *arg)
970{
971 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
972 return 1;
973}
974__setup("noclflush", setup_noclflush);
975
976void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
977{
978 const char *vendor = NULL;
979
980 if (c->x86_vendor < X86_VENDOR_NUM) {
981 vendor = this_cpu->c_vendor;
982 } else {
983 if (c->cpuid_level >= 0)
984 vendor = c->x86_vendor_id;
985 }
986
987 if (vendor && !strstr(c->x86_model_id, vendor))
988 printk(KERN_CONT "%s ", vendor);
989
990 if (c->x86_model_id[0])
991 printk(KERN_CONT "%s", c->x86_model_id);
992 else
993 printk(KERN_CONT "%d86", c->x86);
994
995 if (c->x86_mask || c->cpuid_level >= 0)
996 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
997 else
998 printk(KERN_CONT "\n");
999
1000#ifdef CONFIG_SMP
1001 if (c->cpu_index < show_msr)
1002 print_cpu_msr();
1003#else
1004 if (show_msr)
1005 print_cpu_msr();
1006#endif
1007}
1008
1009static __init int setup_disablecpuid(char *arg)
1010{
1011 int bit;
1012
1013 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1014 setup_clear_cpu_cap(bit);
1015 else
1016 return 0;
1017
1018 return 1;
1019}
1020__setup("clearcpuid=", setup_disablecpuid);
1021
1022#ifdef CONFIG_X86_64
1023struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1024
1025DEFINE_PER_CPU_FIRST(union irq_stack_union,
1026 irq_stack_union) __aligned(PAGE_SIZE);
1027
1028/*
1029 * The following four percpu variables are hot. Align current_task to
1030 * cacheline size such that all four fall in the same cacheline.
1031 */
1032DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1033 &init_task;
1034EXPORT_PER_CPU_SYMBOL(current_task);
1035
1036DEFINE_PER_CPU(unsigned long, kernel_stack) =
1037 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
1038EXPORT_PER_CPU_SYMBOL(kernel_stack);
1039
1040DEFINE_PER_CPU(char *, irq_stack_ptr) =
1041 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1042
1043DEFINE_PER_CPU(unsigned int, irq_count) = -1;
1044
1045/*
1046 * Special IST stacks which the CPU switches to when it calls
1047 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1048 * limit), all of them are 4K, except the debug stack which
1049 * is 8K.
1050 */
1051static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1052 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1053 [DEBUG_STACK - 1] = DEBUG_STKSZ
1054};
1055
1056static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1057 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1058
1059/* May not be marked __init: used by software suspend */
1060void syscall_init(void)
1061{
1062 /*
1063 * LSTAR and STAR live in a bit strange symbiosis.
1064 * They both write to the same internal register. STAR allows to
1065 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1066 */
1067 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
1068 wrmsrl(MSR_LSTAR, system_call);
1069 wrmsrl(MSR_CSTAR, ignore_sysret);
1070
1071#ifdef CONFIG_IA32_EMULATION
1072 syscall32_cpu_init();
1073#endif
1074
1075 /* Flags to clear on syscall */
1076 wrmsrl(MSR_SYSCALL_MASK,
1077 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
1078}
1079
1080unsigned long kernel_eflags;
1081
1082/*
1083 * Copies of the original ist values from the tss are only accessed during
1084 * debugging, no special alignment required.
1085 */
1086DEFINE_PER_CPU(struct orig_ist, orig_ist);
1087
1088#else /* CONFIG_X86_64 */
1089
1090DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1091EXPORT_PER_CPU_SYMBOL(current_task);
1092
1093#ifdef CONFIG_CC_STACKPROTECTOR
1094DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1095#endif
1096
1097/* Make sure %fs and %gs are initialized properly in idle threads */
1098struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
1099{
1100 memset(regs, 0, sizeof(struct pt_regs));
1101 regs->fs = __KERNEL_PERCPU;
1102 regs->gs = __KERNEL_STACK_CANARY;
1103
1104 return regs;
1105}
1106#endif /* CONFIG_X86_64 */
1107
1108/*
1109 * Clear all 6 debug registers:
1110 */
1111static void clear_all_debug_regs(void)
1112{
1113 int i;
1114
1115 for (i = 0; i < 8; i++) {
1116 /* Ignore db4, db5 */
1117 if ((i == 4) || (i == 5))
1118 continue;
1119
1120 set_debugreg(0, i);
1121 }
1122}
1123
1124#ifdef CONFIG_KGDB
1125/*
1126 * Restore debug regs if using kgdbwait and you have a kernel debugger
1127 * connection established.
1128 */
1129static void dbg_restore_debug_regs(void)
1130{
1131 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1132 arch_kgdb_ops.correct_hw_break();
1133}
1134#else /* ! CONFIG_KGDB */
1135#define dbg_restore_debug_regs()
1136#endif /* ! CONFIG_KGDB */
1137
1138/*
1139 * cpu_init() initializes state that is per-CPU. Some data is already
1140 * initialized (naturally) in the bootstrap process, such as the GDT
1141 * and IDT. We reload them nevertheless, this function acts as a
1142 * 'CPU state barrier', nothing should get across.
1143 * A lot of state is already set up in PDA init for 64 bit
1144 */
1145#ifdef CONFIG_X86_64
1146
1147void __cpuinit cpu_init(void)
1148{
1149 struct orig_ist *oist;
1150 struct task_struct *me;
1151 struct tss_struct *t;
1152 unsigned long v;
1153 int cpu;
1154 int i;
1155
1156 cpu = stack_smp_processor_id();
1157 t = &per_cpu(init_tss, cpu);
1158 oist = &per_cpu(orig_ist, cpu);
1159
1160#ifdef CONFIG_NUMA
1161 if (cpu != 0 && percpu_read(numa_node) == 0 &&
1162 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1163 set_numa_node(early_cpu_to_node(cpu));
1164#endif
1165
1166 me = current;
1167
1168 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1169 panic("CPU#%d already initialized!\n", cpu);
1170
1171 pr_debug("Initializing CPU#%d\n", cpu);
1172
1173 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1174
1175 /*
1176 * Initialize the per-CPU GDT with the boot GDT,
1177 * and set up the GDT descriptor:
1178 */
1179
1180 switch_to_new_gdt(cpu);
1181 loadsegment(fs, 0);
1182
1183 load_idt((const struct desc_ptr *)&idt_descr);
1184
1185 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1186 syscall_init();
1187
1188 wrmsrl(MSR_FS_BASE, 0);
1189 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1190 barrier();
1191
1192 x86_configure_nx();
1193 if (cpu != 0)
1194 enable_x2apic();
1195
1196 /*
1197 * set up and load the per-CPU TSS
1198 */
1199 if (!oist->ist[0]) {
1200 char *estacks = per_cpu(exception_stacks, cpu);
1201
1202 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1203 estacks += exception_stack_sizes[v];
1204 oist->ist[v] = t->x86_tss.ist[v] =
1205 (unsigned long)estacks;
1206 }
1207 }
1208
1209 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1210
1211 /*
1212 * <= is required because the CPU will access up to
1213 * 8 bits beyond the end of the IO permission bitmap.
1214 */
1215 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1216 t->io_bitmap[i] = ~0UL;
1217
1218 atomic_inc(&init_mm.mm_count);
1219 me->active_mm = &init_mm;
1220 BUG_ON(me->mm);
1221 enter_lazy_tlb(&init_mm, me);
1222
1223 load_sp0(t, ¤t->thread);
1224 set_tss_desc(cpu, t);
1225 load_TR_desc();
1226 load_LDT(&init_mm.context);
1227
1228 clear_all_debug_regs();
1229 dbg_restore_debug_regs();
1230
1231 fpu_init();
1232 xsave_init();
1233
1234 raw_local_save_flags(kernel_eflags);
1235
1236 if (is_uv_system())
1237 uv_cpu_init();
1238}
1239
1240#else
1241
1242void __cpuinit cpu_init(void)
1243{
1244 int cpu = smp_processor_id();
1245 struct task_struct *curr = current;
1246 struct tss_struct *t = &per_cpu(init_tss, cpu);
1247 struct thread_struct *thread = &curr->thread;
1248
1249 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1250 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1251 for (;;)
1252 local_irq_enable();
1253 }
1254
1255 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1256
1257 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1258 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1259
1260 load_idt(&idt_descr);
1261 switch_to_new_gdt(cpu);
1262
1263 /*
1264 * Set up and load the per-CPU TSS and LDT
1265 */
1266 atomic_inc(&init_mm.mm_count);
1267 curr->active_mm = &init_mm;
1268 BUG_ON(curr->mm);
1269 enter_lazy_tlb(&init_mm, curr);
1270
1271 load_sp0(t, thread);
1272 set_tss_desc(cpu, t);
1273 load_TR_desc();
1274 load_LDT(&init_mm.context);
1275
1276 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1277
1278#ifdef CONFIG_DOUBLEFAULT
1279 /* Set up doublefault TSS pointer in the GDT */
1280 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1281#endif
1282
1283 clear_all_debug_regs();
1284 dbg_restore_debug_regs();
1285
1286 fpu_init();
1287 xsave_init();
1288}
1289#endif