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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 *
6 * Right now, I am very wasteful with the buffers. I allocate memory
7 * pages and then divide them into 2K frame buffers. This way I know I
8 * have buffers large enough to hold one frame within one buffer descriptor.
9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
10 * will be much more memory efficient and will easily handle lots of
11 * small packets.
12 *
13 * Much better multiple PHY support by Magnus Damm.
14 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 *
16 * Support for FEC controller of ColdFire processors.
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 *
19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
21 *
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
23 */
24
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/string.h>
28#include <linux/pm_runtime.h>
29#include <linux/ptrace.h>
30#include <linux/errno.h>
31#include <linux/ioport.h>
32#include <linux/slab.h>
33#include <linux/interrupt.h>
34#include <linux/delay.h>
35#include <linux/netdevice.h>
36#include <linux/etherdevice.h>
37#include <linux/skbuff.h>
38#include <linux/in.h>
39#include <linux/ip.h>
40#include <net/ip.h>
41#include <net/tso.h>
42#include <linux/tcp.h>
43#include <linux/udp.h>
44#include <linux/icmp.h>
45#include <linux/spinlock.h>
46#include <linux/workqueue.h>
47#include <linux/bitops.h>
48#include <linux/io.h>
49#include <linux/irq.h>
50#include <linux/clk.h>
51#include <linux/platform_device.h>
52#include <linux/mdio.h>
53#include <linux/phy.h>
54#include <linux/fec.h>
55#include <linux/of.h>
56#include <linux/of_device.h>
57#include <linux/of_gpio.h>
58#include <linux/of_mdio.h>
59#include <linux/of_net.h>
60#include <linux/regulator/consumer.h>
61#include <linux/if_vlan.h>
62#include <linux/pinctrl/consumer.h>
63#include <linux/prefetch.h>
64#include <soc/imx/cpuidle.h>
65
66#include <asm/cacheflush.h>
67
68#include "fec.h"
69
70static void set_multicast_list(struct net_device *ndev);
71static void fec_enet_itr_coal_init(struct net_device *ndev);
72
73#define DRIVER_NAME "fec"
74
75#define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
76
77/* Pause frame feild and FIFO threshold */
78#define FEC_ENET_FCE (1 << 5)
79#define FEC_ENET_RSEM_V 0x84
80#define FEC_ENET_RSFL_V 16
81#define FEC_ENET_RAEM_V 0x8
82#define FEC_ENET_RAFL_V 0x8
83#define FEC_ENET_OPD_V 0xFFF0
84#define FEC_MDIO_PM_TIMEOUT 100 /* ms */
85
86static struct platform_device_id fec_devtype[] = {
87 {
88 /* keep it for coldfire */
89 .name = DRIVER_NAME,
90 .driver_data = 0,
91 }, {
92 .name = "imx25-fec",
93 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR,
94 }, {
95 .name = "imx27-fec",
96 .driver_data = FEC_QUIRK_MIB_CLEAR,
97 }, {
98 .name = "imx28-fec",
99 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
100 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC,
101 }, {
102 .name = "imx6q-fec",
103 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
104 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
105 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
106 FEC_QUIRK_HAS_RACC,
107 }, {
108 .name = "mvf600-fec",
109 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
110 }, {
111 .name = "imx6sx-fec",
112 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
113 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
114 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
115 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
116 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE,
117 }, {
118 .name = "imx6ul-fec",
119 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
120 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
121 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
122 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
123 FEC_QUIRK_HAS_COALESCE,
124 }, {
125 /* sentinel */
126 }
127};
128MODULE_DEVICE_TABLE(platform, fec_devtype);
129
130enum imx_fec_type {
131 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
132 IMX27_FEC, /* runs on i.mx27/35/51 */
133 IMX28_FEC,
134 IMX6Q_FEC,
135 MVF600_FEC,
136 IMX6SX_FEC,
137 IMX6UL_FEC,
138};
139
140static const struct of_device_id fec_dt_ids[] = {
141 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
142 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
143 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
144 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
145 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
146 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
147 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
148 { /* sentinel */ }
149};
150MODULE_DEVICE_TABLE(of, fec_dt_ids);
151
152static unsigned char macaddr[ETH_ALEN];
153module_param_array(macaddr, byte, NULL, 0);
154MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
155
156#if defined(CONFIG_M5272)
157/*
158 * Some hardware gets it MAC address out of local flash memory.
159 * if this is non-zero then assume it is the address to get MAC from.
160 */
161#if defined(CONFIG_NETtel)
162#define FEC_FLASHMAC 0xf0006006
163#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
164#define FEC_FLASHMAC 0xf0006000
165#elif defined(CONFIG_CANCam)
166#define FEC_FLASHMAC 0xf0020000
167#elif defined (CONFIG_M5272C3)
168#define FEC_FLASHMAC (0xffe04000 + 4)
169#elif defined(CONFIG_MOD5272)
170#define FEC_FLASHMAC 0xffc0406b
171#else
172#define FEC_FLASHMAC 0
173#endif
174#endif /* CONFIG_M5272 */
175
176/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
177 *
178 * 2048 byte skbufs are allocated. However, alignment requirements
179 * varies between FEC variants. Worst case is 64, so round down by 64.
180 */
181#define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64))
182#define PKT_MINBUF_SIZE 64
183
184/* FEC receive acceleration */
185#define FEC_RACC_IPDIS (1 << 1)
186#define FEC_RACC_PRODIS (1 << 2)
187#define FEC_RACC_SHIFT16 BIT(7)
188#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
189
190/* MIB Control Register */
191#define FEC_MIB_CTRLSTAT_DISABLE BIT(31)
192
193/*
194 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
195 * size bits. Other FEC hardware does not, so we need to take that into
196 * account when setting it.
197 */
198#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
199 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
200 defined(CONFIG_ARM64)
201#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
202#else
203#define OPT_FRAME_SIZE 0
204#endif
205
206/* FEC MII MMFR bits definition */
207#define FEC_MMFR_ST (1 << 30)
208#define FEC_MMFR_OP_READ (2 << 28)
209#define FEC_MMFR_OP_WRITE (1 << 28)
210#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
211#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
212#define FEC_MMFR_TA (2 << 16)
213#define FEC_MMFR_DATA(v) (v & 0xffff)
214/* FEC ECR bits definition */
215#define FEC_ECR_MAGICEN (1 << 2)
216#define FEC_ECR_SLEEP (1 << 3)
217
218#define FEC_MII_TIMEOUT 30000 /* us */
219
220/* Transmitter timeout */
221#define TX_TIMEOUT (2 * HZ)
222
223#define FEC_PAUSE_FLAG_AUTONEG 0x1
224#define FEC_PAUSE_FLAG_ENABLE 0x2
225#define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
226#define FEC_WOL_FLAG_ENABLE (0x1 << 1)
227#define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
228
229#define COPYBREAK_DEFAULT 256
230
231/* Max number of allowed TCP segments for software TSO */
232#define FEC_MAX_TSO_SEGS 100
233#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
234
235#define IS_TSO_HEADER(txq, addr) \
236 ((addr >= txq->tso_hdrs_dma) && \
237 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
238
239static int mii_cnt;
240
241static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
242 struct bufdesc_prop *bd)
243{
244 return (bdp >= bd->last) ? bd->base
245 : (struct bufdesc *)(((void *)bdp) + bd->dsize);
246}
247
248static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
249 struct bufdesc_prop *bd)
250{
251 return (bdp <= bd->base) ? bd->last
252 : (struct bufdesc *)(((void *)bdp) - bd->dsize);
253}
254
255static int fec_enet_get_bd_index(struct bufdesc *bdp,
256 struct bufdesc_prop *bd)
257{
258 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
259}
260
261static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
262{
263 int entries;
264
265 entries = (((const char *)txq->dirty_tx -
266 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
267
268 return entries >= 0 ? entries : entries + txq->bd.ring_size;
269}
270
271static void swap_buffer(void *bufaddr, int len)
272{
273 int i;
274 unsigned int *buf = bufaddr;
275
276 for (i = 0; i < len; i += 4, buf++)
277 swab32s(buf);
278}
279
280static void swap_buffer2(void *dst_buf, void *src_buf, int len)
281{
282 int i;
283 unsigned int *src = src_buf;
284 unsigned int *dst = dst_buf;
285
286 for (i = 0; i < len; i += 4, src++, dst++)
287 *dst = swab32p(src);
288}
289
290static void fec_dump(struct net_device *ndev)
291{
292 struct fec_enet_private *fep = netdev_priv(ndev);
293 struct bufdesc *bdp;
294 struct fec_enet_priv_tx_q *txq;
295 int index = 0;
296
297 netdev_info(ndev, "TX ring dump\n");
298 pr_info("Nr SC addr len SKB\n");
299
300 txq = fep->tx_queue[0];
301 bdp = txq->bd.base;
302
303 do {
304 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
305 index,
306 bdp == txq->bd.cur ? 'S' : ' ',
307 bdp == txq->dirty_tx ? 'H' : ' ',
308 fec16_to_cpu(bdp->cbd_sc),
309 fec32_to_cpu(bdp->cbd_bufaddr),
310 fec16_to_cpu(bdp->cbd_datlen),
311 txq->tx_skbuff[index]);
312 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
313 index++;
314 } while (bdp != txq->bd.base);
315}
316
317static inline bool is_ipv4_pkt(struct sk_buff *skb)
318{
319 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
320}
321
322static int
323fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
324{
325 /* Only run for packets requiring a checksum. */
326 if (skb->ip_summed != CHECKSUM_PARTIAL)
327 return 0;
328
329 if (unlikely(skb_cow_head(skb, 0)))
330 return -1;
331
332 if (is_ipv4_pkt(skb))
333 ip_hdr(skb)->check = 0;
334 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
335
336 return 0;
337}
338
339static struct bufdesc *
340fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
341 struct sk_buff *skb,
342 struct net_device *ndev)
343{
344 struct fec_enet_private *fep = netdev_priv(ndev);
345 struct bufdesc *bdp = txq->bd.cur;
346 struct bufdesc_ex *ebdp;
347 int nr_frags = skb_shinfo(skb)->nr_frags;
348 int frag, frag_len;
349 unsigned short status;
350 unsigned int estatus = 0;
351 skb_frag_t *this_frag;
352 unsigned int index;
353 void *bufaddr;
354 dma_addr_t addr;
355 int i;
356
357 for (frag = 0; frag < nr_frags; frag++) {
358 this_frag = &skb_shinfo(skb)->frags[frag];
359 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
360 ebdp = (struct bufdesc_ex *)bdp;
361
362 status = fec16_to_cpu(bdp->cbd_sc);
363 status &= ~BD_ENET_TX_STATS;
364 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
365 frag_len = skb_shinfo(skb)->frags[frag].size;
366
367 /* Handle the last BD specially */
368 if (frag == nr_frags - 1) {
369 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
370 if (fep->bufdesc_ex) {
371 estatus |= BD_ENET_TX_INT;
372 if (unlikely(skb_shinfo(skb)->tx_flags &
373 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
374 estatus |= BD_ENET_TX_TS;
375 }
376 }
377
378 if (fep->bufdesc_ex) {
379 if (fep->quirks & FEC_QUIRK_HAS_AVB)
380 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
381 if (skb->ip_summed == CHECKSUM_PARTIAL)
382 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
383 ebdp->cbd_bdu = 0;
384 ebdp->cbd_esc = cpu_to_fec32(estatus);
385 }
386
387 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
388
389 index = fec_enet_get_bd_index(bdp, &txq->bd);
390 if (((unsigned long) bufaddr) & fep->tx_align ||
391 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
392 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
393 bufaddr = txq->tx_bounce[index];
394
395 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
396 swap_buffer(bufaddr, frag_len);
397 }
398
399 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
400 DMA_TO_DEVICE);
401 if (dma_mapping_error(&fep->pdev->dev, addr)) {
402 if (net_ratelimit())
403 netdev_err(ndev, "Tx DMA memory map failed\n");
404 goto dma_mapping_error;
405 }
406
407 bdp->cbd_bufaddr = cpu_to_fec32(addr);
408 bdp->cbd_datlen = cpu_to_fec16(frag_len);
409 /* Make sure the updates to rest of the descriptor are
410 * performed before transferring ownership.
411 */
412 wmb();
413 bdp->cbd_sc = cpu_to_fec16(status);
414 }
415
416 return bdp;
417dma_mapping_error:
418 bdp = txq->bd.cur;
419 for (i = 0; i < frag; i++) {
420 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
421 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
422 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
423 }
424 return ERR_PTR(-ENOMEM);
425}
426
427static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
428 struct sk_buff *skb, struct net_device *ndev)
429{
430 struct fec_enet_private *fep = netdev_priv(ndev);
431 int nr_frags = skb_shinfo(skb)->nr_frags;
432 struct bufdesc *bdp, *last_bdp;
433 void *bufaddr;
434 dma_addr_t addr;
435 unsigned short status;
436 unsigned short buflen;
437 unsigned int estatus = 0;
438 unsigned int index;
439 int entries_free;
440
441 entries_free = fec_enet_get_free_txdesc_num(txq);
442 if (entries_free < MAX_SKB_FRAGS + 1) {
443 dev_kfree_skb_any(skb);
444 if (net_ratelimit())
445 netdev_err(ndev, "NOT enough BD for SG!\n");
446 return NETDEV_TX_OK;
447 }
448
449 /* Protocol checksum off-load for TCP and UDP. */
450 if (fec_enet_clear_csum(skb, ndev)) {
451 dev_kfree_skb_any(skb);
452 return NETDEV_TX_OK;
453 }
454
455 /* Fill in a Tx ring entry */
456 bdp = txq->bd.cur;
457 last_bdp = bdp;
458 status = fec16_to_cpu(bdp->cbd_sc);
459 status &= ~BD_ENET_TX_STATS;
460
461 /* Set buffer length and buffer pointer */
462 bufaddr = skb->data;
463 buflen = skb_headlen(skb);
464
465 index = fec_enet_get_bd_index(bdp, &txq->bd);
466 if (((unsigned long) bufaddr) & fep->tx_align ||
467 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
468 memcpy(txq->tx_bounce[index], skb->data, buflen);
469 bufaddr = txq->tx_bounce[index];
470
471 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
472 swap_buffer(bufaddr, buflen);
473 }
474
475 /* Push the data cache so the CPM does not get stale memory data. */
476 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
477 if (dma_mapping_error(&fep->pdev->dev, addr)) {
478 dev_kfree_skb_any(skb);
479 if (net_ratelimit())
480 netdev_err(ndev, "Tx DMA memory map failed\n");
481 return NETDEV_TX_OK;
482 }
483
484 if (nr_frags) {
485 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
486 if (IS_ERR(last_bdp)) {
487 dma_unmap_single(&fep->pdev->dev, addr,
488 buflen, DMA_TO_DEVICE);
489 dev_kfree_skb_any(skb);
490 return NETDEV_TX_OK;
491 }
492 } else {
493 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
494 if (fep->bufdesc_ex) {
495 estatus = BD_ENET_TX_INT;
496 if (unlikely(skb_shinfo(skb)->tx_flags &
497 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
498 estatus |= BD_ENET_TX_TS;
499 }
500 }
501 bdp->cbd_bufaddr = cpu_to_fec32(addr);
502 bdp->cbd_datlen = cpu_to_fec16(buflen);
503
504 if (fep->bufdesc_ex) {
505
506 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
507
508 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
509 fep->hwts_tx_en))
510 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
511
512 if (fep->quirks & FEC_QUIRK_HAS_AVB)
513 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
514
515 if (skb->ip_summed == CHECKSUM_PARTIAL)
516 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
517
518 ebdp->cbd_bdu = 0;
519 ebdp->cbd_esc = cpu_to_fec32(estatus);
520 }
521
522 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
523 /* Save skb pointer */
524 txq->tx_skbuff[index] = skb;
525
526 /* Make sure the updates to rest of the descriptor are performed before
527 * transferring ownership.
528 */
529 wmb();
530
531 /* Send it on its way. Tell FEC it's ready, interrupt when done,
532 * it's the last BD of the frame, and to put the CRC on the end.
533 */
534 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
535 bdp->cbd_sc = cpu_to_fec16(status);
536
537 /* If this was the last BD in the ring, start at the beginning again. */
538 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
539
540 skb_tx_timestamp(skb);
541
542 /* Make sure the update to bdp and tx_skbuff are performed before
543 * txq->bd.cur.
544 */
545 wmb();
546 txq->bd.cur = bdp;
547
548 /* Trigger transmission start */
549 writel(0, txq->bd.reg_desc_active);
550
551 return 0;
552}
553
554static int
555fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
556 struct net_device *ndev,
557 struct bufdesc *bdp, int index, char *data,
558 int size, bool last_tcp, bool is_last)
559{
560 struct fec_enet_private *fep = netdev_priv(ndev);
561 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
562 unsigned short status;
563 unsigned int estatus = 0;
564 dma_addr_t addr;
565
566 status = fec16_to_cpu(bdp->cbd_sc);
567 status &= ~BD_ENET_TX_STATS;
568
569 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
570
571 if (((unsigned long) data) & fep->tx_align ||
572 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
573 memcpy(txq->tx_bounce[index], data, size);
574 data = txq->tx_bounce[index];
575
576 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
577 swap_buffer(data, size);
578 }
579
580 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
581 if (dma_mapping_error(&fep->pdev->dev, addr)) {
582 dev_kfree_skb_any(skb);
583 if (net_ratelimit())
584 netdev_err(ndev, "Tx DMA memory map failed\n");
585 return NETDEV_TX_BUSY;
586 }
587
588 bdp->cbd_datlen = cpu_to_fec16(size);
589 bdp->cbd_bufaddr = cpu_to_fec32(addr);
590
591 if (fep->bufdesc_ex) {
592 if (fep->quirks & FEC_QUIRK_HAS_AVB)
593 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
594 if (skb->ip_summed == CHECKSUM_PARTIAL)
595 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
596 ebdp->cbd_bdu = 0;
597 ebdp->cbd_esc = cpu_to_fec32(estatus);
598 }
599
600 /* Handle the last BD specially */
601 if (last_tcp)
602 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
603 if (is_last) {
604 status |= BD_ENET_TX_INTR;
605 if (fep->bufdesc_ex)
606 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
607 }
608
609 bdp->cbd_sc = cpu_to_fec16(status);
610
611 return 0;
612}
613
614static int
615fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
616 struct sk_buff *skb, struct net_device *ndev,
617 struct bufdesc *bdp, int index)
618{
619 struct fec_enet_private *fep = netdev_priv(ndev);
620 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
621 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
622 void *bufaddr;
623 unsigned long dmabuf;
624 unsigned short status;
625 unsigned int estatus = 0;
626
627 status = fec16_to_cpu(bdp->cbd_sc);
628 status &= ~BD_ENET_TX_STATS;
629 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
630
631 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
632 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
633 if (((unsigned long)bufaddr) & fep->tx_align ||
634 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
635 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
636 bufaddr = txq->tx_bounce[index];
637
638 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
639 swap_buffer(bufaddr, hdr_len);
640
641 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
642 hdr_len, DMA_TO_DEVICE);
643 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
644 dev_kfree_skb_any(skb);
645 if (net_ratelimit())
646 netdev_err(ndev, "Tx DMA memory map failed\n");
647 return NETDEV_TX_BUSY;
648 }
649 }
650
651 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
652 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
653
654 if (fep->bufdesc_ex) {
655 if (fep->quirks & FEC_QUIRK_HAS_AVB)
656 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
657 if (skb->ip_summed == CHECKSUM_PARTIAL)
658 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
659 ebdp->cbd_bdu = 0;
660 ebdp->cbd_esc = cpu_to_fec32(estatus);
661 }
662
663 bdp->cbd_sc = cpu_to_fec16(status);
664
665 return 0;
666}
667
668static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
669 struct sk_buff *skb,
670 struct net_device *ndev)
671{
672 struct fec_enet_private *fep = netdev_priv(ndev);
673 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
674 int total_len, data_left;
675 struct bufdesc *bdp = txq->bd.cur;
676 struct tso_t tso;
677 unsigned int index = 0;
678 int ret;
679
680 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
681 dev_kfree_skb_any(skb);
682 if (net_ratelimit())
683 netdev_err(ndev, "NOT enough BD for TSO!\n");
684 return NETDEV_TX_OK;
685 }
686
687 /* Protocol checksum off-load for TCP and UDP. */
688 if (fec_enet_clear_csum(skb, ndev)) {
689 dev_kfree_skb_any(skb);
690 return NETDEV_TX_OK;
691 }
692
693 /* Initialize the TSO handler, and prepare the first payload */
694 tso_start(skb, &tso);
695
696 total_len = skb->len - hdr_len;
697 while (total_len > 0) {
698 char *hdr;
699
700 index = fec_enet_get_bd_index(bdp, &txq->bd);
701 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
702 total_len -= data_left;
703
704 /* prepare packet headers: MAC + IP + TCP */
705 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
706 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
707 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
708 if (ret)
709 goto err_release;
710
711 while (data_left > 0) {
712 int size;
713
714 size = min_t(int, tso.size, data_left);
715 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
716 index = fec_enet_get_bd_index(bdp, &txq->bd);
717 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
718 bdp, index,
719 tso.data, size,
720 size == data_left,
721 total_len == 0);
722 if (ret)
723 goto err_release;
724
725 data_left -= size;
726 tso_build_data(skb, &tso, size);
727 }
728
729 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
730 }
731
732 /* Save skb pointer */
733 txq->tx_skbuff[index] = skb;
734
735 skb_tx_timestamp(skb);
736 txq->bd.cur = bdp;
737
738 /* Trigger transmission start */
739 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
740 !readl(txq->bd.reg_desc_active) ||
741 !readl(txq->bd.reg_desc_active) ||
742 !readl(txq->bd.reg_desc_active) ||
743 !readl(txq->bd.reg_desc_active))
744 writel(0, txq->bd.reg_desc_active);
745
746 return 0;
747
748err_release:
749 /* TODO: Release all used data descriptors for TSO */
750 return ret;
751}
752
753static netdev_tx_t
754fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
755{
756 struct fec_enet_private *fep = netdev_priv(ndev);
757 int entries_free;
758 unsigned short queue;
759 struct fec_enet_priv_tx_q *txq;
760 struct netdev_queue *nq;
761 int ret;
762
763 queue = skb_get_queue_mapping(skb);
764 txq = fep->tx_queue[queue];
765 nq = netdev_get_tx_queue(ndev, queue);
766
767 if (skb_is_gso(skb))
768 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
769 else
770 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
771 if (ret)
772 return ret;
773
774 entries_free = fec_enet_get_free_txdesc_num(txq);
775 if (entries_free <= txq->tx_stop_threshold)
776 netif_tx_stop_queue(nq);
777
778 return NETDEV_TX_OK;
779}
780
781/* Init RX & TX buffer descriptors
782 */
783static void fec_enet_bd_init(struct net_device *dev)
784{
785 struct fec_enet_private *fep = netdev_priv(dev);
786 struct fec_enet_priv_tx_q *txq;
787 struct fec_enet_priv_rx_q *rxq;
788 struct bufdesc *bdp;
789 unsigned int i;
790 unsigned int q;
791
792 for (q = 0; q < fep->num_rx_queues; q++) {
793 /* Initialize the receive buffer descriptors. */
794 rxq = fep->rx_queue[q];
795 bdp = rxq->bd.base;
796
797 for (i = 0; i < rxq->bd.ring_size; i++) {
798
799 /* Initialize the BD for every fragment in the page. */
800 if (bdp->cbd_bufaddr)
801 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
802 else
803 bdp->cbd_sc = cpu_to_fec16(0);
804 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
805 }
806
807 /* Set the last buffer to wrap */
808 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
809 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
810
811 rxq->bd.cur = rxq->bd.base;
812 }
813
814 for (q = 0; q < fep->num_tx_queues; q++) {
815 /* ...and the same for transmit */
816 txq = fep->tx_queue[q];
817 bdp = txq->bd.base;
818 txq->bd.cur = bdp;
819
820 for (i = 0; i < txq->bd.ring_size; i++) {
821 /* Initialize the BD for every fragment in the page. */
822 bdp->cbd_sc = cpu_to_fec16(0);
823 if (bdp->cbd_bufaddr &&
824 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
825 dma_unmap_single(&fep->pdev->dev,
826 fec32_to_cpu(bdp->cbd_bufaddr),
827 fec16_to_cpu(bdp->cbd_datlen),
828 DMA_TO_DEVICE);
829 if (txq->tx_skbuff[i]) {
830 dev_kfree_skb_any(txq->tx_skbuff[i]);
831 txq->tx_skbuff[i] = NULL;
832 }
833 bdp->cbd_bufaddr = cpu_to_fec32(0);
834 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
835 }
836
837 /* Set the last buffer to wrap */
838 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
839 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
840 txq->dirty_tx = bdp;
841 }
842}
843
844static void fec_enet_active_rxring(struct net_device *ndev)
845{
846 struct fec_enet_private *fep = netdev_priv(ndev);
847 int i;
848
849 for (i = 0; i < fep->num_rx_queues; i++)
850 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
851}
852
853static void fec_enet_enable_ring(struct net_device *ndev)
854{
855 struct fec_enet_private *fep = netdev_priv(ndev);
856 struct fec_enet_priv_tx_q *txq;
857 struct fec_enet_priv_rx_q *rxq;
858 int i;
859
860 for (i = 0; i < fep->num_rx_queues; i++) {
861 rxq = fep->rx_queue[i];
862 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
863 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
864
865 /* enable DMA1/2 */
866 if (i)
867 writel(RCMR_MATCHEN | RCMR_CMP(i),
868 fep->hwp + FEC_RCMR(i));
869 }
870
871 for (i = 0; i < fep->num_tx_queues; i++) {
872 txq = fep->tx_queue[i];
873 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
874
875 /* enable DMA1/2 */
876 if (i)
877 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
878 fep->hwp + FEC_DMA_CFG(i));
879 }
880}
881
882static void fec_enet_reset_skb(struct net_device *ndev)
883{
884 struct fec_enet_private *fep = netdev_priv(ndev);
885 struct fec_enet_priv_tx_q *txq;
886 int i, j;
887
888 for (i = 0; i < fep->num_tx_queues; i++) {
889 txq = fep->tx_queue[i];
890
891 for (j = 0; j < txq->bd.ring_size; j++) {
892 if (txq->tx_skbuff[j]) {
893 dev_kfree_skb_any(txq->tx_skbuff[j]);
894 txq->tx_skbuff[j] = NULL;
895 }
896 }
897 }
898}
899
900/*
901 * This function is called to start or restart the FEC during a link
902 * change, transmit timeout, or to reconfigure the FEC. The network
903 * packet processing for this device must be stopped before this call.
904 */
905static void
906fec_restart(struct net_device *ndev)
907{
908 struct fec_enet_private *fep = netdev_priv(ndev);
909 u32 val;
910 u32 temp_mac[2];
911 u32 rcntl = OPT_FRAME_SIZE | 0x04;
912 u32 ecntl = 0x2; /* ETHEREN */
913
914 /* Whack a reset. We should wait for this.
915 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
916 * instead of reset MAC itself.
917 */
918 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
919 writel(0, fep->hwp + FEC_ECNTRL);
920 } else {
921 writel(1, fep->hwp + FEC_ECNTRL);
922 udelay(10);
923 }
924
925 /*
926 * enet-mac reset will reset mac address registers too,
927 * so need to reconfigure it.
928 */
929 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
930 writel((__force u32)cpu_to_be32(temp_mac[0]),
931 fep->hwp + FEC_ADDR_LOW);
932 writel((__force u32)cpu_to_be32(temp_mac[1]),
933 fep->hwp + FEC_ADDR_HIGH);
934
935 /* Clear any outstanding interrupt. */
936 writel(0xffffffff, fep->hwp + FEC_IEVENT);
937
938 fec_enet_bd_init(ndev);
939
940 fec_enet_enable_ring(ndev);
941
942 /* Reset tx SKB buffers. */
943 fec_enet_reset_skb(ndev);
944
945 /* Enable MII mode */
946 if (fep->full_duplex == DUPLEX_FULL) {
947 /* FD enable */
948 writel(0x04, fep->hwp + FEC_X_CNTRL);
949 } else {
950 /* No Rcv on Xmit */
951 rcntl |= 0x02;
952 writel(0x0, fep->hwp + FEC_X_CNTRL);
953 }
954
955 /* Set MII speed */
956 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
957
958#if !defined(CONFIG_M5272)
959 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
960 val = readl(fep->hwp + FEC_RACC);
961 /* align IP header */
962 val |= FEC_RACC_SHIFT16;
963 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
964 /* set RX checksum */
965 val |= FEC_RACC_OPTIONS;
966 else
967 val &= ~FEC_RACC_OPTIONS;
968 writel(val, fep->hwp + FEC_RACC);
969 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
970 }
971#endif
972
973 /*
974 * The phy interface and speed need to get configured
975 * differently on enet-mac.
976 */
977 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
978 /* Enable flow control and length check */
979 rcntl |= 0x40000000 | 0x00000020;
980
981 /* RGMII, RMII or MII */
982 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
983 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
984 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
985 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
986 rcntl |= (1 << 6);
987 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
988 rcntl |= (1 << 8);
989 else
990 rcntl &= ~(1 << 8);
991
992 /* 1G, 100M or 10M */
993 if (ndev->phydev) {
994 if (ndev->phydev->speed == SPEED_1000)
995 ecntl |= (1 << 5);
996 else if (ndev->phydev->speed == SPEED_100)
997 rcntl &= ~(1 << 9);
998 else
999 rcntl |= (1 << 9);
1000 }
1001 } else {
1002#ifdef FEC_MIIGSK_ENR
1003 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1004 u32 cfgr;
1005 /* disable the gasket and wait */
1006 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1007 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1008 udelay(1);
1009
1010 /*
1011 * configure the gasket:
1012 * RMII, 50 MHz, no loopback, no echo
1013 * MII, 25 MHz, no loopback, no echo
1014 */
1015 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1016 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1017 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1018 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1019 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1020
1021 /* re-enable the gasket */
1022 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1023 }
1024#endif
1025 }
1026
1027#if !defined(CONFIG_M5272)
1028 /* enable pause frame*/
1029 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1030 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1031 ndev->phydev && ndev->phydev->pause)) {
1032 rcntl |= FEC_ENET_FCE;
1033
1034 /* set FIFO threshold parameter to reduce overrun */
1035 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1036 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1037 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1038 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1039
1040 /* OPD */
1041 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1042 } else {
1043 rcntl &= ~FEC_ENET_FCE;
1044 }
1045#endif /* !defined(CONFIG_M5272) */
1046
1047 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1048
1049 /* Setup multicast filter. */
1050 set_multicast_list(ndev);
1051#ifndef CONFIG_M5272
1052 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1053 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1054#endif
1055
1056 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1057 /* enable ENET endian swap */
1058 ecntl |= (1 << 8);
1059 /* enable ENET store and forward mode */
1060 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1061 }
1062
1063 if (fep->bufdesc_ex)
1064 ecntl |= (1 << 4);
1065
1066#ifndef CONFIG_M5272
1067 /* Enable the MIB statistic event counters */
1068 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1069#endif
1070
1071 /* And last, enable the transmit and receive processing */
1072 writel(ecntl, fep->hwp + FEC_ECNTRL);
1073 fec_enet_active_rxring(ndev);
1074
1075 if (fep->bufdesc_ex)
1076 fec_ptp_start_cyclecounter(ndev);
1077
1078 /* Enable interrupts we wish to service */
1079 if (fep->link)
1080 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1081 else
1082 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1083
1084 /* Init the interrupt coalescing */
1085 fec_enet_itr_coal_init(ndev);
1086
1087}
1088
1089static void
1090fec_stop(struct net_device *ndev)
1091{
1092 struct fec_enet_private *fep = netdev_priv(ndev);
1093 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1094 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1095 u32 val;
1096
1097 /* We cannot expect a graceful transmit stop without link !!! */
1098 if (fep->link) {
1099 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1100 udelay(10);
1101 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1102 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1103 }
1104
1105 /* Whack a reset. We should wait for this.
1106 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1107 * instead of reset MAC itself.
1108 */
1109 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1110 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1111 writel(0, fep->hwp + FEC_ECNTRL);
1112 } else {
1113 writel(1, fep->hwp + FEC_ECNTRL);
1114 udelay(10);
1115 }
1116 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1117 } else {
1118 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1119 val = readl(fep->hwp + FEC_ECNTRL);
1120 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1121 writel(val, fep->hwp + FEC_ECNTRL);
1122
1123 if (pdata && pdata->sleep_mode_enable)
1124 pdata->sleep_mode_enable(true);
1125 }
1126 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1127
1128 /* We have to keep ENET enabled to have MII interrupt stay working */
1129 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1130 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1131 writel(2, fep->hwp + FEC_ECNTRL);
1132 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1133 }
1134}
1135
1136
1137static void
1138fec_timeout(struct net_device *ndev)
1139{
1140 struct fec_enet_private *fep = netdev_priv(ndev);
1141
1142 fec_dump(ndev);
1143
1144 ndev->stats.tx_errors++;
1145
1146 schedule_work(&fep->tx_timeout_work);
1147}
1148
1149static void fec_enet_timeout_work(struct work_struct *work)
1150{
1151 struct fec_enet_private *fep =
1152 container_of(work, struct fec_enet_private, tx_timeout_work);
1153 struct net_device *ndev = fep->netdev;
1154
1155 rtnl_lock();
1156 if (netif_device_present(ndev) || netif_running(ndev)) {
1157 napi_disable(&fep->napi);
1158 netif_tx_lock_bh(ndev);
1159 fec_restart(ndev);
1160 netif_wake_queue(ndev);
1161 netif_tx_unlock_bh(ndev);
1162 napi_enable(&fep->napi);
1163 }
1164 rtnl_unlock();
1165}
1166
1167static void
1168fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1169 struct skb_shared_hwtstamps *hwtstamps)
1170{
1171 unsigned long flags;
1172 u64 ns;
1173
1174 spin_lock_irqsave(&fep->tmreg_lock, flags);
1175 ns = timecounter_cyc2time(&fep->tc, ts);
1176 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1177
1178 memset(hwtstamps, 0, sizeof(*hwtstamps));
1179 hwtstamps->hwtstamp = ns_to_ktime(ns);
1180}
1181
1182static void
1183fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1184{
1185 struct fec_enet_private *fep;
1186 struct bufdesc *bdp;
1187 unsigned short status;
1188 struct sk_buff *skb;
1189 struct fec_enet_priv_tx_q *txq;
1190 struct netdev_queue *nq;
1191 int index = 0;
1192 int entries_free;
1193
1194 fep = netdev_priv(ndev);
1195
1196 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1197
1198 txq = fep->tx_queue[queue_id];
1199 /* get next bdp of dirty_tx */
1200 nq = netdev_get_tx_queue(ndev, queue_id);
1201 bdp = txq->dirty_tx;
1202
1203 /* get next bdp of dirty_tx */
1204 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1205
1206 while (bdp != READ_ONCE(txq->bd.cur)) {
1207 /* Order the load of bd.cur and cbd_sc */
1208 rmb();
1209 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1210 if (status & BD_ENET_TX_READY)
1211 break;
1212
1213 index = fec_enet_get_bd_index(bdp, &txq->bd);
1214
1215 skb = txq->tx_skbuff[index];
1216 txq->tx_skbuff[index] = NULL;
1217 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1218 dma_unmap_single(&fep->pdev->dev,
1219 fec32_to_cpu(bdp->cbd_bufaddr),
1220 fec16_to_cpu(bdp->cbd_datlen),
1221 DMA_TO_DEVICE);
1222 bdp->cbd_bufaddr = cpu_to_fec32(0);
1223 if (!skb)
1224 goto skb_done;
1225
1226 /* Check for errors. */
1227 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1228 BD_ENET_TX_RL | BD_ENET_TX_UN |
1229 BD_ENET_TX_CSL)) {
1230 ndev->stats.tx_errors++;
1231 if (status & BD_ENET_TX_HB) /* No heartbeat */
1232 ndev->stats.tx_heartbeat_errors++;
1233 if (status & BD_ENET_TX_LC) /* Late collision */
1234 ndev->stats.tx_window_errors++;
1235 if (status & BD_ENET_TX_RL) /* Retrans limit */
1236 ndev->stats.tx_aborted_errors++;
1237 if (status & BD_ENET_TX_UN) /* Underrun */
1238 ndev->stats.tx_fifo_errors++;
1239 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1240 ndev->stats.tx_carrier_errors++;
1241 } else {
1242 ndev->stats.tx_packets++;
1243 ndev->stats.tx_bytes += skb->len;
1244 }
1245
1246 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1247 fep->bufdesc_ex) {
1248 struct skb_shared_hwtstamps shhwtstamps;
1249 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1250
1251 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1252 skb_tstamp_tx(skb, &shhwtstamps);
1253 }
1254
1255 /* Deferred means some collisions occurred during transmit,
1256 * but we eventually sent the packet OK.
1257 */
1258 if (status & BD_ENET_TX_DEF)
1259 ndev->stats.collisions++;
1260
1261 /* Free the sk buffer associated with this last transmit */
1262 dev_kfree_skb_any(skb);
1263skb_done:
1264 /* Make sure the update to bdp and tx_skbuff are performed
1265 * before dirty_tx
1266 */
1267 wmb();
1268 txq->dirty_tx = bdp;
1269
1270 /* Update pointer to next buffer descriptor to be transmitted */
1271 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1272
1273 /* Since we have freed up a buffer, the ring is no longer full
1274 */
1275 if (netif_queue_stopped(ndev)) {
1276 entries_free = fec_enet_get_free_txdesc_num(txq);
1277 if (entries_free >= txq->tx_wake_threshold)
1278 netif_tx_wake_queue(nq);
1279 }
1280 }
1281
1282 /* ERR006358: Keep the transmitter going */
1283 if (bdp != txq->bd.cur &&
1284 readl(txq->bd.reg_desc_active) == 0)
1285 writel(0, txq->bd.reg_desc_active);
1286}
1287
1288static void
1289fec_enet_tx(struct net_device *ndev)
1290{
1291 struct fec_enet_private *fep = netdev_priv(ndev);
1292 u16 queue_id;
1293 /* First process class A queue, then Class B and Best Effort queue */
1294 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1295 clear_bit(queue_id, &fep->work_tx);
1296 fec_enet_tx_queue(ndev, queue_id);
1297 }
1298 return;
1299}
1300
1301static int
1302fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1303{
1304 struct fec_enet_private *fep = netdev_priv(ndev);
1305 int off;
1306
1307 off = ((unsigned long)skb->data) & fep->rx_align;
1308 if (off)
1309 skb_reserve(skb, fep->rx_align + 1 - off);
1310
1311 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1312 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1313 if (net_ratelimit())
1314 netdev_err(ndev, "Rx DMA memory map failed\n");
1315 return -ENOMEM;
1316 }
1317
1318 return 0;
1319}
1320
1321static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1322 struct bufdesc *bdp, u32 length, bool swap)
1323{
1324 struct fec_enet_private *fep = netdev_priv(ndev);
1325 struct sk_buff *new_skb;
1326
1327 if (length > fep->rx_copybreak)
1328 return false;
1329
1330 new_skb = netdev_alloc_skb(ndev, length);
1331 if (!new_skb)
1332 return false;
1333
1334 dma_sync_single_for_cpu(&fep->pdev->dev,
1335 fec32_to_cpu(bdp->cbd_bufaddr),
1336 FEC_ENET_RX_FRSIZE - fep->rx_align,
1337 DMA_FROM_DEVICE);
1338 if (!swap)
1339 memcpy(new_skb->data, (*skb)->data, length);
1340 else
1341 swap_buffer2(new_skb->data, (*skb)->data, length);
1342 *skb = new_skb;
1343
1344 return true;
1345}
1346
1347/* During a receive, the bd_rx.cur points to the current incoming buffer.
1348 * When we update through the ring, if the next incoming buffer has
1349 * not been given to the system, we just set the empty indicator,
1350 * effectively tossing the packet.
1351 */
1352static int
1353fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1354{
1355 struct fec_enet_private *fep = netdev_priv(ndev);
1356 struct fec_enet_priv_rx_q *rxq;
1357 struct bufdesc *bdp;
1358 unsigned short status;
1359 struct sk_buff *skb_new = NULL;
1360 struct sk_buff *skb;
1361 ushort pkt_len;
1362 __u8 *data;
1363 int pkt_received = 0;
1364 struct bufdesc_ex *ebdp = NULL;
1365 bool vlan_packet_rcvd = false;
1366 u16 vlan_tag;
1367 int index = 0;
1368 bool is_copybreak;
1369 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1370
1371#ifdef CONFIG_M532x
1372 flush_cache_all();
1373#endif
1374 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1375 rxq = fep->rx_queue[queue_id];
1376
1377 /* First, grab all of the stats for the incoming packet.
1378 * These get messed up if we get called due to a busy condition.
1379 */
1380 bdp = rxq->bd.cur;
1381
1382 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1383
1384 if (pkt_received >= budget)
1385 break;
1386 pkt_received++;
1387
1388 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1389
1390 /* Check for errors. */
1391 status ^= BD_ENET_RX_LAST;
1392 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1393 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1394 BD_ENET_RX_CL)) {
1395 ndev->stats.rx_errors++;
1396 if (status & BD_ENET_RX_OV) {
1397 /* FIFO overrun */
1398 ndev->stats.rx_fifo_errors++;
1399 goto rx_processing_done;
1400 }
1401 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1402 | BD_ENET_RX_LAST)) {
1403 /* Frame too long or too short. */
1404 ndev->stats.rx_length_errors++;
1405 if (status & BD_ENET_RX_LAST)
1406 netdev_err(ndev, "rcv is not +last\n");
1407 }
1408 if (status & BD_ENET_RX_CR) /* CRC Error */
1409 ndev->stats.rx_crc_errors++;
1410 /* Report late collisions as a frame error. */
1411 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1412 ndev->stats.rx_frame_errors++;
1413 goto rx_processing_done;
1414 }
1415
1416 /* Process the incoming frame. */
1417 ndev->stats.rx_packets++;
1418 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1419 ndev->stats.rx_bytes += pkt_len;
1420
1421 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1422 skb = rxq->rx_skbuff[index];
1423
1424 /* The packet length includes FCS, but we don't want to
1425 * include that when passing upstream as it messes up
1426 * bridging applications.
1427 */
1428 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1429 need_swap);
1430 if (!is_copybreak) {
1431 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1432 if (unlikely(!skb_new)) {
1433 ndev->stats.rx_dropped++;
1434 goto rx_processing_done;
1435 }
1436 dma_unmap_single(&fep->pdev->dev,
1437 fec32_to_cpu(bdp->cbd_bufaddr),
1438 FEC_ENET_RX_FRSIZE - fep->rx_align,
1439 DMA_FROM_DEVICE);
1440 }
1441
1442 prefetch(skb->data - NET_IP_ALIGN);
1443 skb_put(skb, pkt_len - 4);
1444 data = skb->data;
1445
1446 if (!is_copybreak && need_swap)
1447 swap_buffer(data, pkt_len);
1448
1449#if !defined(CONFIG_M5272)
1450 if (fep->quirks & FEC_QUIRK_HAS_RACC)
1451 data = skb_pull_inline(skb, 2);
1452#endif
1453
1454 /* Extract the enhanced buffer descriptor */
1455 ebdp = NULL;
1456 if (fep->bufdesc_ex)
1457 ebdp = (struct bufdesc_ex *)bdp;
1458
1459 /* If this is a VLAN packet remove the VLAN Tag */
1460 vlan_packet_rcvd = false;
1461 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1462 fep->bufdesc_ex &&
1463 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1464 /* Push and remove the vlan tag */
1465 struct vlan_hdr *vlan_header =
1466 (struct vlan_hdr *) (data + ETH_HLEN);
1467 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1468
1469 vlan_packet_rcvd = true;
1470
1471 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1472 skb_pull(skb, VLAN_HLEN);
1473 }
1474
1475 skb->protocol = eth_type_trans(skb, ndev);
1476
1477 /* Get receive timestamp from the skb */
1478 if (fep->hwts_rx_en && fep->bufdesc_ex)
1479 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1480 skb_hwtstamps(skb));
1481
1482 if (fep->bufdesc_ex &&
1483 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1484 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1485 /* don't check it */
1486 skb->ip_summed = CHECKSUM_UNNECESSARY;
1487 } else {
1488 skb_checksum_none_assert(skb);
1489 }
1490 }
1491
1492 /* Handle received VLAN packets */
1493 if (vlan_packet_rcvd)
1494 __vlan_hwaccel_put_tag(skb,
1495 htons(ETH_P_8021Q),
1496 vlan_tag);
1497
1498 napi_gro_receive(&fep->napi, skb);
1499
1500 if (is_copybreak) {
1501 dma_sync_single_for_device(&fep->pdev->dev,
1502 fec32_to_cpu(bdp->cbd_bufaddr),
1503 FEC_ENET_RX_FRSIZE - fep->rx_align,
1504 DMA_FROM_DEVICE);
1505 } else {
1506 rxq->rx_skbuff[index] = skb_new;
1507 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1508 }
1509
1510rx_processing_done:
1511 /* Clear the status flags for this buffer */
1512 status &= ~BD_ENET_RX_STATS;
1513
1514 /* Mark the buffer empty */
1515 status |= BD_ENET_RX_EMPTY;
1516
1517 if (fep->bufdesc_ex) {
1518 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1519
1520 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1521 ebdp->cbd_prot = 0;
1522 ebdp->cbd_bdu = 0;
1523 }
1524 /* Make sure the updates to rest of the descriptor are
1525 * performed before transferring ownership.
1526 */
1527 wmb();
1528 bdp->cbd_sc = cpu_to_fec16(status);
1529
1530 /* Update BD pointer to next entry */
1531 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1532
1533 /* Doing this here will keep the FEC running while we process
1534 * incoming frames. On a heavily loaded network, we should be
1535 * able to keep up at the expense of system resources.
1536 */
1537 writel(0, rxq->bd.reg_desc_active);
1538 }
1539 rxq->bd.cur = bdp;
1540 return pkt_received;
1541}
1542
1543static int
1544fec_enet_rx(struct net_device *ndev, int budget)
1545{
1546 int pkt_received = 0;
1547 u16 queue_id;
1548 struct fec_enet_private *fep = netdev_priv(ndev);
1549
1550 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1551 int ret;
1552
1553 ret = fec_enet_rx_queue(ndev,
1554 budget - pkt_received, queue_id);
1555
1556 if (ret < budget - pkt_received)
1557 clear_bit(queue_id, &fep->work_rx);
1558
1559 pkt_received += ret;
1560 }
1561 return pkt_received;
1562}
1563
1564static bool
1565fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1566{
1567 if (int_events == 0)
1568 return false;
1569
1570 if (int_events & FEC_ENET_RXF_0)
1571 fep->work_rx |= (1 << 2);
1572 if (int_events & FEC_ENET_RXF_1)
1573 fep->work_rx |= (1 << 0);
1574 if (int_events & FEC_ENET_RXF_2)
1575 fep->work_rx |= (1 << 1);
1576
1577 if (int_events & FEC_ENET_TXF_0)
1578 fep->work_tx |= (1 << 2);
1579 if (int_events & FEC_ENET_TXF_1)
1580 fep->work_tx |= (1 << 0);
1581 if (int_events & FEC_ENET_TXF_2)
1582 fep->work_tx |= (1 << 1);
1583
1584 return true;
1585}
1586
1587static irqreturn_t
1588fec_enet_interrupt(int irq, void *dev_id)
1589{
1590 struct net_device *ndev = dev_id;
1591 struct fec_enet_private *fep = netdev_priv(ndev);
1592 uint int_events;
1593 irqreturn_t ret = IRQ_NONE;
1594
1595 int_events = readl(fep->hwp + FEC_IEVENT);
1596 writel(int_events, fep->hwp + FEC_IEVENT);
1597 fec_enet_collect_events(fep, int_events);
1598
1599 if ((fep->work_tx || fep->work_rx) && fep->link) {
1600 ret = IRQ_HANDLED;
1601
1602 if (napi_schedule_prep(&fep->napi)) {
1603 /* Disable the NAPI interrupts */
1604 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK);
1605 __napi_schedule(&fep->napi);
1606 }
1607 }
1608
1609 if (int_events & FEC_ENET_MII) {
1610 ret = IRQ_HANDLED;
1611 complete(&fep->mdio_done);
1612 }
1613 return ret;
1614}
1615
1616static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1617{
1618 struct net_device *ndev = napi->dev;
1619 struct fec_enet_private *fep = netdev_priv(ndev);
1620 int pkts;
1621
1622 pkts = fec_enet_rx(ndev, budget);
1623
1624 fec_enet_tx(ndev);
1625
1626 if (pkts < budget) {
1627 napi_complete_done(napi, pkts);
1628 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1629 }
1630 return pkts;
1631}
1632
1633/* ------------------------------------------------------------------------- */
1634static void fec_get_mac(struct net_device *ndev)
1635{
1636 struct fec_enet_private *fep = netdev_priv(ndev);
1637 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1638 unsigned char *iap, tmpaddr[ETH_ALEN];
1639
1640 /*
1641 * try to get mac address in following order:
1642 *
1643 * 1) module parameter via kernel command line in form
1644 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1645 */
1646 iap = macaddr;
1647
1648 /*
1649 * 2) from device tree data
1650 */
1651 if (!is_valid_ether_addr(iap)) {
1652 struct device_node *np = fep->pdev->dev.of_node;
1653 if (np) {
1654 const char *mac = of_get_mac_address(np);
1655 if (mac)
1656 iap = (unsigned char *) mac;
1657 }
1658 }
1659
1660 /*
1661 * 3) from flash or fuse (via platform data)
1662 */
1663 if (!is_valid_ether_addr(iap)) {
1664#ifdef CONFIG_M5272
1665 if (FEC_FLASHMAC)
1666 iap = (unsigned char *)FEC_FLASHMAC;
1667#else
1668 if (pdata)
1669 iap = (unsigned char *)&pdata->mac;
1670#endif
1671 }
1672
1673 /*
1674 * 4) FEC mac registers set by bootloader
1675 */
1676 if (!is_valid_ether_addr(iap)) {
1677 *((__be32 *) &tmpaddr[0]) =
1678 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1679 *((__be16 *) &tmpaddr[4]) =
1680 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1681 iap = &tmpaddr[0];
1682 }
1683
1684 /*
1685 * 5) random mac address
1686 */
1687 if (!is_valid_ether_addr(iap)) {
1688 /* Report it and use a random ethernet address instead */
1689 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1690 eth_hw_addr_random(ndev);
1691 netdev_info(ndev, "Using random MAC address: %pM\n",
1692 ndev->dev_addr);
1693 return;
1694 }
1695
1696 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1697
1698 /* Adjust MAC if using macaddr */
1699 if (iap == macaddr)
1700 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1701}
1702
1703/* ------------------------------------------------------------------------- */
1704
1705/*
1706 * Phy section
1707 */
1708static void fec_enet_adjust_link(struct net_device *ndev)
1709{
1710 struct fec_enet_private *fep = netdev_priv(ndev);
1711 struct phy_device *phy_dev = ndev->phydev;
1712 int status_change = 0;
1713
1714 /* Prevent a state halted on mii error */
1715 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1716 phy_dev->state = PHY_RESUMING;
1717 return;
1718 }
1719
1720 /*
1721 * If the netdev is down, or is going down, we're not interested
1722 * in link state events, so just mark our idea of the link as down
1723 * and ignore the event.
1724 */
1725 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1726 fep->link = 0;
1727 } else if (phy_dev->link) {
1728 if (!fep->link) {
1729 fep->link = phy_dev->link;
1730 status_change = 1;
1731 }
1732
1733 if (fep->full_duplex != phy_dev->duplex) {
1734 fep->full_duplex = phy_dev->duplex;
1735 status_change = 1;
1736 }
1737
1738 if (phy_dev->speed != fep->speed) {
1739 fep->speed = phy_dev->speed;
1740 status_change = 1;
1741 }
1742
1743 /* if any of the above changed restart the FEC */
1744 if (status_change) {
1745 napi_disable(&fep->napi);
1746 netif_tx_lock_bh(ndev);
1747 fec_restart(ndev);
1748 netif_wake_queue(ndev);
1749 netif_tx_unlock_bh(ndev);
1750 napi_enable(&fep->napi);
1751 }
1752 } else {
1753 if (fep->link) {
1754 napi_disable(&fep->napi);
1755 netif_tx_lock_bh(ndev);
1756 fec_stop(ndev);
1757 netif_tx_unlock_bh(ndev);
1758 napi_enable(&fep->napi);
1759 fep->link = phy_dev->link;
1760 status_change = 1;
1761 }
1762 }
1763
1764 if (status_change)
1765 phy_print_status(phy_dev);
1766}
1767
1768static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1769{
1770 struct fec_enet_private *fep = bus->priv;
1771 struct device *dev = &fep->pdev->dev;
1772 unsigned long time_left;
1773 int ret = 0;
1774
1775 ret = pm_runtime_get_sync(dev);
1776 if (ret < 0)
1777 return ret;
1778
1779 fep->mii_timeout = 0;
1780 reinit_completion(&fep->mdio_done);
1781
1782 /* start a read op */
1783 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1784 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1785 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1786
1787 /* wait for end of transfer */
1788 time_left = wait_for_completion_timeout(&fep->mdio_done,
1789 usecs_to_jiffies(FEC_MII_TIMEOUT));
1790 if (time_left == 0) {
1791 fep->mii_timeout = 1;
1792 netdev_err(fep->netdev, "MDIO read timeout\n");
1793 ret = -ETIMEDOUT;
1794 goto out;
1795 }
1796
1797 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1798
1799out:
1800 pm_runtime_mark_last_busy(dev);
1801 pm_runtime_put_autosuspend(dev);
1802
1803 return ret;
1804}
1805
1806static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1807 u16 value)
1808{
1809 struct fec_enet_private *fep = bus->priv;
1810 struct device *dev = &fep->pdev->dev;
1811 unsigned long time_left;
1812 int ret;
1813
1814 ret = pm_runtime_get_sync(dev);
1815 if (ret < 0)
1816 return ret;
1817 else
1818 ret = 0;
1819
1820 fep->mii_timeout = 0;
1821 reinit_completion(&fep->mdio_done);
1822
1823 /* start a write op */
1824 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1825 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1826 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1827 fep->hwp + FEC_MII_DATA);
1828
1829 /* wait for end of transfer */
1830 time_left = wait_for_completion_timeout(&fep->mdio_done,
1831 usecs_to_jiffies(FEC_MII_TIMEOUT));
1832 if (time_left == 0) {
1833 fep->mii_timeout = 1;
1834 netdev_err(fep->netdev, "MDIO write timeout\n");
1835 ret = -ETIMEDOUT;
1836 }
1837
1838 pm_runtime_mark_last_busy(dev);
1839 pm_runtime_put_autosuspend(dev);
1840
1841 return ret;
1842}
1843
1844static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1845{
1846 struct fec_enet_private *fep = netdev_priv(ndev);
1847 int ret;
1848
1849 if (enable) {
1850 ret = clk_prepare_enable(fep->clk_ahb);
1851 if (ret)
1852 return ret;
1853
1854 ret = clk_prepare_enable(fep->clk_enet_out);
1855 if (ret)
1856 goto failed_clk_enet_out;
1857
1858 if (fep->clk_ptp) {
1859 mutex_lock(&fep->ptp_clk_mutex);
1860 ret = clk_prepare_enable(fep->clk_ptp);
1861 if (ret) {
1862 mutex_unlock(&fep->ptp_clk_mutex);
1863 goto failed_clk_ptp;
1864 } else {
1865 fep->ptp_clk_on = true;
1866 }
1867 mutex_unlock(&fep->ptp_clk_mutex);
1868 }
1869
1870 ret = clk_prepare_enable(fep->clk_ref);
1871 if (ret)
1872 goto failed_clk_ref;
1873
1874 phy_reset_after_clk_enable(ndev->phydev);
1875 } else {
1876 clk_disable_unprepare(fep->clk_ahb);
1877 clk_disable_unprepare(fep->clk_enet_out);
1878 if (fep->clk_ptp) {
1879 mutex_lock(&fep->ptp_clk_mutex);
1880 clk_disable_unprepare(fep->clk_ptp);
1881 fep->ptp_clk_on = false;
1882 mutex_unlock(&fep->ptp_clk_mutex);
1883 }
1884 clk_disable_unprepare(fep->clk_ref);
1885 }
1886
1887 return 0;
1888
1889failed_clk_ref:
1890 if (fep->clk_ref)
1891 clk_disable_unprepare(fep->clk_ref);
1892failed_clk_ptp:
1893 if (fep->clk_enet_out)
1894 clk_disable_unprepare(fep->clk_enet_out);
1895failed_clk_enet_out:
1896 clk_disable_unprepare(fep->clk_ahb);
1897
1898 return ret;
1899}
1900
1901static int fec_enet_mii_probe(struct net_device *ndev)
1902{
1903 struct fec_enet_private *fep = netdev_priv(ndev);
1904 struct phy_device *phy_dev = NULL;
1905 char mdio_bus_id[MII_BUS_ID_SIZE];
1906 char phy_name[MII_BUS_ID_SIZE + 3];
1907 int phy_id;
1908 int dev_id = fep->dev_id;
1909
1910 if (fep->phy_node) {
1911 phy_dev = of_phy_connect(ndev, fep->phy_node,
1912 &fec_enet_adjust_link, 0,
1913 fep->phy_interface);
1914 if (!phy_dev) {
1915 netdev_err(ndev, "Unable to connect to phy\n");
1916 return -ENODEV;
1917 }
1918 } else {
1919 /* check for attached phy */
1920 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1921 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
1922 continue;
1923 if (dev_id--)
1924 continue;
1925 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1926 break;
1927 }
1928
1929 if (phy_id >= PHY_MAX_ADDR) {
1930 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1931 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1932 phy_id = 0;
1933 }
1934
1935 snprintf(phy_name, sizeof(phy_name),
1936 PHY_ID_FMT, mdio_bus_id, phy_id);
1937 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1938 fep->phy_interface);
1939 }
1940
1941 if (IS_ERR(phy_dev)) {
1942 netdev_err(ndev, "could not attach to PHY\n");
1943 return PTR_ERR(phy_dev);
1944 }
1945
1946 /* mask with MAC supported features */
1947 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1948 phy_dev->supported &= PHY_GBIT_FEATURES;
1949 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1950#if !defined(CONFIG_M5272)
1951 phy_dev->supported |= SUPPORTED_Pause;
1952#endif
1953 }
1954 else
1955 phy_dev->supported &= PHY_BASIC_FEATURES;
1956
1957 phy_dev->advertising = phy_dev->supported;
1958
1959 fep->link = 0;
1960 fep->full_duplex = 0;
1961
1962 phy_attached_info(phy_dev);
1963
1964 return 0;
1965}
1966
1967static int fec_enet_mii_init(struct platform_device *pdev)
1968{
1969 static struct mii_bus *fec0_mii_bus;
1970 struct net_device *ndev = platform_get_drvdata(pdev);
1971 struct fec_enet_private *fep = netdev_priv(ndev);
1972 struct device_node *node;
1973 int err = -ENXIO;
1974 u32 mii_speed, holdtime;
1975
1976 /*
1977 * The i.MX28 dual fec interfaces are not equal.
1978 * Here are the differences:
1979 *
1980 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1981 * - fec0 acts as the 1588 time master while fec1 is slave
1982 * - external phys can only be configured by fec0
1983 *
1984 * That is to say fec1 can not work independently. It only works
1985 * when fec0 is working. The reason behind this design is that the
1986 * second interface is added primarily for Switch mode.
1987 *
1988 * Because of the last point above, both phys are attached on fec0
1989 * mdio interface in board design, and need to be configured by
1990 * fec0 mii_bus.
1991 */
1992 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
1993 /* fec1 uses fec0 mii_bus */
1994 if (mii_cnt && fec0_mii_bus) {
1995 fep->mii_bus = fec0_mii_bus;
1996 mii_cnt++;
1997 return 0;
1998 }
1999 return -ENOENT;
2000 }
2001
2002 fep->mii_timeout = 0;
2003
2004 /*
2005 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
2006 *
2007 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2008 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2009 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2010 * document.
2011 */
2012 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
2013 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2014 mii_speed--;
2015 if (mii_speed > 63) {
2016 dev_err(&pdev->dev,
2017 "fec clock (%lu) too fast to get right mii speed\n",
2018 clk_get_rate(fep->clk_ipg));
2019 err = -EINVAL;
2020 goto err_out;
2021 }
2022
2023 /*
2024 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2025 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2026 * versions are RAZ there, so just ignore the difference and write the
2027 * register always.
2028 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2029 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2030 * output.
2031 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2032 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2033 * holdtime cannot result in a value greater than 3.
2034 */
2035 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2036
2037 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2038
2039 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2040
2041 fep->mii_bus = mdiobus_alloc();
2042 if (fep->mii_bus == NULL) {
2043 err = -ENOMEM;
2044 goto err_out;
2045 }
2046
2047 fep->mii_bus->name = "fec_enet_mii_bus";
2048 fep->mii_bus->read = fec_enet_mdio_read;
2049 fep->mii_bus->write = fec_enet_mdio_write;
2050 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2051 pdev->name, fep->dev_id + 1);
2052 fep->mii_bus->priv = fep;
2053 fep->mii_bus->parent = &pdev->dev;
2054
2055 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2056 if (node) {
2057 err = of_mdiobus_register(fep->mii_bus, node);
2058 of_node_put(node);
2059 } else {
2060 err = mdiobus_register(fep->mii_bus);
2061 }
2062
2063 if (err)
2064 goto err_out_free_mdiobus;
2065
2066 mii_cnt++;
2067
2068 /* save fec0 mii_bus */
2069 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2070 fec0_mii_bus = fep->mii_bus;
2071
2072 return 0;
2073
2074err_out_free_mdiobus:
2075 mdiobus_free(fep->mii_bus);
2076err_out:
2077 return err;
2078}
2079
2080static void fec_enet_mii_remove(struct fec_enet_private *fep)
2081{
2082 if (--mii_cnt == 0) {
2083 mdiobus_unregister(fep->mii_bus);
2084 mdiobus_free(fep->mii_bus);
2085 }
2086}
2087
2088static void fec_enet_get_drvinfo(struct net_device *ndev,
2089 struct ethtool_drvinfo *info)
2090{
2091 struct fec_enet_private *fep = netdev_priv(ndev);
2092
2093 strlcpy(info->driver, fep->pdev->dev.driver->name,
2094 sizeof(info->driver));
2095 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2096 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2097}
2098
2099static int fec_enet_get_regs_len(struct net_device *ndev)
2100{
2101 struct fec_enet_private *fep = netdev_priv(ndev);
2102 struct resource *r;
2103 int s = 0;
2104
2105 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2106 if (r)
2107 s = resource_size(r);
2108
2109 return s;
2110}
2111
2112/* List of registers that can be safety be read to dump them with ethtool */
2113#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2114 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2115 defined(CONFIG_ARM64)
2116static u32 fec_enet_register_offset[] = {
2117 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2118 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2119 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2120 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2121 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2122 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2123 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2124 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2125 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2126 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2127 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2128 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2129 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2130 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2131 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2132 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2133 RMON_T_P_GTE2048, RMON_T_OCTETS,
2134 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2135 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2136 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2137 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2138 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2139 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2140 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2141 RMON_R_P_GTE2048, RMON_R_OCTETS,
2142 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2143 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2144};
2145#else
2146static u32 fec_enet_register_offset[] = {
2147 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2148 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2149 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2150 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2151 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2152 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2153 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2154 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2155 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2156};
2157#endif
2158
2159static void fec_enet_get_regs(struct net_device *ndev,
2160 struct ethtool_regs *regs, void *regbuf)
2161{
2162 struct fec_enet_private *fep = netdev_priv(ndev);
2163 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2164 u32 *buf = (u32 *)regbuf;
2165 u32 i, off;
2166
2167 memset(buf, 0, regs->len);
2168
2169 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2170 off = fec_enet_register_offset[i] / 4;
2171 buf[off] = readl(&theregs[off]);
2172 }
2173}
2174
2175static int fec_enet_get_ts_info(struct net_device *ndev,
2176 struct ethtool_ts_info *info)
2177{
2178 struct fec_enet_private *fep = netdev_priv(ndev);
2179
2180 if (fep->bufdesc_ex) {
2181
2182 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2183 SOF_TIMESTAMPING_RX_SOFTWARE |
2184 SOF_TIMESTAMPING_SOFTWARE |
2185 SOF_TIMESTAMPING_TX_HARDWARE |
2186 SOF_TIMESTAMPING_RX_HARDWARE |
2187 SOF_TIMESTAMPING_RAW_HARDWARE;
2188 if (fep->ptp_clock)
2189 info->phc_index = ptp_clock_index(fep->ptp_clock);
2190 else
2191 info->phc_index = -1;
2192
2193 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2194 (1 << HWTSTAMP_TX_ON);
2195
2196 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2197 (1 << HWTSTAMP_FILTER_ALL);
2198 return 0;
2199 } else {
2200 return ethtool_op_get_ts_info(ndev, info);
2201 }
2202}
2203
2204#if !defined(CONFIG_M5272)
2205
2206static void fec_enet_get_pauseparam(struct net_device *ndev,
2207 struct ethtool_pauseparam *pause)
2208{
2209 struct fec_enet_private *fep = netdev_priv(ndev);
2210
2211 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2212 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2213 pause->rx_pause = pause->tx_pause;
2214}
2215
2216static int fec_enet_set_pauseparam(struct net_device *ndev,
2217 struct ethtool_pauseparam *pause)
2218{
2219 struct fec_enet_private *fep = netdev_priv(ndev);
2220
2221 if (!ndev->phydev)
2222 return -ENODEV;
2223
2224 if (pause->tx_pause != pause->rx_pause) {
2225 netdev_info(ndev,
2226 "hardware only support enable/disable both tx and rx");
2227 return -EINVAL;
2228 }
2229
2230 fep->pause_flag = 0;
2231
2232 /* tx pause must be same as rx pause */
2233 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2234 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2235
2236 if (pause->rx_pause || pause->autoneg) {
2237 ndev->phydev->supported |= ADVERTISED_Pause;
2238 ndev->phydev->advertising |= ADVERTISED_Pause;
2239 } else {
2240 ndev->phydev->supported &= ~ADVERTISED_Pause;
2241 ndev->phydev->advertising &= ~ADVERTISED_Pause;
2242 }
2243
2244 if (pause->autoneg) {
2245 if (netif_running(ndev))
2246 fec_stop(ndev);
2247 phy_start_aneg(ndev->phydev);
2248 }
2249 if (netif_running(ndev)) {
2250 napi_disable(&fep->napi);
2251 netif_tx_lock_bh(ndev);
2252 fec_restart(ndev);
2253 netif_wake_queue(ndev);
2254 netif_tx_unlock_bh(ndev);
2255 napi_enable(&fep->napi);
2256 }
2257
2258 return 0;
2259}
2260
2261static const struct fec_stat {
2262 char name[ETH_GSTRING_LEN];
2263 u16 offset;
2264} fec_stats[] = {
2265 /* RMON TX */
2266 { "tx_dropped", RMON_T_DROP },
2267 { "tx_packets", RMON_T_PACKETS },
2268 { "tx_broadcast", RMON_T_BC_PKT },
2269 { "tx_multicast", RMON_T_MC_PKT },
2270 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2271 { "tx_undersize", RMON_T_UNDERSIZE },
2272 { "tx_oversize", RMON_T_OVERSIZE },
2273 { "tx_fragment", RMON_T_FRAG },
2274 { "tx_jabber", RMON_T_JAB },
2275 { "tx_collision", RMON_T_COL },
2276 { "tx_64byte", RMON_T_P64 },
2277 { "tx_65to127byte", RMON_T_P65TO127 },
2278 { "tx_128to255byte", RMON_T_P128TO255 },
2279 { "tx_256to511byte", RMON_T_P256TO511 },
2280 { "tx_512to1023byte", RMON_T_P512TO1023 },
2281 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2282 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2283 { "tx_octets", RMON_T_OCTETS },
2284
2285 /* IEEE TX */
2286 { "IEEE_tx_drop", IEEE_T_DROP },
2287 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2288 { "IEEE_tx_1col", IEEE_T_1COL },
2289 { "IEEE_tx_mcol", IEEE_T_MCOL },
2290 { "IEEE_tx_def", IEEE_T_DEF },
2291 { "IEEE_tx_lcol", IEEE_T_LCOL },
2292 { "IEEE_tx_excol", IEEE_T_EXCOL },
2293 { "IEEE_tx_macerr", IEEE_T_MACERR },
2294 { "IEEE_tx_cserr", IEEE_T_CSERR },
2295 { "IEEE_tx_sqe", IEEE_T_SQE },
2296 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2297 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2298
2299 /* RMON RX */
2300 { "rx_packets", RMON_R_PACKETS },
2301 { "rx_broadcast", RMON_R_BC_PKT },
2302 { "rx_multicast", RMON_R_MC_PKT },
2303 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2304 { "rx_undersize", RMON_R_UNDERSIZE },
2305 { "rx_oversize", RMON_R_OVERSIZE },
2306 { "rx_fragment", RMON_R_FRAG },
2307 { "rx_jabber", RMON_R_JAB },
2308 { "rx_64byte", RMON_R_P64 },
2309 { "rx_65to127byte", RMON_R_P65TO127 },
2310 { "rx_128to255byte", RMON_R_P128TO255 },
2311 { "rx_256to511byte", RMON_R_P256TO511 },
2312 { "rx_512to1023byte", RMON_R_P512TO1023 },
2313 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2314 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2315 { "rx_octets", RMON_R_OCTETS },
2316
2317 /* IEEE RX */
2318 { "IEEE_rx_drop", IEEE_R_DROP },
2319 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2320 { "IEEE_rx_crc", IEEE_R_CRC },
2321 { "IEEE_rx_align", IEEE_R_ALIGN },
2322 { "IEEE_rx_macerr", IEEE_R_MACERR },
2323 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2324 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2325};
2326
2327#define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64))
2328
2329static void fec_enet_update_ethtool_stats(struct net_device *dev)
2330{
2331 struct fec_enet_private *fep = netdev_priv(dev);
2332 int i;
2333
2334 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2335 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2336}
2337
2338static void fec_enet_get_ethtool_stats(struct net_device *dev,
2339 struct ethtool_stats *stats, u64 *data)
2340{
2341 struct fec_enet_private *fep = netdev_priv(dev);
2342
2343 if (netif_running(dev))
2344 fec_enet_update_ethtool_stats(dev);
2345
2346 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2347}
2348
2349static void fec_enet_get_strings(struct net_device *netdev,
2350 u32 stringset, u8 *data)
2351{
2352 int i;
2353 switch (stringset) {
2354 case ETH_SS_STATS:
2355 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2356 memcpy(data + i * ETH_GSTRING_LEN,
2357 fec_stats[i].name, ETH_GSTRING_LEN);
2358 break;
2359 }
2360}
2361
2362static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2363{
2364 switch (sset) {
2365 case ETH_SS_STATS:
2366 return ARRAY_SIZE(fec_stats);
2367 default:
2368 return -EOPNOTSUPP;
2369 }
2370}
2371
2372static void fec_enet_clear_ethtool_stats(struct net_device *dev)
2373{
2374 struct fec_enet_private *fep = netdev_priv(dev);
2375 int i;
2376
2377 /* Disable MIB statistics counters */
2378 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
2379
2380 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2381 writel(0, fep->hwp + fec_stats[i].offset);
2382
2383 /* Don't disable MIB statistics counters */
2384 writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
2385}
2386
2387#else /* !defined(CONFIG_M5272) */
2388#define FEC_STATS_SIZE 0
2389static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2390{
2391}
2392
2393static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
2394{
2395}
2396#endif /* !defined(CONFIG_M5272) */
2397
2398/* ITR clock source is enet system clock (clk_ahb).
2399 * TCTT unit is cycle_ns * 64 cycle
2400 * So, the ICTT value = X us / (cycle_ns * 64)
2401 */
2402static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2403{
2404 struct fec_enet_private *fep = netdev_priv(ndev);
2405
2406 return us * (fep->itr_clk_rate / 64000) / 1000;
2407}
2408
2409/* Set threshold for interrupt coalescing */
2410static void fec_enet_itr_coal_set(struct net_device *ndev)
2411{
2412 struct fec_enet_private *fep = netdev_priv(ndev);
2413 int rx_itr, tx_itr;
2414
2415 /* Must be greater than zero to avoid unpredictable behavior */
2416 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2417 !fep->tx_time_itr || !fep->tx_pkts_itr)
2418 return;
2419
2420 /* Select enet system clock as Interrupt Coalescing
2421 * timer Clock Source
2422 */
2423 rx_itr = FEC_ITR_CLK_SEL;
2424 tx_itr = FEC_ITR_CLK_SEL;
2425
2426 /* set ICFT and ICTT */
2427 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2428 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2429 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2430 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2431
2432 rx_itr |= FEC_ITR_EN;
2433 tx_itr |= FEC_ITR_EN;
2434
2435 writel(tx_itr, fep->hwp + FEC_TXIC0);
2436 writel(rx_itr, fep->hwp + FEC_RXIC0);
2437 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
2438 writel(tx_itr, fep->hwp + FEC_TXIC1);
2439 writel(rx_itr, fep->hwp + FEC_RXIC1);
2440 writel(tx_itr, fep->hwp + FEC_TXIC2);
2441 writel(rx_itr, fep->hwp + FEC_RXIC2);
2442 }
2443}
2444
2445static int
2446fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2447{
2448 struct fec_enet_private *fep = netdev_priv(ndev);
2449
2450 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2451 return -EOPNOTSUPP;
2452
2453 ec->rx_coalesce_usecs = fep->rx_time_itr;
2454 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2455
2456 ec->tx_coalesce_usecs = fep->tx_time_itr;
2457 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2458
2459 return 0;
2460}
2461
2462static int
2463fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2464{
2465 struct fec_enet_private *fep = netdev_priv(ndev);
2466 unsigned int cycle;
2467
2468 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2469 return -EOPNOTSUPP;
2470
2471 if (ec->rx_max_coalesced_frames > 255) {
2472 pr_err("Rx coalesced frames exceed hardware limitation\n");
2473 return -EINVAL;
2474 }
2475
2476 if (ec->tx_max_coalesced_frames > 255) {
2477 pr_err("Tx coalesced frame exceed hardware limitation\n");
2478 return -EINVAL;
2479 }
2480
2481 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2482 if (cycle > 0xFFFF) {
2483 pr_err("Rx coalesced usec exceed hardware limitation\n");
2484 return -EINVAL;
2485 }
2486
2487 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2488 if (cycle > 0xFFFF) {
2489 pr_err("Rx coalesced usec exceed hardware limitation\n");
2490 return -EINVAL;
2491 }
2492
2493 fep->rx_time_itr = ec->rx_coalesce_usecs;
2494 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2495
2496 fep->tx_time_itr = ec->tx_coalesce_usecs;
2497 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2498
2499 fec_enet_itr_coal_set(ndev);
2500
2501 return 0;
2502}
2503
2504static void fec_enet_itr_coal_init(struct net_device *ndev)
2505{
2506 struct ethtool_coalesce ec;
2507
2508 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2509 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2510
2511 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2512 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2513
2514 fec_enet_set_coalesce(ndev, &ec);
2515}
2516
2517static int fec_enet_get_tunable(struct net_device *netdev,
2518 const struct ethtool_tunable *tuna,
2519 void *data)
2520{
2521 struct fec_enet_private *fep = netdev_priv(netdev);
2522 int ret = 0;
2523
2524 switch (tuna->id) {
2525 case ETHTOOL_RX_COPYBREAK:
2526 *(u32 *)data = fep->rx_copybreak;
2527 break;
2528 default:
2529 ret = -EINVAL;
2530 break;
2531 }
2532
2533 return ret;
2534}
2535
2536static int fec_enet_set_tunable(struct net_device *netdev,
2537 const struct ethtool_tunable *tuna,
2538 const void *data)
2539{
2540 struct fec_enet_private *fep = netdev_priv(netdev);
2541 int ret = 0;
2542
2543 switch (tuna->id) {
2544 case ETHTOOL_RX_COPYBREAK:
2545 fep->rx_copybreak = *(u32 *)data;
2546 break;
2547 default:
2548 ret = -EINVAL;
2549 break;
2550 }
2551
2552 return ret;
2553}
2554
2555static void
2556fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2557{
2558 struct fec_enet_private *fep = netdev_priv(ndev);
2559
2560 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2561 wol->supported = WAKE_MAGIC;
2562 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2563 } else {
2564 wol->supported = wol->wolopts = 0;
2565 }
2566}
2567
2568static int
2569fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2570{
2571 struct fec_enet_private *fep = netdev_priv(ndev);
2572
2573 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2574 return -EINVAL;
2575
2576 if (wol->wolopts & ~WAKE_MAGIC)
2577 return -EINVAL;
2578
2579 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2580 if (device_may_wakeup(&ndev->dev)) {
2581 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2582 if (fep->irq[0] > 0)
2583 enable_irq_wake(fep->irq[0]);
2584 } else {
2585 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2586 if (fep->irq[0] > 0)
2587 disable_irq_wake(fep->irq[0]);
2588 }
2589
2590 return 0;
2591}
2592
2593static const struct ethtool_ops fec_enet_ethtool_ops = {
2594 .get_drvinfo = fec_enet_get_drvinfo,
2595 .get_regs_len = fec_enet_get_regs_len,
2596 .get_regs = fec_enet_get_regs,
2597 .nway_reset = phy_ethtool_nway_reset,
2598 .get_link = ethtool_op_get_link,
2599 .get_coalesce = fec_enet_get_coalesce,
2600 .set_coalesce = fec_enet_set_coalesce,
2601#ifndef CONFIG_M5272
2602 .get_pauseparam = fec_enet_get_pauseparam,
2603 .set_pauseparam = fec_enet_set_pauseparam,
2604 .get_strings = fec_enet_get_strings,
2605 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2606 .get_sset_count = fec_enet_get_sset_count,
2607#endif
2608 .get_ts_info = fec_enet_get_ts_info,
2609 .get_tunable = fec_enet_get_tunable,
2610 .set_tunable = fec_enet_set_tunable,
2611 .get_wol = fec_enet_get_wol,
2612 .set_wol = fec_enet_set_wol,
2613 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2614 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2615};
2616
2617static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2618{
2619 struct fec_enet_private *fep = netdev_priv(ndev);
2620 struct phy_device *phydev = ndev->phydev;
2621
2622 if (!netif_running(ndev))
2623 return -EINVAL;
2624
2625 if (!phydev)
2626 return -ENODEV;
2627
2628 if (fep->bufdesc_ex) {
2629 if (cmd == SIOCSHWTSTAMP)
2630 return fec_ptp_set(ndev, rq);
2631 if (cmd == SIOCGHWTSTAMP)
2632 return fec_ptp_get(ndev, rq);
2633 }
2634
2635 return phy_mii_ioctl(phydev, rq, cmd);
2636}
2637
2638static void fec_enet_free_buffers(struct net_device *ndev)
2639{
2640 struct fec_enet_private *fep = netdev_priv(ndev);
2641 unsigned int i;
2642 struct sk_buff *skb;
2643 struct bufdesc *bdp;
2644 struct fec_enet_priv_tx_q *txq;
2645 struct fec_enet_priv_rx_q *rxq;
2646 unsigned int q;
2647
2648 for (q = 0; q < fep->num_rx_queues; q++) {
2649 rxq = fep->rx_queue[q];
2650 bdp = rxq->bd.base;
2651 for (i = 0; i < rxq->bd.ring_size; i++) {
2652 skb = rxq->rx_skbuff[i];
2653 rxq->rx_skbuff[i] = NULL;
2654 if (skb) {
2655 dma_unmap_single(&fep->pdev->dev,
2656 fec32_to_cpu(bdp->cbd_bufaddr),
2657 FEC_ENET_RX_FRSIZE - fep->rx_align,
2658 DMA_FROM_DEVICE);
2659 dev_kfree_skb(skb);
2660 }
2661 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2662 }
2663 }
2664
2665 for (q = 0; q < fep->num_tx_queues; q++) {
2666 txq = fep->tx_queue[q];
2667 bdp = txq->bd.base;
2668 for (i = 0; i < txq->bd.ring_size; i++) {
2669 kfree(txq->tx_bounce[i]);
2670 txq->tx_bounce[i] = NULL;
2671 skb = txq->tx_skbuff[i];
2672 txq->tx_skbuff[i] = NULL;
2673 dev_kfree_skb(skb);
2674 }
2675 }
2676}
2677
2678static void fec_enet_free_queue(struct net_device *ndev)
2679{
2680 struct fec_enet_private *fep = netdev_priv(ndev);
2681 int i;
2682 struct fec_enet_priv_tx_q *txq;
2683
2684 for (i = 0; i < fep->num_tx_queues; i++)
2685 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2686 txq = fep->tx_queue[i];
2687 dma_free_coherent(&fep->pdev->dev,
2688 txq->bd.ring_size * TSO_HEADER_SIZE,
2689 txq->tso_hdrs,
2690 txq->tso_hdrs_dma);
2691 }
2692
2693 for (i = 0; i < fep->num_rx_queues; i++)
2694 kfree(fep->rx_queue[i]);
2695 for (i = 0; i < fep->num_tx_queues; i++)
2696 kfree(fep->tx_queue[i]);
2697}
2698
2699static int fec_enet_alloc_queue(struct net_device *ndev)
2700{
2701 struct fec_enet_private *fep = netdev_priv(ndev);
2702 int i;
2703 int ret = 0;
2704 struct fec_enet_priv_tx_q *txq;
2705
2706 for (i = 0; i < fep->num_tx_queues; i++) {
2707 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2708 if (!txq) {
2709 ret = -ENOMEM;
2710 goto alloc_failed;
2711 }
2712
2713 fep->tx_queue[i] = txq;
2714 txq->bd.ring_size = TX_RING_SIZE;
2715 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
2716
2717 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2718 txq->tx_wake_threshold =
2719 (txq->bd.ring_size - txq->tx_stop_threshold) / 2;
2720
2721 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev,
2722 txq->bd.ring_size * TSO_HEADER_SIZE,
2723 &txq->tso_hdrs_dma,
2724 GFP_KERNEL);
2725 if (!txq->tso_hdrs) {
2726 ret = -ENOMEM;
2727 goto alloc_failed;
2728 }
2729 }
2730
2731 for (i = 0; i < fep->num_rx_queues; i++) {
2732 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2733 GFP_KERNEL);
2734 if (!fep->rx_queue[i]) {
2735 ret = -ENOMEM;
2736 goto alloc_failed;
2737 }
2738
2739 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2740 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
2741 }
2742 return ret;
2743
2744alloc_failed:
2745 fec_enet_free_queue(ndev);
2746 return ret;
2747}
2748
2749static int
2750fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2751{
2752 struct fec_enet_private *fep = netdev_priv(ndev);
2753 unsigned int i;
2754 struct sk_buff *skb;
2755 struct bufdesc *bdp;
2756 struct fec_enet_priv_rx_q *rxq;
2757
2758 rxq = fep->rx_queue[queue];
2759 bdp = rxq->bd.base;
2760 for (i = 0; i < rxq->bd.ring_size; i++) {
2761 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2762 if (!skb)
2763 goto err_alloc;
2764
2765 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2766 dev_kfree_skb(skb);
2767 goto err_alloc;
2768 }
2769
2770 rxq->rx_skbuff[i] = skb;
2771 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
2772
2773 if (fep->bufdesc_ex) {
2774 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2775 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
2776 }
2777
2778 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2779 }
2780
2781 /* Set the last buffer to wrap. */
2782 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
2783 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2784 return 0;
2785
2786 err_alloc:
2787 fec_enet_free_buffers(ndev);
2788 return -ENOMEM;
2789}
2790
2791static int
2792fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2793{
2794 struct fec_enet_private *fep = netdev_priv(ndev);
2795 unsigned int i;
2796 struct bufdesc *bdp;
2797 struct fec_enet_priv_tx_q *txq;
2798
2799 txq = fep->tx_queue[queue];
2800 bdp = txq->bd.base;
2801 for (i = 0; i < txq->bd.ring_size; i++) {
2802 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2803 if (!txq->tx_bounce[i])
2804 goto err_alloc;
2805
2806 bdp->cbd_sc = cpu_to_fec16(0);
2807 bdp->cbd_bufaddr = cpu_to_fec32(0);
2808
2809 if (fep->bufdesc_ex) {
2810 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2811 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
2812 }
2813
2814 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
2815 }
2816
2817 /* Set the last buffer to wrap. */
2818 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
2819 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2820
2821 return 0;
2822
2823 err_alloc:
2824 fec_enet_free_buffers(ndev);
2825 return -ENOMEM;
2826}
2827
2828static int fec_enet_alloc_buffers(struct net_device *ndev)
2829{
2830 struct fec_enet_private *fep = netdev_priv(ndev);
2831 unsigned int i;
2832
2833 for (i = 0; i < fep->num_rx_queues; i++)
2834 if (fec_enet_alloc_rxq_buffers(ndev, i))
2835 return -ENOMEM;
2836
2837 for (i = 0; i < fep->num_tx_queues; i++)
2838 if (fec_enet_alloc_txq_buffers(ndev, i))
2839 return -ENOMEM;
2840 return 0;
2841}
2842
2843static int
2844fec_enet_open(struct net_device *ndev)
2845{
2846 struct fec_enet_private *fep = netdev_priv(ndev);
2847 int ret;
2848 bool reset_again;
2849
2850 ret = pm_runtime_get_sync(&fep->pdev->dev);
2851 if (ret < 0)
2852 return ret;
2853
2854 pinctrl_pm_select_default_state(&fep->pdev->dev);
2855 ret = fec_enet_clk_enable(ndev, true);
2856 if (ret)
2857 goto clk_enable;
2858
2859 /* During the first fec_enet_open call the PHY isn't probed at this
2860 * point. Therefore the phy_reset_after_clk_enable() call within
2861 * fec_enet_clk_enable() fails. As we need this reset in order to be
2862 * sure the PHY is working correctly we check if we need to reset again
2863 * later when the PHY is probed
2864 */
2865 if (ndev->phydev && ndev->phydev->drv)
2866 reset_again = false;
2867 else
2868 reset_again = true;
2869
2870 /* I should reset the ring buffers here, but I don't yet know
2871 * a simple way to do that.
2872 */
2873
2874 ret = fec_enet_alloc_buffers(ndev);
2875 if (ret)
2876 goto err_enet_alloc;
2877
2878 /* Init MAC prior to mii bus probe */
2879 fec_restart(ndev);
2880
2881 /* Probe and connect to PHY when open the interface */
2882 ret = fec_enet_mii_probe(ndev);
2883 if (ret)
2884 goto err_enet_mii_probe;
2885
2886 /* Call phy_reset_after_clk_enable() again if it failed during
2887 * phy_reset_after_clk_enable() before because the PHY wasn't probed.
2888 */
2889 if (reset_again)
2890 phy_reset_after_clk_enable(ndev->phydev);
2891
2892 if (fep->quirks & FEC_QUIRK_ERR006687)
2893 imx6q_cpuidle_fec_irqs_used();
2894
2895 napi_enable(&fep->napi);
2896 phy_start(ndev->phydev);
2897 netif_tx_start_all_queues(ndev);
2898
2899 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2900 FEC_WOL_FLAG_ENABLE);
2901
2902 return 0;
2903
2904err_enet_mii_probe:
2905 fec_enet_free_buffers(ndev);
2906err_enet_alloc:
2907 fec_enet_clk_enable(ndev, false);
2908clk_enable:
2909 pm_runtime_mark_last_busy(&fep->pdev->dev);
2910 pm_runtime_put_autosuspend(&fep->pdev->dev);
2911 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2912 return ret;
2913}
2914
2915static int
2916fec_enet_close(struct net_device *ndev)
2917{
2918 struct fec_enet_private *fep = netdev_priv(ndev);
2919
2920 phy_stop(ndev->phydev);
2921
2922 if (netif_device_present(ndev)) {
2923 napi_disable(&fep->napi);
2924 netif_tx_disable(ndev);
2925 fec_stop(ndev);
2926 }
2927
2928 phy_disconnect(ndev->phydev);
2929
2930 if (fep->quirks & FEC_QUIRK_ERR006687)
2931 imx6q_cpuidle_fec_irqs_unused();
2932
2933 fec_enet_update_ethtool_stats(ndev);
2934
2935 fec_enet_clk_enable(ndev, false);
2936 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2937 pm_runtime_mark_last_busy(&fep->pdev->dev);
2938 pm_runtime_put_autosuspend(&fep->pdev->dev);
2939
2940 fec_enet_free_buffers(ndev);
2941
2942 return 0;
2943}
2944
2945/* Set or clear the multicast filter for this adaptor.
2946 * Skeleton taken from sunlance driver.
2947 * The CPM Ethernet implementation allows Multicast as well as individual
2948 * MAC address filtering. Some of the drivers check to make sure it is
2949 * a group multicast address, and discard those that are not. I guess I
2950 * will do the same for now, but just remove the test if you want
2951 * individual filtering as well (do the upper net layers want or support
2952 * this kind of feature?).
2953 */
2954
2955#define FEC_HASH_BITS 6 /* #bits in hash */
2956#define CRC32_POLY 0xEDB88320
2957
2958static void set_multicast_list(struct net_device *ndev)
2959{
2960 struct fec_enet_private *fep = netdev_priv(ndev);
2961 struct netdev_hw_addr *ha;
2962 unsigned int i, bit, data, crc, tmp;
2963 unsigned char hash;
2964 unsigned int hash_high = 0, hash_low = 0;
2965
2966 if (ndev->flags & IFF_PROMISC) {
2967 tmp = readl(fep->hwp + FEC_R_CNTRL);
2968 tmp |= 0x8;
2969 writel(tmp, fep->hwp + FEC_R_CNTRL);
2970 return;
2971 }
2972
2973 tmp = readl(fep->hwp + FEC_R_CNTRL);
2974 tmp &= ~0x8;
2975 writel(tmp, fep->hwp + FEC_R_CNTRL);
2976
2977 if (ndev->flags & IFF_ALLMULTI) {
2978 /* Catch all multicast addresses, so set the
2979 * filter to all 1's
2980 */
2981 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2982 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2983
2984 return;
2985 }
2986
2987 /* Add the addresses in hash register */
2988 netdev_for_each_mc_addr(ha, ndev) {
2989 /* calculate crc32 value of mac address */
2990 crc = 0xffffffff;
2991
2992 for (i = 0; i < ndev->addr_len; i++) {
2993 data = ha->addr[i];
2994 for (bit = 0; bit < 8; bit++, data >>= 1) {
2995 crc = (crc >> 1) ^
2996 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2997 }
2998 }
2999
3000 /* only upper 6 bits (FEC_HASH_BITS) are used
3001 * which point to specific bit in the hash registers
3002 */
3003 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
3004
3005 if (hash > 31)
3006 hash_high |= 1 << (hash - 32);
3007 else
3008 hash_low |= 1 << hash;
3009 }
3010
3011 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3012 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3013}
3014
3015/* Set a MAC change in hardware. */
3016static int
3017fec_set_mac_address(struct net_device *ndev, void *p)
3018{
3019 struct fec_enet_private *fep = netdev_priv(ndev);
3020 struct sockaddr *addr = p;
3021
3022 if (addr) {
3023 if (!is_valid_ether_addr(addr->sa_data))
3024 return -EADDRNOTAVAIL;
3025 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3026 }
3027
3028 /* Add netif status check here to avoid system hang in below case:
3029 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3030 * After ethx down, fec all clocks are gated off and then register
3031 * access causes system hang.
3032 */
3033 if (!netif_running(ndev))
3034 return 0;
3035
3036 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3037 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3038 fep->hwp + FEC_ADDR_LOW);
3039 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3040 fep->hwp + FEC_ADDR_HIGH);
3041 return 0;
3042}
3043
3044#ifdef CONFIG_NET_POLL_CONTROLLER
3045/**
3046 * fec_poll_controller - FEC Poll controller function
3047 * @dev: The FEC network adapter
3048 *
3049 * Polled functionality used by netconsole and others in non interrupt mode
3050 *
3051 */
3052static void fec_poll_controller(struct net_device *dev)
3053{
3054 int i;
3055 struct fec_enet_private *fep = netdev_priv(dev);
3056
3057 for (i = 0; i < FEC_IRQ_NUM; i++) {
3058 if (fep->irq[i] > 0) {
3059 disable_irq(fep->irq[i]);
3060 fec_enet_interrupt(fep->irq[i], dev);
3061 enable_irq(fep->irq[i]);
3062 }
3063 }
3064}
3065#endif
3066
3067static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3068 netdev_features_t features)
3069{
3070 struct fec_enet_private *fep = netdev_priv(netdev);
3071 netdev_features_t changed = features ^ netdev->features;
3072
3073 netdev->features = features;
3074
3075 /* Receive checksum has been changed */
3076 if (changed & NETIF_F_RXCSUM) {
3077 if (features & NETIF_F_RXCSUM)
3078 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3079 else
3080 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3081 }
3082}
3083
3084static int fec_set_features(struct net_device *netdev,
3085 netdev_features_t features)
3086{
3087 struct fec_enet_private *fep = netdev_priv(netdev);
3088 netdev_features_t changed = features ^ netdev->features;
3089
3090 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3091 napi_disable(&fep->napi);
3092 netif_tx_lock_bh(netdev);
3093 fec_stop(netdev);
3094 fec_enet_set_netdev_features(netdev, features);
3095 fec_restart(netdev);
3096 netif_tx_wake_all_queues(netdev);
3097 netif_tx_unlock_bh(netdev);
3098 napi_enable(&fep->napi);
3099 } else {
3100 fec_enet_set_netdev_features(netdev, features);
3101 }
3102
3103 return 0;
3104}
3105
3106static const struct net_device_ops fec_netdev_ops = {
3107 .ndo_open = fec_enet_open,
3108 .ndo_stop = fec_enet_close,
3109 .ndo_start_xmit = fec_enet_start_xmit,
3110 .ndo_set_rx_mode = set_multicast_list,
3111 .ndo_validate_addr = eth_validate_addr,
3112 .ndo_tx_timeout = fec_timeout,
3113 .ndo_set_mac_address = fec_set_mac_address,
3114 .ndo_do_ioctl = fec_enet_ioctl,
3115#ifdef CONFIG_NET_POLL_CONTROLLER
3116 .ndo_poll_controller = fec_poll_controller,
3117#endif
3118 .ndo_set_features = fec_set_features,
3119};
3120
3121static const unsigned short offset_des_active_rxq[] = {
3122 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3123};
3124
3125static const unsigned short offset_des_active_txq[] = {
3126 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3127};
3128
3129 /*
3130 * XXX: We need to clean up on failure exits here.
3131 *
3132 */
3133static int fec_enet_init(struct net_device *ndev)
3134{
3135 struct fec_enet_private *fep = netdev_priv(ndev);
3136 struct bufdesc *cbd_base;
3137 dma_addr_t bd_dma;
3138 int bd_size;
3139 unsigned int i;
3140 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3141 sizeof(struct bufdesc);
3142 unsigned dsize_log2 = __fls(dsize);
3143
3144 WARN_ON(dsize != (1 << dsize_log2));
3145#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
3146 fep->rx_align = 0xf;
3147 fep->tx_align = 0xf;
3148#else
3149 fep->rx_align = 0x3;
3150 fep->tx_align = 0x3;
3151#endif
3152
3153 fec_enet_alloc_queue(ndev);
3154
3155 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
3156
3157 /* Allocate memory for buffer descriptors. */
3158 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3159 GFP_KERNEL);
3160 if (!cbd_base) {
3161 return -ENOMEM;
3162 }
3163
3164 memset(cbd_base, 0, bd_size);
3165
3166 /* Get the Ethernet address */
3167 fec_get_mac(ndev);
3168 /* make sure MAC we just acquired is programmed into the hw */
3169 fec_set_mac_address(ndev, NULL);
3170
3171 /* Set receive and transmit descriptor base. */
3172 for (i = 0; i < fep->num_rx_queues; i++) {
3173 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3174 unsigned size = dsize * rxq->bd.ring_size;
3175
3176 rxq->bd.qid = i;
3177 rxq->bd.base = cbd_base;
3178 rxq->bd.cur = cbd_base;
3179 rxq->bd.dma = bd_dma;
3180 rxq->bd.dsize = dsize;
3181 rxq->bd.dsize_log2 = dsize_log2;
3182 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
3183 bd_dma += size;
3184 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3185 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3186 }
3187
3188 for (i = 0; i < fep->num_tx_queues; i++) {
3189 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3190 unsigned size = dsize * txq->bd.ring_size;
3191
3192 txq->bd.qid = i;
3193 txq->bd.base = cbd_base;
3194 txq->bd.cur = cbd_base;
3195 txq->bd.dma = bd_dma;
3196 txq->bd.dsize = dsize;
3197 txq->bd.dsize_log2 = dsize_log2;
3198 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
3199 bd_dma += size;
3200 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3201 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3202 }
3203
3204
3205 /* The FEC Ethernet specific entries in the device structure */
3206 ndev->watchdog_timeo = TX_TIMEOUT;
3207 ndev->netdev_ops = &fec_netdev_ops;
3208 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3209
3210 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3211 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3212
3213 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3214 /* enable hw VLAN support */
3215 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3216
3217 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3218 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3219
3220 /* enable hw accelerator */
3221 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3222 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3223 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3224 }
3225
3226 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3227 fep->tx_align = 0;
3228 fep->rx_align = 0x3f;
3229 }
3230
3231 ndev->hw_features = ndev->features;
3232
3233 fec_restart(ndev);
3234
3235 if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
3236 fec_enet_clear_ethtool_stats(ndev);
3237 else
3238 fec_enet_update_ethtool_stats(ndev);
3239
3240 return 0;
3241}
3242
3243#ifdef CONFIG_OF
3244static int fec_reset_phy(struct platform_device *pdev)
3245{
3246 int err, phy_reset;
3247 bool active_high = false;
3248 int msec = 1, phy_post_delay = 0;
3249 struct device_node *np = pdev->dev.of_node;
3250
3251 if (!np)
3252 return 0;
3253
3254 err = of_property_read_u32(np, "phy-reset-duration", &msec);
3255 /* A sane reset duration should not be longer than 1s */
3256 if (!err && msec > 1000)
3257 msec = 1;
3258
3259 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3260 if (phy_reset == -EPROBE_DEFER)
3261 return phy_reset;
3262 else if (!gpio_is_valid(phy_reset))
3263 return 0;
3264
3265 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
3266 /* valid reset duration should be less than 1s */
3267 if (!err && phy_post_delay > 1000)
3268 return -EINVAL;
3269
3270 active_high = of_property_read_bool(np, "phy-reset-active-high");
3271
3272 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3273 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
3274 "phy-reset");
3275 if (err) {
3276 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3277 return err;
3278 }
3279
3280 if (msec > 20)
3281 msleep(msec);
3282 else
3283 usleep_range(msec * 1000, msec * 1000 + 1000);
3284
3285 gpio_set_value_cansleep(phy_reset, !active_high);
3286
3287 if (!phy_post_delay)
3288 return 0;
3289
3290 if (phy_post_delay > 20)
3291 msleep(phy_post_delay);
3292 else
3293 usleep_range(phy_post_delay * 1000,
3294 phy_post_delay * 1000 + 1000);
3295
3296 return 0;
3297}
3298#else /* CONFIG_OF */
3299static int fec_reset_phy(struct platform_device *pdev)
3300{
3301 /*
3302 * In case of platform probe, the reset has been done
3303 * by machine code.
3304 */
3305 return 0;
3306}
3307#endif /* CONFIG_OF */
3308
3309static void
3310fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3311{
3312 struct device_node *np = pdev->dev.of_node;
3313
3314 *num_tx = *num_rx = 1;
3315
3316 if (!np || !of_device_is_available(np))
3317 return;
3318
3319 /* parse the num of tx and rx queues */
3320 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3321
3322 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3323
3324 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3325 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3326 *num_tx);
3327 *num_tx = 1;
3328 return;
3329 }
3330
3331 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3332 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3333 *num_rx);
3334 *num_rx = 1;
3335 return;
3336 }
3337
3338}
3339
3340static int fec_enet_get_irq_cnt(struct platform_device *pdev)
3341{
3342 int irq_cnt = platform_irq_count(pdev);
3343
3344 if (irq_cnt > FEC_IRQ_NUM)
3345 irq_cnt = FEC_IRQ_NUM; /* last for pps */
3346 else if (irq_cnt == 2)
3347 irq_cnt = 1; /* last for pps */
3348 else if (irq_cnt <= 0)
3349 irq_cnt = 1; /* At least 1 irq is needed */
3350 return irq_cnt;
3351}
3352
3353static int
3354fec_probe(struct platform_device *pdev)
3355{
3356 struct fec_enet_private *fep;
3357 struct fec_platform_data *pdata;
3358 struct net_device *ndev;
3359 int i, irq, ret = 0;
3360 struct resource *r;
3361 const struct of_device_id *of_id;
3362 static int dev_id;
3363 struct device_node *np = pdev->dev.of_node, *phy_node;
3364 int num_tx_qs;
3365 int num_rx_qs;
3366 char irq_name[8];
3367 int irq_cnt;
3368
3369 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3370
3371 /* Init network device */
3372 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
3373 FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
3374 if (!ndev)
3375 return -ENOMEM;
3376
3377 SET_NETDEV_DEV(ndev, &pdev->dev);
3378
3379 /* setup board info structure */
3380 fep = netdev_priv(ndev);
3381
3382 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3383 if (of_id)
3384 pdev->id_entry = of_id->data;
3385 fep->quirks = pdev->id_entry->driver_data;
3386
3387 fep->netdev = ndev;
3388 fep->num_rx_queues = num_rx_qs;
3389 fep->num_tx_queues = num_tx_qs;
3390
3391#if !defined(CONFIG_M5272)
3392 /* default enable pause frame auto negotiation */
3393 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3394 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3395#endif
3396
3397 /* Select default pin state */
3398 pinctrl_pm_select_default_state(&pdev->dev);
3399
3400 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3401 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3402 if (IS_ERR(fep->hwp)) {
3403 ret = PTR_ERR(fep->hwp);
3404 goto failed_ioremap;
3405 }
3406
3407 fep->pdev = pdev;
3408 fep->dev_id = dev_id++;
3409
3410 platform_set_drvdata(pdev, ndev);
3411
3412 if ((of_machine_is_compatible("fsl,imx6q") ||
3413 of_machine_is_compatible("fsl,imx6dl")) &&
3414 !of_property_read_bool(np, "fsl,err006687-workaround-present"))
3415 fep->quirks |= FEC_QUIRK_ERR006687;
3416
3417 if (of_get_property(np, "fsl,magic-packet", NULL))
3418 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3419
3420 phy_node = of_parse_phandle(np, "phy-handle", 0);
3421 if (!phy_node && of_phy_is_fixed_link(np)) {
3422 ret = of_phy_register_fixed_link(np);
3423 if (ret < 0) {
3424 dev_err(&pdev->dev,
3425 "broken fixed-link specification\n");
3426 goto failed_phy;
3427 }
3428 phy_node = of_node_get(np);
3429 }
3430 fep->phy_node = phy_node;
3431
3432 ret = of_get_phy_mode(pdev->dev.of_node);
3433 if (ret < 0) {
3434 pdata = dev_get_platdata(&pdev->dev);
3435 if (pdata)
3436 fep->phy_interface = pdata->phy;
3437 else
3438 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3439 } else {
3440 fep->phy_interface = ret;
3441 }
3442
3443 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3444 if (IS_ERR(fep->clk_ipg)) {
3445 ret = PTR_ERR(fep->clk_ipg);
3446 goto failed_clk;
3447 }
3448
3449 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3450 if (IS_ERR(fep->clk_ahb)) {
3451 ret = PTR_ERR(fep->clk_ahb);
3452 goto failed_clk;
3453 }
3454
3455 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3456
3457 /* enet_out is optional, depends on board */
3458 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3459 if (IS_ERR(fep->clk_enet_out))
3460 fep->clk_enet_out = NULL;
3461
3462 fep->ptp_clk_on = false;
3463 mutex_init(&fep->ptp_clk_mutex);
3464
3465 /* clk_ref is optional, depends on board */
3466 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3467 if (IS_ERR(fep->clk_ref))
3468 fep->clk_ref = NULL;
3469
3470 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3471 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3472 if (IS_ERR(fep->clk_ptp)) {
3473 fep->clk_ptp = NULL;
3474 fep->bufdesc_ex = false;
3475 }
3476
3477 ret = fec_enet_clk_enable(ndev, true);
3478 if (ret)
3479 goto failed_clk;
3480
3481 ret = clk_prepare_enable(fep->clk_ipg);
3482 if (ret)
3483 goto failed_clk_ipg;
3484
3485 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3486 if (!IS_ERR(fep->reg_phy)) {
3487 ret = regulator_enable(fep->reg_phy);
3488 if (ret) {
3489 dev_err(&pdev->dev,
3490 "Failed to enable phy regulator: %d\n", ret);
3491 clk_disable_unprepare(fep->clk_ipg);
3492 goto failed_regulator;
3493 }
3494 } else {
3495 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
3496 ret = -EPROBE_DEFER;
3497 goto failed_regulator;
3498 }
3499 fep->reg_phy = NULL;
3500 }
3501
3502 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3503 pm_runtime_use_autosuspend(&pdev->dev);
3504 pm_runtime_get_noresume(&pdev->dev);
3505 pm_runtime_set_active(&pdev->dev);
3506 pm_runtime_enable(&pdev->dev);
3507
3508 ret = fec_reset_phy(pdev);
3509 if (ret)
3510 goto failed_reset;
3511
3512 irq_cnt = fec_enet_get_irq_cnt(pdev);
3513 if (fep->bufdesc_ex)
3514 fec_ptp_init(pdev, irq_cnt);
3515
3516 ret = fec_enet_init(ndev);
3517 if (ret)
3518 goto failed_init;
3519
3520 for (i = 0; i < irq_cnt; i++) {
3521 sprintf(irq_name, "int%d", i);
3522 irq = platform_get_irq_byname(pdev, irq_name);
3523 if (irq < 0)
3524 irq = platform_get_irq(pdev, i);
3525 if (irq < 0) {
3526 ret = irq;
3527 goto failed_irq;
3528 }
3529 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3530 0, pdev->name, ndev);
3531 if (ret)
3532 goto failed_irq;
3533
3534 fep->irq[i] = irq;
3535 }
3536
3537 init_completion(&fep->mdio_done);
3538 ret = fec_enet_mii_init(pdev);
3539 if (ret)
3540 goto failed_mii_init;
3541
3542 /* Carrier starts down, phylib will bring it up */
3543 netif_carrier_off(ndev);
3544 fec_enet_clk_enable(ndev, false);
3545 pinctrl_pm_select_sleep_state(&pdev->dev);
3546
3547 ret = register_netdev(ndev);
3548 if (ret)
3549 goto failed_register;
3550
3551 device_init_wakeup(&ndev->dev, fep->wol_flag &
3552 FEC_WOL_HAS_MAGIC_PACKET);
3553
3554 if (fep->bufdesc_ex && fep->ptp_clock)
3555 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3556
3557 fep->rx_copybreak = COPYBREAK_DEFAULT;
3558 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3559
3560 pm_runtime_mark_last_busy(&pdev->dev);
3561 pm_runtime_put_autosuspend(&pdev->dev);
3562
3563 return 0;
3564
3565failed_register:
3566 fec_enet_mii_remove(fep);
3567failed_mii_init:
3568failed_irq:
3569failed_init:
3570 fec_ptp_stop(pdev);
3571 if (fep->reg_phy)
3572 regulator_disable(fep->reg_phy);
3573failed_reset:
3574 pm_runtime_put(&pdev->dev);
3575 pm_runtime_disable(&pdev->dev);
3576failed_regulator:
3577failed_clk_ipg:
3578 fec_enet_clk_enable(ndev, false);
3579failed_clk:
3580 if (of_phy_is_fixed_link(np))
3581 of_phy_deregister_fixed_link(np);
3582 of_node_put(phy_node);
3583failed_phy:
3584 dev_id--;
3585failed_ioremap:
3586 free_netdev(ndev);
3587
3588 return ret;
3589}
3590
3591static int
3592fec_drv_remove(struct platform_device *pdev)
3593{
3594 struct net_device *ndev = platform_get_drvdata(pdev);
3595 struct fec_enet_private *fep = netdev_priv(ndev);
3596 struct device_node *np = pdev->dev.of_node;
3597
3598 cancel_work_sync(&fep->tx_timeout_work);
3599 fec_ptp_stop(pdev);
3600 unregister_netdev(ndev);
3601 fec_enet_mii_remove(fep);
3602 if (fep->reg_phy)
3603 regulator_disable(fep->reg_phy);
3604 pm_runtime_put(&pdev->dev);
3605 pm_runtime_disable(&pdev->dev);
3606 if (of_phy_is_fixed_link(np))
3607 of_phy_deregister_fixed_link(np);
3608 of_node_put(fep->phy_node);
3609 free_netdev(ndev);
3610
3611 return 0;
3612}
3613
3614static int __maybe_unused fec_suspend(struct device *dev)
3615{
3616 struct net_device *ndev = dev_get_drvdata(dev);
3617 struct fec_enet_private *fep = netdev_priv(ndev);
3618
3619 rtnl_lock();
3620 if (netif_running(ndev)) {
3621 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3622 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3623 phy_stop(ndev->phydev);
3624 napi_disable(&fep->napi);
3625 netif_tx_lock_bh(ndev);
3626 netif_device_detach(ndev);
3627 netif_tx_unlock_bh(ndev);
3628 fec_stop(ndev);
3629 fec_enet_clk_enable(ndev, false);
3630 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3631 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3632 }
3633 rtnl_unlock();
3634
3635 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3636 regulator_disable(fep->reg_phy);
3637
3638 /* SOC supply clock to phy, when clock is disabled, phy link down
3639 * SOC control phy regulator, when regulator is disabled, phy link down
3640 */
3641 if (fep->clk_enet_out || fep->reg_phy)
3642 fep->link = 0;
3643
3644 return 0;
3645}
3646
3647static int __maybe_unused fec_resume(struct device *dev)
3648{
3649 struct net_device *ndev = dev_get_drvdata(dev);
3650 struct fec_enet_private *fep = netdev_priv(ndev);
3651 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3652 int ret;
3653 int val;
3654
3655 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3656 ret = regulator_enable(fep->reg_phy);
3657 if (ret)
3658 return ret;
3659 }
3660
3661 rtnl_lock();
3662 if (netif_running(ndev)) {
3663 ret = fec_enet_clk_enable(ndev, true);
3664 if (ret) {
3665 rtnl_unlock();
3666 goto failed_clk;
3667 }
3668 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3669 if (pdata && pdata->sleep_mode_enable)
3670 pdata->sleep_mode_enable(false);
3671 val = readl(fep->hwp + FEC_ECNTRL);
3672 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3673 writel(val, fep->hwp + FEC_ECNTRL);
3674 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3675 } else {
3676 pinctrl_pm_select_default_state(&fep->pdev->dev);
3677 }
3678 fec_restart(ndev);
3679 netif_tx_lock_bh(ndev);
3680 netif_device_attach(ndev);
3681 netif_tx_unlock_bh(ndev);
3682 napi_enable(&fep->napi);
3683 phy_start(ndev->phydev);
3684 }
3685 rtnl_unlock();
3686
3687 return 0;
3688
3689failed_clk:
3690 if (fep->reg_phy)
3691 regulator_disable(fep->reg_phy);
3692 return ret;
3693}
3694
3695static int __maybe_unused fec_runtime_suspend(struct device *dev)
3696{
3697 struct net_device *ndev = dev_get_drvdata(dev);
3698 struct fec_enet_private *fep = netdev_priv(ndev);
3699
3700 clk_disable_unprepare(fep->clk_ipg);
3701
3702 return 0;
3703}
3704
3705static int __maybe_unused fec_runtime_resume(struct device *dev)
3706{
3707 struct net_device *ndev = dev_get_drvdata(dev);
3708 struct fec_enet_private *fep = netdev_priv(ndev);
3709
3710 return clk_prepare_enable(fep->clk_ipg);
3711}
3712
3713static const struct dev_pm_ops fec_pm_ops = {
3714 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3715 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3716};
3717
3718static struct platform_driver fec_driver = {
3719 .driver = {
3720 .name = DRIVER_NAME,
3721 .pm = &fec_pm_ops,
3722 .of_match_table = fec_dt_ids,
3723 },
3724 .id_table = fec_devtype,
3725 .probe = fec_probe,
3726 .remove = fec_drv_remove,
3727};
3728
3729module_platform_driver(fec_driver);
3730
3731MODULE_ALIAS("platform:"DRIVER_NAME);
3732MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 *
6 * Right now, I am very wasteful with the buffers. I allocate memory
7 * pages and then divide them into 2K frame buffers. This way I know I
8 * have buffers large enough to hold one frame within one buffer descriptor.
9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
10 * will be much more memory efficient and will easily handle lots of
11 * small packets.
12 *
13 * Much better multiple PHY support by Magnus Damm.
14 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 *
16 * Support for FEC controller of ColdFire processors.
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 *
19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
21 *
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
23 */
24
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/string.h>
28#include <linux/pm_runtime.h>
29#include <linux/ptrace.h>
30#include <linux/errno.h>
31#include <linux/ioport.h>
32#include <linux/slab.h>
33#include <linux/interrupt.h>
34#include <linux/delay.h>
35#include <linux/netdevice.h>
36#include <linux/etherdevice.h>
37#include <linux/skbuff.h>
38#include <linux/in.h>
39#include <linux/ip.h>
40#include <net/ip.h>
41#include <net/page_pool/helpers.h>
42#include <net/selftests.h>
43#include <net/tso.h>
44#include <linux/tcp.h>
45#include <linux/udp.h>
46#include <linux/icmp.h>
47#include <linux/spinlock.h>
48#include <linux/workqueue.h>
49#include <linux/bitops.h>
50#include <linux/io.h>
51#include <linux/irq.h>
52#include <linux/clk.h>
53#include <linux/crc32.h>
54#include <linux/platform_device.h>
55#include <linux/property.h>
56#include <linux/mdio.h>
57#include <linux/phy.h>
58#include <linux/fec.h>
59#include <linux/of.h>
60#include <linux/of_mdio.h>
61#include <linux/of_net.h>
62#include <linux/regulator/consumer.h>
63#include <linux/if_vlan.h>
64#include <linux/pinctrl/consumer.h>
65#include <linux/gpio/consumer.h>
66#include <linux/prefetch.h>
67#include <linux/mfd/syscon.h>
68#include <linux/regmap.h>
69#include <soc/imx/cpuidle.h>
70#include <linux/filter.h>
71#include <linux/bpf.h>
72#include <linux/bpf_trace.h>
73
74#include <asm/cacheflush.h>
75
76#include "fec.h"
77
78static void set_multicast_list(struct net_device *ndev);
79static void fec_enet_itr_coal_set(struct net_device *ndev);
80static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep,
81 int cpu, struct xdp_buff *xdp,
82 u32 dma_sync_len);
83
84#define DRIVER_NAME "fec"
85
86static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2};
87
88#define FEC_ENET_RSEM_V 0x84
89#define FEC_ENET_RSFL_V 16
90#define FEC_ENET_RAEM_V 0x8
91#define FEC_ENET_RAFL_V 0x8
92#define FEC_ENET_OPD_V 0xFFF0
93#define FEC_MDIO_PM_TIMEOUT 100 /* ms */
94
95#define FEC_ENET_XDP_PASS 0
96#define FEC_ENET_XDP_CONSUMED BIT(0)
97#define FEC_ENET_XDP_TX BIT(1)
98#define FEC_ENET_XDP_REDIR BIT(2)
99
100struct fec_devinfo {
101 u32 quirks;
102};
103
104static const struct fec_devinfo fec_imx25_info = {
105 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR |
106 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45,
107};
108
109static const struct fec_devinfo fec_imx27_info = {
110 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG |
111 FEC_QUIRK_HAS_MDIO_C45,
112};
113
114static const struct fec_devinfo fec_imx28_info = {
115 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
116 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
117 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII |
118 FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45,
119};
120
121static const struct fec_devinfo fec_imx6q_info = {
122 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
125 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII |
126 FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45,
127};
128
129static const struct fec_devinfo fec_mvf600_info = {
130 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC |
131 FEC_QUIRK_HAS_MDIO_C45,
132};
133
134static const struct fec_devinfo fec_imx6x_info = {
135 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
136 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
137 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
138 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
139 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
140 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
141 FEC_QUIRK_HAS_MDIO_C45,
142};
143
144static const struct fec_devinfo fec_imx6ul_info = {
145 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
146 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
147 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
148 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
149 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII |
150 FEC_QUIRK_HAS_MDIO_C45,
151};
152
153static const struct fec_devinfo fec_imx8mq_info = {
154 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
155 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
156 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
157 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
158 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
159 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
160 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 |
161 FEC_QUIRK_HAS_MDIO_C45,
162};
163
164static const struct fec_devinfo fec_imx8qm_info = {
165 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
166 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
167 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
168 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
169 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
170 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
171 FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45,
172};
173
174static const struct fec_devinfo fec_s32v234_info = {
175 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
176 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
177 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
178 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
179 FEC_QUIRK_HAS_MDIO_C45,
180};
181
182static struct platform_device_id fec_devtype[] = {
183 {
184 /* keep it for coldfire */
185 .name = DRIVER_NAME,
186 .driver_data = 0,
187 }, {
188 /* sentinel */
189 }
190};
191MODULE_DEVICE_TABLE(platform, fec_devtype);
192
193static const struct of_device_id fec_dt_ids[] = {
194 { .compatible = "fsl,imx25-fec", .data = &fec_imx25_info, },
195 { .compatible = "fsl,imx27-fec", .data = &fec_imx27_info, },
196 { .compatible = "fsl,imx28-fec", .data = &fec_imx28_info, },
197 { .compatible = "fsl,imx6q-fec", .data = &fec_imx6q_info, },
198 { .compatible = "fsl,mvf600-fec", .data = &fec_mvf600_info, },
199 { .compatible = "fsl,imx6sx-fec", .data = &fec_imx6x_info, },
200 { .compatible = "fsl,imx6ul-fec", .data = &fec_imx6ul_info, },
201 { .compatible = "fsl,imx8mq-fec", .data = &fec_imx8mq_info, },
202 { .compatible = "fsl,imx8qm-fec", .data = &fec_imx8qm_info, },
203 { .compatible = "fsl,s32v234-fec", .data = &fec_s32v234_info, },
204 { /* sentinel */ }
205};
206MODULE_DEVICE_TABLE(of, fec_dt_ids);
207
208static unsigned char macaddr[ETH_ALEN];
209module_param_array(macaddr, byte, NULL, 0);
210MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
211
212#if defined(CONFIG_M5272)
213/*
214 * Some hardware gets it MAC address out of local flash memory.
215 * if this is non-zero then assume it is the address to get MAC from.
216 */
217#if defined(CONFIG_NETtel)
218#define FEC_FLASHMAC 0xf0006006
219#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
220#define FEC_FLASHMAC 0xf0006000
221#elif defined(CONFIG_CANCam)
222#define FEC_FLASHMAC 0xf0020000
223#elif defined (CONFIG_M5272C3)
224#define FEC_FLASHMAC (0xffe04000 + 4)
225#elif defined(CONFIG_MOD5272)
226#define FEC_FLASHMAC 0xffc0406b
227#else
228#define FEC_FLASHMAC 0
229#endif
230#endif /* CONFIG_M5272 */
231
232/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
233 *
234 * 2048 byte skbufs are allocated. However, alignment requirements
235 * varies between FEC variants. Worst case is 64, so round down by 64.
236 */
237#define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64))
238#define PKT_MINBUF_SIZE 64
239
240/* FEC receive acceleration */
241#define FEC_RACC_IPDIS BIT(1)
242#define FEC_RACC_PRODIS BIT(2)
243#define FEC_RACC_SHIFT16 BIT(7)
244#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
245
246/* MIB Control Register */
247#define FEC_MIB_CTRLSTAT_DISABLE BIT(31)
248
249/*
250 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
251 * size bits. Other FEC hardware does not, so we need to take that into
252 * account when setting it.
253 */
254#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
255 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
256 defined(CONFIG_ARM64)
257#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
258#else
259#define OPT_FRAME_SIZE 0
260#endif
261
262/* FEC MII MMFR bits definition */
263#define FEC_MMFR_ST (1 << 30)
264#define FEC_MMFR_ST_C45 (0)
265#define FEC_MMFR_OP_READ (2 << 28)
266#define FEC_MMFR_OP_READ_C45 (3 << 28)
267#define FEC_MMFR_OP_WRITE (1 << 28)
268#define FEC_MMFR_OP_ADDR_WRITE (0)
269#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
270#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
271#define FEC_MMFR_TA (2 << 16)
272#define FEC_MMFR_DATA(v) (v & 0xffff)
273/* FEC ECR bits definition */
274#define FEC_ECR_RESET BIT(0)
275#define FEC_ECR_ETHEREN BIT(1)
276#define FEC_ECR_MAGICEN BIT(2)
277#define FEC_ECR_SLEEP BIT(3)
278#define FEC_ECR_EN1588 BIT(4)
279#define FEC_ECR_BYTESWP BIT(8)
280/* FEC RCR bits definition */
281#define FEC_RCR_LOOP BIT(0)
282#define FEC_RCR_HALFDPX BIT(1)
283#define FEC_RCR_MII BIT(2)
284#define FEC_RCR_PROMISC BIT(3)
285#define FEC_RCR_BC_REJ BIT(4)
286#define FEC_RCR_FLOWCTL BIT(5)
287#define FEC_RCR_RMII BIT(8)
288#define FEC_RCR_10BASET BIT(9)
289/* TX WMARK bits */
290#define FEC_TXWMRK_STRFWD BIT(8)
291
292#define FEC_MII_TIMEOUT 30000 /* us */
293
294/* Transmitter timeout */
295#define TX_TIMEOUT (2 * HZ)
296
297#define FEC_PAUSE_FLAG_AUTONEG 0x1
298#define FEC_PAUSE_FLAG_ENABLE 0x2
299#define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
300#define FEC_WOL_FLAG_ENABLE (0x1 << 1)
301#define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
302
303/* Max number of allowed TCP segments for software TSO */
304#define FEC_MAX_TSO_SEGS 100
305#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
306
307#define IS_TSO_HEADER(txq, addr) \
308 ((addr >= txq->tso_hdrs_dma) && \
309 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
310
311static int mii_cnt;
312
313static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
314 struct bufdesc_prop *bd)
315{
316 return (bdp >= bd->last) ? bd->base
317 : (struct bufdesc *)(((void *)bdp) + bd->dsize);
318}
319
320static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
321 struct bufdesc_prop *bd)
322{
323 return (bdp <= bd->base) ? bd->last
324 : (struct bufdesc *)(((void *)bdp) - bd->dsize);
325}
326
327static int fec_enet_get_bd_index(struct bufdesc *bdp,
328 struct bufdesc_prop *bd)
329{
330 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
331}
332
333static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
334{
335 int entries;
336
337 entries = (((const char *)txq->dirty_tx -
338 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
339
340 return entries >= 0 ? entries : entries + txq->bd.ring_size;
341}
342
343static void swap_buffer(void *bufaddr, int len)
344{
345 int i;
346 unsigned int *buf = bufaddr;
347
348 for (i = 0; i < len; i += 4, buf++)
349 swab32s(buf);
350}
351
352static void fec_dump(struct net_device *ndev)
353{
354 struct fec_enet_private *fep = netdev_priv(ndev);
355 struct bufdesc *bdp;
356 struct fec_enet_priv_tx_q *txq;
357 int index = 0;
358
359 netdev_info(ndev, "TX ring dump\n");
360 pr_info("Nr SC addr len SKB\n");
361
362 txq = fep->tx_queue[0];
363 bdp = txq->bd.base;
364
365 do {
366 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
367 index,
368 bdp == txq->bd.cur ? 'S' : ' ',
369 bdp == txq->dirty_tx ? 'H' : ' ',
370 fec16_to_cpu(bdp->cbd_sc),
371 fec32_to_cpu(bdp->cbd_bufaddr),
372 fec16_to_cpu(bdp->cbd_datlen),
373 txq->tx_buf[index].buf_p);
374 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
375 index++;
376 } while (bdp != txq->bd.base);
377}
378
379/*
380 * Coldfire does not support DMA coherent allocations, and has historically used
381 * a band-aid with a manual flush in fec_enet_rx_queue.
382 */
383#if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA)
384static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
385 gfp_t gfp)
386{
387 return dma_alloc_noncoherent(dev, size, handle, DMA_BIDIRECTIONAL, gfp);
388}
389
390static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr,
391 dma_addr_t handle)
392{
393 dma_free_noncoherent(dev, size, cpu_addr, handle, DMA_BIDIRECTIONAL);
394}
395#else /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */
396static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
397 gfp_t gfp)
398{
399 return dma_alloc_coherent(dev, size, handle, gfp);
400}
401
402static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr,
403 dma_addr_t handle)
404{
405 dma_free_coherent(dev, size, cpu_addr, handle);
406}
407#endif /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */
408
409struct fec_dma_devres {
410 size_t size;
411 void *vaddr;
412 dma_addr_t dma_handle;
413};
414
415static void fec_dmam_release(struct device *dev, void *res)
416{
417 struct fec_dma_devres *this = res;
418
419 fec_dma_free(dev, this->size, this->vaddr, this->dma_handle);
420}
421
422static void *fec_dmam_alloc(struct device *dev, size_t size, dma_addr_t *handle,
423 gfp_t gfp)
424{
425 struct fec_dma_devres *dr;
426 void *vaddr;
427
428 dr = devres_alloc(fec_dmam_release, sizeof(*dr), gfp);
429 if (!dr)
430 return NULL;
431 vaddr = fec_dma_alloc(dev, size, handle, gfp);
432 if (!vaddr) {
433 devres_free(dr);
434 return NULL;
435 }
436 dr->vaddr = vaddr;
437 dr->dma_handle = *handle;
438 dr->size = size;
439 devres_add(dev, dr);
440 return vaddr;
441}
442
443static inline bool is_ipv4_pkt(struct sk_buff *skb)
444{
445 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
446}
447
448static int
449fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
450{
451 /* Only run for packets requiring a checksum. */
452 if (skb->ip_summed != CHECKSUM_PARTIAL)
453 return 0;
454
455 if (unlikely(skb_cow_head(skb, 0)))
456 return -1;
457
458 if (is_ipv4_pkt(skb))
459 ip_hdr(skb)->check = 0;
460 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
461
462 return 0;
463}
464
465static int
466fec_enet_create_page_pool(struct fec_enet_private *fep,
467 struct fec_enet_priv_rx_q *rxq, int size)
468{
469 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog);
470 struct page_pool_params pp_params = {
471 .order = 0,
472 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
473 .pool_size = size,
474 .nid = dev_to_node(&fep->pdev->dev),
475 .dev = &fep->pdev->dev,
476 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE,
477 .offset = FEC_ENET_XDP_HEADROOM,
478 .max_len = FEC_ENET_RX_FRSIZE,
479 };
480 int err;
481
482 rxq->page_pool = page_pool_create(&pp_params);
483 if (IS_ERR(rxq->page_pool)) {
484 err = PTR_ERR(rxq->page_pool);
485 rxq->page_pool = NULL;
486 return err;
487 }
488
489 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0);
490 if (err < 0)
491 goto err_free_pp;
492
493 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL,
494 rxq->page_pool);
495 if (err)
496 goto err_unregister_rxq;
497
498 return 0;
499
500err_unregister_rxq:
501 xdp_rxq_info_unreg(&rxq->xdp_rxq);
502err_free_pp:
503 page_pool_destroy(rxq->page_pool);
504 rxq->page_pool = NULL;
505 return err;
506}
507
508static struct bufdesc *
509fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
510 struct sk_buff *skb,
511 struct net_device *ndev)
512{
513 struct fec_enet_private *fep = netdev_priv(ndev);
514 struct bufdesc *bdp = txq->bd.cur;
515 struct bufdesc_ex *ebdp;
516 int nr_frags = skb_shinfo(skb)->nr_frags;
517 int frag, frag_len;
518 unsigned short status;
519 unsigned int estatus = 0;
520 skb_frag_t *this_frag;
521 unsigned int index;
522 void *bufaddr;
523 dma_addr_t addr;
524 int i;
525
526 for (frag = 0; frag < nr_frags; frag++) {
527 this_frag = &skb_shinfo(skb)->frags[frag];
528 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
529 ebdp = (struct bufdesc_ex *)bdp;
530
531 status = fec16_to_cpu(bdp->cbd_sc);
532 status &= ~BD_ENET_TX_STATS;
533 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
534 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]);
535
536 /* Handle the last BD specially */
537 if (frag == nr_frags - 1) {
538 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
539 if (fep->bufdesc_ex) {
540 estatus |= BD_ENET_TX_INT;
541 if (unlikely(skb_shinfo(skb)->tx_flags &
542 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
543 estatus |= BD_ENET_TX_TS;
544 }
545 }
546
547 if (fep->bufdesc_ex) {
548 if (fep->quirks & FEC_QUIRK_HAS_AVB)
549 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
550 if (skb->ip_summed == CHECKSUM_PARTIAL)
551 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
552
553 ebdp->cbd_bdu = 0;
554 ebdp->cbd_esc = cpu_to_fec32(estatus);
555 }
556
557 bufaddr = skb_frag_address(this_frag);
558
559 index = fec_enet_get_bd_index(bdp, &txq->bd);
560 if (((unsigned long) bufaddr) & fep->tx_align ||
561 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
562 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
563 bufaddr = txq->tx_bounce[index];
564
565 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
566 swap_buffer(bufaddr, frag_len);
567 }
568
569 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
570 DMA_TO_DEVICE);
571 if (dma_mapping_error(&fep->pdev->dev, addr)) {
572 if (net_ratelimit())
573 netdev_err(ndev, "Tx DMA memory map failed\n");
574 goto dma_mapping_error;
575 }
576
577 bdp->cbd_bufaddr = cpu_to_fec32(addr);
578 bdp->cbd_datlen = cpu_to_fec16(frag_len);
579 /* Make sure the updates to rest of the descriptor are
580 * performed before transferring ownership.
581 */
582 wmb();
583 bdp->cbd_sc = cpu_to_fec16(status);
584 }
585
586 return bdp;
587dma_mapping_error:
588 bdp = txq->bd.cur;
589 for (i = 0; i < frag; i++) {
590 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
591 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
592 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
593 }
594 return ERR_PTR(-ENOMEM);
595}
596
597static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
598 struct sk_buff *skb, struct net_device *ndev)
599{
600 struct fec_enet_private *fep = netdev_priv(ndev);
601 int nr_frags = skb_shinfo(skb)->nr_frags;
602 struct bufdesc *bdp, *last_bdp;
603 void *bufaddr;
604 dma_addr_t addr;
605 unsigned short status;
606 unsigned short buflen;
607 unsigned int estatus = 0;
608 unsigned int index;
609 int entries_free;
610
611 entries_free = fec_enet_get_free_txdesc_num(txq);
612 if (entries_free < MAX_SKB_FRAGS + 1) {
613 dev_kfree_skb_any(skb);
614 if (net_ratelimit())
615 netdev_err(ndev, "NOT enough BD for SG!\n");
616 return NETDEV_TX_OK;
617 }
618
619 /* Protocol checksum off-load for TCP and UDP. */
620 if (fec_enet_clear_csum(skb, ndev)) {
621 dev_kfree_skb_any(skb);
622 return NETDEV_TX_OK;
623 }
624
625 /* Fill in a Tx ring entry */
626 bdp = txq->bd.cur;
627 last_bdp = bdp;
628 status = fec16_to_cpu(bdp->cbd_sc);
629 status &= ~BD_ENET_TX_STATS;
630
631 /* Set buffer length and buffer pointer */
632 bufaddr = skb->data;
633 buflen = skb_headlen(skb);
634
635 index = fec_enet_get_bd_index(bdp, &txq->bd);
636 if (((unsigned long) bufaddr) & fep->tx_align ||
637 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
638 memcpy(txq->tx_bounce[index], skb->data, buflen);
639 bufaddr = txq->tx_bounce[index];
640
641 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
642 swap_buffer(bufaddr, buflen);
643 }
644
645 /* Push the data cache so the CPM does not get stale memory data. */
646 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
647 if (dma_mapping_error(&fep->pdev->dev, addr)) {
648 dev_kfree_skb_any(skb);
649 if (net_ratelimit())
650 netdev_err(ndev, "Tx DMA memory map failed\n");
651 return NETDEV_TX_OK;
652 }
653
654 if (nr_frags) {
655 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
656 if (IS_ERR(last_bdp)) {
657 dma_unmap_single(&fep->pdev->dev, addr,
658 buflen, DMA_TO_DEVICE);
659 dev_kfree_skb_any(skb);
660 return NETDEV_TX_OK;
661 }
662 } else {
663 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
664 if (fep->bufdesc_ex) {
665 estatus = BD_ENET_TX_INT;
666 if (unlikely(skb_shinfo(skb)->tx_flags &
667 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
668 estatus |= BD_ENET_TX_TS;
669 }
670 }
671 bdp->cbd_bufaddr = cpu_to_fec32(addr);
672 bdp->cbd_datlen = cpu_to_fec16(buflen);
673
674 if (fep->bufdesc_ex) {
675
676 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
677
678 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
679 fep->hwts_tx_en))
680 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
681
682 if (fep->quirks & FEC_QUIRK_HAS_AVB)
683 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
684
685 if (skb->ip_summed == CHECKSUM_PARTIAL)
686 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
687
688 ebdp->cbd_bdu = 0;
689 ebdp->cbd_esc = cpu_to_fec32(estatus);
690 }
691
692 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
693 /* Save skb pointer */
694 txq->tx_buf[index].buf_p = skb;
695
696 /* Make sure the updates to rest of the descriptor are performed before
697 * transferring ownership.
698 */
699 wmb();
700
701 /* Send it on its way. Tell FEC it's ready, interrupt when done,
702 * it's the last BD of the frame, and to put the CRC on the end.
703 */
704 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
705 bdp->cbd_sc = cpu_to_fec16(status);
706
707 /* If this was the last BD in the ring, start at the beginning again. */
708 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
709
710 skb_tx_timestamp(skb);
711
712 /* Make sure the update to bdp is performed before txq->bd.cur. */
713 wmb();
714 txq->bd.cur = bdp;
715
716 /* Trigger transmission start */
717 writel(0, txq->bd.reg_desc_active);
718
719 return 0;
720}
721
722static int
723fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
724 struct net_device *ndev,
725 struct bufdesc *bdp, int index, char *data,
726 int size, bool last_tcp, bool is_last)
727{
728 struct fec_enet_private *fep = netdev_priv(ndev);
729 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
730 unsigned short status;
731 unsigned int estatus = 0;
732 dma_addr_t addr;
733
734 status = fec16_to_cpu(bdp->cbd_sc);
735 status &= ~BD_ENET_TX_STATS;
736
737 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
738
739 if (((unsigned long) data) & fep->tx_align ||
740 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
741 memcpy(txq->tx_bounce[index], data, size);
742 data = txq->tx_bounce[index];
743
744 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
745 swap_buffer(data, size);
746 }
747
748 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
749 if (dma_mapping_error(&fep->pdev->dev, addr)) {
750 dev_kfree_skb_any(skb);
751 if (net_ratelimit())
752 netdev_err(ndev, "Tx DMA memory map failed\n");
753 return NETDEV_TX_OK;
754 }
755
756 bdp->cbd_datlen = cpu_to_fec16(size);
757 bdp->cbd_bufaddr = cpu_to_fec32(addr);
758
759 if (fep->bufdesc_ex) {
760 if (fep->quirks & FEC_QUIRK_HAS_AVB)
761 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
762 if (skb->ip_summed == CHECKSUM_PARTIAL)
763 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
764 ebdp->cbd_bdu = 0;
765 ebdp->cbd_esc = cpu_to_fec32(estatus);
766 }
767
768 /* Handle the last BD specially */
769 if (last_tcp)
770 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
771 if (is_last) {
772 status |= BD_ENET_TX_INTR;
773 if (fep->bufdesc_ex)
774 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
775 }
776
777 bdp->cbd_sc = cpu_to_fec16(status);
778
779 return 0;
780}
781
782static int
783fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
784 struct sk_buff *skb, struct net_device *ndev,
785 struct bufdesc *bdp, int index)
786{
787 struct fec_enet_private *fep = netdev_priv(ndev);
788 int hdr_len = skb_tcp_all_headers(skb);
789 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
790 void *bufaddr;
791 unsigned long dmabuf;
792 unsigned short status;
793 unsigned int estatus = 0;
794
795 status = fec16_to_cpu(bdp->cbd_sc);
796 status &= ~BD_ENET_TX_STATS;
797 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
798
799 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
800 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
801 if (((unsigned long)bufaddr) & fep->tx_align ||
802 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
803 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
804 bufaddr = txq->tx_bounce[index];
805
806 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
807 swap_buffer(bufaddr, hdr_len);
808
809 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
810 hdr_len, DMA_TO_DEVICE);
811 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
812 dev_kfree_skb_any(skb);
813 if (net_ratelimit())
814 netdev_err(ndev, "Tx DMA memory map failed\n");
815 return NETDEV_TX_OK;
816 }
817 }
818
819 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
820 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
821
822 if (fep->bufdesc_ex) {
823 if (fep->quirks & FEC_QUIRK_HAS_AVB)
824 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
825 if (skb->ip_summed == CHECKSUM_PARTIAL)
826 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
827 ebdp->cbd_bdu = 0;
828 ebdp->cbd_esc = cpu_to_fec32(estatus);
829 }
830
831 bdp->cbd_sc = cpu_to_fec16(status);
832
833 return 0;
834}
835
836static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
837 struct sk_buff *skb,
838 struct net_device *ndev)
839{
840 struct fec_enet_private *fep = netdev_priv(ndev);
841 int hdr_len, total_len, data_left;
842 struct bufdesc *bdp = txq->bd.cur;
843 struct tso_t tso;
844 unsigned int index = 0;
845 int ret;
846
847 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
848 dev_kfree_skb_any(skb);
849 if (net_ratelimit())
850 netdev_err(ndev, "NOT enough BD for TSO!\n");
851 return NETDEV_TX_OK;
852 }
853
854 /* Protocol checksum off-load for TCP and UDP. */
855 if (fec_enet_clear_csum(skb, ndev)) {
856 dev_kfree_skb_any(skb);
857 return NETDEV_TX_OK;
858 }
859
860 /* Initialize the TSO handler, and prepare the first payload */
861 hdr_len = tso_start(skb, &tso);
862
863 total_len = skb->len - hdr_len;
864 while (total_len > 0) {
865 char *hdr;
866
867 index = fec_enet_get_bd_index(bdp, &txq->bd);
868 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
869 total_len -= data_left;
870
871 /* prepare packet headers: MAC + IP + TCP */
872 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
873 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
874 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
875 if (ret)
876 goto err_release;
877
878 while (data_left > 0) {
879 int size;
880
881 size = min_t(int, tso.size, data_left);
882 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
883 index = fec_enet_get_bd_index(bdp, &txq->bd);
884 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
885 bdp, index,
886 tso.data, size,
887 size == data_left,
888 total_len == 0);
889 if (ret)
890 goto err_release;
891
892 data_left -= size;
893 tso_build_data(skb, &tso, size);
894 }
895
896 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
897 }
898
899 /* Save skb pointer */
900 txq->tx_buf[index].buf_p = skb;
901
902 skb_tx_timestamp(skb);
903 txq->bd.cur = bdp;
904
905 /* Trigger transmission start */
906 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
907 !readl(txq->bd.reg_desc_active) ||
908 !readl(txq->bd.reg_desc_active) ||
909 !readl(txq->bd.reg_desc_active) ||
910 !readl(txq->bd.reg_desc_active))
911 writel(0, txq->bd.reg_desc_active);
912
913 return 0;
914
915err_release:
916 /* TODO: Release all used data descriptors for TSO */
917 return ret;
918}
919
920static netdev_tx_t
921fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
922{
923 struct fec_enet_private *fep = netdev_priv(ndev);
924 int entries_free;
925 unsigned short queue;
926 struct fec_enet_priv_tx_q *txq;
927 struct netdev_queue *nq;
928 int ret;
929
930 queue = skb_get_queue_mapping(skb);
931 txq = fep->tx_queue[queue];
932 nq = netdev_get_tx_queue(ndev, queue);
933
934 if (skb_is_gso(skb))
935 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
936 else
937 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
938 if (ret)
939 return ret;
940
941 entries_free = fec_enet_get_free_txdesc_num(txq);
942 if (entries_free <= txq->tx_stop_threshold)
943 netif_tx_stop_queue(nq);
944
945 return NETDEV_TX_OK;
946}
947
948/* Init RX & TX buffer descriptors
949 */
950static void fec_enet_bd_init(struct net_device *dev)
951{
952 struct fec_enet_private *fep = netdev_priv(dev);
953 struct fec_enet_priv_tx_q *txq;
954 struct fec_enet_priv_rx_q *rxq;
955 struct bufdesc *bdp;
956 unsigned int i;
957 unsigned int q;
958
959 for (q = 0; q < fep->num_rx_queues; q++) {
960 /* Initialize the receive buffer descriptors. */
961 rxq = fep->rx_queue[q];
962 bdp = rxq->bd.base;
963
964 for (i = 0; i < rxq->bd.ring_size; i++) {
965
966 /* Initialize the BD for every fragment in the page. */
967 if (bdp->cbd_bufaddr)
968 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
969 else
970 bdp->cbd_sc = cpu_to_fec16(0);
971 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
972 }
973
974 /* Set the last buffer to wrap */
975 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
976 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
977
978 rxq->bd.cur = rxq->bd.base;
979 }
980
981 for (q = 0; q < fep->num_tx_queues; q++) {
982 /* ...and the same for transmit */
983 txq = fep->tx_queue[q];
984 bdp = txq->bd.base;
985 txq->bd.cur = bdp;
986
987 for (i = 0; i < txq->bd.ring_size; i++) {
988 /* Initialize the BD for every fragment in the page. */
989 bdp->cbd_sc = cpu_to_fec16(0);
990 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) {
991 if (bdp->cbd_bufaddr &&
992 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
993 dma_unmap_single(&fep->pdev->dev,
994 fec32_to_cpu(bdp->cbd_bufaddr),
995 fec16_to_cpu(bdp->cbd_datlen),
996 DMA_TO_DEVICE);
997 if (txq->tx_buf[i].buf_p)
998 dev_kfree_skb_any(txq->tx_buf[i].buf_p);
999 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) {
1000 if (bdp->cbd_bufaddr)
1001 dma_unmap_single(&fep->pdev->dev,
1002 fec32_to_cpu(bdp->cbd_bufaddr),
1003 fec16_to_cpu(bdp->cbd_datlen),
1004 DMA_TO_DEVICE);
1005
1006 if (txq->tx_buf[i].buf_p)
1007 xdp_return_frame(txq->tx_buf[i].buf_p);
1008 } else {
1009 struct page *page = txq->tx_buf[i].buf_p;
1010
1011 if (page)
1012 page_pool_put_page(page->pp, page, 0, false);
1013 }
1014
1015 txq->tx_buf[i].buf_p = NULL;
1016 /* restore default tx buffer type: FEC_TXBUF_T_SKB */
1017 txq->tx_buf[i].type = FEC_TXBUF_T_SKB;
1018 bdp->cbd_bufaddr = cpu_to_fec32(0);
1019 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1020 }
1021
1022 /* Set the last buffer to wrap */
1023 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
1024 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
1025 txq->dirty_tx = bdp;
1026 }
1027}
1028
1029static void fec_enet_active_rxring(struct net_device *ndev)
1030{
1031 struct fec_enet_private *fep = netdev_priv(ndev);
1032 int i;
1033
1034 for (i = 0; i < fep->num_rx_queues; i++)
1035 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
1036}
1037
1038static void fec_enet_enable_ring(struct net_device *ndev)
1039{
1040 struct fec_enet_private *fep = netdev_priv(ndev);
1041 struct fec_enet_priv_tx_q *txq;
1042 struct fec_enet_priv_rx_q *rxq;
1043 int i;
1044
1045 for (i = 0; i < fep->num_rx_queues; i++) {
1046 rxq = fep->rx_queue[i];
1047 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
1048 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
1049
1050 /* enable DMA1/2 */
1051 if (i)
1052 writel(RCMR_MATCHEN | RCMR_CMP(i),
1053 fep->hwp + FEC_RCMR(i));
1054 }
1055
1056 for (i = 0; i < fep->num_tx_queues; i++) {
1057 txq = fep->tx_queue[i];
1058 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
1059
1060 /* enable DMA1/2 */
1061 if (i)
1062 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
1063 fep->hwp + FEC_DMA_CFG(i));
1064 }
1065}
1066
1067/*
1068 * This function is called to start or restart the FEC during a link
1069 * change, transmit timeout, or to reconfigure the FEC. The network
1070 * packet processing for this device must be stopped before this call.
1071 */
1072static void
1073fec_restart(struct net_device *ndev)
1074{
1075 struct fec_enet_private *fep = netdev_priv(ndev);
1076 u32 temp_mac[2];
1077 u32 rcntl = OPT_FRAME_SIZE | 0x04;
1078 u32 ecntl = FEC_ECR_ETHEREN;
1079
1080 /* Whack a reset. We should wait for this.
1081 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1082 * instead of reset MAC itself.
1083 */
1084 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES ||
1085 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) {
1086 writel(0, fep->hwp + FEC_ECNTRL);
1087 } else {
1088 writel(1, fep->hwp + FEC_ECNTRL);
1089 udelay(10);
1090 }
1091
1092 /*
1093 * enet-mac reset will reset mac address registers too,
1094 * so need to reconfigure it.
1095 */
1096 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
1097 writel((__force u32)cpu_to_be32(temp_mac[0]),
1098 fep->hwp + FEC_ADDR_LOW);
1099 writel((__force u32)cpu_to_be32(temp_mac[1]),
1100 fep->hwp + FEC_ADDR_HIGH);
1101
1102 /* Clear any outstanding interrupt, except MDIO. */
1103 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT);
1104
1105 fec_enet_bd_init(ndev);
1106
1107 fec_enet_enable_ring(ndev);
1108
1109 /* Enable MII mode */
1110 if (fep->full_duplex == DUPLEX_FULL) {
1111 /* FD enable */
1112 writel(0x04, fep->hwp + FEC_X_CNTRL);
1113 } else {
1114 /* No Rcv on Xmit */
1115 rcntl |= 0x02;
1116 writel(0x0, fep->hwp + FEC_X_CNTRL);
1117 }
1118
1119 /* Set MII speed */
1120 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1121
1122#if !defined(CONFIG_M5272)
1123 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
1124 u32 val = readl(fep->hwp + FEC_RACC);
1125
1126 /* align IP header */
1127 val |= FEC_RACC_SHIFT16;
1128 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
1129 /* set RX checksum */
1130 val |= FEC_RACC_OPTIONS;
1131 else
1132 val &= ~FEC_RACC_OPTIONS;
1133 writel(val, fep->hwp + FEC_RACC);
1134 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
1135 }
1136#endif
1137
1138 /*
1139 * The phy interface and speed need to get configured
1140 * differently on enet-mac.
1141 */
1142 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1143 /* Enable flow control and length check */
1144 rcntl |= 0x40000000 | 0x00000020;
1145
1146 /* RGMII, RMII or MII */
1147 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
1148 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1149 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1150 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1151 rcntl |= (1 << 6);
1152 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1153 rcntl |= FEC_RCR_RMII;
1154 else
1155 rcntl &= ~FEC_RCR_RMII;
1156
1157 /* 1G, 100M or 10M */
1158 if (ndev->phydev) {
1159 if (ndev->phydev->speed == SPEED_1000)
1160 ecntl |= (1 << 5);
1161 else if (ndev->phydev->speed == SPEED_100)
1162 rcntl &= ~FEC_RCR_10BASET;
1163 else
1164 rcntl |= FEC_RCR_10BASET;
1165 }
1166 } else {
1167#ifdef FEC_MIIGSK_ENR
1168 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1169 u32 cfgr;
1170 /* disable the gasket and wait */
1171 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1172 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1173 udelay(1);
1174
1175 /*
1176 * configure the gasket:
1177 * RMII, 50 MHz, no loopback, no echo
1178 * MII, 25 MHz, no loopback, no echo
1179 */
1180 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1181 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1182 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1183 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1184 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1185
1186 /* re-enable the gasket */
1187 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1188 }
1189#endif
1190 }
1191
1192#if !defined(CONFIG_M5272)
1193 /* enable pause frame*/
1194 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1195 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1196 ndev->phydev && ndev->phydev->pause)) {
1197 rcntl |= FEC_RCR_FLOWCTL;
1198
1199 /* set FIFO threshold parameter to reduce overrun */
1200 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1201 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1202 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1203 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1204
1205 /* OPD */
1206 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1207 } else {
1208 rcntl &= ~FEC_RCR_FLOWCTL;
1209 }
1210#endif /* !defined(CONFIG_M5272) */
1211
1212 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1213
1214 /* Setup multicast filter. */
1215 set_multicast_list(ndev);
1216#ifndef CONFIG_M5272
1217 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1218 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1219#endif
1220
1221 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1222 /* enable ENET endian swap */
1223 ecntl |= FEC_ECR_BYTESWP;
1224 /* enable ENET store and forward mode */
1225 writel(FEC_TXWMRK_STRFWD, fep->hwp + FEC_X_WMRK);
1226 }
1227
1228 if (fep->bufdesc_ex)
1229 ecntl |= FEC_ECR_EN1588;
1230
1231 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT &&
1232 fep->rgmii_txc_dly)
1233 ecntl |= FEC_ENET_TXC_DLY;
1234 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT &&
1235 fep->rgmii_rxc_dly)
1236 ecntl |= FEC_ENET_RXC_DLY;
1237
1238#ifndef CONFIG_M5272
1239 /* Enable the MIB statistic event counters */
1240 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1241#endif
1242
1243 /* And last, enable the transmit and receive processing */
1244 writel(ecntl, fep->hwp + FEC_ECNTRL);
1245 fec_enet_active_rxring(ndev);
1246
1247 if (fep->bufdesc_ex)
1248 fec_ptp_start_cyclecounter(ndev);
1249
1250 /* Enable interrupts we wish to service */
1251 if (fep->link)
1252 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1253 else
1254 writel(0, fep->hwp + FEC_IMASK);
1255
1256 /* Init the interrupt coalescing */
1257 if (fep->quirks & FEC_QUIRK_HAS_COALESCE)
1258 fec_enet_itr_coal_set(ndev);
1259}
1260
1261static int fec_enet_ipc_handle_init(struct fec_enet_private *fep)
1262{
1263 if (!(of_machine_is_compatible("fsl,imx8qm") ||
1264 of_machine_is_compatible("fsl,imx8qxp") ||
1265 of_machine_is_compatible("fsl,imx8dxl")))
1266 return 0;
1267
1268 return imx_scu_get_handle(&fep->ipc_handle);
1269}
1270
1271static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled)
1272{
1273 struct device_node *np = fep->pdev->dev.of_node;
1274 u32 rsrc_id, val;
1275 int idx;
1276
1277 if (!np || !fep->ipc_handle)
1278 return;
1279
1280 idx = of_alias_get_id(np, "ethernet");
1281 if (idx < 0)
1282 idx = 0;
1283 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0;
1284
1285 val = enabled ? 1 : 0;
1286 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val);
1287}
1288
1289static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled)
1290{
1291 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1292 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr;
1293
1294 if (stop_gpr->gpr) {
1295 if (enabled)
1296 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1297 BIT(stop_gpr->bit),
1298 BIT(stop_gpr->bit));
1299 else
1300 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1301 BIT(stop_gpr->bit), 0);
1302 } else if (pdata && pdata->sleep_mode_enable) {
1303 pdata->sleep_mode_enable(enabled);
1304 } else {
1305 fec_enet_ipg_stop_set(fep, enabled);
1306 }
1307}
1308
1309static void fec_irqs_disable(struct net_device *ndev)
1310{
1311 struct fec_enet_private *fep = netdev_priv(ndev);
1312
1313 writel(0, fep->hwp + FEC_IMASK);
1314}
1315
1316static void fec_irqs_disable_except_wakeup(struct net_device *ndev)
1317{
1318 struct fec_enet_private *fep = netdev_priv(ndev);
1319
1320 writel(0, fep->hwp + FEC_IMASK);
1321 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1322}
1323
1324static void
1325fec_stop(struct net_device *ndev)
1326{
1327 struct fec_enet_private *fep = netdev_priv(ndev);
1328 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & FEC_RCR_RMII;
1329 u32 val;
1330
1331 /* We cannot expect a graceful transmit stop without link !!! */
1332 if (fep->link) {
1333 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1334 udelay(10);
1335 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1336 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1337 }
1338
1339 /* Whack a reset. We should wait for this.
1340 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1341 * instead of reset MAC itself.
1342 */
1343 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1344 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
1345 writel(0, fep->hwp + FEC_ECNTRL);
1346 } else {
1347 writel(FEC_ECR_RESET, fep->hwp + FEC_ECNTRL);
1348 udelay(10);
1349 }
1350 } else {
1351 val = readl(fep->hwp + FEC_ECNTRL);
1352 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1353 writel(val, fep->hwp + FEC_ECNTRL);
1354 }
1355 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1356 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1357
1358 /* We have to keep ENET enabled to have MII interrupt stay working */
1359 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1360 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1361 writel(FEC_ECR_ETHEREN, fep->hwp + FEC_ECNTRL);
1362 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1363 }
1364}
1365
1366static void
1367fec_timeout(struct net_device *ndev, unsigned int txqueue)
1368{
1369 struct fec_enet_private *fep = netdev_priv(ndev);
1370
1371 fec_dump(ndev);
1372
1373 ndev->stats.tx_errors++;
1374
1375 schedule_work(&fep->tx_timeout_work);
1376}
1377
1378static void fec_enet_timeout_work(struct work_struct *work)
1379{
1380 struct fec_enet_private *fep =
1381 container_of(work, struct fec_enet_private, tx_timeout_work);
1382 struct net_device *ndev = fep->netdev;
1383
1384 rtnl_lock();
1385 if (netif_device_present(ndev) || netif_running(ndev)) {
1386 napi_disable(&fep->napi);
1387 netif_tx_lock_bh(ndev);
1388 fec_restart(ndev);
1389 netif_tx_wake_all_queues(ndev);
1390 netif_tx_unlock_bh(ndev);
1391 napi_enable(&fep->napi);
1392 }
1393 rtnl_unlock();
1394}
1395
1396static void
1397fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1398 struct skb_shared_hwtstamps *hwtstamps)
1399{
1400 unsigned long flags;
1401 u64 ns;
1402
1403 spin_lock_irqsave(&fep->tmreg_lock, flags);
1404 ns = timecounter_cyc2time(&fep->tc, ts);
1405 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1406
1407 memset(hwtstamps, 0, sizeof(*hwtstamps));
1408 hwtstamps->hwtstamp = ns_to_ktime(ns);
1409}
1410
1411static void
1412fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget)
1413{
1414 struct fec_enet_private *fep;
1415 struct xdp_frame *xdpf;
1416 struct bufdesc *bdp;
1417 unsigned short status;
1418 struct sk_buff *skb;
1419 struct fec_enet_priv_tx_q *txq;
1420 struct netdev_queue *nq;
1421 int index = 0;
1422 int entries_free;
1423 struct page *page;
1424 int frame_len;
1425
1426 fep = netdev_priv(ndev);
1427
1428 txq = fep->tx_queue[queue_id];
1429 /* get next bdp of dirty_tx */
1430 nq = netdev_get_tx_queue(ndev, queue_id);
1431 bdp = txq->dirty_tx;
1432
1433 /* get next bdp of dirty_tx */
1434 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1435
1436 while (bdp != READ_ONCE(txq->bd.cur)) {
1437 /* Order the load of bd.cur and cbd_sc */
1438 rmb();
1439 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1440 if (status & BD_ENET_TX_READY)
1441 break;
1442
1443 index = fec_enet_get_bd_index(bdp, &txq->bd);
1444
1445 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) {
1446 skb = txq->tx_buf[index].buf_p;
1447 if (bdp->cbd_bufaddr &&
1448 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1449 dma_unmap_single(&fep->pdev->dev,
1450 fec32_to_cpu(bdp->cbd_bufaddr),
1451 fec16_to_cpu(bdp->cbd_datlen),
1452 DMA_TO_DEVICE);
1453 bdp->cbd_bufaddr = cpu_to_fec32(0);
1454 if (!skb)
1455 goto tx_buf_done;
1456 } else {
1457 /* Tx processing cannot call any XDP (or page pool) APIs if
1458 * the "budget" is 0. Because NAPI is called with budget of
1459 * 0 (such as netpoll) indicates we may be in an IRQ context,
1460 * however, we can't use the page pool from IRQ context.
1461 */
1462 if (unlikely(!budget))
1463 break;
1464
1465 if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) {
1466 xdpf = txq->tx_buf[index].buf_p;
1467 if (bdp->cbd_bufaddr)
1468 dma_unmap_single(&fep->pdev->dev,
1469 fec32_to_cpu(bdp->cbd_bufaddr),
1470 fec16_to_cpu(bdp->cbd_datlen),
1471 DMA_TO_DEVICE);
1472 } else {
1473 page = txq->tx_buf[index].buf_p;
1474 }
1475
1476 bdp->cbd_bufaddr = cpu_to_fec32(0);
1477 if (unlikely(!txq->tx_buf[index].buf_p)) {
1478 txq->tx_buf[index].type = FEC_TXBUF_T_SKB;
1479 goto tx_buf_done;
1480 }
1481
1482 frame_len = fec16_to_cpu(bdp->cbd_datlen);
1483 }
1484
1485 /* Check for errors. */
1486 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1487 BD_ENET_TX_RL | BD_ENET_TX_UN |
1488 BD_ENET_TX_CSL)) {
1489 ndev->stats.tx_errors++;
1490 if (status & BD_ENET_TX_HB) /* No heartbeat */
1491 ndev->stats.tx_heartbeat_errors++;
1492 if (status & BD_ENET_TX_LC) /* Late collision */
1493 ndev->stats.tx_window_errors++;
1494 if (status & BD_ENET_TX_RL) /* Retrans limit */
1495 ndev->stats.tx_aborted_errors++;
1496 if (status & BD_ENET_TX_UN) /* Underrun */
1497 ndev->stats.tx_fifo_errors++;
1498 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1499 ndev->stats.tx_carrier_errors++;
1500 } else {
1501 ndev->stats.tx_packets++;
1502
1503 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB)
1504 ndev->stats.tx_bytes += skb->len;
1505 else
1506 ndev->stats.tx_bytes += frame_len;
1507 }
1508
1509 /* Deferred means some collisions occurred during transmit,
1510 * but we eventually sent the packet OK.
1511 */
1512 if (status & BD_ENET_TX_DEF)
1513 ndev->stats.collisions++;
1514
1515 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) {
1516 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who
1517 * are to time stamp the packet, so we still need to check time
1518 * stamping enabled flag.
1519 */
1520 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS &&
1521 fep->hwts_tx_en) && fep->bufdesc_ex) {
1522 struct skb_shared_hwtstamps shhwtstamps;
1523 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1524
1525 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1526 skb_tstamp_tx(skb, &shhwtstamps);
1527 }
1528
1529 /* Free the sk buffer associated with this last transmit */
1530 napi_consume_skb(skb, budget);
1531 } else if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) {
1532 xdp_return_frame_rx_napi(xdpf);
1533 } else { /* recycle pages of XDP_TX frames */
1534 /* The dma_sync_size = 0 as XDP_TX has already synced DMA for_device */
1535 page_pool_put_page(page->pp, page, 0, true);
1536 }
1537
1538 txq->tx_buf[index].buf_p = NULL;
1539 /* restore default tx buffer type: FEC_TXBUF_T_SKB */
1540 txq->tx_buf[index].type = FEC_TXBUF_T_SKB;
1541
1542tx_buf_done:
1543 /* Make sure the update to bdp and tx_buf are performed
1544 * before dirty_tx
1545 */
1546 wmb();
1547 txq->dirty_tx = bdp;
1548
1549 /* Update pointer to next buffer descriptor to be transmitted */
1550 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1551
1552 /* Since we have freed up a buffer, the ring is no longer full
1553 */
1554 if (netif_tx_queue_stopped(nq)) {
1555 entries_free = fec_enet_get_free_txdesc_num(txq);
1556 if (entries_free >= txq->tx_wake_threshold)
1557 netif_tx_wake_queue(nq);
1558 }
1559 }
1560
1561 /* ERR006358: Keep the transmitter going */
1562 if (bdp != txq->bd.cur &&
1563 readl(txq->bd.reg_desc_active) == 0)
1564 writel(0, txq->bd.reg_desc_active);
1565}
1566
1567static void fec_enet_tx(struct net_device *ndev, int budget)
1568{
1569 struct fec_enet_private *fep = netdev_priv(ndev);
1570 int i;
1571
1572 /* Make sure that AVB queues are processed first. */
1573 for (i = fep->num_tx_queues - 1; i >= 0; i--)
1574 fec_enet_tx_queue(ndev, i, budget);
1575}
1576
1577static void fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq,
1578 struct bufdesc *bdp, int index)
1579{
1580 struct page *new_page;
1581 dma_addr_t phys_addr;
1582
1583 new_page = page_pool_dev_alloc_pages(rxq->page_pool);
1584 WARN_ON(!new_page);
1585 rxq->rx_skb_info[index].page = new_page;
1586
1587 rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM;
1588 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM;
1589 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr);
1590}
1591
1592static u32
1593fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog,
1594 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int cpu)
1595{
1596 unsigned int sync, len = xdp->data_end - xdp->data;
1597 u32 ret = FEC_ENET_XDP_PASS;
1598 struct page *page;
1599 int err;
1600 u32 act;
1601
1602 act = bpf_prog_run_xdp(prog, xdp);
1603
1604 /* Due xdp_adjust_tail and xdp_adjust_head: DMA sync for_device cover
1605 * max len CPU touch
1606 */
1607 sync = xdp->data_end - xdp->data;
1608 sync = max(sync, len);
1609
1610 switch (act) {
1611 case XDP_PASS:
1612 rxq->stats[RX_XDP_PASS]++;
1613 ret = FEC_ENET_XDP_PASS;
1614 break;
1615
1616 case XDP_REDIRECT:
1617 rxq->stats[RX_XDP_REDIRECT]++;
1618 err = xdp_do_redirect(fep->netdev, xdp, prog);
1619 if (unlikely(err))
1620 goto xdp_err;
1621
1622 ret = FEC_ENET_XDP_REDIR;
1623 break;
1624
1625 case XDP_TX:
1626 rxq->stats[RX_XDP_TX]++;
1627 err = fec_enet_xdp_tx_xmit(fep, cpu, xdp, sync);
1628 if (unlikely(err)) {
1629 rxq->stats[RX_XDP_TX_ERRORS]++;
1630 goto xdp_err;
1631 }
1632
1633 ret = FEC_ENET_XDP_TX;
1634 break;
1635
1636 default:
1637 bpf_warn_invalid_xdp_action(fep->netdev, prog, act);
1638 fallthrough;
1639
1640 case XDP_ABORTED:
1641 fallthrough; /* handle aborts by dropping packet */
1642
1643 case XDP_DROP:
1644 rxq->stats[RX_XDP_DROP]++;
1645xdp_err:
1646 ret = FEC_ENET_XDP_CONSUMED;
1647 page = virt_to_head_page(xdp->data);
1648 page_pool_put_page(rxq->page_pool, page, sync, true);
1649 if (act != XDP_DROP)
1650 trace_xdp_exception(fep->netdev, prog, act);
1651 break;
1652 }
1653
1654 return ret;
1655}
1656
1657/* During a receive, the bd_rx.cur points to the current incoming buffer.
1658 * When we update through the ring, if the next incoming buffer has
1659 * not been given to the system, we just set the empty indicator,
1660 * effectively tossing the packet.
1661 */
1662static int
1663fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1664{
1665 struct fec_enet_private *fep = netdev_priv(ndev);
1666 struct fec_enet_priv_rx_q *rxq;
1667 struct bufdesc *bdp;
1668 unsigned short status;
1669 struct sk_buff *skb;
1670 ushort pkt_len;
1671 __u8 *data;
1672 int pkt_received = 0;
1673 struct bufdesc_ex *ebdp = NULL;
1674 bool vlan_packet_rcvd = false;
1675 u16 vlan_tag;
1676 int index = 0;
1677 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1678 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog);
1679 u32 ret, xdp_result = FEC_ENET_XDP_PASS;
1680 u32 data_start = FEC_ENET_XDP_HEADROOM;
1681 int cpu = smp_processor_id();
1682 struct xdp_buff xdp;
1683 struct page *page;
1684 u32 sub_len = 4;
1685
1686#if !defined(CONFIG_M5272)
1687 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of
1688 * FEC_RACC_SHIFT16 is set by default in the probe function.
1689 */
1690 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
1691 data_start += 2;
1692 sub_len += 2;
1693 }
1694#endif
1695
1696#if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA)
1697 /*
1698 * Hacky flush of all caches instead of using the DMA API for the TSO
1699 * headers.
1700 */
1701 flush_cache_all();
1702#endif
1703 rxq = fep->rx_queue[queue_id];
1704
1705 /* First, grab all of the stats for the incoming packet.
1706 * These get messed up if we get called due to a busy condition.
1707 */
1708 bdp = rxq->bd.cur;
1709 xdp_init_buff(&xdp, PAGE_SIZE, &rxq->xdp_rxq);
1710
1711 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1712
1713 if (pkt_received >= budget)
1714 break;
1715 pkt_received++;
1716
1717 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT);
1718
1719 /* Check for errors. */
1720 status ^= BD_ENET_RX_LAST;
1721 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1722 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1723 BD_ENET_RX_CL)) {
1724 ndev->stats.rx_errors++;
1725 if (status & BD_ENET_RX_OV) {
1726 /* FIFO overrun */
1727 ndev->stats.rx_fifo_errors++;
1728 goto rx_processing_done;
1729 }
1730 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1731 | BD_ENET_RX_LAST)) {
1732 /* Frame too long or too short. */
1733 ndev->stats.rx_length_errors++;
1734 if (status & BD_ENET_RX_LAST)
1735 netdev_err(ndev, "rcv is not +last\n");
1736 }
1737 if (status & BD_ENET_RX_CR) /* CRC Error */
1738 ndev->stats.rx_crc_errors++;
1739 /* Report late collisions as a frame error. */
1740 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1741 ndev->stats.rx_frame_errors++;
1742 goto rx_processing_done;
1743 }
1744
1745 /* Process the incoming frame. */
1746 ndev->stats.rx_packets++;
1747 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1748 ndev->stats.rx_bytes += pkt_len;
1749
1750 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1751 page = rxq->rx_skb_info[index].page;
1752 dma_sync_single_for_cpu(&fep->pdev->dev,
1753 fec32_to_cpu(bdp->cbd_bufaddr),
1754 pkt_len,
1755 DMA_FROM_DEVICE);
1756 prefetch(page_address(page));
1757 fec_enet_update_cbd(rxq, bdp, index);
1758
1759 if (xdp_prog) {
1760 xdp_buff_clear_frags_flag(&xdp);
1761 /* subtract 16bit shift and FCS */
1762 xdp_prepare_buff(&xdp, page_address(page),
1763 data_start, pkt_len - sub_len, false);
1764 ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, cpu);
1765 xdp_result |= ret;
1766 if (ret != FEC_ENET_XDP_PASS)
1767 goto rx_processing_done;
1768 }
1769
1770 /* The packet length includes FCS, but we don't want to
1771 * include that when passing upstream as it messes up
1772 * bridging applications.
1773 */
1774 skb = build_skb(page_address(page), PAGE_SIZE);
1775 if (unlikely(!skb)) {
1776 page_pool_recycle_direct(rxq->page_pool, page);
1777 ndev->stats.rx_dropped++;
1778
1779 netdev_err_once(ndev, "build_skb failed!\n");
1780 goto rx_processing_done;
1781 }
1782
1783 skb_reserve(skb, data_start);
1784 skb_put(skb, pkt_len - sub_len);
1785 skb_mark_for_recycle(skb);
1786
1787 if (unlikely(need_swap)) {
1788 data = page_address(page) + FEC_ENET_XDP_HEADROOM;
1789 swap_buffer(data, pkt_len);
1790 }
1791 data = skb->data;
1792
1793 /* Extract the enhanced buffer descriptor */
1794 ebdp = NULL;
1795 if (fep->bufdesc_ex)
1796 ebdp = (struct bufdesc_ex *)bdp;
1797
1798 /* If this is a VLAN packet remove the VLAN Tag */
1799 vlan_packet_rcvd = false;
1800 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1801 fep->bufdesc_ex &&
1802 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1803 /* Push and remove the vlan tag */
1804 struct vlan_hdr *vlan_header =
1805 (struct vlan_hdr *) (data + ETH_HLEN);
1806 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1807
1808 vlan_packet_rcvd = true;
1809
1810 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1811 skb_pull(skb, VLAN_HLEN);
1812 }
1813
1814 skb->protocol = eth_type_trans(skb, ndev);
1815
1816 /* Get receive timestamp from the skb */
1817 if (fep->hwts_rx_en && fep->bufdesc_ex)
1818 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1819 skb_hwtstamps(skb));
1820
1821 if (fep->bufdesc_ex &&
1822 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1823 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1824 /* don't check it */
1825 skb->ip_summed = CHECKSUM_UNNECESSARY;
1826 } else {
1827 skb_checksum_none_assert(skb);
1828 }
1829 }
1830
1831 /* Handle received VLAN packets */
1832 if (vlan_packet_rcvd)
1833 __vlan_hwaccel_put_tag(skb,
1834 htons(ETH_P_8021Q),
1835 vlan_tag);
1836
1837 skb_record_rx_queue(skb, queue_id);
1838 napi_gro_receive(&fep->napi, skb);
1839
1840rx_processing_done:
1841 /* Clear the status flags for this buffer */
1842 status &= ~BD_ENET_RX_STATS;
1843
1844 /* Mark the buffer empty */
1845 status |= BD_ENET_RX_EMPTY;
1846
1847 if (fep->bufdesc_ex) {
1848 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1849
1850 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1851 ebdp->cbd_prot = 0;
1852 ebdp->cbd_bdu = 0;
1853 }
1854 /* Make sure the updates to rest of the descriptor are
1855 * performed before transferring ownership.
1856 */
1857 wmb();
1858 bdp->cbd_sc = cpu_to_fec16(status);
1859
1860 /* Update BD pointer to next entry */
1861 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1862
1863 /* Doing this here will keep the FEC running while we process
1864 * incoming frames. On a heavily loaded network, we should be
1865 * able to keep up at the expense of system resources.
1866 */
1867 writel(0, rxq->bd.reg_desc_active);
1868 }
1869 rxq->bd.cur = bdp;
1870
1871 if (xdp_result & FEC_ENET_XDP_REDIR)
1872 xdp_do_flush();
1873
1874 return pkt_received;
1875}
1876
1877static int fec_enet_rx(struct net_device *ndev, int budget)
1878{
1879 struct fec_enet_private *fep = netdev_priv(ndev);
1880 int i, done = 0;
1881
1882 /* Make sure that AVB queues are processed first. */
1883 for (i = fep->num_rx_queues - 1; i >= 0; i--)
1884 done += fec_enet_rx_queue(ndev, budget - done, i);
1885
1886 return done;
1887}
1888
1889static bool fec_enet_collect_events(struct fec_enet_private *fep)
1890{
1891 uint int_events;
1892
1893 int_events = readl(fep->hwp + FEC_IEVENT);
1894
1895 /* Don't clear MDIO events, we poll for those */
1896 int_events &= ~FEC_ENET_MII;
1897
1898 writel(int_events, fep->hwp + FEC_IEVENT);
1899
1900 return int_events != 0;
1901}
1902
1903static irqreturn_t
1904fec_enet_interrupt(int irq, void *dev_id)
1905{
1906 struct net_device *ndev = dev_id;
1907 struct fec_enet_private *fep = netdev_priv(ndev);
1908 irqreturn_t ret = IRQ_NONE;
1909
1910 if (fec_enet_collect_events(fep) && fep->link) {
1911 ret = IRQ_HANDLED;
1912
1913 if (napi_schedule_prep(&fep->napi)) {
1914 /* Disable interrupts */
1915 writel(0, fep->hwp + FEC_IMASK);
1916 __napi_schedule(&fep->napi);
1917 }
1918 }
1919
1920 return ret;
1921}
1922
1923static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1924{
1925 struct net_device *ndev = napi->dev;
1926 struct fec_enet_private *fep = netdev_priv(ndev);
1927 int done = 0;
1928
1929 do {
1930 done += fec_enet_rx(ndev, budget - done);
1931 fec_enet_tx(ndev, budget);
1932 } while ((done < budget) && fec_enet_collect_events(fep));
1933
1934 if (done < budget) {
1935 napi_complete_done(napi, done);
1936 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1937 }
1938
1939 return done;
1940}
1941
1942/* ------------------------------------------------------------------------- */
1943static int fec_get_mac(struct net_device *ndev)
1944{
1945 struct fec_enet_private *fep = netdev_priv(ndev);
1946 unsigned char *iap, tmpaddr[ETH_ALEN];
1947 int ret;
1948
1949 /*
1950 * try to get mac address in following order:
1951 *
1952 * 1) module parameter via kernel command line in form
1953 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1954 */
1955 iap = macaddr;
1956
1957 /*
1958 * 2) from device tree data
1959 */
1960 if (!is_valid_ether_addr(iap)) {
1961 struct device_node *np = fep->pdev->dev.of_node;
1962 if (np) {
1963 ret = of_get_mac_address(np, tmpaddr);
1964 if (!ret)
1965 iap = tmpaddr;
1966 else if (ret == -EPROBE_DEFER)
1967 return ret;
1968 }
1969 }
1970
1971 /*
1972 * 3) from flash or fuse (via platform data)
1973 */
1974 if (!is_valid_ether_addr(iap)) {
1975#ifdef CONFIG_M5272
1976 if (FEC_FLASHMAC)
1977 iap = (unsigned char *)FEC_FLASHMAC;
1978#else
1979 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1980
1981 if (pdata)
1982 iap = (unsigned char *)&pdata->mac;
1983#endif
1984 }
1985
1986 /*
1987 * 4) FEC mac registers set by bootloader
1988 */
1989 if (!is_valid_ether_addr(iap)) {
1990 *((__be32 *) &tmpaddr[0]) =
1991 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1992 *((__be16 *) &tmpaddr[4]) =
1993 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1994 iap = &tmpaddr[0];
1995 }
1996
1997 /*
1998 * 5) random mac address
1999 */
2000 if (!is_valid_ether_addr(iap)) {
2001 /* Report it and use a random ethernet address instead */
2002 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap);
2003 eth_hw_addr_random(ndev);
2004 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n",
2005 ndev->dev_addr);
2006 return 0;
2007 }
2008
2009 /* Adjust MAC if using macaddr */
2010 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0);
2011
2012 return 0;
2013}
2014
2015/* ------------------------------------------------------------------------- */
2016
2017/*
2018 * Phy section
2019 */
2020
2021/* LPI Sleep Ts count base on tx clk (clk_ref).
2022 * The lpi sleep cnt value = X us / (cycle_ns).
2023 */
2024static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us)
2025{
2026 struct fec_enet_private *fep = netdev_priv(ndev);
2027
2028 return us * (fep->clk_ref_rate / 1000) / 1000;
2029}
2030
2031static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable)
2032{
2033 struct fec_enet_private *fep = netdev_priv(ndev);
2034 struct ethtool_keee *p = &fep->eee;
2035 unsigned int sleep_cycle, wake_cycle;
2036
2037 if (enable) {
2038 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer);
2039 wake_cycle = sleep_cycle;
2040 } else {
2041 sleep_cycle = 0;
2042 wake_cycle = 0;
2043 }
2044
2045 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP);
2046 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE);
2047
2048 return 0;
2049}
2050
2051static void fec_enet_adjust_link(struct net_device *ndev)
2052{
2053 struct fec_enet_private *fep = netdev_priv(ndev);
2054 struct phy_device *phy_dev = ndev->phydev;
2055 int status_change = 0;
2056
2057 /*
2058 * If the netdev is down, or is going down, we're not interested
2059 * in link state events, so just mark our idea of the link as down
2060 * and ignore the event.
2061 */
2062 if (!netif_running(ndev) || !netif_device_present(ndev)) {
2063 fep->link = 0;
2064 } else if (phy_dev->link) {
2065 if (!fep->link) {
2066 fep->link = phy_dev->link;
2067 status_change = 1;
2068 }
2069
2070 if (fep->full_duplex != phy_dev->duplex) {
2071 fep->full_duplex = phy_dev->duplex;
2072 status_change = 1;
2073 }
2074
2075 if (phy_dev->speed != fep->speed) {
2076 fep->speed = phy_dev->speed;
2077 status_change = 1;
2078 }
2079
2080 /* if any of the above changed restart the FEC */
2081 if (status_change) {
2082 netif_stop_queue(ndev);
2083 napi_disable(&fep->napi);
2084 netif_tx_lock_bh(ndev);
2085 fec_restart(ndev);
2086 netif_tx_wake_all_queues(ndev);
2087 netif_tx_unlock_bh(ndev);
2088 napi_enable(&fep->napi);
2089 }
2090 if (fep->quirks & FEC_QUIRK_HAS_EEE)
2091 fec_enet_eee_mode_set(ndev, phy_dev->enable_tx_lpi);
2092 } else {
2093 if (fep->link) {
2094 netif_stop_queue(ndev);
2095 napi_disable(&fep->napi);
2096 netif_tx_lock_bh(ndev);
2097 fec_stop(ndev);
2098 netif_tx_unlock_bh(ndev);
2099 napi_enable(&fep->napi);
2100 fep->link = phy_dev->link;
2101 status_change = 1;
2102 }
2103 }
2104
2105 if (status_change)
2106 phy_print_status(phy_dev);
2107}
2108
2109static int fec_enet_mdio_wait(struct fec_enet_private *fep)
2110{
2111 uint ievent;
2112 int ret;
2113
2114 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent,
2115 ievent & FEC_ENET_MII, 2, 30000);
2116
2117 if (!ret)
2118 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
2119
2120 return ret;
2121}
2122
2123static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum)
2124{
2125 struct fec_enet_private *fep = bus->priv;
2126 struct device *dev = &fep->pdev->dev;
2127 int ret = 0, frame_start, frame_addr, frame_op;
2128
2129 ret = pm_runtime_resume_and_get(dev);
2130 if (ret < 0)
2131 return ret;
2132
2133 /* C22 read */
2134 frame_op = FEC_MMFR_OP_READ;
2135 frame_start = FEC_MMFR_ST;
2136 frame_addr = regnum;
2137
2138 /* start a read op */
2139 writel(frame_start | frame_op |
2140 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
2141 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
2142
2143 /* wait for end of transfer */
2144 ret = fec_enet_mdio_wait(fep);
2145 if (ret) {
2146 netdev_err(fep->netdev, "MDIO read timeout\n");
2147 goto out;
2148 }
2149
2150 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
2151
2152out:
2153 pm_runtime_mark_last_busy(dev);
2154 pm_runtime_put_autosuspend(dev);
2155
2156 return ret;
2157}
2158
2159static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id,
2160 int devad, int regnum)
2161{
2162 struct fec_enet_private *fep = bus->priv;
2163 struct device *dev = &fep->pdev->dev;
2164 int ret = 0, frame_start, frame_op;
2165
2166 ret = pm_runtime_resume_and_get(dev);
2167 if (ret < 0)
2168 return ret;
2169
2170 frame_start = FEC_MMFR_ST_C45;
2171
2172 /* write address */
2173 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
2174 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2175 FEC_MMFR_TA | (regnum & 0xFFFF),
2176 fep->hwp + FEC_MII_DATA);
2177
2178 /* wait for end of transfer */
2179 ret = fec_enet_mdio_wait(fep);
2180 if (ret) {
2181 netdev_err(fep->netdev, "MDIO address write timeout\n");
2182 goto out;
2183 }
2184
2185 frame_op = FEC_MMFR_OP_READ_C45;
2186
2187 /* start a read op */
2188 writel(frame_start | frame_op |
2189 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2190 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
2191
2192 /* wait for end of transfer */
2193 ret = fec_enet_mdio_wait(fep);
2194 if (ret) {
2195 netdev_err(fep->netdev, "MDIO read timeout\n");
2196 goto out;
2197 }
2198
2199 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
2200
2201out:
2202 pm_runtime_mark_last_busy(dev);
2203 pm_runtime_put_autosuspend(dev);
2204
2205 return ret;
2206}
2207
2208static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,
2209 u16 value)
2210{
2211 struct fec_enet_private *fep = bus->priv;
2212 struct device *dev = &fep->pdev->dev;
2213 int ret, frame_start, frame_addr;
2214
2215 ret = pm_runtime_resume_and_get(dev);
2216 if (ret < 0)
2217 return ret;
2218
2219 /* C22 write */
2220 frame_start = FEC_MMFR_ST;
2221 frame_addr = regnum;
2222
2223 /* start a write op */
2224 writel(frame_start | FEC_MMFR_OP_WRITE |
2225 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
2226 FEC_MMFR_TA | FEC_MMFR_DATA(value),
2227 fep->hwp + FEC_MII_DATA);
2228
2229 /* wait for end of transfer */
2230 ret = fec_enet_mdio_wait(fep);
2231 if (ret)
2232 netdev_err(fep->netdev, "MDIO write timeout\n");
2233
2234 pm_runtime_mark_last_busy(dev);
2235 pm_runtime_put_autosuspend(dev);
2236
2237 return ret;
2238}
2239
2240static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id,
2241 int devad, int regnum, u16 value)
2242{
2243 struct fec_enet_private *fep = bus->priv;
2244 struct device *dev = &fep->pdev->dev;
2245 int ret, frame_start;
2246
2247 ret = pm_runtime_resume_and_get(dev);
2248 if (ret < 0)
2249 return ret;
2250
2251 frame_start = FEC_MMFR_ST_C45;
2252
2253 /* write address */
2254 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
2255 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2256 FEC_MMFR_TA | (regnum & 0xFFFF),
2257 fep->hwp + FEC_MII_DATA);
2258
2259 /* wait for end of transfer */
2260 ret = fec_enet_mdio_wait(fep);
2261 if (ret) {
2262 netdev_err(fep->netdev, "MDIO address write timeout\n");
2263 goto out;
2264 }
2265
2266 /* start a write op */
2267 writel(frame_start | FEC_MMFR_OP_WRITE |
2268 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2269 FEC_MMFR_TA | FEC_MMFR_DATA(value),
2270 fep->hwp + FEC_MII_DATA);
2271
2272 /* wait for end of transfer */
2273 ret = fec_enet_mdio_wait(fep);
2274 if (ret)
2275 netdev_err(fep->netdev, "MDIO write timeout\n");
2276
2277out:
2278 pm_runtime_mark_last_busy(dev);
2279 pm_runtime_put_autosuspend(dev);
2280
2281 return ret;
2282}
2283
2284static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev)
2285{
2286 struct fec_enet_private *fep = netdev_priv(ndev);
2287 struct phy_device *phy_dev = ndev->phydev;
2288
2289 if (phy_dev) {
2290 phy_reset_after_clk_enable(phy_dev);
2291 } else if (fep->phy_node) {
2292 /*
2293 * If the PHY still is not bound to the MAC, but there is
2294 * OF PHY node and a matching PHY device instance already,
2295 * use the OF PHY node to obtain the PHY device instance,
2296 * and then use that PHY device instance when triggering
2297 * the PHY reset.
2298 */
2299 phy_dev = of_phy_find_device(fep->phy_node);
2300 phy_reset_after_clk_enable(phy_dev);
2301 put_device(&phy_dev->mdio.dev);
2302 }
2303}
2304
2305static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
2306{
2307 struct fec_enet_private *fep = netdev_priv(ndev);
2308 int ret;
2309
2310 if (enable) {
2311 ret = clk_prepare_enable(fep->clk_enet_out);
2312 if (ret)
2313 return ret;
2314
2315 if (fep->clk_ptp) {
2316 mutex_lock(&fep->ptp_clk_mutex);
2317 ret = clk_prepare_enable(fep->clk_ptp);
2318 if (ret) {
2319 mutex_unlock(&fep->ptp_clk_mutex);
2320 goto failed_clk_ptp;
2321 } else {
2322 fep->ptp_clk_on = true;
2323 }
2324 mutex_unlock(&fep->ptp_clk_mutex);
2325 }
2326
2327 ret = clk_prepare_enable(fep->clk_ref);
2328 if (ret)
2329 goto failed_clk_ref;
2330
2331 ret = clk_prepare_enable(fep->clk_2x_txclk);
2332 if (ret)
2333 goto failed_clk_2x_txclk;
2334
2335 fec_enet_phy_reset_after_clk_enable(ndev);
2336 } else {
2337 clk_disable_unprepare(fep->clk_enet_out);
2338 if (fep->clk_ptp) {
2339 mutex_lock(&fep->ptp_clk_mutex);
2340 clk_disable_unprepare(fep->clk_ptp);
2341 fep->ptp_clk_on = false;
2342 mutex_unlock(&fep->ptp_clk_mutex);
2343 }
2344 clk_disable_unprepare(fep->clk_ref);
2345 clk_disable_unprepare(fep->clk_2x_txclk);
2346 }
2347
2348 return 0;
2349
2350failed_clk_2x_txclk:
2351 if (fep->clk_ref)
2352 clk_disable_unprepare(fep->clk_ref);
2353failed_clk_ref:
2354 if (fep->clk_ptp) {
2355 mutex_lock(&fep->ptp_clk_mutex);
2356 clk_disable_unprepare(fep->clk_ptp);
2357 fep->ptp_clk_on = false;
2358 mutex_unlock(&fep->ptp_clk_mutex);
2359 }
2360failed_clk_ptp:
2361 clk_disable_unprepare(fep->clk_enet_out);
2362
2363 return ret;
2364}
2365
2366static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep,
2367 struct device_node *np)
2368{
2369 u32 rgmii_tx_delay, rgmii_rx_delay;
2370
2371 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */
2372 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) {
2373 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) {
2374 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps");
2375 return -EINVAL;
2376 } else if (rgmii_tx_delay == 2000) {
2377 fep->rgmii_txc_dly = true;
2378 }
2379 }
2380
2381 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */
2382 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) {
2383 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) {
2384 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps");
2385 return -EINVAL;
2386 } else if (rgmii_rx_delay == 2000) {
2387 fep->rgmii_rxc_dly = true;
2388 }
2389 }
2390
2391 return 0;
2392}
2393
2394static int fec_enet_mii_probe(struct net_device *ndev)
2395{
2396 struct fec_enet_private *fep = netdev_priv(ndev);
2397 struct phy_device *phy_dev = NULL;
2398 char mdio_bus_id[MII_BUS_ID_SIZE];
2399 char phy_name[MII_BUS_ID_SIZE + 3];
2400 int phy_id;
2401 int dev_id = fep->dev_id;
2402
2403 if (fep->phy_node) {
2404 phy_dev = of_phy_connect(ndev, fep->phy_node,
2405 &fec_enet_adjust_link, 0,
2406 fep->phy_interface);
2407 if (!phy_dev) {
2408 netdev_err(ndev, "Unable to connect to phy\n");
2409 return -ENODEV;
2410 }
2411 } else {
2412 /* check for attached phy */
2413 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
2414 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
2415 continue;
2416 if (dev_id--)
2417 continue;
2418 strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
2419 break;
2420 }
2421
2422 if (phy_id >= PHY_MAX_ADDR) {
2423 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
2424 strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
2425 phy_id = 0;
2426 }
2427
2428 snprintf(phy_name, sizeof(phy_name),
2429 PHY_ID_FMT, mdio_bus_id, phy_id);
2430 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
2431 fep->phy_interface);
2432 }
2433
2434 if (IS_ERR(phy_dev)) {
2435 netdev_err(ndev, "could not attach to PHY\n");
2436 return PTR_ERR(phy_dev);
2437 }
2438
2439 /* mask with MAC supported features */
2440 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
2441 phy_set_max_speed(phy_dev, 1000);
2442 phy_remove_link_mode(phy_dev,
2443 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
2444#if !defined(CONFIG_M5272)
2445 phy_support_sym_pause(phy_dev);
2446#endif
2447 }
2448 else
2449 phy_set_max_speed(phy_dev, 100);
2450
2451 if (fep->quirks & FEC_QUIRK_HAS_EEE)
2452 phy_support_eee(phy_dev);
2453
2454 fep->link = 0;
2455 fep->full_duplex = 0;
2456
2457 phy_attached_info(phy_dev);
2458
2459 return 0;
2460}
2461
2462static int fec_enet_mii_init(struct platform_device *pdev)
2463{
2464 static struct mii_bus *fec0_mii_bus;
2465 struct net_device *ndev = platform_get_drvdata(pdev);
2466 struct fec_enet_private *fep = netdev_priv(ndev);
2467 bool suppress_preamble = false;
2468 struct phy_device *phydev;
2469 struct device_node *node;
2470 int err = -ENXIO;
2471 u32 mii_speed, holdtime;
2472 u32 bus_freq;
2473 int addr;
2474
2475 /*
2476 * The i.MX28 dual fec interfaces are not equal.
2477 * Here are the differences:
2478 *
2479 * - fec0 supports MII & RMII modes while fec1 only supports RMII
2480 * - fec0 acts as the 1588 time master while fec1 is slave
2481 * - external phys can only be configured by fec0
2482 *
2483 * That is to say fec1 can not work independently. It only works
2484 * when fec0 is working. The reason behind this design is that the
2485 * second interface is added primarily for Switch mode.
2486 *
2487 * Because of the last point above, both phys are attached on fec0
2488 * mdio interface in board design, and need to be configured by
2489 * fec0 mii_bus.
2490 */
2491 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
2492 /* fec1 uses fec0 mii_bus */
2493 if (mii_cnt && fec0_mii_bus) {
2494 fep->mii_bus = fec0_mii_bus;
2495 mii_cnt++;
2496 return 0;
2497 }
2498 return -ENOENT;
2499 }
2500
2501 bus_freq = 2500000; /* 2.5MHz by default */
2502 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2503 if (node) {
2504 of_property_read_u32(node, "clock-frequency", &bus_freq);
2505 suppress_preamble = of_property_read_bool(node,
2506 "suppress-preamble");
2507 }
2508
2509 /*
2510 * Set MII speed (= clk_get_rate() / 2 * phy_speed)
2511 *
2512 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2513 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2514 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2515 * document.
2516 */
2517 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2);
2518 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2519 mii_speed--;
2520 if (mii_speed > 63) {
2521 dev_err(&pdev->dev,
2522 "fec clock (%lu) too fast to get right mii speed\n",
2523 clk_get_rate(fep->clk_ipg));
2524 err = -EINVAL;
2525 goto err_out;
2526 }
2527
2528 /*
2529 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2530 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2531 * versions are RAZ there, so just ignore the difference and write the
2532 * register always.
2533 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2534 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2535 * output.
2536 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2537 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2538 * holdtime cannot result in a value greater than 3.
2539 */
2540 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2541
2542 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2543
2544 if (suppress_preamble)
2545 fep->phy_speed |= BIT(7);
2546
2547 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) {
2548 /* Clear MMFR to avoid to generate MII event by writing MSCR.
2549 * MII event generation condition:
2550 * - writing MSCR:
2551 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero &
2552 * mscr_reg_data_in[7:0] != 0
2553 * - writing MMFR:
2554 * - mscr[7:0]_not_zero
2555 */
2556 writel(0, fep->hwp + FEC_MII_DATA);
2557 }
2558
2559 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2560
2561 /* Clear any pending transaction complete indication */
2562 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
2563
2564 fep->mii_bus = mdiobus_alloc();
2565 if (fep->mii_bus == NULL) {
2566 err = -ENOMEM;
2567 goto err_out;
2568 }
2569
2570 fep->mii_bus->name = "fec_enet_mii_bus";
2571 fep->mii_bus->read = fec_enet_mdio_read_c22;
2572 fep->mii_bus->write = fec_enet_mdio_write_c22;
2573 if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) {
2574 fep->mii_bus->read_c45 = fec_enet_mdio_read_c45;
2575 fep->mii_bus->write_c45 = fec_enet_mdio_write_c45;
2576 }
2577 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2578 pdev->name, fep->dev_id + 1);
2579 fep->mii_bus->priv = fep;
2580 fep->mii_bus->parent = &pdev->dev;
2581
2582 err = of_mdiobus_register(fep->mii_bus, node);
2583 if (err)
2584 goto err_out_free_mdiobus;
2585 of_node_put(node);
2586
2587 /* find all the PHY devices on the bus and set mac_managed_pm to true */
2588 for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
2589 phydev = mdiobus_get_phy(fep->mii_bus, addr);
2590 if (phydev)
2591 phydev->mac_managed_pm = true;
2592 }
2593
2594 mii_cnt++;
2595
2596 /* save fec0 mii_bus */
2597 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2598 fec0_mii_bus = fep->mii_bus;
2599
2600 return 0;
2601
2602err_out_free_mdiobus:
2603 mdiobus_free(fep->mii_bus);
2604err_out:
2605 of_node_put(node);
2606 return err;
2607}
2608
2609static void fec_enet_mii_remove(struct fec_enet_private *fep)
2610{
2611 if (--mii_cnt == 0) {
2612 mdiobus_unregister(fep->mii_bus);
2613 mdiobus_free(fep->mii_bus);
2614 }
2615}
2616
2617static void fec_enet_get_drvinfo(struct net_device *ndev,
2618 struct ethtool_drvinfo *info)
2619{
2620 struct fec_enet_private *fep = netdev_priv(ndev);
2621
2622 strscpy(info->driver, fep->pdev->dev.driver->name,
2623 sizeof(info->driver));
2624 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2625}
2626
2627static int fec_enet_get_regs_len(struct net_device *ndev)
2628{
2629 struct fec_enet_private *fep = netdev_priv(ndev);
2630 struct resource *r;
2631 int s = 0;
2632
2633 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2634 if (r)
2635 s = resource_size(r);
2636
2637 return s;
2638}
2639
2640/* List of registers that can be safety be read to dump them with ethtool */
2641#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2642 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2643 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2644static __u32 fec_enet_register_version = 2;
2645static u32 fec_enet_register_offset[] = {
2646 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2647 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2648 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2649 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2650 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2651 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2652 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2653 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2654 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2655 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2656 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2657 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2658 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2659 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2660 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2661 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2662 RMON_T_P_GTE2048, RMON_T_OCTETS,
2663 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2664 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2665 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2666 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2667 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2668 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2669 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2670 RMON_R_P_GTE2048, RMON_R_OCTETS,
2671 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2672 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2673};
2674/* for i.MX6ul */
2675static u32 fec_enet_register_offset_6ul[] = {
2676 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2677 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2678 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0,
2679 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH,
2680 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0,
2681 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2682 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC,
2683 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2684 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2685 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2686 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2687 RMON_T_P_GTE2048, RMON_T_OCTETS,
2688 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2689 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2690 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2691 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2692 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2693 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2694 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2695 RMON_R_P_GTE2048, RMON_R_OCTETS,
2696 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2697 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2698};
2699#else
2700static __u32 fec_enet_register_version = 1;
2701static u32 fec_enet_register_offset[] = {
2702 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2703 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2704 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2705 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2706 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2707 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2708 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2709 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2710 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2711};
2712#endif
2713
2714static void fec_enet_get_regs(struct net_device *ndev,
2715 struct ethtool_regs *regs, void *regbuf)
2716{
2717 struct fec_enet_private *fep = netdev_priv(ndev);
2718 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2719 struct device *dev = &fep->pdev->dev;
2720 u32 *buf = (u32 *)regbuf;
2721 u32 i, off;
2722 int ret;
2723#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2724 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2725 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2726 u32 *reg_list;
2727 u32 reg_cnt;
2728
2729 if (!of_machine_is_compatible("fsl,imx6ul")) {
2730 reg_list = fec_enet_register_offset;
2731 reg_cnt = ARRAY_SIZE(fec_enet_register_offset);
2732 } else {
2733 reg_list = fec_enet_register_offset_6ul;
2734 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul);
2735 }
2736#else
2737 /* coldfire */
2738 static u32 *reg_list = fec_enet_register_offset;
2739 static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset);
2740#endif
2741 ret = pm_runtime_resume_and_get(dev);
2742 if (ret < 0)
2743 return;
2744
2745 regs->version = fec_enet_register_version;
2746
2747 memset(buf, 0, regs->len);
2748
2749 for (i = 0; i < reg_cnt; i++) {
2750 off = reg_list[i];
2751
2752 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) &&
2753 !(fep->quirks & FEC_QUIRK_HAS_FRREG))
2754 continue;
2755
2756 off >>= 2;
2757 buf[off] = readl(&theregs[off]);
2758 }
2759
2760 pm_runtime_mark_last_busy(dev);
2761 pm_runtime_put_autosuspend(dev);
2762}
2763
2764static int fec_enet_get_ts_info(struct net_device *ndev,
2765 struct ethtool_ts_info *info)
2766{
2767 struct fec_enet_private *fep = netdev_priv(ndev);
2768
2769 if (fep->bufdesc_ex) {
2770
2771 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2772 SOF_TIMESTAMPING_RX_SOFTWARE |
2773 SOF_TIMESTAMPING_SOFTWARE |
2774 SOF_TIMESTAMPING_TX_HARDWARE |
2775 SOF_TIMESTAMPING_RX_HARDWARE |
2776 SOF_TIMESTAMPING_RAW_HARDWARE;
2777 if (fep->ptp_clock)
2778 info->phc_index = ptp_clock_index(fep->ptp_clock);
2779 else
2780 info->phc_index = -1;
2781
2782 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2783 (1 << HWTSTAMP_TX_ON);
2784
2785 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2786 (1 << HWTSTAMP_FILTER_ALL);
2787 return 0;
2788 } else {
2789 return ethtool_op_get_ts_info(ndev, info);
2790 }
2791}
2792
2793#if !defined(CONFIG_M5272)
2794
2795static void fec_enet_get_pauseparam(struct net_device *ndev,
2796 struct ethtool_pauseparam *pause)
2797{
2798 struct fec_enet_private *fep = netdev_priv(ndev);
2799
2800 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2801 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2802 pause->rx_pause = pause->tx_pause;
2803}
2804
2805static int fec_enet_set_pauseparam(struct net_device *ndev,
2806 struct ethtool_pauseparam *pause)
2807{
2808 struct fec_enet_private *fep = netdev_priv(ndev);
2809
2810 if (!ndev->phydev)
2811 return -ENODEV;
2812
2813 if (pause->tx_pause != pause->rx_pause) {
2814 netdev_info(ndev,
2815 "hardware only support enable/disable both tx and rx");
2816 return -EINVAL;
2817 }
2818
2819 fep->pause_flag = 0;
2820
2821 /* tx pause must be same as rx pause */
2822 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2823 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2824
2825 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause,
2826 pause->autoneg);
2827
2828 if (pause->autoneg) {
2829 if (netif_running(ndev))
2830 fec_stop(ndev);
2831 phy_start_aneg(ndev->phydev);
2832 }
2833 if (netif_running(ndev)) {
2834 napi_disable(&fep->napi);
2835 netif_tx_lock_bh(ndev);
2836 fec_restart(ndev);
2837 netif_tx_wake_all_queues(ndev);
2838 netif_tx_unlock_bh(ndev);
2839 napi_enable(&fep->napi);
2840 }
2841
2842 return 0;
2843}
2844
2845static const struct fec_stat {
2846 char name[ETH_GSTRING_LEN];
2847 u16 offset;
2848} fec_stats[] = {
2849 /* RMON TX */
2850 { "tx_dropped", RMON_T_DROP },
2851 { "tx_packets", RMON_T_PACKETS },
2852 { "tx_broadcast", RMON_T_BC_PKT },
2853 { "tx_multicast", RMON_T_MC_PKT },
2854 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2855 { "tx_undersize", RMON_T_UNDERSIZE },
2856 { "tx_oversize", RMON_T_OVERSIZE },
2857 { "tx_fragment", RMON_T_FRAG },
2858 { "tx_jabber", RMON_T_JAB },
2859 { "tx_collision", RMON_T_COL },
2860 { "tx_64byte", RMON_T_P64 },
2861 { "tx_65to127byte", RMON_T_P65TO127 },
2862 { "tx_128to255byte", RMON_T_P128TO255 },
2863 { "tx_256to511byte", RMON_T_P256TO511 },
2864 { "tx_512to1023byte", RMON_T_P512TO1023 },
2865 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2866 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2867 { "tx_octets", RMON_T_OCTETS },
2868
2869 /* IEEE TX */
2870 { "IEEE_tx_drop", IEEE_T_DROP },
2871 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2872 { "IEEE_tx_1col", IEEE_T_1COL },
2873 { "IEEE_tx_mcol", IEEE_T_MCOL },
2874 { "IEEE_tx_def", IEEE_T_DEF },
2875 { "IEEE_tx_lcol", IEEE_T_LCOL },
2876 { "IEEE_tx_excol", IEEE_T_EXCOL },
2877 { "IEEE_tx_macerr", IEEE_T_MACERR },
2878 { "IEEE_tx_cserr", IEEE_T_CSERR },
2879 { "IEEE_tx_sqe", IEEE_T_SQE },
2880 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2881 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2882
2883 /* RMON RX */
2884 { "rx_packets", RMON_R_PACKETS },
2885 { "rx_broadcast", RMON_R_BC_PKT },
2886 { "rx_multicast", RMON_R_MC_PKT },
2887 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2888 { "rx_undersize", RMON_R_UNDERSIZE },
2889 { "rx_oversize", RMON_R_OVERSIZE },
2890 { "rx_fragment", RMON_R_FRAG },
2891 { "rx_jabber", RMON_R_JAB },
2892 { "rx_64byte", RMON_R_P64 },
2893 { "rx_65to127byte", RMON_R_P65TO127 },
2894 { "rx_128to255byte", RMON_R_P128TO255 },
2895 { "rx_256to511byte", RMON_R_P256TO511 },
2896 { "rx_512to1023byte", RMON_R_P512TO1023 },
2897 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2898 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2899 { "rx_octets", RMON_R_OCTETS },
2900
2901 /* IEEE RX */
2902 { "IEEE_rx_drop", IEEE_R_DROP },
2903 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2904 { "IEEE_rx_crc", IEEE_R_CRC },
2905 { "IEEE_rx_align", IEEE_R_ALIGN },
2906 { "IEEE_rx_macerr", IEEE_R_MACERR },
2907 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2908 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2909};
2910
2911#define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64))
2912
2913static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = {
2914 "rx_xdp_redirect", /* RX_XDP_REDIRECT = 0, */
2915 "rx_xdp_pass", /* RX_XDP_PASS, */
2916 "rx_xdp_drop", /* RX_XDP_DROP, */
2917 "rx_xdp_tx", /* RX_XDP_TX, */
2918 "rx_xdp_tx_errors", /* RX_XDP_TX_ERRORS, */
2919 "tx_xdp_xmit", /* TX_XDP_XMIT, */
2920 "tx_xdp_xmit_errors", /* TX_XDP_XMIT_ERRORS, */
2921};
2922
2923static void fec_enet_update_ethtool_stats(struct net_device *dev)
2924{
2925 struct fec_enet_private *fep = netdev_priv(dev);
2926 int i;
2927
2928 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2929 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2930}
2931
2932static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data)
2933{
2934 u64 xdp_stats[XDP_STATS_TOTAL] = { 0 };
2935 struct fec_enet_priv_rx_q *rxq;
2936 int i, j;
2937
2938 for (i = fep->num_rx_queues - 1; i >= 0; i--) {
2939 rxq = fep->rx_queue[i];
2940
2941 for (j = 0; j < XDP_STATS_TOTAL; j++)
2942 xdp_stats[j] += rxq->stats[j];
2943 }
2944
2945 memcpy(data, xdp_stats, sizeof(xdp_stats));
2946}
2947
2948static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data)
2949{
2950#ifdef CONFIG_PAGE_POOL_STATS
2951 struct page_pool_stats stats = {};
2952 struct fec_enet_priv_rx_q *rxq;
2953 int i;
2954
2955 for (i = fep->num_rx_queues - 1; i >= 0; i--) {
2956 rxq = fep->rx_queue[i];
2957
2958 if (!rxq->page_pool)
2959 continue;
2960
2961 page_pool_get_stats(rxq->page_pool, &stats);
2962 }
2963
2964 page_pool_ethtool_stats_get(data, &stats);
2965#endif
2966}
2967
2968static void fec_enet_get_ethtool_stats(struct net_device *dev,
2969 struct ethtool_stats *stats, u64 *data)
2970{
2971 struct fec_enet_private *fep = netdev_priv(dev);
2972
2973 if (netif_running(dev))
2974 fec_enet_update_ethtool_stats(dev);
2975
2976 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2977 data += FEC_STATS_SIZE / sizeof(u64);
2978
2979 fec_enet_get_xdp_stats(fep, data);
2980 data += XDP_STATS_TOTAL;
2981
2982 fec_enet_page_pool_stats(fep, data);
2983}
2984
2985static void fec_enet_get_strings(struct net_device *netdev,
2986 u32 stringset, u8 *data)
2987{
2988 int i;
2989 switch (stringset) {
2990 case ETH_SS_STATS:
2991 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) {
2992 ethtool_puts(&data, fec_stats[i].name);
2993 }
2994 for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) {
2995 ethtool_puts(&data, fec_xdp_stat_strs[i]);
2996 }
2997 page_pool_ethtool_stats_get_strings(data);
2998
2999 break;
3000 case ETH_SS_TEST:
3001 net_selftest_get_strings(data);
3002 break;
3003 }
3004}
3005
3006static int fec_enet_get_sset_count(struct net_device *dev, int sset)
3007{
3008 int count;
3009
3010 switch (sset) {
3011 case ETH_SS_STATS:
3012 count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL;
3013 count += page_pool_ethtool_stats_get_count();
3014 return count;
3015
3016 case ETH_SS_TEST:
3017 return net_selftest_get_count();
3018 default:
3019 return -EOPNOTSUPP;
3020 }
3021}
3022
3023static void fec_enet_clear_ethtool_stats(struct net_device *dev)
3024{
3025 struct fec_enet_private *fep = netdev_priv(dev);
3026 struct fec_enet_priv_rx_q *rxq;
3027 int i, j;
3028
3029 /* Disable MIB statistics counters */
3030 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
3031
3032 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
3033 writel(0, fep->hwp + fec_stats[i].offset);
3034
3035 for (i = fep->num_rx_queues - 1; i >= 0; i--) {
3036 rxq = fep->rx_queue[i];
3037 for (j = 0; j < XDP_STATS_TOTAL; j++)
3038 rxq->stats[j] = 0;
3039 }
3040
3041 /* Don't disable MIB statistics counters */
3042 writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
3043}
3044
3045#else /* !defined(CONFIG_M5272) */
3046#define FEC_STATS_SIZE 0
3047static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
3048{
3049}
3050
3051static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
3052{
3053}
3054#endif /* !defined(CONFIG_M5272) */
3055
3056/* ITR clock source is enet system clock (clk_ahb).
3057 * TCTT unit is cycle_ns * 64 cycle
3058 * So, the ICTT value = X us / (cycle_ns * 64)
3059 */
3060static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
3061{
3062 struct fec_enet_private *fep = netdev_priv(ndev);
3063
3064 return us * (fep->itr_clk_rate / 64000) / 1000;
3065}
3066
3067/* Set threshold for interrupt coalescing */
3068static void fec_enet_itr_coal_set(struct net_device *ndev)
3069{
3070 struct fec_enet_private *fep = netdev_priv(ndev);
3071 int rx_itr, tx_itr;
3072
3073 /* Must be greater than zero to avoid unpredictable behavior */
3074 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
3075 !fep->tx_time_itr || !fep->tx_pkts_itr)
3076 return;
3077
3078 /* Select enet system clock as Interrupt Coalescing
3079 * timer Clock Source
3080 */
3081 rx_itr = FEC_ITR_CLK_SEL;
3082 tx_itr = FEC_ITR_CLK_SEL;
3083
3084 /* set ICFT and ICTT */
3085 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
3086 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
3087 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
3088 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
3089
3090 rx_itr |= FEC_ITR_EN;
3091 tx_itr |= FEC_ITR_EN;
3092
3093 writel(tx_itr, fep->hwp + FEC_TXIC0);
3094 writel(rx_itr, fep->hwp + FEC_RXIC0);
3095 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
3096 writel(tx_itr, fep->hwp + FEC_TXIC1);
3097 writel(rx_itr, fep->hwp + FEC_RXIC1);
3098 writel(tx_itr, fep->hwp + FEC_TXIC2);
3099 writel(rx_itr, fep->hwp + FEC_RXIC2);
3100 }
3101}
3102
3103static int fec_enet_get_coalesce(struct net_device *ndev,
3104 struct ethtool_coalesce *ec,
3105 struct kernel_ethtool_coalesce *kernel_coal,
3106 struct netlink_ext_ack *extack)
3107{
3108 struct fec_enet_private *fep = netdev_priv(ndev);
3109
3110 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
3111 return -EOPNOTSUPP;
3112
3113 ec->rx_coalesce_usecs = fep->rx_time_itr;
3114 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
3115
3116 ec->tx_coalesce_usecs = fep->tx_time_itr;
3117 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
3118
3119 return 0;
3120}
3121
3122static int fec_enet_set_coalesce(struct net_device *ndev,
3123 struct ethtool_coalesce *ec,
3124 struct kernel_ethtool_coalesce *kernel_coal,
3125 struct netlink_ext_ack *extack)
3126{
3127 struct fec_enet_private *fep = netdev_priv(ndev);
3128 struct device *dev = &fep->pdev->dev;
3129 unsigned int cycle;
3130
3131 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
3132 return -EOPNOTSUPP;
3133
3134 if (ec->rx_max_coalesced_frames > 255) {
3135 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n");
3136 return -EINVAL;
3137 }
3138
3139 if (ec->tx_max_coalesced_frames > 255) {
3140 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n");
3141 return -EINVAL;
3142 }
3143
3144 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs);
3145 if (cycle > 0xFFFF) {
3146 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");
3147 return -EINVAL;
3148 }
3149
3150 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs);
3151 if (cycle > 0xFFFF) {
3152 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n");
3153 return -EINVAL;
3154 }
3155
3156 fep->rx_time_itr = ec->rx_coalesce_usecs;
3157 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
3158
3159 fep->tx_time_itr = ec->tx_coalesce_usecs;
3160 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
3161
3162 fec_enet_itr_coal_set(ndev);
3163
3164 return 0;
3165}
3166
3167static int
3168fec_enet_get_eee(struct net_device *ndev, struct ethtool_keee *edata)
3169{
3170 struct fec_enet_private *fep = netdev_priv(ndev);
3171 struct ethtool_keee *p = &fep->eee;
3172
3173 if (!(fep->quirks & FEC_QUIRK_HAS_EEE))
3174 return -EOPNOTSUPP;
3175
3176 if (!netif_running(ndev))
3177 return -ENETDOWN;
3178
3179 edata->tx_lpi_timer = p->tx_lpi_timer;
3180
3181 return phy_ethtool_get_eee(ndev->phydev, edata);
3182}
3183
3184static int
3185fec_enet_set_eee(struct net_device *ndev, struct ethtool_keee *edata)
3186{
3187 struct fec_enet_private *fep = netdev_priv(ndev);
3188 struct ethtool_keee *p = &fep->eee;
3189
3190 if (!(fep->quirks & FEC_QUIRK_HAS_EEE))
3191 return -EOPNOTSUPP;
3192
3193 if (!netif_running(ndev))
3194 return -ENETDOWN;
3195
3196 p->tx_lpi_timer = edata->tx_lpi_timer;
3197
3198 return phy_ethtool_set_eee(ndev->phydev, edata);
3199}
3200
3201static void
3202fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
3203{
3204 struct fec_enet_private *fep = netdev_priv(ndev);
3205
3206 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
3207 wol->supported = WAKE_MAGIC;
3208 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
3209 } else {
3210 wol->supported = wol->wolopts = 0;
3211 }
3212}
3213
3214static int
3215fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
3216{
3217 struct fec_enet_private *fep = netdev_priv(ndev);
3218
3219 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
3220 return -EINVAL;
3221
3222 if (wol->wolopts & ~WAKE_MAGIC)
3223 return -EINVAL;
3224
3225 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
3226 if (device_may_wakeup(&ndev->dev))
3227 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
3228 else
3229 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
3230
3231 return 0;
3232}
3233
3234static const struct ethtool_ops fec_enet_ethtool_ops = {
3235 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
3236 ETHTOOL_COALESCE_MAX_FRAMES,
3237 .get_drvinfo = fec_enet_get_drvinfo,
3238 .get_regs_len = fec_enet_get_regs_len,
3239 .get_regs = fec_enet_get_regs,
3240 .nway_reset = phy_ethtool_nway_reset,
3241 .get_link = ethtool_op_get_link,
3242 .get_coalesce = fec_enet_get_coalesce,
3243 .set_coalesce = fec_enet_set_coalesce,
3244#ifndef CONFIG_M5272
3245 .get_pauseparam = fec_enet_get_pauseparam,
3246 .set_pauseparam = fec_enet_set_pauseparam,
3247 .get_strings = fec_enet_get_strings,
3248 .get_ethtool_stats = fec_enet_get_ethtool_stats,
3249 .get_sset_count = fec_enet_get_sset_count,
3250#endif
3251 .get_ts_info = fec_enet_get_ts_info,
3252 .get_wol = fec_enet_get_wol,
3253 .set_wol = fec_enet_set_wol,
3254 .get_eee = fec_enet_get_eee,
3255 .set_eee = fec_enet_set_eee,
3256 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3257 .set_link_ksettings = phy_ethtool_set_link_ksettings,
3258 .self_test = net_selftest,
3259};
3260
3261static void fec_enet_free_buffers(struct net_device *ndev)
3262{
3263 struct fec_enet_private *fep = netdev_priv(ndev);
3264 unsigned int i;
3265 struct fec_enet_priv_tx_q *txq;
3266 struct fec_enet_priv_rx_q *rxq;
3267 unsigned int q;
3268
3269 for (q = 0; q < fep->num_rx_queues; q++) {
3270 rxq = fep->rx_queue[q];
3271 for (i = 0; i < rxq->bd.ring_size; i++)
3272 page_pool_put_full_page(rxq->page_pool, rxq->rx_skb_info[i].page, false);
3273
3274 for (i = 0; i < XDP_STATS_TOTAL; i++)
3275 rxq->stats[i] = 0;
3276
3277 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq))
3278 xdp_rxq_info_unreg(&rxq->xdp_rxq);
3279 page_pool_destroy(rxq->page_pool);
3280 rxq->page_pool = NULL;
3281 }
3282
3283 for (q = 0; q < fep->num_tx_queues; q++) {
3284 txq = fep->tx_queue[q];
3285 for (i = 0; i < txq->bd.ring_size; i++) {
3286 kfree(txq->tx_bounce[i]);
3287 txq->tx_bounce[i] = NULL;
3288
3289 if (!txq->tx_buf[i].buf_p) {
3290 txq->tx_buf[i].type = FEC_TXBUF_T_SKB;
3291 continue;
3292 }
3293
3294 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) {
3295 dev_kfree_skb(txq->tx_buf[i].buf_p);
3296 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) {
3297 xdp_return_frame(txq->tx_buf[i].buf_p);
3298 } else {
3299 struct page *page = txq->tx_buf[i].buf_p;
3300
3301 page_pool_put_page(page->pp, page, 0, false);
3302 }
3303
3304 txq->tx_buf[i].buf_p = NULL;
3305 txq->tx_buf[i].type = FEC_TXBUF_T_SKB;
3306 }
3307 }
3308}
3309
3310static void fec_enet_free_queue(struct net_device *ndev)
3311{
3312 struct fec_enet_private *fep = netdev_priv(ndev);
3313 int i;
3314 struct fec_enet_priv_tx_q *txq;
3315
3316 for (i = 0; i < fep->num_tx_queues; i++)
3317 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
3318 txq = fep->tx_queue[i];
3319 fec_dma_free(&fep->pdev->dev,
3320 txq->bd.ring_size * TSO_HEADER_SIZE,
3321 txq->tso_hdrs, txq->tso_hdrs_dma);
3322 }
3323
3324 for (i = 0; i < fep->num_rx_queues; i++)
3325 kfree(fep->rx_queue[i]);
3326 for (i = 0; i < fep->num_tx_queues; i++)
3327 kfree(fep->tx_queue[i]);
3328}
3329
3330static int fec_enet_alloc_queue(struct net_device *ndev)
3331{
3332 struct fec_enet_private *fep = netdev_priv(ndev);
3333 int i;
3334 int ret = 0;
3335 struct fec_enet_priv_tx_q *txq;
3336
3337 for (i = 0; i < fep->num_tx_queues; i++) {
3338 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
3339 if (!txq) {
3340 ret = -ENOMEM;
3341 goto alloc_failed;
3342 }
3343
3344 fep->tx_queue[i] = txq;
3345 txq->bd.ring_size = TX_RING_SIZE;
3346 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
3347
3348 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
3349 txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS;
3350
3351 txq->tso_hdrs = fec_dma_alloc(&fep->pdev->dev,
3352 txq->bd.ring_size * TSO_HEADER_SIZE,
3353 &txq->tso_hdrs_dma, GFP_KERNEL);
3354 if (!txq->tso_hdrs) {
3355 ret = -ENOMEM;
3356 goto alloc_failed;
3357 }
3358 }
3359
3360 for (i = 0; i < fep->num_rx_queues; i++) {
3361 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
3362 GFP_KERNEL);
3363 if (!fep->rx_queue[i]) {
3364 ret = -ENOMEM;
3365 goto alloc_failed;
3366 }
3367
3368 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
3369 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
3370 }
3371 return ret;
3372
3373alloc_failed:
3374 fec_enet_free_queue(ndev);
3375 return ret;
3376}
3377
3378static int
3379fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
3380{
3381 struct fec_enet_private *fep = netdev_priv(ndev);
3382 struct fec_enet_priv_rx_q *rxq;
3383 dma_addr_t phys_addr;
3384 struct bufdesc *bdp;
3385 struct page *page;
3386 int i, err;
3387
3388 rxq = fep->rx_queue[queue];
3389 bdp = rxq->bd.base;
3390
3391 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size);
3392 if (err < 0) {
3393 netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err);
3394 return err;
3395 }
3396
3397 for (i = 0; i < rxq->bd.ring_size; i++) {
3398 page = page_pool_dev_alloc_pages(rxq->page_pool);
3399 if (!page)
3400 goto err_alloc;
3401
3402 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM;
3403 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr);
3404
3405 rxq->rx_skb_info[i].page = page;
3406 rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM;
3407 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
3408
3409 if (fep->bufdesc_ex) {
3410 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3411 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
3412 }
3413
3414 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
3415 }
3416
3417 /* Set the last buffer to wrap. */
3418 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
3419 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
3420 return 0;
3421
3422 err_alloc:
3423 fec_enet_free_buffers(ndev);
3424 return -ENOMEM;
3425}
3426
3427static int
3428fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
3429{
3430 struct fec_enet_private *fep = netdev_priv(ndev);
3431 unsigned int i;
3432 struct bufdesc *bdp;
3433 struct fec_enet_priv_tx_q *txq;
3434
3435 txq = fep->tx_queue[queue];
3436 bdp = txq->bd.base;
3437 for (i = 0; i < txq->bd.ring_size; i++) {
3438 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
3439 if (!txq->tx_bounce[i])
3440 goto err_alloc;
3441
3442 bdp->cbd_sc = cpu_to_fec16(0);
3443 bdp->cbd_bufaddr = cpu_to_fec32(0);
3444
3445 if (fep->bufdesc_ex) {
3446 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3447 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
3448 }
3449
3450 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
3451 }
3452
3453 /* Set the last buffer to wrap. */
3454 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
3455 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
3456
3457 return 0;
3458
3459 err_alloc:
3460 fec_enet_free_buffers(ndev);
3461 return -ENOMEM;
3462}
3463
3464static int fec_enet_alloc_buffers(struct net_device *ndev)
3465{
3466 struct fec_enet_private *fep = netdev_priv(ndev);
3467 unsigned int i;
3468
3469 for (i = 0; i < fep->num_rx_queues; i++)
3470 if (fec_enet_alloc_rxq_buffers(ndev, i))
3471 return -ENOMEM;
3472
3473 for (i = 0; i < fep->num_tx_queues; i++)
3474 if (fec_enet_alloc_txq_buffers(ndev, i))
3475 return -ENOMEM;
3476 return 0;
3477}
3478
3479static int
3480fec_enet_open(struct net_device *ndev)
3481{
3482 struct fec_enet_private *fep = netdev_priv(ndev);
3483 int ret;
3484 bool reset_again;
3485
3486 ret = pm_runtime_resume_and_get(&fep->pdev->dev);
3487 if (ret < 0)
3488 return ret;
3489
3490 pinctrl_pm_select_default_state(&fep->pdev->dev);
3491 ret = fec_enet_clk_enable(ndev, true);
3492 if (ret)
3493 goto clk_enable;
3494
3495 /* During the first fec_enet_open call the PHY isn't probed at this
3496 * point. Therefore the phy_reset_after_clk_enable() call within
3497 * fec_enet_clk_enable() fails. As we need this reset in order to be
3498 * sure the PHY is working correctly we check if we need to reset again
3499 * later when the PHY is probed
3500 */
3501 if (ndev->phydev && ndev->phydev->drv)
3502 reset_again = false;
3503 else
3504 reset_again = true;
3505
3506 /* I should reset the ring buffers here, but I don't yet know
3507 * a simple way to do that.
3508 */
3509
3510 ret = fec_enet_alloc_buffers(ndev);
3511 if (ret)
3512 goto err_enet_alloc;
3513
3514 /* Init MAC prior to mii bus probe */
3515 fec_restart(ndev);
3516
3517 /* Call phy_reset_after_clk_enable() again if it failed during
3518 * phy_reset_after_clk_enable() before because the PHY wasn't probed.
3519 */
3520 if (reset_again)
3521 fec_enet_phy_reset_after_clk_enable(ndev);
3522
3523 /* Probe and connect to PHY when open the interface */
3524 ret = fec_enet_mii_probe(ndev);
3525 if (ret)
3526 goto err_enet_mii_probe;
3527
3528 if (fep->quirks & FEC_QUIRK_ERR006687)
3529 imx6q_cpuidle_fec_irqs_used();
3530
3531 if (fep->quirks & FEC_QUIRK_HAS_PMQOS)
3532 cpu_latency_qos_add_request(&fep->pm_qos_req, 0);
3533
3534 napi_enable(&fep->napi);
3535 phy_start(ndev->phydev);
3536 netif_tx_start_all_queues(ndev);
3537
3538 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
3539 FEC_WOL_FLAG_ENABLE);
3540
3541 return 0;
3542
3543err_enet_mii_probe:
3544 fec_enet_free_buffers(ndev);
3545err_enet_alloc:
3546 fec_enet_clk_enable(ndev, false);
3547clk_enable:
3548 pm_runtime_mark_last_busy(&fep->pdev->dev);
3549 pm_runtime_put_autosuspend(&fep->pdev->dev);
3550 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3551 return ret;
3552}
3553
3554static int
3555fec_enet_close(struct net_device *ndev)
3556{
3557 struct fec_enet_private *fep = netdev_priv(ndev);
3558
3559 phy_stop(ndev->phydev);
3560
3561 if (netif_device_present(ndev)) {
3562 napi_disable(&fep->napi);
3563 netif_tx_disable(ndev);
3564 fec_stop(ndev);
3565 }
3566
3567 phy_disconnect(ndev->phydev);
3568
3569 if (fep->quirks & FEC_QUIRK_ERR006687)
3570 imx6q_cpuidle_fec_irqs_unused();
3571
3572 fec_enet_update_ethtool_stats(ndev);
3573
3574 fec_enet_clk_enable(ndev, false);
3575 if (fep->quirks & FEC_QUIRK_HAS_PMQOS)
3576 cpu_latency_qos_remove_request(&fep->pm_qos_req);
3577
3578 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3579 pm_runtime_mark_last_busy(&fep->pdev->dev);
3580 pm_runtime_put_autosuspend(&fep->pdev->dev);
3581
3582 fec_enet_free_buffers(ndev);
3583
3584 return 0;
3585}
3586
3587/* Set or clear the multicast filter for this adaptor.
3588 * Skeleton taken from sunlance driver.
3589 * The CPM Ethernet implementation allows Multicast as well as individual
3590 * MAC address filtering. Some of the drivers check to make sure it is
3591 * a group multicast address, and discard those that are not. I guess I
3592 * will do the same for now, but just remove the test if you want
3593 * individual filtering as well (do the upper net layers want or support
3594 * this kind of feature?).
3595 */
3596
3597#define FEC_HASH_BITS 6 /* #bits in hash */
3598
3599static void set_multicast_list(struct net_device *ndev)
3600{
3601 struct fec_enet_private *fep = netdev_priv(ndev);
3602 struct netdev_hw_addr *ha;
3603 unsigned int crc, tmp;
3604 unsigned char hash;
3605 unsigned int hash_high = 0, hash_low = 0;
3606
3607 if (ndev->flags & IFF_PROMISC) {
3608 tmp = readl(fep->hwp + FEC_R_CNTRL);
3609 tmp |= 0x8;
3610 writel(tmp, fep->hwp + FEC_R_CNTRL);
3611 return;
3612 }
3613
3614 tmp = readl(fep->hwp + FEC_R_CNTRL);
3615 tmp &= ~0x8;
3616 writel(tmp, fep->hwp + FEC_R_CNTRL);
3617
3618 if (ndev->flags & IFF_ALLMULTI) {
3619 /* Catch all multicast addresses, so set the
3620 * filter to all 1's
3621 */
3622 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3623 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3624
3625 return;
3626 }
3627
3628 /* Add the addresses in hash register */
3629 netdev_for_each_mc_addr(ha, ndev) {
3630 /* calculate crc32 value of mac address */
3631 crc = ether_crc_le(ndev->addr_len, ha->addr);
3632
3633 /* only upper 6 bits (FEC_HASH_BITS) are used
3634 * which point to specific bit in the hash registers
3635 */
3636 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
3637
3638 if (hash > 31)
3639 hash_high |= 1 << (hash - 32);
3640 else
3641 hash_low |= 1 << hash;
3642 }
3643
3644 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3645 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3646}
3647
3648/* Set a MAC change in hardware. */
3649static int
3650fec_set_mac_address(struct net_device *ndev, void *p)
3651{
3652 struct fec_enet_private *fep = netdev_priv(ndev);
3653 struct sockaddr *addr = p;
3654
3655 if (addr) {
3656 if (!is_valid_ether_addr(addr->sa_data))
3657 return -EADDRNOTAVAIL;
3658 eth_hw_addr_set(ndev, addr->sa_data);
3659 }
3660
3661 /* Add netif status check here to avoid system hang in below case:
3662 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3663 * After ethx down, fec all clocks are gated off and then register
3664 * access causes system hang.
3665 */
3666 if (!netif_running(ndev))
3667 return 0;
3668
3669 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3670 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3671 fep->hwp + FEC_ADDR_LOW);
3672 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3673 fep->hwp + FEC_ADDR_HIGH);
3674 return 0;
3675}
3676
3677static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3678 netdev_features_t features)
3679{
3680 struct fec_enet_private *fep = netdev_priv(netdev);
3681 netdev_features_t changed = features ^ netdev->features;
3682
3683 netdev->features = features;
3684
3685 /* Receive checksum has been changed */
3686 if (changed & NETIF_F_RXCSUM) {
3687 if (features & NETIF_F_RXCSUM)
3688 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3689 else
3690 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3691 }
3692}
3693
3694static int fec_set_features(struct net_device *netdev,
3695 netdev_features_t features)
3696{
3697 struct fec_enet_private *fep = netdev_priv(netdev);
3698 netdev_features_t changed = features ^ netdev->features;
3699
3700 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3701 napi_disable(&fep->napi);
3702 netif_tx_lock_bh(netdev);
3703 fec_stop(netdev);
3704 fec_enet_set_netdev_features(netdev, features);
3705 fec_restart(netdev);
3706 netif_tx_wake_all_queues(netdev);
3707 netif_tx_unlock_bh(netdev);
3708 napi_enable(&fep->napi);
3709 } else {
3710 fec_enet_set_netdev_features(netdev, features);
3711 }
3712
3713 return 0;
3714}
3715
3716static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb,
3717 struct net_device *sb_dev)
3718{
3719 struct fec_enet_private *fep = netdev_priv(ndev);
3720 u16 vlan_tag = 0;
3721
3722 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
3723 return netdev_pick_tx(ndev, skb, NULL);
3724
3725 /* VLAN is present in the payload.*/
3726 if (eth_type_vlan(skb->protocol)) {
3727 struct vlan_ethhdr *vhdr = skb_vlan_eth_hdr(skb);
3728
3729 vlan_tag = ntohs(vhdr->h_vlan_TCI);
3730 /* VLAN is present in the skb but not yet pushed in the payload.*/
3731 } else if (skb_vlan_tag_present(skb)) {
3732 vlan_tag = skb->vlan_tci;
3733 } else {
3734 return vlan_tag;
3735 }
3736
3737 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13];
3738}
3739
3740static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf)
3741{
3742 struct fec_enet_private *fep = netdev_priv(dev);
3743 bool is_run = netif_running(dev);
3744 struct bpf_prog *old_prog;
3745
3746 switch (bpf->command) {
3747 case XDP_SETUP_PROG:
3748 /* No need to support the SoCs that require to
3749 * do the frame swap because the performance wouldn't be
3750 * better than the skb mode.
3751 */
3752 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
3753 return -EOPNOTSUPP;
3754
3755 if (!bpf->prog)
3756 xdp_features_clear_redirect_target(dev);
3757
3758 if (is_run) {
3759 napi_disable(&fep->napi);
3760 netif_tx_disable(dev);
3761 }
3762
3763 old_prog = xchg(&fep->xdp_prog, bpf->prog);
3764 if (old_prog)
3765 bpf_prog_put(old_prog);
3766
3767 fec_restart(dev);
3768
3769 if (is_run) {
3770 napi_enable(&fep->napi);
3771 netif_tx_start_all_queues(dev);
3772 }
3773
3774 if (bpf->prog)
3775 xdp_features_set_redirect_target(dev, false);
3776
3777 return 0;
3778
3779 case XDP_SETUP_XSK_POOL:
3780 return -EOPNOTSUPP;
3781
3782 default:
3783 return -EOPNOTSUPP;
3784 }
3785}
3786
3787static int
3788fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index)
3789{
3790 if (unlikely(index < 0))
3791 return 0;
3792
3793 return (index % fep->num_tx_queues);
3794}
3795
3796static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep,
3797 struct fec_enet_priv_tx_q *txq,
3798 void *frame, u32 dma_sync_len,
3799 bool ndo_xmit)
3800{
3801 unsigned int index, status, estatus;
3802 struct bufdesc *bdp;
3803 dma_addr_t dma_addr;
3804 int entries_free;
3805 u16 frame_len;
3806
3807 entries_free = fec_enet_get_free_txdesc_num(txq);
3808 if (entries_free < MAX_SKB_FRAGS + 1) {
3809 netdev_err_once(fep->netdev, "NOT enough BD for SG!\n");
3810 return -EBUSY;
3811 }
3812
3813 /* Fill in a Tx ring entry */
3814 bdp = txq->bd.cur;
3815 status = fec16_to_cpu(bdp->cbd_sc);
3816 status &= ~BD_ENET_TX_STATS;
3817
3818 index = fec_enet_get_bd_index(bdp, &txq->bd);
3819
3820 if (ndo_xmit) {
3821 struct xdp_frame *xdpf = frame;
3822
3823 dma_addr = dma_map_single(&fep->pdev->dev, xdpf->data,
3824 xdpf->len, DMA_TO_DEVICE);
3825 if (dma_mapping_error(&fep->pdev->dev, dma_addr))
3826 return -ENOMEM;
3827
3828 frame_len = xdpf->len;
3829 txq->tx_buf[index].buf_p = xdpf;
3830 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO;
3831 } else {
3832 struct xdp_buff *xdpb = frame;
3833 struct page *page;
3834
3835 page = virt_to_page(xdpb->data);
3836 dma_addr = page_pool_get_dma_addr(page) +
3837 (xdpb->data - xdpb->data_hard_start);
3838 dma_sync_single_for_device(&fep->pdev->dev, dma_addr,
3839 dma_sync_len, DMA_BIDIRECTIONAL);
3840 frame_len = xdpb->data_end - xdpb->data;
3841 txq->tx_buf[index].buf_p = page;
3842 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_TX;
3843 }
3844
3845 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
3846 if (fep->bufdesc_ex)
3847 estatus = BD_ENET_TX_INT;
3848
3849 bdp->cbd_bufaddr = cpu_to_fec32(dma_addr);
3850 bdp->cbd_datlen = cpu_to_fec16(frame_len);
3851
3852 if (fep->bufdesc_ex) {
3853 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3854
3855 if (fep->quirks & FEC_QUIRK_HAS_AVB)
3856 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
3857
3858 ebdp->cbd_bdu = 0;
3859 ebdp->cbd_esc = cpu_to_fec32(estatus);
3860 }
3861
3862 /* Make sure the updates to rest of the descriptor are performed before
3863 * transferring ownership.
3864 */
3865 dma_wmb();
3866
3867 /* Send it on its way. Tell FEC it's ready, interrupt when done,
3868 * it's the last BD of the frame, and to put the CRC on the end.
3869 */
3870 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
3871 bdp->cbd_sc = cpu_to_fec16(status);
3872
3873 /* If this was the last BD in the ring, start at the beginning again. */
3874 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
3875
3876 /* Make sure the update to bdp are performed before txq->bd.cur. */
3877 dma_wmb();
3878
3879 txq->bd.cur = bdp;
3880
3881 /* Trigger transmission start */
3882 writel(0, txq->bd.reg_desc_active);
3883
3884 return 0;
3885}
3886
3887static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep,
3888 int cpu, struct xdp_buff *xdp,
3889 u32 dma_sync_len)
3890{
3891 struct fec_enet_priv_tx_q *txq;
3892 struct netdev_queue *nq;
3893 int queue, ret;
3894
3895 queue = fec_enet_xdp_get_tx_queue(fep, cpu);
3896 txq = fep->tx_queue[queue];
3897 nq = netdev_get_tx_queue(fep->netdev, queue);
3898
3899 __netif_tx_lock(nq, cpu);
3900
3901 /* Avoid tx timeout as XDP shares the queue with kernel stack */
3902 txq_trans_cond_update(nq);
3903 ret = fec_enet_txq_xmit_frame(fep, txq, xdp, dma_sync_len, false);
3904
3905 __netif_tx_unlock(nq);
3906
3907 return ret;
3908}
3909
3910static int fec_enet_xdp_xmit(struct net_device *dev,
3911 int num_frames,
3912 struct xdp_frame **frames,
3913 u32 flags)
3914{
3915 struct fec_enet_private *fep = netdev_priv(dev);
3916 struct fec_enet_priv_tx_q *txq;
3917 int cpu = smp_processor_id();
3918 unsigned int sent_frames = 0;
3919 struct netdev_queue *nq;
3920 unsigned int queue;
3921 int i;
3922
3923 queue = fec_enet_xdp_get_tx_queue(fep, cpu);
3924 txq = fep->tx_queue[queue];
3925 nq = netdev_get_tx_queue(fep->netdev, queue);
3926
3927 __netif_tx_lock(nq, cpu);
3928
3929 /* Avoid tx timeout as XDP shares the queue with kernel stack */
3930 txq_trans_cond_update(nq);
3931 for (i = 0; i < num_frames; i++) {
3932 if (fec_enet_txq_xmit_frame(fep, txq, frames[i], 0, true) < 0)
3933 break;
3934 sent_frames++;
3935 }
3936
3937 __netif_tx_unlock(nq);
3938
3939 return sent_frames;
3940}
3941
3942static int fec_hwtstamp_get(struct net_device *ndev,
3943 struct kernel_hwtstamp_config *config)
3944{
3945 struct fec_enet_private *fep = netdev_priv(ndev);
3946
3947 if (!netif_running(ndev))
3948 return -EINVAL;
3949
3950 if (!fep->bufdesc_ex)
3951 return -EOPNOTSUPP;
3952
3953 fec_ptp_get(ndev, config);
3954
3955 return 0;
3956}
3957
3958static int fec_hwtstamp_set(struct net_device *ndev,
3959 struct kernel_hwtstamp_config *config,
3960 struct netlink_ext_ack *extack)
3961{
3962 struct fec_enet_private *fep = netdev_priv(ndev);
3963
3964 if (!netif_running(ndev))
3965 return -EINVAL;
3966
3967 if (!fep->bufdesc_ex)
3968 return -EOPNOTSUPP;
3969
3970 return fec_ptp_set(ndev, config, extack);
3971}
3972
3973static const struct net_device_ops fec_netdev_ops = {
3974 .ndo_open = fec_enet_open,
3975 .ndo_stop = fec_enet_close,
3976 .ndo_start_xmit = fec_enet_start_xmit,
3977 .ndo_select_queue = fec_enet_select_queue,
3978 .ndo_set_rx_mode = set_multicast_list,
3979 .ndo_validate_addr = eth_validate_addr,
3980 .ndo_tx_timeout = fec_timeout,
3981 .ndo_set_mac_address = fec_set_mac_address,
3982 .ndo_eth_ioctl = phy_do_ioctl_running,
3983 .ndo_set_features = fec_set_features,
3984 .ndo_bpf = fec_enet_bpf,
3985 .ndo_xdp_xmit = fec_enet_xdp_xmit,
3986 .ndo_hwtstamp_get = fec_hwtstamp_get,
3987 .ndo_hwtstamp_set = fec_hwtstamp_set,
3988};
3989
3990static const unsigned short offset_des_active_rxq[] = {
3991 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3992};
3993
3994static const unsigned short offset_des_active_txq[] = {
3995 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3996};
3997
3998 /*
3999 * XXX: We need to clean up on failure exits here.
4000 *
4001 */
4002static int fec_enet_init(struct net_device *ndev)
4003{
4004 struct fec_enet_private *fep = netdev_priv(ndev);
4005 struct bufdesc *cbd_base;
4006 dma_addr_t bd_dma;
4007 int bd_size;
4008 unsigned int i;
4009 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
4010 sizeof(struct bufdesc);
4011 unsigned dsize_log2 = __fls(dsize);
4012 int ret;
4013
4014 WARN_ON(dsize != (1 << dsize_log2));
4015#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
4016 fep->rx_align = 0xf;
4017 fep->tx_align = 0xf;
4018#else
4019 fep->rx_align = 0x3;
4020 fep->tx_align = 0x3;
4021#endif
4022 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT;
4023 fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT;
4024 fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT;
4025 fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT;
4026
4027 /* Check mask of the streaming and coherent API */
4028 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32));
4029 if (ret < 0) {
4030 dev_warn(&fep->pdev->dev, "No suitable DMA available\n");
4031 return ret;
4032 }
4033
4034 ret = fec_enet_alloc_queue(ndev);
4035 if (ret)
4036 return ret;
4037
4038 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
4039
4040 /* Allocate memory for buffer descriptors. */
4041 cbd_base = fec_dmam_alloc(&fep->pdev->dev, bd_size, &bd_dma,
4042 GFP_KERNEL);
4043 if (!cbd_base) {
4044 ret = -ENOMEM;
4045 goto free_queue_mem;
4046 }
4047
4048 /* Get the Ethernet address */
4049 ret = fec_get_mac(ndev);
4050 if (ret)
4051 goto free_queue_mem;
4052
4053 /* Set receive and transmit descriptor base. */
4054 for (i = 0; i < fep->num_rx_queues; i++) {
4055 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
4056 unsigned size = dsize * rxq->bd.ring_size;
4057
4058 rxq->bd.qid = i;
4059 rxq->bd.base = cbd_base;
4060 rxq->bd.cur = cbd_base;
4061 rxq->bd.dma = bd_dma;
4062 rxq->bd.dsize = dsize;
4063 rxq->bd.dsize_log2 = dsize_log2;
4064 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
4065 bd_dma += size;
4066 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
4067 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
4068 }
4069
4070 for (i = 0; i < fep->num_tx_queues; i++) {
4071 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
4072 unsigned size = dsize * txq->bd.ring_size;
4073
4074 txq->bd.qid = i;
4075 txq->bd.base = cbd_base;
4076 txq->bd.cur = cbd_base;
4077 txq->bd.dma = bd_dma;
4078 txq->bd.dsize = dsize;
4079 txq->bd.dsize_log2 = dsize_log2;
4080 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
4081 bd_dma += size;
4082 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
4083 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
4084 }
4085
4086
4087 /* The FEC Ethernet specific entries in the device structure */
4088 ndev->watchdog_timeo = TX_TIMEOUT;
4089 ndev->netdev_ops = &fec_netdev_ops;
4090 ndev->ethtool_ops = &fec_enet_ethtool_ops;
4091
4092 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
4093 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi);
4094
4095 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
4096 /* enable hw VLAN support */
4097 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
4098
4099 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
4100 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS);
4101
4102 /* enable hw accelerator */
4103 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
4104 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
4105 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
4106 }
4107
4108 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
4109 fep->tx_align = 0;
4110 fep->rx_align = 0x3f;
4111 }
4112
4113 ndev->hw_features = ndev->features;
4114
4115 if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME))
4116 ndev->xdp_features = NETDEV_XDP_ACT_BASIC |
4117 NETDEV_XDP_ACT_REDIRECT;
4118
4119 fec_restart(ndev);
4120
4121 if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
4122 fec_enet_clear_ethtool_stats(ndev);
4123 else
4124 fec_enet_update_ethtool_stats(ndev);
4125
4126 return 0;
4127
4128free_queue_mem:
4129 fec_enet_free_queue(ndev);
4130 return ret;
4131}
4132
4133static void fec_enet_deinit(struct net_device *ndev)
4134{
4135 struct fec_enet_private *fep = netdev_priv(ndev);
4136
4137 netif_napi_del(&fep->napi);
4138 fec_enet_free_queue(ndev);
4139}
4140
4141#ifdef CONFIG_OF
4142static int fec_reset_phy(struct platform_device *pdev)
4143{
4144 struct gpio_desc *phy_reset;
4145 int msec = 1, phy_post_delay = 0;
4146 struct device_node *np = pdev->dev.of_node;
4147 int err;
4148
4149 if (!np)
4150 return 0;
4151
4152 err = of_property_read_u32(np, "phy-reset-duration", &msec);
4153 /* A sane reset duration should not be longer than 1s */
4154 if (!err && msec > 1000)
4155 msec = 1;
4156
4157 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
4158 /* valid reset duration should be less than 1s */
4159 if (!err && phy_post_delay > 1000)
4160 return -EINVAL;
4161
4162 phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset",
4163 GPIOD_OUT_HIGH);
4164 if (IS_ERR(phy_reset))
4165 return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset),
4166 "failed to get phy-reset-gpios\n");
4167
4168 if (!phy_reset)
4169 return 0;
4170
4171 if (msec > 20)
4172 msleep(msec);
4173 else
4174 usleep_range(msec * 1000, msec * 1000 + 1000);
4175
4176 gpiod_set_value_cansleep(phy_reset, 0);
4177
4178 if (!phy_post_delay)
4179 return 0;
4180
4181 if (phy_post_delay > 20)
4182 msleep(phy_post_delay);
4183 else
4184 usleep_range(phy_post_delay * 1000,
4185 phy_post_delay * 1000 + 1000);
4186
4187 return 0;
4188}
4189#else /* CONFIG_OF */
4190static int fec_reset_phy(struct platform_device *pdev)
4191{
4192 /*
4193 * In case of platform probe, the reset has been done
4194 * by machine code.
4195 */
4196 return 0;
4197}
4198#endif /* CONFIG_OF */
4199
4200static void
4201fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
4202{
4203 struct device_node *np = pdev->dev.of_node;
4204
4205 *num_tx = *num_rx = 1;
4206
4207 if (!np || !of_device_is_available(np))
4208 return;
4209
4210 /* parse the num of tx and rx queues */
4211 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
4212
4213 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
4214
4215 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
4216 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
4217 *num_tx);
4218 *num_tx = 1;
4219 return;
4220 }
4221
4222 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
4223 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
4224 *num_rx);
4225 *num_rx = 1;
4226 return;
4227 }
4228
4229}
4230
4231static int fec_enet_get_irq_cnt(struct platform_device *pdev)
4232{
4233 int irq_cnt = platform_irq_count(pdev);
4234
4235 if (irq_cnt > FEC_IRQ_NUM)
4236 irq_cnt = FEC_IRQ_NUM; /* last for pps */
4237 else if (irq_cnt == 2)
4238 irq_cnt = 1; /* last for pps */
4239 else if (irq_cnt <= 0)
4240 irq_cnt = 1; /* At least 1 irq is needed */
4241 return irq_cnt;
4242}
4243
4244static void fec_enet_get_wakeup_irq(struct platform_device *pdev)
4245{
4246 struct net_device *ndev = platform_get_drvdata(pdev);
4247 struct fec_enet_private *fep = netdev_priv(ndev);
4248
4249 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2)
4250 fep->wake_irq = fep->irq[2];
4251 else
4252 fep->wake_irq = fep->irq[0];
4253}
4254
4255static int fec_enet_init_stop_mode(struct fec_enet_private *fep,
4256 struct device_node *np)
4257{
4258 struct device_node *gpr_np;
4259 u32 out_val[3];
4260 int ret = 0;
4261
4262 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0);
4263 if (!gpr_np)
4264 return 0;
4265
4266 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
4267 ARRAY_SIZE(out_val));
4268 if (ret) {
4269 dev_dbg(&fep->pdev->dev, "no stop mode property\n");
4270 goto out;
4271 }
4272
4273 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np);
4274 if (IS_ERR(fep->stop_gpr.gpr)) {
4275 dev_err(&fep->pdev->dev, "could not find gpr regmap\n");
4276 ret = PTR_ERR(fep->stop_gpr.gpr);
4277 fep->stop_gpr.gpr = NULL;
4278 goto out;
4279 }
4280
4281 fep->stop_gpr.reg = out_val[1];
4282 fep->stop_gpr.bit = out_val[2];
4283
4284out:
4285 of_node_put(gpr_np);
4286
4287 return ret;
4288}
4289
4290static int
4291fec_probe(struct platform_device *pdev)
4292{
4293 struct fec_enet_private *fep;
4294 struct fec_platform_data *pdata;
4295 phy_interface_t interface;
4296 struct net_device *ndev;
4297 int i, irq, ret = 0;
4298 static int dev_id;
4299 struct device_node *np = pdev->dev.of_node, *phy_node;
4300 int num_tx_qs;
4301 int num_rx_qs;
4302 char irq_name[8];
4303 int irq_cnt;
4304 const struct fec_devinfo *dev_info;
4305
4306 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
4307
4308 /* Init network device */
4309 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
4310 FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
4311 if (!ndev)
4312 return -ENOMEM;
4313
4314 SET_NETDEV_DEV(ndev, &pdev->dev);
4315
4316 /* setup board info structure */
4317 fep = netdev_priv(ndev);
4318
4319 dev_info = device_get_match_data(&pdev->dev);
4320 if (!dev_info)
4321 dev_info = (const struct fec_devinfo *)pdev->id_entry->driver_data;
4322 if (dev_info)
4323 fep->quirks = dev_info->quirks;
4324
4325 fep->netdev = ndev;
4326 fep->num_rx_queues = num_rx_qs;
4327 fep->num_tx_queues = num_tx_qs;
4328
4329#if !defined(CONFIG_M5272)
4330 /* default enable pause frame auto negotiation */
4331 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
4332 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
4333#endif
4334
4335 /* Select default pin state */
4336 pinctrl_pm_select_default_state(&pdev->dev);
4337
4338 fep->hwp = devm_platform_ioremap_resource(pdev, 0);
4339 if (IS_ERR(fep->hwp)) {
4340 ret = PTR_ERR(fep->hwp);
4341 goto failed_ioremap;
4342 }
4343
4344 fep->pdev = pdev;
4345 fep->dev_id = dev_id++;
4346
4347 platform_set_drvdata(pdev, ndev);
4348
4349 if ((of_machine_is_compatible("fsl,imx6q") ||
4350 of_machine_is_compatible("fsl,imx6dl")) &&
4351 !of_property_read_bool(np, "fsl,err006687-workaround-present"))
4352 fep->quirks |= FEC_QUIRK_ERR006687;
4353
4354 ret = fec_enet_ipc_handle_init(fep);
4355 if (ret)
4356 goto failed_ipc_init;
4357
4358 if (of_property_read_bool(np, "fsl,magic-packet"))
4359 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
4360
4361 ret = fec_enet_init_stop_mode(fep, np);
4362 if (ret)
4363 goto failed_stop_mode;
4364
4365 phy_node = of_parse_phandle(np, "phy-handle", 0);
4366 if (!phy_node && of_phy_is_fixed_link(np)) {
4367 ret = of_phy_register_fixed_link(np);
4368 if (ret < 0) {
4369 dev_err(&pdev->dev,
4370 "broken fixed-link specification\n");
4371 goto failed_phy;
4372 }
4373 phy_node = of_node_get(np);
4374 }
4375 fep->phy_node = phy_node;
4376
4377 ret = of_get_phy_mode(pdev->dev.of_node, &interface);
4378 if (ret) {
4379 pdata = dev_get_platdata(&pdev->dev);
4380 if (pdata)
4381 fep->phy_interface = pdata->phy;
4382 else
4383 fep->phy_interface = PHY_INTERFACE_MODE_MII;
4384 } else {
4385 fep->phy_interface = interface;
4386 }
4387
4388 ret = fec_enet_parse_rgmii_delay(fep, np);
4389 if (ret)
4390 goto failed_rgmii_delay;
4391
4392 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
4393 if (IS_ERR(fep->clk_ipg)) {
4394 ret = PTR_ERR(fep->clk_ipg);
4395 goto failed_clk;
4396 }
4397
4398 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
4399 if (IS_ERR(fep->clk_ahb)) {
4400 ret = PTR_ERR(fep->clk_ahb);
4401 goto failed_clk;
4402 }
4403
4404 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
4405
4406 /* enet_out is optional, depends on board */
4407 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out");
4408 if (IS_ERR(fep->clk_enet_out)) {
4409 ret = PTR_ERR(fep->clk_enet_out);
4410 goto failed_clk;
4411 }
4412
4413 fep->ptp_clk_on = false;
4414 mutex_init(&fep->ptp_clk_mutex);
4415
4416 /* clk_ref is optional, depends on board */
4417 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref");
4418 if (IS_ERR(fep->clk_ref)) {
4419 ret = PTR_ERR(fep->clk_ref);
4420 goto failed_clk;
4421 }
4422 fep->clk_ref_rate = clk_get_rate(fep->clk_ref);
4423
4424 /* clk_2x_txclk is optional, depends on board */
4425 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) {
4426 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk");
4427 if (IS_ERR(fep->clk_2x_txclk))
4428 fep->clk_2x_txclk = NULL;
4429 }
4430
4431 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
4432 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
4433 if (IS_ERR(fep->clk_ptp)) {
4434 fep->clk_ptp = NULL;
4435 fep->bufdesc_ex = false;
4436 }
4437
4438 ret = fec_enet_clk_enable(ndev, true);
4439 if (ret)
4440 goto failed_clk;
4441
4442 ret = clk_prepare_enable(fep->clk_ipg);
4443 if (ret)
4444 goto failed_clk_ipg;
4445 ret = clk_prepare_enable(fep->clk_ahb);
4446 if (ret)
4447 goto failed_clk_ahb;
4448
4449 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy");
4450 if (!IS_ERR(fep->reg_phy)) {
4451 ret = regulator_enable(fep->reg_phy);
4452 if (ret) {
4453 dev_err(&pdev->dev,
4454 "Failed to enable phy regulator: %d\n", ret);
4455 goto failed_regulator;
4456 }
4457 } else {
4458 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
4459 ret = -EPROBE_DEFER;
4460 goto failed_regulator;
4461 }
4462 fep->reg_phy = NULL;
4463 }
4464
4465 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
4466 pm_runtime_use_autosuspend(&pdev->dev);
4467 pm_runtime_get_noresume(&pdev->dev);
4468 pm_runtime_set_active(&pdev->dev);
4469 pm_runtime_enable(&pdev->dev);
4470
4471 ret = fec_reset_phy(pdev);
4472 if (ret)
4473 goto failed_reset;
4474
4475 irq_cnt = fec_enet_get_irq_cnt(pdev);
4476 if (fep->bufdesc_ex)
4477 fec_ptp_init(pdev, irq_cnt);
4478
4479 ret = fec_enet_init(ndev);
4480 if (ret)
4481 goto failed_init;
4482
4483 for (i = 0; i < irq_cnt; i++) {
4484 snprintf(irq_name, sizeof(irq_name), "int%d", i);
4485 irq = platform_get_irq_byname_optional(pdev, irq_name);
4486 if (irq < 0)
4487 irq = platform_get_irq(pdev, i);
4488 if (irq < 0) {
4489 ret = irq;
4490 goto failed_irq;
4491 }
4492 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
4493 0, pdev->name, ndev);
4494 if (ret)
4495 goto failed_irq;
4496
4497 fep->irq[i] = irq;
4498 }
4499
4500 /* Decide which interrupt line is wakeup capable */
4501 fec_enet_get_wakeup_irq(pdev);
4502
4503 ret = fec_enet_mii_init(pdev);
4504 if (ret)
4505 goto failed_mii_init;
4506
4507 /* Carrier starts down, phylib will bring it up */
4508 netif_carrier_off(ndev);
4509 fec_enet_clk_enable(ndev, false);
4510 pinctrl_pm_select_sleep_state(&pdev->dev);
4511
4512 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN;
4513
4514 ret = register_netdev(ndev);
4515 if (ret)
4516 goto failed_register;
4517
4518 device_init_wakeup(&ndev->dev, fep->wol_flag &
4519 FEC_WOL_HAS_MAGIC_PACKET);
4520
4521 if (fep->bufdesc_ex && fep->ptp_clock)
4522 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
4523
4524 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
4525
4526 pm_runtime_mark_last_busy(&pdev->dev);
4527 pm_runtime_put_autosuspend(&pdev->dev);
4528
4529 return 0;
4530
4531failed_register:
4532 fec_enet_mii_remove(fep);
4533failed_mii_init:
4534failed_irq:
4535 fec_enet_deinit(ndev);
4536failed_init:
4537 fec_ptp_stop(pdev);
4538failed_reset:
4539 pm_runtime_put_noidle(&pdev->dev);
4540 pm_runtime_disable(&pdev->dev);
4541 if (fep->reg_phy)
4542 regulator_disable(fep->reg_phy);
4543failed_regulator:
4544 clk_disable_unprepare(fep->clk_ahb);
4545failed_clk_ahb:
4546 clk_disable_unprepare(fep->clk_ipg);
4547failed_clk_ipg:
4548 fec_enet_clk_enable(ndev, false);
4549failed_clk:
4550failed_rgmii_delay:
4551 if (of_phy_is_fixed_link(np))
4552 of_phy_deregister_fixed_link(np);
4553 of_node_put(phy_node);
4554failed_stop_mode:
4555failed_ipc_init:
4556failed_phy:
4557 dev_id--;
4558failed_ioremap:
4559 free_netdev(ndev);
4560
4561 return ret;
4562}
4563
4564static void
4565fec_drv_remove(struct platform_device *pdev)
4566{
4567 struct net_device *ndev = platform_get_drvdata(pdev);
4568 struct fec_enet_private *fep = netdev_priv(ndev);
4569 struct device_node *np = pdev->dev.of_node;
4570 int ret;
4571
4572 ret = pm_runtime_get_sync(&pdev->dev);
4573 if (ret < 0)
4574 dev_err(&pdev->dev,
4575 "Failed to resume device in remove callback (%pe)\n",
4576 ERR_PTR(ret));
4577
4578 cancel_work_sync(&fep->tx_timeout_work);
4579 fec_ptp_stop(pdev);
4580 unregister_netdev(ndev);
4581 fec_enet_mii_remove(fep);
4582 if (fep->reg_phy)
4583 regulator_disable(fep->reg_phy);
4584
4585 if (of_phy_is_fixed_link(np))
4586 of_phy_deregister_fixed_link(np);
4587 of_node_put(fep->phy_node);
4588
4589 /* After pm_runtime_get_sync() failed, the clks are still off, so skip
4590 * disabling them again.
4591 */
4592 if (ret >= 0) {
4593 clk_disable_unprepare(fep->clk_ahb);
4594 clk_disable_unprepare(fep->clk_ipg);
4595 }
4596 pm_runtime_put_noidle(&pdev->dev);
4597 pm_runtime_disable(&pdev->dev);
4598
4599 fec_enet_deinit(ndev);
4600 free_netdev(ndev);
4601}
4602
4603static int __maybe_unused fec_suspend(struct device *dev)
4604{
4605 struct net_device *ndev = dev_get_drvdata(dev);
4606 struct fec_enet_private *fep = netdev_priv(ndev);
4607 int ret;
4608
4609 rtnl_lock();
4610 if (netif_running(ndev)) {
4611 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
4612 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
4613 phy_stop(ndev->phydev);
4614 napi_disable(&fep->napi);
4615 netif_tx_lock_bh(ndev);
4616 netif_device_detach(ndev);
4617 netif_tx_unlock_bh(ndev);
4618 fec_stop(ndev);
4619 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
4620 fec_irqs_disable(ndev);
4621 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
4622 } else {
4623 fec_irqs_disable_except_wakeup(ndev);
4624 if (fep->wake_irq > 0) {
4625 disable_irq(fep->wake_irq);
4626 enable_irq_wake(fep->wake_irq);
4627 }
4628 fec_enet_stop_mode(fep, true);
4629 }
4630 /* It's safe to disable clocks since interrupts are masked */
4631 fec_enet_clk_enable(ndev, false);
4632
4633 fep->rpm_active = !pm_runtime_status_suspended(dev);
4634 if (fep->rpm_active) {
4635 ret = pm_runtime_force_suspend(dev);
4636 if (ret < 0) {
4637 rtnl_unlock();
4638 return ret;
4639 }
4640 }
4641 }
4642 rtnl_unlock();
4643
4644 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
4645 regulator_disable(fep->reg_phy);
4646
4647 /* SOC supply clock to phy, when clock is disabled, phy link down
4648 * SOC control phy regulator, when regulator is disabled, phy link down
4649 */
4650 if (fep->clk_enet_out || fep->reg_phy)
4651 fep->link = 0;
4652
4653 return 0;
4654}
4655
4656static int __maybe_unused fec_resume(struct device *dev)
4657{
4658 struct net_device *ndev = dev_get_drvdata(dev);
4659 struct fec_enet_private *fep = netdev_priv(ndev);
4660 int ret;
4661 int val;
4662
4663 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
4664 ret = regulator_enable(fep->reg_phy);
4665 if (ret)
4666 return ret;
4667 }
4668
4669 rtnl_lock();
4670 if (netif_running(ndev)) {
4671 if (fep->rpm_active)
4672 pm_runtime_force_resume(dev);
4673
4674 ret = fec_enet_clk_enable(ndev, true);
4675 if (ret) {
4676 rtnl_unlock();
4677 goto failed_clk;
4678 }
4679 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
4680 fec_enet_stop_mode(fep, false);
4681 if (fep->wake_irq) {
4682 disable_irq_wake(fep->wake_irq);
4683 enable_irq(fep->wake_irq);
4684 }
4685
4686 val = readl(fep->hwp + FEC_ECNTRL);
4687 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
4688 writel(val, fep->hwp + FEC_ECNTRL);
4689 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
4690 } else {
4691 pinctrl_pm_select_default_state(&fep->pdev->dev);
4692 }
4693 fec_restart(ndev);
4694 netif_tx_lock_bh(ndev);
4695 netif_device_attach(ndev);
4696 netif_tx_unlock_bh(ndev);
4697 napi_enable(&fep->napi);
4698 phy_init_hw(ndev->phydev);
4699 phy_start(ndev->phydev);
4700 }
4701 rtnl_unlock();
4702
4703 return 0;
4704
4705failed_clk:
4706 if (fep->reg_phy)
4707 regulator_disable(fep->reg_phy);
4708 return ret;
4709}
4710
4711static int __maybe_unused fec_runtime_suspend(struct device *dev)
4712{
4713 struct net_device *ndev = dev_get_drvdata(dev);
4714 struct fec_enet_private *fep = netdev_priv(ndev);
4715
4716 clk_disable_unprepare(fep->clk_ahb);
4717 clk_disable_unprepare(fep->clk_ipg);
4718
4719 return 0;
4720}
4721
4722static int __maybe_unused fec_runtime_resume(struct device *dev)
4723{
4724 struct net_device *ndev = dev_get_drvdata(dev);
4725 struct fec_enet_private *fep = netdev_priv(ndev);
4726 int ret;
4727
4728 ret = clk_prepare_enable(fep->clk_ahb);
4729 if (ret)
4730 return ret;
4731 ret = clk_prepare_enable(fep->clk_ipg);
4732 if (ret)
4733 goto failed_clk_ipg;
4734
4735 return 0;
4736
4737failed_clk_ipg:
4738 clk_disable_unprepare(fep->clk_ahb);
4739 return ret;
4740}
4741
4742static const struct dev_pm_ops fec_pm_ops = {
4743 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
4744 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
4745};
4746
4747static struct platform_driver fec_driver = {
4748 .driver = {
4749 .name = DRIVER_NAME,
4750 .pm = &fec_pm_ops,
4751 .of_match_table = fec_dt_ids,
4752 .suppress_bind_attrs = true,
4753 },
4754 .id_table = fec_devtype,
4755 .probe = fec_probe,
4756 .remove_new = fec_drv_remove,
4757};
4758
4759module_platform_driver(fec_driver);
4760
4761MODULE_DESCRIPTION("NXP Fast Ethernet Controller (FEC) driver");
4762MODULE_LICENSE("GPL");