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1/*
2 * Copyright (C) 1994 Linus Torvalds
3 *
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 */
8#include <asm/fpu/internal.h>
9#include <asm/fpu/regset.h>
10#include <asm/fpu/signal.h>
11#include <asm/fpu/types.h>
12#include <asm/traps.h>
13
14#include <linux/hardirq.h>
15#include <linux/pkeys.h>
16
17#define CREATE_TRACE_POINTS
18#include <asm/trace/fpu.h>
19
20/*
21 * Represents the initial FPU state. It's mostly (but not completely) zeroes,
22 * depending on the FPU hardware format:
23 */
24union fpregs_state init_fpstate __read_mostly;
25
26/*
27 * Track whether the kernel is using the FPU state
28 * currently.
29 *
30 * This flag is used:
31 *
32 * - by IRQ context code to potentially use the FPU
33 * if it's unused.
34 *
35 * - to debug kernel_fpu_begin()/end() correctness
36 */
37static DEFINE_PER_CPU(bool, in_kernel_fpu);
38
39/*
40 * Track which context is using the FPU on the CPU:
41 */
42DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
43
44static void kernel_fpu_disable(void)
45{
46 WARN_ON_FPU(this_cpu_read(in_kernel_fpu));
47 this_cpu_write(in_kernel_fpu, true);
48}
49
50static void kernel_fpu_enable(void)
51{
52 WARN_ON_FPU(!this_cpu_read(in_kernel_fpu));
53 this_cpu_write(in_kernel_fpu, false);
54}
55
56static bool kernel_fpu_disabled(void)
57{
58 return this_cpu_read(in_kernel_fpu);
59}
60
61static bool interrupted_kernel_fpu_idle(void)
62{
63 return !kernel_fpu_disabled();
64}
65
66/*
67 * Were we in user mode (or vm86 mode) when we were
68 * interrupted?
69 *
70 * Doing kernel_fpu_begin/end() is ok if we are running
71 * in an interrupt context from user mode - we'll just
72 * save the FPU state as required.
73 */
74static bool interrupted_user_mode(void)
75{
76 struct pt_regs *regs = get_irq_regs();
77 return regs && user_mode(regs);
78}
79
80/*
81 * Can we use the FPU in kernel mode with the
82 * whole "kernel_fpu_begin/end()" sequence?
83 *
84 * It's always ok in process context (ie "not interrupt")
85 * but it is sometimes ok even from an irq.
86 */
87bool irq_fpu_usable(void)
88{
89 return !in_interrupt() ||
90 interrupted_user_mode() ||
91 interrupted_kernel_fpu_idle();
92}
93EXPORT_SYMBOL(irq_fpu_usable);
94
95void __kernel_fpu_begin(void)
96{
97 struct fpu *fpu = ¤t->thread.fpu;
98
99 WARN_ON_FPU(!irq_fpu_usable());
100
101 kernel_fpu_disable();
102
103 if (fpu->initialized) {
104 /*
105 * Ignore return value -- we don't care if reg state
106 * is clobbered.
107 */
108 copy_fpregs_to_fpstate(fpu);
109 } else {
110 __cpu_invalidate_fpregs_state();
111 }
112}
113EXPORT_SYMBOL(__kernel_fpu_begin);
114
115void __kernel_fpu_end(void)
116{
117 struct fpu *fpu = ¤t->thread.fpu;
118
119 if (fpu->initialized)
120 copy_kernel_to_fpregs(&fpu->state);
121
122 kernel_fpu_enable();
123}
124EXPORT_SYMBOL(__kernel_fpu_end);
125
126void kernel_fpu_begin(void)
127{
128 preempt_disable();
129 __kernel_fpu_begin();
130}
131EXPORT_SYMBOL_GPL(kernel_fpu_begin);
132
133void kernel_fpu_end(void)
134{
135 __kernel_fpu_end();
136 preempt_enable();
137}
138EXPORT_SYMBOL_GPL(kernel_fpu_end);
139
140/*
141 * Save the FPU state (mark it for reload if necessary):
142 *
143 * This only ever gets called for the current task.
144 */
145void fpu__save(struct fpu *fpu)
146{
147 WARN_ON_FPU(fpu != ¤t->thread.fpu);
148
149 preempt_disable();
150 trace_x86_fpu_before_save(fpu);
151 if (fpu->initialized) {
152 if (!copy_fpregs_to_fpstate(fpu)) {
153 copy_kernel_to_fpregs(&fpu->state);
154 }
155 }
156 trace_x86_fpu_after_save(fpu);
157 preempt_enable();
158}
159EXPORT_SYMBOL_GPL(fpu__save);
160
161/*
162 * Legacy x87 fpstate state init:
163 */
164static inline void fpstate_init_fstate(struct fregs_state *fp)
165{
166 fp->cwd = 0xffff037fu;
167 fp->swd = 0xffff0000u;
168 fp->twd = 0xffffffffu;
169 fp->fos = 0xffff0000u;
170}
171
172void fpstate_init(union fpregs_state *state)
173{
174 if (!static_cpu_has(X86_FEATURE_FPU)) {
175 fpstate_init_soft(&state->soft);
176 return;
177 }
178
179 memset(state, 0, fpu_kernel_xstate_size);
180
181 if (static_cpu_has(X86_FEATURE_XSAVES))
182 fpstate_init_xstate(&state->xsave);
183 if (static_cpu_has(X86_FEATURE_FXSR))
184 fpstate_init_fxstate(&state->fxsave);
185 else
186 fpstate_init_fstate(&state->fsave);
187}
188EXPORT_SYMBOL_GPL(fpstate_init);
189
190int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu)
191{
192 dst_fpu->last_cpu = -1;
193
194 if (!src_fpu->initialized || !static_cpu_has(X86_FEATURE_FPU))
195 return 0;
196
197 WARN_ON_FPU(src_fpu != ¤t->thread.fpu);
198
199 /*
200 * Don't let 'init optimized' areas of the XSAVE area
201 * leak into the child task:
202 */
203 memset(&dst_fpu->state.xsave, 0, fpu_kernel_xstate_size);
204
205 /*
206 * Save current FPU registers directly into the child
207 * FPU context, without any memory-to-memory copying.
208 *
209 * ( The function 'fails' in the FNSAVE case, which destroys
210 * register contents so we have to copy them back. )
211 */
212 if (!copy_fpregs_to_fpstate(dst_fpu)) {
213 memcpy(&src_fpu->state, &dst_fpu->state, fpu_kernel_xstate_size);
214 copy_kernel_to_fpregs(&src_fpu->state);
215 }
216
217 trace_x86_fpu_copy_src(src_fpu);
218 trace_x86_fpu_copy_dst(dst_fpu);
219
220 return 0;
221}
222
223/*
224 * Activate the current task's in-memory FPU context,
225 * if it has not been used before:
226 */
227void fpu__initialize(struct fpu *fpu)
228{
229 WARN_ON_FPU(fpu != ¤t->thread.fpu);
230
231 if (!fpu->initialized) {
232 fpstate_init(&fpu->state);
233 trace_x86_fpu_init_state(fpu);
234
235 trace_x86_fpu_activate_state(fpu);
236 /* Safe to do for the current task: */
237 fpu->initialized = 1;
238 }
239}
240EXPORT_SYMBOL_GPL(fpu__initialize);
241
242/*
243 * This function must be called before we read a task's fpstate.
244 *
245 * There's two cases where this gets called:
246 *
247 * - for the current task (when coredumping), in which case we have
248 * to save the latest FPU registers into the fpstate,
249 *
250 * - or it's called for stopped tasks (ptrace), in which case the
251 * registers were already saved by the context-switch code when
252 * the task scheduled out - we only have to initialize the registers
253 * if they've never been initialized.
254 *
255 * If the task has used the FPU before then save it.
256 */
257void fpu__prepare_read(struct fpu *fpu)
258{
259 if (fpu == ¤t->thread.fpu) {
260 fpu__save(fpu);
261 } else {
262 if (!fpu->initialized) {
263 fpstate_init(&fpu->state);
264 trace_x86_fpu_init_state(fpu);
265
266 trace_x86_fpu_activate_state(fpu);
267 /* Safe to do for current and for stopped child tasks: */
268 fpu->initialized = 1;
269 }
270 }
271}
272
273/*
274 * This function must be called before we write a task's fpstate.
275 *
276 * If the task has used the FPU before then invalidate any cached FPU registers.
277 * If the task has not used the FPU before then initialize its fpstate.
278 *
279 * After this function call, after registers in the fpstate are
280 * modified and the child task has woken up, the child task will
281 * restore the modified FPU state from the modified context. If we
282 * didn't clear its cached status here then the cached in-registers
283 * state pending on its former CPU could be restored, corrupting
284 * the modifications.
285 */
286void fpu__prepare_write(struct fpu *fpu)
287{
288 /*
289 * Only stopped child tasks can be used to modify the FPU
290 * state in the fpstate buffer:
291 */
292 WARN_ON_FPU(fpu == ¤t->thread.fpu);
293
294 if (fpu->initialized) {
295 /* Invalidate any cached state: */
296 __fpu_invalidate_fpregs_state(fpu);
297 } else {
298 fpstate_init(&fpu->state);
299 trace_x86_fpu_init_state(fpu);
300
301 trace_x86_fpu_activate_state(fpu);
302 /* Safe to do for stopped child tasks: */
303 fpu->initialized = 1;
304 }
305}
306
307/*
308 * 'fpu__restore()' is called to copy FPU registers from
309 * the FPU fpstate to the live hw registers and to activate
310 * access to the hardware registers, so that FPU instructions
311 * can be used afterwards.
312 *
313 * Must be called with kernel preemption disabled (for example
314 * with local interrupts disabled, as it is in the case of
315 * do_device_not_available()).
316 */
317void fpu__restore(struct fpu *fpu)
318{
319 fpu__initialize(fpu);
320
321 /* Avoid __kernel_fpu_begin() right after fpregs_activate() */
322 kernel_fpu_disable();
323 trace_x86_fpu_before_restore(fpu);
324 fpregs_activate(fpu);
325 copy_kernel_to_fpregs(&fpu->state);
326 trace_x86_fpu_after_restore(fpu);
327 kernel_fpu_enable();
328}
329EXPORT_SYMBOL_GPL(fpu__restore);
330
331/*
332 * Drops current FPU state: deactivates the fpregs and
333 * the fpstate. NOTE: it still leaves previous contents
334 * in the fpregs in the eager-FPU case.
335 *
336 * This function can be used in cases where we know that
337 * a state-restore is coming: either an explicit one,
338 * or a reschedule.
339 */
340void fpu__drop(struct fpu *fpu)
341{
342 preempt_disable();
343
344 if (fpu == ¤t->thread.fpu) {
345 if (fpu->initialized) {
346 /* Ignore delayed exceptions from user space */
347 asm volatile("1: fwait\n"
348 "2:\n"
349 _ASM_EXTABLE(1b, 2b));
350 fpregs_deactivate(fpu);
351 }
352 }
353
354 fpu->initialized = 0;
355
356 trace_x86_fpu_dropped(fpu);
357
358 preempt_enable();
359}
360
361/*
362 * Clear FPU registers by setting them up from
363 * the init fpstate:
364 */
365static inline void copy_init_fpstate_to_fpregs(void)
366{
367 if (use_xsave())
368 copy_kernel_to_xregs(&init_fpstate.xsave, -1);
369 else if (static_cpu_has(X86_FEATURE_FXSR))
370 copy_kernel_to_fxregs(&init_fpstate.fxsave);
371 else
372 copy_kernel_to_fregs(&init_fpstate.fsave);
373
374 if (boot_cpu_has(X86_FEATURE_OSPKE))
375 copy_init_pkru_to_fpregs();
376}
377
378/*
379 * Clear the FPU state back to init state.
380 *
381 * Called by sys_execve(), by the signal handler code and by various
382 * error paths.
383 */
384void fpu__clear(struct fpu *fpu)
385{
386 WARN_ON_FPU(fpu != ¤t->thread.fpu); /* Almost certainly an anomaly */
387
388 fpu__drop(fpu);
389
390 /*
391 * Make sure fpstate is cleared and initialized.
392 */
393 if (static_cpu_has(X86_FEATURE_FPU)) {
394 preempt_disable();
395 fpu__initialize(fpu);
396 user_fpu_begin();
397 copy_init_fpstate_to_fpregs();
398 preempt_enable();
399 }
400}
401
402/*
403 * x87 math exception handling:
404 */
405
406int fpu__exception_code(struct fpu *fpu, int trap_nr)
407{
408 int err;
409
410 if (trap_nr == X86_TRAP_MF) {
411 unsigned short cwd, swd;
412 /*
413 * (~cwd & swd) will mask out exceptions that are not set to unmasked
414 * status. 0x3f is the exception bits in these regs, 0x200 is the
415 * C1 reg you need in case of a stack fault, 0x040 is the stack
416 * fault bit. We should only be taking one exception at a time,
417 * so if this combination doesn't produce any single exception,
418 * then we have a bad program that isn't synchronizing its FPU usage
419 * and it will suffer the consequences since we won't be able to
420 * fully reproduce the context of the exception.
421 */
422 if (boot_cpu_has(X86_FEATURE_FXSR)) {
423 cwd = fpu->state.fxsave.cwd;
424 swd = fpu->state.fxsave.swd;
425 } else {
426 cwd = (unsigned short)fpu->state.fsave.cwd;
427 swd = (unsigned short)fpu->state.fsave.swd;
428 }
429
430 err = swd & ~cwd;
431 } else {
432 /*
433 * The SIMD FPU exceptions are handled a little differently, as there
434 * is only a single status/control register. Thus, to determine which
435 * unmasked exception was caught we must mask the exception mask bits
436 * at 0x1f80, and then use these to mask the exception bits at 0x3f.
437 */
438 unsigned short mxcsr = MXCSR_DEFAULT;
439
440 if (boot_cpu_has(X86_FEATURE_XMM))
441 mxcsr = fpu->state.fxsave.mxcsr;
442
443 err = ~(mxcsr >> 7) & mxcsr;
444 }
445
446 if (err & 0x001) { /* Invalid op */
447 /*
448 * swd & 0x240 == 0x040: Stack Underflow
449 * swd & 0x240 == 0x240: Stack Overflow
450 * User must clear the SF bit (0x40) if set
451 */
452 return FPE_FLTINV;
453 } else if (err & 0x004) { /* Divide by Zero */
454 return FPE_FLTDIV;
455 } else if (err & 0x008) { /* Overflow */
456 return FPE_FLTOVF;
457 } else if (err & 0x012) { /* Denormal, Underflow */
458 return FPE_FLTUND;
459 } else if (err & 0x020) { /* Precision */
460 return FPE_FLTRES;
461 }
462
463 /*
464 * If we're using IRQ 13, or supposedly even some trap
465 * X86_TRAP_MF implementations, it's possible
466 * we get a spurious trap, which is not an error.
467 */
468 return 0;
469}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 1994 Linus Torvalds
4 *
5 * Pentium III FXSR, SSE support
6 * General FPU state handling cleanups
7 * Gareth Hughes <gareth@valinux.com>, May 2000
8 */
9#include <asm/fpu/api.h>
10#include <asm/fpu/regset.h>
11#include <asm/fpu/sched.h>
12#include <asm/fpu/signal.h>
13#include <asm/fpu/types.h>
14#include <asm/traps.h>
15#include <asm/irq_regs.h>
16
17#include <uapi/asm/kvm.h>
18
19#include <linux/hardirq.h>
20#include <linux/pkeys.h>
21#include <linux/vmalloc.h>
22
23#include "context.h"
24#include "internal.h"
25#include "legacy.h"
26#include "xstate.h"
27
28#define CREATE_TRACE_POINTS
29#include <asm/trace/fpu.h>
30
31#ifdef CONFIG_X86_64
32DEFINE_STATIC_KEY_FALSE(__fpu_state_size_dynamic);
33DEFINE_PER_CPU(u64, xfd_state);
34#endif
35
36/* The FPU state configuration data for kernel and user space */
37struct fpu_state_config fpu_kernel_cfg __ro_after_init;
38struct fpu_state_config fpu_user_cfg __ro_after_init;
39
40/*
41 * Represents the initial FPU state. It's mostly (but not completely) zeroes,
42 * depending on the FPU hardware format:
43 */
44struct fpstate init_fpstate __ro_after_init;
45
46/* Track in-kernel FPU usage */
47static DEFINE_PER_CPU(bool, in_kernel_fpu);
48
49/*
50 * Track which context is using the FPU on the CPU:
51 */
52DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
53
54/*
55 * Can we use the FPU in kernel mode with the
56 * whole "kernel_fpu_begin/end()" sequence?
57 */
58bool irq_fpu_usable(void)
59{
60 if (WARN_ON_ONCE(in_nmi()))
61 return false;
62
63 /* In kernel FPU usage already active? */
64 if (this_cpu_read(in_kernel_fpu))
65 return false;
66
67 /*
68 * When not in NMI or hard interrupt context, FPU can be used in:
69 *
70 * - Task context except from within fpregs_lock()'ed critical
71 * regions.
72 *
73 * - Soft interrupt processing context which cannot happen
74 * while in a fpregs_lock()'ed critical region.
75 */
76 if (!in_hardirq())
77 return true;
78
79 /*
80 * In hard interrupt context it's safe when soft interrupts
81 * are enabled, which means the interrupt did not hit in
82 * a fpregs_lock()'ed critical region.
83 */
84 return !softirq_count();
85}
86EXPORT_SYMBOL(irq_fpu_usable);
87
88/*
89 * Track AVX512 state use because it is known to slow the max clock
90 * speed of the core.
91 */
92static void update_avx_timestamp(struct fpu *fpu)
93{
94
95#define AVX512_TRACKING_MASK (XFEATURE_MASK_ZMM_Hi256 | XFEATURE_MASK_Hi16_ZMM)
96
97 if (fpu->fpstate->regs.xsave.header.xfeatures & AVX512_TRACKING_MASK)
98 fpu->avx512_timestamp = jiffies;
99}
100
101/*
102 * Save the FPU register state in fpu->fpstate->regs. The register state is
103 * preserved.
104 *
105 * Must be called with fpregs_lock() held.
106 *
107 * The legacy FNSAVE instruction clears all FPU state unconditionally, so
108 * register state has to be reloaded. That might be a pointless exercise
109 * when the FPU is going to be used by another task right after that. But
110 * this only affects 20+ years old 32bit systems and avoids conditionals all
111 * over the place.
112 *
113 * FXSAVE and all XSAVE variants preserve the FPU register state.
114 */
115void save_fpregs_to_fpstate(struct fpu *fpu)
116{
117 if (likely(use_xsave())) {
118 os_xsave(fpu->fpstate);
119 update_avx_timestamp(fpu);
120 return;
121 }
122
123 if (likely(use_fxsr())) {
124 fxsave(&fpu->fpstate->regs.fxsave);
125 return;
126 }
127
128 /*
129 * Legacy FPU register saving, FNSAVE always clears FPU registers,
130 * so we have to reload them from the memory state.
131 */
132 asm volatile("fnsave %[fp]; fwait" : [fp] "=m" (fpu->fpstate->regs.fsave));
133 frstor(&fpu->fpstate->regs.fsave);
134}
135
136void restore_fpregs_from_fpstate(struct fpstate *fpstate, u64 mask)
137{
138 /*
139 * AMD K7/K8 and later CPUs up to Zen don't save/restore
140 * FDP/FIP/FOP unless an exception is pending. Clear the x87 state
141 * here by setting it to fixed values. "m" is a random variable
142 * that should be in L1.
143 */
144 if (unlikely(static_cpu_has_bug(X86_BUG_FXSAVE_LEAK))) {
145 asm volatile(
146 "fnclex\n\t"
147 "emms\n\t"
148 "fildl %P[addr]" /* set F?P to defined value */
149 : : [addr] "m" (fpstate));
150 }
151
152 if (use_xsave()) {
153 /*
154 * Dynamically enabled features are enabled in XCR0, but
155 * usage requires also that the corresponding bits in XFD
156 * are cleared. If the bits are set then using a related
157 * instruction will raise #NM. This allows to do the
158 * allocation of the larger FPU buffer lazy from #NM or if
159 * the task has no permission to kill it which would happen
160 * via #UD if the feature is disabled in XCR0.
161 *
162 * XFD state is following the same life time rules as
163 * XSTATE and to restore state correctly XFD has to be
164 * updated before XRSTORS otherwise the component would
165 * stay in or go into init state even if the bits are set
166 * in fpstate::regs::xsave::xfeatures.
167 */
168 xfd_update_state(fpstate);
169
170 /*
171 * Restoring state always needs to modify all features
172 * which are in @mask even if the current task cannot use
173 * extended features.
174 *
175 * So fpstate->xfeatures cannot be used here, because then
176 * a feature for which the task has no permission but was
177 * used by the previous task would not go into init state.
178 */
179 mask = fpu_kernel_cfg.max_features & mask;
180
181 os_xrstor(fpstate, mask);
182 } else {
183 if (use_fxsr())
184 fxrstor(&fpstate->regs.fxsave);
185 else
186 frstor(&fpstate->regs.fsave);
187 }
188}
189
190void fpu_reset_from_exception_fixup(void)
191{
192 restore_fpregs_from_fpstate(&init_fpstate, XFEATURE_MASK_FPSTATE);
193}
194
195#if IS_ENABLED(CONFIG_KVM)
196static void __fpstate_reset(struct fpstate *fpstate, u64 xfd);
197
198static void fpu_init_guest_permissions(struct fpu_guest *gfpu)
199{
200 struct fpu_state_perm *fpuperm;
201 u64 perm;
202
203 if (!IS_ENABLED(CONFIG_X86_64))
204 return;
205
206 spin_lock_irq(¤t->sighand->siglock);
207 fpuperm = ¤t->group_leader->thread.fpu.guest_perm;
208 perm = fpuperm->__state_perm;
209
210 /* First fpstate allocation locks down permissions. */
211 WRITE_ONCE(fpuperm->__state_perm, perm | FPU_GUEST_PERM_LOCKED);
212
213 spin_unlock_irq(¤t->sighand->siglock);
214
215 gfpu->perm = perm & ~FPU_GUEST_PERM_LOCKED;
216}
217
218bool fpu_alloc_guest_fpstate(struct fpu_guest *gfpu)
219{
220 struct fpstate *fpstate;
221 unsigned int size;
222
223 size = fpu_user_cfg.default_size + ALIGN(offsetof(struct fpstate, regs), 64);
224 fpstate = vzalloc(size);
225 if (!fpstate)
226 return false;
227
228 /* Leave xfd to 0 (the reset value defined by spec) */
229 __fpstate_reset(fpstate, 0);
230 fpstate_init_user(fpstate);
231 fpstate->is_valloc = true;
232 fpstate->is_guest = true;
233
234 gfpu->fpstate = fpstate;
235 gfpu->xfeatures = fpu_user_cfg.default_features;
236 gfpu->perm = fpu_user_cfg.default_features;
237
238 /*
239 * KVM sets the FP+SSE bits in the XSAVE header when copying FPU state
240 * to userspace, even when XSAVE is unsupported, so that restoring FPU
241 * state on a different CPU that does support XSAVE can cleanly load
242 * the incoming state using its natural XSAVE. In other words, KVM's
243 * uABI size may be larger than this host's default size. Conversely,
244 * the default size should never be larger than KVM's base uABI size;
245 * all features that can expand the uABI size must be opt-in.
246 */
247 gfpu->uabi_size = sizeof(struct kvm_xsave);
248 if (WARN_ON_ONCE(fpu_user_cfg.default_size > gfpu->uabi_size))
249 gfpu->uabi_size = fpu_user_cfg.default_size;
250
251 fpu_init_guest_permissions(gfpu);
252
253 return true;
254}
255EXPORT_SYMBOL_GPL(fpu_alloc_guest_fpstate);
256
257void fpu_free_guest_fpstate(struct fpu_guest *gfpu)
258{
259 struct fpstate *fps = gfpu->fpstate;
260
261 if (!fps)
262 return;
263
264 if (WARN_ON_ONCE(!fps->is_valloc || !fps->is_guest || fps->in_use))
265 return;
266
267 gfpu->fpstate = NULL;
268 vfree(fps);
269}
270EXPORT_SYMBOL_GPL(fpu_free_guest_fpstate);
271
272/*
273 * fpu_enable_guest_xfd_features - Check xfeatures against guest perm and enable
274 * @guest_fpu: Pointer to the guest FPU container
275 * @xfeatures: Features requested by guest CPUID
276 *
277 * Enable all dynamic xfeatures according to guest perm and requested CPUID.
278 *
279 * Return: 0 on success, error code otherwise
280 */
281int fpu_enable_guest_xfd_features(struct fpu_guest *guest_fpu, u64 xfeatures)
282{
283 lockdep_assert_preemption_enabled();
284
285 /* Nothing to do if all requested features are already enabled. */
286 xfeatures &= ~guest_fpu->xfeatures;
287 if (!xfeatures)
288 return 0;
289
290 return __xfd_enable_feature(xfeatures, guest_fpu);
291}
292EXPORT_SYMBOL_GPL(fpu_enable_guest_xfd_features);
293
294#ifdef CONFIG_X86_64
295void fpu_update_guest_xfd(struct fpu_guest *guest_fpu, u64 xfd)
296{
297 fpregs_lock();
298 guest_fpu->fpstate->xfd = xfd;
299 if (guest_fpu->fpstate->in_use)
300 xfd_update_state(guest_fpu->fpstate);
301 fpregs_unlock();
302}
303EXPORT_SYMBOL_GPL(fpu_update_guest_xfd);
304
305/**
306 * fpu_sync_guest_vmexit_xfd_state - Synchronize XFD MSR and software state
307 *
308 * Must be invoked from KVM after a VMEXIT before enabling interrupts when
309 * XFD write emulation is disabled. This is required because the guest can
310 * freely modify XFD and the state at VMEXIT is not guaranteed to be the
311 * same as the state on VMENTER. So software state has to be updated before
312 * any operation which depends on it can take place.
313 *
314 * Note: It can be invoked unconditionally even when write emulation is
315 * enabled for the price of a then pointless MSR read.
316 */
317void fpu_sync_guest_vmexit_xfd_state(void)
318{
319 struct fpstate *fps = current->thread.fpu.fpstate;
320
321 lockdep_assert_irqs_disabled();
322 if (fpu_state_size_dynamic()) {
323 rdmsrl(MSR_IA32_XFD, fps->xfd);
324 __this_cpu_write(xfd_state, fps->xfd);
325 }
326}
327EXPORT_SYMBOL_GPL(fpu_sync_guest_vmexit_xfd_state);
328#endif /* CONFIG_X86_64 */
329
330int fpu_swap_kvm_fpstate(struct fpu_guest *guest_fpu, bool enter_guest)
331{
332 struct fpstate *guest_fps = guest_fpu->fpstate;
333 struct fpu *fpu = ¤t->thread.fpu;
334 struct fpstate *cur_fps = fpu->fpstate;
335
336 fpregs_lock();
337 if (!cur_fps->is_confidential && !test_thread_flag(TIF_NEED_FPU_LOAD))
338 save_fpregs_to_fpstate(fpu);
339
340 /* Swap fpstate */
341 if (enter_guest) {
342 fpu->__task_fpstate = cur_fps;
343 fpu->fpstate = guest_fps;
344 guest_fps->in_use = true;
345 } else {
346 guest_fps->in_use = false;
347 fpu->fpstate = fpu->__task_fpstate;
348 fpu->__task_fpstate = NULL;
349 }
350
351 cur_fps = fpu->fpstate;
352
353 if (!cur_fps->is_confidential) {
354 /* Includes XFD update */
355 restore_fpregs_from_fpstate(cur_fps, XFEATURE_MASK_FPSTATE);
356 } else {
357 /*
358 * XSTATE is restored by firmware from encrypted
359 * memory. Make sure XFD state is correct while
360 * running with guest fpstate
361 */
362 xfd_update_state(cur_fps);
363 }
364
365 fpregs_mark_activate();
366 fpregs_unlock();
367 return 0;
368}
369EXPORT_SYMBOL_GPL(fpu_swap_kvm_fpstate);
370
371void fpu_copy_guest_fpstate_to_uabi(struct fpu_guest *gfpu, void *buf,
372 unsigned int size, u64 xfeatures, u32 pkru)
373{
374 struct fpstate *kstate = gfpu->fpstate;
375 union fpregs_state *ustate = buf;
376 struct membuf mb = { .p = buf, .left = size };
377
378 if (cpu_feature_enabled(X86_FEATURE_XSAVE)) {
379 __copy_xstate_to_uabi_buf(mb, kstate, xfeatures, pkru,
380 XSTATE_COPY_XSAVE);
381 } else {
382 memcpy(&ustate->fxsave, &kstate->regs.fxsave,
383 sizeof(ustate->fxsave));
384 /* Make it restorable on a XSAVE enabled host */
385 ustate->xsave.header.xfeatures = XFEATURE_MASK_FPSSE;
386 }
387}
388EXPORT_SYMBOL_GPL(fpu_copy_guest_fpstate_to_uabi);
389
390int fpu_copy_uabi_to_guest_fpstate(struct fpu_guest *gfpu, const void *buf,
391 u64 xcr0, u32 *vpkru)
392{
393 struct fpstate *kstate = gfpu->fpstate;
394 const union fpregs_state *ustate = buf;
395
396 if (!cpu_feature_enabled(X86_FEATURE_XSAVE)) {
397 if (ustate->xsave.header.xfeatures & ~XFEATURE_MASK_FPSSE)
398 return -EINVAL;
399 if (ustate->fxsave.mxcsr & ~mxcsr_feature_mask)
400 return -EINVAL;
401 memcpy(&kstate->regs.fxsave, &ustate->fxsave, sizeof(ustate->fxsave));
402 return 0;
403 }
404
405 if (ustate->xsave.header.xfeatures & ~xcr0)
406 return -EINVAL;
407
408 /*
409 * Nullify @vpkru to preserve its current value if PKRU's bit isn't set
410 * in the header. KVM's odd ABI is to leave PKRU untouched in this
411 * case (all other components are eventually re-initialized).
412 */
413 if (!(ustate->xsave.header.xfeatures & XFEATURE_MASK_PKRU))
414 vpkru = NULL;
415
416 return copy_uabi_from_kernel_to_xstate(kstate, ustate, vpkru);
417}
418EXPORT_SYMBOL_GPL(fpu_copy_uabi_to_guest_fpstate);
419#endif /* CONFIG_KVM */
420
421void kernel_fpu_begin_mask(unsigned int kfpu_mask)
422{
423 preempt_disable();
424
425 WARN_ON_FPU(!irq_fpu_usable());
426 WARN_ON_FPU(this_cpu_read(in_kernel_fpu));
427
428 this_cpu_write(in_kernel_fpu, true);
429
430 if (!(current->flags & (PF_KTHREAD | PF_USER_WORKER)) &&
431 !test_thread_flag(TIF_NEED_FPU_LOAD)) {
432 set_thread_flag(TIF_NEED_FPU_LOAD);
433 save_fpregs_to_fpstate(¤t->thread.fpu);
434 }
435 __cpu_invalidate_fpregs_state();
436
437 /* Put sane initial values into the control registers. */
438 if (likely(kfpu_mask & KFPU_MXCSR) && boot_cpu_has(X86_FEATURE_XMM))
439 ldmxcsr(MXCSR_DEFAULT);
440
441 if (unlikely(kfpu_mask & KFPU_387) && boot_cpu_has(X86_FEATURE_FPU))
442 asm volatile ("fninit");
443}
444EXPORT_SYMBOL_GPL(kernel_fpu_begin_mask);
445
446void kernel_fpu_end(void)
447{
448 WARN_ON_FPU(!this_cpu_read(in_kernel_fpu));
449
450 this_cpu_write(in_kernel_fpu, false);
451 preempt_enable();
452}
453EXPORT_SYMBOL_GPL(kernel_fpu_end);
454
455/*
456 * Sync the FPU register state to current's memory register state when the
457 * current task owns the FPU. The hardware register state is preserved.
458 */
459void fpu_sync_fpstate(struct fpu *fpu)
460{
461 WARN_ON_FPU(fpu != ¤t->thread.fpu);
462
463 fpregs_lock();
464 trace_x86_fpu_before_save(fpu);
465
466 if (!test_thread_flag(TIF_NEED_FPU_LOAD))
467 save_fpregs_to_fpstate(fpu);
468
469 trace_x86_fpu_after_save(fpu);
470 fpregs_unlock();
471}
472
473static inline unsigned int init_fpstate_copy_size(void)
474{
475 if (!use_xsave())
476 return fpu_kernel_cfg.default_size;
477
478 /* XSAVE(S) just needs the legacy and the xstate header part */
479 return sizeof(init_fpstate.regs.xsave);
480}
481
482static inline void fpstate_init_fxstate(struct fpstate *fpstate)
483{
484 fpstate->regs.fxsave.cwd = 0x37f;
485 fpstate->regs.fxsave.mxcsr = MXCSR_DEFAULT;
486}
487
488/*
489 * Legacy x87 fpstate state init:
490 */
491static inline void fpstate_init_fstate(struct fpstate *fpstate)
492{
493 fpstate->regs.fsave.cwd = 0xffff037fu;
494 fpstate->regs.fsave.swd = 0xffff0000u;
495 fpstate->regs.fsave.twd = 0xffffffffu;
496 fpstate->regs.fsave.fos = 0xffff0000u;
497}
498
499/*
500 * Used in two places:
501 * 1) Early boot to setup init_fpstate for non XSAVE systems
502 * 2) fpu_init_fpstate_user() which is invoked from KVM
503 */
504void fpstate_init_user(struct fpstate *fpstate)
505{
506 if (!cpu_feature_enabled(X86_FEATURE_FPU)) {
507 fpstate_init_soft(&fpstate->regs.soft);
508 return;
509 }
510
511 xstate_init_xcomp_bv(&fpstate->regs.xsave, fpstate->xfeatures);
512
513 if (cpu_feature_enabled(X86_FEATURE_FXSR))
514 fpstate_init_fxstate(fpstate);
515 else
516 fpstate_init_fstate(fpstate);
517}
518
519static void __fpstate_reset(struct fpstate *fpstate, u64 xfd)
520{
521 /* Initialize sizes and feature masks */
522 fpstate->size = fpu_kernel_cfg.default_size;
523 fpstate->user_size = fpu_user_cfg.default_size;
524 fpstate->xfeatures = fpu_kernel_cfg.default_features;
525 fpstate->user_xfeatures = fpu_user_cfg.default_features;
526 fpstate->xfd = xfd;
527}
528
529void fpstate_reset(struct fpu *fpu)
530{
531 /* Set the fpstate pointer to the default fpstate */
532 fpu->fpstate = &fpu->__fpstate;
533 __fpstate_reset(fpu->fpstate, init_fpstate.xfd);
534
535 /* Initialize the permission related info in fpu */
536 fpu->perm.__state_perm = fpu_kernel_cfg.default_features;
537 fpu->perm.__state_size = fpu_kernel_cfg.default_size;
538 fpu->perm.__user_state_size = fpu_user_cfg.default_size;
539 /* Same defaults for guests */
540 fpu->guest_perm = fpu->perm;
541}
542
543static inline void fpu_inherit_perms(struct fpu *dst_fpu)
544{
545 if (fpu_state_size_dynamic()) {
546 struct fpu *src_fpu = ¤t->group_leader->thread.fpu;
547
548 spin_lock_irq(¤t->sighand->siglock);
549 /* Fork also inherits the permissions of the parent */
550 dst_fpu->perm = src_fpu->perm;
551 dst_fpu->guest_perm = src_fpu->guest_perm;
552 spin_unlock_irq(¤t->sighand->siglock);
553 }
554}
555
556/* A passed ssp of zero will not cause any update */
557static int update_fpu_shstk(struct task_struct *dst, unsigned long ssp)
558{
559#ifdef CONFIG_X86_USER_SHADOW_STACK
560 struct cet_user_state *xstate;
561
562 /* If ssp update is not needed. */
563 if (!ssp)
564 return 0;
565
566 xstate = get_xsave_addr(&dst->thread.fpu.fpstate->regs.xsave,
567 XFEATURE_CET_USER);
568
569 /*
570 * If there is a non-zero ssp, then 'dst' must be configured with a shadow
571 * stack and the fpu state should be up to date since it was just copied
572 * from the parent in fpu_clone(). So there must be a valid non-init CET
573 * state location in the buffer.
574 */
575 if (WARN_ON_ONCE(!xstate))
576 return 1;
577
578 xstate->user_ssp = (u64)ssp;
579#endif
580 return 0;
581}
582
583/* Clone current's FPU state on fork */
584int fpu_clone(struct task_struct *dst, unsigned long clone_flags, bool minimal,
585 unsigned long ssp)
586{
587 struct fpu *src_fpu = ¤t->thread.fpu;
588 struct fpu *dst_fpu = &dst->thread.fpu;
589
590 /* The new task's FPU state cannot be valid in the hardware. */
591 dst_fpu->last_cpu = -1;
592
593 fpstate_reset(dst_fpu);
594
595 if (!cpu_feature_enabled(X86_FEATURE_FPU))
596 return 0;
597
598 /*
599 * Enforce reload for user space tasks and prevent kernel threads
600 * from trying to save the FPU registers on context switch.
601 */
602 set_tsk_thread_flag(dst, TIF_NEED_FPU_LOAD);
603
604 /*
605 * No FPU state inheritance for kernel threads and IO
606 * worker threads.
607 */
608 if (minimal) {
609 /* Clear out the minimal state */
610 memcpy(&dst_fpu->fpstate->regs, &init_fpstate.regs,
611 init_fpstate_copy_size());
612 return 0;
613 }
614
615 /*
616 * If a new feature is added, ensure all dynamic features are
617 * caller-saved from here!
618 */
619 BUILD_BUG_ON(XFEATURE_MASK_USER_DYNAMIC != XFEATURE_MASK_XTILE_DATA);
620
621 /*
622 * Save the default portion of the current FPU state into the
623 * clone. Assume all dynamic features to be defined as caller-
624 * saved, which enables skipping both the expansion of fpstate
625 * and the copying of any dynamic state.
626 *
627 * Do not use memcpy() when TIF_NEED_FPU_LOAD is set because
628 * copying is not valid when current uses non-default states.
629 */
630 fpregs_lock();
631 if (test_thread_flag(TIF_NEED_FPU_LOAD))
632 fpregs_restore_userregs();
633 save_fpregs_to_fpstate(dst_fpu);
634 fpregs_unlock();
635 if (!(clone_flags & CLONE_THREAD))
636 fpu_inherit_perms(dst_fpu);
637
638 /*
639 * Children never inherit PASID state.
640 * Force it to have its init value:
641 */
642 if (use_xsave())
643 dst_fpu->fpstate->regs.xsave.header.xfeatures &= ~XFEATURE_MASK_PASID;
644
645 /*
646 * Update shadow stack pointer, in case it changed during clone.
647 */
648 if (update_fpu_shstk(dst, ssp))
649 return 1;
650
651 trace_x86_fpu_copy_src(src_fpu);
652 trace_x86_fpu_copy_dst(dst_fpu);
653
654 return 0;
655}
656
657/*
658 * Whitelist the FPU register state embedded into task_struct for hardened
659 * usercopy.
660 */
661void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size)
662{
663 *offset = offsetof(struct thread_struct, fpu.__fpstate.regs);
664 *size = fpu_kernel_cfg.default_size;
665}
666
667/*
668 * Drops current FPU state: deactivates the fpregs and
669 * the fpstate. NOTE: it still leaves previous contents
670 * in the fpregs in the eager-FPU case.
671 *
672 * This function can be used in cases where we know that
673 * a state-restore is coming: either an explicit one,
674 * or a reschedule.
675 */
676void fpu__drop(struct fpu *fpu)
677{
678 preempt_disable();
679
680 if (fpu == ¤t->thread.fpu) {
681 /* Ignore delayed exceptions from user space */
682 asm volatile("1: fwait\n"
683 "2:\n"
684 _ASM_EXTABLE(1b, 2b));
685 fpregs_deactivate(fpu);
686 }
687
688 trace_x86_fpu_dropped(fpu);
689
690 preempt_enable();
691}
692
693/*
694 * Clear FPU registers by setting them up from the init fpstate.
695 * Caller must do fpregs_[un]lock() around it.
696 */
697static inline void restore_fpregs_from_init_fpstate(u64 features_mask)
698{
699 if (use_xsave())
700 os_xrstor(&init_fpstate, features_mask);
701 else if (use_fxsr())
702 fxrstor(&init_fpstate.regs.fxsave);
703 else
704 frstor(&init_fpstate.regs.fsave);
705
706 pkru_write_default();
707}
708
709/*
710 * Reset current->fpu memory state to the init values.
711 */
712static void fpu_reset_fpregs(void)
713{
714 struct fpu *fpu = ¤t->thread.fpu;
715
716 fpregs_lock();
717 __fpu_invalidate_fpregs_state(fpu);
718 /*
719 * This does not change the actual hardware registers. It just
720 * resets the memory image and sets TIF_NEED_FPU_LOAD so a
721 * subsequent return to usermode will reload the registers from the
722 * task's memory image.
723 *
724 * Do not use fpstate_init() here. Just copy init_fpstate which has
725 * the correct content already except for PKRU.
726 *
727 * PKRU handling does not rely on the xstate when restoring for
728 * user space as PKRU is eagerly written in switch_to() and
729 * flush_thread().
730 */
731 memcpy(&fpu->fpstate->regs, &init_fpstate.regs, init_fpstate_copy_size());
732 set_thread_flag(TIF_NEED_FPU_LOAD);
733 fpregs_unlock();
734}
735
736/*
737 * Reset current's user FPU states to the init states. current's
738 * supervisor states, if any, are not modified by this function. The
739 * caller guarantees that the XSTATE header in memory is intact.
740 */
741void fpu__clear_user_states(struct fpu *fpu)
742{
743 WARN_ON_FPU(fpu != ¤t->thread.fpu);
744
745 fpregs_lock();
746 if (!cpu_feature_enabled(X86_FEATURE_FPU)) {
747 fpu_reset_fpregs();
748 fpregs_unlock();
749 return;
750 }
751
752 /*
753 * Ensure that current's supervisor states are loaded into their
754 * corresponding registers.
755 */
756 if (xfeatures_mask_supervisor() &&
757 !fpregs_state_valid(fpu, smp_processor_id()))
758 os_xrstor_supervisor(fpu->fpstate);
759
760 /* Reset user states in registers. */
761 restore_fpregs_from_init_fpstate(XFEATURE_MASK_USER_RESTORE);
762
763 /*
764 * Now all FPU registers have their desired values. Inform the FPU
765 * state machine that current's FPU registers are in the hardware
766 * registers. The memory image does not need to be updated because
767 * any operation relying on it has to save the registers first when
768 * current's FPU is marked active.
769 */
770 fpregs_mark_activate();
771 fpregs_unlock();
772}
773
774void fpu_flush_thread(void)
775{
776 fpstate_reset(¤t->thread.fpu);
777 fpu_reset_fpregs();
778}
779/*
780 * Load FPU context before returning to userspace.
781 */
782void switch_fpu_return(void)
783{
784 if (!static_cpu_has(X86_FEATURE_FPU))
785 return;
786
787 fpregs_restore_userregs();
788}
789EXPORT_SYMBOL_GPL(switch_fpu_return);
790
791void fpregs_lock_and_load(void)
792{
793 /*
794 * fpregs_lock() only disables preemption (mostly). So modifying state
795 * in an interrupt could screw up some in progress fpregs operation.
796 * Warn about it.
797 */
798 WARN_ON_ONCE(!irq_fpu_usable());
799 WARN_ON_ONCE(current->flags & PF_KTHREAD);
800
801 fpregs_lock();
802
803 fpregs_assert_state_consistent();
804
805 if (test_thread_flag(TIF_NEED_FPU_LOAD))
806 fpregs_restore_userregs();
807}
808
809#ifdef CONFIG_X86_DEBUG_FPU
810/*
811 * If current FPU state according to its tracking (loaded FPU context on this
812 * CPU) is not valid then we must have TIF_NEED_FPU_LOAD set so the context is
813 * loaded on return to userland.
814 */
815void fpregs_assert_state_consistent(void)
816{
817 struct fpu *fpu = ¤t->thread.fpu;
818
819 if (test_thread_flag(TIF_NEED_FPU_LOAD))
820 return;
821
822 WARN_ON_FPU(!fpregs_state_valid(fpu, smp_processor_id()));
823}
824EXPORT_SYMBOL_GPL(fpregs_assert_state_consistent);
825#endif
826
827void fpregs_mark_activate(void)
828{
829 struct fpu *fpu = ¤t->thread.fpu;
830
831 fpregs_activate(fpu);
832 fpu->last_cpu = smp_processor_id();
833 clear_thread_flag(TIF_NEED_FPU_LOAD);
834}
835
836/*
837 * x87 math exception handling:
838 */
839
840int fpu__exception_code(struct fpu *fpu, int trap_nr)
841{
842 int err;
843
844 if (trap_nr == X86_TRAP_MF) {
845 unsigned short cwd, swd;
846 /*
847 * (~cwd & swd) will mask out exceptions that are not set to unmasked
848 * status. 0x3f is the exception bits in these regs, 0x200 is the
849 * C1 reg you need in case of a stack fault, 0x040 is the stack
850 * fault bit. We should only be taking one exception at a time,
851 * so if this combination doesn't produce any single exception,
852 * then we have a bad program that isn't synchronizing its FPU usage
853 * and it will suffer the consequences since we won't be able to
854 * fully reproduce the context of the exception.
855 */
856 if (boot_cpu_has(X86_FEATURE_FXSR)) {
857 cwd = fpu->fpstate->regs.fxsave.cwd;
858 swd = fpu->fpstate->regs.fxsave.swd;
859 } else {
860 cwd = (unsigned short)fpu->fpstate->regs.fsave.cwd;
861 swd = (unsigned short)fpu->fpstate->regs.fsave.swd;
862 }
863
864 err = swd & ~cwd;
865 } else {
866 /*
867 * The SIMD FPU exceptions are handled a little differently, as there
868 * is only a single status/control register. Thus, to determine which
869 * unmasked exception was caught we must mask the exception mask bits
870 * at 0x1f80, and then use these to mask the exception bits at 0x3f.
871 */
872 unsigned short mxcsr = MXCSR_DEFAULT;
873
874 if (boot_cpu_has(X86_FEATURE_XMM))
875 mxcsr = fpu->fpstate->regs.fxsave.mxcsr;
876
877 err = ~(mxcsr >> 7) & mxcsr;
878 }
879
880 if (err & 0x001) { /* Invalid op */
881 /*
882 * swd & 0x240 == 0x040: Stack Underflow
883 * swd & 0x240 == 0x240: Stack Overflow
884 * User must clear the SF bit (0x40) if set
885 */
886 return FPE_FLTINV;
887 } else if (err & 0x004) { /* Divide by Zero */
888 return FPE_FLTDIV;
889 } else if (err & 0x008) { /* Overflow */
890 return FPE_FLTOVF;
891 } else if (err & 0x012) { /* Denormal, Underflow */
892 return FPE_FLTUND;
893 } else if (err & 0x020) { /* Precision */
894 return FPE_FLTRES;
895 }
896
897 /*
898 * If we're using IRQ 13, or supposedly even some trap
899 * X86_TRAP_MF implementations, it's possible
900 * we get a spurious trap, which is not an error.
901 */
902 return 0;
903}
904
905/*
906 * Initialize register state that may prevent from entering low-power idle.
907 * This function will be invoked from the cpuidle driver only when needed.
908 */
909noinstr void fpu_idle_fpregs(void)
910{
911 /* Note: AMX_TILE being enabled implies XGETBV1 support */
912 if (cpu_feature_enabled(X86_FEATURE_AMX_TILE) &&
913 (xfeatures_in_use() & XFEATURE_MASK_XTILE)) {
914 tile_release();
915 __this_cpu_write(fpu_fpregs_owner_ctx, NULL);
916 }
917}