1/*
  2 * Copyright 2018 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#ifndef __DAL_DCCG_H__
 27#define __DAL_DCCG_H__
 28
 29#include "dc_types.h"
 30#include "hw_shared.h"
 31
 32enum phyd32clk_clock_source {
 33	PHYD32CLKA,
 34	PHYD32CLKB,
 35	PHYD32CLKC,
 36	PHYD32CLKD,
 37	PHYD32CLKE,
 38	PHYD32CLKF,
 39	PHYD32CLKG,
 40};
 41
 42enum physymclk_clock_source {
 43	PHYSYMCLK_FORCE_SRC_SYMCLK,    // Select symclk as source of clock which is output to PHY through DCIO.
 44	PHYSYMCLK_FORCE_SRC_PHYD18CLK, // Select phyd18clk as the source of clock which is output to PHY through DCIO.
 45	PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO.
 46};
 47
 48enum streamclk_source {
 49	REFCLK,                   // Selects REFCLK as source for hdmistreamclk.
 50	DTBCLK0,                  // Selects DTBCLK0 as source for hdmistreamclk.
 51	DPREFCLK,                 // Selects DPREFCLK as source for hdmistreamclk
 52};
 53
 54enum dentist_dispclk_change_mode {
 55	DISPCLK_CHANGE_MODE_IMMEDIATE,
 56	DISPCLK_CHANGE_MODE_RAMPING,
 57};
 58
 59enum pixel_rate_div {
 60   PIXEL_RATE_DIV_BY_1 = 0,
 61   PIXEL_RATE_DIV_BY_2 = 1,
 62   PIXEL_RATE_DIV_BY_4 = 3,
 63   PIXEL_RATE_DIV_NA = 0xF
 64};
 65
 66struct dccg {
 67	struct dc_context *ctx;
 68	const struct dccg_funcs *funcs;
 69	int pipe_dppclk_khz[MAX_PIPES];
 70	int ref_dppclk;
 71	//int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */
 72	//int audio_dtbclk_khz;/* TODO needs to be removed */
 73	//int ref_dtbclk_khz;/* TODO needs to be removed */
 74};
 75
 76struct dtbclk_dto_params {
 77	const struct dc_crtc_timing *timing;
 78	int otg_inst;
 79	int pixclk_khz;
 80	int req_audio_dtbclk_khz;
 81	int num_odm_segments;
 82	int ref_dtbclk_khz;
 83	bool is_hdmi;
 84};
 85
 86struct dccg_funcs {
 87	void (*update_dpp_dto)(struct dccg *dccg,
 88			int dpp_inst,
 89			int req_dppclk);
 90	void (*get_dccg_ref_freq)(struct dccg *dccg,
 91			unsigned int xtalin_freq_inKhz,
 92			unsigned int *dccg_ref_freq_inKhz);
 93	void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,
 94			bool en);
 95	void (*otg_add_pixel)(struct dccg *dccg,
 96			uint32_t otg_inst);
 97	void (*otg_drop_pixel)(struct dccg *dccg,
 98			uint32_t otg_inst);
 99	void (*dccg_init)(struct dccg *dccg);
100
101	void (*set_dpstreamclk)(
102			struct dccg *dccg,
103			enum streamclk_source src,
104			int otg_inst,
105			int dp_hpo_inst);
106
107	void (*enable_symclk32_se)(
108			struct dccg *dccg,
109			int hpo_se_inst,
110			enum phyd32clk_clock_source phyd32clk);
111
112	void (*disable_symclk32_se)(
113			struct dccg *dccg,
114			int hpo_se_inst);
115
116	void (*enable_symclk32_le)(
117			struct dccg *dccg,
118			int hpo_le_inst,
119			enum phyd32clk_clock_source phyd32clk);
120
121	void (*disable_symclk32_le)(
122			struct dccg *dccg,
123			int hpo_le_inst);
124
125	void (*set_physymclk)(
126			struct dccg *dccg,
127			int phy_inst,
128			enum physymclk_clock_source clk_src,
129			bool force_enable);
130
131	void (*set_dtbclk_dto)(
132			struct dccg *dccg,
133			const struct dtbclk_dto_params *params);
134
135	void (*set_audio_dtbclk_dto)(
136			struct dccg *dccg,
137			const struct dtbclk_dto_params *params);
138
139	void (*set_dispclk_change_mode)(
140			struct dccg *dccg,
141			enum dentist_dispclk_change_mode change_mode);
142
143	void (*disable_dsc)(
144		struct dccg *dccg,
145		int inst);
146
147	void (*enable_dsc)(
148		struct dccg *dccg,
149		int inst);
150
151void (*set_pixel_rate_div)(
152        struct dccg *dccg,
153        uint32_t otg_inst,
154        enum pixel_rate_div k1,
155        enum pixel_rate_div k2);
156
157void (*set_valid_pixel_rate)(
158        struct dccg *dccg,
159	int ref_dtbclk_khz,
160        int otg_inst,
161        int pixclk_khz);
162
163};
164
165#endif //__DAL_DCCG_H__