1/*
  2 * Copyright 2018 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#ifndef __DAL_DCCG_H__
 27#define __DAL_DCCG_H__
 28
 29#include "dc_types.h"
 30#include "hw_shared.h"
 31
 32enum phyd32clk_clock_source {
 33	PHYD32CLKA,
 34	PHYD32CLKB,
 35	PHYD32CLKC,
 36	PHYD32CLKD,
 37	PHYD32CLKE,
 38	PHYD32CLKF,
 39	PHYD32CLKG,
 40};
 41
 42enum physymclk_clock_source {
 43	PHYSYMCLK_FORCE_SRC_SYMCLK,    // Select symclk as source of clock which is output to PHY through DCIO.
 44	PHYSYMCLK_FORCE_SRC_PHYD18CLK, // Select phyd18clk as the source of clock which is output to PHY through DCIO.
 45	PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO.
 46};
 47
 48enum hdmistreamclk_source {
 49	REFCLK,                   // Selects REFCLK as source for hdmistreamclk.
 50	DTBCLK0,                  // Selects DTBCLK0 as source for hdmistreamclk.
 51};
 52
 53enum dentist_dispclk_change_mode {
 54	DISPCLK_CHANGE_MODE_IMMEDIATE,
 55	DISPCLK_CHANGE_MODE_RAMPING,
 56};
 57
 58struct dccg {
 59	struct dc_context *ctx;
 60	const struct dccg_funcs *funcs;
 61	int pipe_dppclk_khz[MAX_PIPES];
 62	int ref_dppclk;
 63	int dtbclk_khz[MAX_PIPES];
 64	int audio_dtbclk_khz;
 65	int ref_dtbclk_khz;
 66};
 67
 68struct dccg_funcs {
 69	void (*update_dpp_dto)(struct dccg *dccg,
 70			int dpp_inst,
 71			int req_dppclk);
 72	void (*get_dccg_ref_freq)(struct dccg *dccg,
 73			unsigned int xtalin_freq_inKhz,
 74			unsigned int *dccg_ref_freq_inKhz);
 75	void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,
 76			bool en);
 77	void (*otg_add_pixel)(struct dccg *dccg,
 78			uint32_t otg_inst);
 79	void (*otg_drop_pixel)(struct dccg *dccg,
 80			uint32_t otg_inst);
 81	void (*dccg_init)(struct dccg *dccg);
 82
 83	void (*set_physymclk)(
 84			struct dccg *dccg,
 85			int phy_inst,
 86			enum physymclk_clock_source clk_src,
 87			bool force_enable);
 88
 89	void (*set_dtbclk_dto)(
 90			struct dccg *dccg,
 91			int dtbclk_inst,
 92			int req_dtbclk_khz,
 93			int num_odm_segments,
 94			const struct dc_crtc_timing *timing);
 95
 96	void (*set_audio_dtbclk_dto)(
 97			struct dccg *dccg,
 98			uint32_t req_audio_dtbclk_khz);
 99
100	void (*set_dispclk_change_mode)(
101			struct dccg *dccg,
102			enum dentist_dispclk_change_mode change_mode);
103};
104
105#endif //__DAL_DCCG_H__