Loading...
1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_DCCG_H__
27#define __DAL_DCCG_H__
28
29#include "dc_types.h"
30#include "hw_shared.h"
31
32enum phyd32clk_clock_source {
33 PHYD32CLKA,
34 PHYD32CLKB,
35 PHYD32CLKC,
36 PHYD32CLKD,
37 PHYD32CLKE,
38 PHYD32CLKF,
39 PHYD32CLKG,
40};
41
42enum physymclk_clock_source {
43 PHYSYMCLK_FORCE_SRC_SYMCLK, // Select symclk as source of clock which is output to PHY through DCIO.
44 PHYSYMCLK_FORCE_SRC_PHYD18CLK, // Select phyd18clk as the source of clock which is output to PHY through DCIO.
45 PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO.
46};
47
48enum streamclk_source {
49 REFCLK, // Selects REFCLK as source for hdmistreamclk.
50 DTBCLK0, // Selects DTBCLK0 as source for hdmistreamclk.
51 DPREFCLK, // Selects DPREFCLK as source for hdmistreamclk
52};
53
54enum dentist_dispclk_change_mode {
55 DISPCLK_CHANGE_MODE_IMMEDIATE,
56 DISPCLK_CHANGE_MODE_RAMPING,
57};
58
59struct dp_dto_params {
60 int otg_inst;
61 enum signal_type signal;
62 uint64_t pixclk_hz;
63 uint64_t refclk_hz;
64};
65
66enum pixel_rate_div {
67 PIXEL_RATE_DIV_BY_1 = 0,
68 PIXEL_RATE_DIV_BY_2 = 1,
69 PIXEL_RATE_DIV_BY_4 = 3,
70 PIXEL_RATE_DIV_NA = 0xF
71};
72
73struct dccg {
74 struct dc_context *ctx;
75 const struct dccg_funcs *funcs;
76 int pipe_dppclk_khz[MAX_PIPES];
77 int ref_dppclk;
78 bool dpp_clock_gated[MAX_PIPES];
79 //int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */
80 //int audio_dtbclk_khz;/* TODO needs to be removed */
81 //int ref_dtbclk_khz;/* TODO needs to be removed */
82};
83
84struct dtbclk_dto_params {
85 const struct dc_crtc_timing *timing;
86 int otg_inst;
87 int pixclk_khz;
88 int req_audio_dtbclk_khz;
89 int num_odm_segments;
90 int ref_dtbclk_khz;
91 bool is_hdmi;
92};
93
94struct dccg_funcs {
95 void (*update_dpp_dto)(struct dccg *dccg,
96 int dpp_inst,
97 int req_dppclk);
98 void (*get_dccg_ref_freq)(struct dccg *dccg,
99 unsigned int xtalin_freq_inKhz,
100 unsigned int *dccg_ref_freq_inKhz);
101 void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,
102 bool en);
103 void (*otg_add_pixel)(struct dccg *dccg,
104 uint32_t otg_inst);
105 void (*otg_drop_pixel)(struct dccg *dccg,
106 uint32_t otg_inst);
107 void (*dccg_init)(struct dccg *dccg);
108
109 void (*set_dpstreamclk)(
110 struct dccg *dccg,
111 enum streamclk_source src,
112 int otg_inst,
113 int dp_hpo_inst);
114
115 void (*enable_symclk32_se)(
116 struct dccg *dccg,
117 int hpo_se_inst,
118 enum phyd32clk_clock_source phyd32clk);
119
120 void (*disable_symclk32_se)(
121 struct dccg *dccg,
122 int hpo_se_inst);
123
124 void (*enable_symclk32_le)(
125 struct dccg *dccg,
126 int hpo_le_inst,
127 enum phyd32clk_clock_source phyd32clk);
128
129 void (*disable_symclk32_le)(
130 struct dccg *dccg,
131 int hpo_le_inst);
132
133 void (*set_symclk32_le_root_clock_gating)(
134 struct dccg *dccg,
135 int hpo_le_inst,
136 bool enable);
137
138 void (*set_physymclk)(
139 struct dccg *dccg,
140 int phy_inst,
141 enum physymclk_clock_source clk_src,
142 bool force_enable);
143
144 void (*set_physymclk_root_clock_gating)(
145 struct dccg *dccg,
146 int phy_inst,
147 bool enable);
148
149 void (*set_dtbclk_dto)(
150 struct dccg *dccg,
151 const struct dtbclk_dto_params *params);
152
153 void (*set_audio_dtbclk_dto)(
154 struct dccg *dccg,
155 const struct dtbclk_dto_params *params);
156
157 void (*set_dispclk_change_mode)(
158 struct dccg *dccg,
159 enum dentist_dispclk_change_mode change_mode);
160
161 void (*disable_dsc)(
162 struct dccg *dccg,
163 int inst);
164
165 void (*enable_dsc)(
166 struct dccg *dccg,
167 int inst);
168
169 void (*set_pixel_rate_div)(struct dccg *dccg,
170 uint32_t otg_inst,
171 enum pixel_rate_div k1,
172 enum pixel_rate_div k2);
173
174 void (*set_valid_pixel_rate)(
175 struct dccg *dccg,
176 int ref_dtbclk_khz,
177 int otg_inst,
178 int pixclk_khz);
179
180 void (*trigger_dio_fifo_resync)(
181 struct dccg *dccg);
182
183 void (*dpp_root_clock_control)(
184 struct dccg *dccg,
185 unsigned int dpp_inst,
186 bool clock_on);
187
188 void (*enable_symclk_se)(
189 struct dccg *dccg,
190 uint32_t stream_enc_inst,
191 uint32_t link_enc_inst);
192
193 void (*disable_symclk_se)(
194 struct dccg *dccg,
195 uint32_t stream_enc_inst,
196 uint32_t link_enc_inst);
197 void (*set_dp_dto)(
198 struct dccg *dccg,
199 const struct dp_dto_params *params);
200 void (*set_dtbclk_p_src)(
201 struct dccg *dccg,
202 enum streamclk_source src,
203 uint32_t otg_inst);
204 void (*set_dto_dscclk)(
205 struct dccg *dccg,
206 uint32_t dsc_inst);
207 void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst);
208};
209
210#endif //__DAL_DCCG_H__