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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4/include/ "skeleton.dtsi"
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/qcom,gcc-msm8960.h>
8#include <dt-bindings/mfd/qcom-rpm.h>
9#include <dt-bindings/soc/qcom,gsbi.h>
10
11/ {
12 model = "Qualcomm MSM8960";
13 compatible = "qcom,msm8960";
14 interrupt-parent = <&intc>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19 interrupts = <1 14 0x304>;
20
21 cpu@0 {
22 compatible = "qcom,krait";
23 enable-method = "qcom,kpss-acc-v1";
24 device_type = "cpu";
25 reg = <0>;
26 next-level-cache = <&L2>;
27 qcom,acc = <&acc0>;
28 qcom,saw = <&saw0>;
29 };
30
31 cpu@1 {
32 compatible = "qcom,krait";
33 enable-method = "qcom,kpss-acc-v1";
34 device_type = "cpu";
35 reg = <1>;
36 next-level-cache = <&L2>;
37 qcom,acc = <&acc1>;
38 qcom,saw = <&saw1>;
39 };
40
41 L2: l2-cache {
42 compatible = "cache";
43 cache-level = <2>;
44 };
45 };
46
47 cpu-pmu {
48 compatible = "qcom,krait-pmu";
49 interrupts = <1 10 0x304>;
50 qcom,no-pc-write;
51 };
52
53 clocks {
54 cxo_board {
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <19200000>;
58 clock-output-names = "cxo_board";
59 };
60
61 pxo_board {
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <27000000>;
65 clock-output-names = "pxo_board";
66 };
67
68 sleep_clk {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <32768>;
72 clock-output-names = "sleep_clk";
73 };
74 };
75
76 soc: soc {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80 compatible = "simple-bus";
81
82 intc: interrupt-controller@2000000 {
83 compatible = "qcom,msm-qgic2";
84 interrupt-controller;
85 #interrupt-cells = <3>;
86 reg = <0x02000000 0x1000>,
87 <0x02002000 0x1000>;
88 };
89
90 timer@200a000 {
91 compatible = "qcom,kpss-timer",
92 "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
93 interrupts = <1 1 0x301>,
94 <1 2 0x301>,
95 <1 3 0x301>;
96 reg = <0x0200a000 0x100>;
97 clock-frequency = <27000000>,
98 <32768>;
99 cpu-offset = <0x80000>;
100 };
101
102 msmgpio: pinctrl@800000 {
103 compatible = "qcom,msm8960-pinctrl";
104 gpio-controller;
105 #gpio-cells = <2>;
106 interrupts = <0 16 0x4>;
107 interrupt-controller;
108 #interrupt-cells = <2>;
109 reg = <0x800000 0x4000>;
110 };
111
112 gcc: clock-controller@900000 {
113 compatible = "qcom,gcc-msm8960";
114 #clock-cells = <1>;
115 #reset-cells = <1>;
116 reg = <0x900000 0x4000>;
117 };
118
119 lcc: clock-controller@28000000 {
120 compatible = "qcom,lcc-msm8960";
121 reg = <0x28000000 0x1000>;
122 #clock-cells = <1>;
123 #reset-cells = <1>;
124 };
125
126 clock-controller@4000000 {
127 compatible = "qcom,mmcc-msm8960";
128 reg = <0x4000000 0x1000>;
129 #clock-cells = <1>;
130 #reset-cells = <1>;
131 };
132
133 l2cc: clock-controller@2011000 {
134 compatible = "syscon";
135 reg = <0x2011000 0x1000>;
136 };
137
138 rpm@108000 {
139 compatible = "qcom,rpm-msm8960";
140 reg = <0x108000 0x1000>;
141 qcom,ipc = <&l2cc 0x8 2>;
142
143 interrupts = <0 19 0>, <0 21 0>, <0 22 0>;
144 interrupt-names = "ack", "err", "wakeup";
145
146 regulators {
147 compatible = "qcom,rpm-pm8921-regulators";
148 };
149 };
150
151 acc0: clock-controller@2088000 {
152 compatible = "qcom,kpss-acc-v1";
153 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
154 };
155
156 acc1: clock-controller@2098000 {
157 compatible = "qcom,kpss-acc-v1";
158 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
159 };
160
161 saw0: regulator@2089000 {
162 compatible = "qcom,saw2";
163 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
164 regulator;
165 };
166
167 saw1: regulator@2099000 {
168 compatible = "qcom,saw2";
169 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
170 regulator;
171 };
172
173 gsbi5: gsbi@16400000 {
174 compatible = "qcom,gsbi-v1.0.0";
175 cell-index = <5>;
176 reg = <0x16400000 0x100>;
177 clocks = <&gcc GSBI5_H_CLK>;
178 clock-names = "iface";
179 #address-cells = <1>;
180 #size-cells = <1>;
181 ranges;
182
183 syscon-tcsr = <&tcsr>;
184
185 gsbi5_serial: serial@16440000 {
186 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
187 reg = <0x16440000 0x1000>,
188 <0x16400000 0x1000>;
189 interrupts = <0 154 0x0>;
190 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
191 clock-names = "core", "iface";
192 status = "disabled";
193 };
194 };
195
196 qcom,ssbi@500000 {
197 compatible = "qcom,ssbi";
198 reg = <0x500000 0x1000>;
199 qcom,controller-type = "pmic-arbiter";
200
201 pmicintc: pmic@0 {
202 compatible = "qcom,pm8921";
203 interrupt-parent = <&msmgpio>;
204 interrupts = <104 8>;
205 #interrupt-cells = <2>;
206 interrupt-controller;
207 #address-cells = <1>;
208 #size-cells = <0>;
209
210 pwrkey@1c {
211 compatible = "qcom,pm8921-pwrkey";
212 reg = <0x1c>;
213 interrupt-parent = <&pmicintc>;
214 interrupts = <50 1>, <51 1>;
215 debounce = <15625>;
216 pull-up;
217 };
218
219 keypad@148 {
220 compatible = "qcom,pm8921-keypad";
221 reg = <0x148>;
222 interrupt-parent = <&pmicintc>;
223 interrupts = <74 1>, <75 1>;
224 debounce = <15>;
225 scan-delay = <32>;
226 row-hold = <91500>;
227 };
228
229 rtc@11d {
230 compatible = "qcom,pm8921-rtc";
231 interrupt-parent = <&pmicintc>;
232 interrupts = <39 1>;
233 reg = <0x11d>;
234 allow-set-time;
235 };
236 };
237 };
238
239 rng@1a500000 {
240 compatible = "qcom,prng";
241 reg = <0x1a500000 0x200>;
242 clocks = <&gcc PRNG_CLK>;
243 clock-names = "core";
244 };
245
246 /* Temporary fixed regulator */
247 vsdcc_fixed: vsdcc-regulator {
248 compatible = "regulator-fixed";
249 regulator-name = "SDCC Power";
250 regulator-min-microvolt = <2700000>;
251 regulator-max-microvolt = <2700000>;
252 regulator-always-on;
253 };
254
255 amba {
256 compatible = "simple-bus";
257 #address-cells = <1>;
258 #size-cells = <1>;
259 ranges;
260 sdcc1: sdcc@12400000 {
261 status = "disabled";
262 compatible = "arm,pl18x", "arm,primecell";
263 arm,primecell-periphid = <0x00051180>;
264 reg = <0x12400000 0x8000>;
265 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
266 interrupt-names = "cmd_irq";
267 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
268 clock-names = "mclk", "apb_pclk";
269 bus-width = <8>;
270 max-frequency = <96000000>;
271 non-removable;
272 cap-sd-highspeed;
273 cap-mmc-highspeed;
274 vmmc-supply = <&vsdcc_fixed>;
275 };
276
277 sdcc3: sdcc@12180000 {
278 compatible = "arm,pl18x", "arm,primecell";
279 arm,primecell-periphid = <0x00051180>;
280 status = "disabled";
281 reg = <0x12180000 0x8000>;
282 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
283 interrupt-names = "cmd_irq";
284 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
285 clock-names = "mclk", "apb_pclk";
286 bus-width = <4>;
287 cap-sd-highspeed;
288 cap-mmc-highspeed;
289 max-frequency = <192000000>;
290 no-1-8-v;
291 vmmc-supply = <&vsdcc_fixed>;
292 };
293 };
294
295 tcsr: syscon@1a400000 {
296 compatible = "qcom,tcsr-msm8960", "syscon";
297 reg = <0x1a400000 0x100>;
298 };
299
300 gsbi@16000000 {
301 compatible = "qcom,gsbi-v1.0.0";
302 cell-index = <1>;
303 reg = <0x16000000 0x100>;
304 clocks = <&gcc GSBI1_H_CLK>;
305 clock-names = "iface";
306 #address-cells = <1>;
307 #size-cells = <1>;
308 ranges;
309
310 spi@16080000 {
311 compatible = "qcom,spi-qup-v1.1.1";
312 #address-cells = <1>;
313 #size-cells = <0>;
314 reg = <0x16080000 0x1000>;
315 interrupts = <0 147 0>;
316 spi-max-frequency = <24000000>;
317 cs-gpios = <&msmgpio 8 0>;
318
319 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
320 clock-names = "core", "iface";
321 status = "disabled";
322 };
323 };
324 };
325};
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-msm8960.h>
6#include <dt-bindings/mfd/qcom-rpm.h>
7#include <dt-bindings/soc/qcom,gsbi.h>
8
9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12 model = "Qualcomm MSM8960";
13 compatible = "qcom,msm8960";
14 interrupt-parent = <&intc>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19 interrupts = <1 14 0x304>;
20
21 cpu@0 {
22 compatible = "qcom,krait";
23 enable-method = "qcom,kpss-acc-v1";
24 device_type = "cpu";
25 reg = <0>;
26 next-level-cache = <&L2>;
27 qcom,acc = <&acc0>;
28 qcom,saw = <&saw0>;
29 };
30
31 cpu@1 {
32 compatible = "qcom,krait";
33 enable-method = "qcom,kpss-acc-v1";
34 device_type = "cpu";
35 reg = <1>;
36 next-level-cache = <&L2>;
37 qcom,acc = <&acc1>;
38 qcom,saw = <&saw1>;
39 };
40
41 L2: l2-cache {
42 compatible = "cache";
43 cache-level = <2>;
44 };
45 };
46
47 memory {
48 device_type = "memory";
49 reg = <0x0 0x0>;
50 };
51
52 cpu-pmu {
53 compatible = "qcom,krait-pmu";
54 interrupts = <1 10 0x304>;
55 qcom,no-pc-write;
56 };
57
58 clocks {
59 cxo_board {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <19200000>;
63 clock-output-names = "cxo_board";
64 };
65
66 pxo_board {
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <27000000>;
70 clock-output-names = "pxo_board";
71 };
72
73 sleep_clk {
74 compatible = "fixed-clock";
75 #clock-cells = <0>;
76 clock-frequency = <32768>;
77 clock-output-names = "sleep_clk";
78 };
79 };
80
81 soc: soc {
82 #address-cells = <1>;
83 #size-cells = <1>;
84 ranges;
85 compatible = "simple-bus";
86
87 intc: interrupt-controller@2000000 {
88 compatible = "qcom,msm-qgic2";
89 interrupt-controller;
90 #interrupt-cells = <3>;
91 reg = <0x02000000 0x1000>,
92 <0x02002000 0x1000>;
93 };
94
95 timer@200a000 {
96 compatible = "qcom,kpss-timer",
97 "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
98 interrupts = <1 1 0x301>,
99 <1 2 0x301>,
100 <1 3 0x301>;
101 reg = <0x0200a000 0x100>;
102 clock-frequency = <27000000>,
103 <32768>;
104 cpu-offset = <0x80000>;
105 };
106
107 msmgpio: pinctrl@800000 {
108 compatible = "qcom,msm8960-pinctrl";
109 gpio-controller;
110 #gpio-cells = <2>;
111 interrupts = <0 16 0x4>;
112 interrupt-controller;
113 #interrupt-cells = <2>;
114 reg = <0x800000 0x4000>;
115 };
116
117 gcc: clock-controller@900000 {
118 compatible = "qcom,gcc-msm8960";
119 #clock-cells = <1>;
120 #reset-cells = <1>;
121 reg = <0x900000 0x4000>;
122 };
123
124 lcc: clock-controller@28000000 {
125 compatible = "qcom,lcc-msm8960";
126 reg = <0x28000000 0x1000>;
127 #clock-cells = <1>;
128 #reset-cells = <1>;
129 };
130
131 clock-controller@4000000 {
132 compatible = "qcom,mmcc-msm8960";
133 reg = <0x4000000 0x1000>;
134 #clock-cells = <1>;
135 #reset-cells = <1>;
136 };
137
138 l2cc: clock-controller@2011000 {
139 compatible = "syscon";
140 reg = <0x2011000 0x1000>;
141 };
142
143 rpm@108000 {
144 compatible = "qcom,rpm-msm8960";
145 reg = <0x108000 0x1000>;
146 qcom,ipc = <&l2cc 0x8 2>;
147
148 interrupts = <0 19 0>, <0 21 0>, <0 22 0>;
149 interrupt-names = "ack", "err", "wakeup";
150
151 regulators {
152 compatible = "qcom,rpm-pm8921-regulators";
153 };
154 };
155
156 acc0: clock-controller@2088000 {
157 compatible = "qcom,kpss-acc-v1";
158 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
159 };
160
161 acc1: clock-controller@2098000 {
162 compatible = "qcom,kpss-acc-v1";
163 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
164 };
165
166 saw0: regulator@2089000 {
167 compatible = "qcom,saw2";
168 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
169 regulator;
170 };
171
172 saw1: regulator@2099000 {
173 compatible = "qcom,saw2";
174 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
175 regulator;
176 };
177
178 gsbi5: gsbi@16400000 {
179 compatible = "qcom,gsbi-v1.0.0";
180 cell-index = <5>;
181 reg = <0x16400000 0x100>;
182 clocks = <&gcc GSBI5_H_CLK>;
183 clock-names = "iface";
184 #address-cells = <1>;
185 #size-cells = <1>;
186 ranges;
187
188 syscon-tcsr = <&tcsr>;
189
190 gsbi5_serial: serial@16440000 {
191 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
192 reg = <0x16440000 0x1000>,
193 <0x16400000 0x1000>;
194 interrupts = <0 154 0x0>;
195 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
196 clock-names = "core", "iface";
197 status = "disabled";
198 };
199 };
200
201 qcom,ssbi@500000 {
202 compatible = "qcom,ssbi";
203 reg = <0x500000 0x1000>;
204 qcom,controller-type = "pmic-arbiter";
205
206 pmicintc: pmic@0 {
207 compatible = "qcom,pm8921";
208 interrupt-parent = <&msmgpio>;
209 interrupts = <104 8>;
210 #interrupt-cells = <2>;
211 interrupt-controller;
212 #address-cells = <1>;
213 #size-cells = <0>;
214
215 pwrkey@1c {
216 compatible = "qcom,pm8921-pwrkey";
217 reg = <0x1c>;
218 interrupt-parent = <&pmicintc>;
219 interrupts = <50 1>, <51 1>;
220 debounce = <15625>;
221 pull-up;
222 };
223
224 keypad@148 {
225 compatible = "qcom,pm8921-keypad";
226 reg = <0x148>;
227 interrupt-parent = <&pmicintc>;
228 interrupts = <74 1>, <75 1>;
229 debounce = <15>;
230 scan-delay = <32>;
231 row-hold = <91500>;
232 };
233
234 rtc@11d {
235 compatible = "qcom,pm8921-rtc";
236 interrupt-parent = <&pmicintc>;
237 interrupts = <39 1>;
238 reg = <0x11d>;
239 allow-set-time;
240 };
241 };
242 };
243
244 rng@1a500000 {
245 compatible = "qcom,prng";
246 reg = <0x1a500000 0x200>;
247 clocks = <&gcc PRNG_CLK>;
248 clock-names = "core";
249 };
250
251 /* Temporary fixed regulator */
252 vsdcc_fixed: vsdcc-regulator {
253 compatible = "regulator-fixed";
254 regulator-name = "SDCC Power";
255 regulator-min-microvolt = <2700000>;
256 regulator-max-microvolt = <2700000>;
257 regulator-always-on;
258 };
259
260 amba {
261 compatible = "simple-bus";
262 #address-cells = <1>;
263 #size-cells = <1>;
264 ranges;
265 sdcc1: sdcc@12400000 {
266 status = "disabled";
267 compatible = "arm,pl18x", "arm,primecell";
268 arm,primecell-periphid = <0x00051180>;
269 reg = <0x12400000 0x8000>;
270 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
271 interrupt-names = "cmd_irq";
272 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
273 clock-names = "mclk", "apb_pclk";
274 bus-width = <8>;
275 max-frequency = <96000000>;
276 non-removable;
277 cap-sd-highspeed;
278 cap-mmc-highspeed;
279 vmmc-supply = <&vsdcc_fixed>;
280 };
281
282 sdcc3: sdcc@12180000 {
283 compatible = "arm,pl18x", "arm,primecell";
284 arm,primecell-periphid = <0x00051180>;
285 status = "disabled";
286 reg = <0x12180000 0x8000>;
287 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
288 interrupt-names = "cmd_irq";
289 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
290 clock-names = "mclk", "apb_pclk";
291 bus-width = <4>;
292 cap-sd-highspeed;
293 cap-mmc-highspeed;
294 max-frequency = <192000000>;
295 no-1-8-v;
296 vmmc-supply = <&vsdcc_fixed>;
297 };
298 };
299
300 tcsr: syscon@1a400000 {
301 compatible = "qcom,tcsr-msm8960", "syscon";
302 reg = <0x1a400000 0x100>;
303 };
304
305 gsbi@16000000 {
306 compatible = "qcom,gsbi-v1.0.0";
307 cell-index = <1>;
308 reg = <0x16000000 0x100>;
309 clocks = <&gcc GSBI1_H_CLK>;
310 clock-names = "iface";
311 #address-cells = <1>;
312 #size-cells = <1>;
313 ranges;
314
315 spi@16080000 {
316 compatible = "qcom,spi-qup-v1.1.1";
317 #address-cells = <1>;
318 #size-cells = <0>;
319 reg = <0x16080000 0x1000>;
320 interrupts = <0 147 0>;
321 spi-max-frequency = <24000000>;
322 cs-gpios = <&msmgpio 8 0>;
323
324 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
325 clock-names = "core", "iface";
326 status = "disabled";
327 };
328 };
329 };
330};