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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4/include/ "skeleton.dtsi"
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/qcom,gcc-msm8960.h>
8#include <dt-bindings/mfd/qcom-rpm.h>
9#include <dt-bindings/soc/qcom,gsbi.h>
10
11/ {
12 model = "Qualcomm MSM8960";
13 compatible = "qcom,msm8960";
14 interrupt-parent = <&intc>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19 interrupts = <1 14 0x304>;
20
21 cpu@0 {
22 compatible = "qcom,krait";
23 enable-method = "qcom,kpss-acc-v1";
24 device_type = "cpu";
25 reg = <0>;
26 next-level-cache = <&L2>;
27 qcom,acc = <&acc0>;
28 qcom,saw = <&saw0>;
29 };
30
31 cpu@1 {
32 compatible = "qcom,krait";
33 enable-method = "qcom,kpss-acc-v1";
34 device_type = "cpu";
35 reg = <1>;
36 next-level-cache = <&L2>;
37 qcom,acc = <&acc1>;
38 qcom,saw = <&saw1>;
39 };
40
41 L2: l2-cache {
42 compatible = "cache";
43 cache-level = <2>;
44 };
45 };
46
47 cpu-pmu {
48 compatible = "qcom,krait-pmu";
49 interrupts = <1 10 0x304>;
50 qcom,no-pc-write;
51 };
52
53 clocks {
54 cxo_board {
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <19200000>;
58 clock-output-names = "cxo_board";
59 };
60
61 pxo_board {
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <27000000>;
65 clock-output-names = "pxo_board";
66 };
67
68 sleep_clk {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <32768>;
72 clock-output-names = "sleep_clk";
73 };
74 };
75
76 soc: soc {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80 compatible = "simple-bus";
81
82 intc: interrupt-controller@2000000 {
83 compatible = "qcom,msm-qgic2";
84 interrupt-controller;
85 #interrupt-cells = <3>;
86 reg = <0x02000000 0x1000>,
87 <0x02002000 0x1000>;
88 };
89
90 timer@200a000 {
91 compatible = "qcom,kpss-timer",
92 "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
93 interrupts = <1 1 0x301>,
94 <1 2 0x301>,
95 <1 3 0x301>;
96 reg = <0x0200a000 0x100>;
97 clock-frequency = <27000000>,
98 <32768>;
99 cpu-offset = <0x80000>;
100 };
101
102 msmgpio: pinctrl@800000 {
103 compatible = "qcom,msm8960-pinctrl";
104 gpio-controller;
105 #gpio-cells = <2>;
106 interrupts = <0 16 0x4>;
107 interrupt-controller;
108 #interrupt-cells = <2>;
109 reg = <0x800000 0x4000>;
110 };
111
112 gcc: clock-controller@900000 {
113 compatible = "qcom,gcc-msm8960";
114 #clock-cells = <1>;
115 #reset-cells = <1>;
116 reg = <0x900000 0x4000>;
117 };
118
119 lcc: clock-controller@28000000 {
120 compatible = "qcom,lcc-msm8960";
121 reg = <0x28000000 0x1000>;
122 #clock-cells = <1>;
123 #reset-cells = <1>;
124 };
125
126 clock-controller@4000000 {
127 compatible = "qcom,mmcc-msm8960";
128 reg = <0x4000000 0x1000>;
129 #clock-cells = <1>;
130 #reset-cells = <1>;
131 };
132
133 l2cc: clock-controller@2011000 {
134 compatible = "syscon";
135 reg = <0x2011000 0x1000>;
136 };
137
138 rpm@108000 {
139 compatible = "qcom,rpm-msm8960";
140 reg = <0x108000 0x1000>;
141 qcom,ipc = <&l2cc 0x8 2>;
142
143 interrupts = <0 19 0>, <0 21 0>, <0 22 0>;
144 interrupt-names = "ack", "err", "wakeup";
145
146 regulators {
147 compatible = "qcom,rpm-pm8921-regulators";
148 };
149 };
150
151 acc0: clock-controller@2088000 {
152 compatible = "qcom,kpss-acc-v1";
153 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
154 };
155
156 acc1: clock-controller@2098000 {
157 compatible = "qcom,kpss-acc-v1";
158 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
159 };
160
161 saw0: regulator@2089000 {
162 compatible = "qcom,saw2";
163 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
164 regulator;
165 };
166
167 saw1: regulator@2099000 {
168 compatible = "qcom,saw2";
169 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
170 regulator;
171 };
172
173 gsbi5: gsbi@16400000 {
174 compatible = "qcom,gsbi-v1.0.0";
175 cell-index = <5>;
176 reg = <0x16400000 0x100>;
177 clocks = <&gcc GSBI5_H_CLK>;
178 clock-names = "iface";
179 #address-cells = <1>;
180 #size-cells = <1>;
181 ranges;
182
183 syscon-tcsr = <&tcsr>;
184
185 gsbi5_serial: serial@16440000 {
186 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
187 reg = <0x16440000 0x1000>,
188 <0x16400000 0x1000>;
189 interrupts = <0 154 0x0>;
190 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
191 clock-names = "core", "iface";
192 status = "disabled";
193 };
194 };
195
196 qcom,ssbi@500000 {
197 compatible = "qcom,ssbi";
198 reg = <0x500000 0x1000>;
199 qcom,controller-type = "pmic-arbiter";
200
201 pmicintc: pmic@0 {
202 compatible = "qcom,pm8921";
203 interrupt-parent = <&msmgpio>;
204 interrupts = <104 8>;
205 #interrupt-cells = <2>;
206 interrupt-controller;
207 #address-cells = <1>;
208 #size-cells = <0>;
209
210 pwrkey@1c {
211 compatible = "qcom,pm8921-pwrkey";
212 reg = <0x1c>;
213 interrupt-parent = <&pmicintc>;
214 interrupts = <50 1>, <51 1>;
215 debounce = <15625>;
216 pull-up;
217 };
218
219 keypad@148 {
220 compatible = "qcom,pm8921-keypad";
221 reg = <0x148>;
222 interrupt-parent = <&pmicintc>;
223 interrupts = <74 1>, <75 1>;
224 debounce = <15>;
225 scan-delay = <32>;
226 row-hold = <91500>;
227 };
228
229 rtc@11d {
230 compatible = "qcom,pm8921-rtc";
231 interrupt-parent = <&pmicintc>;
232 interrupts = <39 1>;
233 reg = <0x11d>;
234 allow-set-time;
235 };
236 };
237 };
238
239 rng@1a500000 {
240 compatible = "qcom,prng";
241 reg = <0x1a500000 0x200>;
242 clocks = <&gcc PRNG_CLK>;
243 clock-names = "core";
244 };
245
246 /* Temporary fixed regulator */
247 vsdcc_fixed: vsdcc-regulator {
248 compatible = "regulator-fixed";
249 regulator-name = "SDCC Power";
250 regulator-min-microvolt = <2700000>;
251 regulator-max-microvolt = <2700000>;
252 regulator-always-on;
253 };
254
255 amba {
256 compatible = "simple-bus";
257 #address-cells = <1>;
258 #size-cells = <1>;
259 ranges;
260 sdcc1: sdcc@12400000 {
261 status = "disabled";
262 compatible = "arm,pl18x", "arm,primecell";
263 arm,primecell-periphid = <0x00051180>;
264 reg = <0x12400000 0x8000>;
265 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
266 interrupt-names = "cmd_irq";
267 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
268 clock-names = "mclk", "apb_pclk";
269 bus-width = <8>;
270 max-frequency = <96000000>;
271 non-removable;
272 cap-sd-highspeed;
273 cap-mmc-highspeed;
274 vmmc-supply = <&vsdcc_fixed>;
275 };
276
277 sdcc3: sdcc@12180000 {
278 compatible = "arm,pl18x", "arm,primecell";
279 arm,primecell-periphid = <0x00051180>;
280 status = "disabled";
281 reg = <0x12180000 0x8000>;
282 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
283 interrupt-names = "cmd_irq";
284 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
285 clock-names = "mclk", "apb_pclk";
286 bus-width = <4>;
287 cap-sd-highspeed;
288 cap-mmc-highspeed;
289 max-frequency = <192000000>;
290 no-1-8-v;
291 vmmc-supply = <&vsdcc_fixed>;
292 };
293 };
294
295 tcsr: syscon@1a400000 {
296 compatible = "qcom,tcsr-msm8960", "syscon";
297 reg = <0x1a400000 0x100>;
298 };
299
300 gsbi@16000000 {
301 compatible = "qcom,gsbi-v1.0.0";
302 cell-index = <1>;
303 reg = <0x16000000 0x100>;
304 clocks = <&gcc GSBI1_H_CLK>;
305 clock-names = "iface";
306 #address-cells = <1>;
307 #size-cells = <1>;
308 ranges;
309
310 spi@16080000 {
311 compatible = "qcom,spi-qup-v1.1.1";
312 #address-cells = <1>;
313 #size-cells = <0>;
314 reg = <0x16080000 0x1000>;
315 interrupts = <0 147 0>;
316 spi-max-frequency = <24000000>;
317 cs-gpios = <&msmgpio 8 0>;
318
319 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
320 clock-names = "core", "iface";
321 status = "disabled";
322 };
323 };
324 };
325};
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-msm8960.h>
6#include <dt-bindings/clock/qcom,lcc-msm8960.h>
7#include <dt-bindings/mfd/qcom-rpm.h>
8#include <dt-bindings/soc/qcom,gsbi.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 model = "Qualcomm MSM8960";
14 compatible = "qcom,msm8960";
15 interrupt-parent = <&intc>;
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20 interrupts = <GIC_PPI 14 0x304>;
21
22 cpu@0 {
23 compatible = "qcom,krait";
24 enable-method = "qcom,kpss-acc-v1";
25 device_type = "cpu";
26 reg = <0>;
27 next-level-cache = <&L2>;
28 qcom,acc = <&acc0>;
29 qcom,saw = <&saw0>;
30 };
31
32 cpu@1 {
33 compatible = "qcom,krait";
34 enable-method = "qcom,kpss-acc-v1";
35 device_type = "cpu";
36 reg = <1>;
37 next-level-cache = <&L2>;
38 qcom,acc = <&acc1>;
39 qcom,saw = <&saw1>;
40 };
41
42 L2: l2-cache {
43 compatible = "cache";
44 cache-level = <2>;
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 reg = <0x0 0x0>;
51 };
52
53 cpu-pmu {
54 compatible = "qcom,krait-pmu";
55 interrupts = <GIC_PPI 10 0x304>;
56 qcom,no-pc-write;
57 };
58
59 clocks {
60 cxo_board: cxo_board {
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
63 clock-frequency = <19200000>;
64 clock-output-names = "cxo_board";
65 };
66
67 pxo_board: pxo_board {
68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <27000000>;
71 clock-output-names = "pxo_board";
72 };
73
74 sleep_clk {
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <32768>;
78 clock-output-names = "sleep_clk";
79 };
80 };
81
82 /* Temporary fixed regulator */
83 vsdcc_fixed: vsdcc-regulator {
84 compatible = "regulator-fixed";
85 regulator-name = "SDCC Power";
86 regulator-min-microvolt = <2700000>;
87 regulator-max-microvolt = <2700000>;
88 regulator-always-on;
89 };
90
91 soc: soc {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges;
95 compatible = "simple-bus";
96
97 intc: interrupt-controller@2000000 {
98 compatible = "qcom,msm-qgic2";
99 interrupt-controller;
100 #interrupt-cells = <3>;
101 reg = <0x02000000 0x1000>,
102 <0x02002000 0x1000>;
103 };
104
105 timer@200a000 {
106 compatible = "qcom,kpss-timer",
107 "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
108 interrupts = <GIC_PPI 1 0x301>,
109 <GIC_PPI 2 0x301>,
110 <GIC_PPI 3 0x301>;
111 reg = <0x0200a000 0x100>;
112 clock-frequency = <27000000>,
113 <32768>;
114 cpu-offset = <0x80000>;
115 };
116
117 msmgpio: pinctrl@800000 {
118 compatible = "qcom,msm8960-pinctrl";
119 gpio-controller;
120 gpio-ranges = <&msmgpio 0 0 152>;
121 #gpio-cells = <2>;
122 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
123 interrupt-controller;
124 #interrupt-cells = <2>;
125 reg = <0x800000 0x4000>;
126 };
127
128 gcc: clock-controller@900000 {
129 compatible = "qcom,gcc-msm8960";
130 #clock-cells = <1>;
131 #power-domain-cells = <1>;
132 #reset-cells = <1>;
133 reg = <0x900000 0x4000>;
134 clocks = <&cxo_board>,
135 <&pxo_board>,
136 <&lcc PLL4>;
137 clock-names = "cxo", "pxo", "pll4";
138 };
139
140 lcc: clock-controller@28000000 {
141 compatible = "qcom,lcc-msm8960";
142 reg = <0x28000000 0x1000>;
143 #clock-cells = <1>;
144 #reset-cells = <1>;
145 clocks = <&pxo_board>,
146 <&gcc PLL4_VOTE>,
147 <0>,
148 <0>, <0>,
149 <0>, <0>,
150 <0>;
151 clock-names = "pxo",
152 "pll4_vote",
153 "mi2s_codec_clk",
154 "codec_i2s_mic_codec_clk",
155 "spare_i2s_mic_codec_clk",
156 "codec_i2s_spkr_codec_clk",
157 "spare_i2s_spkr_codec_clk",
158 "pcm_codec_clk";
159 };
160
161 clock-controller@4000000 {
162 compatible = "qcom,mmcc-msm8960";
163 reg = <0x4000000 0x1000>;
164 #clock-cells = <1>;
165 #power-domain-cells = <1>;
166 #reset-cells = <1>;
167 clocks = <&pxo_board>,
168 <&gcc PLL3>,
169 <&gcc PLL8_VOTE>,
170 <0>,
171 <0>,
172 <0>,
173 <0>,
174 <0>;
175 clock-names = "pxo",
176 "pll3",
177 "pll8_vote",
178 "dsi1pll",
179 "dsi1pllbyte",
180 "dsi2pll",
181 "dsi2pllbyte",
182 "hdmipll";
183 };
184
185 l2cc: clock-controller@2011000 {
186 compatible = "qcom,kpss-gcc", "syscon";
187 reg = <0x2011000 0x1000>;
188 };
189
190 rpm: rpm@108000 {
191 compatible = "qcom,rpm-msm8960";
192 reg = <0x108000 0x1000>;
193 qcom,ipc = <&l2cc 0x8 2>;
194
195 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
196 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
197 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
198 interrupt-names = "ack", "err", "wakeup";
199
200 regulators {
201 compatible = "qcom,rpm-pm8921-regulators";
202 };
203 };
204
205 acc0: clock-controller@2088000 {
206 compatible = "qcom,kpss-acc-v1";
207 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
208 };
209
210 acc1: clock-controller@2098000 {
211 compatible = "qcom,kpss-acc-v1";
212 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
213 };
214
215 saw0: regulator@2089000 {
216 compatible = "qcom,saw2";
217 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
218 regulator;
219 };
220
221 saw1: regulator@2099000 {
222 compatible = "qcom,saw2";
223 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
224 regulator;
225 };
226
227 gsbi5: gsbi@16400000 {
228 compatible = "qcom,gsbi-v1.0.0";
229 cell-index = <5>;
230 reg = <0x16400000 0x100>;
231 clocks = <&gcc GSBI5_H_CLK>;
232 clock-names = "iface";
233 #address-cells = <1>;
234 #size-cells = <1>;
235 ranges;
236
237 syscon-tcsr = <&tcsr>;
238
239 gsbi5_serial: serial@16440000 {
240 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
241 reg = <0x16440000 0x1000>,
242 <0x16400000 0x1000>;
243 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
245 clock-names = "core", "iface";
246 status = "disabled";
247 };
248 };
249
250 ssbi@500000 {
251 compatible = "qcom,ssbi";
252 reg = <0x500000 0x1000>;
253 qcom,controller-type = "pmic-arbiter";
254
255 pmicintc: pmic {
256 compatible = "qcom,pm8921";
257 interrupt-parent = <&msmgpio>;
258 interrupts = <104 IRQ_TYPE_LEVEL_LOW>;
259 #interrupt-cells = <2>;
260 interrupt-controller;
261 #address-cells = <1>;
262 #size-cells = <0>;
263
264 pwrkey@1c {
265 compatible = "qcom,pm8921-pwrkey";
266 reg = <0x1c>;
267 interrupt-parent = <&pmicintc>;
268 interrupts = <50 IRQ_TYPE_EDGE_RISING>,
269 <51 IRQ_TYPE_EDGE_RISING>;
270 debounce = <15625>;
271 pull-up;
272 };
273
274 keypad@148 {
275 compatible = "qcom,pm8921-keypad";
276 reg = <0x148>;
277 interrupt-parent = <&pmicintc>;
278 interrupts = <74 IRQ_TYPE_EDGE_RISING>,
279 <75 IRQ_TYPE_EDGE_RISING>;
280 debounce = <15>;
281 scan-delay = <32>;
282 row-hold = <91500>;
283 };
284
285 rtc@11d {
286 compatible = "qcom,pm8921-rtc";
287 interrupt-parent = <&pmicintc>;
288 interrupts = <39 IRQ_TYPE_EDGE_RISING>;
289 reg = <0x11d>;
290 allow-set-time;
291 };
292 };
293 };
294
295 rng@1a500000 {
296 compatible = "qcom,prng";
297 reg = <0x1a500000 0x200>;
298 clocks = <&gcc PRNG_CLK>;
299 clock-names = "core";
300 };
301
302 sdcc3: mmc@12180000 {
303 compatible = "arm,pl18x", "arm,primecell";
304 arm,primecell-periphid = <0x00051180>;
305 status = "disabled";
306 reg = <0x12180000 0x8000>;
307 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
309 clock-names = "mclk", "apb_pclk";
310 bus-width = <4>;
311 cap-sd-highspeed;
312 cap-mmc-highspeed;
313 max-frequency = <192000000>;
314 no-1-8-v;
315 vmmc-supply = <&vsdcc_fixed>;
316 };
317
318 sdcc1: mmc@12400000 {
319 status = "disabled";
320 compatible = "arm,pl18x", "arm,primecell";
321 arm,primecell-periphid = <0x00051180>;
322 reg = <0x12400000 0x8000>;
323 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
325 clock-names = "mclk", "apb_pclk";
326 bus-width = <8>;
327 max-frequency = <96000000>;
328 non-removable;
329 cap-sd-highspeed;
330 cap-mmc-highspeed;
331 vmmc-supply = <&vsdcc_fixed>;
332 };
333
334 tcsr: syscon@1a400000 {
335 compatible = "qcom,tcsr-msm8960", "syscon";
336 reg = <0x1a400000 0x100>;
337 };
338
339 gsbi1: gsbi@16000000 {
340 compatible = "qcom,gsbi-v1.0.0";
341 cell-index = <1>;
342 reg = <0x16000000 0x100>;
343 clocks = <&gcc GSBI1_H_CLK>;
344 clock-names = "iface";
345 #address-cells = <1>;
346 #size-cells = <1>;
347 ranges;
348
349 gsbi1_spi: spi@16080000 {
350 compatible = "qcom,spi-qup-v1.1.1";
351 #address-cells = <1>;
352 #size-cells = <0>;
353 reg = <0x16080000 0x1000>;
354 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
355 spi-max-frequency = <24000000>;
356 cs-gpios = <&msmgpio 8 0>;
357
358 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
359 clock-names = "core", "iface";
360 status = "disabled";
361 };
362 };
363 };
364};