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1/*
2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
4 *
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
7 *
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
10 *
11 * Common pmac/prep/chrp pci routines. -- Cort
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/bootmem.h>
24#include <linux/mm.h>
25#include <linux/shmem_fs.h>
26#include <linux/list.h>
27#include <linux/syscalls.h>
28#include <linux/irq.h>
29#include <linux/vmalloc.h>
30#include <linux/slab.h>
31#include <linux/of.h>
32#include <linux/of_address.h>
33#include <linux/of_irq.h>
34#include <linux/of_pci.h>
35#include <linux/export.h>
36
37#include <asm/processor.h>
38#include <linux/io.h>
39#include <asm/pci-bridge.h>
40#include <asm/byteorder.h>
41
42static DEFINE_SPINLOCK(hose_spinlock);
43LIST_HEAD(hose_list);
44
45/* XXX kill that some day ... */
46static int global_phb_number; /* Global phb counter */
47
48/* ISA Memory physical address */
49resource_size_t isa_mem_base;
50
51unsigned long isa_io_base;
52EXPORT_SYMBOL(isa_io_base);
53
54static int pci_bus_count;
55
56struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
57{
58 struct pci_controller *phb;
59
60 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
61 if (!phb)
62 return NULL;
63 spin_lock(&hose_spinlock);
64 phb->global_number = global_phb_number++;
65 list_add_tail(&phb->list_node, &hose_list);
66 spin_unlock(&hose_spinlock);
67 phb->dn = dev;
68 phb->is_dynamic = mem_init_done;
69 return phb;
70}
71
72void pcibios_free_controller(struct pci_controller *phb)
73{
74 spin_lock(&hose_spinlock);
75 list_del(&phb->list_node);
76 spin_unlock(&hose_spinlock);
77
78 if (phb->is_dynamic)
79 kfree(phb);
80}
81
82static resource_size_t pcibios_io_size(const struct pci_controller *hose)
83{
84 return resource_size(&hose->io_resource);
85}
86
87int pcibios_vaddr_is_ioport(void __iomem *address)
88{
89 int ret = 0;
90 struct pci_controller *hose;
91 resource_size_t size;
92
93 spin_lock(&hose_spinlock);
94 list_for_each_entry(hose, &hose_list, list_node) {
95 size = pcibios_io_size(hose);
96 if (address >= hose->io_base_virt &&
97 address < (hose->io_base_virt + size)) {
98 ret = 1;
99 break;
100 }
101 }
102 spin_unlock(&hose_spinlock);
103 return ret;
104}
105
106unsigned long pci_address_to_pio(phys_addr_t address)
107{
108 struct pci_controller *hose;
109 resource_size_t size;
110 unsigned long ret = ~0;
111
112 spin_lock(&hose_spinlock);
113 list_for_each_entry(hose, &hose_list, list_node) {
114 size = pcibios_io_size(hose);
115 if (address >= hose->io_base_phys &&
116 address < (hose->io_base_phys + size)) {
117 unsigned long base =
118 (unsigned long)hose->io_base_virt - _IO_BASE;
119 ret = base + (address - hose->io_base_phys);
120 break;
121 }
122 }
123 spin_unlock(&hose_spinlock);
124
125 return ret;
126}
127EXPORT_SYMBOL_GPL(pci_address_to_pio);
128
129/* This routine is meant to be used early during boot, when the
130 * PCI bus numbers have not yet been assigned, and you need to
131 * issue PCI config cycles to an OF device.
132 * It could also be used to "fix" RTAS config cycles if you want
133 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
134 * config cycles.
135 */
136struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
137{
138 while (node) {
139 struct pci_controller *hose, *tmp;
140 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
141 if (hose->dn == node)
142 return hose;
143 node = node->parent;
144 }
145 return NULL;
146}
147
148void pcibios_set_master(struct pci_dev *dev)
149{
150 /* No special bus mastering setup handling */
151}
152
153/*
154 * Platform support for /proc/bus/pci/X/Y mmap()s.
155 */
156
157int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
158{
159 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
160 resource_size_t ioaddr = pci_resource_start(pdev, bar);
161
162 if (!hose)
163 return -EINVAL; /* should never happen */
164
165 /* Convert to an offset within this PCI controller */
166 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
167
168 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
169 return 0;
170}
171
172/*
173 * This one is used by /dev/mem and fbdev who have no clue about the
174 * PCI device, it tries to find the PCI device first and calls the
175 * above routine
176 */
177pgprot_t pci_phys_mem_access_prot(struct file *file,
178 unsigned long pfn,
179 unsigned long size,
180 pgprot_t prot)
181{
182 struct pci_dev *pdev = NULL;
183 struct resource *found = NULL;
184 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
185 int i;
186
187 if (page_is_ram(pfn))
188 return prot;
189
190 prot = pgprot_noncached(prot);
191 for_each_pci_dev(pdev) {
192 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
193 struct resource *rp = &pdev->resource[i];
194 int flags = rp->flags;
195
196 /* Active and same type? */
197 if ((flags & IORESOURCE_MEM) == 0)
198 continue;
199 /* In the range of this resource? */
200 if (offset < (rp->start & PAGE_MASK) ||
201 offset > rp->end)
202 continue;
203 found = rp;
204 break;
205 }
206 if (found)
207 break;
208 }
209 if (found) {
210 if (found->flags & IORESOURCE_PREFETCH)
211 prot = pgprot_noncached_wc(prot);
212 pci_dev_put(pdev);
213 }
214
215 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
216 (unsigned long long)offset, pgprot_val(prot));
217
218 return prot;
219}
220
221/* This provides legacy IO read access on a bus */
222int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
223{
224 unsigned long offset;
225 struct pci_controller *hose = pci_bus_to_host(bus);
226 struct resource *rp = &hose->io_resource;
227 void __iomem *addr;
228
229 /* Check if port can be supported by that bus. We only check
230 * the ranges of the PHB though, not the bus itself as the rules
231 * for forwarding legacy cycles down bridges are not our problem
232 * here. So if the host bridge supports it, we do it.
233 */
234 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
235 offset += port;
236
237 if (!(rp->flags & IORESOURCE_IO))
238 return -ENXIO;
239 if (offset < rp->start || (offset + size) > rp->end)
240 return -ENXIO;
241 addr = hose->io_base_virt + port;
242
243 switch (size) {
244 case 1:
245 *((u8 *)val) = in_8(addr);
246 return 1;
247 case 2:
248 if (port & 1)
249 return -EINVAL;
250 *((u16 *)val) = in_le16(addr);
251 return 2;
252 case 4:
253 if (port & 3)
254 return -EINVAL;
255 *((u32 *)val) = in_le32(addr);
256 return 4;
257 }
258 return -EINVAL;
259}
260
261/* This provides legacy IO write access on a bus */
262int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
263{
264 unsigned long offset;
265 struct pci_controller *hose = pci_bus_to_host(bus);
266 struct resource *rp = &hose->io_resource;
267 void __iomem *addr;
268
269 /* Check if port can be supported by that bus. We only check
270 * the ranges of the PHB though, not the bus itself as the rules
271 * for forwarding legacy cycles down bridges are not our problem
272 * here. So if the host bridge supports it, we do it.
273 */
274 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
275 offset += port;
276
277 if (!(rp->flags & IORESOURCE_IO))
278 return -ENXIO;
279 if (offset < rp->start || (offset + size) > rp->end)
280 return -ENXIO;
281 addr = hose->io_base_virt + port;
282
283 /* WARNING: The generic code is idiotic. It gets passed a pointer
284 * to what can be a 1, 2 or 4 byte quantity and always reads that
285 * as a u32, which means that we have to correct the location of
286 * the data read within those 32 bits for size 1 and 2
287 */
288 switch (size) {
289 case 1:
290 out_8(addr, val >> 24);
291 return 1;
292 case 2:
293 if (port & 1)
294 return -EINVAL;
295 out_le16(addr, val >> 16);
296 return 2;
297 case 4:
298 if (port & 3)
299 return -EINVAL;
300 out_le32(addr, val);
301 return 4;
302 }
303 return -EINVAL;
304}
305
306/* This provides legacy IO or memory mmap access on a bus */
307int pci_mmap_legacy_page_range(struct pci_bus *bus,
308 struct vm_area_struct *vma,
309 enum pci_mmap_state mmap_state)
310{
311 struct pci_controller *hose = pci_bus_to_host(bus);
312 resource_size_t offset =
313 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
314 resource_size_t size = vma->vm_end - vma->vm_start;
315 struct resource *rp;
316
317 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
318 pci_domain_nr(bus), bus->number,
319 mmap_state == pci_mmap_mem ? "MEM" : "IO",
320 (unsigned long long)offset,
321 (unsigned long long)(offset + size - 1));
322
323 if (mmap_state == pci_mmap_mem) {
324 /* Hack alert !
325 *
326 * Because X is lame and can fail starting if it gets an error
327 * trying to mmap legacy_mem (instead of just moving on without
328 * legacy memory access) we fake it here by giving it anonymous
329 * memory, effectively behaving just like /dev/zero
330 */
331 if ((offset + size) > hose->isa_mem_size) {
332#ifdef CONFIG_MMU
333 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
334 current->comm, current->pid);
335 pr_debug("legacy memory for 0%04x:%02x\n",
336 pci_domain_nr(bus), bus->number);
337#endif
338 if (vma->vm_flags & VM_SHARED)
339 return shmem_zero_setup(vma);
340 return 0;
341 }
342 offset += hose->isa_mem_phys;
343 } else {
344 unsigned long io_offset = (unsigned long)hose->io_base_virt -
345 _IO_BASE;
346 unsigned long roffset = offset + io_offset;
347 rp = &hose->io_resource;
348 if (!(rp->flags & IORESOURCE_IO))
349 return -ENXIO;
350 if (roffset < rp->start || (roffset + size) > rp->end)
351 return -ENXIO;
352 offset += hose->io_base_phys;
353 }
354 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
355
356 vma->vm_pgoff = offset >> PAGE_SHIFT;
357 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
358 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
359 vma->vm_end - vma->vm_start,
360 vma->vm_page_prot);
361}
362
363void pci_resource_to_user(const struct pci_dev *dev, int bar,
364 const struct resource *rsrc,
365 resource_size_t *start, resource_size_t *end)
366{
367 struct pci_bus_region region;
368
369 if (rsrc->flags & IORESOURCE_IO) {
370 pcibios_resource_to_bus(dev->bus, ®ion,
371 (struct resource *) rsrc);
372 *start = region.start;
373 *end = region.end;
374 return;
375 }
376
377 /* We pass a CPU physical address to userland for MMIO instead of a
378 * BAR value because X is lame and expects to be able to use that
379 * to pass to /dev/mem!
380 *
381 * That means we may have 64-bit values where some apps only expect
382 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
383 */
384 *start = rsrc->start;
385 *end = rsrc->end;
386}
387
388/**
389 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
390 * @hose: newly allocated pci_controller to be setup
391 * @dev: device node of the host bridge
392 * @primary: set if primary bus (32 bits only, soon to be deprecated)
393 *
394 * This function will parse the "ranges" property of a PCI host bridge device
395 * node and setup the resource mapping of a pci controller based on its
396 * content.
397 *
398 * Life would be boring if it wasn't for a few issues that we have to deal
399 * with here:
400 *
401 * - We can only cope with one IO space range and up to 3 Memory space
402 * ranges. However, some machines (thanks Apple !) tend to split their
403 * space into lots of small contiguous ranges. So we have to coalesce.
404 *
405 * - We can only cope with all memory ranges having the same offset
406 * between CPU addresses and PCI addresses. Unfortunately, some bridges
407 * are setup for a large 1:1 mapping along with a small "window" which
408 * maps PCI address 0 to some arbitrary high address of the CPU space in
409 * order to give access to the ISA memory hole.
410 * The way out of here that I've chosen for now is to always set the
411 * offset based on the first resource found, then override it if we
412 * have a different offset and the previous was set by an ISA hole.
413 *
414 * - Some busses have IO space not starting at 0, which causes trouble with
415 * the way we do our IO resource renumbering. The code somewhat deals with
416 * it for 64 bits but I would expect problems on 32 bits.
417 *
418 * - Some 32 bits platforms such as 4xx can have physical space larger than
419 * 32 bits so we need to use 64 bits values for the parsing
420 */
421void pci_process_bridge_OF_ranges(struct pci_controller *hose,
422 struct device_node *dev, int primary)
423{
424 int memno = 0, isa_hole = -1;
425 unsigned long long isa_mb = 0;
426 struct resource *res;
427 struct of_pci_range range;
428 struct of_pci_range_parser parser;
429
430 pr_info("PCI host bridge %pOF %s ranges:\n",
431 dev, primary ? "(primary)" : "");
432
433 /* Check for ranges property */
434 if (of_pci_range_parser_init(&parser, dev))
435 return;
436
437 pr_debug("Parsing ranges property...\n");
438 for_each_of_pci_range(&parser, &range) {
439 /* Read next ranges element */
440 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
441 range.pci_space, range.pci_addr);
442 pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
443 range.cpu_addr, range.size);
444
445 /* If we failed translation or got a zero-sized region
446 * (some FW try to feed us with non sensical zero sized regions
447 * such as power3 which look like some kind of attempt
448 * at exposing the VGA memory hole)
449 */
450 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
451 continue;
452
453 /* Act based on address space type */
454 res = NULL;
455 switch (range.flags & IORESOURCE_TYPE_BITS) {
456 case IORESOURCE_IO:
457 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
458 range.cpu_addr, range.cpu_addr + range.size - 1,
459 range.pci_addr);
460
461 /* We support only one IO range */
462 if (hose->pci_io_size) {
463 pr_info(" \\--> Skipped (too many) !\n");
464 continue;
465 }
466 /* On 32 bits, limit I/O space to 16MB */
467 if (range.size > 0x01000000)
468 range.size = 0x01000000;
469
470 /* 32 bits needs to map IOs here */
471 hose->io_base_virt = ioremap(range.cpu_addr,
472 range.size);
473
474 /* Expect trouble if pci_addr is not 0 */
475 if (primary)
476 isa_io_base =
477 (unsigned long)hose->io_base_virt;
478 /* pci_io_size and io_base_phys always represent IO
479 * space starting at 0 so we factor in pci_addr
480 */
481 hose->pci_io_size = range.pci_addr + range.size;
482 hose->io_base_phys = range.cpu_addr - range.pci_addr;
483
484 /* Build resource */
485 res = &hose->io_resource;
486 range.cpu_addr = range.pci_addr;
487
488 break;
489 case IORESOURCE_MEM:
490 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
491 range.cpu_addr, range.cpu_addr + range.size - 1,
492 range.pci_addr,
493 (range.pci_space & 0x40000000) ?
494 "Prefetch" : "");
495
496 /* We support only 3 memory ranges */
497 if (memno >= 3) {
498 pr_info(" \\--> Skipped (too many) !\n");
499 continue;
500 }
501 /* Handles ISA memory hole space here */
502 if (range.pci_addr == 0) {
503 isa_mb = range.cpu_addr;
504 isa_hole = memno;
505 if (primary || isa_mem_base == 0)
506 isa_mem_base = range.cpu_addr;
507 hose->isa_mem_phys = range.cpu_addr;
508 hose->isa_mem_size = range.size;
509 }
510
511 /* We get the PCI/Mem offset from the first range or
512 * the, current one if the offset came from an ISA
513 * hole. If they don't match, bugger.
514 */
515 if (memno == 0 ||
516 (isa_hole >= 0 && range.pci_addr != 0 &&
517 hose->pci_mem_offset == isa_mb))
518 hose->pci_mem_offset = range.cpu_addr -
519 range.pci_addr;
520 else if (range.pci_addr != 0 &&
521 hose->pci_mem_offset != range.cpu_addr -
522 range.pci_addr) {
523 pr_info(" \\--> Skipped (offset mismatch) !\n");
524 continue;
525 }
526
527 /* Build resource */
528 res = &hose->mem_resources[memno++];
529 break;
530 }
531 if (res != NULL) {
532 res->name = dev->full_name;
533 res->flags = range.flags;
534 res->start = range.cpu_addr;
535 res->end = range.cpu_addr + range.size - 1;
536 res->parent = res->child = res->sibling = NULL;
537 }
538 }
539
540 /* If there's an ISA hole and the pci_mem_offset is -not- matching
541 * the ISA hole offset, then we need to remove the ISA hole from
542 * the resource list for that brige
543 */
544 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
545 unsigned int next = isa_hole + 1;
546 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
547 if (next < memno)
548 memmove(&hose->mem_resources[isa_hole],
549 &hose->mem_resources[next],
550 sizeof(struct resource) * (memno - next));
551 hose->mem_resources[--memno].flags = 0;
552 }
553}
554
555/* Display the domain number in /proc */
556int pci_proc_domain(struct pci_bus *bus)
557{
558 return pci_domain_nr(bus);
559}
560
561/* This header fixup will do the resource fixup for all devices as they are
562 * probed, but not for bridge ranges
563 */
564static void pcibios_fixup_resources(struct pci_dev *dev)
565{
566 struct pci_controller *hose = pci_bus_to_host(dev->bus);
567 int i;
568
569 if (!hose) {
570 pr_err("No host bridge for PCI dev %s !\n",
571 pci_name(dev));
572 return;
573 }
574 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
575 struct resource *res = dev->resource + i;
576 if (!res->flags)
577 continue;
578 if (res->start == 0) {
579 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
580 pci_name(dev), i,
581 (unsigned long long)res->start,
582 (unsigned long long)res->end,
583 (unsigned int)res->flags);
584 pr_debug("is unassigned\n");
585 res->end -= res->start;
586 res->start = 0;
587 res->flags |= IORESOURCE_UNSET;
588 continue;
589 }
590
591 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
592 pci_name(dev), i,
593 (unsigned long long)res->start,
594 (unsigned long long)res->end,
595 (unsigned int)res->flags);
596 }
597}
598DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
599
600/*
601 * We need to avoid collisions with `mirrored' VGA ports
602 * and other strange ISA hardware, so we always want the
603 * addresses to be allocated in the 0x000-0x0ff region
604 * modulo 0x400.
605 *
606 * Why? Because some silly external IO cards only decode
607 * the low 10 bits of the IO address. The 0x00-0xff region
608 * is reserved for motherboard devices that decode all 16
609 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
610 * but we want to try to avoid allocating at 0x2900-0x2bff
611 * which might have be mirrored at 0x0100-0x03ff..
612 */
613int pcibios_add_device(struct pci_dev *dev)
614{
615 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
616
617 return 0;
618}
619EXPORT_SYMBOL(pcibios_add_device);
620
621/*
622 * Reparent resource children of pr that conflict with res
623 * under res, and make res replace those children.
624 */
625static int __init reparent_resources(struct resource *parent,
626 struct resource *res)
627{
628 struct resource *p, **pp;
629 struct resource **firstpp = NULL;
630
631 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
632 if (p->end < res->start)
633 continue;
634 if (res->end < p->start)
635 break;
636 if (p->start < res->start || p->end > res->end)
637 return -1; /* not completely contained */
638 if (firstpp == NULL)
639 firstpp = pp;
640 }
641 if (firstpp == NULL)
642 return -1; /* didn't find any conflicting entries? */
643 res->parent = parent;
644 res->child = *firstpp;
645 res->sibling = *pp;
646 *firstpp = res;
647 *pp = NULL;
648 for (p = res->child; p != NULL; p = p->sibling) {
649 p->parent = res;
650 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
651 p->name,
652 (unsigned long long)p->start,
653 (unsigned long long)p->end, res->name);
654 }
655 return 0;
656}
657
658/*
659 * Handle resources of PCI devices. If the world were perfect, we could
660 * just allocate all the resource regions and do nothing more. It isn't.
661 * On the other hand, we cannot just re-allocate all devices, as it would
662 * require us to know lots of host bridge internals. So we attempt to
663 * keep as much of the original configuration as possible, but tweak it
664 * when it's found to be wrong.
665 *
666 * Known BIOS problems we have to work around:
667 * - I/O or memory regions not configured
668 * - regions configured, but not enabled in the command register
669 * - bogus I/O addresses above 64K used
670 * - expansion ROMs left enabled (this may sound harmless, but given
671 * the fact the PCI specs explicitly allow address decoders to be
672 * shared between expansion ROMs and other resource regions, it's
673 * at least dangerous)
674 *
675 * Our solution:
676 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
677 * This gives us fixed barriers on where we can allocate.
678 * (2) Allocate resources for all enabled devices. If there is
679 * a collision, just mark the resource as unallocated. Also
680 * disable expansion ROMs during this step.
681 * (3) Try to allocate resources for disabled devices. If the
682 * resources were assigned correctly, everything goes well,
683 * if they weren't, they won't disturb allocation of other
684 * resources.
685 * (4) Assign new addresses to resources which were either
686 * not configured at all or misconfigured. If explicitly
687 * requested by the user, configure expansion ROM address
688 * as well.
689 */
690
691static void pcibios_allocate_bus_resources(struct pci_bus *bus)
692{
693 struct pci_bus *b;
694 int i;
695 struct resource *res, *pr;
696
697 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
698 pci_domain_nr(bus), bus->number);
699
700 pci_bus_for_each_resource(bus, res, i) {
701 if (!res || !res->flags
702 || res->start > res->end || res->parent)
703 continue;
704 if (bus->parent == NULL)
705 pr = (res->flags & IORESOURCE_IO) ?
706 &ioport_resource : &iomem_resource;
707 else {
708 /* Don't bother with non-root busses when
709 * re-assigning all resources. We clear the
710 * resource flags as if they were colliding
711 * and as such ensure proper re-allocation
712 * later.
713 */
714 pr = pci_find_parent_resource(bus->self, res);
715 if (pr == res) {
716 /* this happens when the generic PCI
717 * code (wrongly) decides that this
718 * bridge is transparent -- paulus
719 */
720 continue;
721 }
722 }
723
724 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
725 bus->self ? pci_name(bus->self) : "PHB",
726 bus->number, i,
727 (unsigned long long)res->start,
728 (unsigned long long)res->end);
729 pr_debug("[0x%x], parent %p (%s)\n",
730 (unsigned int)res->flags,
731 pr, (pr && pr->name) ? pr->name : "nil");
732
733 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
734 struct pci_dev *dev = bus->self;
735
736 if (request_resource(pr, res) == 0)
737 continue;
738 /*
739 * Must be a conflict with an existing entry.
740 * Move that entry (or entries) under the
741 * bridge resource and try again.
742 */
743 if (reparent_resources(pr, res) == 0)
744 continue;
745
746 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
747 pci_claim_bridge_resource(dev,
748 i + PCI_BRIDGE_RESOURCES) == 0)
749 continue;
750
751 }
752 pr_warn("PCI: Cannot allocate resource region ");
753 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
754 res->start = res->end = 0;
755 res->flags = 0;
756 }
757
758 list_for_each_entry(b, &bus->children, node)
759 pcibios_allocate_bus_resources(b);
760}
761
762static inline void alloc_resource(struct pci_dev *dev, int idx)
763{
764 struct resource *pr, *r = &dev->resource[idx];
765
766 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
767 pci_name(dev), idx,
768 (unsigned long long)r->start,
769 (unsigned long long)r->end,
770 (unsigned int)r->flags);
771
772 pr = pci_find_parent_resource(dev, r);
773 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
774 request_resource(pr, r) < 0) {
775 pr_warn("PCI: Cannot allocate resource region %d ", idx);
776 pr_cont("of device %s, will remap\n", pci_name(dev));
777 if (pr)
778 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
779 pr,
780 (unsigned long long)pr->start,
781 (unsigned long long)pr->end,
782 (unsigned int)pr->flags);
783 /* We'll assign a new address later */
784 r->flags |= IORESOURCE_UNSET;
785 r->end -= r->start;
786 r->start = 0;
787 }
788}
789
790static void __init pcibios_allocate_resources(int pass)
791{
792 struct pci_dev *dev = NULL;
793 int idx, disabled;
794 u16 command;
795 struct resource *r;
796
797 for_each_pci_dev(dev) {
798 pci_read_config_word(dev, PCI_COMMAND, &command);
799 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
800 r = &dev->resource[idx];
801 if (r->parent) /* Already allocated */
802 continue;
803 if (!r->flags || (r->flags & IORESOURCE_UNSET))
804 continue; /* Not assigned at all */
805 /* We only allocate ROMs on pass 1 just in case they
806 * have been screwed up by firmware
807 */
808 if (idx == PCI_ROM_RESOURCE)
809 disabled = 1;
810 if (r->flags & IORESOURCE_IO)
811 disabled = !(command & PCI_COMMAND_IO);
812 else
813 disabled = !(command & PCI_COMMAND_MEMORY);
814 if (pass == disabled)
815 alloc_resource(dev, idx);
816 }
817 if (pass)
818 continue;
819 r = &dev->resource[PCI_ROM_RESOURCE];
820 if (r->flags) {
821 /* Turn the ROM off, leave the resource region,
822 * but keep it unregistered.
823 */
824 u32 reg;
825 pci_read_config_dword(dev, dev->rom_base_reg, ®);
826 if (reg & PCI_ROM_ADDRESS_ENABLE) {
827 pr_debug("PCI: Switching off ROM of %s\n",
828 pci_name(dev));
829 r->flags &= ~IORESOURCE_ROM_ENABLE;
830 pci_write_config_dword(dev, dev->rom_base_reg,
831 reg & ~PCI_ROM_ADDRESS_ENABLE);
832 }
833 }
834 }
835}
836
837static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
838{
839 struct pci_controller *hose = pci_bus_to_host(bus);
840 resource_size_t offset;
841 struct resource *res, *pres;
842 int i;
843
844 pr_debug("Reserving legacy ranges for domain %04x\n",
845 pci_domain_nr(bus));
846
847 /* Check for IO */
848 if (!(hose->io_resource.flags & IORESOURCE_IO))
849 goto no_io;
850 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
851 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
852 BUG_ON(res == NULL);
853 res->name = "Legacy IO";
854 res->flags = IORESOURCE_IO;
855 res->start = offset;
856 res->end = (offset + 0xfff) & 0xfffffffful;
857 pr_debug("Candidate legacy IO: %pR\n", res);
858 if (request_resource(&hose->io_resource, res)) {
859 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
860 pci_domain_nr(bus), bus->number, res);
861 kfree(res);
862 }
863
864 no_io:
865 /* Check for memory */
866 offset = hose->pci_mem_offset;
867 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
868 for (i = 0; i < 3; i++) {
869 pres = &hose->mem_resources[i];
870 if (!(pres->flags & IORESOURCE_MEM))
871 continue;
872 pr_debug("hose mem res: %pR\n", pres);
873 if ((pres->start - offset) <= 0xa0000 &&
874 (pres->end - offset) >= 0xbffff)
875 break;
876 }
877 if (i >= 3)
878 return;
879 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
880 BUG_ON(res == NULL);
881 res->name = "Legacy VGA memory";
882 res->flags = IORESOURCE_MEM;
883 res->start = 0xa0000 + offset;
884 res->end = 0xbffff + offset;
885 pr_debug("Candidate VGA memory: %pR\n", res);
886 if (request_resource(pres, res)) {
887 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
888 pci_domain_nr(bus), bus->number, res);
889 kfree(res);
890 }
891}
892
893void __init pcibios_resource_survey(void)
894{
895 struct pci_bus *b;
896
897 /* Allocate and assign resources. If we re-assign everything, then
898 * we skip the allocate phase
899 */
900 list_for_each_entry(b, &pci_root_buses, node)
901 pcibios_allocate_bus_resources(b);
902
903 pcibios_allocate_resources(0);
904 pcibios_allocate_resources(1);
905
906 /* Before we start assigning unassigned resource, we try to reserve
907 * the low IO area and the VGA memory area if they intersect the
908 * bus available resources to avoid allocating things on top of them
909 */
910 list_for_each_entry(b, &pci_root_buses, node)
911 pcibios_reserve_legacy_regions(b);
912
913 /* Now proceed to assigning things that were left unassigned */
914 pr_debug("PCI: Assigning unassigned resources...\n");
915 pci_assign_unassigned_resources();
916}
917
918/* This is used by the PCI hotplug driver to allocate resource
919 * of newly plugged busses. We can try to consolidate with the
920 * rest of the code later, for now, keep it as-is as our main
921 * resource allocation function doesn't deal with sub-trees yet.
922 */
923void pcibios_claim_one_bus(struct pci_bus *bus)
924{
925 struct pci_dev *dev;
926 struct pci_bus *child_bus;
927
928 list_for_each_entry(dev, &bus->devices, bus_list) {
929 int i;
930
931 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
932 struct resource *r = &dev->resource[i];
933
934 if (r->parent || !r->start || !r->flags)
935 continue;
936
937 pr_debug("PCI: Claiming %s: ", pci_name(dev));
938 pr_debug("Resource %d: %016llx..%016llx [%x]\n",
939 i, (unsigned long long)r->start,
940 (unsigned long long)r->end,
941 (unsigned int)r->flags);
942
943 if (pci_claim_resource(dev, i) == 0)
944 continue;
945
946 pci_claim_bridge_resource(dev, i);
947 }
948 }
949
950 list_for_each_entry(child_bus, &bus->children, node)
951 pcibios_claim_one_bus(child_bus);
952}
953EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
954
955
956/* pcibios_finish_adding_to_bus
957 *
958 * This is to be called by the hotplug code after devices have been
959 * added to a bus, this include calling it for a PHB that is just
960 * being added
961 */
962void pcibios_finish_adding_to_bus(struct pci_bus *bus)
963{
964 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
965 pci_domain_nr(bus), bus->number);
966
967 /* Allocate bus and devices resources */
968 pcibios_allocate_bus_resources(bus);
969 pcibios_claim_one_bus(bus);
970
971 /* Add new devices to global lists. Register in proc, sysfs. */
972 pci_bus_add_devices(bus);
973
974 /* Fixup EEH */
975 /* eeh_add_device_tree_late(bus); */
976}
977EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
978
979static void pcibios_setup_phb_resources(struct pci_controller *hose,
980 struct list_head *resources)
981{
982 unsigned long io_offset;
983 struct resource *res;
984 int i;
985
986 /* Hookup PHB IO resource */
987 res = &hose->io_resource;
988
989 /* Fixup IO space offset */
990 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
991 res->start = (res->start + io_offset) & 0xffffffffu;
992 res->end = (res->end + io_offset) & 0xffffffffu;
993
994 if (!res->flags) {
995 pr_warn("PCI: I/O resource not set for host ");
996 pr_cont("bridge %pOF (domain %d)\n",
997 hose->dn, hose->global_number);
998 /* Workaround for lack of IO resource only on 32-bit */
999 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1000 res->end = res->start + IO_SPACE_LIMIT;
1001 res->flags = IORESOURCE_IO;
1002 }
1003 pci_add_resource_offset(resources, res,
1004 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
1005
1006 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1007 (unsigned long long)res->start,
1008 (unsigned long long)res->end,
1009 (unsigned long)res->flags);
1010
1011 /* Hookup PHB Memory resources */
1012 for (i = 0; i < 3; ++i) {
1013 res = &hose->mem_resources[i];
1014 if (!res->flags) {
1015 if (i > 0)
1016 continue;
1017 pr_err("PCI: Memory resource 0 not set for ");
1018 pr_cont("host bridge %pOF (domain %d)\n",
1019 hose->dn, hose->global_number);
1020
1021 /* Workaround for lack of MEM resource only on 32-bit */
1022 res->start = hose->pci_mem_offset;
1023 res->end = (resource_size_t)-1LL;
1024 res->flags = IORESOURCE_MEM;
1025
1026 }
1027 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
1028
1029 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1030 i, (unsigned long long)res->start,
1031 (unsigned long long)res->end,
1032 (unsigned long)res->flags);
1033 }
1034
1035 pr_debug("PCI: PHB MEM offset = %016llx\n",
1036 (unsigned long long)hose->pci_mem_offset);
1037 pr_debug("PCI: PHB IO offset = %08lx\n",
1038 (unsigned long)hose->io_base_virt - _IO_BASE);
1039}
1040
1041static void pcibios_scan_phb(struct pci_controller *hose)
1042{
1043 LIST_HEAD(resources);
1044 struct pci_bus *bus;
1045 struct device_node *node = hose->dn;
1046
1047 pr_debug("PCI: Scanning PHB %pOF\n", node);
1048
1049 pcibios_setup_phb_resources(hose, &resources);
1050
1051 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
1052 hose->ops, hose, &resources);
1053 if (bus == NULL) {
1054 pr_err("Failed to create bus for PCI domain %04x\n",
1055 hose->global_number);
1056 pci_free_resource_list(&resources);
1057 return;
1058 }
1059 bus->busn_res.start = hose->first_busno;
1060 hose->bus = bus;
1061
1062 hose->last_busno = bus->busn_res.end;
1063}
1064
1065static int __init pcibios_init(void)
1066{
1067 struct pci_controller *hose, *tmp;
1068 int next_busno = 0;
1069
1070 pr_info("PCI: Probing PCI hardware\n");
1071
1072 /* Scan all of the recorded PCI controllers. */
1073 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1074 hose->last_busno = 0xff;
1075 pcibios_scan_phb(hose);
1076 if (next_busno <= hose->last_busno)
1077 next_busno = hose->last_busno + 1;
1078 }
1079 pci_bus_count = next_busno;
1080
1081 /* Call common code to handle resource allocation */
1082 pcibios_resource_survey();
1083 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1084 if (hose->bus)
1085 pci_bus_add_devices(hose->bus);
1086 }
1087
1088 return 0;
1089}
1090
1091subsys_initcall(pcibios_init);
1092
1093static struct pci_controller *pci_bus_to_hose(int bus)
1094{
1095 struct pci_controller *hose, *tmp;
1096
1097 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1098 if (bus >= hose->first_busno && bus <= hose->last_busno)
1099 return hose;
1100 return NULL;
1101}
1102
1103/* Provide information on locations of various I/O regions in physical
1104 * memory. Do this on a per-card basis so that we choose the right
1105 * root bridge.
1106 * Note that the returned IO or memory base is a physical address
1107 */
1108
1109long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1110{
1111 struct pci_controller *hose;
1112 long result = -EOPNOTSUPP;
1113
1114 hose = pci_bus_to_hose(bus);
1115 if (!hose)
1116 return -ENODEV;
1117
1118 switch (which) {
1119 case IOBASE_BRIDGE_NUMBER:
1120 return (long)hose->first_busno;
1121 case IOBASE_MEMORY:
1122 return (long)hose->pci_mem_offset;
1123 case IOBASE_IO:
1124 return (long)hose->io_base_phys;
1125 case IOBASE_ISA_IO:
1126 return (long)isa_io_base;
1127 case IOBASE_ISA_MEM:
1128 return (long)isa_mem_base;
1129 }
1130
1131 return result;
1132}
1133
1134/*
1135 * Null PCI config access functions, for the case when we can't
1136 * find a hose.
1137 */
1138#define NULL_PCI_OP(rw, size, type) \
1139static int \
1140null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1141{ \
1142 return PCIBIOS_DEVICE_NOT_FOUND; \
1143}
1144
1145static int
1146null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1147 int len, u32 *val)
1148{
1149 return PCIBIOS_DEVICE_NOT_FOUND;
1150}
1151
1152static int
1153null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1154 int len, u32 val)
1155{
1156 return PCIBIOS_DEVICE_NOT_FOUND;
1157}
1158
1159static struct pci_ops null_pci_ops = {
1160 .read = null_read_config,
1161 .write = null_write_config,
1162};
1163
1164/*
1165 * These functions are used early on before PCI scanning is done
1166 * and all of the pci_dev and pci_bus structures have been created.
1167 */
1168static struct pci_bus *
1169fake_pci_bus(struct pci_controller *hose, int busnr)
1170{
1171 static struct pci_bus bus;
1172
1173 if (!hose)
1174 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1175
1176 bus.number = busnr;
1177 bus.sysdata = hose;
1178 bus.ops = hose ? hose->ops : &null_pci_ops;
1179 return &bus;
1180}
1181
1182#define EARLY_PCI_OP(rw, size, type) \
1183int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1184 int devfn, int offset, type value) \
1185{ \
1186 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1187 devfn, offset, value); \
1188}
1189
1190EARLY_PCI_OP(read, byte, u8 *)
1191EARLY_PCI_OP(read, word, u16 *)
1192EARLY_PCI_OP(read, dword, u32 *)
1193EARLY_PCI_OP(write, byte, u8)
1194EARLY_PCI_OP(write, word, u16)
1195EARLY_PCI_OP(write, dword, u32)
1196
1197int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1198 int cap)
1199{
1200 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1201}
1202
1/*
2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
4 *
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
7 *
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
10 *
11 * Common pmac/prep/chrp pci routines. -- Cort
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/bootmem.h>
24#include <linux/mm.h>
25#include <linux/list.h>
26#include <linux/syscalls.h>
27#include <linux/irq.h>
28#include <linux/vmalloc.h>
29#include <linux/slab.h>
30#include <linux/of.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/of_pci.h>
34#include <linux/export.h>
35
36#include <asm/processor.h>
37#include <linux/io.h>
38#include <asm/pci-bridge.h>
39#include <asm/byteorder.h>
40
41static DEFINE_SPINLOCK(hose_spinlock);
42LIST_HEAD(hose_list);
43
44/* XXX kill that some day ... */
45static int global_phb_number; /* Global phb counter */
46
47/* ISA Memory physical address */
48resource_size_t isa_mem_base;
49
50unsigned long isa_io_base;
51EXPORT_SYMBOL(isa_io_base);
52
53static int pci_bus_count;
54
55struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
56{
57 struct pci_controller *phb;
58
59 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
60 if (!phb)
61 return NULL;
62 spin_lock(&hose_spinlock);
63 phb->global_number = global_phb_number++;
64 list_add_tail(&phb->list_node, &hose_list);
65 spin_unlock(&hose_spinlock);
66 phb->dn = dev;
67 phb->is_dynamic = mem_init_done;
68 return phb;
69}
70
71void pcibios_free_controller(struct pci_controller *phb)
72{
73 spin_lock(&hose_spinlock);
74 list_del(&phb->list_node);
75 spin_unlock(&hose_spinlock);
76
77 if (phb->is_dynamic)
78 kfree(phb);
79}
80
81static resource_size_t pcibios_io_size(const struct pci_controller *hose)
82{
83 return resource_size(&hose->io_resource);
84}
85
86int pcibios_vaddr_is_ioport(void __iomem *address)
87{
88 int ret = 0;
89 struct pci_controller *hose;
90 resource_size_t size;
91
92 spin_lock(&hose_spinlock);
93 list_for_each_entry(hose, &hose_list, list_node) {
94 size = pcibios_io_size(hose);
95 if (address >= hose->io_base_virt &&
96 address < (hose->io_base_virt + size)) {
97 ret = 1;
98 break;
99 }
100 }
101 spin_unlock(&hose_spinlock);
102 return ret;
103}
104
105unsigned long pci_address_to_pio(phys_addr_t address)
106{
107 struct pci_controller *hose;
108 resource_size_t size;
109 unsigned long ret = ~0;
110
111 spin_lock(&hose_spinlock);
112 list_for_each_entry(hose, &hose_list, list_node) {
113 size = pcibios_io_size(hose);
114 if (address >= hose->io_base_phys &&
115 address < (hose->io_base_phys + size)) {
116 unsigned long base =
117 (unsigned long)hose->io_base_virt - _IO_BASE;
118 ret = base + (address - hose->io_base_phys);
119 break;
120 }
121 }
122 spin_unlock(&hose_spinlock);
123
124 return ret;
125}
126EXPORT_SYMBOL_GPL(pci_address_to_pio);
127
128/* This routine is meant to be used early during boot, when the
129 * PCI bus numbers have not yet been assigned, and you need to
130 * issue PCI config cycles to an OF device.
131 * It could also be used to "fix" RTAS config cycles if you want
132 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
133 * config cycles.
134 */
135struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
136{
137 while (node) {
138 struct pci_controller *hose, *tmp;
139 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
140 if (hose->dn == node)
141 return hose;
142 node = node->parent;
143 }
144 return NULL;
145}
146
147void pcibios_set_master(struct pci_dev *dev)
148{
149 /* No special bus mastering setup handling */
150}
151
152/*
153 * Platform support for /proc/bus/pci/X/Y mmap()s,
154 * modelled on the sparc64 implementation by Dave Miller.
155 * -- paulus.
156 */
157
158/*
159 * Adjust vm_pgoff of VMA such that it is the physical page offset
160 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
161 *
162 * Basically, the user finds the base address for his device which he wishes
163 * to mmap. They read the 32-bit value from the config space base register,
164 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
165 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
166 *
167 * Returns negative error code on failure, zero on success.
168 */
169static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
170 resource_size_t *offset,
171 enum pci_mmap_state mmap_state)
172{
173 struct pci_controller *hose = pci_bus_to_host(dev->bus);
174 unsigned long io_offset = 0;
175 int i, res_bit;
176
177 if (!hose)
178 return NULL; /* should never happen */
179
180 /* If memory, add on the PCI bridge address offset */
181 if (mmap_state == pci_mmap_mem) {
182#if 0 /* See comment in pci_resource_to_user() for why this is disabled */
183 *offset += hose->pci_mem_offset;
184#endif
185 res_bit = IORESOURCE_MEM;
186 } else {
187 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
188 *offset += io_offset;
189 res_bit = IORESOURCE_IO;
190 }
191
192 /*
193 * Check that the offset requested corresponds to one of the
194 * resources of the device.
195 */
196 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
197 struct resource *rp = &dev->resource[i];
198 int flags = rp->flags;
199
200 /* treat ROM as memory (should be already) */
201 if (i == PCI_ROM_RESOURCE)
202 flags |= IORESOURCE_MEM;
203
204 /* Active and same type? */
205 if ((flags & res_bit) == 0)
206 continue;
207
208 /* In the range of this resource? */
209 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
210 continue;
211
212 /* found it! construct the final physical address */
213 if (mmap_state == pci_mmap_io)
214 *offset += hose->io_base_phys - io_offset;
215 return rp;
216 }
217
218 return NULL;
219}
220
221/*
222 * This one is used by /dev/mem and fbdev who have no clue about the
223 * PCI device, it tries to find the PCI device first and calls the
224 * above routine
225 */
226pgprot_t pci_phys_mem_access_prot(struct file *file,
227 unsigned long pfn,
228 unsigned long size,
229 pgprot_t prot)
230{
231 struct pci_dev *pdev = NULL;
232 struct resource *found = NULL;
233 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
234 int i;
235
236 if (page_is_ram(pfn))
237 return prot;
238
239 prot = pgprot_noncached(prot);
240 for_each_pci_dev(pdev) {
241 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
242 struct resource *rp = &pdev->resource[i];
243 int flags = rp->flags;
244
245 /* Active and same type? */
246 if ((flags & IORESOURCE_MEM) == 0)
247 continue;
248 /* In the range of this resource? */
249 if (offset < (rp->start & PAGE_MASK) ||
250 offset > rp->end)
251 continue;
252 found = rp;
253 break;
254 }
255 if (found)
256 break;
257 }
258 if (found) {
259 if (found->flags & IORESOURCE_PREFETCH)
260 prot = pgprot_noncached_wc(prot);
261 pci_dev_put(pdev);
262 }
263
264 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
265 (unsigned long long)offset, pgprot_val(prot));
266
267 return prot;
268}
269
270/*
271 * Perform the actual remap of the pages for a PCI device mapping, as
272 * appropriate for this architecture. The region in the process to map
273 * is described by vm_start and vm_end members of VMA, the base physical
274 * address is found in vm_pgoff.
275 * The pci device structure is provided so that architectures may make mapping
276 * decisions on a per-device or per-bus basis.
277 *
278 * Returns a negative error code on failure, zero on success.
279 */
280int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
281 enum pci_mmap_state mmap_state, int write_combine)
282{
283 resource_size_t offset =
284 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
285 struct resource *rp;
286 int ret;
287
288 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
289 if (rp == NULL)
290 return -EINVAL;
291
292 vma->vm_pgoff = offset >> PAGE_SHIFT;
293 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
294
295 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
296 vma->vm_end - vma->vm_start, vma->vm_page_prot);
297
298 return ret;
299}
300
301/* This provides legacy IO read access on a bus */
302int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
303{
304 unsigned long offset;
305 struct pci_controller *hose = pci_bus_to_host(bus);
306 struct resource *rp = &hose->io_resource;
307 void __iomem *addr;
308
309 /* Check if port can be supported by that bus. We only check
310 * the ranges of the PHB though, not the bus itself as the rules
311 * for forwarding legacy cycles down bridges are not our problem
312 * here. So if the host bridge supports it, we do it.
313 */
314 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
315 offset += port;
316
317 if (!(rp->flags & IORESOURCE_IO))
318 return -ENXIO;
319 if (offset < rp->start || (offset + size) > rp->end)
320 return -ENXIO;
321 addr = hose->io_base_virt + port;
322
323 switch (size) {
324 case 1:
325 *((u8 *)val) = in_8(addr);
326 return 1;
327 case 2:
328 if (port & 1)
329 return -EINVAL;
330 *((u16 *)val) = in_le16(addr);
331 return 2;
332 case 4:
333 if (port & 3)
334 return -EINVAL;
335 *((u32 *)val) = in_le32(addr);
336 return 4;
337 }
338 return -EINVAL;
339}
340
341/* This provides legacy IO write access on a bus */
342int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
343{
344 unsigned long offset;
345 struct pci_controller *hose = pci_bus_to_host(bus);
346 struct resource *rp = &hose->io_resource;
347 void __iomem *addr;
348
349 /* Check if port can be supported by that bus. We only check
350 * the ranges of the PHB though, not the bus itself as the rules
351 * for forwarding legacy cycles down bridges are not our problem
352 * here. So if the host bridge supports it, we do it.
353 */
354 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
355 offset += port;
356
357 if (!(rp->flags & IORESOURCE_IO))
358 return -ENXIO;
359 if (offset < rp->start || (offset + size) > rp->end)
360 return -ENXIO;
361 addr = hose->io_base_virt + port;
362
363 /* WARNING: The generic code is idiotic. It gets passed a pointer
364 * to what can be a 1, 2 or 4 byte quantity and always reads that
365 * as a u32, which means that we have to correct the location of
366 * the data read within those 32 bits for size 1 and 2
367 */
368 switch (size) {
369 case 1:
370 out_8(addr, val >> 24);
371 return 1;
372 case 2:
373 if (port & 1)
374 return -EINVAL;
375 out_le16(addr, val >> 16);
376 return 2;
377 case 4:
378 if (port & 3)
379 return -EINVAL;
380 out_le32(addr, val);
381 return 4;
382 }
383 return -EINVAL;
384}
385
386/* This provides legacy IO or memory mmap access on a bus */
387int pci_mmap_legacy_page_range(struct pci_bus *bus,
388 struct vm_area_struct *vma,
389 enum pci_mmap_state mmap_state)
390{
391 struct pci_controller *hose = pci_bus_to_host(bus);
392 resource_size_t offset =
393 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
394 resource_size_t size = vma->vm_end - vma->vm_start;
395 struct resource *rp;
396
397 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
398 pci_domain_nr(bus), bus->number,
399 mmap_state == pci_mmap_mem ? "MEM" : "IO",
400 (unsigned long long)offset,
401 (unsigned long long)(offset + size - 1));
402
403 if (mmap_state == pci_mmap_mem) {
404 /* Hack alert !
405 *
406 * Because X is lame and can fail starting if it gets an error
407 * trying to mmap legacy_mem (instead of just moving on without
408 * legacy memory access) we fake it here by giving it anonymous
409 * memory, effectively behaving just like /dev/zero
410 */
411 if ((offset + size) > hose->isa_mem_size) {
412#ifdef CONFIG_MMU
413 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
414 current->comm, current->pid);
415 pr_debug("legacy memory for 0%04x:%02x\n",
416 pci_domain_nr(bus), bus->number);
417#endif
418 if (vma->vm_flags & VM_SHARED)
419 return shmem_zero_setup(vma);
420 return 0;
421 }
422 offset += hose->isa_mem_phys;
423 } else {
424 unsigned long io_offset = (unsigned long)hose->io_base_virt -
425 _IO_BASE;
426 unsigned long roffset = offset + io_offset;
427 rp = &hose->io_resource;
428 if (!(rp->flags & IORESOURCE_IO))
429 return -ENXIO;
430 if (roffset < rp->start || (roffset + size) > rp->end)
431 return -ENXIO;
432 offset += hose->io_base_phys;
433 }
434 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
435
436 vma->vm_pgoff = offset >> PAGE_SHIFT;
437 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
438 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
439 vma->vm_end - vma->vm_start,
440 vma->vm_page_prot);
441}
442
443void pci_resource_to_user(const struct pci_dev *dev, int bar,
444 const struct resource *rsrc,
445 resource_size_t *start, resource_size_t *end)
446{
447 struct pci_bus_region region;
448
449 if (rsrc->flags & IORESOURCE_IO) {
450 pcibios_resource_to_bus(dev->bus, ®ion,
451 (struct resource *) rsrc);
452 *start = region.start;
453 *end = region.end;
454 return;
455 }
456
457 /* We pass a CPU physical address to userland for MMIO instead of a
458 * BAR value because X is lame and expects to be able to use that
459 * to pass to /dev/mem!
460 *
461 * That means we may have 64-bit values where some apps only expect
462 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
463 */
464 *start = rsrc->start;
465 *end = rsrc->end;
466}
467
468/**
469 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
470 * @hose: newly allocated pci_controller to be setup
471 * @dev: device node of the host bridge
472 * @primary: set if primary bus (32 bits only, soon to be deprecated)
473 *
474 * This function will parse the "ranges" property of a PCI host bridge device
475 * node and setup the resource mapping of a pci controller based on its
476 * content.
477 *
478 * Life would be boring if it wasn't for a few issues that we have to deal
479 * with here:
480 *
481 * - We can only cope with one IO space range and up to 3 Memory space
482 * ranges. However, some machines (thanks Apple !) tend to split their
483 * space into lots of small contiguous ranges. So we have to coalesce.
484 *
485 * - We can only cope with all memory ranges having the same offset
486 * between CPU addresses and PCI addresses. Unfortunately, some bridges
487 * are setup for a large 1:1 mapping along with a small "window" which
488 * maps PCI address 0 to some arbitrary high address of the CPU space in
489 * order to give access to the ISA memory hole.
490 * The way out of here that I've chosen for now is to always set the
491 * offset based on the first resource found, then override it if we
492 * have a different offset and the previous was set by an ISA hole.
493 *
494 * - Some busses have IO space not starting at 0, which causes trouble with
495 * the way we do our IO resource renumbering. The code somewhat deals with
496 * it for 64 bits but I would expect problems on 32 bits.
497 *
498 * - Some 32 bits platforms such as 4xx can have physical space larger than
499 * 32 bits so we need to use 64 bits values for the parsing
500 */
501void pci_process_bridge_OF_ranges(struct pci_controller *hose,
502 struct device_node *dev, int primary)
503{
504 int memno = 0, isa_hole = -1;
505 unsigned long long isa_mb = 0;
506 struct resource *res;
507 struct of_pci_range range;
508 struct of_pci_range_parser parser;
509
510 pr_info("PCI host bridge %s %s ranges:\n",
511 dev->full_name, primary ? "(primary)" : "");
512
513 /* Check for ranges property */
514 if (of_pci_range_parser_init(&parser, dev))
515 return;
516
517 pr_debug("Parsing ranges property...\n");
518 for_each_of_pci_range(&parser, &range) {
519 /* Read next ranges element */
520 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
521 range.pci_space, range.pci_addr);
522 pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
523 range.cpu_addr, range.size);
524
525 /* If we failed translation or got a zero-sized region
526 * (some FW try to feed us with non sensical zero sized regions
527 * such as power3 which look like some kind of attempt
528 * at exposing the VGA memory hole)
529 */
530 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
531 continue;
532
533 /* Act based on address space type */
534 res = NULL;
535 switch (range.flags & IORESOURCE_TYPE_BITS) {
536 case IORESOURCE_IO:
537 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
538 range.cpu_addr, range.cpu_addr + range.size - 1,
539 range.pci_addr);
540
541 /* We support only one IO range */
542 if (hose->pci_io_size) {
543 pr_info(" \\--> Skipped (too many) !\n");
544 continue;
545 }
546 /* On 32 bits, limit I/O space to 16MB */
547 if (range.size > 0x01000000)
548 range.size = 0x01000000;
549
550 /* 32 bits needs to map IOs here */
551 hose->io_base_virt = ioremap(range.cpu_addr,
552 range.size);
553
554 /* Expect trouble if pci_addr is not 0 */
555 if (primary)
556 isa_io_base =
557 (unsigned long)hose->io_base_virt;
558 /* pci_io_size and io_base_phys always represent IO
559 * space starting at 0 so we factor in pci_addr
560 */
561 hose->pci_io_size = range.pci_addr + range.size;
562 hose->io_base_phys = range.cpu_addr - range.pci_addr;
563
564 /* Build resource */
565 res = &hose->io_resource;
566 range.cpu_addr = range.pci_addr;
567
568 break;
569 case IORESOURCE_MEM:
570 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
571 range.cpu_addr, range.cpu_addr + range.size - 1,
572 range.pci_addr,
573 (range.pci_space & 0x40000000) ?
574 "Prefetch" : "");
575
576 /* We support only 3 memory ranges */
577 if (memno >= 3) {
578 pr_info(" \\--> Skipped (too many) !\n");
579 continue;
580 }
581 /* Handles ISA memory hole space here */
582 if (range.pci_addr == 0) {
583 isa_mb = range.cpu_addr;
584 isa_hole = memno;
585 if (primary || isa_mem_base == 0)
586 isa_mem_base = range.cpu_addr;
587 hose->isa_mem_phys = range.cpu_addr;
588 hose->isa_mem_size = range.size;
589 }
590
591 /* We get the PCI/Mem offset from the first range or
592 * the, current one if the offset came from an ISA
593 * hole. If they don't match, bugger.
594 */
595 if (memno == 0 ||
596 (isa_hole >= 0 && range.pci_addr != 0 &&
597 hose->pci_mem_offset == isa_mb))
598 hose->pci_mem_offset = range.cpu_addr -
599 range.pci_addr;
600 else if (range.pci_addr != 0 &&
601 hose->pci_mem_offset != range.cpu_addr -
602 range.pci_addr) {
603 pr_info(" \\--> Skipped (offset mismatch) !\n");
604 continue;
605 }
606
607 /* Build resource */
608 res = &hose->mem_resources[memno++];
609 break;
610 }
611 if (res != NULL) {
612 res->name = dev->full_name;
613 res->flags = range.flags;
614 res->start = range.cpu_addr;
615 res->end = range.cpu_addr + range.size - 1;
616 res->parent = res->child = res->sibling = NULL;
617 }
618 }
619
620 /* If there's an ISA hole and the pci_mem_offset is -not- matching
621 * the ISA hole offset, then we need to remove the ISA hole from
622 * the resource list for that brige
623 */
624 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
625 unsigned int next = isa_hole + 1;
626 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
627 if (next < memno)
628 memmove(&hose->mem_resources[isa_hole],
629 &hose->mem_resources[next],
630 sizeof(struct resource) * (memno - next));
631 hose->mem_resources[--memno].flags = 0;
632 }
633}
634
635/* Display the domain number in /proc */
636int pci_proc_domain(struct pci_bus *bus)
637{
638 return pci_domain_nr(bus);
639}
640
641/* This header fixup will do the resource fixup for all devices as they are
642 * probed, but not for bridge ranges
643 */
644static void pcibios_fixup_resources(struct pci_dev *dev)
645{
646 struct pci_controller *hose = pci_bus_to_host(dev->bus);
647 int i;
648
649 if (!hose) {
650 pr_err("No host bridge for PCI dev %s !\n",
651 pci_name(dev));
652 return;
653 }
654 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
655 struct resource *res = dev->resource + i;
656 if (!res->flags)
657 continue;
658 if (res->start == 0) {
659 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
660 pci_name(dev), i,
661 (unsigned long long)res->start,
662 (unsigned long long)res->end,
663 (unsigned int)res->flags);
664 pr_debug("is unassigned\n");
665 res->end -= res->start;
666 res->start = 0;
667 res->flags |= IORESOURCE_UNSET;
668 continue;
669 }
670
671 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
672 pci_name(dev), i,
673 (unsigned long long)res->start,
674 (unsigned long long)res->end,
675 (unsigned int)res->flags);
676 }
677}
678DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
679
680/* This function tries to figure out if a bridge resource has been initialized
681 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
682 * things go more smoothly when it gets it right. It should covers cases such
683 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
684 */
685static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
686 struct resource *res)
687{
688 struct pci_controller *hose = pci_bus_to_host(bus);
689 struct pci_dev *dev = bus->self;
690 resource_size_t offset;
691 u16 command;
692 int i;
693
694 /* Job is a bit different between memory and IO */
695 if (res->flags & IORESOURCE_MEM) {
696 /* If the BAR is non-0 (res != pci_mem_offset) then it's
697 * probably been initialized by somebody
698 */
699 if (res->start != hose->pci_mem_offset)
700 return 0;
701
702 /* The BAR is 0, let's check if memory decoding is enabled on
703 * the bridge. If not, we consider it unassigned
704 */
705 pci_read_config_word(dev, PCI_COMMAND, &command);
706 if ((command & PCI_COMMAND_MEMORY) == 0)
707 return 1;
708
709 /* Memory decoding is enabled and the BAR is 0. If any of
710 * the bridge resources covers that starting address (0 then
711 * it's good enough for us for memory
712 */
713 for (i = 0; i < 3; i++) {
714 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
715 hose->mem_resources[i].start == hose->pci_mem_offset)
716 return 0;
717 }
718
719 /* Well, it starts at 0 and we know it will collide so we may as
720 * well consider it as unassigned. That covers the Apple case.
721 */
722 return 1;
723 } else {
724 /* If the BAR is non-0, then we consider it assigned */
725 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
726 if (((res->start - offset) & 0xfffffffful) != 0)
727 return 0;
728
729 /* Here, we are a bit different than memory as typically IO
730 * space starting at low addresses -is- valid. What we do
731 * instead if that we consider as unassigned anything that
732 * doesn't have IO enabled in the PCI command register,
733 * and that's it.
734 */
735 pci_read_config_word(dev, PCI_COMMAND, &command);
736 if (command & PCI_COMMAND_IO)
737 return 0;
738
739 /* It's starting at 0 and IO is disabled in the bridge, consider
740 * it unassigned
741 */
742 return 1;
743 }
744}
745
746/* Fixup resources of a PCI<->PCI bridge */
747static void pcibios_fixup_bridge(struct pci_bus *bus)
748{
749 struct resource *res;
750 int i;
751
752 struct pci_dev *dev = bus->self;
753
754 pci_bus_for_each_resource(bus, res, i) {
755 if (!res)
756 continue;
757 if (!res->flags)
758 continue;
759 if (i >= 3 && bus->self->transparent)
760 continue;
761
762 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
763 pci_name(dev), i,
764 (unsigned long long)res->start,
765 (unsigned long long)res->end,
766 (unsigned int)res->flags);
767
768 /* Try to detect uninitialized P2P bridge resources,
769 * and clear them out so they get re-assigned later
770 */
771 if (pcibios_uninitialized_bridge_resource(bus, res)) {
772 res->flags = 0;
773 pr_debug("PCI:%s (unassigned)\n",
774 pci_name(dev));
775 } else {
776 pr_debug("PCI:%s %016llx-%016llx\n",
777 pci_name(dev),
778 (unsigned long long)res->start,
779 (unsigned long long)res->end);
780 }
781 }
782}
783
784void pcibios_setup_bus_self(struct pci_bus *bus)
785{
786 /* Fix up the bus resources for P2P bridges */
787 if (bus->self != NULL)
788 pcibios_fixup_bridge(bus);
789}
790
791void pcibios_setup_bus_devices(struct pci_bus *bus)
792{
793 struct pci_dev *dev;
794
795 pr_debug("PCI: Fixup bus devices %d (%s)\n",
796 bus->number, bus->self ? pci_name(bus->self) : "PHB");
797
798 list_for_each_entry(dev, &bus->devices, bus_list) {
799 /* Setup OF node pointer in archdata */
800 dev->dev.of_node = pci_device_to_OF_node(dev);
801
802 /* Fixup NUMA node as it may not be setup yet by the generic
803 * code and is needed by the DMA init
804 */
805 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
806
807 /* Read default IRQs and fixup if necessary */
808 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
809 }
810}
811
812void pcibios_fixup_bus(struct pci_bus *bus)
813{
814 /* nothing to do */
815}
816EXPORT_SYMBOL(pcibios_fixup_bus);
817
818/*
819 * We need to avoid collisions with `mirrored' VGA ports
820 * and other strange ISA hardware, so we always want the
821 * addresses to be allocated in the 0x000-0x0ff region
822 * modulo 0x400.
823 *
824 * Why? Because some silly external IO cards only decode
825 * the low 10 bits of the IO address. The 0x00-0xff region
826 * is reserved for motherboard devices that decode all 16
827 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
828 * but we want to try to avoid allocating at 0x2900-0x2bff
829 * which might have be mirrored at 0x0100-0x03ff..
830 */
831resource_size_t pcibios_align_resource(void *data, const struct resource *res,
832 resource_size_t size, resource_size_t align)
833{
834 return res->start;
835}
836EXPORT_SYMBOL(pcibios_align_resource);
837
838int pcibios_add_device(struct pci_dev *dev)
839{
840 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
841
842 return 0;
843}
844EXPORT_SYMBOL(pcibios_add_device);
845
846/*
847 * Reparent resource children of pr that conflict with res
848 * under res, and make res replace those children.
849 */
850static int __init reparent_resources(struct resource *parent,
851 struct resource *res)
852{
853 struct resource *p, **pp;
854 struct resource **firstpp = NULL;
855
856 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
857 if (p->end < res->start)
858 continue;
859 if (res->end < p->start)
860 break;
861 if (p->start < res->start || p->end > res->end)
862 return -1; /* not completely contained */
863 if (firstpp == NULL)
864 firstpp = pp;
865 }
866 if (firstpp == NULL)
867 return -1; /* didn't find any conflicting entries? */
868 res->parent = parent;
869 res->child = *firstpp;
870 res->sibling = *pp;
871 *firstpp = res;
872 *pp = NULL;
873 for (p = res->child; p != NULL; p = p->sibling) {
874 p->parent = res;
875 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
876 p->name,
877 (unsigned long long)p->start,
878 (unsigned long long)p->end, res->name);
879 }
880 return 0;
881}
882
883/*
884 * Handle resources of PCI devices. If the world were perfect, we could
885 * just allocate all the resource regions and do nothing more. It isn't.
886 * On the other hand, we cannot just re-allocate all devices, as it would
887 * require us to know lots of host bridge internals. So we attempt to
888 * keep as much of the original configuration as possible, but tweak it
889 * when it's found to be wrong.
890 *
891 * Known BIOS problems we have to work around:
892 * - I/O or memory regions not configured
893 * - regions configured, but not enabled in the command register
894 * - bogus I/O addresses above 64K used
895 * - expansion ROMs left enabled (this may sound harmless, but given
896 * the fact the PCI specs explicitly allow address decoders to be
897 * shared between expansion ROMs and other resource regions, it's
898 * at least dangerous)
899 *
900 * Our solution:
901 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
902 * This gives us fixed barriers on where we can allocate.
903 * (2) Allocate resources for all enabled devices. If there is
904 * a collision, just mark the resource as unallocated. Also
905 * disable expansion ROMs during this step.
906 * (3) Try to allocate resources for disabled devices. If the
907 * resources were assigned correctly, everything goes well,
908 * if they weren't, they won't disturb allocation of other
909 * resources.
910 * (4) Assign new addresses to resources which were either
911 * not configured at all or misconfigured. If explicitly
912 * requested by the user, configure expansion ROM address
913 * as well.
914 */
915
916static void pcibios_allocate_bus_resources(struct pci_bus *bus)
917{
918 struct pci_bus *b;
919 int i;
920 struct resource *res, *pr;
921
922 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
923 pci_domain_nr(bus), bus->number);
924
925 pci_bus_for_each_resource(bus, res, i) {
926 if (!res || !res->flags
927 || res->start > res->end || res->parent)
928 continue;
929 if (bus->parent == NULL)
930 pr = (res->flags & IORESOURCE_IO) ?
931 &ioport_resource : &iomem_resource;
932 else {
933 /* Don't bother with non-root busses when
934 * re-assigning all resources. We clear the
935 * resource flags as if they were colliding
936 * and as such ensure proper re-allocation
937 * later.
938 */
939 pr = pci_find_parent_resource(bus->self, res);
940 if (pr == res) {
941 /* this happens when the generic PCI
942 * code (wrongly) decides that this
943 * bridge is transparent -- paulus
944 */
945 continue;
946 }
947 }
948
949 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
950 bus->self ? pci_name(bus->self) : "PHB",
951 bus->number, i,
952 (unsigned long long)res->start,
953 (unsigned long long)res->end);
954 pr_debug("[0x%x], parent %p (%s)\n",
955 (unsigned int)res->flags,
956 pr, (pr && pr->name) ? pr->name : "nil");
957
958 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
959 struct pci_dev *dev = bus->self;
960
961 if (request_resource(pr, res) == 0)
962 continue;
963 /*
964 * Must be a conflict with an existing entry.
965 * Move that entry (or entries) under the
966 * bridge resource and try again.
967 */
968 if (reparent_resources(pr, res) == 0)
969 continue;
970
971 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
972 pci_claim_bridge_resource(dev,
973 i + PCI_BRIDGE_RESOURCES) == 0)
974 continue;
975
976 }
977 pr_warn("PCI: Cannot allocate resource region ");
978 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
979 res->start = res->end = 0;
980 res->flags = 0;
981 }
982
983 list_for_each_entry(b, &bus->children, node)
984 pcibios_allocate_bus_resources(b);
985}
986
987static inline void alloc_resource(struct pci_dev *dev, int idx)
988{
989 struct resource *pr, *r = &dev->resource[idx];
990
991 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
992 pci_name(dev), idx,
993 (unsigned long long)r->start,
994 (unsigned long long)r->end,
995 (unsigned int)r->flags);
996
997 pr = pci_find_parent_resource(dev, r);
998 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
999 request_resource(pr, r) < 0) {
1000 pr_warn("PCI: Cannot allocate resource region %d ", idx);
1001 pr_cont("of device %s, will remap\n", pci_name(dev));
1002 if (pr)
1003 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1004 pr,
1005 (unsigned long long)pr->start,
1006 (unsigned long long)pr->end,
1007 (unsigned int)pr->flags);
1008 /* We'll assign a new address later */
1009 r->flags |= IORESOURCE_UNSET;
1010 r->end -= r->start;
1011 r->start = 0;
1012 }
1013}
1014
1015static void __init pcibios_allocate_resources(int pass)
1016{
1017 struct pci_dev *dev = NULL;
1018 int idx, disabled;
1019 u16 command;
1020 struct resource *r;
1021
1022 for_each_pci_dev(dev) {
1023 pci_read_config_word(dev, PCI_COMMAND, &command);
1024 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1025 r = &dev->resource[idx];
1026 if (r->parent) /* Already allocated */
1027 continue;
1028 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1029 continue; /* Not assigned at all */
1030 /* We only allocate ROMs on pass 1 just in case they
1031 * have been screwed up by firmware
1032 */
1033 if (idx == PCI_ROM_RESOURCE)
1034 disabled = 1;
1035 if (r->flags & IORESOURCE_IO)
1036 disabled = !(command & PCI_COMMAND_IO);
1037 else
1038 disabled = !(command & PCI_COMMAND_MEMORY);
1039 if (pass == disabled)
1040 alloc_resource(dev, idx);
1041 }
1042 if (pass)
1043 continue;
1044 r = &dev->resource[PCI_ROM_RESOURCE];
1045 if (r->flags) {
1046 /* Turn the ROM off, leave the resource region,
1047 * but keep it unregistered.
1048 */
1049 u32 reg;
1050 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1051 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1052 pr_debug("PCI: Switching off ROM of %s\n",
1053 pci_name(dev));
1054 r->flags &= ~IORESOURCE_ROM_ENABLE;
1055 pci_write_config_dword(dev, dev->rom_base_reg,
1056 reg & ~PCI_ROM_ADDRESS_ENABLE);
1057 }
1058 }
1059 }
1060}
1061
1062static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1063{
1064 struct pci_controller *hose = pci_bus_to_host(bus);
1065 resource_size_t offset;
1066 struct resource *res, *pres;
1067 int i;
1068
1069 pr_debug("Reserving legacy ranges for domain %04x\n",
1070 pci_domain_nr(bus));
1071
1072 /* Check for IO */
1073 if (!(hose->io_resource.flags & IORESOURCE_IO))
1074 goto no_io;
1075 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1076 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1077 BUG_ON(res == NULL);
1078 res->name = "Legacy IO";
1079 res->flags = IORESOURCE_IO;
1080 res->start = offset;
1081 res->end = (offset + 0xfff) & 0xfffffffful;
1082 pr_debug("Candidate legacy IO: %pR\n", res);
1083 if (request_resource(&hose->io_resource, res)) {
1084 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1085 pci_domain_nr(bus), bus->number, res);
1086 kfree(res);
1087 }
1088
1089 no_io:
1090 /* Check for memory */
1091 offset = hose->pci_mem_offset;
1092 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1093 for (i = 0; i < 3; i++) {
1094 pres = &hose->mem_resources[i];
1095 if (!(pres->flags & IORESOURCE_MEM))
1096 continue;
1097 pr_debug("hose mem res: %pR\n", pres);
1098 if ((pres->start - offset) <= 0xa0000 &&
1099 (pres->end - offset) >= 0xbffff)
1100 break;
1101 }
1102 if (i >= 3)
1103 return;
1104 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1105 BUG_ON(res == NULL);
1106 res->name = "Legacy VGA memory";
1107 res->flags = IORESOURCE_MEM;
1108 res->start = 0xa0000 + offset;
1109 res->end = 0xbffff + offset;
1110 pr_debug("Candidate VGA memory: %pR\n", res);
1111 if (request_resource(pres, res)) {
1112 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1113 pci_domain_nr(bus), bus->number, res);
1114 kfree(res);
1115 }
1116}
1117
1118void __init pcibios_resource_survey(void)
1119{
1120 struct pci_bus *b;
1121
1122 /* Allocate and assign resources. If we re-assign everything, then
1123 * we skip the allocate phase
1124 */
1125 list_for_each_entry(b, &pci_root_buses, node)
1126 pcibios_allocate_bus_resources(b);
1127
1128 pcibios_allocate_resources(0);
1129 pcibios_allocate_resources(1);
1130
1131 /* Before we start assigning unassigned resource, we try to reserve
1132 * the low IO area and the VGA memory area if they intersect the
1133 * bus available resources to avoid allocating things on top of them
1134 */
1135 list_for_each_entry(b, &pci_root_buses, node)
1136 pcibios_reserve_legacy_regions(b);
1137
1138 /* Now proceed to assigning things that were left unassigned */
1139 pr_debug("PCI: Assigning unassigned resources...\n");
1140 pci_assign_unassigned_resources();
1141}
1142
1143/* This is used by the PCI hotplug driver to allocate resource
1144 * of newly plugged busses. We can try to consolidate with the
1145 * rest of the code later, for now, keep it as-is as our main
1146 * resource allocation function doesn't deal with sub-trees yet.
1147 */
1148void pcibios_claim_one_bus(struct pci_bus *bus)
1149{
1150 struct pci_dev *dev;
1151 struct pci_bus *child_bus;
1152
1153 list_for_each_entry(dev, &bus->devices, bus_list) {
1154 int i;
1155
1156 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1157 struct resource *r = &dev->resource[i];
1158
1159 if (r->parent || !r->start || !r->flags)
1160 continue;
1161
1162 pr_debug("PCI: Claiming %s: ", pci_name(dev));
1163 pr_debug("Resource %d: %016llx..%016llx [%x]\n",
1164 i, (unsigned long long)r->start,
1165 (unsigned long long)r->end,
1166 (unsigned int)r->flags);
1167
1168 if (pci_claim_resource(dev, i) == 0)
1169 continue;
1170
1171 pci_claim_bridge_resource(dev, i);
1172 }
1173 }
1174
1175 list_for_each_entry(child_bus, &bus->children, node)
1176 pcibios_claim_one_bus(child_bus);
1177}
1178EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1179
1180
1181/* pcibios_finish_adding_to_bus
1182 *
1183 * This is to be called by the hotplug code after devices have been
1184 * added to a bus, this include calling it for a PHB that is just
1185 * being added
1186 */
1187void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1188{
1189 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1190 pci_domain_nr(bus), bus->number);
1191
1192 /* Allocate bus and devices resources */
1193 pcibios_allocate_bus_resources(bus);
1194 pcibios_claim_one_bus(bus);
1195
1196 /* Add new devices to global lists. Register in proc, sysfs. */
1197 pci_bus_add_devices(bus);
1198
1199 /* Fixup EEH */
1200 /* eeh_add_device_tree_late(bus); */
1201}
1202EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1203
1204static void pcibios_setup_phb_resources(struct pci_controller *hose,
1205 struct list_head *resources)
1206{
1207 unsigned long io_offset;
1208 struct resource *res;
1209 int i;
1210
1211 /* Hookup PHB IO resource */
1212 res = &hose->io_resource;
1213
1214 /* Fixup IO space offset */
1215 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1216 res->start = (res->start + io_offset) & 0xffffffffu;
1217 res->end = (res->end + io_offset) & 0xffffffffu;
1218
1219 if (!res->flags) {
1220 pr_warn("PCI: I/O resource not set for host ");
1221 pr_cont("bridge %s (domain %d)\n",
1222 hose->dn->full_name, hose->global_number);
1223 /* Workaround for lack of IO resource only on 32-bit */
1224 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1225 res->end = res->start + IO_SPACE_LIMIT;
1226 res->flags = IORESOURCE_IO;
1227 }
1228 pci_add_resource_offset(resources, res,
1229 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
1230
1231 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1232 (unsigned long long)res->start,
1233 (unsigned long long)res->end,
1234 (unsigned long)res->flags);
1235
1236 /* Hookup PHB Memory resources */
1237 for (i = 0; i < 3; ++i) {
1238 res = &hose->mem_resources[i];
1239 if (!res->flags) {
1240 if (i > 0)
1241 continue;
1242 pr_err("PCI: Memory resource 0 not set for ");
1243 pr_cont("host bridge %s (domain %d)\n",
1244 hose->dn->full_name, hose->global_number);
1245
1246 /* Workaround for lack of MEM resource only on 32-bit */
1247 res->start = hose->pci_mem_offset;
1248 res->end = (resource_size_t)-1LL;
1249 res->flags = IORESOURCE_MEM;
1250
1251 }
1252 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
1253
1254 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1255 i, (unsigned long long)res->start,
1256 (unsigned long long)res->end,
1257 (unsigned long)res->flags);
1258 }
1259
1260 pr_debug("PCI: PHB MEM offset = %016llx\n",
1261 (unsigned long long)hose->pci_mem_offset);
1262 pr_debug("PCI: PHB IO offset = %08lx\n",
1263 (unsigned long)hose->io_base_virt - _IO_BASE);
1264}
1265
1266static void pcibios_scan_phb(struct pci_controller *hose)
1267{
1268 LIST_HEAD(resources);
1269 struct pci_bus *bus;
1270 struct device_node *node = hose->dn;
1271
1272 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1273
1274 pcibios_setup_phb_resources(hose, &resources);
1275
1276 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
1277 hose->ops, hose, &resources);
1278 if (bus == NULL) {
1279 pr_err("Failed to create bus for PCI domain %04x\n",
1280 hose->global_number);
1281 pci_free_resource_list(&resources);
1282 return;
1283 }
1284 bus->busn_res.start = hose->first_busno;
1285 hose->bus = bus;
1286
1287 hose->last_busno = bus->busn_res.end;
1288}
1289
1290static int __init pcibios_init(void)
1291{
1292 struct pci_controller *hose, *tmp;
1293 int next_busno = 0;
1294
1295 pr_info("PCI: Probing PCI hardware\n");
1296
1297 /* Scan all of the recorded PCI controllers. */
1298 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1299 hose->last_busno = 0xff;
1300 pcibios_scan_phb(hose);
1301 if (next_busno <= hose->last_busno)
1302 next_busno = hose->last_busno + 1;
1303 }
1304 pci_bus_count = next_busno;
1305
1306 /* Call common code to handle resource allocation */
1307 pcibios_resource_survey();
1308 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1309 if (hose->bus)
1310 pci_bus_add_devices(hose->bus);
1311 }
1312
1313 return 0;
1314}
1315
1316subsys_initcall(pcibios_init);
1317
1318static struct pci_controller *pci_bus_to_hose(int bus)
1319{
1320 struct pci_controller *hose, *tmp;
1321
1322 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1323 if (bus >= hose->first_busno && bus <= hose->last_busno)
1324 return hose;
1325 return NULL;
1326}
1327
1328/* Provide information on locations of various I/O regions in physical
1329 * memory. Do this on a per-card basis so that we choose the right
1330 * root bridge.
1331 * Note that the returned IO or memory base is a physical address
1332 */
1333
1334long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1335{
1336 struct pci_controller *hose;
1337 long result = -EOPNOTSUPP;
1338
1339 hose = pci_bus_to_hose(bus);
1340 if (!hose)
1341 return -ENODEV;
1342
1343 switch (which) {
1344 case IOBASE_BRIDGE_NUMBER:
1345 return (long)hose->first_busno;
1346 case IOBASE_MEMORY:
1347 return (long)hose->pci_mem_offset;
1348 case IOBASE_IO:
1349 return (long)hose->io_base_phys;
1350 case IOBASE_ISA_IO:
1351 return (long)isa_io_base;
1352 case IOBASE_ISA_MEM:
1353 return (long)isa_mem_base;
1354 }
1355
1356 return result;
1357}
1358
1359/*
1360 * Null PCI config access functions, for the case when we can't
1361 * find a hose.
1362 */
1363#define NULL_PCI_OP(rw, size, type) \
1364static int \
1365null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1366{ \
1367 return PCIBIOS_DEVICE_NOT_FOUND; \
1368}
1369
1370static int
1371null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1372 int len, u32 *val)
1373{
1374 return PCIBIOS_DEVICE_NOT_FOUND;
1375}
1376
1377static int
1378null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1379 int len, u32 val)
1380{
1381 return PCIBIOS_DEVICE_NOT_FOUND;
1382}
1383
1384static struct pci_ops null_pci_ops = {
1385 .read = null_read_config,
1386 .write = null_write_config,
1387};
1388
1389/*
1390 * These functions are used early on before PCI scanning is done
1391 * and all of the pci_dev and pci_bus structures have been created.
1392 */
1393static struct pci_bus *
1394fake_pci_bus(struct pci_controller *hose, int busnr)
1395{
1396 static struct pci_bus bus;
1397
1398 if (!hose)
1399 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1400
1401 bus.number = busnr;
1402 bus.sysdata = hose;
1403 bus.ops = hose ? hose->ops : &null_pci_ops;
1404 return &bus;
1405}
1406
1407#define EARLY_PCI_OP(rw, size, type) \
1408int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1409 int devfn, int offset, type value) \
1410{ \
1411 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1412 devfn, offset, value); \
1413}
1414
1415EARLY_PCI_OP(read, byte, u8 *)
1416EARLY_PCI_OP(read, word, u16 *)
1417EARLY_PCI_OP(read, dword, u32 *)
1418EARLY_PCI_OP(write, byte, u8)
1419EARLY_PCI_OP(write, word, u16)
1420EARLY_PCI_OP(write, dword, u32)
1421
1422int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1423 int cap)
1424{
1425 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1426}
1427