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1/*
2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
4 *
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
7 *
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
10 *
11 * Common pmac/prep/chrp pci routines. -- Cort
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/bootmem.h>
24#include <linux/mm.h>
25#include <linux/shmem_fs.h>
26#include <linux/list.h>
27#include <linux/syscalls.h>
28#include <linux/irq.h>
29#include <linux/vmalloc.h>
30#include <linux/slab.h>
31#include <linux/of.h>
32#include <linux/of_address.h>
33#include <linux/of_irq.h>
34#include <linux/of_pci.h>
35#include <linux/export.h>
36
37#include <asm/processor.h>
38#include <linux/io.h>
39#include <asm/pci-bridge.h>
40#include <asm/byteorder.h>
41
42static DEFINE_SPINLOCK(hose_spinlock);
43LIST_HEAD(hose_list);
44
45/* XXX kill that some day ... */
46static int global_phb_number; /* Global phb counter */
47
48/* ISA Memory physical address */
49resource_size_t isa_mem_base;
50
51unsigned long isa_io_base;
52EXPORT_SYMBOL(isa_io_base);
53
54static int pci_bus_count;
55
56struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
57{
58 struct pci_controller *phb;
59
60 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
61 if (!phb)
62 return NULL;
63 spin_lock(&hose_spinlock);
64 phb->global_number = global_phb_number++;
65 list_add_tail(&phb->list_node, &hose_list);
66 spin_unlock(&hose_spinlock);
67 phb->dn = dev;
68 phb->is_dynamic = mem_init_done;
69 return phb;
70}
71
72void pcibios_free_controller(struct pci_controller *phb)
73{
74 spin_lock(&hose_spinlock);
75 list_del(&phb->list_node);
76 spin_unlock(&hose_spinlock);
77
78 if (phb->is_dynamic)
79 kfree(phb);
80}
81
82static resource_size_t pcibios_io_size(const struct pci_controller *hose)
83{
84 return resource_size(&hose->io_resource);
85}
86
87int pcibios_vaddr_is_ioport(void __iomem *address)
88{
89 int ret = 0;
90 struct pci_controller *hose;
91 resource_size_t size;
92
93 spin_lock(&hose_spinlock);
94 list_for_each_entry(hose, &hose_list, list_node) {
95 size = pcibios_io_size(hose);
96 if (address >= hose->io_base_virt &&
97 address < (hose->io_base_virt + size)) {
98 ret = 1;
99 break;
100 }
101 }
102 spin_unlock(&hose_spinlock);
103 return ret;
104}
105
106unsigned long pci_address_to_pio(phys_addr_t address)
107{
108 struct pci_controller *hose;
109 resource_size_t size;
110 unsigned long ret = ~0;
111
112 spin_lock(&hose_spinlock);
113 list_for_each_entry(hose, &hose_list, list_node) {
114 size = pcibios_io_size(hose);
115 if (address >= hose->io_base_phys &&
116 address < (hose->io_base_phys + size)) {
117 unsigned long base =
118 (unsigned long)hose->io_base_virt - _IO_BASE;
119 ret = base + (address - hose->io_base_phys);
120 break;
121 }
122 }
123 spin_unlock(&hose_spinlock);
124
125 return ret;
126}
127EXPORT_SYMBOL_GPL(pci_address_to_pio);
128
129/* This routine is meant to be used early during boot, when the
130 * PCI bus numbers have not yet been assigned, and you need to
131 * issue PCI config cycles to an OF device.
132 * It could also be used to "fix" RTAS config cycles if you want
133 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
134 * config cycles.
135 */
136struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
137{
138 while (node) {
139 struct pci_controller *hose, *tmp;
140 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
141 if (hose->dn == node)
142 return hose;
143 node = node->parent;
144 }
145 return NULL;
146}
147
148void pcibios_set_master(struct pci_dev *dev)
149{
150 /* No special bus mastering setup handling */
151}
152
153/*
154 * Platform support for /proc/bus/pci/X/Y mmap()s.
155 */
156
157int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
158{
159 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
160 resource_size_t ioaddr = pci_resource_start(pdev, bar);
161
162 if (!hose)
163 return -EINVAL; /* should never happen */
164
165 /* Convert to an offset within this PCI controller */
166 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
167
168 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
169 return 0;
170}
171
172/*
173 * This one is used by /dev/mem and fbdev who have no clue about the
174 * PCI device, it tries to find the PCI device first and calls the
175 * above routine
176 */
177pgprot_t pci_phys_mem_access_prot(struct file *file,
178 unsigned long pfn,
179 unsigned long size,
180 pgprot_t prot)
181{
182 struct pci_dev *pdev = NULL;
183 struct resource *found = NULL;
184 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
185 int i;
186
187 if (page_is_ram(pfn))
188 return prot;
189
190 prot = pgprot_noncached(prot);
191 for_each_pci_dev(pdev) {
192 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
193 struct resource *rp = &pdev->resource[i];
194 int flags = rp->flags;
195
196 /* Active and same type? */
197 if ((flags & IORESOURCE_MEM) == 0)
198 continue;
199 /* In the range of this resource? */
200 if (offset < (rp->start & PAGE_MASK) ||
201 offset > rp->end)
202 continue;
203 found = rp;
204 break;
205 }
206 if (found)
207 break;
208 }
209 if (found) {
210 if (found->flags & IORESOURCE_PREFETCH)
211 prot = pgprot_noncached_wc(prot);
212 pci_dev_put(pdev);
213 }
214
215 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
216 (unsigned long long)offset, pgprot_val(prot));
217
218 return prot;
219}
220
221/* This provides legacy IO read access on a bus */
222int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
223{
224 unsigned long offset;
225 struct pci_controller *hose = pci_bus_to_host(bus);
226 struct resource *rp = &hose->io_resource;
227 void __iomem *addr;
228
229 /* Check if port can be supported by that bus. We only check
230 * the ranges of the PHB though, not the bus itself as the rules
231 * for forwarding legacy cycles down bridges are not our problem
232 * here. So if the host bridge supports it, we do it.
233 */
234 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
235 offset += port;
236
237 if (!(rp->flags & IORESOURCE_IO))
238 return -ENXIO;
239 if (offset < rp->start || (offset + size) > rp->end)
240 return -ENXIO;
241 addr = hose->io_base_virt + port;
242
243 switch (size) {
244 case 1:
245 *((u8 *)val) = in_8(addr);
246 return 1;
247 case 2:
248 if (port & 1)
249 return -EINVAL;
250 *((u16 *)val) = in_le16(addr);
251 return 2;
252 case 4:
253 if (port & 3)
254 return -EINVAL;
255 *((u32 *)val) = in_le32(addr);
256 return 4;
257 }
258 return -EINVAL;
259}
260
261/* This provides legacy IO write access on a bus */
262int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
263{
264 unsigned long offset;
265 struct pci_controller *hose = pci_bus_to_host(bus);
266 struct resource *rp = &hose->io_resource;
267 void __iomem *addr;
268
269 /* Check if port can be supported by that bus. We only check
270 * the ranges of the PHB though, not the bus itself as the rules
271 * for forwarding legacy cycles down bridges are not our problem
272 * here. So if the host bridge supports it, we do it.
273 */
274 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
275 offset += port;
276
277 if (!(rp->flags & IORESOURCE_IO))
278 return -ENXIO;
279 if (offset < rp->start || (offset + size) > rp->end)
280 return -ENXIO;
281 addr = hose->io_base_virt + port;
282
283 /* WARNING: The generic code is idiotic. It gets passed a pointer
284 * to what can be a 1, 2 or 4 byte quantity and always reads that
285 * as a u32, which means that we have to correct the location of
286 * the data read within those 32 bits for size 1 and 2
287 */
288 switch (size) {
289 case 1:
290 out_8(addr, val >> 24);
291 return 1;
292 case 2:
293 if (port & 1)
294 return -EINVAL;
295 out_le16(addr, val >> 16);
296 return 2;
297 case 4:
298 if (port & 3)
299 return -EINVAL;
300 out_le32(addr, val);
301 return 4;
302 }
303 return -EINVAL;
304}
305
306/* This provides legacy IO or memory mmap access on a bus */
307int pci_mmap_legacy_page_range(struct pci_bus *bus,
308 struct vm_area_struct *vma,
309 enum pci_mmap_state mmap_state)
310{
311 struct pci_controller *hose = pci_bus_to_host(bus);
312 resource_size_t offset =
313 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
314 resource_size_t size = vma->vm_end - vma->vm_start;
315 struct resource *rp;
316
317 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
318 pci_domain_nr(bus), bus->number,
319 mmap_state == pci_mmap_mem ? "MEM" : "IO",
320 (unsigned long long)offset,
321 (unsigned long long)(offset + size - 1));
322
323 if (mmap_state == pci_mmap_mem) {
324 /* Hack alert !
325 *
326 * Because X is lame and can fail starting if it gets an error
327 * trying to mmap legacy_mem (instead of just moving on without
328 * legacy memory access) we fake it here by giving it anonymous
329 * memory, effectively behaving just like /dev/zero
330 */
331 if ((offset + size) > hose->isa_mem_size) {
332#ifdef CONFIG_MMU
333 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
334 current->comm, current->pid);
335 pr_debug("legacy memory for 0%04x:%02x\n",
336 pci_domain_nr(bus), bus->number);
337#endif
338 if (vma->vm_flags & VM_SHARED)
339 return shmem_zero_setup(vma);
340 return 0;
341 }
342 offset += hose->isa_mem_phys;
343 } else {
344 unsigned long io_offset = (unsigned long)hose->io_base_virt -
345 _IO_BASE;
346 unsigned long roffset = offset + io_offset;
347 rp = &hose->io_resource;
348 if (!(rp->flags & IORESOURCE_IO))
349 return -ENXIO;
350 if (roffset < rp->start || (roffset + size) > rp->end)
351 return -ENXIO;
352 offset += hose->io_base_phys;
353 }
354 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
355
356 vma->vm_pgoff = offset >> PAGE_SHIFT;
357 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
358 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
359 vma->vm_end - vma->vm_start,
360 vma->vm_page_prot);
361}
362
363void pci_resource_to_user(const struct pci_dev *dev, int bar,
364 const struct resource *rsrc,
365 resource_size_t *start, resource_size_t *end)
366{
367 struct pci_bus_region region;
368
369 if (rsrc->flags & IORESOURCE_IO) {
370 pcibios_resource_to_bus(dev->bus, ®ion,
371 (struct resource *) rsrc);
372 *start = region.start;
373 *end = region.end;
374 return;
375 }
376
377 /* We pass a CPU physical address to userland for MMIO instead of a
378 * BAR value because X is lame and expects to be able to use that
379 * to pass to /dev/mem!
380 *
381 * That means we may have 64-bit values where some apps only expect
382 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
383 */
384 *start = rsrc->start;
385 *end = rsrc->end;
386}
387
388/**
389 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
390 * @hose: newly allocated pci_controller to be setup
391 * @dev: device node of the host bridge
392 * @primary: set if primary bus (32 bits only, soon to be deprecated)
393 *
394 * This function will parse the "ranges" property of a PCI host bridge device
395 * node and setup the resource mapping of a pci controller based on its
396 * content.
397 *
398 * Life would be boring if it wasn't for a few issues that we have to deal
399 * with here:
400 *
401 * - We can only cope with one IO space range and up to 3 Memory space
402 * ranges. However, some machines (thanks Apple !) tend to split their
403 * space into lots of small contiguous ranges. So we have to coalesce.
404 *
405 * - We can only cope with all memory ranges having the same offset
406 * between CPU addresses and PCI addresses. Unfortunately, some bridges
407 * are setup for a large 1:1 mapping along with a small "window" which
408 * maps PCI address 0 to some arbitrary high address of the CPU space in
409 * order to give access to the ISA memory hole.
410 * The way out of here that I've chosen for now is to always set the
411 * offset based on the first resource found, then override it if we
412 * have a different offset and the previous was set by an ISA hole.
413 *
414 * - Some busses have IO space not starting at 0, which causes trouble with
415 * the way we do our IO resource renumbering. The code somewhat deals with
416 * it for 64 bits but I would expect problems on 32 bits.
417 *
418 * - Some 32 bits platforms such as 4xx can have physical space larger than
419 * 32 bits so we need to use 64 bits values for the parsing
420 */
421void pci_process_bridge_OF_ranges(struct pci_controller *hose,
422 struct device_node *dev, int primary)
423{
424 int memno = 0, isa_hole = -1;
425 unsigned long long isa_mb = 0;
426 struct resource *res;
427 struct of_pci_range range;
428 struct of_pci_range_parser parser;
429
430 pr_info("PCI host bridge %pOF %s ranges:\n",
431 dev, primary ? "(primary)" : "");
432
433 /* Check for ranges property */
434 if (of_pci_range_parser_init(&parser, dev))
435 return;
436
437 pr_debug("Parsing ranges property...\n");
438 for_each_of_pci_range(&parser, &range) {
439 /* Read next ranges element */
440 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
441 range.pci_space, range.pci_addr);
442 pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
443 range.cpu_addr, range.size);
444
445 /* If we failed translation or got a zero-sized region
446 * (some FW try to feed us with non sensical zero sized regions
447 * such as power3 which look like some kind of attempt
448 * at exposing the VGA memory hole)
449 */
450 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
451 continue;
452
453 /* Act based on address space type */
454 res = NULL;
455 switch (range.flags & IORESOURCE_TYPE_BITS) {
456 case IORESOURCE_IO:
457 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
458 range.cpu_addr, range.cpu_addr + range.size - 1,
459 range.pci_addr);
460
461 /* We support only one IO range */
462 if (hose->pci_io_size) {
463 pr_info(" \\--> Skipped (too many) !\n");
464 continue;
465 }
466 /* On 32 bits, limit I/O space to 16MB */
467 if (range.size > 0x01000000)
468 range.size = 0x01000000;
469
470 /* 32 bits needs to map IOs here */
471 hose->io_base_virt = ioremap(range.cpu_addr,
472 range.size);
473
474 /* Expect trouble if pci_addr is not 0 */
475 if (primary)
476 isa_io_base =
477 (unsigned long)hose->io_base_virt;
478 /* pci_io_size and io_base_phys always represent IO
479 * space starting at 0 so we factor in pci_addr
480 */
481 hose->pci_io_size = range.pci_addr + range.size;
482 hose->io_base_phys = range.cpu_addr - range.pci_addr;
483
484 /* Build resource */
485 res = &hose->io_resource;
486 range.cpu_addr = range.pci_addr;
487
488 break;
489 case IORESOURCE_MEM:
490 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
491 range.cpu_addr, range.cpu_addr + range.size - 1,
492 range.pci_addr,
493 (range.pci_space & 0x40000000) ?
494 "Prefetch" : "");
495
496 /* We support only 3 memory ranges */
497 if (memno >= 3) {
498 pr_info(" \\--> Skipped (too many) !\n");
499 continue;
500 }
501 /* Handles ISA memory hole space here */
502 if (range.pci_addr == 0) {
503 isa_mb = range.cpu_addr;
504 isa_hole = memno;
505 if (primary || isa_mem_base == 0)
506 isa_mem_base = range.cpu_addr;
507 hose->isa_mem_phys = range.cpu_addr;
508 hose->isa_mem_size = range.size;
509 }
510
511 /* We get the PCI/Mem offset from the first range or
512 * the, current one if the offset came from an ISA
513 * hole. If they don't match, bugger.
514 */
515 if (memno == 0 ||
516 (isa_hole >= 0 && range.pci_addr != 0 &&
517 hose->pci_mem_offset == isa_mb))
518 hose->pci_mem_offset = range.cpu_addr -
519 range.pci_addr;
520 else if (range.pci_addr != 0 &&
521 hose->pci_mem_offset != range.cpu_addr -
522 range.pci_addr) {
523 pr_info(" \\--> Skipped (offset mismatch) !\n");
524 continue;
525 }
526
527 /* Build resource */
528 res = &hose->mem_resources[memno++];
529 break;
530 }
531 if (res != NULL) {
532 res->name = dev->full_name;
533 res->flags = range.flags;
534 res->start = range.cpu_addr;
535 res->end = range.cpu_addr + range.size - 1;
536 res->parent = res->child = res->sibling = NULL;
537 }
538 }
539
540 /* If there's an ISA hole and the pci_mem_offset is -not- matching
541 * the ISA hole offset, then we need to remove the ISA hole from
542 * the resource list for that brige
543 */
544 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
545 unsigned int next = isa_hole + 1;
546 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
547 if (next < memno)
548 memmove(&hose->mem_resources[isa_hole],
549 &hose->mem_resources[next],
550 sizeof(struct resource) * (memno - next));
551 hose->mem_resources[--memno].flags = 0;
552 }
553}
554
555/* Display the domain number in /proc */
556int pci_proc_domain(struct pci_bus *bus)
557{
558 return pci_domain_nr(bus);
559}
560
561/* This header fixup will do the resource fixup for all devices as they are
562 * probed, but not for bridge ranges
563 */
564static void pcibios_fixup_resources(struct pci_dev *dev)
565{
566 struct pci_controller *hose = pci_bus_to_host(dev->bus);
567 int i;
568
569 if (!hose) {
570 pr_err("No host bridge for PCI dev %s !\n",
571 pci_name(dev));
572 return;
573 }
574 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
575 struct resource *res = dev->resource + i;
576 if (!res->flags)
577 continue;
578 if (res->start == 0) {
579 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
580 pci_name(dev), i,
581 (unsigned long long)res->start,
582 (unsigned long long)res->end,
583 (unsigned int)res->flags);
584 pr_debug("is unassigned\n");
585 res->end -= res->start;
586 res->start = 0;
587 res->flags |= IORESOURCE_UNSET;
588 continue;
589 }
590
591 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
592 pci_name(dev), i,
593 (unsigned long long)res->start,
594 (unsigned long long)res->end,
595 (unsigned int)res->flags);
596 }
597}
598DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
599
600/*
601 * We need to avoid collisions with `mirrored' VGA ports
602 * and other strange ISA hardware, so we always want the
603 * addresses to be allocated in the 0x000-0x0ff region
604 * modulo 0x400.
605 *
606 * Why? Because some silly external IO cards only decode
607 * the low 10 bits of the IO address. The 0x00-0xff region
608 * is reserved for motherboard devices that decode all 16
609 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
610 * but we want to try to avoid allocating at 0x2900-0x2bff
611 * which might have be mirrored at 0x0100-0x03ff..
612 */
613int pcibios_add_device(struct pci_dev *dev)
614{
615 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
616
617 return 0;
618}
619EXPORT_SYMBOL(pcibios_add_device);
620
621/*
622 * Reparent resource children of pr that conflict with res
623 * under res, and make res replace those children.
624 */
625static int __init reparent_resources(struct resource *parent,
626 struct resource *res)
627{
628 struct resource *p, **pp;
629 struct resource **firstpp = NULL;
630
631 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
632 if (p->end < res->start)
633 continue;
634 if (res->end < p->start)
635 break;
636 if (p->start < res->start || p->end > res->end)
637 return -1; /* not completely contained */
638 if (firstpp == NULL)
639 firstpp = pp;
640 }
641 if (firstpp == NULL)
642 return -1; /* didn't find any conflicting entries? */
643 res->parent = parent;
644 res->child = *firstpp;
645 res->sibling = *pp;
646 *firstpp = res;
647 *pp = NULL;
648 for (p = res->child; p != NULL; p = p->sibling) {
649 p->parent = res;
650 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
651 p->name,
652 (unsigned long long)p->start,
653 (unsigned long long)p->end, res->name);
654 }
655 return 0;
656}
657
658/*
659 * Handle resources of PCI devices. If the world were perfect, we could
660 * just allocate all the resource regions and do nothing more. It isn't.
661 * On the other hand, we cannot just re-allocate all devices, as it would
662 * require us to know lots of host bridge internals. So we attempt to
663 * keep as much of the original configuration as possible, but tweak it
664 * when it's found to be wrong.
665 *
666 * Known BIOS problems we have to work around:
667 * - I/O or memory regions not configured
668 * - regions configured, but not enabled in the command register
669 * - bogus I/O addresses above 64K used
670 * - expansion ROMs left enabled (this may sound harmless, but given
671 * the fact the PCI specs explicitly allow address decoders to be
672 * shared between expansion ROMs and other resource regions, it's
673 * at least dangerous)
674 *
675 * Our solution:
676 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
677 * This gives us fixed barriers on where we can allocate.
678 * (2) Allocate resources for all enabled devices. If there is
679 * a collision, just mark the resource as unallocated. Also
680 * disable expansion ROMs during this step.
681 * (3) Try to allocate resources for disabled devices. If the
682 * resources were assigned correctly, everything goes well,
683 * if they weren't, they won't disturb allocation of other
684 * resources.
685 * (4) Assign new addresses to resources which were either
686 * not configured at all or misconfigured. If explicitly
687 * requested by the user, configure expansion ROM address
688 * as well.
689 */
690
691static void pcibios_allocate_bus_resources(struct pci_bus *bus)
692{
693 struct pci_bus *b;
694 int i;
695 struct resource *res, *pr;
696
697 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
698 pci_domain_nr(bus), bus->number);
699
700 pci_bus_for_each_resource(bus, res, i) {
701 if (!res || !res->flags
702 || res->start > res->end || res->parent)
703 continue;
704 if (bus->parent == NULL)
705 pr = (res->flags & IORESOURCE_IO) ?
706 &ioport_resource : &iomem_resource;
707 else {
708 /* Don't bother with non-root busses when
709 * re-assigning all resources. We clear the
710 * resource flags as if they were colliding
711 * and as such ensure proper re-allocation
712 * later.
713 */
714 pr = pci_find_parent_resource(bus->self, res);
715 if (pr == res) {
716 /* this happens when the generic PCI
717 * code (wrongly) decides that this
718 * bridge is transparent -- paulus
719 */
720 continue;
721 }
722 }
723
724 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
725 bus->self ? pci_name(bus->self) : "PHB",
726 bus->number, i,
727 (unsigned long long)res->start,
728 (unsigned long long)res->end);
729 pr_debug("[0x%x], parent %p (%s)\n",
730 (unsigned int)res->flags,
731 pr, (pr && pr->name) ? pr->name : "nil");
732
733 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
734 struct pci_dev *dev = bus->self;
735
736 if (request_resource(pr, res) == 0)
737 continue;
738 /*
739 * Must be a conflict with an existing entry.
740 * Move that entry (or entries) under the
741 * bridge resource and try again.
742 */
743 if (reparent_resources(pr, res) == 0)
744 continue;
745
746 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
747 pci_claim_bridge_resource(dev,
748 i + PCI_BRIDGE_RESOURCES) == 0)
749 continue;
750
751 }
752 pr_warn("PCI: Cannot allocate resource region ");
753 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
754 res->start = res->end = 0;
755 res->flags = 0;
756 }
757
758 list_for_each_entry(b, &bus->children, node)
759 pcibios_allocate_bus_resources(b);
760}
761
762static inline void alloc_resource(struct pci_dev *dev, int idx)
763{
764 struct resource *pr, *r = &dev->resource[idx];
765
766 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
767 pci_name(dev), idx,
768 (unsigned long long)r->start,
769 (unsigned long long)r->end,
770 (unsigned int)r->flags);
771
772 pr = pci_find_parent_resource(dev, r);
773 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
774 request_resource(pr, r) < 0) {
775 pr_warn("PCI: Cannot allocate resource region %d ", idx);
776 pr_cont("of device %s, will remap\n", pci_name(dev));
777 if (pr)
778 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
779 pr,
780 (unsigned long long)pr->start,
781 (unsigned long long)pr->end,
782 (unsigned int)pr->flags);
783 /* We'll assign a new address later */
784 r->flags |= IORESOURCE_UNSET;
785 r->end -= r->start;
786 r->start = 0;
787 }
788}
789
790static void __init pcibios_allocate_resources(int pass)
791{
792 struct pci_dev *dev = NULL;
793 int idx, disabled;
794 u16 command;
795 struct resource *r;
796
797 for_each_pci_dev(dev) {
798 pci_read_config_word(dev, PCI_COMMAND, &command);
799 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
800 r = &dev->resource[idx];
801 if (r->parent) /* Already allocated */
802 continue;
803 if (!r->flags || (r->flags & IORESOURCE_UNSET))
804 continue; /* Not assigned at all */
805 /* We only allocate ROMs on pass 1 just in case they
806 * have been screwed up by firmware
807 */
808 if (idx == PCI_ROM_RESOURCE)
809 disabled = 1;
810 if (r->flags & IORESOURCE_IO)
811 disabled = !(command & PCI_COMMAND_IO);
812 else
813 disabled = !(command & PCI_COMMAND_MEMORY);
814 if (pass == disabled)
815 alloc_resource(dev, idx);
816 }
817 if (pass)
818 continue;
819 r = &dev->resource[PCI_ROM_RESOURCE];
820 if (r->flags) {
821 /* Turn the ROM off, leave the resource region,
822 * but keep it unregistered.
823 */
824 u32 reg;
825 pci_read_config_dword(dev, dev->rom_base_reg, ®);
826 if (reg & PCI_ROM_ADDRESS_ENABLE) {
827 pr_debug("PCI: Switching off ROM of %s\n",
828 pci_name(dev));
829 r->flags &= ~IORESOURCE_ROM_ENABLE;
830 pci_write_config_dword(dev, dev->rom_base_reg,
831 reg & ~PCI_ROM_ADDRESS_ENABLE);
832 }
833 }
834 }
835}
836
837static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
838{
839 struct pci_controller *hose = pci_bus_to_host(bus);
840 resource_size_t offset;
841 struct resource *res, *pres;
842 int i;
843
844 pr_debug("Reserving legacy ranges for domain %04x\n",
845 pci_domain_nr(bus));
846
847 /* Check for IO */
848 if (!(hose->io_resource.flags & IORESOURCE_IO))
849 goto no_io;
850 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
851 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
852 BUG_ON(res == NULL);
853 res->name = "Legacy IO";
854 res->flags = IORESOURCE_IO;
855 res->start = offset;
856 res->end = (offset + 0xfff) & 0xfffffffful;
857 pr_debug("Candidate legacy IO: %pR\n", res);
858 if (request_resource(&hose->io_resource, res)) {
859 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
860 pci_domain_nr(bus), bus->number, res);
861 kfree(res);
862 }
863
864 no_io:
865 /* Check for memory */
866 offset = hose->pci_mem_offset;
867 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
868 for (i = 0; i < 3; i++) {
869 pres = &hose->mem_resources[i];
870 if (!(pres->flags & IORESOURCE_MEM))
871 continue;
872 pr_debug("hose mem res: %pR\n", pres);
873 if ((pres->start - offset) <= 0xa0000 &&
874 (pres->end - offset) >= 0xbffff)
875 break;
876 }
877 if (i >= 3)
878 return;
879 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
880 BUG_ON(res == NULL);
881 res->name = "Legacy VGA memory";
882 res->flags = IORESOURCE_MEM;
883 res->start = 0xa0000 + offset;
884 res->end = 0xbffff + offset;
885 pr_debug("Candidate VGA memory: %pR\n", res);
886 if (request_resource(pres, res)) {
887 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
888 pci_domain_nr(bus), bus->number, res);
889 kfree(res);
890 }
891}
892
893void __init pcibios_resource_survey(void)
894{
895 struct pci_bus *b;
896
897 /* Allocate and assign resources. If we re-assign everything, then
898 * we skip the allocate phase
899 */
900 list_for_each_entry(b, &pci_root_buses, node)
901 pcibios_allocate_bus_resources(b);
902
903 pcibios_allocate_resources(0);
904 pcibios_allocate_resources(1);
905
906 /* Before we start assigning unassigned resource, we try to reserve
907 * the low IO area and the VGA memory area if they intersect the
908 * bus available resources to avoid allocating things on top of them
909 */
910 list_for_each_entry(b, &pci_root_buses, node)
911 pcibios_reserve_legacy_regions(b);
912
913 /* Now proceed to assigning things that were left unassigned */
914 pr_debug("PCI: Assigning unassigned resources...\n");
915 pci_assign_unassigned_resources();
916}
917
918/* This is used by the PCI hotplug driver to allocate resource
919 * of newly plugged busses. We can try to consolidate with the
920 * rest of the code later, for now, keep it as-is as our main
921 * resource allocation function doesn't deal with sub-trees yet.
922 */
923void pcibios_claim_one_bus(struct pci_bus *bus)
924{
925 struct pci_dev *dev;
926 struct pci_bus *child_bus;
927
928 list_for_each_entry(dev, &bus->devices, bus_list) {
929 int i;
930
931 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
932 struct resource *r = &dev->resource[i];
933
934 if (r->parent || !r->start || !r->flags)
935 continue;
936
937 pr_debug("PCI: Claiming %s: ", pci_name(dev));
938 pr_debug("Resource %d: %016llx..%016llx [%x]\n",
939 i, (unsigned long long)r->start,
940 (unsigned long long)r->end,
941 (unsigned int)r->flags);
942
943 if (pci_claim_resource(dev, i) == 0)
944 continue;
945
946 pci_claim_bridge_resource(dev, i);
947 }
948 }
949
950 list_for_each_entry(child_bus, &bus->children, node)
951 pcibios_claim_one_bus(child_bus);
952}
953EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
954
955
956/* pcibios_finish_adding_to_bus
957 *
958 * This is to be called by the hotplug code after devices have been
959 * added to a bus, this include calling it for a PHB that is just
960 * being added
961 */
962void pcibios_finish_adding_to_bus(struct pci_bus *bus)
963{
964 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
965 pci_domain_nr(bus), bus->number);
966
967 /* Allocate bus and devices resources */
968 pcibios_allocate_bus_resources(bus);
969 pcibios_claim_one_bus(bus);
970
971 /* Add new devices to global lists. Register in proc, sysfs. */
972 pci_bus_add_devices(bus);
973
974 /* Fixup EEH */
975 /* eeh_add_device_tree_late(bus); */
976}
977EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
978
979static void pcibios_setup_phb_resources(struct pci_controller *hose,
980 struct list_head *resources)
981{
982 unsigned long io_offset;
983 struct resource *res;
984 int i;
985
986 /* Hookup PHB IO resource */
987 res = &hose->io_resource;
988
989 /* Fixup IO space offset */
990 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
991 res->start = (res->start + io_offset) & 0xffffffffu;
992 res->end = (res->end + io_offset) & 0xffffffffu;
993
994 if (!res->flags) {
995 pr_warn("PCI: I/O resource not set for host ");
996 pr_cont("bridge %pOF (domain %d)\n",
997 hose->dn, hose->global_number);
998 /* Workaround for lack of IO resource only on 32-bit */
999 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1000 res->end = res->start + IO_SPACE_LIMIT;
1001 res->flags = IORESOURCE_IO;
1002 }
1003 pci_add_resource_offset(resources, res,
1004 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
1005
1006 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1007 (unsigned long long)res->start,
1008 (unsigned long long)res->end,
1009 (unsigned long)res->flags);
1010
1011 /* Hookup PHB Memory resources */
1012 for (i = 0; i < 3; ++i) {
1013 res = &hose->mem_resources[i];
1014 if (!res->flags) {
1015 if (i > 0)
1016 continue;
1017 pr_err("PCI: Memory resource 0 not set for ");
1018 pr_cont("host bridge %pOF (domain %d)\n",
1019 hose->dn, hose->global_number);
1020
1021 /* Workaround for lack of MEM resource only on 32-bit */
1022 res->start = hose->pci_mem_offset;
1023 res->end = (resource_size_t)-1LL;
1024 res->flags = IORESOURCE_MEM;
1025
1026 }
1027 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
1028
1029 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1030 i, (unsigned long long)res->start,
1031 (unsigned long long)res->end,
1032 (unsigned long)res->flags);
1033 }
1034
1035 pr_debug("PCI: PHB MEM offset = %016llx\n",
1036 (unsigned long long)hose->pci_mem_offset);
1037 pr_debug("PCI: PHB IO offset = %08lx\n",
1038 (unsigned long)hose->io_base_virt - _IO_BASE);
1039}
1040
1041static void pcibios_scan_phb(struct pci_controller *hose)
1042{
1043 LIST_HEAD(resources);
1044 struct pci_bus *bus;
1045 struct device_node *node = hose->dn;
1046
1047 pr_debug("PCI: Scanning PHB %pOF\n", node);
1048
1049 pcibios_setup_phb_resources(hose, &resources);
1050
1051 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
1052 hose->ops, hose, &resources);
1053 if (bus == NULL) {
1054 pr_err("Failed to create bus for PCI domain %04x\n",
1055 hose->global_number);
1056 pci_free_resource_list(&resources);
1057 return;
1058 }
1059 bus->busn_res.start = hose->first_busno;
1060 hose->bus = bus;
1061
1062 hose->last_busno = bus->busn_res.end;
1063}
1064
1065static int __init pcibios_init(void)
1066{
1067 struct pci_controller *hose, *tmp;
1068 int next_busno = 0;
1069
1070 pr_info("PCI: Probing PCI hardware\n");
1071
1072 /* Scan all of the recorded PCI controllers. */
1073 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1074 hose->last_busno = 0xff;
1075 pcibios_scan_phb(hose);
1076 if (next_busno <= hose->last_busno)
1077 next_busno = hose->last_busno + 1;
1078 }
1079 pci_bus_count = next_busno;
1080
1081 /* Call common code to handle resource allocation */
1082 pcibios_resource_survey();
1083 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1084 if (hose->bus)
1085 pci_bus_add_devices(hose->bus);
1086 }
1087
1088 return 0;
1089}
1090
1091subsys_initcall(pcibios_init);
1092
1093static struct pci_controller *pci_bus_to_hose(int bus)
1094{
1095 struct pci_controller *hose, *tmp;
1096
1097 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1098 if (bus >= hose->first_busno && bus <= hose->last_busno)
1099 return hose;
1100 return NULL;
1101}
1102
1103/* Provide information on locations of various I/O regions in physical
1104 * memory. Do this on a per-card basis so that we choose the right
1105 * root bridge.
1106 * Note that the returned IO or memory base is a physical address
1107 */
1108
1109long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1110{
1111 struct pci_controller *hose;
1112 long result = -EOPNOTSUPP;
1113
1114 hose = pci_bus_to_hose(bus);
1115 if (!hose)
1116 return -ENODEV;
1117
1118 switch (which) {
1119 case IOBASE_BRIDGE_NUMBER:
1120 return (long)hose->first_busno;
1121 case IOBASE_MEMORY:
1122 return (long)hose->pci_mem_offset;
1123 case IOBASE_IO:
1124 return (long)hose->io_base_phys;
1125 case IOBASE_ISA_IO:
1126 return (long)isa_io_base;
1127 case IOBASE_ISA_MEM:
1128 return (long)isa_mem_base;
1129 }
1130
1131 return result;
1132}
1133
1134/*
1135 * Null PCI config access functions, for the case when we can't
1136 * find a hose.
1137 */
1138#define NULL_PCI_OP(rw, size, type) \
1139static int \
1140null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1141{ \
1142 return PCIBIOS_DEVICE_NOT_FOUND; \
1143}
1144
1145static int
1146null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1147 int len, u32 *val)
1148{
1149 return PCIBIOS_DEVICE_NOT_FOUND;
1150}
1151
1152static int
1153null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1154 int len, u32 val)
1155{
1156 return PCIBIOS_DEVICE_NOT_FOUND;
1157}
1158
1159static struct pci_ops null_pci_ops = {
1160 .read = null_read_config,
1161 .write = null_write_config,
1162};
1163
1164/*
1165 * These functions are used early on before PCI scanning is done
1166 * and all of the pci_dev and pci_bus structures have been created.
1167 */
1168static struct pci_bus *
1169fake_pci_bus(struct pci_controller *hose, int busnr)
1170{
1171 static struct pci_bus bus;
1172
1173 if (!hose)
1174 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1175
1176 bus.number = busnr;
1177 bus.sysdata = hose;
1178 bus.ops = hose ? hose->ops : &null_pci_ops;
1179 return &bus;
1180}
1181
1182#define EARLY_PCI_OP(rw, size, type) \
1183int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1184 int devfn, int offset, type value) \
1185{ \
1186 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1187 devfn, offset, value); \
1188}
1189
1190EARLY_PCI_OP(read, byte, u8 *)
1191EARLY_PCI_OP(read, word, u16 *)
1192EARLY_PCI_OP(read, dword, u32 *)
1193EARLY_PCI_OP(write, byte, u8)
1194EARLY_PCI_OP(write, word, u16)
1195EARLY_PCI_OP(write, dword, u32)
1196
1197int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1198 int cap)
1199{
1200 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1201}
1202
1/*
2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
4 *
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
7 *
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
10 *
11 * Common pmac/prep/chrp pci routines. -- Cort
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/bootmem.h>
24#include <linux/mm.h>
25#include <linux/list.h>
26#include <linux/syscalls.h>
27#include <linux/irq.h>
28#include <linux/vmalloc.h>
29#include <linux/slab.h>
30#include <linux/of.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/of_pci.h>
34#include <linux/export.h>
35
36#include <asm/processor.h>
37#include <linux/io.h>
38#include <asm/pci-bridge.h>
39#include <asm/byteorder.h>
40
41static DEFINE_SPINLOCK(hose_spinlock);
42LIST_HEAD(hose_list);
43
44/* XXX kill that some day ... */
45static int global_phb_number; /* Global phb counter */
46
47/* ISA Memory physical address */
48resource_size_t isa_mem_base;
49
50unsigned long isa_io_base;
51static int pci_bus_count;
52
53struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
54{
55 struct pci_controller *phb;
56
57 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
58 if (!phb)
59 return NULL;
60 spin_lock(&hose_spinlock);
61 phb->global_number = global_phb_number++;
62 list_add_tail(&phb->list_node, &hose_list);
63 spin_unlock(&hose_spinlock);
64 phb->dn = dev;
65 phb->is_dynamic = mem_init_done;
66 return phb;
67}
68
69void pcibios_free_controller(struct pci_controller *phb)
70{
71 spin_lock(&hose_spinlock);
72 list_del(&phb->list_node);
73 spin_unlock(&hose_spinlock);
74
75 if (phb->is_dynamic)
76 kfree(phb);
77}
78
79static resource_size_t pcibios_io_size(const struct pci_controller *hose)
80{
81 return resource_size(&hose->io_resource);
82}
83
84int pcibios_vaddr_is_ioport(void __iomem *address)
85{
86 int ret = 0;
87 struct pci_controller *hose;
88 resource_size_t size;
89
90 spin_lock(&hose_spinlock);
91 list_for_each_entry(hose, &hose_list, list_node) {
92 size = pcibios_io_size(hose);
93 if (address >= hose->io_base_virt &&
94 address < (hose->io_base_virt + size)) {
95 ret = 1;
96 break;
97 }
98 }
99 spin_unlock(&hose_spinlock);
100 return ret;
101}
102
103unsigned long pci_address_to_pio(phys_addr_t address)
104{
105 struct pci_controller *hose;
106 resource_size_t size;
107 unsigned long ret = ~0;
108
109 spin_lock(&hose_spinlock);
110 list_for_each_entry(hose, &hose_list, list_node) {
111 size = pcibios_io_size(hose);
112 if (address >= hose->io_base_phys &&
113 address < (hose->io_base_phys + size)) {
114 unsigned long base =
115 (unsigned long)hose->io_base_virt - _IO_BASE;
116 ret = base + (address - hose->io_base_phys);
117 break;
118 }
119 }
120 spin_unlock(&hose_spinlock);
121
122 return ret;
123}
124EXPORT_SYMBOL_GPL(pci_address_to_pio);
125
126/* This routine is meant to be used early during boot, when the
127 * PCI bus numbers have not yet been assigned, and you need to
128 * issue PCI config cycles to an OF device.
129 * It could also be used to "fix" RTAS config cycles if you want
130 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
131 * config cycles.
132 */
133struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
134{
135 while (node) {
136 struct pci_controller *hose, *tmp;
137 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
138 if (hose->dn == node)
139 return hose;
140 node = node->parent;
141 }
142 return NULL;
143}
144
145void pcibios_set_master(struct pci_dev *dev)
146{
147 /* No special bus mastering setup handling */
148}
149
150/*
151 * Platform support for /proc/bus/pci/X/Y mmap()s,
152 * modelled on the sparc64 implementation by Dave Miller.
153 * -- paulus.
154 */
155
156/*
157 * Adjust vm_pgoff of VMA such that it is the physical page offset
158 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
159 *
160 * Basically, the user finds the base address for his device which he wishes
161 * to mmap. They read the 32-bit value from the config space base register,
162 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
163 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
164 *
165 * Returns negative error code on failure, zero on success.
166 */
167static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
168 resource_size_t *offset,
169 enum pci_mmap_state mmap_state)
170{
171 struct pci_controller *hose = pci_bus_to_host(dev->bus);
172 unsigned long io_offset = 0;
173 int i, res_bit;
174
175 if (!hose)
176 return NULL; /* should never happen */
177
178 /* If memory, add on the PCI bridge address offset */
179 if (mmap_state == pci_mmap_mem) {
180#if 0 /* See comment in pci_resource_to_user() for why this is disabled */
181 *offset += hose->pci_mem_offset;
182#endif
183 res_bit = IORESOURCE_MEM;
184 } else {
185 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
186 *offset += io_offset;
187 res_bit = IORESOURCE_IO;
188 }
189
190 /*
191 * Check that the offset requested corresponds to one of the
192 * resources of the device.
193 */
194 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
195 struct resource *rp = &dev->resource[i];
196 int flags = rp->flags;
197
198 /* treat ROM as memory (should be already) */
199 if (i == PCI_ROM_RESOURCE)
200 flags |= IORESOURCE_MEM;
201
202 /* Active and same type? */
203 if ((flags & res_bit) == 0)
204 continue;
205
206 /* In the range of this resource? */
207 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
208 continue;
209
210 /* found it! construct the final physical address */
211 if (mmap_state == pci_mmap_io)
212 *offset += hose->io_base_phys - io_offset;
213 return rp;
214 }
215
216 return NULL;
217}
218
219/*
220 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
221 * device mapping.
222 */
223static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
224 pgprot_t protection,
225 enum pci_mmap_state mmap_state,
226 int write_combine)
227{
228 pgprot_t prot = protection;
229
230 /* Write combine is always 0 on non-memory space mappings. On
231 * memory space, if the user didn't pass 1, we check for a
232 * "prefetchable" resource. This is a bit hackish, but we use
233 * this to workaround the inability of /sysfs to provide a write
234 * combine bit
235 */
236 if (mmap_state != pci_mmap_mem)
237 write_combine = 0;
238 else if (write_combine == 0) {
239 if (rp->flags & IORESOURCE_PREFETCH)
240 write_combine = 1;
241 }
242
243 return pgprot_noncached(prot);
244}
245
246/*
247 * This one is used by /dev/mem and fbdev who have no clue about the
248 * PCI device, it tries to find the PCI device first and calls the
249 * above routine
250 */
251pgprot_t pci_phys_mem_access_prot(struct file *file,
252 unsigned long pfn,
253 unsigned long size,
254 pgprot_t prot)
255{
256 struct pci_dev *pdev = NULL;
257 struct resource *found = NULL;
258 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
259 int i;
260
261 if (page_is_ram(pfn))
262 return prot;
263
264 prot = pgprot_noncached(prot);
265 for_each_pci_dev(pdev) {
266 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
267 struct resource *rp = &pdev->resource[i];
268 int flags = rp->flags;
269
270 /* Active and same type? */
271 if ((flags & IORESOURCE_MEM) == 0)
272 continue;
273 /* In the range of this resource? */
274 if (offset < (rp->start & PAGE_MASK) ||
275 offset > rp->end)
276 continue;
277 found = rp;
278 break;
279 }
280 if (found)
281 break;
282 }
283 if (found) {
284 if (found->flags & IORESOURCE_PREFETCH)
285 prot = pgprot_noncached_wc(prot);
286 pci_dev_put(pdev);
287 }
288
289 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
290 (unsigned long long)offset, pgprot_val(prot));
291
292 return prot;
293}
294
295/*
296 * Perform the actual remap of the pages for a PCI device mapping, as
297 * appropriate for this architecture. The region in the process to map
298 * is described by vm_start and vm_end members of VMA, the base physical
299 * address is found in vm_pgoff.
300 * The pci device structure is provided so that architectures may make mapping
301 * decisions on a per-device or per-bus basis.
302 *
303 * Returns a negative error code on failure, zero on success.
304 */
305int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
306 enum pci_mmap_state mmap_state, int write_combine)
307{
308 resource_size_t offset =
309 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
310 struct resource *rp;
311 int ret;
312
313 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
314 if (rp == NULL)
315 return -EINVAL;
316
317 vma->vm_pgoff = offset >> PAGE_SHIFT;
318 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
319 vma->vm_page_prot,
320 mmap_state, write_combine);
321
322 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
323 vma->vm_end - vma->vm_start, vma->vm_page_prot);
324
325 return ret;
326}
327
328/* This provides legacy IO read access on a bus */
329int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
330{
331 unsigned long offset;
332 struct pci_controller *hose = pci_bus_to_host(bus);
333 struct resource *rp = &hose->io_resource;
334 void __iomem *addr;
335
336 /* Check if port can be supported by that bus. We only check
337 * the ranges of the PHB though, not the bus itself as the rules
338 * for forwarding legacy cycles down bridges are not our problem
339 * here. So if the host bridge supports it, we do it.
340 */
341 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
342 offset += port;
343
344 if (!(rp->flags & IORESOURCE_IO))
345 return -ENXIO;
346 if (offset < rp->start || (offset + size) > rp->end)
347 return -ENXIO;
348 addr = hose->io_base_virt + port;
349
350 switch (size) {
351 case 1:
352 *((u8 *)val) = in_8(addr);
353 return 1;
354 case 2:
355 if (port & 1)
356 return -EINVAL;
357 *((u16 *)val) = in_le16(addr);
358 return 2;
359 case 4:
360 if (port & 3)
361 return -EINVAL;
362 *((u32 *)val) = in_le32(addr);
363 return 4;
364 }
365 return -EINVAL;
366}
367
368/* This provides legacy IO write access on a bus */
369int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
370{
371 unsigned long offset;
372 struct pci_controller *hose = pci_bus_to_host(bus);
373 struct resource *rp = &hose->io_resource;
374 void __iomem *addr;
375
376 /* Check if port can be supported by that bus. We only check
377 * the ranges of the PHB though, not the bus itself as the rules
378 * for forwarding legacy cycles down bridges are not our problem
379 * here. So if the host bridge supports it, we do it.
380 */
381 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
382 offset += port;
383
384 if (!(rp->flags & IORESOURCE_IO))
385 return -ENXIO;
386 if (offset < rp->start || (offset + size) > rp->end)
387 return -ENXIO;
388 addr = hose->io_base_virt + port;
389
390 /* WARNING: The generic code is idiotic. It gets passed a pointer
391 * to what can be a 1, 2 or 4 byte quantity and always reads that
392 * as a u32, which means that we have to correct the location of
393 * the data read within those 32 bits for size 1 and 2
394 */
395 switch (size) {
396 case 1:
397 out_8(addr, val >> 24);
398 return 1;
399 case 2:
400 if (port & 1)
401 return -EINVAL;
402 out_le16(addr, val >> 16);
403 return 2;
404 case 4:
405 if (port & 3)
406 return -EINVAL;
407 out_le32(addr, val);
408 return 4;
409 }
410 return -EINVAL;
411}
412
413/* This provides legacy IO or memory mmap access on a bus */
414int pci_mmap_legacy_page_range(struct pci_bus *bus,
415 struct vm_area_struct *vma,
416 enum pci_mmap_state mmap_state)
417{
418 struct pci_controller *hose = pci_bus_to_host(bus);
419 resource_size_t offset =
420 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
421 resource_size_t size = vma->vm_end - vma->vm_start;
422 struct resource *rp;
423
424 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
425 pci_domain_nr(bus), bus->number,
426 mmap_state == pci_mmap_mem ? "MEM" : "IO",
427 (unsigned long long)offset,
428 (unsigned long long)(offset + size - 1));
429
430 if (mmap_state == pci_mmap_mem) {
431 /* Hack alert !
432 *
433 * Because X is lame and can fail starting if it gets an error
434 * trying to mmap legacy_mem (instead of just moving on without
435 * legacy memory access) we fake it here by giving it anonymous
436 * memory, effectively behaving just like /dev/zero
437 */
438 if ((offset + size) > hose->isa_mem_size) {
439#ifdef CONFIG_MMU
440 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
441 current->comm, current->pid);
442 pr_debug("legacy memory for 0%04x:%02x\n",
443 pci_domain_nr(bus), bus->number);
444#endif
445 if (vma->vm_flags & VM_SHARED)
446 return shmem_zero_setup(vma);
447 return 0;
448 }
449 offset += hose->isa_mem_phys;
450 } else {
451 unsigned long io_offset = (unsigned long)hose->io_base_virt -
452 _IO_BASE;
453 unsigned long roffset = offset + io_offset;
454 rp = &hose->io_resource;
455 if (!(rp->flags & IORESOURCE_IO))
456 return -ENXIO;
457 if (roffset < rp->start || (roffset + size) > rp->end)
458 return -ENXIO;
459 offset += hose->io_base_phys;
460 }
461 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
462
463 vma->vm_pgoff = offset >> PAGE_SHIFT;
464 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
465 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
466 vma->vm_end - vma->vm_start,
467 vma->vm_page_prot);
468}
469
470void pci_resource_to_user(const struct pci_dev *dev, int bar,
471 const struct resource *rsrc,
472 resource_size_t *start, resource_size_t *end)
473{
474 struct pci_controller *hose = pci_bus_to_host(dev->bus);
475 resource_size_t offset = 0;
476
477 if (hose == NULL)
478 return;
479
480 if (rsrc->flags & IORESOURCE_IO)
481 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
482
483 /* We pass a fully fixed up address to userland for MMIO instead of
484 * a BAR value because X is lame and expects to be able to use that
485 * to pass to /dev/mem !
486 *
487 * That means that we'll have potentially 64 bits values where some
488 * userland apps only expect 32 (like X itself since it thinks only
489 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
490 * 32 bits CHRPs :-(
491 *
492 * Hopefully, the sysfs insterface is immune to that gunk. Once X
493 * has been fixed (and the fix spread enough), we can re-enable the
494 * 2 lines below and pass down a BAR value to userland. In that case
495 * we'll also have to re-enable the matching code in
496 * __pci_mmap_make_offset().
497 *
498 * BenH.
499 */
500#if 0
501 else if (rsrc->flags & IORESOURCE_MEM)
502 offset = hose->pci_mem_offset;
503#endif
504
505 *start = rsrc->start - offset;
506 *end = rsrc->end - offset;
507}
508
509/**
510 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
511 * @hose: newly allocated pci_controller to be setup
512 * @dev: device node of the host bridge
513 * @primary: set if primary bus (32 bits only, soon to be deprecated)
514 *
515 * This function will parse the "ranges" property of a PCI host bridge device
516 * node and setup the resource mapping of a pci controller based on its
517 * content.
518 *
519 * Life would be boring if it wasn't for a few issues that we have to deal
520 * with here:
521 *
522 * - We can only cope with one IO space range and up to 3 Memory space
523 * ranges. However, some machines (thanks Apple !) tend to split their
524 * space into lots of small contiguous ranges. So we have to coalesce.
525 *
526 * - We can only cope with all memory ranges having the same offset
527 * between CPU addresses and PCI addresses. Unfortunately, some bridges
528 * are setup for a large 1:1 mapping along with a small "window" which
529 * maps PCI address 0 to some arbitrary high address of the CPU space in
530 * order to give access to the ISA memory hole.
531 * The way out of here that I've chosen for now is to always set the
532 * offset based on the first resource found, then override it if we
533 * have a different offset and the previous was set by an ISA hole.
534 *
535 * - Some busses have IO space not starting at 0, which causes trouble with
536 * the way we do our IO resource renumbering. The code somewhat deals with
537 * it for 64 bits but I would expect problems on 32 bits.
538 *
539 * - Some 32 bits platforms such as 4xx can have physical space larger than
540 * 32 bits so we need to use 64 bits values for the parsing
541 */
542void pci_process_bridge_OF_ranges(struct pci_controller *hose,
543 struct device_node *dev, int primary)
544{
545 int memno = 0, isa_hole = -1;
546 unsigned long long isa_mb = 0;
547 struct resource *res;
548 struct of_pci_range range;
549 struct of_pci_range_parser parser;
550
551 pr_info("PCI host bridge %s %s ranges:\n",
552 dev->full_name, primary ? "(primary)" : "");
553
554 /* Check for ranges property */
555 if (of_pci_range_parser_init(&parser, dev))
556 return;
557
558 pr_debug("Parsing ranges property...\n");
559 for_each_of_pci_range(&parser, &range) {
560 /* Read next ranges element */
561 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
562 range.pci_space, range.pci_addr);
563 pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
564 range.cpu_addr, range.size);
565
566 /* If we failed translation or got a zero-sized region
567 * (some FW try to feed us with non sensical zero sized regions
568 * such as power3 which look like some kind of attempt
569 * at exposing the VGA memory hole)
570 */
571 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
572 continue;
573
574 /* Act based on address space type */
575 res = NULL;
576 switch (range.flags & IORESOURCE_TYPE_BITS) {
577 case IORESOURCE_IO:
578 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
579 range.cpu_addr, range.cpu_addr + range.size - 1,
580 range.pci_addr);
581
582 /* We support only one IO range */
583 if (hose->pci_io_size) {
584 pr_info(" \\--> Skipped (too many) !\n");
585 continue;
586 }
587 /* On 32 bits, limit I/O space to 16MB */
588 if (range.size > 0x01000000)
589 range.size = 0x01000000;
590
591 /* 32 bits needs to map IOs here */
592 hose->io_base_virt = ioremap(range.cpu_addr,
593 range.size);
594
595 /* Expect trouble if pci_addr is not 0 */
596 if (primary)
597 isa_io_base =
598 (unsigned long)hose->io_base_virt;
599 /* pci_io_size and io_base_phys always represent IO
600 * space starting at 0 so we factor in pci_addr
601 */
602 hose->pci_io_size = range.pci_addr + range.size;
603 hose->io_base_phys = range.cpu_addr - range.pci_addr;
604
605 /* Build resource */
606 res = &hose->io_resource;
607 range.cpu_addr = range.pci_addr;
608
609 break;
610 case IORESOURCE_MEM:
611 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
612 range.cpu_addr, range.cpu_addr + range.size - 1,
613 range.pci_addr,
614 (range.pci_space & 0x40000000) ?
615 "Prefetch" : "");
616
617 /* We support only 3 memory ranges */
618 if (memno >= 3) {
619 pr_info(" \\--> Skipped (too many) !\n");
620 continue;
621 }
622 /* Handles ISA memory hole space here */
623 if (range.pci_addr == 0) {
624 isa_mb = range.cpu_addr;
625 isa_hole = memno;
626 if (primary || isa_mem_base == 0)
627 isa_mem_base = range.cpu_addr;
628 hose->isa_mem_phys = range.cpu_addr;
629 hose->isa_mem_size = range.size;
630 }
631
632 /* We get the PCI/Mem offset from the first range or
633 * the, current one if the offset came from an ISA
634 * hole. If they don't match, bugger.
635 */
636 if (memno == 0 ||
637 (isa_hole >= 0 && range.pci_addr != 0 &&
638 hose->pci_mem_offset == isa_mb))
639 hose->pci_mem_offset = range.cpu_addr -
640 range.pci_addr;
641 else if (range.pci_addr != 0 &&
642 hose->pci_mem_offset != range.cpu_addr -
643 range.pci_addr) {
644 pr_info(" \\--> Skipped (offset mismatch) !\n");
645 continue;
646 }
647
648 /* Build resource */
649 res = &hose->mem_resources[memno++];
650 break;
651 }
652 if (res != NULL) {
653 res->name = dev->full_name;
654 res->flags = range.flags;
655 res->start = range.cpu_addr;
656 res->end = range.cpu_addr + range.size - 1;
657 res->parent = res->child = res->sibling = NULL;
658 }
659 }
660
661 /* If there's an ISA hole and the pci_mem_offset is -not- matching
662 * the ISA hole offset, then we need to remove the ISA hole from
663 * the resource list for that brige
664 */
665 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
666 unsigned int next = isa_hole + 1;
667 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
668 if (next < memno)
669 memmove(&hose->mem_resources[isa_hole],
670 &hose->mem_resources[next],
671 sizeof(struct resource) * (memno - next));
672 hose->mem_resources[--memno].flags = 0;
673 }
674}
675
676/* Decide whether to display the domain number in /proc */
677int pci_proc_domain(struct pci_bus *bus)
678{
679 return 0;
680}
681
682/* This header fixup will do the resource fixup for all devices as they are
683 * probed, but not for bridge ranges
684 */
685static void pcibios_fixup_resources(struct pci_dev *dev)
686{
687 struct pci_controller *hose = pci_bus_to_host(dev->bus);
688 int i;
689
690 if (!hose) {
691 pr_err("No host bridge for PCI dev %s !\n",
692 pci_name(dev));
693 return;
694 }
695 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
696 struct resource *res = dev->resource + i;
697 if (!res->flags)
698 continue;
699 if (res->start == 0) {
700 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
701 pci_name(dev), i,
702 (unsigned long long)res->start,
703 (unsigned long long)res->end,
704 (unsigned int)res->flags);
705 pr_debug("is unassigned\n");
706 res->end -= res->start;
707 res->start = 0;
708 res->flags |= IORESOURCE_UNSET;
709 continue;
710 }
711
712 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
713 pci_name(dev), i,
714 (unsigned long long)res->start,
715 (unsigned long long)res->end,
716 (unsigned int)res->flags);
717 }
718}
719DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
720
721/* This function tries to figure out if a bridge resource has been initialized
722 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
723 * things go more smoothly when it gets it right. It should covers cases such
724 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
725 */
726static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
727 struct resource *res)
728{
729 struct pci_controller *hose = pci_bus_to_host(bus);
730 struct pci_dev *dev = bus->self;
731 resource_size_t offset;
732 u16 command;
733 int i;
734
735 /* Job is a bit different between memory and IO */
736 if (res->flags & IORESOURCE_MEM) {
737 /* If the BAR is non-0 (res != pci_mem_offset) then it's
738 * probably been initialized by somebody
739 */
740 if (res->start != hose->pci_mem_offset)
741 return 0;
742
743 /* The BAR is 0, let's check if memory decoding is enabled on
744 * the bridge. If not, we consider it unassigned
745 */
746 pci_read_config_word(dev, PCI_COMMAND, &command);
747 if ((command & PCI_COMMAND_MEMORY) == 0)
748 return 1;
749
750 /* Memory decoding is enabled and the BAR is 0. If any of
751 * the bridge resources covers that starting address (0 then
752 * it's good enough for us for memory
753 */
754 for (i = 0; i < 3; i++) {
755 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
756 hose->mem_resources[i].start == hose->pci_mem_offset)
757 return 0;
758 }
759
760 /* Well, it starts at 0 and we know it will collide so we may as
761 * well consider it as unassigned. That covers the Apple case.
762 */
763 return 1;
764 } else {
765 /* If the BAR is non-0, then we consider it assigned */
766 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
767 if (((res->start - offset) & 0xfffffffful) != 0)
768 return 0;
769
770 /* Here, we are a bit different than memory as typically IO
771 * space starting at low addresses -is- valid. What we do
772 * instead if that we consider as unassigned anything that
773 * doesn't have IO enabled in the PCI command register,
774 * and that's it.
775 */
776 pci_read_config_word(dev, PCI_COMMAND, &command);
777 if (command & PCI_COMMAND_IO)
778 return 0;
779
780 /* It's starting at 0 and IO is disabled in the bridge, consider
781 * it unassigned
782 */
783 return 1;
784 }
785}
786
787/* Fixup resources of a PCI<->PCI bridge */
788static void pcibios_fixup_bridge(struct pci_bus *bus)
789{
790 struct resource *res;
791 int i;
792
793 struct pci_dev *dev = bus->self;
794
795 pci_bus_for_each_resource(bus, res, i) {
796 if (!res)
797 continue;
798 if (!res->flags)
799 continue;
800 if (i >= 3 && bus->self->transparent)
801 continue;
802
803 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
804 pci_name(dev), i,
805 (unsigned long long)res->start,
806 (unsigned long long)res->end,
807 (unsigned int)res->flags);
808
809 /* Try to detect uninitialized P2P bridge resources,
810 * and clear them out so they get re-assigned later
811 */
812 if (pcibios_uninitialized_bridge_resource(bus, res)) {
813 res->flags = 0;
814 pr_debug("PCI:%s (unassigned)\n",
815 pci_name(dev));
816 } else {
817 pr_debug("PCI:%s %016llx-%016llx\n",
818 pci_name(dev),
819 (unsigned long long)res->start,
820 (unsigned long long)res->end);
821 }
822 }
823}
824
825void pcibios_setup_bus_self(struct pci_bus *bus)
826{
827 /* Fix up the bus resources for P2P bridges */
828 if (bus->self != NULL)
829 pcibios_fixup_bridge(bus);
830}
831
832void pcibios_setup_bus_devices(struct pci_bus *bus)
833{
834 struct pci_dev *dev;
835
836 pr_debug("PCI: Fixup bus devices %d (%s)\n",
837 bus->number, bus->self ? pci_name(bus->self) : "PHB");
838
839 list_for_each_entry(dev, &bus->devices, bus_list) {
840 /* Setup OF node pointer in archdata */
841 dev->dev.of_node = pci_device_to_OF_node(dev);
842
843 /* Fixup NUMA node as it may not be setup yet by the generic
844 * code and is needed by the DMA init
845 */
846 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
847
848 /* Read default IRQs and fixup if necessary */
849 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
850 }
851}
852
853void pcibios_fixup_bus(struct pci_bus *bus)
854{
855 /* nothing to do */
856}
857EXPORT_SYMBOL(pcibios_fixup_bus);
858
859/*
860 * We need to avoid collisions with `mirrored' VGA ports
861 * and other strange ISA hardware, so we always want the
862 * addresses to be allocated in the 0x000-0x0ff region
863 * modulo 0x400.
864 *
865 * Why? Because some silly external IO cards only decode
866 * the low 10 bits of the IO address. The 0x00-0xff region
867 * is reserved for motherboard devices that decode all 16
868 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
869 * but we want to try to avoid allocating at 0x2900-0x2bff
870 * which might have be mirrored at 0x0100-0x03ff..
871 */
872resource_size_t pcibios_align_resource(void *data, const struct resource *res,
873 resource_size_t size, resource_size_t align)
874{
875 return res->start;
876}
877EXPORT_SYMBOL(pcibios_align_resource);
878
879int pcibios_add_device(struct pci_dev *dev)
880{
881 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
882
883 return 0;
884}
885EXPORT_SYMBOL(pcibios_add_device);
886
887/*
888 * Reparent resource children of pr that conflict with res
889 * under res, and make res replace those children.
890 */
891static int __init reparent_resources(struct resource *parent,
892 struct resource *res)
893{
894 struct resource *p, **pp;
895 struct resource **firstpp = NULL;
896
897 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
898 if (p->end < res->start)
899 continue;
900 if (res->end < p->start)
901 break;
902 if (p->start < res->start || p->end > res->end)
903 return -1; /* not completely contained */
904 if (firstpp == NULL)
905 firstpp = pp;
906 }
907 if (firstpp == NULL)
908 return -1; /* didn't find any conflicting entries? */
909 res->parent = parent;
910 res->child = *firstpp;
911 res->sibling = *pp;
912 *firstpp = res;
913 *pp = NULL;
914 for (p = res->child; p != NULL; p = p->sibling) {
915 p->parent = res;
916 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
917 p->name,
918 (unsigned long long)p->start,
919 (unsigned long long)p->end, res->name);
920 }
921 return 0;
922}
923
924/*
925 * Handle resources of PCI devices. If the world were perfect, we could
926 * just allocate all the resource regions and do nothing more. It isn't.
927 * On the other hand, we cannot just re-allocate all devices, as it would
928 * require us to know lots of host bridge internals. So we attempt to
929 * keep as much of the original configuration as possible, but tweak it
930 * when it's found to be wrong.
931 *
932 * Known BIOS problems we have to work around:
933 * - I/O or memory regions not configured
934 * - regions configured, but not enabled in the command register
935 * - bogus I/O addresses above 64K used
936 * - expansion ROMs left enabled (this may sound harmless, but given
937 * the fact the PCI specs explicitly allow address decoders to be
938 * shared between expansion ROMs and other resource regions, it's
939 * at least dangerous)
940 *
941 * Our solution:
942 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
943 * This gives us fixed barriers on where we can allocate.
944 * (2) Allocate resources for all enabled devices. If there is
945 * a collision, just mark the resource as unallocated. Also
946 * disable expansion ROMs during this step.
947 * (3) Try to allocate resources for disabled devices. If the
948 * resources were assigned correctly, everything goes well,
949 * if they weren't, they won't disturb allocation of other
950 * resources.
951 * (4) Assign new addresses to resources which were either
952 * not configured at all or misconfigured. If explicitly
953 * requested by the user, configure expansion ROM address
954 * as well.
955 */
956
957static void pcibios_allocate_bus_resources(struct pci_bus *bus)
958{
959 struct pci_bus *b;
960 int i;
961 struct resource *res, *pr;
962
963 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
964 pci_domain_nr(bus), bus->number);
965
966 pci_bus_for_each_resource(bus, res, i) {
967 if (!res || !res->flags
968 || res->start > res->end || res->parent)
969 continue;
970 if (bus->parent == NULL)
971 pr = (res->flags & IORESOURCE_IO) ?
972 &ioport_resource : &iomem_resource;
973 else {
974 /* Don't bother with non-root busses when
975 * re-assigning all resources. We clear the
976 * resource flags as if they were colliding
977 * and as such ensure proper re-allocation
978 * later.
979 */
980 pr = pci_find_parent_resource(bus->self, res);
981 if (pr == res) {
982 /* this happens when the generic PCI
983 * code (wrongly) decides that this
984 * bridge is transparent -- paulus
985 */
986 continue;
987 }
988 }
989
990 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
991 bus->self ? pci_name(bus->self) : "PHB",
992 bus->number, i,
993 (unsigned long long)res->start,
994 (unsigned long long)res->end);
995 pr_debug("[0x%x], parent %p (%s)\n",
996 (unsigned int)res->flags,
997 pr, (pr && pr->name) ? pr->name : "nil");
998
999 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1000 struct pci_dev *dev = bus->self;
1001
1002 if (request_resource(pr, res) == 0)
1003 continue;
1004 /*
1005 * Must be a conflict with an existing entry.
1006 * Move that entry (or entries) under the
1007 * bridge resource and try again.
1008 */
1009 if (reparent_resources(pr, res) == 0)
1010 continue;
1011
1012 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1013 pci_claim_bridge_resource(dev,
1014 i + PCI_BRIDGE_RESOURCES) == 0)
1015 continue;
1016
1017 }
1018 pr_warn("PCI: Cannot allocate resource region ");
1019 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
1020 res->start = res->end = 0;
1021 res->flags = 0;
1022 }
1023
1024 list_for_each_entry(b, &bus->children, node)
1025 pcibios_allocate_bus_resources(b);
1026}
1027
1028static inline void alloc_resource(struct pci_dev *dev, int idx)
1029{
1030 struct resource *pr, *r = &dev->resource[idx];
1031
1032 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1033 pci_name(dev), idx,
1034 (unsigned long long)r->start,
1035 (unsigned long long)r->end,
1036 (unsigned int)r->flags);
1037
1038 pr = pci_find_parent_resource(dev, r);
1039 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1040 request_resource(pr, r) < 0) {
1041 pr_warn("PCI: Cannot allocate resource region %d ", idx);
1042 pr_cont("of device %s, will remap\n", pci_name(dev));
1043 if (pr)
1044 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1045 pr,
1046 (unsigned long long)pr->start,
1047 (unsigned long long)pr->end,
1048 (unsigned int)pr->flags);
1049 /* We'll assign a new address later */
1050 r->flags |= IORESOURCE_UNSET;
1051 r->end -= r->start;
1052 r->start = 0;
1053 }
1054}
1055
1056static void __init pcibios_allocate_resources(int pass)
1057{
1058 struct pci_dev *dev = NULL;
1059 int idx, disabled;
1060 u16 command;
1061 struct resource *r;
1062
1063 for_each_pci_dev(dev) {
1064 pci_read_config_word(dev, PCI_COMMAND, &command);
1065 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1066 r = &dev->resource[idx];
1067 if (r->parent) /* Already allocated */
1068 continue;
1069 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1070 continue; /* Not assigned at all */
1071 /* We only allocate ROMs on pass 1 just in case they
1072 * have been screwed up by firmware
1073 */
1074 if (idx == PCI_ROM_RESOURCE)
1075 disabled = 1;
1076 if (r->flags & IORESOURCE_IO)
1077 disabled = !(command & PCI_COMMAND_IO);
1078 else
1079 disabled = !(command & PCI_COMMAND_MEMORY);
1080 if (pass == disabled)
1081 alloc_resource(dev, idx);
1082 }
1083 if (pass)
1084 continue;
1085 r = &dev->resource[PCI_ROM_RESOURCE];
1086 if (r->flags) {
1087 /* Turn the ROM off, leave the resource region,
1088 * but keep it unregistered.
1089 */
1090 u32 reg;
1091 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1092 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1093 pr_debug("PCI: Switching off ROM of %s\n",
1094 pci_name(dev));
1095 r->flags &= ~IORESOURCE_ROM_ENABLE;
1096 pci_write_config_dword(dev, dev->rom_base_reg,
1097 reg & ~PCI_ROM_ADDRESS_ENABLE);
1098 }
1099 }
1100 }
1101}
1102
1103static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1104{
1105 struct pci_controller *hose = pci_bus_to_host(bus);
1106 resource_size_t offset;
1107 struct resource *res, *pres;
1108 int i;
1109
1110 pr_debug("Reserving legacy ranges for domain %04x\n",
1111 pci_domain_nr(bus));
1112
1113 /* Check for IO */
1114 if (!(hose->io_resource.flags & IORESOURCE_IO))
1115 goto no_io;
1116 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1117 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1118 BUG_ON(res == NULL);
1119 res->name = "Legacy IO";
1120 res->flags = IORESOURCE_IO;
1121 res->start = offset;
1122 res->end = (offset + 0xfff) & 0xfffffffful;
1123 pr_debug("Candidate legacy IO: %pR\n", res);
1124 if (request_resource(&hose->io_resource, res)) {
1125 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1126 pci_domain_nr(bus), bus->number, res);
1127 kfree(res);
1128 }
1129
1130 no_io:
1131 /* Check for memory */
1132 offset = hose->pci_mem_offset;
1133 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1134 for (i = 0; i < 3; i++) {
1135 pres = &hose->mem_resources[i];
1136 if (!(pres->flags & IORESOURCE_MEM))
1137 continue;
1138 pr_debug("hose mem res: %pR\n", pres);
1139 if ((pres->start - offset) <= 0xa0000 &&
1140 (pres->end - offset) >= 0xbffff)
1141 break;
1142 }
1143 if (i >= 3)
1144 return;
1145 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1146 BUG_ON(res == NULL);
1147 res->name = "Legacy VGA memory";
1148 res->flags = IORESOURCE_MEM;
1149 res->start = 0xa0000 + offset;
1150 res->end = 0xbffff + offset;
1151 pr_debug("Candidate VGA memory: %pR\n", res);
1152 if (request_resource(pres, res)) {
1153 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1154 pci_domain_nr(bus), bus->number, res);
1155 kfree(res);
1156 }
1157}
1158
1159void __init pcibios_resource_survey(void)
1160{
1161 struct pci_bus *b;
1162
1163 /* Allocate and assign resources. If we re-assign everything, then
1164 * we skip the allocate phase
1165 */
1166 list_for_each_entry(b, &pci_root_buses, node)
1167 pcibios_allocate_bus_resources(b);
1168
1169 pcibios_allocate_resources(0);
1170 pcibios_allocate_resources(1);
1171
1172 /* Before we start assigning unassigned resource, we try to reserve
1173 * the low IO area and the VGA memory area if they intersect the
1174 * bus available resources to avoid allocating things on top of them
1175 */
1176 list_for_each_entry(b, &pci_root_buses, node)
1177 pcibios_reserve_legacy_regions(b);
1178
1179 /* Now proceed to assigning things that were left unassigned */
1180 pr_debug("PCI: Assigning unassigned resources...\n");
1181 pci_assign_unassigned_resources();
1182}
1183
1184/* This is used by the PCI hotplug driver to allocate resource
1185 * of newly plugged busses. We can try to consolidate with the
1186 * rest of the code later, for now, keep it as-is as our main
1187 * resource allocation function doesn't deal with sub-trees yet.
1188 */
1189void pcibios_claim_one_bus(struct pci_bus *bus)
1190{
1191 struct pci_dev *dev;
1192 struct pci_bus *child_bus;
1193
1194 list_for_each_entry(dev, &bus->devices, bus_list) {
1195 int i;
1196
1197 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1198 struct resource *r = &dev->resource[i];
1199
1200 if (r->parent || !r->start || !r->flags)
1201 continue;
1202
1203 pr_debug("PCI: Claiming %s: ", pci_name(dev));
1204 pr_debug("Resource %d: %016llx..%016llx [%x]\n",
1205 i, (unsigned long long)r->start,
1206 (unsigned long long)r->end,
1207 (unsigned int)r->flags);
1208
1209 if (pci_claim_resource(dev, i) == 0)
1210 continue;
1211
1212 pci_claim_bridge_resource(dev, i);
1213 }
1214 }
1215
1216 list_for_each_entry(child_bus, &bus->children, node)
1217 pcibios_claim_one_bus(child_bus);
1218}
1219EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1220
1221
1222/* pcibios_finish_adding_to_bus
1223 *
1224 * This is to be called by the hotplug code after devices have been
1225 * added to a bus, this include calling it for a PHB that is just
1226 * being added
1227 */
1228void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1229{
1230 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1231 pci_domain_nr(bus), bus->number);
1232
1233 /* Allocate bus and devices resources */
1234 pcibios_allocate_bus_resources(bus);
1235 pcibios_claim_one_bus(bus);
1236
1237 /* Add new devices to global lists. Register in proc, sysfs. */
1238 pci_bus_add_devices(bus);
1239
1240 /* Fixup EEH */
1241 /* eeh_add_device_tree_late(bus); */
1242}
1243EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1244
1245static void pcibios_setup_phb_resources(struct pci_controller *hose,
1246 struct list_head *resources)
1247{
1248 unsigned long io_offset;
1249 struct resource *res;
1250 int i;
1251
1252 /* Hookup PHB IO resource */
1253 res = &hose->io_resource;
1254
1255 /* Fixup IO space offset */
1256 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1257 res->start = (res->start + io_offset) & 0xffffffffu;
1258 res->end = (res->end + io_offset) & 0xffffffffu;
1259
1260 if (!res->flags) {
1261 pr_warn("PCI: I/O resource not set for host ");
1262 pr_cont("bridge %s (domain %d)\n",
1263 hose->dn->full_name, hose->global_number);
1264 /* Workaround for lack of IO resource only on 32-bit */
1265 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1266 res->end = res->start + IO_SPACE_LIMIT;
1267 res->flags = IORESOURCE_IO;
1268 }
1269 pci_add_resource_offset(resources, res,
1270 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
1271
1272 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1273 (unsigned long long)res->start,
1274 (unsigned long long)res->end,
1275 (unsigned long)res->flags);
1276
1277 /* Hookup PHB Memory resources */
1278 for (i = 0; i < 3; ++i) {
1279 res = &hose->mem_resources[i];
1280 if (!res->flags) {
1281 if (i > 0)
1282 continue;
1283 pr_err("PCI: Memory resource 0 not set for ");
1284 pr_cont("host bridge %s (domain %d)\n",
1285 hose->dn->full_name, hose->global_number);
1286
1287 /* Workaround for lack of MEM resource only on 32-bit */
1288 res->start = hose->pci_mem_offset;
1289 res->end = (resource_size_t)-1LL;
1290 res->flags = IORESOURCE_MEM;
1291
1292 }
1293 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
1294
1295 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1296 i, (unsigned long long)res->start,
1297 (unsigned long long)res->end,
1298 (unsigned long)res->flags);
1299 }
1300
1301 pr_debug("PCI: PHB MEM offset = %016llx\n",
1302 (unsigned long long)hose->pci_mem_offset);
1303 pr_debug("PCI: PHB IO offset = %08lx\n",
1304 (unsigned long)hose->io_base_virt - _IO_BASE);
1305}
1306
1307static void pcibios_scan_phb(struct pci_controller *hose)
1308{
1309 LIST_HEAD(resources);
1310 struct pci_bus *bus;
1311 struct device_node *node = hose->dn;
1312
1313 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1314
1315 pcibios_setup_phb_resources(hose, &resources);
1316
1317 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
1318 hose->ops, hose, &resources);
1319 if (bus == NULL) {
1320 pr_err("Failed to create bus for PCI domain %04x\n",
1321 hose->global_number);
1322 pci_free_resource_list(&resources);
1323 return;
1324 }
1325 bus->busn_res.start = hose->first_busno;
1326 hose->bus = bus;
1327
1328 hose->last_busno = bus->busn_res.end;
1329}
1330
1331static int __init pcibios_init(void)
1332{
1333 struct pci_controller *hose, *tmp;
1334 int next_busno = 0;
1335
1336 pr_info("PCI: Probing PCI hardware\n");
1337
1338 /* Scan all of the recorded PCI controllers. */
1339 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1340 hose->last_busno = 0xff;
1341 pcibios_scan_phb(hose);
1342 if (next_busno <= hose->last_busno)
1343 next_busno = hose->last_busno + 1;
1344 }
1345 pci_bus_count = next_busno;
1346
1347 /* Call common code to handle resource allocation */
1348 pcibios_resource_survey();
1349 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1350 if (hose->bus)
1351 pci_bus_add_devices(hose->bus);
1352 }
1353
1354 return 0;
1355}
1356
1357subsys_initcall(pcibios_init);
1358
1359static struct pci_controller *pci_bus_to_hose(int bus)
1360{
1361 struct pci_controller *hose, *tmp;
1362
1363 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1364 if (bus >= hose->first_busno && bus <= hose->last_busno)
1365 return hose;
1366 return NULL;
1367}
1368
1369/* Provide information on locations of various I/O regions in physical
1370 * memory. Do this on a per-card basis so that we choose the right
1371 * root bridge.
1372 * Note that the returned IO or memory base is a physical address
1373 */
1374
1375long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1376{
1377 struct pci_controller *hose;
1378 long result = -EOPNOTSUPP;
1379
1380 hose = pci_bus_to_hose(bus);
1381 if (!hose)
1382 return -ENODEV;
1383
1384 switch (which) {
1385 case IOBASE_BRIDGE_NUMBER:
1386 return (long)hose->first_busno;
1387 case IOBASE_MEMORY:
1388 return (long)hose->pci_mem_offset;
1389 case IOBASE_IO:
1390 return (long)hose->io_base_phys;
1391 case IOBASE_ISA_IO:
1392 return (long)isa_io_base;
1393 case IOBASE_ISA_MEM:
1394 return (long)isa_mem_base;
1395 }
1396
1397 return result;
1398}
1399
1400/*
1401 * Null PCI config access functions, for the case when we can't
1402 * find a hose.
1403 */
1404#define NULL_PCI_OP(rw, size, type) \
1405static int \
1406null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1407{ \
1408 return PCIBIOS_DEVICE_NOT_FOUND; \
1409}
1410
1411static int
1412null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1413 int len, u32 *val)
1414{
1415 return PCIBIOS_DEVICE_NOT_FOUND;
1416}
1417
1418static int
1419null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1420 int len, u32 val)
1421{
1422 return PCIBIOS_DEVICE_NOT_FOUND;
1423}
1424
1425static struct pci_ops null_pci_ops = {
1426 .read = null_read_config,
1427 .write = null_write_config,
1428};
1429
1430/*
1431 * These functions are used early on before PCI scanning is done
1432 * and all of the pci_dev and pci_bus structures have been created.
1433 */
1434static struct pci_bus *
1435fake_pci_bus(struct pci_controller *hose, int busnr)
1436{
1437 static struct pci_bus bus;
1438
1439 if (!hose)
1440 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1441
1442 bus.number = busnr;
1443 bus.sysdata = hose;
1444 bus.ops = hose ? hose->ops : &null_pci_ops;
1445 return &bus;
1446}
1447
1448#define EARLY_PCI_OP(rw, size, type) \
1449int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1450 int devfn, int offset, type value) \
1451{ \
1452 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1453 devfn, offset, value); \
1454}
1455
1456EARLY_PCI_OP(read, byte, u8 *)
1457EARLY_PCI_OP(read, word, u16 *)
1458EARLY_PCI_OP(read, dword, u32 *)
1459EARLY_PCI_OP(write, byte, u8)
1460EARLY_PCI_OP(write, word, u16)
1461EARLY_PCI_OP(write, dword, u32)
1462
1463int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1464 int cap)
1465{
1466 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1467}
1468