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1/*
2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
4 *
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
7 *
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
10 *
11 * Common pmac/prep/chrp pci routines. -- Cort
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/bootmem.h>
24#include <linux/mm.h>
25#include <linux/shmem_fs.h>
26#include <linux/list.h>
27#include <linux/syscalls.h>
28#include <linux/irq.h>
29#include <linux/vmalloc.h>
30#include <linux/slab.h>
31#include <linux/of.h>
32#include <linux/of_address.h>
33#include <linux/of_irq.h>
34#include <linux/of_pci.h>
35#include <linux/export.h>
36
37#include <asm/processor.h>
38#include <linux/io.h>
39#include <asm/pci-bridge.h>
40#include <asm/byteorder.h>
41
42static DEFINE_SPINLOCK(hose_spinlock);
43LIST_HEAD(hose_list);
44
45/* XXX kill that some day ... */
46static int global_phb_number; /* Global phb counter */
47
48/* ISA Memory physical address */
49resource_size_t isa_mem_base;
50
51unsigned long isa_io_base;
52EXPORT_SYMBOL(isa_io_base);
53
54static int pci_bus_count;
55
56struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
57{
58 struct pci_controller *phb;
59
60 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
61 if (!phb)
62 return NULL;
63 spin_lock(&hose_spinlock);
64 phb->global_number = global_phb_number++;
65 list_add_tail(&phb->list_node, &hose_list);
66 spin_unlock(&hose_spinlock);
67 phb->dn = dev;
68 phb->is_dynamic = mem_init_done;
69 return phb;
70}
71
72void pcibios_free_controller(struct pci_controller *phb)
73{
74 spin_lock(&hose_spinlock);
75 list_del(&phb->list_node);
76 spin_unlock(&hose_spinlock);
77
78 if (phb->is_dynamic)
79 kfree(phb);
80}
81
82static resource_size_t pcibios_io_size(const struct pci_controller *hose)
83{
84 return resource_size(&hose->io_resource);
85}
86
87int pcibios_vaddr_is_ioport(void __iomem *address)
88{
89 int ret = 0;
90 struct pci_controller *hose;
91 resource_size_t size;
92
93 spin_lock(&hose_spinlock);
94 list_for_each_entry(hose, &hose_list, list_node) {
95 size = pcibios_io_size(hose);
96 if (address >= hose->io_base_virt &&
97 address < (hose->io_base_virt + size)) {
98 ret = 1;
99 break;
100 }
101 }
102 spin_unlock(&hose_spinlock);
103 return ret;
104}
105
106unsigned long pci_address_to_pio(phys_addr_t address)
107{
108 struct pci_controller *hose;
109 resource_size_t size;
110 unsigned long ret = ~0;
111
112 spin_lock(&hose_spinlock);
113 list_for_each_entry(hose, &hose_list, list_node) {
114 size = pcibios_io_size(hose);
115 if (address >= hose->io_base_phys &&
116 address < (hose->io_base_phys + size)) {
117 unsigned long base =
118 (unsigned long)hose->io_base_virt - _IO_BASE;
119 ret = base + (address - hose->io_base_phys);
120 break;
121 }
122 }
123 spin_unlock(&hose_spinlock);
124
125 return ret;
126}
127EXPORT_SYMBOL_GPL(pci_address_to_pio);
128
129/* This routine is meant to be used early during boot, when the
130 * PCI bus numbers have not yet been assigned, and you need to
131 * issue PCI config cycles to an OF device.
132 * It could also be used to "fix" RTAS config cycles if you want
133 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
134 * config cycles.
135 */
136struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
137{
138 while (node) {
139 struct pci_controller *hose, *tmp;
140 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
141 if (hose->dn == node)
142 return hose;
143 node = node->parent;
144 }
145 return NULL;
146}
147
148void pcibios_set_master(struct pci_dev *dev)
149{
150 /* No special bus mastering setup handling */
151}
152
153/*
154 * Platform support for /proc/bus/pci/X/Y mmap()s.
155 */
156
157int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
158{
159 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
160 resource_size_t ioaddr = pci_resource_start(pdev, bar);
161
162 if (!hose)
163 return -EINVAL; /* should never happen */
164
165 /* Convert to an offset within this PCI controller */
166 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
167
168 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
169 return 0;
170}
171
172/*
173 * This one is used by /dev/mem and fbdev who have no clue about the
174 * PCI device, it tries to find the PCI device first and calls the
175 * above routine
176 */
177pgprot_t pci_phys_mem_access_prot(struct file *file,
178 unsigned long pfn,
179 unsigned long size,
180 pgprot_t prot)
181{
182 struct pci_dev *pdev = NULL;
183 struct resource *found = NULL;
184 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
185 int i;
186
187 if (page_is_ram(pfn))
188 return prot;
189
190 prot = pgprot_noncached(prot);
191 for_each_pci_dev(pdev) {
192 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
193 struct resource *rp = &pdev->resource[i];
194 int flags = rp->flags;
195
196 /* Active and same type? */
197 if ((flags & IORESOURCE_MEM) == 0)
198 continue;
199 /* In the range of this resource? */
200 if (offset < (rp->start & PAGE_MASK) ||
201 offset > rp->end)
202 continue;
203 found = rp;
204 break;
205 }
206 if (found)
207 break;
208 }
209 if (found) {
210 if (found->flags & IORESOURCE_PREFETCH)
211 prot = pgprot_noncached_wc(prot);
212 pci_dev_put(pdev);
213 }
214
215 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
216 (unsigned long long)offset, pgprot_val(prot));
217
218 return prot;
219}
220
221/* This provides legacy IO read access on a bus */
222int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
223{
224 unsigned long offset;
225 struct pci_controller *hose = pci_bus_to_host(bus);
226 struct resource *rp = &hose->io_resource;
227 void __iomem *addr;
228
229 /* Check if port can be supported by that bus. We only check
230 * the ranges of the PHB though, not the bus itself as the rules
231 * for forwarding legacy cycles down bridges are not our problem
232 * here. So if the host bridge supports it, we do it.
233 */
234 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
235 offset += port;
236
237 if (!(rp->flags & IORESOURCE_IO))
238 return -ENXIO;
239 if (offset < rp->start || (offset + size) > rp->end)
240 return -ENXIO;
241 addr = hose->io_base_virt + port;
242
243 switch (size) {
244 case 1:
245 *((u8 *)val) = in_8(addr);
246 return 1;
247 case 2:
248 if (port & 1)
249 return -EINVAL;
250 *((u16 *)val) = in_le16(addr);
251 return 2;
252 case 4:
253 if (port & 3)
254 return -EINVAL;
255 *((u32 *)val) = in_le32(addr);
256 return 4;
257 }
258 return -EINVAL;
259}
260
261/* This provides legacy IO write access on a bus */
262int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
263{
264 unsigned long offset;
265 struct pci_controller *hose = pci_bus_to_host(bus);
266 struct resource *rp = &hose->io_resource;
267 void __iomem *addr;
268
269 /* Check if port can be supported by that bus. We only check
270 * the ranges of the PHB though, not the bus itself as the rules
271 * for forwarding legacy cycles down bridges are not our problem
272 * here. So if the host bridge supports it, we do it.
273 */
274 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
275 offset += port;
276
277 if (!(rp->flags & IORESOURCE_IO))
278 return -ENXIO;
279 if (offset < rp->start || (offset + size) > rp->end)
280 return -ENXIO;
281 addr = hose->io_base_virt + port;
282
283 /* WARNING: The generic code is idiotic. It gets passed a pointer
284 * to what can be a 1, 2 or 4 byte quantity and always reads that
285 * as a u32, which means that we have to correct the location of
286 * the data read within those 32 bits for size 1 and 2
287 */
288 switch (size) {
289 case 1:
290 out_8(addr, val >> 24);
291 return 1;
292 case 2:
293 if (port & 1)
294 return -EINVAL;
295 out_le16(addr, val >> 16);
296 return 2;
297 case 4:
298 if (port & 3)
299 return -EINVAL;
300 out_le32(addr, val);
301 return 4;
302 }
303 return -EINVAL;
304}
305
306/* This provides legacy IO or memory mmap access on a bus */
307int pci_mmap_legacy_page_range(struct pci_bus *bus,
308 struct vm_area_struct *vma,
309 enum pci_mmap_state mmap_state)
310{
311 struct pci_controller *hose = pci_bus_to_host(bus);
312 resource_size_t offset =
313 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
314 resource_size_t size = vma->vm_end - vma->vm_start;
315 struct resource *rp;
316
317 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
318 pci_domain_nr(bus), bus->number,
319 mmap_state == pci_mmap_mem ? "MEM" : "IO",
320 (unsigned long long)offset,
321 (unsigned long long)(offset + size - 1));
322
323 if (mmap_state == pci_mmap_mem) {
324 /* Hack alert !
325 *
326 * Because X is lame and can fail starting if it gets an error
327 * trying to mmap legacy_mem (instead of just moving on without
328 * legacy memory access) we fake it here by giving it anonymous
329 * memory, effectively behaving just like /dev/zero
330 */
331 if ((offset + size) > hose->isa_mem_size) {
332#ifdef CONFIG_MMU
333 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
334 current->comm, current->pid);
335 pr_debug("legacy memory for 0%04x:%02x\n",
336 pci_domain_nr(bus), bus->number);
337#endif
338 if (vma->vm_flags & VM_SHARED)
339 return shmem_zero_setup(vma);
340 return 0;
341 }
342 offset += hose->isa_mem_phys;
343 } else {
344 unsigned long io_offset = (unsigned long)hose->io_base_virt -
345 _IO_BASE;
346 unsigned long roffset = offset + io_offset;
347 rp = &hose->io_resource;
348 if (!(rp->flags & IORESOURCE_IO))
349 return -ENXIO;
350 if (roffset < rp->start || (roffset + size) > rp->end)
351 return -ENXIO;
352 offset += hose->io_base_phys;
353 }
354 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
355
356 vma->vm_pgoff = offset >> PAGE_SHIFT;
357 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
358 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
359 vma->vm_end - vma->vm_start,
360 vma->vm_page_prot);
361}
362
363void pci_resource_to_user(const struct pci_dev *dev, int bar,
364 const struct resource *rsrc,
365 resource_size_t *start, resource_size_t *end)
366{
367 struct pci_bus_region region;
368
369 if (rsrc->flags & IORESOURCE_IO) {
370 pcibios_resource_to_bus(dev->bus, ®ion,
371 (struct resource *) rsrc);
372 *start = region.start;
373 *end = region.end;
374 return;
375 }
376
377 /* We pass a CPU physical address to userland for MMIO instead of a
378 * BAR value because X is lame and expects to be able to use that
379 * to pass to /dev/mem!
380 *
381 * That means we may have 64-bit values where some apps only expect
382 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
383 */
384 *start = rsrc->start;
385 *end = rsrc->end;
386}
387
388/**
389 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
390 * @hose: newly allocated pci_controller to be setup
391 * @dev: device node of the host bridge
392 * @primary: set if primary bus (32 bits only, soon to be deprecated)
393 *
394 * This function will parse the "ranges" property of a PCI host bridge device
395 * node and setup the resource mapping of a pci controller based on its
396 * content.
397 *
398 * Life would be boring if it wasn't for a few issues that we have to deal
399 * with here:
400 *
401 * - We can only cope with one IO space range and up to 3 Memory space
402 * ranges. However, some machines (thanks Apple !) tend to split their
403 * space into lots of small contiguous ranges. So we have to coalesce.
404 *
405 * - We can only cope with all memory ranges having the same offset
406 * between CPU addresses and PCI addresses. Unfortunately, some bridges
407 * are setup for a large 1:1 mapping along with a small "window" which
408 * maps PCI address 0 to some arbitrary high address of the CPU space in
409 * order to give access to the ISA memory hole.
410 * The way out of here that I've chosen for now is to always set the
411 * offset based on the first resource found, then override it if we
412 * have a different offset and the previous was set by an ISA hole.
413 *
414 * - Some busses have IO space not starting at 0, which causes trouble with
415 * the way we do our IO resource renumbering. The code somewhat deals with
416 * it for 64 bits but I would expect problems on 32 bits.
417 *
418 * - Some 32 bits platforms such as 4xx can have physical space larger than
419 * 32 bits so we need to use 64 bits values for the parsing
420 */
421void pci_process_bridge_OF_ranges(struct pci_controller *hose,
422 struct device_node *dev, int primary)
423{
424 int memno = 0, isa_hole = -1;
425 unsigned long long isa_mb = 0;
426 struct resource *res;
427 struct of_pci_range range;
428 struct of_pci_range_parser parser;
429
430 pr_info("PCI host bridge %pOF %s ranges:\n",
431 dev, primary ? "(primary)" : "");
432
433 /* Check for ranges property */
434 if (of_pci_range_parser_init(&parser, dev))
435 return;
436
437 pr_debug("Parsing ranges property...\n");
438 for_each_of_pci_range(&parser, &range) {
439 /* Read next ranges element */
440 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
441 range.pci_space, range.pci_addr);
442 pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
443 range.cpu_addr, range.size);
444
445 /* If we failed translation or got a zero-sized region
446 * (some FW try to feed us with non sensical zero sized regions
447 * such as power3 which look like some kind of attempt
448 * at exposing the VGA memory hole)
449 */
450 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
451 continue;
452
453 /* Act based on address space type */
454 res = NULL;
455 switch (range.flags & IORESOURCE_TYPE_BITS) {
456 case IORESOURCE_IO:
457 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
458 range.cpu_addr, range.cpu_addr + range.size - 1,
459 range.pci_addr);
460
461 /* We support only one IO range */
462 if (hose->pci_io_size) {
463 pr_info(" \\--> Skipped (too many) !\n");
464 continue;
465 }
466 /* On 32 bits, limit I/O space to 16MB */
467 if (range.size > 0x01000000)
468 range.size = 0x01000000;
469
470 /* 32 bits needs to map IOs here */
471 hose->io_base_virt = ioremap(range.cpu_addr,
472 range.size);
473
474 /* Expect trouble if pci_addr is not 0 */
475 if (primary)
476 isa_io_base =
477 (unsigned long)hose->io_base_virt;
478 /* pci_io_size and io_base_phys always represent IO
479 * space starting at 0 so we factor in pci_addr
480 */
481 hose->pci_io_size = range.pci_addr + range.size;
482 hose->io_base_phys = range.cpu_addr - range.pci_addr;
483
484 /* Build resource */
485 res = &hose->io_resource;
486 range.cpu_addr = range.pci_addr;
487
488 break;
489 case IORESOURCE_MEM:
490 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
491 range.cpu_addr, range.cpu_addr + range.size - 1,
492 range.pci_addr,
493 (range.pci_space & 0x40000000) ?
494 "Prefetch" : "");
495
496 /* We support only 3 memory ranges */
497 if (memno >= 3) {
498 pr_info(" \\--> Skipped (too many) !\n");
499 continue;
500 }
501 /* Handles ISA memory hole space here */
502 if (range.pci_addr == 0) {
503 isa_mb = range.cpu_addr;
504 isa_hole = memno;
505 if (primary || isa_mem_base == 0)
506 isa_mem_base = range.cpu_addr;
507 hose->isa_mem_phys = range.cpu_addr;
508 hose->isa_mem_size = range.size;
509 }
510
511 /* We get the PCI/Mem offset from the first range or
512 * the, current one if the offset came from an ISA
513 * hole. If they don't match, bugger.
514 */
515 if (memno == 0 ||
516 (isa_hole >= 0 && range.pci_addr != 0 &&
517 hose->pci_mem_offset == isa_mb))
518 hose->pci_mem_offset = range.cpu_addr -
519 range.pci_addr;
520 else if (range.pci_addr != 0 &&
521 hose->pci_mem_offset != range.cpu_addr -
522 range.pci_addr) {
523 pr_info(" \\--> Skipped (offset mismatch) !\n");
524 continue;
525 }
526
527 /* Build resource */
528 res = &hose->mem_resources[memno++];
529 break;
530 }
531 if (res != NULL) {
532 res->name = dev->full_name;
533 res->flags = range.flags;
534 res->start = range.cpu_addr;
535 res->end = range.cpu_addr + range.size - 1;
536 res->parent = res->child = res->sibling = NULL;
537 }
538 }
539
540 /* If there's an ISA hole and the pci_mem_offset is -not- matching
541 * the ISA hole offset, then we need to remove the ISA hole from
542 * the resource list for that brige
543 */
544 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
545 unsigned int next = isa_hole + 1;
546 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
547 if (next < memno)
548 memmove(&hose->mem_resources[isa_hole],
549 &hose->mem_resources[next],
550 sizeof(struct resource) * (memno - next));
551 hose->mem_resources[--memno].flags = 0;
552 }
553}
554
555/* Display the domain number in /proc */
556int pci_proc_domain(struct pci_bus *bus)
557{
558 return pci_domain_nr(bus);
559}
560
561/* This header fixup will do the resource fixup for all devices as they are
562 * probed, but not for bridge ranges
563 */
564static void pcibios_fixup_resources(struct pci_dev *dev)
565{
566 struct pci_controller *hose = pci_bus_to_host(dev->bus);
567 int i;
568
569 if (!hose) {
570 pr_err("No host bridge for PCI dev %s !\n",
571 pci_name(dev));
572 return;
573 }
574 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
575 struct resource *res = dev->resource + i;
576 if (!res->flags)
577 continue;
578 if (res->start == 0) {
579 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
580 pci_name(dev), i,
581 (unsigned long long)res->start,
582 (unsigned long long)res->end,
583 (unsigned int)res->flags);
584 pr_debug("is unassigned\n");
585 res->end -= res->start;
586 res->start = 0;
587 res->flags |= IORESOURCE_UNSET;
588 continue;
589 }
590
591 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
592 pci_name(dev), i,
593 (unsigned long long)res->start,
594 (unsigned long long)res->end,
595 (unsigned int)res->flags);
596 }
597}
598DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
599
600/*
601 * We need to avoid collisions with `mirrored' VGA ports
602 * and other strange ISA hardware, so we always want the
603 * addresses to be allocated in the 0x000-0x0ff region
604 * modulo 0x400.
605 *
606 * Why? Because some silly external IO cards only decode
607 * the low 10 bits of the IO address. The 0x00-0xff region
608 * is reserved for motherboard devices that decode all 16
609 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
610 * but we want to try to avoid allocating at 0x2900-0x2bff
611 * which might have be mirrored at 0x0100-0x03ff..
612 */
613int pcibios_add_device(struct pci_dev *dev)
614{
615 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
616
617 return 0;
618}
619EXPORT_SYMBOL(pcibios_add_device);
620
621/*
622 * Reparent resource children of pr that conflict with res
623 * under res, and make res replace those children.
624 */
625static int __init reparent_resources(struct resource *parent,
626 struct resource *res)
627{
628 struct resource *p, **pp;
629 struct resource **firstpp = NULL;
630
631 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
632 if (p->end < res->start)
633 continue;
634 if (res->end < p->start)
635 break;
636 if (p->start < res->start || p->end > res->end)
637 return -1; /* not completely contained */
638 if (firstpp == NULL)
639 firstpp = pp;
640 }
641 if (firstpp == NULL)
642 return -1; /* didn't find any conflicting entries? */
643 res->parent = parent;
644 res->child = *firstpp;
645 res->sibling = *pp;
646 *firstpp = res;
647 *pp = NULL;
648 for (p = res->child; p != NULL; p = p->sibling) {
649 p->parent = res;
650 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
651 p->name,
652 (unsigned long long)p->start,
653 (unsigned long long)p->end, res->name);
654 }
655 return 0;
656}
657
658/*
659 * Handle resources of PCI devices. If the world were perfect, we could
660 * just allocate all the resource regions and do nothing more. It isn't.
661 * On the other hand, we cannot just re-allocate all devices, as it would
662 * require us to know lots of host bridge internals. So we attempt to
663 * keep as much of the original configuration as possible, but tweak it
664 * when it's found to be wrong.
665 *
666 * Known BIOS problems we have to work around:
667 * - I/O or memory regions not configured
668 * - regions configured, but not enabled in the command register
669 * - bogus I/O addresses above 64K used
670 * - expansion ROMs left enabled (this may sound harmless, but given
671 * the fact the PCI specs explicitly allow address decoders to be
672 * shared between expansion ROMs and other resource regions, it's
673 * at least dangerous)
674 *
675 * Our solution:
676 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
677 * This gives us fixed barriers on where we can allocate.
678 * (2) Allocate resources for all enabled devices. If there is
679 * a collision, just mark the resource as unallocated. Also
680 * disable expansion ROMs during this step.
681 * (3) Try to allocate resources for disabled devices. If the
682 * resources were assigned correctly, everything goes well,
683 * if they weren't, they won't disturb allocation of other
684 * resources.
685 * (4) Assign new addresses to resources which were either
686 * not configured at all or misconfigured. If explicitly
687 * requested by the user, configure expansion ROM address
688 * as well.
689 */
690
691static void pcibios_allocate_bus_resources(struct pci_bus *bus)
692{
693 struct pci_bus *b;
694 int i;
695 struct resource *res, *pr;
696
697 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
698 pci_domain_nr(bus), bus->number);
699
700 pci_bus_for_each_resource(bus, res, i) {
701 if (!res || !res->flags
702 || res->start > res->end || res->parent)
703 continue;
704 if (bus->parent == NULL)
705 pr = (res->flags & IORESOURCE_IO) ?
706 &ioport_resource : &iomem_resource;
707 else {
708 /* Don't bother with non-root busses when
709 * re-assigning all resources. We clear the
710 * resource flags as if they were colliding
711 * and as such ensure proper re-allocation
712 * later.
713 */
714 pr = pci_find_parent_resource(bus->self, res);
715 if (pr == res) {
716 /* this happens when the generic PCI
717 * code (wrongly) decides that this
718 * bridge is transparent -- paulus
719 */
720 continue;
721 }
722 }
723
724 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
725 bus->self ? pci_name(bus->self) : "PHB",
726 bus->number, i,
727 (unsigned long long)res->start,
728 (unsigned long long)res->end);
729 pr_debug("[0x%x], parent %p (%s)\n",
730 (unsigned int)res->flags,
731 pr, (pr && pr->name) ? pr->name : "nil");
732
733 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
734 struct pci_dev *dev = bus->self;
735
736 if (request_resource(pr, res) == 0)
737 continue;
738 /*
739 * Must be a conflict with an existing entry.
740 * Move that entry (or entries) under the
741 * bridge resource and try again.
742 */
743 if (reparent_resources(pr, res) == 0)
744 continue;
745
746 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
747 pci_claim_bridge_resource(dev,
748 i + PCI_BRIDGE_RESOURCES) == 0)
749 continue;
750
751 }
752 pr_warn("PCI: Cannot allocate resource region ");
753 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
754 res->start = res->end = 0;
755 res->flags = 0;
756 }
757
758 list_for_each_entry(b, &bus->children, node)
759 pcibios_allocate_bus_resources(b);
760}
761
762static inline void alloc_resource(struct pci_dev *dev, int idx)
763{
764 struct resource *pr, *r = &dev->resource[idx];
765
766 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
767 pci_name(dev), idx,
768 (unsigned long long)r->start,
769 (unsigned long long)r->end,
770 (unsigned int)r->flags);
771
772 pr = pci_find_parent_resource(dev, r);
773 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
774 request_resource(pr, r) < 0) {
775 pr_warn("PCI: Cannot allocate resource region %d ", idx);
776 pr_cont("of device %s, will remap\n", pci_name(dev));
777 if (pr)
778 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
779 pr,
780 (unsigned long long)pr->start,
781 (unsigned long long)pr->end,
782 (unsigned int)pr->flags);
783 /* We'll assign a new address later */
784 r->flags |= IORESOURCE_UNSET;
785 r->end -= r->start;
786 r->start = 0;
787 }
788}
789
790static void __init pcibios_allocate_resources(int pass)
791{
792 struct pci_dev *dev = NULL;
793 int idx, disabled;
794 u16 command;
795 struct resource *r;
796
797 for_each_pci_dev(dev) {
798 pci_read_config_word(dev, PCI_COMMAND, &command);
799 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
800 r = &dev->resource[idx];
801 if (r->parent) /* Already allocated */
802 continue;
803 if (!r->flags || (r->flags & IORESOURCE_UNSET))
804 continue; /* Not assigned at all */
805 /* We only allocate ROMs on pass 1 just in case they
806 * have been screwed up by firmware
807 */
808 if (idx == PCI_ROM_RESOURCE)
809 disabled = 1;
810 if (r->flags & IORESOURCE_IO)
811 disabled = !(command & PCI_COMMAND_IO);
812 else
813 disabled = !(command & PCI_COMMAND_MEMORY);
814 if (pass == disabled)
815 alloc_resource(dev, idx);
816 }
817 if (pass)
818 continue;
819 r = &dev->resource[PCI_ROM_RESOURCE];
820 if (r->flags) {
821 /* Turn the ROM off, leave the resource region,
822 * but keep it unregistered.
823 */
824 u32 reg;
825 pci_read_config_dword(dev, dev->rom_base_reg, ®);
826 if (reg & PCI_ROM_ADDRESS_ENABLE) {
827 pr_debug("PCI: Switching off ROM of %s\n",
828 pci_name(dev));
829 r->flags &= ~IORESOURCE_ROM_ENABLE;
830 pci_write_config_dword(dev, dev->rom_base_reg,
831 reg & ~PCI_ROM_ADDRESS_ENABLE);
832 }
833 }
834 }
835}
836
837static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
838{
839 struct pci_controller *hose = pci_bus_to_host(bus);
840 resource_size_t offset;
841 struct resource *res, *pres;
842 int i;
843
844 pr_debug("Reserving legacy ranges for domain %04x\n",
845 pci_domain_nr(bus));
846
847 /* Check for IO */
848 if (!(hose->io_resource.flags & IORESOURCE_IO))
849 goto no_io;
850 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
851 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
852 BUG_ON(res == NULL);
853 res->name = "Legacy IO";
854 res->flags = IORESOURCE_IO;
855 res->start = offset;
856 res->end = (offset + 0xfff) & 0xfffffffful;
857 pr_debug("Candidate legacy IO: %pR\n", res);
858 if (request_resource(&hose->io_resource, res)) {
859 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
860 pci_domain_nr(bus), bus->number, res);
861 kfree(res);
862 }
863
864 no_io:
865 /* Check for memory */
866 offset = hose->pci_mem_offset;
867 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
868 for (i = 0; i < 3; i++) {
869 pres = &hose->mem_resources[i];
870 if (!(pres->flags & IORESOURCE_MEM))
871 continue;
872 pr_debug("hose mem res: %pR\n", pres);
873 if ((pres->start - offset) <= 0xa0000 &&
874 (pres->end - offset) >= 0xbffff)
875 break;
876 }
877 if (i >= 3)
878 return;
879 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
880 BUG_ON(res == NULL);
881 res->name = "Legacy VGA memory";
882 res->flags = IORESOURCE_MEM;
883 res->start = 0xa0000 + offset;
884 res->end = 0xbffff + offset;
885 pr_debug("Candidate VGA memory: %pR\n", res);
886 if (request_resource(pres, res)) {
887 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
888 pci_domain_nr(bus), bus->number, res);
889 kfree(res);
890 }
891}
892
893void __init pcibios_resource_survey(void)
894{
895 struct pci_bus *b;
896
897 /* Allocate and assign resources. If we re-assign everything, then
898 * we skip the allocate phase
899 */
900 list_for_each_entry(b, &pci_root_buses, node)
901 pcibios_allocate_bus_resources(b);
902
903 pcibios_allocate_resources(0);
904 pcibios_allocate_resources(1);
905
906 /* Before we start assigning unassigned resource, we try to reserve
907 * the low IO area and the VGA memory area if they intersect the
908 * bus available resources to avoid allocating things on top of them
909 */
910 list_for_each_entry(b, &pci_root_buses, node)
911 pcibios_reserve_legacy_regions(b);
912
913 /* Now proceed to assigning things that were left unassigned */
914 pr_debug("PCI: Assigning unassigned resources...\n");
915 pci_assign_unassigned_resources();
916}
917
918/* This is used by the PCI hotplug driver to allocate resource
919 * of newly plugged busses. We can try to consolidate with the
920 * rest of the code later, for now, keep it as-is as our main
921 * resource allocation function doesn't deal with sub-trees yet.
922 */
923void pcibios_claim_one_bus(struct pci_bus *bus)
924{
925 struct pci_dev *dev;
926 struct pci_bus *child_bus;
927
928 list_for_each_entry(dev, &bus->devices, bus_list) {
929 int i;
930
931 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
932 struct resource *r = &dev->resource[i];
933
934 if (r->parent || !r->start || !r->flags)
935 continue;
936
937 pr_debug("PCI: Claiming %s: ", pci_name(dev));
938 pr_debug("Resource %d: %016llx..%016llx [%x]\n",
939 i, (unsigned long long)r->start,
940 (unsigned long long)r->end,
941 (unsigned int)r->flags);
942
943 if (pci_claim_resource(dev, i) == 0)
944 continue;
945
946 pci_claim_bridge_resource(dev, i);
947 }
948 }
949
950 list_for_each_entry(child_bus, &bus->children, node)
951 pcibios_claim_one_bus(child_bus);
952}
953EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
954
955
956/* pcibios_finish_adding_to_bus
957 *
958 * This is to be called by the hotplug code after devices have been
959 * added to a bus, this include calling it for a PHB that is just
960 * being added
961 */
962void pcibios_finish_adding_to_bus(struct pci_bus *bus)
963{
964 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
965 pci_domain_nr(bus), bus->number);
966
967 /* Allocate bus and devices resources */
968 pcibios_allocate_bus_resources(bus);
969 pcibios_claim_one_bus(bus);
970
971 /* Add new devices to global lists. Register in proc, sysfs. */
972 pci_bus_add_devices(bus);
973
974 /* Fixup EEH */
975 /* eeh_add_device_tree_late(bus); */
976}
977EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
978
979static void pcibios_setup_phb_resources(struct pci_controller *hose,
980 struct list_head *resources)
981{
982 unsigned long io_offset;
983 struct resource *res;
984 int i;
985
986 /* Hookup PHB IO resource */
987 res = &hose->io_resource;
988
989 /* Fixup IO space offset */
990 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
991 res->start = (res->start + io_offset) & 0xffffffffu;
992 res->end = (res->end + io_offset) & 0xffffffffu;
993
994 if (!res->flags) {
995 pr_warn("PCI: I/O resource not set for host ");
996 pr_cont("bridge %pOF (domain %d)\n",
997 hose->dn, hose->global_number);
998 /* Workaround for lack of IO resource only on 32-bit */
999 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1000 res->end = res->start + IO_SPACE_LIMIT;
1001 res->flags = IORESOURCE_IO;
1002 }
1003 pci_add_resource_offset(resources, res,
1004 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
1005
1006 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1007 (unsigned long long)res->start,
1008 (unsigned long long)res->end,
1009 (unsigned long)res->flags);
1010
1011 /* Hookup PHB Memory resources */
1012 for (i = 0; i < 3; ++i) {
1013 res = &hose->mem_resources[i];
1014 if (!res->flags) {
1015 if (i > 0)
1016 continue;
1017 pr_err("PCI: Memory resource 0 not set for ");
1018 pr_cont("host bridge %pOF (domain %d)\n",
1019 hose->dn, hose->global_number);
1020
1021 /* Workaround for lack of MEM resource only on 32-bit */
1022 res->start = hose->pci_mem_offset;
1023 res->end = (resource_size_t)-1LL;
1024 res->flags = IORESOURCE_MEM;
1025
1026 }
1027 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
1028
1029 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1030 i, (unsigned long long)res->start,
1031 (unsigned long long)res->end,
1032 (unsigned long)res->flags);
1033 }
1034
1035 pr_debug("PCI: PHB MEM offset = %016llx\n",
1036 (unsigned long long)hose->pci_mem_offset);
1037 pr_debug("PCI: PHB IO offset = %08lx\n",
1038 (unsigned long)hose->io_base_virt - _IO_BASE);
1039}
1040
1041static void pcibios_scan_phb(struct pci_controller *hose)
1042{
1043 LIST_HEAD(resources);
1044 struct pci_bus *bus;
1045 struct device_node *node = hose->dn;
1046
1047 pr_debug("PCI: Scanning PHB %pOF\n", node);
1048
1049 pcibios_setup_phb_resources(hose, &resources);
1050
1051 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
1052 hose->ops, hose, &resources);
1053 if (bus == NULL) {
1054 pr_err("Failed to create bus for PCI domain %04x\n",
1055 hose->global_number);
1056 pci_free_resource_list(&resources);
1057 return;
1058 }
1059 bus->busn_res.start = hose->first_busno;
1060 hose->bus = bus;
1061
1062 hose->last_busno = bus->busn_res.end;
1063}
1064
1065static int __init pcibios_init(void)
1066{
1067 struct pci_controller *hose, *tmp;
1068 int next_busno = 0;
1069
1070 pr_info("PCI: Probing PCI hardware\n");
1071
1072 /* Scan all of the recorded PCI controllers. */
1073 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1074 hose->last_busno = 0xff;
1075 pcibios_scan_phb(hose);
1076 if (next_busno <= hose->last_busno)
1077 next_busno = hose->last_busno + 1;
1078 }
1079 pci_bus_count = next_busno;
1080
1081 /* Call common code to handle resource allocation */
1082 pcibios_resource_survey();
1083 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1084 if (hose->bus)
1085 pci_bus_add_devices(hose->bus);
1086 }
1087
1088 return 0;
1089}
1090
1091subsys_initcall(pcibios_init);
1092
1093static struct pci_controller *pci_bus_to_hose(int bus)
1094{
1095 struct pci_controller *hose, *tmp;
1096
1097 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1098 if (bus >= hose->first_busno && bus <= hose->last_busno)
1099 return hose;
1100 return NULL;
1101}
1102
1103/* Provide information on locations of various I/O regions in physical
1104 * memory. Do this on a per-card basis so that we choose the right
1105 * root bridge.
1106 * Note that the returned IO or memory base is a physical address
1107 */
1108
1109long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1110{
1111 struct pci_controller *hose;
1112 long result = -EOPNOTSUPP;
1113
1114 hose = pci_bus_to_hose(bus);
1115 if (!hose)
1116 return -ENODEV;
1117
1118 switch (which) {
1119 case IOBASE_BRIDGE_NUMBER:
1120 return (long)hose->first_busno;
1121 case IOBASE_MEMORY:
1122 return (long)hose->pci_mem_offset;
1123 case IOBASE_IO:
1124 return (long)hose->io_base_phys;
1125 case IOBASE_ISA_IO:
1126 return (long)isa_io_base;
1127 case IOBASE_ISA_MEM:
1128 return (long)isa_mem_base;
1129 }
1130
1131 return result;
1132}
1133
1134/*
1135 * Null PCI config access functions, for the case when we can't
1136 * find a hose.
1137 */
1138#define NULL_PCI_OP(rw, size, type) \
1139static int \
1140null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1141{ \
1142 return PCIBIOS_DEVICE_NOT_FOUND; \
1143}
1144
1145static int
1146null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1147 int len, u32 *val)
1148{
1149 return PCIBIOS_DEVICE_NOT_FOUND;
1150}
1151
1152static int
1153null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1154 int len, u32 val)
1155{
1156 return PCIBIOS_DEVICE_NOT_FOUND;
1157}
1158
1159static struct pci_ops null_pci_ops = {
1160 .read = null_read_config,
1161 .write = null_write_config,
1162};
1163
1164/*
1165 * These functions are used early on before PCI scanning is done
1166 * and all of the pci_dev and pci_bus structures have been created.
1167 */
1168static struct pci_bus *
1169fake_pci_bus(struct pci_controller *hose, int busnr)
1170{
1171 static struct pci_bus bus;
1172
1173 if (!hose)
1174 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1175
1176 bus.number = busnr;
1177 bus.sysdata = hose;
1178 bus.ops = hose ? hose->ops : &null_pci_ops;
1179 return &bus;
1180}
1181
1182#define EARLY_PCI_OP(rw, size, type) \
1183int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1184 int devfn, int offset, type value) \
1185{ \
1186 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1187 devfn, offset, value); \
1188}
1189
1190EARLY_PCI_OP(read, byte, u8 *)
1191EARLY_PCI_OP(read, word, u16 *)
1192EARLY_PCI_OP(read, dword, u32 *)
1193EARLY_PCI_OP(write, byte, u8)
1194EARLY_PCI_OP(write, word, u16)
1195EARLY_PCI_OP(write, dword, u32)
1196
1197int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1198 int cap)
1199{
1200 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1201}
1202
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Contains common pci routines for ALL ppc platform
4 * (based on pci_32.c and pci_64.c)
5 *
6 * Port for PPC64 David Engebretsen, IBM Corp.
7 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 *
9 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
10 * Rework, based on alpha PCI code.
11 *
12 * Common pmac/prep/chrp pci routines. -- Cort
13 */
14
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/string.h>
18#include <linux/init.h>
19#include <linux/memblock.h>
20#include <linux/mm.h>
21#include <linux/shmem_fs.h>
22#include <linux/list.h>
23#include <linux/syscalls.h>
24#include <linux/irq.h>
25#include <linux/vmalloc.h>
26#include <linux/slab.h>
27#include <linux/of.h>
28#include <linux/of_address.h>
29#include <linux/of_irq.h>
30#include <linux/of_pci.h>
31#include <linux/export.h>
32
33#include <asm/processor.h>
34#include <linux/io.h>
35#include <asm/pci-bridge.h>
36#include <asm/byteorder.h>
37
38static DEFINE_SPINLOCK(hose_spinlock);
39LIST_HEAD(hose_list);
40
41/* XXX kill that some day ... */
42static int global_phb_number; /* Global phb counter */
43
44/* ISA Memory physical address */
45resource_size_t isa_mem_base;
46
47unsigned long isa_io_base;
48EXPORT_SYMBOL(isa_io_base);
49
50static int pci_bus_count;
51
52struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
53{
54 struct pci_controller *phb;
55
56 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
57 if (!phb)
58 return NULL;
59 spin_lock(&hose_spinlock);
60 phb->global_number = global_phb_number++;
61 list_add_tail(&phb->list_node, &hose_list);
62 spin_unlock(&hose_spinlock);
63 phb->dn = dev;
64 phb->is_dynamic = mem_init_done;
65 return phb;
66}
67
68void pcibios_free_controller(struct pci_controller *phb)
69{
70 spin_lock(&hose_spinlock);
71 list_del(&phb->list_node);
72 spin_unlock(&hose_spinlock);
73
74 if (phb->is_dynamic)
75 kfree(phb);
76}
77
78static resource_size_t pcibios_io_size(const struct pci_controller *hose)
79{
80 return resource_size(&hose->io_resource);
81}
82
83int pcibios_vaddr_is_ioport(void __iomem *address)
84{
85 int ret = 0;
86 struct pci_controller *hose;
87 resource_size_t size;
88
89 spin_lock(&hose_spinlock);
90 list_for_each_entry(hose, &hose_list, list_node) {
91 size = pcibios_io_size(hose);
92 if (address >= hose->io_base_virt &&
93 address < (hose->io_base_virt + size)) {
94 ret = 1;
95 break;
96 }
97 }
98 spin_unlock(&hose_spinlock);
99 return ret;
100}
101
102unsigned long pci_address_to_pio(phys_addr_t address)
103{
104 struct pci_controller *hose;
105 resource_size_t size;
106 unsigned long ret = ~0;
107
108 spin_lock(&hose_spinlock);
109 list_for_each_entry(hose, &hose_list, list_node) {
110 size = pcibios_io_size(hose);
111 if (address >= hose->io_base_phys &&
112 address < (hose->io_base_phys + size)) {
113 unsigned long base =
114 (unsigned long)hose->io_base_virt - _IO_BASE;
115 ret = base + (address - hose->io_base_phys);
116 break;
117 }
118 }
119 spin_unlock(&hose_spinlock);
120
121 return ret;
122}
123EXPORT_SYMBOL_GPL(pci_address_to_pio);
124
125/* This routine is meant to be used early during boot, when the
126 * PCI bus numbers have not yet been assigned, and you need to
127 * issue PCI config cycles to an OF device.
128 * It could also be used to "fix" RTAS config cycles if you want
129 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
130 * config cycles.
131 */
132struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
133{
134 while (node) {
135 struct pci_controller *hose, *tmp;
136 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
137 if (hose->dn == node)
138 return hose;
139 node = node->parent;
140 }
141 return NULL;
142}
143
144void pcibios_set_master(struct pci_dev *dev)
145{
146 /* No special bus mastering setup handling */
147}
148
149/*
150 * Platform support for /proc/bus/pci/X/Y mmap()s.
151 */
152
153int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
154{
155 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
156 resource_size_t ioaddr = pci_resource_start(pdev, bar);
157
158 if (!hose)
159 return -EINVAL; /* should never happen */
160
161 /* Convert to an offset within this PCI controller */
162 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
163
164 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
165 return 0;
166}
167
168/*
169 * This one is used by /dev/mem and fbdev who have no clue about the
170 * PCI device, it tries to find the PCI device first and calls the
171 * above routine
172 */
173pgprot_t pci_phys_mem_access_prot(struct file *file,
174 unsigned long pfn,
175 unsigned long size,
176 pgprot_t prot)
177{
178 struct pci_dev *pdev = NULL;
179 struct resource *found = NULL;
180 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
181 int i;
182
183 if (page_is_ram(pfn))
184 return prot;
185
186 prot = pgprot_noncached(prot);
187 for_each_pci_dev(pdev) {
188 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
189 struct resource *rp = &pdev->resource[i];
190 int flags = rp->flags;
191
192 /* Active and same type? */
193 if ((flags & IORESOURCE_MEM) == 0)
194 continue;
195 /* In the range of this resource? */
196 if (offset < (rp->start & PAGE_MASK) ||
197 offset > rp->end)
198 continue;
199 found = rp;
200 break;
201 }
202 if (found)
203 break;
204 }
205 if (found) {
206 if (found->flags & IORESOURCE_PREFETCH)
207 prot = pgprot_noncached_wc(prot);
208 pci_dev_put(pdev);
209 }
210
211 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
212 (unsigned long long)offset, pgprot_val(prot));
213
214 return prot;
215}
216
217/* This provides legacy IO read access on a bus */
218int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
219{
220 unsigned long offset;
221 struct pci_controller *hose = pci_bus_to_host(bus);
222 struct resource *rp = &hose->io_resource;
223 void __iomem *addr;
224
225 /* Check if port can be supported by that bus. We only check
226 * the ranges of the PHB though, not the bus itself as the rules
227 * for forwarding legacy cycles down bridges are not our problem
228 * here. So if the host bridge supports it, we do it.
229 */
230 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
231 offset += port;
232
233 if (!(rp->flags & IORESOURCE_IO))
234 return -ENXIO;
235 if (offset < rp->start || (offset + size) > rp->end)
236 return -ENXIO;
237 addr = hose->io_base_virt + port;
238
239 switch (size) {
240 case 1:
241 *((u8 *)val) = in_8(addr);
242 return 1;
243 case 2:
244 if (port & 1)
245 return -EINVAL;
246 *((u16 *)val) = in_le16(addr);
247 return 2;
248 case 4:
249 if (port & 3)
250 return -EINVAL;
251 *((u32 *)val) = in_le32(addr);
252 return 4;
253 }
254 return -EINVAL;
255}
256
257/* This provides legacy IO write access on a bus */
258int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
259{
260 unsigned long offset;
261 struct pci_controller *hose = pci_bus_to_host(bus);
262 struct resource *rp = &hose->io_resource;
263 void __iomem *addr;
264
265 /* Check if port can be supported by that bus. We only check
266 * the ranges of the PHB though, not the bus itself as the rules
267 * for forwarding legacy cycles down bridges are not our problem
268 * here. So if the host bridge supports it, we do it.
269 */
270 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
271 offset += port;
272
273 if (!(rp->flags & IORESOURCE_IO))
274 return -ENXIO;
275 if (offset < rp->start || (offset + size) > rp->end)
276 return -ENXIO;
277 addr = hose->io_base_virt + port;
278
279 /* WARNING: The generic code is idiotic. It gets passed a pointer
280 * to what can be a 1, 2 or 4 byte quantity and always reads that
281 * as a u32, which means that we have to correct the location of
282 * the data read within those 32 bits for size 1 and 2
283 */
284 switch (size) {
285 case 1:
286 out_8(addr, val >> 24);
287 return 1;
288 case 2:
289 if (port & 1)
290 return -EINVAL;
291 out_le16(addr, val >> 16);
292 return 2;
293 case 4:
294 if (port & 3)
295 return -EINVAL;
296 out_le32(addr, val);
297 return 4;
298 }
299 return -EINVAL;
300}
301
302/* This provides legacy IO or memory mmap access on a bus */
303int pci_mmap_legacy_page_range(struct pci_bus *bus,
304 struct vm_area_struct *vma,
305 enum pci_mmap_state mmap_state)
306{
307 struct pci_controller *hose = pci_bus_to_host(bus);
308 resource_size_t offset =
309 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
310 resource_size_t size = vma->vm_end - vma->vm_start;
311 struct resource *rp;
312
313 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
314 pci_domain_nr(bus), bus->number,
315 mmap_state == pci_mmap_mem ? "MEM" : "IO",
316 (unsigned long long)offset,
317 (unsigned long long)(offset + size - 1));
318
319 if (mmap_state == pci_mmap_mem) {
320 /* Hack alert !
321 *
322 * Because X is lame and can fail starting if it gets an error
323 * trying to mmap legacy_mem (instead of just moving on without
324 * legacy memory access) we fake it here by giving it anonymous
325 * memory, effectively behaving just like /dev/zero
326 */
327 if ((offset + size) > hose->isa_mem_size) {
328#ifdef CONFIG_MMU
329 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
330 current->comm, current->pid);
331 pr_debug("legacy memory for 0%04x:%02x\n",
332 pci_domain_nr(bus), bus->number);
333#endif
334 if (vma->vm_flags & VM_SHARED)
335 return shmem_zero_setup(vma);
336 return 0;
337 }
338 offset += hose->isa_mem_phys;
339 } else {
340 unsigned long io_offset = (unsigned long)hose->io_base_virt -
341 _IO_BASE;
342 unsigned long roffset = offset + io_offset;
343 rp = &hose->io_resource;
344 if (!(rp->flags & IORESOURCE_IO))
345 return -ENXIO;
346 if (roffset < rp->start || (roffset + size) > rp->end)
347 return -ENXIO;
348 offset += hose->io_base_phys;
349 }
350 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
351
352 vma->vm_pgoff = offset >> PAGE_SHIFT;
353 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
354 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
355 vma->vm_end - vma->vm_start,
356 vma->vm_page_prot);
357}
358
359void pci_resource_to_user(const struct pci_dev *dev, int bar,
360 const struct resource *rsrc,
361 resource_size_t *start, resource_size_t *end)
362{
363 struct pci_bus_region region;
364
365 if (rsrc->flags & IORESOURCE_IO) {
366 pcibios_resource_to_bus(dev->bus, ®ion,
367 (struct resource *) rsrc);
368 *start = region.start;
369 *end = region.end;
370 return;
371 }
372
373 /* We pass a CPU physical address to userland for MMIO instead of a
374 * BAR value because X is lame and expects to be able to use that
375 * to pass to /dev/mem!
376 *
377 * That means we may have 64-bit values where some apps only expect
378 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
379 */
380 *start = rsrc->start;
381 *end = rsrc->end;
382}
383
384/**
385 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
386 * @hose: newly allocated pci_controller to be setup
387 * @dev: device node of the host bridge
388 * @primary: set if primary bus (32 bits only, soon to be deprecated)
389 *
390 * This function will parse the "ranges" property of a PCI host bridge device
391 * node and setup the resource mapping of a pci controller based on its
392 * content.
393 *
394 * Life would be boring if it wasn't for a few issues that we have to deal
395 * with here:
396 *
397 * - We can only cope with one IO space range and up to 3 Memory space
398 * ranges. However, some machines (thanks Apple !) tend to split their
399 * space into lots of small contiguous ranges. So we have to coalesce.
400 *
401 * - We can only cope with all memory ranges having the same offset
402 * between CPU addresses and PCI addresses. Unfortunately, some bridges
403 * are setup for a large 1:1 mapping along with a small "window" which
404 * maps PCI address 0 to some arbitrary high address of the CPU space in
405 * order to give access to the ISA memory hole.
406 * The way out of here that I've chosen for now is to always set the
407 * offset based on the first resource found, then override it if we
408 * have a different offset and the previous was set by an ISA hole.
409 *
410 * - Some busses have IO space not starting at 0, which causes trouble with
411 * the way we do our IO resource renumbering. The code somewhat deals with
412 * it for 64 bits but I would expect problems on 32 bits.
413 *
414 * - Some 32 bits platforms such as 4xx can have physical space larger than
415 * 32 bits so we need to use 64 bits values for the parsing
416 */
417void pci_process_bridge_OF_ranges(struct pci_controller *hose,
418 struct device_node *dev, int primary)
419{
420 int memno = 0, isa_hole = -1;
421 unsigned long long isa_mb = 0;
422 struct resource *res;
423 struct of_pci_range range;
424 struct of_pci_range_parser parser;
425
426 pr_info("PCI host bridge %pOF %s ranges:\n",
427 dev, primary ? "(primary)" : "");
428
429 /* Check for ranges property */
430 if (of_pci_range_parser_init(&parser, dev))
431 return;
432
433 pr_debug("Parsing ranges property...\n");
434 for_each_of_pci_range(&parser, &range) {
435 /* Read next ranges element */
436
437 /* If we failed translation or got a zero-sized region
438 * (some FW try to feed us with non sensical zero sized regions
439 * such as power3 which look like some kind of attempt
440 * at exposing the VGA memory hole)
441 */
442 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
443 continue;
444
445 /* Act based on address space type */
446 res = NULL;
447 switch (range.flags & IORESOURCE_TYPE_BITS) {
448 case IORESOURCE_IO:
449 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
450 range.cpu_addr, range.cpu_addr + range.size - 1,
451 range.pci_addr);
452
453 /* We support only one IO range */
454 if (hose->pci_io_size) {
455 pr_info(" \\--> Skipped (too many) !\n");
456 continue;
457 }
458 /* On 32 bits, limit I/O space to 16MB */
459 if (range.size > 0x01000000)
460 range.size = 0x01000000;
461
462 /* 32 bits needs to map IOs here */
463 hose->io_base_virt = ioremap(range.cpu_addr,
464 range.size);
465
466 /* Expect trouble if pci_addr is not 0 */
467 if (primary)
468 isa_io_base =
469 (unsigned long)hose->io_base_virt;
470 /* pci_io_size and io_base_phys always represent IO
471 * space starting at 0 so we factor in pci_addr
472 */
473 hose->pci_io_size = range.pci_addr + range.size;
474 hose->io_base_phys = range.cpu_addr - range.pci_addr;
475
476 /* Build resource */
477 res = &hose->io_resource;
478 range.cpu_addr = range.pci_addr;
479
480 break;
481 case IORESOURCE_MEM:
482 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
483 range.cpu_addr, range.cpu_addr + range.size - 1,
484 range.pci_addr,
485 (range.flags & IORESOURCE_PREFETCH) ?
486 "Prefetch" : "");
487
488 /* We support only 3 memory ranges */
489 if (memno >= 3) {
490 pr_info(" \\--> Skipped (too many) !\n");
491 continue;
492 }
493 /* Handles ISA memory hole space here */
494 if (range.pci_addr == 0) {
495 isa_mb = range.cpu_addr;
496 isa_hole = memno;
497 if (primary || isa_mem_base == 0)
498 isa_mem_base = range.cpu_addr;
499 hose->isa_mem_phys = range.cpu_addr;
500 hose->isa_mem_size = range.size;
501 }
502
503 /* We get the PCI/Mem offset from the first range or
504 * the, current one if the offset came from an ISA
505 * hole. If they don't match, bugger.
506 */
507 if (memno == 0 ||
508 (isa_hole >= 0 && range.pci_addr != 0 &&
509 hose->pci_mem_offset == isa_mb))
510 hose->pci_mem_offset = range.cpu_addr -
511 range.pci_addr;
512 else if (range.pci_addr != 0 &&
513 hose->pci_mem_offset != range.cpu_addr -
514 range.pci_addr) {
515 pr_info(" \\--> Skipped (offset mismatch) !\n");
516 continue;
517 }
518
519 /* Build resource */
520 res = &hose->mem_resources[memno++];
521 break;
522 }
523 if (res != NULL) {
524 res->name = dev->full_name;
525 res->flags = range.flags;
526 res->start = range.cpu_addr;
527 res->end = range.cpu_addr + range.size - 1;
528 res->parent = res->child = res->sibling = NULL;
529 }
530 }
531
532 /* If there's an ISA hole and the pci_mem_offset is -not- matching
533 * the ISA hole offset, then we need to remove the ISA hole from
534 * the resource list for that brige
535 */
536 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
537 unsigned int next = isa_hole + 1;
538 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
539 if (next < memno)
540 memmove(&hose->mem_resources[isa_hole],
541 &hose->mem_resources[next],
542 sizeof(struct resource) * (memno - next));
543 hose->mem_resources[--memno].flags = 0;
544 }
545}
546
547/* Display the domain number in /proc */
548int pci_proc_domain(struct pci_bus *bus)
549{
550 return pci_domain_nr(bus);
551}
552
553/* This header fixup will do the resource fixup for all devices as they are
554 * probed, but not for bridge ranges
555 */
556static void pcibios_fixup_resources(struct pci_dev *dev)
557{
558 struct pci_controller *hose = pci_bus_to_host(dev->bus);
559 int i;
560
561 if (!hose) {
562 pr_err("No host bridge for PCI dev %s !\n",
563 pci_name(dev));
564 return;
565 }
566 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
567 struct resource *res = dev->resource + i;
568 if (!res->flags)
569 continue;
570 if (res->start == 0) {
571 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
572 pci_name(dev), i,
573 (unsigned long long)res->start,
574 (unsigned long long)res->end,
575 (unsigned int)res->flags);
576 pr_debug("is unassigned\n");
577 res->end -= res->start;
578 res->start = 0;
579 res->flags |= IORESOURCE_UNSET;
580 continue;
581 }
582
583 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
584 pci_name(dev), i,
585 (unsigned long long)res->start,
586 (unsigned long long)res->end,
587 (unsigned int)res->flags);
588 }
589}
590DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
591
592int pcibios_add_device(struct pci_dev *dev)
593{
594 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
595
596 return 0;
597}
598EXPORT_SYMBOL(pcibios_add_device);
599
600/*
601 * Reparent resource children of pr that conflict with res
602 * under res, and make res replace those children.
603 */
604static int __init reparent_resources(struct resource *parent,
605 struct resource *res)
606{
607 struct resource *p, **pp;
608 struct resource **firstpp = NULL;
609
610 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
611 if (p->end < res->start)
612 continue;
613 if (res->end < p->start)
614 break;
615 if (p->start < res->start || p->end > res->end)
616 return -1; /* not completely contained */
617 if (firstpp == NULL)
618 firstpp = pp;
619 }
620 if (firstpp == NULL)
621 return -1; /* didn't find any conflicting entries? */
622 res->parent = parent;
623 res->child = *firstpp;
624 res->sibling = *pp;
625 *firstpp = res;
626 *pp = NULL;
627 for (p = res->child; p != NULL; p = p->sibling) {
628 p->parent = res;
629 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
630 p->name,
631 (unsigned long long)p->start,
632 (unsigned long long)p->end, res->name);
633 }
634 return 0;
635}
636
637/*
638 * Handle resources of PCI devices. If the world were perfect, we could
639 * just allocate all the resource regions and do nothing more. It isn't.
640 * On the other hand, we cannot just re-allocate all devices, as it would
641 * require us to know lots of host bridge internals. So we attempt to
642 * keep as much of the original configuration as possible, but tweak it
643 * when it's found to be wrong.
644 *
645 * Known BIOS problems we have to work around:
646 * - I/O or memory regions not configured
647 * - regions configured, but not enabled in the command register
648 * - bogus I/O addresses above 64K used
649 * - expansion ROMs left enabled (this may sound harmless, but given
650 * the fact the PCI specs explicitly allow address decoders to be
651 * shared between expansion ROMs and other resource regions, it's
652 * at least dangerous)
653 *
654 * Our solution:
655 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
656 * This gives us fixed barriers on where we can allocate.
657 * (2) Allocate resources for all enabled devices. If there is
658 * a collision, just mark the resource as unallocated. Also
659 * disable expansion ROMs during this step.
660 * (3) Try to allocate resources for disabled devices. If the
661 * resources were assigned correctly, everything goes well,
662 * if they weren't, they won't disturb allocation of other
663 * resources.
664 * (4) Assign new addresses to resources which were either
665 * not configured at all or misconfigured. If explicitly
666 * requested by the user, configure expansion ROM address
667 * as well.
668 */
669
670static void pcibios_allocate_bus_resources(struct pci_bus *bus)
671{
672 struct pci_bus *b;
673 int i;
674 struct resource *res, *pr;
675
676 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
677 pci_domain_nr(bus), bus->number);
678
679 pci_bus_for_each_resource(bus, res, i) {
680 if (!res || !res->flags
681 || res->start > res->end || res->parent)
682 continue;
683 if (bus->parent == NULL)
684 pr = (res->flags & IORESOURCE_IO) ?
685 &ioport_resource : &iomem_resource;
686 else {
687 /* Don't bother with non-root busses when
688 * re-assigning all resources. We clear the
689 * resource flags as if they were colliding
690 * and as such ensure proper re-allocation
691 * later.
692 */
693 pr = pci_find_parent_resource(bus->self, res);
694 if (pr == res) {
695 /* this happens when the generic PCI
696 * code (wrongly) decides that this
697 * bridge is transparent -- paulus
698 */
699 continue;
700 }
701 }
702
703 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
704 bus->self ? pci_name(bus->self) : "PHB",
705 bus->number, i,
706 (unsigned long long)res->start,
707 (unsigned long long)res->end);
708 pr_debug("[0x%x], parent %p (%s)\n",
709 (unsigned int)res->flags,
710 pr, (pr && pr->name) ? pr->name : "nil");
711
712 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
713 struct pci_dev *dev = bus->self;
714
715 if (request_resource(pr, res) == 0)
716 continue;
717 /*
718 * Must be a conflict with an existing entry.
719 * Move that entry (or entries) under the
720 * bridge resource and try again.
721 */
722 if (reparent_resources(pr, res) == 0)
723 continue;
724
725 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
726 pci_claim_bridge_resource(dev,
727 i + PCI_BRIDGE_RESOURCES) == 0)
728 continue;
729
730 }
731 pr_warn("PCI: Cannot allocate resource region ");
732 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
733 res->start = res->end = 0;
734 res->flags = 0;
735 }
736
737 list_for_each_entry(b, &bus->children, node)
738 pcibios_allocate_bus_resources(b);
739}
740
741static inline void alloc_resource(struct pci_dev *dev, int idx)
742{
743 struct resource *pr, *r = &dev->resource[idx];
744
745 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
746 pci_name(dev), idx,
747 (unsigned long long)r->start,
748 (unsigned long long)r->end,
749 (unsigned int)r->flags);
750
751 pr = pci_find_parent_resource(dev, r);
752 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
753 request_resource(pr, r) < 0) {
754 pr_warn("PCI: Cannot allocate resource region %d ", idx);
755 pr_cont("of device %s, will remap\n", pci_name(dev));
756 if (pr)
757 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
758 pr,
759 (unsigned long long)pr->start,
760 (unsigned long long)pr->end,
761 (unsigned int)pr->flags);
762 /* We'll assign a new address later */
763 r->flags |= IORESOURCE_UNSET;
764 r->end -= r->start;
765 r->start = 0;
766 }
767}
768
769static void __init pcibios_allocate_resources(int pass)
770{
771 struct pci_dev *dev = NULL;
772 int idx, disabled;
773 u16 command;
774 struct resource *r;
775
776 for_each_pci_dev(dev) {
777 pci_read_config_word(dev, PCI_COMMAND, &command);
778 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
779 r = &dev->resource[idx];
780 if (r->parent) /* Already allocated */
781 continue;
782 if (!r->flags || (r->flags & IORESOURCE_UNSET))
783 continue; /* Not assigned at all */
784 /* We only allocate ROMs on pass 1 just in case they
785 * have been screwed up by firmware
786 */
787 if (idx == PCI_ROM_RESOURCE)
788 disabled = 1;
789 if (r->flags & IORESOURCE_IO)
790 disabled = !(command & PCI_COMMAND_IO);
791 else
792 disabled = !(command & PCI_COMMAND_MEMORY);
793 if (pass == disabled)
794 alloc_resource(dev, idx);
795 }
796 if (pass)
797 continue;
798 r = &dev->resource[PCI_ROM_RESOURCE];
799 if (r->flags) {
800 /* Turn the ROM off, leave the resource region,
801 * but keep it unregistered.
802 */
803 u32 reg;
804 pci_read_config_dword(dev, dev->rom_base_reg, ®);
805 if (reg & PCI_ROM_ADDRESS_ENABLE) {
806 pr_debug("PCI: Switching off ROM of %s\n",
807 pci_name(dev));
808 r->flags &= ~IORESOURCE_ROM_ENABLE;
809 pci_write_config_dword(dev, dev->rom_base_reg,
810 reg & ~PCI_ROM_ADDRESS_ENABLE);
811 }
812 }
813 }
814}
815
816static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
817{
818 struct pci_controller *hose = pci_bus_to_host(bus);
819 resource_size_t offset;
820 struct resource *res, *pres;
821 int i;
822
823 pr_debug("Reserving legacy ranges for domain %04x\n",
824 pci_domain_nr(bus));
825
826 /* Check for IO */
827 if (!(hose->io_resource.flags & IORESOURCE_IO))
828 goto no_io;
829 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
830 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
831 BUG_ON(res == NULL);
832 res->name = "Legacy IO";
833 res->flags = IORESOURCE_IO;
834 res->start = offset;
835 res->end = (offset + 0xfff) & 0xfffffffful;
836 pr_debug("Candidate legacy IO: %pR\n", res);
837 if (request_resource(&hose->io_resource, res)) {
838 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
839 pci_domain_nr(bus), bus->number, res);
840 kfree(res);
841 }
842
843 no_io:
844 /* Check for memory */
845 offset = hose->pci_mem_offset;
846 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
847 for (i = 0; i < 3; i++) {
848 pres = &hose->mem_resources[i];
849 if (!(pres->flags & IORESOURCE_MEM))
850 continue;
851 pr_debug("hose mem res: %pR\n", pres);
852 if ((pres->start - offset) <= 0xa0000 &&
853 (pres->end - offset) >= 0xbffff)
854 break;
855 }
856 if (i >= 3)
857 return;
858 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
859 BUG_ON(res == NULL);
860 res->name = "Legacy VGA memory";
861 res->flags = IORESOURCE_MEM;
862 res->start = 0xa0000 + offset;
863 res->end = 0xbffff + offset;
864 pr_debug("Candidate VGA memory: %pR\n", res);
865 if (request_resource(pres, res)) {
866 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
867 pci_domain_nr(bus), bus->number, res);
868 kfree(res);
869 }
870}
871
872void __init pcibios_resource_survey(void)
873{
874 struct pci_bus *b;
875
876 /* Allocate and assign resources. If we re-assign everything, then
877 * we skip the allocate phase
878 */
879 list_for_each_entry(b, &pci_root_buses, node)
880 pcibios_allocate_bus_resources(b);
881
882 pcibios_allocate_resources(0);
883 pcibios_allocate_resources(1);
884
885 /* Before we start assigning unassigned resource, we try to reserve
886 * the low IO area and the VGA memory area if they intersect the
887 * bus available resources to avoid allocating things on top of them
888 */
889 list_for_each_entry(b, &pci_root_buses, node)
890 pcibios_reserve_legacy_regions(b);
891
892 /* Now proceed to assigning things that were left unassigned */
893 pr_debug("PCI: Assigning unassigned resources...\n");
894 pci_assign_unassigned_resources();
895}
896
897static void pcibios_setup_phb_resources(struct pci_controller *hose,
898 struct list_head *resources)
899{
900 unsigned long io_offset;
901 struct resource *res;
902 int i;
903
904 /* Hookup PHB IO resource */
905 res = &hose->io_resource;
906
907 /* Fixup IO space offset */
908 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
909 res->start = (res->start + io_offset) & 0xffffffffu;
910 res->end = (res->end + io_offset) & 0xffffffffu;
911
912 if (!res->flags) {
913 pr_warn("PCI: I/O resource not set for host ");
914 pr_cont("bridge %pOF (domain %d)\n",
915 hose->dn, hose->global_number);
916 /* Workaround for lack of IO resource only on 32-bit */
917 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
918 res->end = res->start + IO_SPACE_LIMIT;
919 res->flags = IORESOURCE_IO;
920 }
921 pci_add_resource_offset(resources, res,
922 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
923
924 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
925 (unsigned long long)res->start,
926 (unsigned long long)res->end,
927 (unsigned long)res->flags);
928
929 /* Hookup PHB Memory resources */
930 for (i = 0; i < 3; ++i) {
931 res = &hose->mem_resources[i];
932 if (!res->flags) {
933 if (i > 0)
934 continue;
935 pr_err("PCI: Memory resource 0 not set for ");
936 pr_cont("host bridge %pOF (domain %d)\n",
937 hose->dn, hose->global_number);
938
939 /* Workaround for lack of MEM resource only on 32-bit */
940 res->start = hose->pci_mem_offset;
941 res->end = (resource_size_t)-1LL;
942 res->flags = IORESOURCE_MEM;
943
944 }
945 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
946
947 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
948 i, (unsigned long long)res->start,
949 (unsigned long long)res->end,
950 (unsigned long)res->flags);
951 }
952
953 pr_debug("PCI: PHB MEM offset = %016llx\n",
954 (unsigned long long)hose->pci_mem_offset);
955 pr_debug("PCI: PHB IO offset = %08lx\n",
956 (unsigned long)hose->io_base_virt - _IO_BASE);
957}
958
959static void pcibios_scan_phb(struct pci_controller *hose)
960{
961 LIST_HEAD(resources);
962 struct pci_bus *bus;
963 struct device_node *node = hose->dn;
964
965 pr_debug("PCI: Scanning PHB %pOF\n", node);
966
967 pcibios_setup_phb_resources(hose, &resources);
968
969 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
970 hose->ops, hose, &resources);
971 if (bus == NULL) {
972 pr_err("Failed to create bus for PCI domain %04x\n",
973 hose->global_number);
974 pci_free_resource_list(&resources);
975 return;
976 }
977 bus->busn_res.start = hose->first_busno;
978 hose->bus = bus;
979
980 hose->last_busno = bus->busn_res.end;
981}
982
983static int __init pcibios_init(void)
984{
985 struct pci_controller *hose, *tmp;
986 int next_busno = 0;
987
988 pr_info("PCI: Probing PCI hardware\n");
989
990 /* Scan all of the recorded PCI controllers. */
991 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
992 hose->last_busno = 0xff;
993 pcibios_scan_phb(hose);
994 if (next_busno <= hose->last_busno)
995 next_busno = hose->last_busno + 1;
996 }
997 pci_bus_count = next_busno;
998
999 /* Call common code to handle resource allocation */
1000 pcibios_resource_survey();
1001 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1002 if (hose->bus)
1003 pci_bus_add_devices(hose->bus);
1004 }
1005
1006 return 0;
1007}
1008
1009subsys_initcall(pcibios_init);
1010
1011static struct pci_controller *pci_bus_to_hose(int bus)
1012{
1013 struct pci_controller *hose, *tmp;
1014
1015 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1016 if (bus >= hose->first_busno && bus <= hose->last_busno)
1017 return hose;
1018 return NULL;
1019}
1020
1021/* Provide information on locations of various I/O regions in physical
1022 * memory. Do this on a per-card basis so that we choose the right
1023 * root bridge.
1024 * Note that the returned IO or memory base is a physical address
1025 */
1026
1027long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1028{
1029 struct pci_controller *hose;
1030 long result = -EOPNOTSUPP;
1031
1032 hose = pci_bus_to_hose(bus);
1033 if (!hose)
1034 return -ENODEV;
1035
1036 switch (which) {
1037 case IOBASE_BRIDGE_NUMBER:
1038 return (long)hose->first_busno;
1039 case IOBASE_MEMORY:
1040 return (long)hose->pci_mem_offset;
1041 case IOBASE_IO:
1042 return (long)hose->io_base_phys;
1043 case IOBASE_ISA_IO:
1044 return (long)isa_io_base;
1045 case IOBASE_ISA_MEM:
1046 return (long)isa_mem_base;
1047 }
1048
1049 return result;
1050}
1051
1052/*
1053 * Null PCI config access functions, for the case when we can't
1054 * find a hose.
1055 */
1056#define NULL_PCI_OP(rw, size, type) \
1057static int \
1058null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1059{ \
1060 return PCIBIOS_DEVICE_NOT_FOUND; \
1061}
1062
1063static int
1064null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1065 int len, u32 *val)
1066{
1067 return PCIBIOS_DEVICE_NOT_FOUND;
1068}
1069
1070static int
1071null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1072 int len, u32 val)
1073{
1074 return PCIBIOS_DEVICE_NOT_FOUND;
1075}
1076
1077static struct pci_ops null_pci_ops = {
1078 .read = null_read_config,
1079 .write = null_write_config,
1080};
1081
1082/*
1083 * These functions are used early on before PCI scanning is done
1084 * and all of the pci_dev and pci_bus structures have been created.
1085 */
1086static struct pci_bus *
1087fake_pci_bus(struct pci_controller *hose, int busnr)
1088{
1089 static struct pci_bus bus;
1090
1091 if (!hose)
1092 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1093
1094 bus.number = busnr;
1095 bus.sysdata = hose;
1096 bus.ops = hose ? hose->ops : &null_pci_ops;
1097 return &bus;
1098}
1099
1100#define EARLY_PCI_OP(rw, size, type) \
1101int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1102 int devfn, int offset, type value) \
1103{ \
1104 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1105 devfn, offset, value); \
1106}
1107
1108EARLY_PCI_OP(read, byte, u8 *)
1109EARLY_PCI_OP(read, word, u16 *)
1110EARLY_PCI_OP(read, dword, u32 *)
1111EARLY_PCI_OP(write, byte, u8)
1112EARLY_PCI_OP(write, word, u16)
1113EARLY_PCI_OP(write, dword, u32)
1114
1115int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1116 int cap)
1117{
1118 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1119}