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1# SPDX-License-Identifier: GPL-2.0
2#
3# For a description of the syntax of this configuration file,
4# see Documentation/kbuild/kconfig-language.txt.
5#
6
7config OPENRISC
8 def_bool y
9 select OF
10 select OF_EARLY_FLATTREE
11 select IRQ_DOMAIN
12 select HANDLE_DOMAIN_IRQ
13 select HAVE_MEMBLOCK
14 select GPIOLIB
15 select HAVE_ARCH_TRACEHOOK
16 select SPARSE_IRQ
17 select GENERIC_IRQ_CHIP
18 select GENERIC_IRQ_PROBE
19 select GENERIC_IRQ_SHOW
20 select GENERIC_IOMAP
21 select GENERIC_CPU_DEVICES
22 select HAVE_UID16
23 select GENERIC_ATOMIC64
24 select GENERIC_CLOCKEVENTS
25 select GENERIC_CLOCKEVENTS_BROADCAST
26 select GENERIC_STRNCPY_FROM_USER
27 select GENERIC_STRNLEN_USER
28 select GENERIC_SMP_IDLE_THREAD
29 select MODULES_USE_ELF_RELA
30 select MULTI_IRQ_HANDLER
31 select HAVE_DEBUG_STACKOVERFLOW
32 select OR1K_PIC
33 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
34 select NO_BOOTMEM
35 select ARCH_USE_QUEUED_SPINLOCKS
36 select ARCH_USE_QUEUED_RWLOCKS
37 select OMPIC if SMP
38 select ARCH_WANT_FRAME_POINTERS
39
40config CPU_BIG_ENDIAN
41 def_bool y
42
43config MMU
44 def_bool y
45
46config RWSEM_GENERIC_SPINLOCK
47 def_bool y
48
49config RWSEM_XCHGADD_ALGORITHM
50 def_bool n
51
52config GENERIC_HWEIGHT
53 def_bool y
54
55config NO_IOPORT_MAP
56 def_bool y
57
58config TRACE_IRQFLAGS_SUPPORT
59 def_bool y
60
61# For now, use generic checksum functions
62#These can be reimplemented in assembly later if so inclined
63config GENERIC_CSUM
64 def_bool y
65
66config STACKTRACE_SUPPORT
67 def_bool y
68
69config LOCKDEP_SUPPORT
70 def_bool y
71
72config MULTI_IRQ_HANDLER
73 def_bool y
74
75source "init/Kconfig"
76
77source "kernel/Kconfig.freezer"
78
79menu "Processor type and features"
80
81choice
82 prompt "Subarchitecture"
83 default OR1K_1200
84
85config OR1K_1200
86 bool "OR1200"
87 help
88 Generic OpenRISC 1200 architecture
89
90endchoice
91
92config DCACHE_WRITETHROUGH
93 bool "Have write through data caches"
94 default n
95 help
96 Select this if your implementation features write through data caches.
97 Selecting 'N' here will allow the kernel to force flushing of data
98 caches at relevant times. Most OpenRISC implementations support write-
99 through data caches.
100
101 If unsure say N here
102
103config OPENRISC_BUILTIN_DTB
104 string "Builtin DTB"
105 default ""
106
107menu "Class II Instructions"
108
109config OPENRISC_HAVE_INST_FF1
110 bool "Have instruction l.ff1"
111 default y
112 help
113 Select this if your implementation has the Class II instruction l.ff1
114
115config OPENRISC_HAVE_INST_FL1
116 bool "Have instruction l.fl1"
117 default y
118 help
119 Select this if your implementation has the Class II instruction l.fl1
120
121config OPENRISC_HAVE_INST_MUL
122 bool "Have instruction l.mul for hardware multiply"
123 default y
124 help
125 Select this if your implementation has a hardware multiply instruction
126
127config OPENRISC_HAVE_INST_DIV
128 bool "Have instruction l.div for hardware divide"
129 default y
130 help
131 Select this if your implementation has a hardware divide instruction
132endmenu
133
134config NR_CPUS
135 int "Maximum number of CPUs (2-32)"
136 range 2 32
137 depends on SMP
138 default "2"
139
140config SMP
141 bool "Symmetric Multi-Processing support"
142 help
143 This enables support for systems with more than one CPU. If you have
144 a system with only one CPU, say N. If you have a system with more
145 than one CPU, say Y.
146
147 If you don't know what to do here, say N.
148
149source kernel/Kconfig.hz
150source kernel/Kconfig.preempt
151source "mm/Kconfig"
152
153config OPENRISC_NO_SPR_SR_DSX
154 bool "use SPR_SR_DSX software emulation" if OR1K_1200
155 default y
156 help
157 SPR_SR_DSX bit is status register bit indicating whether
158 the last exception has happened in delay slot.
159
160 OpenRISC architecture makes it optional to have it implemented
161 in hardware and the OR1200 does not have it.
162
163 Say N here if you know that your OpenRISC processor has
164 SPR_SR_DSX bit implemented. Say Y if you are unsure.
165
166config OPENRISC_HAVE_SHADOW_GPRS
167 bool "Support for shadow gpr files" if !SMP
168 default y if SMP
169 help
170 Say Y here if your OpenRISC processor features shadowed
171 register files. They will in such case be used as a
172 scratch reg storage on exception entry.
173
174 On SMP systems, this feature is mandatory.
175 On a unicore system it's safe to say N here if you are unsure.
176
177config CMDLINE
178 string "Default kernel command string"
179 default ""
180 help
181 On some architectures there is currently no way for the boot loader
182 to pass arguments to the kernel. For these architectures, you should
183 supply some command-line options at build time by entering them
184 here.
185
186menu "Debugging options"
187
188config JUMP_UPON_UNHANDLED_EXCEPTION
189 bool "Try to die gracefully"
190 default y
191 help
192 Now this puts kernel into infinite loop after first oops. Till
193 your kernel crashes this doesn't have any influence.
194
195 Say Y if you are unsure.
196
197config OPENRISC_ESR_EXCEPTION_BUG_CHECK
198 bool "Check for possible ESR exception bug"
199 default n
200 help
201 This option enables some checks that might expose some problems
202 in kernel.
203
204 Say N if you are unsure.
205
206endmenu
207
208endmenu
209
210menu "Executable file formats"
211
212source "fs/Kconfig.binfmt"
213
214endmenu
215
216source "net/Kconfig"
217
218source "drivers/Kconfig"
219
220source "fs/Kconfig"
221
222source "security/Kconfig"
223
224source "crypto/Kconfig"
225
226source "lib/Kconfig"
227
228menu "Kernel hacking"
229
230source "lib/Kconfig.debug"
231
232endmenu
1#
2# For a description of the syntax of this configuration file,
3# see Documentation/kbuild/kconfig-language.txt.
4#
5
6config OPENRISC
7 def_bool y
8 select OF
9 select OF_EARLY_FLATTREE
10 select IRQ_DOMAIN
11 select HANDLE_DOMAIN_IRQ
12 select HAVE_MEMBLOCK
13 select GPIOLIB
14 select HAVE_ARCH_TRACEHOOK
15 select GENERIC_IRQ_CHIP
16 select GENERIC_IRQ_PROBE
17 select GENERIC_IRQ_SHOW
18 select GENERIC_IOMAP
19 select GENERIC_CPU_DEVICES
20 select HAVE_UID16
21 select GENERIC_ATOMIC64
22 select GENERIC_CLOCKEVENTS
23 select GENERIC_STRNCPY_FROM_USER
24 select GENERIC_STRNLEN_USER
25 select MODULES_USE_ELF_RELA
26 select HAVE_DEBUG_STACKOVERFLOW
27 select OR1K_PIC
28 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
29 select NO_BOOTMEM
30
31config MMU
32 def_bool y
33
34config RWSEM_GENERIC_SPINLOCK
35 def_bool y
36
37config RWSEM_XCHGADD_ALGORITHM
38 def_bool n
39
40config GENERIC_HWEIGHT
41 def_bool y
42
43config NO_IOPORT_MAP
44 def_bool y
45
46config TRACE_IRQFLAGS_SUPPORT
47 def_bool y
48
49# For now, use generic checksum functions
50#These can be reimplemented in assembly later if so inclined
51config GENERIC_CSUM
52 def_bool y
53
54source "init/Kconfig"
55
56source "kernel/Kconfig.freezer"
57
58menu "Processor type and features"
59
60choice
61 prompt "Subarchitecture"
62 default OR1K_1200
63
64config OR1K_1200
65 bool "OR1200"
66 help
67 Generic OpenRISC 1200 architecture
68
69endchoice
70
71config OPENRISC_BUILTIN_DTB
72 string "Builtin DTB"
73 default ""
74
75menu "Class II Instructions"
76
77config OPENRISC_HAVE_INST_FF1
78 bool "Have instruction l.ff1"
79 default y
80 help
81 Select this if your implementation has the Class II instruction l.ff1
82
83config OPENRISC_HAVE_INST_FL1
84 bool "Have instruction l.fl1"
85 default y
86 help
87 Select this if your implementation has the Class II instruction l.fl1
88
89config OPENRISC_HAVE_INST_MUL
90 bool "Have instruction l.mul for hardware multiply"
91 default y
92 help
93 Select this if your implementation has a hardware multiply instruction
94
95config OPENRISC_HAVE_INST_DIV
96 bool "Have instruction l.div for hardware divide"
97 default y
98 help
99 Select this if your implementation has a hardware divide instruction
100endmenu
101
102config NR_CPUS
103 int
104 default "1"
105
106source kernel/Kconfig.hz
107source kernel/Kconfig.preempt
108source "mm/Kconfig"
109
110config OPENRISC_NO_SPR_SR_DSX
111 bool "use SPR_SR_DSX software emulation" if OR1K_1200
112 default y
113 help
114 SPR_SR_DSX bit is status register bit indicating whether
115 the last exception has happened in delay slot.
116
117 OpenRISC architecture makes it optional to have it implemented
118 in hardware and the OR1200 does not have it.
119
120 Say N here if you know that your OpenRISC processor has
121 SPR_SR_DSX bit implemented. Say Y if you are unsure.
122
123config CMDLINE
124 string "Default kernel command string"
125 default ""
126 help
127 On some architectures there is currently no way for the boot loader
128 to pass arguments to the kernel. For these architectures, you should
129 supply some command-line options at build time by entering them
130 here.
131
132menu "Debugging options"
133
134config JUMP_UPON_UNHANDLED_EXCEPTION
135 bool "Try to die gracefully"
136 default y
137 help
138 Now this puts kernel into infinite loop after first oops. Till
139 your kernel crashes this doesn't have any influence.
140
141 Say Y if you are unsure.
142
143config OPENRISC_ESR_EXCEPTION_BUG_CHECK
144 bool "Check for possible ESR exception bug"
145 default n
146 help
147 This option enables some checks that might expose some problems
148 in kernel.
149
150 Say N if you are unsure.
151
152endmenu
153
154endmenu
155
156menu "Executable file formats"
157
158source "fs/Kconfig.binfmt"
159
160endmenu
161
162source "net/Kconfig"
163
164source "drivers/Kconfig"
165
166source "fs/Kconfig"
167
168source "security/Kconfig"
169
170source "crypto/Kconfig"
171
172source "lib/Kconfig"
173
174menu "Kernel hacking"
175
176source "lib/Kconfig.debug"
177
178endmenu