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1# SPDX-License-Identifier: GPL-2.0
2#
3# For a description of the syntax of this configuration file,
4# see Documentation/kbuild/kconfig-language.txt.
5#
6
7config OPENRISC
8 def_bool y
9 select OF
10 select OF_EARLY_FLATTREE
11 select IRQ_DOMAIN
12 select HANDLE_DOMAIN_IRQ
13 select HAVE_MEMBLOCK
14 select GPIOLIB
15 select HAVE_ARCH_TRACEHOOK
16 select SPARSE_IRQ
17 select GENERIC_IRQ_CHIP
18 select GENERIC_IRQ_PROBE
19 select GENERIC_IRQ_SHOW
20 select GENERIC_IOMAP
21 select GENERIC_CPU_DEVICES
22 select HAVE_UID16
23 select GENERIC_ATOMIC64
24 select GENERIC_CLOCKEVENTS
25 select GENERIC_CLOCKEVENTS_BROADCAST
26 select GENERIC_STRNCPY_FROM_USER
27 select GENERIC_STRNLEN_USER
28 select GENERIC_SMP_IDLE_THREAD
29 select MODULES_USE_ELF_RELA
30 select MULTI_IRQ_HANDLER
31 select HAVE_DEBUG_STACKOVERFLOW
32 select OR1K_PIC
33 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
34 select NO_BOOTMEM
35 select ARCH_USE_QUEUED_SPINLOCKS
36 select ARCH_USE_QUEUED_RWLOCKS
37 select OMPIC if SMP
38 select ARCH_WANT_FRAME_POINTERS
39
40config CPU_BIG_ENDIAN
41 def_bool y
42
43config MMU
44 def_bool y
45
46config RWSEM_GENERIC_SPINLOCK
47 def_bool y
48
49config RWSEM_XCHGADD_ALGORITHM
50 def_bool n
51
52config GENERIC_HWEIGHT
53 def_bool y
54
55config NO_IOPORT_MAP
56 def_bool y
57
58config TRACE_IRQFLAGS_SUPPORT
59 def_bool y
60
61# For now, use generic checksum functions
62#These can be reimplemented in assembly later if so inclined
63config GENERIC_CSUM
64 def_bool y
65
66config STACKTRACE_SUPPORT
67 def_bool y
68
69config LOCKDEP_SUPPORT
70 def_bool y
71
72config MULTI_IRQ_HANDLER
73 def_bool y
74
75source "init/Kconfig"
76
77source "kernel/Kconfig.freezer"
78
79menu "Processor type and features"
80
81choice
82 prompt "Subarchitecture"
83 default OR1K_1200
84
85config OR1K_1200
86 bool "OR1200"
87 help
88 Generic OpenRISC 1200 architecture
89
90endchoice
91
92config DCACHE_WRITETHROUGH
93 bool "Have write through data caches"
94 default n
95 help
96 Select this if your implementation features write through data caches.
97 Selecting 'N' here will allow the kernel to force flushing of data
98 caches at relevant times. Most OpenRISC implementations support write-
99 through data caches.
100
101 If unsure say N here
102
103config OPENRISC_BUILTIN_DTB
104 string "Builtin DTB"
105 default ""
106
107menu "Class II Instructions"
108
109config OPENRISC_HAVE_INST_FF1
110 bool "Have instruction l.ff1"
111 default y
112 help
113 Select this if your implementation has the Class II instruction l.ff1
114
115config OPENRISC_HAVE_INST_FL1
116 bool "Have instruction l.fl1"
117 default y
118 help
119 Select this if your implementation has the Class II instruction l.fl1
120
121config OPENRISC_HAVE_INST_MUL
122 bool "Have instruction l.mul for hardware multiply"
123 default y
124 help
125 Select this if your implementation has a hardware multiply instruction
126
127config OPENRISC_HAVE_INST_DIV
128 bool "Have instruction l.div for hardware divide"
129 default y
130 help
131 Select this if your implementation has a hardware divide instruction
132endmenu
133
134config NR_CPUS
135 int "Maximum number of CPUs (2-32)"
136 range 2 32
137 depends on SMP
138 default "2"
139
140config SMP
141 bool "Symmetric Multi-Processing support"
142 help
143 This enables support for systems with more than one CPU. If you have
144 a system with only one CPU, say N. If you have a system with more
145 than one CPU, say Y.
146
147 If you don't know what to do here, say N.
148
149source kernel/Kconfig.hz
150source kernel/Kconfig.preempt
151source "mm/Kconfig"
152
153config OPENRISC_NO_SPR_SR_DSX
154 bool "use SPR_SR_DSX software emulation" if OR1K_1200
155 default y
156 help
157 SPR_SR_DSX bit is status register bit indicating whether
158 the last exception has happened in delay slot.
159
160 OpenRISC architecture makes it optional to have it implemented
161 in hardware and the OR1200 does not have it.
162
163 Say N here if you know that your OpenRISC processor has
164 SPR_SR_DSX bit implemented. Say Y if you are unsure.
165
166config OPENRISC_HAVE_SHADOW_GPRS
167 bool "Support for shadow gpr files" if !SMP
168 default y if SMP
169 help
170 Say Y here if your OpenRISC processor features shadowed
171 register files. They will in such case be used as a
172 scratch reg storage on exception entry.
173
174 On SMP systems, this feature is mandatory.
175 On a unicore system it's safe to say N here if you are unsure.
176
177config CMDLINE
178 string "Default kernel command string"
179 default ""
180 help
181 On some architectures there is currently no way for the boot loader
182 to pass arguments to the kernel. For these architectures, you should
183 supply some command-line options at build time by entering them
184 here.
185
186menu "Debugging options"
187
188config JUMP_UPON_UNHANDLED_EXCEPTION
189 bool "Try to die gracefully"
190 default y
191 help
192 Now this puts kernel into infinite loop after first oops. Till
193 your kernel crashes this doesn't have any influence.
194
195 Say Y if you are unsure.
196
197config OPENRISC_ESR_EXCEPTION_BUG_CHECK
198 bool "Check for possible ESR exception bug"
199 default n
200 help
201 This option enables some checks that might expose some problems
202 in kernel.
203
204 Say N if you are unsure.
205
206endmenu
207
208endmenu
209
210menu "Executable file formats"
211
212source "fs/Kconfig.binfmt"
213
214endmenu
215
216source "net/Kconfig"
217
218source "drivers/Kconfig"
219
220source "fs/Kconfig"
221
222source "security/Kconfig"
223
224source "crypto/Kconfig"
225
226source "lib/Kconfig"
227
228menu "Kernel hacking"
229
230source "lib/Kconfig.debug"
231
232endmenu
1# SPDX-License-Identifier: GPL-2.0
2#
3# For a description of the syntax of this configuration file,
4# see Documentation/kbuild/kconfig-language.rst.
5#
6
7config OPENRISC
8 def_bool y
9 select ARCH_32BIT_OFF_T
10 select ARCH_HAS_DMA_SET_UNCACHED
11 select ARCH_HAS_DMA_CLEAR_UNCACHED
12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
13 select COMMON_CLK
14 select OF
15 select OF_EARLY_FLATTREE
16 select IRQ_DOMAIN
17 select GPIOLIB
18 select HAVE_ARCH_TRACEHOOK
19 select SPARSE_IRQ
20 select GENERIC_IRQ_CHIP
21 select GENERIC_IRQ_PROBE
22 select GENERIC_IRQ_SHOW
23 select GENERIC_PCI_IOMAP
24 select GENERIC_IOREMAP
25 select GENERIC_CPU_DEVICES
26 select HAVE_PCI
27 select HAVE_UID16
28 select HAVE_PAGE_SIZE_8KB
29 select GENERIC_ATOMIC64
30 select GENERIC_CLOCKEVENTS_BROADCAST
31 select GENERIC_SMP_IDLE_THREAD
32 select MODULES_USE_ELF_RELA
33 select HAVE_DEBUG_STACKOVERFLOW
34 select OR1K_PIC
35 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
36 select ARCH_USE_QUEUED_RWLOCKS
37 select OMPIC if SMP
38 select PCI_DOMAINS_GENERIC if PCI
39 select PCI_MSI if PCI
40 select ARCH_WANT_FRAME_POINTERS
41 select GENERIC_IRQ_MULTI_HANDLER
42 select MMU_GATHER_NO_RANGE if MMU
43 select TRACE_IRQFLAGS_SUPPORT
44
45config CPU_BIG_ENDIAN
46 def_bool y
47
48config MMU
49 def_bool y
50
51config GENERIC_HWEIGHT
52 def_bool y
53
54config NO_IOPORT_MAP
55 def_bool y
56
57# For now, use generic checksum functions
58#These can be reimplemented in assembly later if so inclined
59config GENERIC_CSUM
60 def_bool y
61
62config STACKTRACE_SUPPORT
63 def_bool y
64
65config LOCKDEP_SUPPORT
66 def_bool y
67
68menu "Processor type and features"
69
70choice
71 prompt "Subarchitecture"
72 default OR1K_1200
73
74config OR1K_1200
75 bool "OR1200"
76 help
77 Generic OpenRISC 1200 architecture
78
79endchoice
80
81config DCACHE_WRITETHROUGH
82 bool "Have write through data caches"
83 default n
84 help
85 Select this if your implementation features write through data caches.
86 Selecting 'N' here will allow the kernel to force flushing of data
87 caches at relevant times. Most OpenRISC implementations support write-
88 through data caches.
89
90 If unsure say N here
91
92config OPENRISC_BUILTIN_DTB
93 string "Builtin DTB"
94 default ""
95
96menu "Class II Instructions"
97
98config OPENRISC_HAVE_INST_FF1
99 bool "Have instruction l.ff1"
100 default y
101 help
102 Select this if your implementation has the Class II instruction l.ff1
103
104config OPENRISC_HAVE_INST_FL1
105 bool "Have instruction l.fl1"
106 default y
107 help
108 Select this if your implementation has the Class II instruction l.fl1
109
110config OPENRISC_HAVE_INST_MUL
111 bool "Have instruction l.mul for hardware multiply"
112 default y
113 help
114 Select this if your implementation has a hardware multiply instruction
115
116config OPENRISC_HAVE_INST_DIV
117 bool "Have instruction l.div for hardware divide"
118 default y
119 help
120 Select this if your implementation has a hardware divide instruction
121
122config OPENRISC_HAVE_INST_CMOV
123 bool "Have instruction l.cmov for conditional move"
124 default n
125 help
126 This config enables gcc to generate l.cmov instructions when compiling
127 the kernel which in general will improve performance and reduce the
128 binary size.
129
130 Select this if your implementation has support for the Class II
131 l.cmov conistional move instruction.
132
133 Say N if you are unsure.
134
135config OPENRISC_HAVE_INST_ROR
136 bool "Have instruction l.ror for rotate right"
137 default n
138 help
139 This config enables gcc to generate l.ror instructions when compiling
140 the kernel which in general will improve performance and reduce the
141 binary size.
142
143 Select this if your implementation has support for the Class II
144 l.ror rotate right instruction.
145
146 Say N if you are unsure.
147
148config OPENRISC_HAVE_INST_RORI
149 bool "Have instruction l.rori for rotate right with immediate"
150 default n
151 help
152 This config enables gcc to generate l.rori instructions when compiling
153 the kernel which in general will improve performance and reduce the
154 binary size.
155
156 Select this if your implementation has support for the Class II
157 l.rori rotate right with immediate instruction.
158
159 Say N if you are unsure.
160
161config OPENRISC_HAVE_INST_SEXT
162 bool "Have instructions l.ext* for sign extension"
163 default n
164 help
165 This config enables gcc to generate l.ext* instructions when compiling
166 the kernel which in general will improve performance and reduce the
167 binary size.
168
169 Select this if your implementation has support for the Class II
170 l.exths, l.extbs, l.exthz and l.extbz size extend instructions.
171
172 Say N if you are unsure.
173
174endmenu
175
176config NR_CPUS
177 int "Maximum number of CPUs (2-32)"
178 range 2 32
179 depends on SMP
180 default "2"
181
182config SMP
183 bool "Symmetric Multi-Processing support"
184 help
185 This enables support for systems with more than one CPU. If you have
186 a system with only one CPU, say N. If you have a system with more
187 than one CPU, say Y.
188
189 If you don't know what to do here, say N.
190
191source "kernel/Kconfig.hz"
192
193config OPENRISC_NO_SPR_SR_DSX
194 bool "use SPR_SR_DSX software emulation" if OR1K_1200
195 default y
196 help
197 SPR_SR_DSX bit is status register bit indicating whether
198 the last exception has happened in delay slot.
199
200 OpenRISC architecture makes it optional to have it implemented
201 in hardware and the OR1200 does not have it.
202
203 Say N here if you know that your OpenRISC processor has
204 SPR_SR_DSX bit implemented. Say Y if you are unsure.
205
206config OPENRISC_HAVE_SHADOW_GPRS
207 bool "Support for shadow gpr files" if !SMP
208 default y if SMP
209 help
210 Say Y here if your OpenRISC processor features shadowed
211 register files. They will in such case be used as a
212 scratch reg storage on exception entry.
213
214 On SMP systems, this feature is mandatory.
215 On a unicore system it's safe to say N here if you are unsure.
216
217config CMDLINE
218 string "Default kernel command string"
219 default ""
220 help
221 On some architectures there is currently no way for the boot loader
222 to pass arguments to the kernel. For these architectures, you should
223 supply some command-line options at build time by entering them
224 here.
225
226menu "Debugging options"
227
228config JUMP_UPON_UNHANDLED_EXCEPTION
229 bool "Try to die gracefully"
230 default y
231 help
232 Now this puts kernel into infinite loop after first oops. Till
233 your kernel crashes this doesn't have any influence.
234
235 Say Y if you are unsure.
236
237config OPENRISC_ESR_EXCEPTION_BUG_CHECK
238 bool "Check for possible ESR exception bug"
239 default n
240 help
241 This option enables some checks that might expose some problems
242 in kernel.
243
244 Say N if you are unsure.
245
246endmenu
247
248endmenu