Loading...
1/*
2 * Intel Low Power Subsystem PWM controller driver
3 *
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
7 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
8 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
9 * Author: Alan Cox <alan@linux.intel.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/delay.h>
17#include <linux/io.h>
18#include <linux/iopoll.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pm_runtime.h>
22#include <linux/time.h>
23
24#include "pwm-lpss.h"
25
26#define PWM 0x00000000
27#define PWM_ENABLE BIT(31)
28#define PWM_SW_UPDATE BIT(30)
29#define PWM_BASE_UNIT_SHIFT 8
30#define PWM_ON_TIME_DIV_MASK 0x000000ff
31
32/* Size of each PWM register space if multiple */
33#define PWM_SIZE 0x400
34
35struct pwm_lpss_chip {
36 struct pwm_chip chip;
37 void __iomem *regs;
38 const struct pwm_lpss_boardinfo *info;
39};
40
41static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
42{
43 return container_of(chip, struct pwm_lpss_chip, chip);
44}
45
46static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
47{
48 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
49
50 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
51}
52
53static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
54{
55 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
56
57 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
58}
59
60static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
61{
62 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
63 const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
64 const unsigned int ms = 500 * USEC_PER_MSEC;
65 u32 val;
66 int err;
67
68 /*
69 * PWM Configuration register has SW_UPDATE bit that is set when a new
70 * configuration is written to the register. The bit is automatically
71 * cleared at the start of the next output cycle by the IP block.
72 *
73 * If one writes a new configuration to the register while it still has
74 * the bit enabled, PWM may freeze. That is, while one can still write
75 * to the register, it won't have an effect. Thus, we try to sleep long
76 * enough that the bit gets cleared and make sure the bit is not
77 * enabled while we update the configuration.
78 */
79 err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
80 if (err)
81 dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
82
83 return err;
84}
85
86static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
87{
88 return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0;
89}
90
91static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
92 int duty_ns, int period_ns)
93{
94 unsigned long long on_time_div;
95 unsigned long c = lpwm->info->clk_rate, base_unit_range;
96 unsigned long long base_unit, freq = NSEC_PER_SEC;
97 u32 ctrl;
98
99 do_div(freq, period_ns);
100
101 /*
102 * The equation is:
103 * base_unit = round(base_unit_range * freq / c)
104 */
105 base_unit_range = BIT(lpwm->info->base_unit_bits) - 1;
106 freq *= base_unit_range;
107
108 base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
109
110 on_time_div = 255ULL * duty_ns;
111 do_div(on_time_div, period_ns);
112 on_time_div = 255ULL - on_time_div;
113
114 ctrl = pwm_lpss_read(pwm);
115 ctrl &= ~PWM_ON_TIME_DIV_MASK;
116 ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT);
117 base_unit &= base_unit_range;
118 ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
119 ctrl |= on_time_div;
120 pwm_lpss_write(pwm, ctrl);
121}
122
123static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
124{
125 if (cond)
126 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
127}
128
129static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
130 struct pwm_state *state)
131{
132 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
133 int ret;
134
135 if (state->enabled) {
136 if (!pwm_is_enabled(pwm)) {
137 pm_runtime_get_sync(chip->dev);
138 ret = pwm_lpss_is_updating(pwm);
139 if (ret) {
140 pm_runtime_put(chip->dev);
141 return ret;
142 }
143 pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
144 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE);
145 pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
146 ret = pwm_lpss_wait_for_update(pwm);
147 if (ret) {
148 pm_runtime_put(chip->dev);
149 return ret;
150 }
151 pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
152 } else {
153 ret = pwm_lpss_is_updating(pwm);
154 if (ret)
155 return ret;
156 pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
157 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE);
158 return pwm_lpss_wait_for_update(pwm);
159 }
160 } else if (pwm_is_enabled(pwm)) {
161 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
162 pm_runtime_put(chip->dev);
163 }
164
165 return 0;
166}
167
168static const struct pwm_ops pwm_lpss_ops = {
169 .apply = pwm_lpss_apply,
170 .owner = THIS_MODULE,
171};
172
173struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
174 const struct pwm_lpss_boardinfo *info)
175{
176 struct pwm_lpss_chip *lpwm;
177 unsigned long c;
178 int ret;
179
180 lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
181 if (!lpwm)
182 return ERR_PTR(-ENOMEM);
183
184 lpwm->regs = devm_ioremap_resource(dev, r);
185 if (IS_ERR(lpwm->regs))
186 return ERR_CAST(lpwm->regs);
187
188 lpwm->info = info;
189
190 c = lpwm->info->clk_rate;
191 if (!c)
192 return ERR_PTR(-EINVAL);
193
194 lpwm->chip.dev = dev;
195 lpwm->chip.ops = &pwm_lpss_ops;
196 lpwm->chip.base = -1;
197 lpwm->chip.npwm = info->npwm;
198
199 ret = pwmchip_add(&lpwm->chip);
200 if (ret) {
201 dev_err(dev, "failed to add PWM chip: %d\n", ret);
202 return ERR_PTR(ret);
203 }
204
205 return lpwm;
206}
207EXPORT_SYMBOL_GPL(pwm_lpss_probe);
208
209int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
210{
211 return pwmchip_remove(&lpwm->chip);
212}
213EXPORT_SYMBOL_GPL(pwm_lpss_remove);
214
215MODULE_DESCRIPTION("PWM driver for Intel LPSS");
216MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
217MODULE_LICENSE("GPL v2");
1/*
2 * Intel Low Power Subsystem PWM controller driver
3 *
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
7 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
8 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/acpi.h>
16#include <linux/clk.h>
17#include <linux/device.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pwm.h>
21#include <linux/platform_device.h>
22
23#define PWM 0x00000000
24#define PWM_ENABLE BIT(31)
25#define PWM_SW_UPDATE BIT(30)
26#define PWM_BASE_UNIT_SHIFT 8
27#define PWM_BASE_UNIT_MASK 0x00ffff00
28#define PWM_ON_TIME_DIV_MASK 0x000000ff
29#define PWM_DIVISION_CORRECTION 0x2
30#define PWM_LIMIT (0x8000 + PWM_DIVISION_CORRECTION)
31#define NSECS_PER_SEC 1000000000UL
32
33struct pwm_lpss_chip {
34 struct pwm_chip chip;
35 void __iomem *regs;
36 struct clk *clk;
37};
38
39static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
40{
41 return container_of(chip, struct pwm_lpss_chip, chip);
42}
43
44static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm,
45 int duty_ns, int period_ns)
46{
47 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
48 u8 on_time_div;
49 unsigned long c;
50 unsigned long long base_unit, freq = NSECS_PER_SEC;
51 u32 ctrl;
52
53 do_div(freq, period_ns);
54
55 /* The equation is: base_unit = ((freq / c) * 65536) + correction */
56 base_unit = freq * 65536;
57
58 c = clk_get_rate(lpwm->clk);
59 if (!c)
60 return -EINVAL;
61
62 do_div(base_unit, c);
63 base_unit += PWM_DIVISION_CORRECTION;
64 if (base_unit > PWM_LIMIT)
65 return -EINVAL;
66
67 if (duty_ns <= 0)
68 duty_ns = 1;
69 on_time_div = 255 - (255 * duty_ns / period_ns);
70
71 ctrl = readl(lpwm->regs + PWM);
72 ctrl &= ~(PWM_BASE_UNIT_MASK | PWM_ON_TIME_DIV_MASK);
73 ctrl |= (u16) base_unit << PWM_BASE_UNIT_SHIFT;
74 ctrl |= on_time_div;
75 /* request PWM to update on next cycle */
76 ctrl |= PWM_SW_UPDATE;
77 writel(ctrl, lpwm->regs + PWM);
78
79 return 0;
80}
81
82static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm)
83{
84 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
85 u32 ctrl;
86 int ret;
87
88 ret = clk_prepare_enable(lpwm->clk);
89 if (ret)
90 return ret;
91
92 ctrl = readl(lpwm->regs + PWM);
93 writel(ctrl | PWM_ENABLE, lpwm->regs + PWM);
94
95 return 0;
96}
97
98static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm)
99{
100 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
101 u32 ctrl;
102
103 ctrl = readl(lpwm->regs + PWM);
104 writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM);
105
106 clk_disable_unprepare(lpwm->clk);
107}
108
109static const struct pwm_ops pwm_lpss_ops = {
110 .config = pwm_lpss_config,
111 .enable = pwm_lpss_enable,
112 .disable = pwm_lpss_disable,
113 .owner = THIS_MODULE,
114};
115
116static const struct acpi_device_id pwm_lpss_acpi_match[] = {
117 { "80860F09", 0 },
118 { },
119};
120MODULE_DEVICE_TABLE(acpi, pwm_lpss_acpi_match);
121
122static int pwm_lpss_probe(struct platform_device *pdev)
123{
124 struct pwm_lpss_chip *lpwm;
125 struct resource *r;
126 int ret;
127
128 lpwm = devm_kzalloc(&pdev->dev, sizeof(*lpwm), GFP_KERNEL);
129 if (!lpwm)
130 return -ENOMEM;
131
132 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
133
134 lpwm->regs = devm_ioremap_resource(&pdev->dev, r);
135 if (IS_ERR(lpwm->regs))
136 return PTR_ERR(lpwm->regs);
137
138 lpwm->clk = devm_clk_get(&pdev->dev, NULL);
139 if (IS_ERR(lpwm->clk)) {
140 dev_err(&pdev->dev, "failed to get PWM clock\n");
141 return PTR_ERR(lpwm->clk);
142 }
143
144 lpwm->chip.dev = &pdev->dev;
145 lpwm->chip.ops = &pwm_lpss_ops;
146 lpwm->chip.base = -1;
147 lpwm->chip.npwm = 1;
148
149 ret = pwmchip_add(&lpwm->chip);
150 if (ret) {
151 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
152 return ret;
153 }
154
155 platform_set_drvdata(pdev, lpwm);
156 return 0;
157}
158
159static int pwm_lpss_remove(struct platform_device *pdev)
160{
161 struct pwm_lpss_chip *lpwm = platform_get_drvdata(pdev);
162 u32 ctrl;
163
164 ctrl = readl(lpwm->regs + PWM);
165 writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM);
166
167 return pwmchip_remove(&lpwm->chip);
168}
169
170static struct platform_driver pwm_lpss_driver = {
171 .driver = {
172 .name = "pwm-lpss",
173 .acpi_match_table = pwm_lpss_acpi_match,
174 },
175 .probe = pwm_lpss_probe,
176 .remove = pwm_lpss_remove,
177};
178module_platform_driver(pwm_lpss_driver);
179
180MODULE_DESCRIPTION("PWM driver for Intel LPSS");
181MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
182MODULE_LICENSE("GPL v2");
183MODULE_ALIAS("platform:pwm-lpss");