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1/*
2 * Intel Low Power Subsystem PWM controller driver
3 *
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
7 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
8 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
9 * Author: Alan Cox <alan@linux.intel.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/delay.h>
17#include <linux/io.h>
18#include <linux/iopoll.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pm_runtime.h>
22#include <linux/time.h>
23
24#include "pwm-lpss.h"
25
26#define PWM 0x00000000
27#define PWM_ENABLE BIT(31)
28#define PWM_SW_UPDATE BIT(30)
29#define PWM_BASE_UNIT_SHIFT 8
30#define PWM_ON_TIME_DIV_MASK 0x000000ff
31
32/* Size of each PWM register space if multiple */
33#define PWM_SIZE 0x400
34
35struct pwm_lpss_chip {
36 struct pwm_chip chip;
37 void __iomem *regs;
38 const struct pwm_lpss_boardinfo *info;
39};
40
41static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
42{
43 return container_of(chip, struct pwm_lpss_chip, chip);
44}
45
46static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
47{
48 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
49
50 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
51}
52
53static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
54{
55 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
56
57 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
58}
59
60static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
61{
62 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
63 const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
64 const unsigned int ms = 500 * USEC_PER_MSEC;
65 u32 val;
66 int err;
67
68 /*
69 * PWM Configuration register has SW_UPDATE bit that is set when a new
70 * configuration is written to the register. The bit is automatically
71 * cleared at the start of the next output cycle by the IP block.
72 *
73 * If one writes a new configuration to the register while it still has
74 * the bit enabled, PWM may freeze. That is, while one can still write
75 * to the register, it won't have an effect. Thus, we try to sleep long
76 * enough that the bit gets cleared and make sure the bit is not
77 * enabled while we update the configuration.
78 */
79 err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
80 if (err)
81 dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
82
83 return err;
84}
85
86static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
87{
88 return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0;
89}
90
91static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
92 int duty_ns, int period_ns)
93{
94 unsigned long long on_time_div;
95 unsigned long c = lpwm->info->clk_rate, base_unit_range;
96 unsigned long long base_unit, freq = NSEC_PER_SEC;
97 u32 ctrl;
98
99 do_div(freq, period_ns);
100
101 /*
102 * The equation is:
103 * base_unit = round(base_unit_range * freq / c)
104 */
105 base_unit_range = BIT(lpwm->info->base_unit_bits) - 1;
106 freq *= base_unit_range;
107
108 base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
109
110 on_time_div = 255ULL * duty_ns;
111 do_div(on_time_div, period_ns);
112 on_time_div = 255ULL - on_time_div;
113
114 ctrl = pwm_lpss_read(pwm);
115 ctrl &= ~PWM_ON_TIME_DIV_MASK;
116 ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT);
117 base_unit &= base_unit_range;
118 ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
119 ctrl |= on_time_div;
120 pwm_lpss_write(pwm, ctrl);
121}
122
123static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
124{
125 if (cond)
126 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
127}
128
129static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
130 struct pwm_state *state)
131{
132 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
133 int ret;
134
135 if (state->enabled) {
136 if (!pwm_is_enabled(pwm)) {
137 pm_runtime_get_sync(chip->dev);
138 ret = pwm_lpss_is_updating(pwm);
139 if (ret) {
140 pm_runtime_put(chip->dev);
141 return ret;
142 }
143 pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
144 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE);
145 pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
146 ret = pwm_lpss_wait_for_update(pwm);
147 if (ret) {
148 pm_runtime_put(chip->dev);
149 return ret;
150 }
151 pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
152 } else {
153 ret = pwm_lpss_is_updating(pwm);
154 if (ret)
155 return ret;
156 pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
157 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE);
158 return pwm_lpss_wait_for_update(pwm);
159 }
160 } else if (pwm_is_enabled(pwm)) {
161 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
162 pm_runtime_put(chip->dev);
163 }
164
165 return 0;
166}
167
168static const struct pwm_ops pwm_lpss_ops = {
169 .apply = pwm_lpss_apply,
170 .owner = THIS_MODULE,
171};
172
173struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
174 const struct pwm_lpss_boardinfo *info)
175{
176 struct pwm_lpss_chip *lpwm;
177 unsigned long c;
178 int ret;
179
180 lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
181 if (!lpwm)
182 return ERR_PTR(-ENOMEM);
183
184 lpwm->regs = devm_ioremap_resource(dev, r);
185 if (IS_ERR(lpwm->regs))
186 return ERR_CAST(lpwm->regs);
187
188 lpwm->info = info;
189
190 c = lpwm->info->clk_rate;
191 if (!c)
192 return ERR_PTR(-EINVAL);
193
194 lpwm->chip.dev = dev;
195 lpwm->chip.ops = &pwm_lpss_ops;
196 lpwm->chip.base = -1;
197 lpwm->chip.npwm = info->npwm;
198
199 ret = pwmchip_add(&lpwm->chip);
200 if (ret) {
201 dev_err(dev, "failed to add PWM chip: %d\n", ret);
202 return ERR_PTR(ret);
203 }
204
205 return lpwm;
206}
207EXPORT_SYMBOL_GPL(pwm_lpss_probe);
208
209int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
210{
211 return pwmchip_remove(&lpwm->chip);
212}
213EXPORT_SYMBOL_GPL(pwm_lpss_remove);
214
215MODULE_DESCRIPTION("PWM driver for Intel LPSS");
216MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
217MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Intel Low Power Subsystem PWM controller driver
4 *
5 * Copyright (C) 2014, Intel Corporation
6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
8 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
9 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
10 * Author: Alan Cox <alan@linux.intel.com>
11 */
12
13#include <linux/delay.h>
14#include <linux/io.h>
15#include <linux/iopoll.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/pm_runtime.h>
19#include <linux/time.h>
20
21#include "pwm-lpss.h"
22
23#define PWM 0x00000000
24#define PWM_ENABLE BIT(31)
25#define PWM_SW_UPDATE BIT(30)
26#define PWM_BASE_UNIT_SHIFT 8
27#define PWM_ON_TIME_DIV_MASK 0x000000ff
28
29/* Size of each PWM register space if multiple */
30#define PWM_SIZE 0x400
31
32static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
33{
34 return container_of(chip, struct pwm_lpss_chip, chip);
35}
36
37static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
38{
39 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
40
41 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
42}
43
44static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
45{
46 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
47
48 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
49}
50
51static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
52{
53 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
54 const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
55 const unsigned int ms = 500 * USEC_PER_MSEC;
56 u32 val;
57 int err;
58
59 /*
60 * PWM Configuration register has SW_UPDATE bit that is set when a new
61 * configuration is written to the register. The bit is automatically
62 * cleared at the start of the next output cycle by the IP block.
63 *
64 * If one writes a new configuration to the register while it still has
65 * the bit enabled, PWM may freeze. That is, while one can still write
66 * to the register, it won't have an effect. Thus, we try to sleep long
67 * enough that the bit gets cleared and make sure the bit is not
68 * enabled while we update the configuration.
69 */
70 err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
71 if (err)
72 dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
73
74 return err;
75}
76
77static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
78{
79 return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0;
80}
81
82static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
83 int duty_ns, int period_ns)
84{
85 unsigned long long on_time_div;
86 unsigned long c = lpwm->info->clk_rate, base_unit_range;
87 unsigned long long base_unit, freq = NSEC_PER_SEC;
88 u32 orig_ctrl, ctrl;
89
90 do_div(freq, period_ns);
91
92 /*
93 * The equation is:
94 * base_unit = round(base_unit_range * freq / c)
95 */
96 base_unit_range = BIT(lpwm->info->base_unit_bits) - 1;
97 freq *= base_unit_range;
98
99 base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
100
101 on_time_div = 255ULL * duty_ns;
102 do_div(on_time_div, period_ns);
103 on_time_div = 255ULL - on_time_div;
104
105 orig_ctrl = ctrl = pwm_lpss_read(pwm);
106 ctrl &= ~PWM_ON_TIME_DIV_MASK;
107 ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT);
108 base_unit &= base_unit_range;
109 ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
110 ctrl |= on_time_div;
111
112 if (orig_ctrl != ctrl) {
113 pwm_lpss_write(pwm, ctrl);
114 pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE);
115 }
116}
117
118static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
119{
120 if (cond)
121 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
122}
123
124static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
125 const struct pwm_state *state)
126{
127 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
128 int ret;
129
130 if (state->enabled) {
131 if (!pwm_is_enabled(pwm)) {
132 pm_runtime_get_sync(chip->dev);
133 ret = pwm_lpss_is_updating(pwm);
134 if (ret) {
135 pm_runtime_put(chip->dev);
136 return ret;
137 }
138 pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
139 pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
140 ret = pwm_lpss_wait_for_update(pwm);
141 if (ret) {
142 pm_runtime_put(chip->dev);
143 return ret;
144 }
145 pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
146 } else {
147 ret = pwm_lpss_is_updating(pwm);
148 if (ret)
149 return ret;
150 pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
151 return pwm_lpss_wait_for_update(pwm);
152 }
153 } else if (pwm_is_enabled(pwm)) {
154 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
155 pm_runtime_put(chip->dev);
156 }
157
158 return 0;
159}
160
161static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
162 struct pwm_state *state)
163{
164 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
165 unsigned long base_unit_range;
166 unsigned long long base_unit, freq, on_time_div;
167 u32 ctrl;
168
169 pm_runtime_get_sync(chip->dev);
170
171 base_unit_range = BIT(lpwm->info->base_unit_bits);
172
173 ctrl = pwm_lpss_read(pwm);
174 on_time_div = 255 - (ctrl & PWM_ON_TIME_DIV_MASK);
175 base_unit = (ctrl >> PWM_BASE_UNIT_SHIFT) & (base_unit_range - 1);
176
177 freq = base_unit * lpwm->info->clk_rate;
178 do_div(freq, base_unit_range);
179 if (freq == 0)
180 state->period = NSEC_PER_SEC;
181 else
182 state->period = NSEC_PER_SEC / (unsigned long)freq;
183
184 on_time_div *= state->period;
185 do_div(on_time_div, 255);
186 state->duty_cycle = on_time_div;
187
188 state->polarity = PWM_POLARITY_NORMAL;
189 state->enabled = !!(ctrl & PWM_ENABLE);
190
191 pm_runtime_put(chip->dev);
192}
193
194static const struct pwm_ops pwm_lpss_ops = {
195 .apply = pwm_lpss_apply,
196 .get_state = pwm_lpss_get_state,
197 .owner = THIS_MODULE,
198};
199
200struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
201 const struct pwm_lpss_boardinfo *info)
202{
203 struct pwm_lpss_chip *lpwm;
204 unsigned long c;
205 int i, ret;
206 u32 ctrl;
207
208 if (WARN_ON(info->npwm > MAX_PWMS))
209 return ERR_PTR(-ENODEV);
210
211 lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
212 if (!lpwm)
213 return ERR_PTR(-ENOMEM);
214
215 lpwm->regs = devm_ioremap_resource(dev, r);
216 if (IS_ERR(lpwm->regs))
217 return ERR_CAST(lpwm->regs);
218
219 lpwm->info = info;
220
221 c = lpwm->info->clk_rate;
222 if (!c)
223 return ERR_PTR(-EINVAL);
224
225 lpwm->chip.dev = dev;
226 lpwm->chip.ops = &pwm_lpss_ops;
227 lpwm->chip.base = -1;
228 lpwm->chip.npwm = info->npwm;
229
230 ret = pwmchip_add(&lpwm->chip);
231 if (ret) {
232 dev_err(dev, "failed to add PWM chip: %d\n", ret);
233 return ERR_PTR(ret);
234 }
235
236 for (i = 0; i < lpwm->info->npwm; i++) {
237 ctrl = pwm_lpss_read(&lpwm->chip.pwms[i]);
238 if (ctrl & PWM_ENABLE)
239 pm_runtime_get(dev);
240 }
241
242 return lpwm;
243}
244EXPORT_SYMBOL_GPL(pwm_lpss_probe);
245
246int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
247{
248 int i;
249
250 for (i = 0; i < lpwm->info->npwm; i++) {
251 if (pwm_is_enabled(&lpwm->chip.pwms[i]))
252 pm_runtime_put(lpwm->chip.dev);
253 }
254 return pwmchip_remove(&lpwm->chip);
255}
256EXPORT_SYMBOL_GPL(pwm_lpss_remove);
257
258int pwm_lpss_suspend(struct device *dev)
259{
260 struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
261 int i;
262
263 for (i = 0; i < lpwm->info->npwm; i++)
264 lpwm->saved_ctrl[i] = readl(lpwm->regs + i * PWM_SIZE + PWM);
265
266 return 0;
267}
268EXPORT_SYMBOL_GPL(pwm_lpss_suspend);
269
270int pwm_lpss_resume(struct device *dev)
271{
272 struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
273 int i;
274
275 for (i = 0; i < lpwm->info->npwm; i++)
276 writel(lpwm->saved_ctrl[i], lpwm->regs + i * PWM_SIZE + PWM);
277
278 return 0;
279}
280EXPORT_SYMBOL_GPL(pwm_lpss_resume);
281
282MODULE_DESCRIPTION("PWM driver for Intel LPSS");
283MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
284MODULE_LICENSE("GPL v2");