Loading...
1/*
2 * Intel Low Power Subsystem PWM controller driver
3 *
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
7 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
8 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
9 * Author: Alan Cox <alan@linux.intel.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/delay.h>
17#include <linux/io.h>
18#include <linux/iopoll.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pm_runtime.h>
22#include <linux/time.h>
23
24#include "pwm-lpss.h"
25
26#define PWM 0x00000000
27#define PWM_ENABLE BIT(31)
28#define PWM_SW_UPDATE BIT(30)
29#define PWM_BASE_UNIT_SHIFT 8
30#define PWM_ON_TIME_DIV_MASK 0x000000ff
31
32/* Size of each PWM register space if multiple */
33#define PWM_SIZE 0x400
34
35struct pwm_lpss_chip {
36 struct pwm_chip chip;
37 void __iomem *regs;
38 const struct pwm_lpss_boardinfo *info;
39};
40
41static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
42{
43 return container_of(chip, struct pwm_lpss_chip, chip);
44}
45
46static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
47{
48 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
49
50 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
51}
52
53static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
54{
55 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
56
57 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
58}
59
60static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
61{
62 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
63 const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
64 const unsigned int ms = 500 * USEC_PER_MSEC;
65 u32 val;
66 int err;
67
68 /*
69 * PWM Configuration register has SW_UPDATE bit that is set when a new
70 * configuration is written to the register. The bit is automatically
71 * cleared at the start of the next output cycle by the IP block.
72 *
73 * If one writes a new configuration to the register while it still has
74 * the bit enabled, PWM may freeze. That is, while one can still write
75 * to the register, it won't have an effect. Thus, we try to sleep long
76 * enough that the bit gets cleared and make sure the bit is not
77 * enabled while we update the configuration.
78 */
79 err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
80 if (err)
81 dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
82
83 return err;
84}
85
86static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
87{
88 return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0;
89}
90
91static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
92 int duty_ns, int period_ns)
93{
94 unsigned long long on_time_div;
95 unsigned long c = lpwm->info->clk_rate, base_unit_range;
96 unsigned long long base_unit, freq = NSEC_PER_SEC;
97 u32 ctrl;
98
99 do_div(freq, period_ns);
100
101 /*
102 * The equation is:
103 * base_unit = round(base_unit_range * freq / c)
104 */
105 base_unit_range = BIT(lpwm->info->base_unit_bits) - 1;
106 freq *= base_unit_range;
107
108 base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
109
110 on_time_div = 255ULL * duty_ns;
111 do_div(on_time_div, period_ns);
112 on_time_div = 255ULL - on_time_div;
113
114 ctrl = pwm_lpss_read(pwm);
115 ctrl &= ~PWM_ON_TIME_DIV_MASK;
116 ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT);
117 base_unit &= base_unit_range;
118 ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
119 ctrl |= on_time_div;
120 pwm_lpss_write(pwm, ctrl);
121}
122
123static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
124{
125 if (cond)
126 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
127}
128
129static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
130 struct pwm_state *state)
131{
132 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
133 int ret;
134
135 if (state->enabled) {
136 if (!pwm_is_enabled(pwm)) {
137 pm_runtime_get_sync(chip->dev);
138 ret = pwm_lpss_is_updating(pwm);
139 if (ret) {
140 pm_runtime_put(chip->dev);
141 return ret;
142 }
143 pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
144 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE);
145 pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
146 ret = pwm_lpss_wait_for_update(pwm);
147 if (ret) {
148 pm_runtime_put(chip->dev);
149 return ret;
150 }
151 pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
152 } else {
153 ret = pwm_lpss_is_updating(pwm);
154 if (ret)
155 return ret;
156 pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
157 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE);
158 return pwm_lpss_wait_for_update(pwm);
159 }
160 } else if (pwm_is_enabled(pwm)) {
161 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
162 pm_runtime_put(chip->dev);
163 }
164
165 return 0;
166}
167
168static const struct pwm_ops pwm_lpss_ops = {
169 .apply = pwm_lpss_apply,
170 .owner = THIS_MODULE,
171};
172
173struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
174 const struct pwm_lpss_boardinfo *info)
175{
176 struct pwm_lpss_chip *lpwm;
177 unsigned long c;
178 int ret;
179
180 lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
181 if (!lpwm)
182 return ERR_PTR(-ENOMEM);
183
184 lpwm->regs = devm_ioremap_resource(dev, r);
185 if (IS_ERR(lpwm->regs))
186 return ERR_CAST(lpwm->regs);
187
188 lpwm->info = info;
189
190 c = lpwm->info->clk_rate;
191 if (!c)
192 return ERR_PTR(-EINVAL);
193
194 lpwm->chip.dev = dev;
195 lpwm->chip.ops = &pwm_lpss_ops;
196 lpwm->chip.base = -1;
197 lpwm->chip.npwm = info->npwm;
198
199 ret = pwmchip_add(&lpwm->chip);
200 if (ret) {
201 dev_err(dev, "failed to add PWM chip: %d\n", ret);
202 return ERR_PTR(ret);
203 }
204
205 return lpwm;
206}
207EXPORT_SYMBOL_GPL(pwm_lpss_probe);
208
209int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
210{
211 return pwmchip_remove(&lpwm->chip);
212}
213EXPORT_SYMBOL_GPL(pwm_lpss_remove);
214
215MODULE_DESCRIPTION("PWM driver for Intel LPSS");
216MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
217MODULE_LICENSE("GPL v2");
1/*
2 * Intel Low Power Subsystem PWM controller driver
3 *
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
7 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
8 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
9 * Author: Alan Cox <alan@linux.intel.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/delay.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pm_runtime.h>
21#include <linux/time.h>
22
23#include "pwm-lpss.h"
24
25#define PWM 0x00000000
26#define PWM_ENABLE BIT(31)
27#define PWM_SW_UPDATE BIT(30)
28#define PWM_BASE_UNIT_SHIFT 8
29#define PWM_ON_TIME_DIV_MASK 0x000000ff
30
31/* Size of each PWM register space if multiple */
32#define PWM_SIZE 0x400
33
34struct pwm_lpss_chip {
35 struct pwm_chip chip;
36 void __iomem *regs;
37 const struct pwm_lpss_boardinfo *info;
38};
39
40/* BayTrail */
41const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
42 .clk_rate = 25000000,
43 .npwm = 1,
44 .base_unit_bits = 16,
45};
46EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);
47
48/* Braswell */
49const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
50 .clk_rate = 19200000,
51 .npwm = 1,
52 .base_unit_bits = 16,
53};
54EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
55
56/* Broxton */
57const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
58 .clk_rate = 19200000,
59 .npwm = 4,
60 .base_unit_bits = 22,
61};
62EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info);
63
64static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
65{
66 return container_of(chip, struct pwm_lpss_chip, chip);
67}
68
69static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
70{
71 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
72
73 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
74}
75
76static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
77{
78 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
79
80 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
81}
82
83static void pwm_lpss_update(struct pwm_device *pwm)
84{
85 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE);
86 /* Give it some time to propagate */
87 usleep_range(10, 50);
88}
89
90static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm,
91 int duty_ns, int period_ns)
92{
93 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
94 unsigned long long on_time_div;
95 unsigned long c = lpwm->info->clk_rate, base_unit_range;
96 unsigned long long base_unit, freq = NSEC_PER_SEC;
97 u32 ctrl;
98
99 do_div(freq, period_ns);
100
101 /*
102 * The equation is:
103 * base_unit = round(base_unit_range * freq / c)
104 */
105 base_unit_range = BIT(lpwm->info->base_unit_bits);
106 freq *= base_unit_range;
107
108 base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
109
110 if (duty_ns <= 0)
111 duty_ns = 1;
112 on_time_div = 255ULL * duty_ns;
113 do_div(on_time_div, period_ns);
114 on_time_div = 255ULL - on_time_div;
115
116 pm_runtime_get_sync(chip->dev);
117
118 ctrl = pwm_lpss_read(pwm);
119 ctrl &= ~PWM_ON_TIME_DIV_MASK;
120 ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);
121 base_unit &= (base_unit_range - 1);
122 ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
123 ctrl |= on_time_div;
124 pwm_lpss_write(pwm, ctrl);
125
126 /*
127 * If the PWM is already enabled we need to notify the hardware
128 * about the change by setting PWM_SW_UPDATE.
129 */
130 if (pwm_is_enabled(pwm))
131 pwm_lpss_update(pwm);
132
133 pm_runtime_put(chip->dev);
134
135 return 0;
136}
137
138static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm)
139{
140 pm_runtime_get_sync(chip->dev);
141
142 /*
143 * Hardware must first see PWM_SW_UPDATE before the PWM can be
144 * enabled.
145 */
146 pwm_lpss_update(pwm);
147 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
148 return 0;
149}
150
151static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm)
152{
153 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
154 pm_runtime_put(chip->dev);
155}
156
157static const struct pwm_ops pwm_lpss_ops = {
158 .config = pwm_lpss_config,
159 .enable = pwm_lpss_enable,
160 .disable = pwm_lpss_disable,
161 .owner = THIS_MODULE,
162};
163
164struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
165 const struct pwm_lpss_boardinfo *info)
166{
167 struct pwm_lpss_chip *lpwm;
168 unsigned long c;
169 int ret;
170
171 lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
172 if (!lpwm)
173 return ERR_PTR(-ENOMEM);
174
175 lpwm->regs = devm_ioremap_resource(dev, r);
176 if (IS_ERR(lpwm->regs))
177 return ERR_CAST(lpwm->regs);
178
179 lpwm->info = info;
180
181 c = lpwm->info->clk_rate;
182 if (!c)
183 return ERR_PTR(-EINVAL);
184
185 lpwm->chip.dev = dev;
186 lpwm->chip.ops = &pwm_lpss_ops;
187 lpwm->chip.base = -1;
188 lpwm->chip.npwm = info->npwm;
189
190 ret = pwmchip_add(&lpwm->chip);
191 if (ret) {
192 dev_err(dev, "failed to add PWM chip: %d\n", ret);
193 return ERR_PTR(ret);
194 }
195
196 return lpwm;
197}
198EXPORT_SYMBOL_GPL(pwm_lpss_probe);
199
200int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
201{
202 return pwmchip_remove(&lpwm->chip);
203}
204EXPORT_SYMBOL_GPL(pwm_lpss_remove);
205
206MODULE_DESCRIPTION("PWM driver for Intel LPSS");
207MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
208MODULE_LICENSE("GPL v2");