Loading...
1#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
2
3#include <linux/kernel.h>
4#include <linux/sched.h>
5#include <linux/sched/clock.h>
6#include <linux/init.h>
7#include <linux/export.h>
8#include <linux/timer.h>
9#include <linux/acpi_pmtmr.h>
10#include <linux/cpufreq.h>
11#include <linux/delay.h>
12#include <linux/clocksource.h>
13#include <linux/percpu.h>
14#include <linux/timex.h>
15#include <linux/static_key.h>
16
17#include <asm/hpet.h>
18#include <asm/timer.h>
19#include <asm/vgtod.h>
20#include <asm/time.h>
21#include <asm/delay.h>
22#include <asm/hypervisor.h>
23#include <asm/nmi.h>
24#include <asm/x86_init.h>
25#include <asm/geode.h>
26#include <asm/apic.h>
27#include <asm/intel-family.h>
28#include <asm/i8259.h>
29
30unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
31EXPORT_SYMBOL(cpu_khz);
32
33unsigned int __read_mostly tsc_khz;
34EXPORT_SYMBOL(tsc_khz);
35
36/*
37 * TSC can be unstable due to cpufreq or due to unsynced TSCs
38 */
39static int __read_mostly tsc_unstable;
40
41/* native_sched_clock() is called before tsc_init(), so
42 we must start with the TSC soft disabled to prevent
43 erroneous rdtsc usage on !boot_cpu_has(X86_FEATURE_TSC) processors */
44static int __read_mostly tsc_disabled = -1;
45
46static DEFINE_STATIC_KEY_FALSE(__use_tsc);
47
48int tsc_clocksource_reliable;
49
50static u32 art_to_tsc_numerator;
51static u32 art_to_tsc_denominator;
52static u64 art_to_tsc_offset;
53struct clocksource *art_related_clocksource;
54
55struct cyc2ns {
56 struct cyc2ns_data data[2]; /* 0 + 2*16 = 32 */
57 seqcount_t seq; /* 32 + 4 = 36 */
58
59}; /* fits one cacheline */
60
61static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
62
63void cyc2ns_read_begin(struct cyc2ns_data *data)
64{
65 int seq, idx;
66
67 preempt_disable_notrace();
68
69 do {
70 seq = this_cpu_read(cyc2ns.seq.sequence);
71 idx = seq & 1;
72
73 data->cyc2ns_offset = this_cpu_read(cyc2ns.data[idx].cyc2ns_offset);
74 data->cyc2ns_mul = this_cpu_read(cyc2ns.data[idx].cyc2ns_mul);
75 data->cyc2ns_shift = this_cpu_read(cyc2ns.data[idx].cyc2ns_shift);
76
77 } while (unlikely(seq != this_cpu_read(cyc2ns.seq.sequence)));
78}
79
80void cyc2ns_read_end(void)
81{
82 preempt_enable_notrace();
83}
84
85/*
86 * Accelerators for sched_clock()
87 * convert from cycles(64bits) => nanoseconds (64bits)
88 * basic equation:
89 * ns = cycles / (freq / ns_per_sec)
90 * ns = cycles * (ns_per_sec / freq)
91 * ns = cycles * (10^9 / (cpu_khz * 10^3))
92 * ns = cycles * (10^6 / cpu_khz)
93 *
94 * Then we use scaling math (suggested by george@mvista.com) to get:
95 * ns = cycles * (10^6 * SC / cpu_khz) / SC
96 * ns = cycles * cyc2ns_scale / SC
97 *
98 * And since SC is a constant power of two, we can convert the div
99 * into a shift. The larger SC is, the more accurate the conversion, but
100 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication
101 * (64-bit result) can be used.
102 *
103 * We can use khz divisor instead of mhz to keep a better precision.
104 * (mathieu.desnoyers@polymtl.ca)
105 *
106 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
107 */
108
109static void cyc2ns_data_init(struct cyc2ns_data *data)
110{
111 data->cyc2ns_mul = 0;
112 data->cyc2ns_shift = 0;
113 data->cyc2ns_offset = 0;
114}
115
116static void __init cyc2ns_init(int cpu)
117{
118 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
119
120 cyc2ns_data_init(&c2n->data[0]);
121 cyc2ns_data_init(&c2n->data[1]);
122
123 seqcount_init(&c2n->seq);
124}
125
126static inline unsigned long long cycles_2_ns(unsigned long long cyc)
127{
128 struct cyc2ns_data data;
129 unsigned long long ns;
130
131 cyc2ns_read_begin(&data);
132
133 ns = data.cyc2ns_offset;
134 ns += mul_u64_u32_shr(cyc, data.cyc2ns_mul, data.cyc2ns_shift);
135
136 cyc2ns_read_end();
137
138 return ns;
139}
140
141static void set_cyc2ns_scale(unsigned long khz, int cpu, unsigned long long tsc_now)
142{
143 unsigned long long ns_now;
144 struct cyc2ns_data data;
145 struct cyc2ns *c2n;
146 unsigned long flags;
147
148 local_irq_save(flags);
149 sched_clock_idle_sleep_event();
150
151 if (!khz)
152 goto done;
153
154 ns_now = cycles_2_ns(tsc_now);
155
156 /*
157 * Compute a new multiplier as per the above comment and ensure our
158 * time function is continuous; see the comment near struct
159 * cyc2ns_data.
160 */
161 clocks_calc_mult_shift(&data.cyc2ns_mul, &data.cyc2ns_shift, khz,
162 NSEC_PER_MSEC, 0);
163
164 /*
165 * cyc2ns_shift is exported via arch_perf_update_userpage() where it is
166 * not expected to be greater than 31 due to the original published
167 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit
168 * value) - refer perf_event_mmap_page documentation in perf_event.h.
169 */
170 if (data.cyc2ns_shift == 32) {
171 data.cyc2ns_shift = 31;
172 data.cyc2ns_mul >>= 1;
173 }
174
175 data.cyc2ns_offset = ns_now -
176 mul_u64_u32_shr(tsc_now, data.cyc2ns_mul, data.cyc2ns_shift);
177
178 c2n = per_cpu_ptr(&cyc2ns, cpu);
179
180 raw_write_seqcount_latch(&c2n->seq);
181 c2n->data[0] = data;
182 raw_write_seqcount_latch(&c2n->seq);
183 c2n->data[1] = data;
184
185done:
186 sched_clock_idle_wakeup_event();
187 local_irq_restore(flags);
188}
189
190/*
191 * Scheduler clock - returns current time in nanosec units.
192 */
193u64 native_sched_clock(void)
194{
195 if (static_branch_likely(&__use_tsc)) {
196 u64 tsc_now = rdtsc();
197
198 /* return the value in ns */
199 return cycles_2_ns(tsc_now);
200 }
201
202 /*
203 * Fall back to jiffies if there's no TSC available:
204 * ( But note that we still use it if the TSC is marked
205 * unstable. We do this because unlike Time Of Day,
206 * the scheduler clock tolerates small errors and it's
207 * very important for it to be as fast as the platform
208 * can achieve it. )
209 */
210
211 /* No locking but a rare wrong value is not a big deal: */
212 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
213}
214
215/*
216 * Generate a sched_clock if you already have a TSC value.
217 */
218u64 native_sched_clock_from_tsc(u64 tsc)
219{
220 return cycles_2_ns(tsc);
221}
222
223/* We need to define a real function for sched_clock, to override the
224 weak default version */
225#ifdef CONFIG_PARAVIRT
226unsigned long long sched_clock(void)
227{
228 return paravirt_sched_clock();
229}
230
231bool using_native_sched_clock(void)
232{
233 return pv_time_ops.sched_clock == native_sched_clock;
234}
235#else
236unsigned long long
237sched_clock(void) __attribute__((alias("native_sched_clock")));
238
239bool using_native_sched_clock(void) { return true; }
240#endif
241
242int check_tsc_unstable(void)
243{
244 return tsc_unstable;
245}
246EXPORT_SYMBOL_GPL(check_tsc_unstable);
247
248#ifdef CONFIG_X86_TSC
249int __init notsc_setup(char *str)
250{
251 pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
252 tsc_disabled = 1;
253 return 1;
254}
255#else
256/*
257 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
258 * in cpu/common.c
259 */
260int __init notsc_setup(char *str)
261{
262 setup_clear_cpu_cap(X86_FEATURE_TSC);
263 return 1;
264}
265#endif
266
267__setup("notsc", notsc_setup);
268
269static int no_sched_irq_time;
270
271static int __init tsc_setup(char *str)
272{
273 if (!strcmp(str, "reliable"))
274 tsc_clocksource_reliable = 1;
275 if (!strncmp(str, "noirqtime", 9))
276 no_sched_irq_time = 1;
277 if (!strcmp(str, "unstable"))
278 mark_tsc_unstable("boot parameter");
279 return 1;
280}
281
282__setup("tsc=", tsc_setup);
283
284#define MAX_RETRIES 5
285#define SMI_TRESHOLD 50000
286
287/*
288 * Read TSC and the reference counters. Take care of SMI disturbance
289 */
290static u64 tsc_read_refs(u64 *p, int hpet)
291{
292 u64 t1, t2;
293 int i;
294
295 for (i = 0; i < MAX_RETRIES; i++) {
296 t1 = get_cycles();
297 if (hpet)
298 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
299 else
300 *p = acpi_pm_read_early();
301 t2 = get_cycles();
302 if ((t2 - t1) < SMI_TRESHOLD)
303 return t2;
304 }
305 return ULLONG_MAX;
306}
307
308/*
309 * Calculate the TSC frequency from HPET reference
310 */
311static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
312{
313 u64 tmp;
314
315 if (hpet2 < hpet1)
316 hpet2 += 0x100000000ULL;
317 hpet2 -= hpet1;
318 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
319 do_div(tmp, 1000000);
320 deltatsc = div64_u64(deltatsc, tmp);
321
322 return (unsigned long) deltatsc;
323}
324
325/*
326 * Calculate the TSC frequency from PMTimer reference
327 */
328static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
329{
330 u64 tmp;
331
332 if (!pm1 && !pm2)
333 return ULONG_MAX;
334
335 if (pm2 < pm1)
336 pm2 += (u64)ACPI_PM_OVRRUN;
337 pm2 -= pm1;
338 tmp = pm2 * 1000000000LL;
339 do_div(tmp, PMTMR_TICKS_PER_SEC);
340 do_div(deltatsc, tmp);
341
342 return (unsigned long) deltatsc;
343}
344
345#define CAL_MS 10
346#define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
347#define CAL_PIT_LOOPS 1000
348
349#define CAL2_MS 50
350#define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
351#define CAL2_PIT_LOOPS 5000
352
353
354/*
355 * Try to calibrate the TSC against the Programmable
356 * Interrupt Timer and return the frequency of the TSC
357 * in kHz.
358 *
359 * Return ULONG_MAX on failure to calibrate.
360 */
361static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
362{
363 u64 tsc, t1, t2, delta;
364 unsigned long tscmin, tscmax;
365 int pitcnt;
366
367 if (!has_legacy_pic()) {
368 /*
369 * Relies on tsc_early_delay_calibrate() to have given us semi
370 * usable udelay(), wait for the same 50ms we would have with
371 * the PIT loop below.
372 */
373 udelay(10 * USEC_PER_MSEC);
374 udelay(10 * USEC_PER_MSEC);
375 udelay(10 * USEC_PER_MSEC);
376 udelay(10 * USEC_PER_MSEC);
377 udelay(10 * USEC_PER_MSEC);
378 return ULONG_MAX;
379 }
380
381 /* Set the Gate high, disable speaker */
382 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
383
384 /*
385 * Setup CTC channel 2* for mode 0, (interrupt on terminal
386 * count mode), binary count. Set the latch register to 50ms
387 * (LSB then MSB) to begin countdown.
388 */
389 outb(0xb0, 0x43);
390 outb(latch & 0xff, 0x42);
391 outb(latch >> 8, 0x42);
392
393 tsc = t1 = t2 = get_cycles();
394
395 pitcnt = 0;
396 tscmax = 0;
397 tscmin = ULONG_MAX;
398 while ((inb(0x61) & 0x20) == 0) {
399 t2 = get_cycles();
400 delta = t2 - tsc;
401 tsc = t2;
402 if ((unsigned long) delta < tscmin)
403 tscmin = (unsigned int) delta;
404 if ((unsigned long) delta > tscmax)
405 tscmax = (unsigned int) delta;
406 pitcnt++;
407 }
408
409 /*
410 * Sanity checks:
411 *
412 * If we were not able to read the PIT more than loopmin
413 * times, then we have been hit by a massive SMI
414 *
415 * If the maximum is 10 times larger than the minimum,
416 * then we got hit by an SMI as well.
417 */
418 if (pitcnt < loopmin || tscmax > 10 * tscmin)
419 return ULONG_MAX;
420
421 /* Calculate the PIT value */
422 delta = t2 - t1;
423 do_div(delta, ms);
424 return delta;
425}
426
427/*
428 * This reads the current MSB of the PIT counter, and
429 * checks if we are running on sufficiently fast and
430 * non-virtualized hardware.
431 *
432 * Our expectations are:
433 *
434 * - the PIT is running at roughly 1.19MHz
435 *
436 * - each IO is going to take about 1us on real hardware,
437 * but we allow it to be much faster (by a factor of 10) or
438 * _slightly_ slower (ie we allow up to a 2us read+counter
439 * update - anything else implies a unacceptably slow CPU
440 * or PIT for the fast calibration to work.
441 *
442 * - with 256 PIT ticks to read the value, we have 214us to
443 * see the same MSB (and overhead like doing a single TSC
444 * read per MSB value etc).
445 *
446 * - We're doing 2 reads per loop (LSB, MSB), and we expect
447 * them each to take about a microsecond on real hardware.
448 * So we expect a count value of around 100. But we'll be
449 * generous, and accept anything over 50.
450 *
451 * - if the PIT is stuck, and we see *many* more reads, we
452 * return early (and the next caller of pit_expect_msb()
453 * then consider it a failure when they don't see the
454 * next expected value).
455 *
456 * These expectations mean that we know that we have seen the
457 * transition from one expected value to another with a fairly
458 * high accuracy, and we didn't miss any events. We can thus
459 * use the TSC value at the transitions to calculate a pretty
460 * good value for the TSC frequencty.
461 */
462static inline int pit_verify_msb(unsigned char val)
463{
464 /* Ignore LSB */
465 inb(0x42);
466 return inb(0x42) == val;
467}
468
469static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
470{
471 int count;
472 u64 tsc = 0, prev_tsc = 0;
473
474 for (count = 0; count < 50000; count++) {
475 if (!pit_verify_msb(val))
476 break;
477 prev_tsc = tsc;
478 tsc = get_cycles();
479 }
480 *deltap = get_cycles() - prev_tsc;
481 *tscp = tsc;
482
483 /*
484 * We require _some_ success, but the quality control
485 * will be based on the error terms on the TSC values.
486 */
487 return count > 5;
488}
489
490/*
491 * How many MSB values do we want to see? We aim for
492 * a maximum error rate of 500ppm (in practice the
493 * real error is much smaller), but refuse to spend
494 * more than 50ms on it.
495 */
496#define MAX_QUICK_PIT_MS 50
497#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
498
499static unsigned long quick_pit_calibrate(void)
500{
501 int i;
502 u64 tsc, delta;
503 unsigned long d1, d2;
504
505 if (!has_legacy_pic())
506 return 0;
507
508 /* Set the Gate high, disable speaker */
509 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
510
511 /*
512 * Counter 2, mode 0 (one-shot), binary count
513 *
514 * NOTE! Mode 2 decrements by two (and then the
515 * output is flipped each time, giving the same
516 * final output frequency as a decrement-by-one),
517 * so mode 0 is much better when looking at the
518 * individual counts.
519 */
520 outb(0xb0, 0x43);
521
522 /* Start at 0xffff */
523 outb(0xff, 0x42);
524 outb(0xff, 0x42);
525
526 /*
527 * The PIT starts counting at the next edge, so we
528 * need to delay for a microsecond. The easiest way
529 * to do that is to just read back the 16-bit counter
530 * once from the PIT.
531 */
532 pit_verify_msb(0);
533
534 if (pit_expect_msb(0xff, &tsc, &d1)) {
535 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
536 if (!pit_expect_msb(0xff-i, &delta, &d2))
537 break;
538
539 delta -= tsc;
540
541 /*
542 * Extrapolate the error and fail fast if the error will
543 * never be below 500 ppm.
544 */
545 if (i == 1 &&
546 d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11)
547 return 0;
548
549 /*
550 * Iterate until the error is less than 500 ppm
551 */
552 if (d1+d2 >= delta >> 11)
553 continue;
554
555 /*
556 * Check the PIT one more time to verify that
557 * all TSC reads were stable wrt the PIT.
558 *
559 * This also guarantees serialization of the
560 * last cycle read ('d2') in pit_expect_msb.
561 */
562 if (!pit_verify_msb(0xfe - i))
563 break;
564 goto success;
565 }
566 }
567 pr_info("Fast TSC calibration failed\n");
568 return 0;
569
570success:
571 /*
572 * Ok, if we get here, then we've seen the
573 * MSB of the PIT decrement 'i' times, and the
574 * error has shrunk to less than 500 ppm.
575 *
576 * As a result, we can depend on there not being
577 * any odd delays anywhere, and the TSC reads are
578 * reliable (within the error).
579 *
580 * kHz = ticks / time-in-seconds / 1000;
581 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
582 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
583 */
584 delta *= PIT_TICK_RATE;
585 do_div(delta, i*256*1000);
586 pr_info("Fast TSC calibration using PIT\n");
587 return delta;
588}
589
590/**
591 * native_calibrate_tsc
592 * Determine TSC frequency via CPUID, else return 0.
593 */
594unsigned long native_calibrate_tsc(void)
595{
596 unsigned int eax_denominator, ebx_numerator, ecx_hz, edx;
597 unsigned int crystal_khz;
598
599 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
600 return 0;
601
602 if (boot_cpu_data.cpuid_level < 0x15)
603 return 0;
604
605 eax_denominator = ebx_numerator = ecx_hz = edx = 0;
606
607 /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
608 cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx);
609
610 if (ebx_numerator == 0 || eax_denominator == 0)
611 return 0;
612
613 crystal_khz = ecx_hz / 1000;
614
615 if (crystal_khz == 0) {
616 switch (boot_cpu_data.x86_model) {
617 case INTEL_FAM6_SKYLAKE_MOBILE:
618 case INTEL_FAM6_SKYLAKE_DESKTOP:
619 case INTEL_FAM6_KABYLAKE_MOBILE:
620 case INTEL_FAM6_KABYLAKE_DESKTOP:
621 crystal_khz = 24000; /* 24.0 MHz */
622 break;
623 case INTEL_FAM6_ATOM_DENVERTON:
624 crystal_khz = 25000; /* 25.0 MHz */
625 break;
626 case INTEL_FAM6_ATOM_GOLDMONT:
627 crystal_khz = 19200; /* 19.2 MHz */
628 break;
629 }
630 }
631
632 if (crystal_khz == 0)
633 return 0;
634 /*
635 * TSC frequency determined by CPUID is a "hardware reported"
636 * frequency and is the most accurate one so far we have. This
637 * is considered a known frequency.
638 */
639 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
640
641 /*
642 * For Atom SoCs TSC is the only reliable clocksource.
643 * Mark TSC reliable so no watchdog on it.
644 */
645 if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
646 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
647
648 return crystal_khz * ebx_numerator / eax_denominator;
649}
650
651static unsigned long cpu_khz_from_cpuid(void)
652{
653 unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx;
654
655 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
656 return 0;
657
658 if (boot_cpu_data.cpuid_level < 0x16)
659 return 0;
660
661 eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0;
662
663 cpuid(0x16, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx);
664
665 return eax_base_mhz * 1000;
666}
667
668/**
669 * native_calibrate_cpu - calibrate the cpu on boot
670 */
671unsigned long native_calibrate_cpu(void)
672{
673 u64 tsc1, tsc2, delta, ref1, ref2;
674 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
675 unsigned long flags, latch, ms, fast_calibrate;
676 int hpet = is_hpet_enabled(), i, loopmin;
677
678 fast_calibrate = cpu_khz_from_cpuid();
679 if (fast_calibrate)
680 return fast_calibrate;
681
682 fast_calibrate = cpu_khz_from_msr();
683 if (fast_calibrate)
684 return fast_calibrate;
685
686 local_irq_save(flags);
687 fast_calibrate = quick_pit_calibrate();
688 local_irq_restore(flags);
689 if (fast_calibrate)
690 return fast_calibrate;
691
692 /*
693 * Run 5 calibration loops to get the lowest frequency value
694 * (the best estimate). We use two different calibration modes
695 * here:
696 *
697 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
698 * load a timeout of 50ms. We read the time right after we
699 * started the timer and wait until the PIT count down reaches
700 * zero. In each wait loop iteration we read the TSC and check
701 * the delta to the previous read. We keep track of the min
702 * and max values of that delta. The delta is mostly defined
703 * by the IO time of the PIT access, so we can detect when a
704 * SMI/SMM disturbance happened between the two reads. If the
705 * maximum time is significantly larger than the minimum time,
706 * then we discard the result and have another try.
707 *
708 * 2) Reference counter. If available we use the HPET or the
709 * PMTIMER as a reference to check the sanity of that value.
710 * We use separate TSC readouts and check inside of the
711 * reference read for a SMI/SMM disturbance. We dicard
712 * disturbed values here as well. We do that around the PIT
713 * calibration delay loop as we have to wait for a certain
714 * amount of time anyway.
715 */
716
717 /* Preset PIT loop values */
718 latch = CAL_LATCH;
719 ms = CAL_MS;
720 loopmin = CAL_PIT_LOOPS;
721
722 for (i = 0; i < 3; i++) {
723 unsigned long tsc_pit_khz;
724
725 /*
726 * Read the start value and the reference count of
727 * hpet/pmtimer when available. Then do the PIT
728 * calibration, which will take at least 50ms, and
729 * read the end value.
730 */
731 local_irq_save(flags);
732 tsc1 = tsc_read_refs(&ref1, hpet);
733 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
734 tsc2 = tsc_read_refs(&ref2, hpet);
735 local_irq_restore(flags);
736
737 /* Pick the lowest PIT TSC calibration so far */
738 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
739
740 /* hpet or pmtimer available ? */
741 if (ref1 == ref2)
742 continue;
743
744 /* Check, whether the sampling was disturbed by an SMI */
745 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
746 continue;
747
748 tsc2 = (tsc2 - tsc1) * 1000000LL;
749 if (hpet)
750 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
751 else
752 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
753
754 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
755
756 /* Check the reference deviation */
757 delta = ((u64) tsc_pit_min) * 100;
758 do_div(delta, tsc_ref_min);
759
760 /*
761 * If both calibration results are inside a 10% window
762 * then we can be sure, that the calibration
763 * succeeded. We break out of the loop right away. We
764 * use the reference value, as it is more precise.
765 */
766 if (delta >= 90 && delta <= 110) {
767 pr_info("PIT calibration matches %s. %d loops\n",
768 hpet ? "HPET" : "PMTIMER", i + 1);
769 return tsc_ref_min;
770 }
771
772 /*
773 * Check whether PIT failed more than once. This
774 * happens in virtualized environments. We need to
775 * give the virtual PC a slightly longer timeframe for
776 * the HPET/PMTIMER to make the result precise.
777 */
778 if (i == 1 && tsc_pit_min == ULONG_MAX) {
779 latch = CAL2_LATCH;
780 ms = CAL2_MS;
781 loopmin = CAL2_PIT_LOOPS;
782 }
783 }
784
785 /*
786 * Now check the results.
787 */
788 if (tsc_pit_min == ULONG_MAX) {
789 /* PIT gave no useful value */
790 pr_warn("Unable to calibrate against PIT\n");
791
792 /* We don't have an alternative source, disable TSC */
793 if (!hpet && !ref1 && !ref2) {
794 pr_notice("No reference (HPET/PMTIMER) available\n");
795 return 0;
796 }
797
798 /* The alternative source failed as well, disable TSC */
799 if (tsc_ref_min == ULONG_MAX) {
800 pr_warn("HPET/PMTIMER calibration failed\n");
801 return 0;
802 }
803
804 /* Use the alternative source */
805 pr_info("using %s reference calibration\n",
806 hpet ? "HPET" : "PMTIMER");
807
808 return tsc_ref_min;
809 }
810
811 /* We don't have an alternative source, use the PIT calibration value */
812 if (!hpet && !ref1 && !ref2) {
813 pr_info("Using PIT calibration value\n");
814 return tsc_pit_min;
815 }
816
817 /* The alternative source failed, use the PIT calibration value */
818 if (tsc_ref_min == ULONG_MAX) {
819 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
820 return tsc_pit_min;
821 }
822
823 /*
824 * The calibration values differ too much. In doubt, we use
825 * the PIT value as we know that there are PMTIMERs around
826 * running at double speed. At least we let the user know:
827 */
828 pr_warn("PIT calibration deviates from %s: %lu %lu\n",
829 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
830 pr_info("Using PIT calibration value\n");
831 return tsc_pit_min;
832}
833
834void recalibrate_cpu_khz(void)
835{
836#ifndef CONFIG_SMP
837 unsigned long cpu_khz_old = cpu_khz;
838
839 if (!boot_cpu_has(X86_FEATURE_TSC))
840 return;
841
842 cpu_khz = x86_platform.calibrate_cpu();
843 tsc_khz = x86_platform.calibrate_tsc();
844 if (tsc_khz == 0)
845 tsc_khz = cpu_khz;
846 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
847 cpu_khz = tsc_khz;
848 cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy,
849 cpu_khz_old, cpu_khz);
850#endif
851}
852
853EXPORT_SYMBOL(recalibrate_cpu_khz);
854
855
856static unsigned long long cyc2ns_suspend;
857
858void tsc_save_sched_clock_state(void)
859{
860 if (!sched_clock_stable())
861 return;
862
863 cyc2ns_suspend = sched_clock();
864}
865
866/*
867 * Even on processors with invariant TSC, TSC gets reset in some the
868 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
869 * arbitrary value (still sync'd across cpu's) during resume from such sleep
870 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
871 * that sched_clock() continues from the point where it was left off during
872 * suspend.
873 */
874void tsc_restore_sched_clock_state(void)
875{
876 unsigned long long offset;
877 unsigned long flags;
878 int cpu;
879
880 if (!sched_clock_stable())
881 return;
882
883 local_irq_save(flags);
884
885 /*
886 * We're coming out of suspend, there's no concurrency yet; don't
887 * bother being nice about the RCU stuff, just write to both
888 * data fields.
889 */
890
891 this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0);
892 this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0);
893
894 offset = cyc2ns_suspend - sched_clock();
895
896 for_each_possible_cpu(cpu) {
897 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset;
898 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset;
899 }
900
901 local_irq_restore(flags);
902}
903
904#ifdef CONFIG_CPU_FREQ
905/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
906 * changes.
907 *
908 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
909 * not that important because current Opteron setups do not support
910 * scaling on SMP anyroads.
911 *
912 * Should fix up last_tsc too. Currently gettimeofday in the
913 * first tick after the change will be slightly wrong.
914 */
915
916static unsigned int ref_freq;
917static unsigned long loops_per_jiffy_ref;
918static unsigned long tsc_khz_ref;
919
920static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
921 void *data)
922{
923 struct cpufreq_freqs *freq = data;
924 unsigned long *lpj;
925
926 lpj = &boot_cpu_data.loops_per_jiffy;
927#ifdef CONFIG_SMP
928 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
929 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
930#endif
931
932 if (!ref_freq) {
933 ref_freq = freq->old;
934 loops_per_jiffy_ref = *lpj;
935 tsc_khz_ref = tsc_khz;
936 }
937 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
938 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
939 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
940
941 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
942 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
943 mark_tsc_unstable("cpufreq changes");
944
945 set_cyc2ns_scale(tsc_khz, freq->cpu, rdtsc());
946 }
947
948 return 0;
949}
950
951static struct notifier_block time_cpufreq_notifier_block = {
952 .notifier_call = time_cpufreq_notifier
953};
954
955static int __init cpufreq_register_tsc_scaling(void)
956{
957 if (!boot_cpu_has(X86_FEATURE_TSC))
958 return 0;
959 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
960 return 0;
961 cpufreq_register_notifier(&time_cpufreq_notifier_block,
962 CPUFREQ_TRANSITION_NOTIFIER);
963 return 0;
964}
965
966core_initcall(cpufreq_register_tsc_scaling);
967
968#endif /* CONFIG_CPU_FREQ */
969
970#define ART_CPUID_LEAF (0x15)
971#define ART_MIN_DENOMINATOR (1)
972
973
974/*
975 * If ART is present detect the numerator:denominator to convert to TSC
976 */
977static void __init detect_art(void)
978{
979 unsigned int unused[2];
980
981 if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF)
982 return;
983
984 /*
985 * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required,
986 * and the TSC counter resets must not occur asynchronously.
987 */
988 if (boot_cpu_has(X86_FEATURE_HYPERVISOR) ||
989 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) ||
990 !boot_cpu_has(X86_FEATURE_TSC_ADJUST) ||
991 tsc_async_resets)
992 return;
993
994 cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator,
995 &art_to_tsc_numerator, unused, unused+1);
996
997 if (art_to_tsc_denominator < ART_MIN_DENOMINATOR)
998 return;
999
1000 rdmsrl(MSR_IA32_TSC_ADJUST, art_to_tsc_offset);
1001
1002 /* Make this sticky over multiple CPU init calls */
1003 setup_force_cpu_cap(X86_FEATURE_ART);
1004}
1005
1006
1007/* clocksource code */
1008
1009static void tsc_resume(struct clocksource *cs)
1010{
1011 tsc_verify_tsc_adjust(true);
1012}
1013
1014/*
1015 * We used to compare the TSC to the cycle_last value in the clocksource
1016 * structure to avoid a nasty time-warp. This can be observed in a
1017 * very small window right after one CPU updated cycle_last under
1018 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
1019 * is smaller than the cycle_last reference value due to a TSC which
1020 * is slighty behind. This delta is nowhere else observable, but in
1021 * that case it results in a forward time jump in the range of hours
1022 * due to the unsigned delta calculation of the time keeping core
1023 * code, which is necessary to support wrapping clocksources like pm
1024 * timer.
1025 *
1026 * This sanity check is now done in the core timekeeping code.
1027 * checking the result of read_tsc() - cycle_last for being negative.
1028 * That works because CLOCKSOURCE_MASK(64) does not mask out any bit.
1029 */
1030static u64 read_tsc(struct clocksource *cs)
1031{
1032 return (u64)rdtsc_ordered();
1033}
1034
1035static void tsc_cs_mark_unstable(struct clocksource *cs)
1036{
1037 if (tsc_unstable)
1038 return;
1039
1040 tsc_unstable = 1;
1041 if (using_native_sched_clock())
1042 clear_sched_clock_stable();
1043 disable_sched_clock_irqtime();
1044 pr_info("Marking TSC unstable due to clocksource watchdog\n");
1045}
1046
1047static void tsc_cs_tick_stable(struct clocksource *cs)
1048{
1049 if (tsc_unstable)
1050 return;
1051
1052 if (using_native_sched_clock())
1053 sched_clock_tick_stable();
1054}
1055
1056/*
1057 * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc()
1058 */
1059static struct clocksource clocksource_tsc_early = {
1060 .name = "tsc-early",
1061 .rating = 299,
1062 .read = read_tsc,
1063 .mask = CLOCKSOURCE_MASK(64),
1064 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
1065 CLOCK_SOURCE_MUST_VERIFY,
1066 .archdata = { .vclock_mode = VCLOCK_TSC },
1067 .resume = tsc_resume,
1068 .mark_unstable = tsc_cs_mark_unstable,
1069 .tick_stable = tsc_cs_tick_stable,
1070 .list = LIST_HEAD_INIT(clocksource_tsc_early.list),
1071};
1072
1073/*
1074 * Must mark VALID_FOR_HRES early such that when we unregister tsc_early
1075 * this one will immediately take over. We will only register if TSC has
1076 * been found good.
1077 */
1078static struct clocksource clocksource_tsc = {
1079 .name = "tsc",
1080 .rating = 300,
1081 .read = read_tsc,
1082 .mask = CLOCKSOURCE_MASK(64),
1083 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
1084 CLOCK_SOURCE_VALID_FOR_HRES |
1085 CLOCK_SOURCE_MUST_VERIFY,
1086 .archdata = { .vclock_mode = VCLOCK_TSC },
1087 .resume = tsc_resume,
1088 .mark_unstable = tsc_cs_mark_unstable,
1089 .tick_stable = tsc_cs_tick_stable,
1090 .list = LIST_HEAD_INIT(clocksource_tsc.list),
1091};
1092
1093void mark_tsc_unstable(char *reason)
1094{
1095 if (tsc_unstable)
1096 return;
1097
1098 tsc_unstable = 1;
1099 if (using_native_sched_clock())
1100 clear_sched_clock_stable();
1101 disable_sched_clock_irqtime();
1102 pr_info("Marking TSC unstable due to %s\n", reason);
1103
1104 clocksource_mark_unstable(&clocksource_tsc_early);
1105 clocksource_mark_unstable(&clocksource_tsc);
1106}
1107
1108EXPORT_SYMBOL_GPL(mark_tsc_unstable);
1109
1110static void __init check_system_tsc_reliable(void)
1111{
1112#if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
1113 if (is_geode_lx()) {
1114 /* RTSC counts during suspend */
1115#define RTSC_SUSP 0x100
1116 unsigned long res_low, res_high;
1117
1118 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
1119 /* Geode_LX - the OLPC CPU has a very reliable TSC */
1120 if (res_low & RTSC_SUSP)
1121 tsc_clocksource_reliable = 1;
1122 }
1123#endif
1124 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
1125 tsc_clocksource_reliable = 1;
1126}
1127
1128/*
1129 * Make an educated guess if the TSC is trustworthy and synchronized
1130 * over all CPUs.
1131 */
1132int unsynchronized_tsc(void)
1133{
1134 if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable)
1135 return 1;
1136
1137#ifdef CONFIG_SMP
1138 if (apic_is_clustered_box())
1139 return 1;
1140#endif
1141
1142 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1143 return 0;
1144
1145 if (tsc_clocksource_reliable)
1146 return 0;
1147 /*
1148 * Intel systems are normally all synchronized.
1149 * Exceptions must mark TSC as unstable:
1150 */
1151 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1152 /* assume multi socket systems are not synchronized: */
1153 if (num_possible_cpus() > 1)
1154 return 1;
1155 }
1156
1157 return 0;
1158}
1159
1160/*
1161 * Convert ART to TSC given numerator/denominator found in detect_art()
1162 */
1163struct system_counterval_t convert_art_to_tsc(u64 art)
1164{
1165 u64 tmp, res, rem;
1166
1167 rem = do_div(art, art_to_tsc_denominator);
1168
1169 res = art * art_to_tsc_numerator;
1170 tmp = rem * art_to_tsc_numerator;
1171
1172 do_div(tmp, art_to_tsc_denominator);
1173 res += tmp + art_to_tsc_offset;
1174
1175 return (struct system_counterval_t) {.cs = art_related_clocksource,
1176 .cycles = res};
1177}
1178EXPORT_SYMBOL(convert_art_to_tsc);
1179
1180/**
1181 * convert_art_ns_to_tsc() - Convert ART in nanoseconds to TSC.
1182 * @art_ns: ART (Always Running Timer) in unit of nanoseconds
1183 *
1184 * PTM requires all timestamps to be in units of nanoseconds. When user
1185 * software requests a cross-timestamp, this function converts system timestamp
1186 * to TSC.
1187 *
1188 * This is valid when CPU feature flag X86_FEATURE_TSC_KNOWN_FREQ is set
1189 * indicating the tsc_khz is derived from CPUID[15H]. Drivers should check
1190 * that this flag is set before conversion to TSC is attempted.
1191 *
1192 * Return:
1193 * struct system_counterval_t - system counter value with the pointer to the
1194 * corresponding clocksource
1195 * @cycles: System counter value
1196 * @cs: Clocksource corresponding to system counter value. Used
1197 * by timekeeping code to verify comparibility of two cycle
1198 * values.
1199 */
1200
1201struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns)
1202{
1203 u64 tmp, res, rem;
1204
1205 rem = do_div(art_ns, USEC_PER_SEC);
1206
1207 res = art_ns * tsc_khz;
1208 tmp = rem * tsc_khz;
1209
1210 do_div(tmp, USEC_PER_SEC);
1211 res += tmp;
1212
1213 return (struct system_counterval_t) { .cs = art_related_clocksource,
1214 .cycles = res};
1215}
1216EXPORT_SYMBOL(convert_art_ns_to_tsc);
1217
1218
1219static void tsc_refine_calibration_work(struct work_struct *work);
1220static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
1221/**
1222 * tsc_refine_calibration_work - Further refine tsc freq calibration
1223 * @work - ignored.
1224 *
1225 * This functions uses delayed work over a period of a
1226 * second to further refine the TSC freq value. Since this is
1227 * timer based, instead of loop based, we don't block the boot
1228 * process while this longer calibration is done.
1229 *
1230 * If there are any calibration anomalies (too many SMIs, etc),
1231 * or the refined calibration is off by 1% of the fast early
1232 * calibration, we throw out the new calibration and use the
1233 * early calibration.
1234 */
1235static void tsc_refine_calibration_work(struct work_struct *work)
1236{
1237 static u64 tsc_start = -1, ref_start;
1238 static int hpet;
1239 u64 tsc_stop, ref_stop, delta;
1240 unsigned long freq;
1241 int cpu;
1242
1243 /* Don't bother refining TSC on unstable systems */
1244 if (tsc_unstable)
1245 goto unreg;
1246
1247 /*
1248 * Since the work is started early in boot, we may be
1249 * delayed the first time we expire. So set the workqueue
1250 * again once we know timers are working.
1251 */
1252 if (tsc_start == -1) {
1253 /*
1254 * Only set hpet once, to avoid mixing hardware
1255 * if the hpet becomes enabled later.
1256 */
1257 hpet = is_hpet_enabled();
1258 schedule_delayed_work(&tsc_irqwork, HZ);
1259 tsc_start = tsc_read_refs(&ref_start, hpet);
1260 return;
1261 }
1262
1263 tsc_stop = tsc_read_refs(&ref_stop, hpet);
1264
1265 /* hpet or pmtimer available ? */
1266 if (ref_start == ref_stop)
1267 goto out;
1268
1269 /* Check, whether the sampling was disturbed by an SMI */
1270 if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
1271 goto out;
1272
1273 delta = tsc_stop - tsc_start;
1274 delta *= 1000000LL;
1275 if (hpet)
1276 freq = calc_hpet_ref(delta, ref_start, ref_stop);
1277 else
1278 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
1279
1280 /* Make sure we're within 1% */
1281 if (abs(tsc_khz - freq) > tsc_khz/100)
1282 goto out;
1283
1284 tsc_khz = freq;
1285 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
1286 (unsigned long)tsc_khz / 1000,
1287 (unsigned long)tsc_khz % 1000);
1288
1289 /* Inform the TSC deadline clockevent devices about the recalibration */
1290 lapic_update_tsc_freq();
1291
1292 /* Update the sched_clock() rate to match the clocksource one */
1293 for_each_possible_cpu(cpu)
1294 set_cyc2ns_scale(tsc_khz, cpu, tsc_stop);
1295
1296out:
1297 if (tsc_unstable)
1298 goto unreg;
1299
1300 if (boot_cpu_has(X86_FEATURE_ART))
1301 art_related_clocksource = &clocksource_tsc;
1302 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1303unreg:
1304 clocksource_unregister(&clocksource_tsc_early);
1305}
1306
1307
1308static int __init init_tsc_clocksource(void)
1309{
1310 if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_disabled > 0 || !tsc_khz)
1311 return 0;
1312
1313 if (tsc_unstable)
1314 goto unreg;
1315
1316 if (tsc_clocksource_reliable)
1317 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
1318
1319 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
1320 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1321
1322 /*
1323 * When TSC frequency is known (retrieved via MSR or CPUID), we skip
1324 * the refined calibration and directly register it as a clocksource.
1325 */
1326 if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) {
1327 if (boot_cpu_has(X86_FEATURE_ART))
1328 art_related_clocksource = &clocksource_tsc;
1329 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1330unreg:
1331 clocksource_unregister(&clocksource_tsc_early);
1332 return 0;
1333 }
1334
1335 schedule_delayed_work(&tsc_irqwork, 0);
1336 return 0;
1337}
1338/*
1339 * We use device_initcall here, to ensure we run after the hpet
1340 * is fully initialized, which may occur at fs_initcall time.
1341 */
1342device_initcall(init_tsc_clocksource);
1343
1344void __init tsc_early_delay_calibrate(void)
1345{
1346 unsigned long lpj;
1347
1348 if (!boot_cpu_has(X86_FEATURE_TSC))
1349 return;
1350
1351 cpu_khz = x86_platform.calibrate_cpu();
1352 tsc_khz = x86_platform.calibrate_tsc();
1353
1354 tsc_khz = tsc_khz ? : cpu_khz;
1355 if (!tsc_khz)
1356 return;
1357
1358 lpj = tsc_khz * 1000;
1359 do_div(lpj, HZ);
1360 loops_per_jiffy = lpj;
1361}
1362
1363void __init tsc_init(void)
1364{
1365 u64 lpj, cyc;
1366 int cpu;
1367
1368 if (!boot_cpu_has(X86_FEATURE_TSC)) {
1369 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1370 return;
1371 }
1372
1373 cpu_khz = x86_platform.calibrate_cpu();
1374 tsc_khz = x86_platform.calibrate_tsc();
1375
1376 /*
1377 * Trust non-zero tsc_khz as authorative,
1378 * and use it to sanity check cpu_khz,
1379 * which will be off if system timer is off.
1380 */
1381 if (tsc_khz == 0)
1382 tsc_khz = cpu_khz;
1383 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
1384 cpu_khz = tsc_khz;
1385
1386 if (!tsc_khz) {
1387 mark_tsc_unstable("could not calculate TSC khz");
1388 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1389 return;
1390 }
1391
1392 pr_info("Detected %lu.%03lu MHz processor\n",
1393 (unsigned long)cpu_khz / 1000,
1394 (unsigned long)cpu_khz % 1000);
1395
1396 if (cpu_khz != tsc_khz) {
1397 pr_info("Detected %lu.%03lu MHz TSC",
1398 (unsigned long)tsc_khz / 1000,
1399 (unsigned long)tsc_khz % 1000);
1400 }
1401
1402 /* Sanitize TSC ADJUST before cyc2ns gets initialized */
1403 tsc_store_and_check_tsc_adjust(true);
1404
1405 /*
1406 * Secondary CPUs do not run through tsc_init(), so set up
1407 * all the scale factors for all CPUs, assuming the same
1408 * speed as the bootup CPU. (cpufreq notifiers will fix this
1409 * up if their speed diverges)
1410 */
1411 cyc = rdtsc();
1412 for_each_possible_cpu(cpu) {
1413 cyc2ns_init(cpu);
1414 set_cyc2ns_scale(tsc_khz, cpu, cyc);
1415 }
1416
1417 if (tsc_disabled > 0)
1418 return;
1419
1420 /* now allow native_sched_clock() to use rdtsc */
1421
1422 tsc_disabled = 0;
1423 static_branch_enable(&__use_tsc);
1424
1425 if (!no_sched_irq_time)
1426 enable_sched_clock_irqtime();
1427
1428 lpj = ((u64)tsc_khz * 1000);
1429 do_div(lpj, HZ);
1430 lpj_fine = lpj;
1431
1432 use_tsc_delay();
1433
1434 check_system_tsc_reliable();
1435
1436 if (unsynchronized_tsc()) {
1437 mark_tsc_unstable("TSCs unsynchronized");
1438 return;
1439 }
1440
1441 clocksource_register_khz(&clocksource_tsc_early, tsc_khz);
1442 detect_art();
1443}
1444
1445#ifdef CONFIG_SMP
1446/*
1447 * If we have a constant TSC and are using the TSC for the delay loop,
1448 * we can skip clock calibration if another cpu in the same socket has already
1449 * been calibrated. This assumes that CONSTANT_TSC applies to all
1450 * cpus in the socket - this should be a safe assumption.
1451 */
1452unsigned long calibrate_delay_is_known(void)
1453{
1454 int sibling, cpu = smp_processor_id();
1455 int constant_tsc = cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC);
1456 const struct cpumask *mask = topology_core_cpumask(cpu);
1457
1458 if (tsc_disabled || !constant_tsc || !mask)
1459 return 0;
1460
1461 sibling = cpumask_any_but(mask, cpu);
1462 if (sibling < nr_cpu_ids)
1463 return cpu_data(sibling).loops_per_jiffy;
1464 return 0;
1465}
1466#endif
1#include <linux/kernel.h>
2#include <linux/sched.h>
3#include <linux/init.h>
4#include <linux/module.h>
5#include <linux/timer.h>
6#include <linux/acpi_pmtmr.h>
7#include <linux/cpufreq.h>
8#include <linux/delay.h>
9#include <linux/clocksource.h>
10#include <linux/percpu.h>
11#include <linux/timex.h>
12
13#include <asm/hpet.h>
14#include <asm/timer.h>
15#include <asm/vgtod.h>
16#include <asm/time.h>
17#include <asm/delay.h>
18#include <asm/hypervisor.h>
19#include <asm/nmi.h>
20#include <asm/x86_init.h>
21
22unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
23EXPORT_SYMBOL(cpu_khz);
24
25unsigned int __read_mostly tsc_khz;
26EXPORT_SYMBOL(tsc_khz);
27
28/*
29 * TSC can be unstable due to cpufreq or due to unsynced TSCs
30 */
31static int __read_mostly tsc_unstable;
32
33/* native_sched_clock() is called before tsc_init(), so
34 we must start with the TSC soft disabled to prevent
35 erroneous rdtsc usage on !cpu_has_tsc processors */
36static int __read_mostly tsc_disabled = -1;
37
38static int tsc_clocksource_reliable;
39/*
40 * Scheduler clock - returns current time in nanosec units.
41 */
42u64 native_sched_clock(void)
43{
44 u64 this_offset;
45
46 /*
47 * Fall back to jiffies if there's no TSC available:
48 * ( But note that we still use it if the TSC is marked
49 * unstable. We do this because unlike Time Of Day,
50 * the scheduler clock tolerates small errors and it's
51 * very important for it to be as fast as the platform
52 * can achieve it. )
53 */
54 if (unlikely(tsc_disabled)) {
55 /* No locking but a rare wrong value is not a big deal: */
56 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
57 }
58
59 /* read the Time Stamp Counter: */
60 rdtscll(this_offset);
61
62 /* return the value in ns */
63 return __cycles_2_ns(this_offset);
64}
65
66/* We need to define a real function for sched_clock, to override the
67 weak default version */
68#ifdef CONFIG_PARAVIRT
69unsigned long long sched_clock(void)
70{
71 return paravirt_sched_clock();
72}
73#else
74unsigned long long
75sched_clock(void) __attribute__((alias("native_sched_clock")));
76#endif
77
78int check_tsc_unstable(void)
79{
80 return tsc_unstable;
81}
82EXPORT_SYMBOL_GPL(check_tsc_unstable);
83
84#ifdef CONFIG_X86_TSC
85int __init notsc_setup(char *str)
86{
87 printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
88 "cannot disable TSC completely.\n");
89 tsc_disabled = 1;
90 return 1;
91}
92#else
93/*
94 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
95 * in cpu/common.c
96 */
97int __init notsc_setup(char *str)
98{
99 setup_clear_cpu_cap(X86_FEATURE_TSC);
100 return 1;
101}
102#endif
103
104__setup("notsc", notsc_setup);
105
106static int no_sched_irq_time;
107
108static int __init tsc_setup(char *str)
109{
110 if (!strcmp(str, "reliable"))
111 tsc_clocksource_reliable = 1;
112 if (!strncmp(str, "noirqtime", 9))
113 no_sched_irq_time = 1;
114 return 1;
115}
116
117__setup("tsc=", tsc_setup);
118
119#define MAX_RETRIES 5
120#define SMI_TRESHOLD 50000
121
122/*
123 * Read TSC and the reference counters. Take care of SMI disturbance
124 */
125static u64 tsc_read_refs(u64 *p, int hpet)
126{
127 u64 t1, t2;
128 int i;
129
130 for (i = 0; i < MAX_RETRIES; i++) {
131 t1 = get_cycles();
132 if (hpet)
133 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
134 else
135 *p = acpi_pm_read_early();
136 t2 = get_cycles();
137 if ((t2 - t1) < SMI_TRESHOLD)
138 return t2;
139 }
140 return ULLONG_MAX;
141}
142
143/*
144 * Calculate the TSC frequency from HPET reference
145 */
146static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
147{
148 u64 tmp;
149
150 if (hpet2 < hpet1)
151 hpet2 += 0x100000000ULL;
152 hpet2 -= hpet1;
153 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
154 do_div(tmp, 1000000);
155 do_div(deltatsc, tmp);
156
157 return (unsigned long) deltatsc;
158}
159
160/*
161 * Calculate the TSC frequency from PMTimer reference
162 */
163static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
164{
165 u64 tmp;
166
167 if (!pm1 && !pm2)
168 return ULONG_MAX;
169
170 if (pm2 < pm1)
171 pm2 += (u64)ACPI_PM_OVRRUN;
172 pm2 -= pm1;
173 tmp = pm2 * 1000000000LL;
174 do_div(tmp, PMTMR_TICKS_PER_SEC);
175 do_div(deltatsc, tmp);
176
177 return (unsigned long) deltatsc;
178}
179
180#define CAL_MS 10
181#define CAL_LATCH (CLOCK_TICK_RATE / (1000 / CAL_MS))
182#define CAL_PIT_LOOPS 1000
183
184#define CAL2_MS 50
185#define CAL2_LATCH (CLOCK_TICK_RATE / (1000 / CAL2_MS))
186#define CAL2_PIT_LOOPS 5000
187
188
189/*
190 * Try to calibrate the TSC against the Programmable
191 * Interrupt Timer and return the frequency of the TSC
192 * in kHz.
193 *
194 * Return ULONG_MAX on failure to calibrate.
195 */
196static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
197{
198 u64 tsc, t1, t2, delta;
199 unsigned long tscmin, tscmax;
200 int pitcnt;
201
202 /* Set the Gate high, disable speaker */
203 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
204
205 /*
206 * Setup CTC channel 2* for mode 0, (interrupt on terminal
207 * count mode), binary count. Set the latch register to 50ms
208 * (LSB then MSB) to begin countdown.
209 */
210 outb(0xb0, 0x43);
211 outb(latch & 0xff, 0x42);
212 outb(latch >> 8, 0x42);
213
214 tsc = t1 = t2 = get_cycles();
215
216 pitcnt = 0;
217 tscmax = 0;
218 tscmin = ULONG_MAX;
219 while ((inb(0x61) & 0x20) == 0) {
220 t2 = get_cycles();
221 delta = t2 - tsc;
222 tsc = t2;
223 if ((unsigned long) delta < tscmin)
224 tscmin = (unsigned int) delta;
225 if ((unsigned long) delta > tscmax)
226 tscmax = (unsigned int) delta;
227 pitcnt++;
228 }
229
230 /*
231 * Sanity checks:
232 *
233 * If we were not able to read the PIT more than loopmin
234 * times, then we have been hit by a massive SMI
235 *
236 * If the maximum is 10 times larger than the minimum,
237 * then we got hit by an SMI as well.
238 */
239 if (pitcnt < loopmin || tscmax > 10 * tscmin)
240 return ULONG_MAX;
241
242 /* Calculate the PIT value */
243 delta = t2 - t1;
244 do_div(delta, ms);
245 return delta;
246}
247
248/*
249 * This reads the current MSB of the PIT counter, and
250 * checks if we are running on sufficiently fast and
251 * non-virtualized hardware.
252 *
253 * Our expectations are:
254 *
255 * - the PIT is running at roughly 1.19MHz
256 *
257 * - each IO is going to take about 1us on real hardware,
258 * but we allow it to be much faster (by a factor of 10) or
259 * _slightly_ slower (ie we allow up to a 2us read+counter
260 * update - anything else implies a unacceptably slow CPU
261 * or PIT for the fast calibration to work.
262 *
263 * - with 256 PIT ticks to read the value, we have 214us to
264 * see the same MSB (and overhead like doing a single TSC
265 * read per MSB value etc).
266 *
267 * - We're doing 2 reads per loop (LSB, MSB), and we expect
268 * them each to take about a microsecond on real hardware.
269 * So we expect a count value of around 100. But we'll be
270 * generous, and accept anything over 50.
271 *
272 * - if the PIT is stuck, and we see *many* more reads, we
273 * return early (and the next caller of pit_expect_msb()
274 * then consider it a failure when they don't see the
275 * next expected value).
276 *
277 * These expectations mean that we know that we have seen the
278 * transition from one expected value to another with a fairly
279 * high accuracy, and we didn't miss any events. We can thus
280 * use the TSC value at the transitions to calculate a pretty
281 * good value for the TSC frequencty.
282 */
283static inline int pit_verify_msb(unsigned char val)
284{
285 /* Ignore LSB */
286 inb(0x42);
287 return inb(0x42) == val;
288}
289
290static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
291{
292 int count;
293 u64 tsc = 0;
294
295 for (count = 0; count < 50000; count++) {
296 if (!pit_verify_msb(val))
297 break;
298 tsc = get_cycles();
299 }
300 *deltap = get_cycles() - tsc;
301 *tscp = tsc;
302
303 /*
304 * We require _some_ success, but the quality control
305 * will be based on the error terms on the TSC values.
306 */
307 return count > 5;
308}
309
310/*
311 * How many MSB values do we want to see? We aim for
312 * a maximum error rate of 500ppm (in practice the
313 * real error is much smaller), but refuse to spend
314 * more than 25ms on it.
315 */
316#define MAX_QUICK_PIT_MS 25
317#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
318
319static unsigned long quick_pit_calibrate(void)
320{
321 int i;
322 u64 tsc, delta;
323 unsigned long d1, d2;
324
325 /* Set the Gate high, disable speaker */
326 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
327
328 /*
329 * Counter 2, mode 0 (one-shot), binary count
330 *
331 * NOTE! Mode 2 decrements by two (and then the
332 * output is flipped each time, giving the same
333 * final output frequency as a decrement-by-one),
334 * so mode 0 is much better when looking at the
335 * individual counts.
336 */
337 outb(0xb0, 0x43);
338
339 /* Start at 0xffff */
340 outb(0xff, 0x42);
341 outb(0xff, 0x42);
342
343 /*
344 * The PIT starts counting at the next edge, so we
345 * need to delay for a microsecond. The easiest way
346 * to do that is to just read back the 16-bit counter
347 * once from the PIT.
348 */
349 pit_verify_msb(0);
350
351 if (pit_expect_msb(0xff, &tsc, &d1)) {
352 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
353 if (!pit_expect_msb(0xff-i, &delta, &d2))
354 break;
355
356 /*
357 * Iterate until the error is less than 500 ppm
358 */
359 delta -= tsc;
360 if (d1+d2 >= delta >> 11)
361 continue;
362
363 /*
364 * Check the PIT one more time to verify that
365 * all TSC reads were stable wrt the PIT.
366 *
367 * This also guarantees serialization of the
368 * last cycle read ('d2') in pit_expect_msb.
369 */
370 if (!pit_verify_msb(0xfe - i))
371 break;
372 goto success;
373 }
374 }
375 printk("Fast TSC calibration failed\n");
376 return 0;
377
378success:
379 /*
380 * Ok, if we get here, then we've seen the
381 * MSB of the PIT decrement 'i' times, and the
382 * error has shrunk to less than 500 ppm.
383 *
384 * As a result, we can depend on there not being
385 * any odd delays anywhere, and the TSC reads are
386 * reliable (within the error). We also adjust the
387 * delta to the middle of the error bars, just
388 * because it looks nicer.
389 *
390 * kHz = ticks / time-in-seconds / 1000;
391 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
392 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
393 */
394 delta += (long)(d2 - d1)/2;
395 delta *= PIT_TICK_RATE;
396 do_div(delta, i*256*1000);
397 printk("Fast TSC calibration using PIT\n");
398 return delta;
399}
400
401/**
402 * native_calibrate_tsc - calibrate the tsc on boot
403 */
404unsigned long native_calibrate_tsc(void)
405{
406 u64 tsc1, tsc2, delta, ref1, ref2;
407 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
408 unsigned long flags, latch, ms, fast_calibrate;
409 int hpet = is_hpet_enabled(), i, loopmin;
410
411 local_irq_save(flags);
412 fast_calibrate = quick_pit_calibrate();
413 local_irq_restore(flags);
414 if (fast_calibrate)
415 return fast_calibrate;
416
417 /*
418 * Run 5 calibration loops to get the lowest frequency value
419 * (the best estimate). We use two different calibration modes
420 * here:
421 *
422 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
423 * load a timeout of 50ms. We read the time right after we
424 * started the timer and wait until the PIT count down reaches
425 * zero. In each wait loop iteration we read the TSC and check
426 * the delta to the previous read. We keep track of the min
427 * and max values of that delta. The delta is mostly defined
428 * by the IO time of the PIT access, so we can detect when a
429 * SMI/SMM disturbance happened between the two reads. If the
430 * maximum time is significantly larger than the minimum time,
431 * then we discard the result and have another try.
432 *
433 * 2) Reference counter. If available we use the HPET or the
434 * PMTIMER as a reference to check the sanity of that value.
435 * We use separate TSC readouts and check inside of the
436 * reference read for a SMI/SMM disturbance. We dicard
437 * disturbed values here as well. We do that around the PIT
438 * calibration delay loop as we have to wait for a certain
439 * amount of time anyway.
440 */
441
442 /* Preset PIT loop values */
443 latch = CAL_LATCH;
444 ms = CAL_MS;
445 loopmin = CAL_PIT_LOOPS;
446
447 for (i = 0; i < 3; i++) {
448 unsigned long tsc_pit_khz;
449
450 /*
451 * Read the start value and the reference count of
452 * hpet/pmtimer when available. Then do the PIT
453 * calibration, which will take at least 50ms, and
454 * read the end value.
455 */
456 local_irq_save(flags);
457 tsc1 = tsc_read_refs(&ref1, hpet);
458 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
459 tsc2 = tsc_read_refs(&ref2, hpet);
460 local_irq_restore(flags);
461
462 /* Pick the lowest PIT TSC calibration so far */
463 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
464
465 /* hpet or pmtimer available ? */
466 if (ref1 == ref2)
467 continue;
468
469 /* Check, whether the sampling was disturbed by an SMI */
470 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
471 continue;
472
473 tsc2 = (tsc2 - tsc1) * 1000000LL;
474 if (hpet)
475 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
476 else
477 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
478
479 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
480
481 /* Check the reference deviation */
482 delta = ((u64) tsc_pit_min) * 100;
483 do_div(delta, tsc_ref_min);
484
485 /*
486 * If both calibration results are inside a 10% window
487 * then we can be sure, that the calibration
488 * succeeded. We break out of the loop right away. We
489 * use the reference value, as it is more precise.
490 */
491 if (delta >= 90 && delta <= 110) {
492 printk(KERN_INFO
493 "TSC: PIT calibration matches %s. %d loops\n",
494 hpet ? "HPET" : "PMTIMER", i + 1);
495 return tsc_ref_min;
496 }
497
498 /*
499 * Check whether PIT failed more than once. This
500 * happens in virtualized environments. We need to
501 * give the virtual PC a slightly longer timeframe for
502 * the HPET/PMTIMER to make the result precise.
503 */
504 if (i == 1 && tsc_pit_min == ULONG_MAX) {
505 latch = CAL2_LATCH;
506 ms = CAL2_MS;
507 loopmin = CAL2_PIT_LOOPS;
508 }
509 }
510
511 /*
512 * Now check the results.
513 */
514 if (tsc_pit_min == ULONG_MAX) {
515 /* PIT gave no useful value */
516 printk(KERN_WARNING "TSC: Unable to calibrate against PIT\n");
517
518 /* We don't have an alternative source, disable TSC */
519 if (!hpet && !ref1 && !ref2) {
520 printk("TSC: No reference (HPET/PMTIMER) available\n");
521 return 0;
522 }
523
524 /* The alternative source failed as well, disable TSC */
525 if (tsc_ref_min == ULONG_MAX) {
526 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration "
527 "failed.\n");
528 return 0;
529 }
530
531 /* Use the alternative source */
532 printk(KERN_INFO "TSC: using %s reference calibration\n",
533 hpet ? "HPET" : "PMTIMER");
534
535 return tsc_ref_min;
536 }
537
538 /* We don't have an alternative source, use the PIT calibration value */
539 if (!hpet && !ref1 && !ref2) {
540 printk(KERN_INFO "TSC: Using PIT calibration value\n");
541 return tsc_pit_min;
542 }
543
544 /* The alternative source failed, use the PIT calibration value */
545 if (tsc_ref_min == ULONG_MAX) {
546 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed. "
547 "Using PIT calibration\n");
548 return tsc_pit_min;
549 }
550
551 /*
552 * The calibration values differ too much. In doubt, we use
553 * the PIT value as we know that there are PMTIMERs around
554 * running at double speed. At least we let the user know:
555 */
556 printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n",
557 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
558 printk(KERN_INFO "TSC: Using PIT calibration value\n");
559 return tsc_pit_min;
560}
561
562int recalibrate_cpu_khz(void)
563{
564#ifndef CONFIG_SMP
565 unsigned long cpu_khz_old = cpu_khz;
566
567 if (cpu_has_tsc) {
568 tsc_khz = x86_platform.calibrate_tsc();
569 cpu_khz = tsc_khz;
570 cpu_data(0).loops_per_jiffy =
571 cpufreq_scale(cpu_data(0).loops_per_jiffy,
572 cpu_khz_old, cpu_khz);
573 return 0;
574 } else
575 return -ENODEV;
576#else
577 return -ENODEV;
578#endif
579}
580
581EXPORT_SYMBOL(recalibrate_cpu_khz);
582
583
584/* Accelerators for sched_clock()
585 * convert from cycles(64bits) => nanoseconds (64bits)
586 * basic equation:
587 * ns = cycles / (freq / ns_per_sec)
588 * ns = cycles * (ns_per_sec / freq)
589 * ns = cycles * (10^9 / (cpu_khz * 10^3))
590 * ns = cycles * (10^6 / cpu_khz)
591 *
592 * Then we use scaling math (suggested by george@mvista.com) to get:
593 * ns = cycles * (10^6 * SC / cpu_khz) / SC
594 * ns = cycles * cyc2ns_scale / SC
595 *
596 * And since SC is a constant power of two, we can convert the div
597 * into a shift.
598 *
599 * We can use khz divisor instead of mhz to keep a better precision, since
600 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
601 * (mathieu.desnoyers@polymtl.ca)
602 *
603 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
604 */
605
606DEFINE_PER_CPU(unsigned long, cyc2ns);
607DEFINE_PER_CPU(unsigned long long, cyc2ns_offset);
608
609static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
610{
611 unsigned long long tsc_now, ns_now, *offset;
612 unsigned long flags, *scale;
613
614 local_irq_save(flags);
615 sched_clock_idle_sleep_event();
616
617 scale = &per_cpu(cyc2ns, cpu);
618 offset = &per_cpu(cyc2ns_offset, cpu);
619
620 rdtscll(tsc_now);
621 ns_now = __cycles_2_ns(tsc_now);
622
623 if (cpu_khz) {
624 *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
625 *offset = ns_now - (tsc_now * *scale >> CYC2NS_SCALE_FACTOR);
626 }
627
628 sched_clock_idle_wakeup_event(0);
629 local_irq_restore(flags);
630}
631
632static unsigned long long cyc2ns_suspend;
633
634void save_sched_clock_state(void)
635{
636 if (!sched_clock_stable)
637 return;
638
639 cyc2ns_suspend = sched_clock();
640}
641
642/*
643 * Even on processors with invariant TSC, TSC gets reset in some the
644 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
645 * arbitrary value (still sync'd across cpu's) during resume from such sleep
646 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
647 * that sched_clock() continues from the point where it was left off during
648 * suspend.
649 */
650void restore_sched_clock_state(void)
651{
652 unsigned long long offset;
653 unsigned long flags;
654 int cpu;
655
656 if (!sched_clock_stable)
657 return;
658
659 local_irq_save(flags);
660
661 __this_cpu_write(cyc2ns_offset, 0);
662 offset = cyc2ns_suspend - sched_clock();
663
664 for_each_possible_cpu(cpu)
665 per_cpu(cyc2ns_offset, cpu) = offset;
666
667 local_irq_restore(flags);
668}
669
670#ifdef CONFIG_CPU_FREQ
671
672/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
673 * changes.
674 *
675 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
676 * not that important because current Opteron setups do not support
677 * scaling on SMP anyroads.
678 *
679 * Should fix up last_tsc too. Currently gettimeofday in the
680 * first tick after the change will be slightly wrong.
681 */
682
683static unsigned int ref_freq;
684static unsigned long loops_per_jiffy_ref;
685static unsigned long tsc_khz_ref;
686
687static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
688 void *data)
689{
690 struct cpufreq_freqs *freq = data;
691 unsigned long *lpj;
692
693 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
694 return 0;
695
696 lpj = &boot_cpu_data.loops_per_jiffy;
697#ifdef CONFIG_SMP
698 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
699 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
700#endif
701
702 if (!ref_freq) {
703 ref_freq = freq->old;
704 loops_per_jiffy_ref = *lpj;
705 tsc_khz_ref = tsc_khz;
706 }
707 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
708 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
709 (val == CPUFREQ_RESUMECHANGE)) {
710 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
711
712 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
713 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
714 mark_tsc_unstable("cpufreq changes");
715 }
716
717 set_cyc2ns_scale(tsc_khz, freq->cpu);
718
719 return 0;
720}
721
722static struct notifier_block time_cpufreq_notifier_block = {
723 .notifier_call = time_cpufreq_notifier
724};
725
726static int __init cpufreq_tsc(void)
727{
728 if (!cpu_has_tsc)
729 return 0;
730 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
731 return 0;
732 cpufreq_register_notifier(&time_cpufreq_notifier_block,
733 CPUFREQ_TRANSITION_NOTIFIER);
734 return 0;
735}
736
737core_initcall(cpufreq_tsc);
738
739#endif /* CONFIG_CPU_FREQ */
740
741/* clocksource code */
742
743static struct clocksource clocksource_tsc;
744
745/*
746 * We compare the TSC to the cycle_last value in the clocksource
747 * structure to avoid a nasty time-warp. This can be observed in a
748 * very small window right after one CPU updated cycle_last under
749 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
750 * is smaller than the cycle_last reference value due to a TSC which
751 * is slighty behind. This delta is nowhere else observable, but in
752 * that case it results in a forward time jump in the range of hours
753 * due to the unsigned delta calculation of the time keeping core
754 * code, which is necessary to support wrapping clocksources like pm
755 * timer.
756 */
757static cycle_t read_tsc(struct clocksource *cs)
758{
759 cycle_t ret = (cycle_t)get_cycles();
760
761 return ret >= clocksource_tsc.cycle_last ?
762 ret : clocksource_tsc.cycle_last;
763}
764
765static void resume_tsc(struct clocksource *cs)
766{
767 clocksource_tsc.cycle_last = 0;
768}
769
770static struct clocksource clocksource_tsc = {
771 .name = "tsc",
772 .rating = 300,
773 .read = read_tsc,
774 .resume = resume_tsc,
775 .mask = CLOCKSOURCE_MASK(64),
776 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
777 CLOCK_SOURCE_MUST_VERIFY,
778#ifdef CONFIG_X86_64
779 .archdata = { .vclock_mode = VCLOCK_TSC },
780#endif
781};
782
783void mark_tsc_unstable(char *reason)
784{
785 if (!tsc_unstable) {
786 tsc_unstable = 1;
787 sched_clock_stable = 0;
788 disable_sched_clock_irqtime();
789 printk(KERN_INFO "Marking TSC unstable due to %s\n", reason);
790 /* Change only the rating, when not registered */
791 if (clocksource_tsc.mult)
792 clocksource_mark_unstable(&clocksource_tsc);
793 else {
794 clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
795 clocksource_tsc.rating = 0;
796 }
797 }
798}
799
800EXPORT_SYMBOL_GPL(mark_tsc_unstable);
801
802static void __init check_system_tsc_reliable(void)
803{
804#ifdef CONFIG_MGEODE_LX
805 /* RTSC counts during suspend */
806#define RTSC_SUSP 0x100
807 unsigned long res_low, res_high;
808
809 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
810 /* Geode_LX - the OLPC CPU has a very reliable TSC */
811 if (res_low & RTSC_SUSP)
812 tsc_clocksource_reliable = 1;
813#endif
814 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
815 tsc_clocksource_reliable = 1;
816}
817
818/*
819 * Make an educated guess if the TSC is trustworthy and synchronized
820 * over all CPUs.
821 */
822__cpuinit int unsynchronized_tsc(void)
823{
824 if (!cpu_has_tsc || tsc_unstable)
825 return 1;
826
827#ifdef CONFIG_SMP
828 if (apic_is_clustered_box())
829 return 1;
830#endif
831
832 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
833 return 0;
834
835 if (tsc_clocksource_reliable)
836 return 0;
837 /*
838 * Intel systems are normally all synchronized.
839 * Exceptions must mark TSC as unstable:
840 */
841 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
842 /* assume multi socket systems are not synchronized: */
843 if (num_possible_cpus() > 1)
844 return 1;
845 }
846
847 return 0;
848}
849
850
851static void tsc_refine_calibration_work(struct work_struct *work);
852static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
853/**
854 * tsc_refine_calibration_work - Further refine tsc freq calibration
855 * @work - ignored.
856 *
857 * This functions uses delayed work over a period of a
858 * second to further refine the TSC freq value. Since this is
859 * timer based, instead of loop based, we don't block the boot
860 * process while this longer calibration is done.
861 *
862 * If there are any calibration anomalies (too many SMIs, etc),
863 * or the refined calibration is off by 1% of the fast early
864 * calibration, we throw out the new calibration and use the
865 * early calibration.
866 */
867static void tsc_refine_calibration_work(struct work_struct *work)
868{
869 static u64 tsc_start = -1, ref_start;
870 static int hpet;
871 u64 tsc_stop, ref_stop, delta;
872 unsigned long freq;
873
874 /* Don't bother refining TSC on unstable systems */
875 if (check_tsc_unstable())
876 goto out;
877
878 /*
879 * Since the work is started early in boot, we may be
880 * delayed the first time we expire. So set the workqueue
881 * again once we know timers are working.
882 */
883 if (tsc_start == -1) {
884 /*
885 * Only set hpet once, to avoid mixing hardware
886 * if the hpet becomes enabled later.
887 */
888 hpet = is_hpet_enabled();
889 schedule_delayed_work(&tsc_irqwork, HZ);
890 tsc_start = tsc_read_refs(&ref_start, hpet);
891 return;
892 }
893
894 tsc_stop = tsc_read_refs(&ref_stop, hpet);
895
896 /* hpet or pmtimer available ? */
897 if (ref_start == ref_stop)
898 goto out;
899
900 /* Check, whether the sampling was disturbed by an SMI */
901 if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
902 goto out;
903
904 delta = tsc_stop - tsc_start;
905 delta *= 1000000LL;
906 if (hpet)
907 freq = calc_hpet_ref(delta, ref_start, ref_stop);
908 else
909 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
910
911 /* Make sure we're within 1% */
912 if (abs(tsc_khz - freq) > tsc_khz/100)
913 goto out;
914
915 tsc_khz = freq;
916 printk(KERN_INFO "Refined TSC clocksource calibration: "
917 "%lu.%03lu MHz.\n", (unsigned long)tsc_khz / 1000,
918 (unsigned long)tsc_khz % 1000);
919
920out:
921 clocksource_register_khz(&clocksource_tsc, tsc_khz);
922}
923
924
925static int __init init_tsc_clocksource(void)
926{
927 if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
928 return 0;
929
930 if (tsc_clocksource_reliable)
931 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
932 /* lower the rating if we already know its unstable: */
933 if (check_tsc_unstable()) {
934 clocksource_tsc.rating = 0;
935 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
936 }
937 schedule_delayed_work(&tsc_irqwork, 0);
938 return 0;
939}
940/*
941 * We use device_initcall here, to ensure we run after the hpet
942 * is fully initialized, which may occur at fs_initcall time.
943 */
944device_initcall(init_tsc_clocksource);
945
946void __init tsc_init(void)
947{
948 u64 lpj;
949 int cpu;
950
951 x86_init.timers.tsc_pre_init();
952
953 if (!cpu_has_tsc)
954 return;
955
956 tsc_khz = x86_platform.calibrate_tsc();
957 cpu_khz = tsc_khz;
958
959 if (!tsc_khz) {
960 mark_tsc_unstable("could not calculate TSC khz");
961 return;
962 }
963
964 printk("Detected %lu.%03lu MHz processor.\n",
965 (unsigned long)cpu_khz / 1000,
966 (unsigned long)cpu_khz % 1000);
967
968 /*
969 * Secondary CPUs do not run through tsc_init(), so set up
970 * all the scale factors for all CPUs, assuming the same
971 * speed as the bootup CPU. (cpufreq notifiers will fix this
972 * up if their speed diverges)
973 */
974 for_each_possible_cpu(cpu)
975 set_cyc2ns_scale(cpu_khz, cpu);
976
977 if (tsc_disabled > 0)
978 return;
979
980 /* now allow native_sched_clock() to use rdtsc */
981 tsc_disabled = 0;
982
983 if (!no_sched_irq_time)
984 enable_sched_clock_irqtime();
985
986 lpj = ((u64)tsc_khz * 1000);
987 do_div(lpj, HZ);
988 lpj_fine = lpj;
989
990 use_tsc_delay();
991
992 if (unsynchronized_tsc())
993 mark_tsc_unstable("TSCs unsynchronized");
994
995 check_system_tsc_reliable();
996}
997