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1#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
2
3#include <linux/kernel.h>
4#include <linux/sched.h>
5#include <linux/sched/clock.h>
6#include <linux/init.h>
7#include <linux/export.h>
8#include <linux/timer.h>
9#include <linux/acpi_pmtmr.h>
10#include <linux/cpufreq.h>
11#include <linux/delay.h>
12#include <linux/clocksource.h>
13#include <linux/percpu.h>
14#include <linux/timex.h>
15#include <linux/static_key.h>
16
17#include <asm/hpet.h>
18#include <asm/timer.h>
19#include <asm/vgtod.h>
20#include <asm/time.h>
21#include <asm/delay.h>
22#include <asm/hypervisor.h>
23#include <asm/nmi.h>
24#include <asm/x86_init.h>
25#include <asm/geode.h>
26#include <asm/apic.h>
27#include <asm/intel-family.h>
28#include <asm/i8259.h>
29
30unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
31EXPORT_SYMBOL(cpu_khz);
32
33unsigned int __read_mostly tsc_khz;
34EXPORT_SYMBOL(tsc_khz);
35
36/*
37 * TSC can be unstable due to cpufreq or due to unsynced TSCs
38 */
39static int __read_mostly tsc_unstable;
40
41/* native_sched_clock() is called before tsc_init(), so
42 we must start with the TSC soft disabled to prevent
43 erroneous rdtsc usage on !boot_cpu_has(X86_FEATURE_TSC) processors */
44static int __read_mostly tsc_disabled = -1;
45
46static DEFINE_STATIC_KEY_FALSE(__use_tsc);
47
48int tsc_clocksource_reliable;
49
50static u32 art_to_tsc_numerator;
51static u32 art_to_tsc_denominator;
52static u64 art_to_tsc_offset;
53struct clocksource *art_related_clocksource;
54
55struct cyc2ns {
56 struct cyc2ns_data data[2]; /* 0 + 2*16 = 32 */
57 seqcount_t seq; /* 32 + 4 = 36 */
58
59}; /* fits one cacheline */
60
61static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
62
63void cyc2ns_read_begin(struct cyc2ns_data *data)
64{
65 int seq, idx;
66
67 preempt_disable_notrace();
68
69 do {
70 seq = this_cpu_read(cyc2ns.seq.sequence);
71 idx = seq & 1;
72
73 data->cyc2ns_offset = this_cpu_read(cyc2ns.data[idx].cyc2ns_offset);
74 data->cyc2ns_mul = this_cpu_read(cyc2ns.data[idx].cyc2ns_mul);
75 data->cyc2ns_shift = this_cpu_read(cyc2ns.data[idx].cyc2ns_shift);
76
77 } while (unlikely(seq != this_cpu_read(cyc2ns.seq.sequence)));
78}
79
80void cyc2ns_read_end(void)
81{
82 preempt_enable_notrace();
83}
84
85/*
86 * Accelerators for sched_clock()
87 * convert from cycles(64bits) => nanoseconds (64bits)
88 * basic equation:
89 * ns = cycles / (freq / ns_per_sec)
90 * ns = cycles * (ns_per_sec / freq)
91 * ns = cycles * (10^9 / (cpu_khz * 10^3))
92 * ns = cycles * (10^6 / cpu_khz)
93 *
94 * Then we use scaling math (suggested by george@mvista.com) to get:
95 * ns = cycles * (10^6 * SC / cpu_khz) / SC
96 * ns = cycles * cyc2ns_scale / SC
97 *
98 * And since SC is a constant power of two, we can convert the div
99 * into a shift. The larger SC is, the more accurate the conversion, but
100 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication
101 * (64-bit result) can be used.
102 *
103 * We can use khz divisor instead of mhz to keep a better precision.
104 * (mathieu.desnoyers@polymtl.ca)
105 *
106 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
107 */
108
109static void cyc2ns_data_init(struct cyc2ns_data *data)
110{
111 data->cyc2ns_mul = 0;
112 data->cyc2ns_shift = 0;
113 data->cyc2ns_offset = 0;
114}
115
116static void __init cyc2ns_init(int cpu)
117{
118 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
119
120 cyc2ns_data_init(&c2n->data[0]);
121 cyc2ns_data_init(&c2n->data[1]);
122
123 seqcount_init(&c2n->seq);
124}
125
126static inline unsigned long long cycles_2_ns(unsigned long long cyc)
127{
128 struct cyc2ns_data data;
129 unsigned long long ns;
130
131 cyc2ns_read_begin(&data);
132
133 ns = data.cyc2ns_offset;
134 ns += mul_u64_u32_shr(cyc, data.cyc2ns_mul, data.cyc2ns_shift);
135
136 cyc2ns_read_end();
137
138 return ns;
139}
140
141static void set_cyc2ns_scale(unsigned long khz, int cpu, unsigned long long tsc_now)
142{
143 unsigned long long ns_now;
144 struct cyc2ns_data data;
145 struct cyc2ns *c2n;
146 unsigned long flags;
147
148 local_irq_save(flags);
149 sched_clock_idle_sleep_event();
150
151 if (!khz)
152 goto done;
153
154 ns_now = cycles_2_ns(tsc_now);
155
156 /*
157 * Compute a new multiplier as per the above comment and ensure our
158 * time function is continuous; see the comment near struct
159 * cyc2ns_data.
160 */
161 clocks_calc_mult_shift(&data.cyc2ns_mul, &data.cyc2ns_shift, khz,
162 NSEC_PER_MSEC, 0);
163
164 /*
165 * cyc2ns_shift is exported via arch_perf_update_userpage() where it is
166 * not expected to be greater than 31 due to the original published
167 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit
168 * value) - refer perf_event_mmap_page documentation in perf_event.h.
169 */
170 if (data.cyc2ns_shift == 32) {
171 data.cyc2ns_shift = 31;
172 data.cyc2ns_mul >>= 1;
173 }
174
175 data.cyc2ns_offset = ns_now -
176 mul_u64_u32_shr(tsc_now, data.cyc2ns_mul, data.cyc2ns_shift);
177
178 c2n = per_cpu_ptr(&cyc2ns, cpu);
179
180 raw_write_seqcount_latch(&c2n->seq);
181 c2n->data[0] = data;
182 raw_write_seqcount_latch(&c2n->seq);
183 c2n->data[1] = data;
184
185done:
186 sched_clock_idle_wakeup_event();
187 local_irq_restore(flags);
188}
189
190/*
191 * Scheduler clock - returns current time in nanosec units.
192 */
193u64 native_sched_clock(void)
194{
195 if (static_branch_likely(&__use_tsc)) {
196 u64 tsc_now = rdtsc();
197
198 /* return the value in ns */
199 return cycles_2_ns(tsc_now);
200 }
201
202 /*
203 * Fall back to jiffies if there's no TSC available:
204 * ( But note that we still use it if the TSC is marked
205 * unstable. We do this because unlike Time Of Day,
206 * the scheduler clock tolerates small errors and it's
207 * very important for it to be as fast as the platform
208 * can achieve it. )
209 */
210
211 /* No locking but a rare wrong value is not a big deal: */
212 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
213}
214
215/*
216 * Generate a sched_clock if you already have a TSC value.
217 */
218u64 native_sched_clock_from_tsc(u64 tsc)
219{
220 return cycles_2_ns(tsc);
221}
222
223/* We need to define a real function for sched_clock, to override the
224 weak default version */
225#ifdef CONFIG_PARAVIRT
226unsigned long long sched_clock(void)
227{
228 return paravirt_sched_clock();
229}
230
231bool using_native_sched_clock(void)
232{
233 return pv_time_ops.sched_clock == native_sched_clock;
234}
235#else
236unsigned long long
237sched_clock(void) __attribute__((alias("native_sched_clock")));
238
239bool using_native_sched_clock(void) { return true; }
240#endif
241
242int check_tsc_unstable(void)
243{
244 return tsc_unstable;
245}
246EXPORT_SYMBOL_GPL(check_tsc_unstable);
247
248#ifdef CONFIG_X86_TSC
249int __init notsc_setup(char *str)
250{
251 pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
252 tsc_disabled = 1;
253 return 1;
254}
255#else
256/*
257 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
258 * in cpu/common.c
259 */
260int __init notsc_setup(char *str)
261{
262 setup_clear_cpu_cap(X86_FEATURE_TSC);
263 return 1;
264}
265#endif
266
267__setup("notsc", notsc_setup);
268
269static int no_sched_irq_time;
270
271static int __init tsc_setup(char *str)
272{
273 if (!strcmp(str, "reliable"))
274 tsc_clocksource_reliable = 1;
275 if (!strncmp(str, "noirqtime", 9))
276 no_sched_irq_time = 1;
277 if (!strcmp(str, "unstable"))
278 mark_tsc_unstable("boot parameter");
279 return 1;
280}
281
282__setup("tsc=", tsc_setup);
283
284#define MAX_RETRIES 5
285#define SMI_TRESHOLD 50000
286
287/*
288 * Read TSC and the reference counters. Take care of SMI disturbance
289 */
290static u64 tsc_read_refs(u64 *p, int hpet)
291{
292 u64 t1, t2;
293 int i;
294
295 for (i = 0; i < MAX_RETRIES; i++) {
296 t1 = get_cycles();
297 if (hpet)
298 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
299 else
300 *p = acpi_pm_read_early();
301 t2 = get_cycles();
302 if ((t2 - t1) < SMI_TRESHOLD)
303 return t2;
304 }
305 return ULLONG_MAX;
306}
307
308/*
309 * Calculate the TSC frequency from HPET reference
310 */
311static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
312{
313 u64 tmp;
314
315 if (hpet2 < hpet1)
316 hpet2 += 0x100000000ULL;
317 hpet2 -= hpet1;
318 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
319 do_div(tmp, 1000000);
320 deltatsc = div64_u64(deltatsc, tmp);
321
322 return (unsigned long) deltatsc;
323}
324
325/*
326 * Calculate the TSC frequency from PMTimer reference
327 */
328static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
329{
330 u64 tmp;
331
332 if (!pm1 && !pm2)
333 return ULONG_MAX;
334
335 if (pm2 < pm1)
336 pm2 += (u64)ACPI_PM_OVRRUN;
337 pm2 -= pm1;
338 tmp = pm2 * 1000000000LL;
339 do_div(tmp, PMTMR_TICKS_PER_SEC);
340 do_div(deltatsc, tmp);
341
342 return (unsigned long) deltatsc;
343}
344
345#define CAL_MS 10
346#define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
347#define CAL_PIT_LOOPS 1000
348
349#define CAL2_MS 50
350#define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
351#define CAL2_PIT_LOOPS 5000
352
353
354/*
355 * Try to calibrate the TSC against the Programmable
356 * Interrupt Timer and return the frequency of the TSC
357 * in kHz.
358 *
359 * Return ULONG_MAX on failure to calibrate.
360 */
361static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
362{
363 u64 tsc, t1, t2, delta;
364 unsigned long tscmin, tscmax;
365 int pitcnt;
366
367 if (!has_legacy_pic()) {
368 /*
369 * Relies on tsc_early_delay_calibrate() to have given us semi
370 * usable udelay(), wait for the same 50ms we would have with
371 * the PIT loop below.
372 */
373 udelay(10 * USEC_PER_MSEC);
374 udelay(10 * USEC_PER_MSEC);
375 udelay(10 * USEC_PER_MSEC);
376 udelay(10 * USEC_PER_MSEC);
377 udelay(10 * USEC_PER_MSEC);
378 return ULONG_MAX;
379 }
380
381 /* Set the Gate high, disable speaker */
382 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
383
384 /*
385 * Setup CTC channel 2* for mode 0, (interrupt on terminal
386 * count mode), binary count. Set the latch register to 50ms
387 * (LSB then MSB) to begin countdown.
388 */
389 outb(0xb0, 0x43);
390 outb(latch & 0xff, 0x42);
391 outb(latch >> 8, 0x42);
392
393 tsc = t1 = t2 = get_cycles();
394
395 pitcnt = 0;
396 tscmax = 0;
397 tscmin = ULONG_MAX;
398 while ((inb(0x61) & 0x20) == 0) {
399 t2 = get_cycles();
400 delta = t2 - tsc;
401 tsc = t2;
402 if ((unsigned long) delta < tscmin)
403 tscmin = (unsigned int) delta;
404 if ((unsigned long) delta > tscmax)
405 tscmax = (unsigned int) delta;
406 pitcnt++;
407 }
408
409 /*
410 * Sanity checks:
411 *
412 * If we were not able to read the PIT more than loopmin
413 * times, then we have been hit by a massive SMI
414 *
415 * If the maximum is 10 times larger than the minimum,
416 * then we got hit by an SMI as well.
417 */
418 if (pitcnt < loopmin || tscmax > 10 * tscmin)
419 return ULONG_MAX;
420
421 /* Calculate the PIT value */
422 delta = t2 - t1;
423 do_div(delta, ms);
424 return delta;
425}
426
427/*
428 * This reads the current MSB of the PIT counter, and
429 * checks if we are running on sufficiently fast and
430 * non-virtualized hardware.
431 *
432 * Our expectations are:
433 *
434 * - the PIT is running at roughly 1.19MHz
435 *
436 * - each IO is going to take about 1us on real hardware,
437 * but we allow it to be much faster (by a factor of 10) or
438 * _slightly_ slower (ie we allow up to a 2us read+counter
439 * update - anything else implies a unacceptably slow CPU
440 * or PIT for the fast calibration to work.
441 *
442 * - with 256 PIT ticks to read the value, we have 214us to
443 * see the same MSB (and overhead like doing a single TSC
444 * read per MSB value etc).
445 *
446 * - We're doing 2 reads per loop (LSB, MSB), and we expect
447 * them each to take about a microsecond on real hardware.
448 * So we expect a count value of around 100. But we'll be
449 * generous, and accept anything over 50.
450 *
451 * - if the PIT is stuck, and we see *many* more reads, we
452 * return early (and the next caller of pit_expect_msb()
453 * then consider it a failure when they don't see the
454 * next expected value).
455 *
456 * These expectations mean that we know that we have seen the
457 * transition from one expected value to another with a fairly
458 * high accuracy, and we didn't miss any events. We can thus
459 * use the TSC value at the transitions to calculate a pretty
460 * good value for the TSC frequencty.
461 */
462static inline int pit_verify_msb(unsigned char val)
463{
464 /* Ignore LSB */
465 inb(0x42);
466 return inb(0x42) == val;
467}
468
469static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
470{
471 int count;
472 u64 tsc = 0, prev_tsc = 0;
473
474 for (count = 0; count < 50000; count++) {
475 if (!pit_verify_msb(val))
476 break;
477 prev_tsc = tsc;
478 tsc = get_cycles();
479 }
480 *deltap = get_cycles() - prev_tsc;
481 *tscp = tsc;
482
483 /*
484 * We require _some_ success, but the quality control
485 * will be based on the error terms on the TSC values.
486 */
487 return count > 5;
488}
489
490/*
491 * How many MSB values do we want to see? We aim for
492 * a maximum error rate of 500ppm (in practice the
493 * real error is much smaller), but refuse to spend
494 * more than 50ms on it.
495 */
496#define MAX_QUICK_PIT_MS 50
497#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
498
499static unsigned long quick_pit_calibrate(void)
500{
501 int i;
502 u64 tsc, delta;
503 unsigned long d1, d2;
504
505 if (!has_legacy_pic())
506 return 0;
507
508 /* Set the Gate high, disable speaker */
509 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
510
511 /*
512 * Counter 2, mode 0 (one-shot), binary count
513 *
514 * NOTE! Mode 2 decrements by two (and then the
515 * output is flipped each time, giving the same
516 * final output frequency as a decrement-by-one),
517 * so mode 0 is much better when looking at the
518 * individual counts.
519 */
520 outb(0xb0, 0x43);
521
522 /* Start at 0xffff */
523 outb(0xff, 0x42);
524 outb(0xff, 0x42);
525
526 /*
527 * The PIT starts counting at the next edge, so we
528 * need to delay for a microsecond. The easiest way
529 * to do that is to just read back the 16-bit counter
530 * once from the PIT.
531 */
532 pit_verify_msb(0);
533
534 if (pit_expect_msb(0xff, &tsc, &d1)) {
535 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
536 if (!pit_expect_msb(0xff-i, &delta, &d2))
537 break;
538
539 delta -= tsc;
540
541 /*
542 * Extrapolate the error and fail fast if the error will
543 * never be below 500 ppm.
544 */
545 if (i == 1 &&
546 d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11)
547 return 0;
548
549 /*
550 * Iterate until the error is less than 500 ppm
551 */
552 if (d1+d2 >= delta >> 11)
553 continue;
554
555 /*
556 * Check the PIT one more time to verify that
557 * all TSC reads were stable wrt the PIT.
558 *
559 * This also guarantees serialization of the
560 * last cycle read ('d2') in pit_expect_msb.
561 */
562 if (!pit_verify_msb(0xfe - i))
563 break;
564 goto success;
565 }
566 }
567 pr_info("Fast TSC calibration failed\n");
568 return 0;
569
570success:
571 /*
572 * Ok, if we get here, then we've seen the
573 * MSB of the PIT decrement 'i' times, and the
574 * error has shrunk to less than 500 ppm.
575 *
576 * As a result, we can depend on there not being
577 * any odd delays anywhere, and the TSC reads are
578 * reliable (within the error).
579 *
580 * kHz = ticks / time-in-seconds / 1000;
581 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
582 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
583 */
584 delta *= PIT_TICK_RATE;
585 do_div(delta, i*256*1000);
586 pr_info("Fast TSC calibration using PIT\n");
587 return delta;
588}
589
590/**
591 * native_calibrate_tsc
592 * Determine TSC frequency via CPUID, else return 0.
593 */
594unsigned long native_calibrate_tsc(void)
595{
596 unsigned int eax_denominator, ebx_numerator, ecx_hz, edx;
597 unsigned int crystal_khz;
598
599 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
600 return 0;
601
602 if (boot_cpu_data.cpuid_level < 0x15)
603 return 0;
604
605 eax_denominator = ebx_numerator = ecx_hz = edx = 0;
606
607 /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
608 cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx);
609
610 if (ebx_numerator == 0 || eax_denominator == 0)
611 return 0;
612
613 crystal_khz = ecx_hz / 1000;
614
615 if (crystal_khz == 0) {
616 switch (boot_cpu_data.x86_model) {
617 case INTEL_FAM6_SKYLAKE_MOBILE:
618 case INTEL_FAM6_SKYLAKE_DESKTOP:
619 case INTEL_FAM6_KABYLAKE_MOBILE:
620 case INTEL_FAM6_KABYLAKE_DESKTOP:
621 crystal_khz = 24000; /* 24.0 MHz */
622 break;
623 case INTEL_FAM6_ATOM_DENVERTON:
624 crystal_khz = 25000; /* 25.0 MHz */
625 break;
626 case INTEL_FAM6_ATOM_GOLDMONT:
627 crystal_khz = 19200; /* 19.2 MHz */
628 break;
629 }
630 }
631
632 if (crystal_khz == 0)
633 return 0;
634 /*
635 * TSC frequency determined by CPUID is a "hardware reported"
636 * frequency and is the most accurate one so far we have. This
637 * is considered a known frequency.
638 */
639 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
640
641 /*
642 * For Atom SoCs TSC is the only reliable clocksource.
643 * Mark TSC reliable so no watchdog on it.
644 */
645 if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
646 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
647
648 return crystal_khz * ebx_numerator / eax_denominator;
649}
650
651static unsigned long cpu_khz_from_cpuid(void)
652{
653 unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx;
654
655 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
656 return 0;
657
658 if (boot_cpu_data.cpuid_level < 0x16)
659 return 0;
660
661 eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0;
662
663 cpuid(0x16, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx);
664
665 return eax_base_mhz * 1000;
666}
667
668/**
669 * native_calibrate_cpu - calibrate the cpu on boot
670 */
671unsigned long native_calibrate_cpu(void)
672{
673 u64 tsc1, tsc2, delta, ref1, ref2;
674 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
675 unsigned long flags, latch, ms, fast_calibrate;
676 int hpet = is_hpet_enabled(), i, loopmin;
677
678 fast_calibrate = cpu_khz_from_cpuid();
679 if (fast_calibrate)
680 return fast_calibrate;
681
682 fast_calibrate = cpu_khz_from_msr();
683 if (fast_calibrate)
684 return fast_calibrate;
685
686 local_irq_save(flags);
687 fast_calibrate = quick_pit_calibrate();
688 local_irq_restore(flags);
689 if (fast_calibrate)
690 return fast_calibrate;
691
692 /*
693 * Run 5 calibration loops to get the lowest frequency value
694 * (the best estimate). We use two different calibration modes
695 * here:
696 *
697 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
698 * load a timeout of 50ms. We read the time right after we
699 * started the timer and wait until the PIT count down reaches
700 * zero. In each wait loop iteration we read the TSC and check
701 * the delta to the previous read. We keep track of the min
702 * and max values of that delta. The delta is mostly defined
703 * by the IO time of the PIT access, so we can detect when a
704 * SMI/SMM disturbance happened between the two reads. If the
705 * maximum time is significantly larger than the minimum time,
706 * then we discard the result and have another try.
707 *
708 * 2) Reference counter. If available we use the HPET or the
709 * PMTIMER as a reference to check the sanity of that value.
710 * We use separate TSC readouts and check inside of the
711 * reference read for a SMI/SMM disturbance. We dicard
712 * disturbed values here as well. We do that around the PIT
713 * calibration delay loop as we have to wait for a certain
714 * amount of time anyway.
715 */
716
717 /* Preset PIT loop values */
718 latch = CAL_LATCH;
719 ms = CAL_MS;
720 loopmin = CAL_PIT_LOOPS;
721
722 for (i = 0; i < 3; i++) {
723 unsigned long tsc_pit_khz;
724
725 /*
726 * Read the start value and the reference count of
727 * hpet/pmtimer when available. Then do the PIT
728 * calibration, which will take at least 50ms, and
729 * read the end value.
730 */
731 local_irq_save(flags);
732 tsc1 = tsc_read_refs(&ref1, hpet);
733 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
734 tsc2 = tsc_read_refs(&ref2, hpet);
735 local_irq_restore(flags);
736
737 /* Pick the lowest PIT TSC calibration so far */
738 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
739
740 /* hpet or pmtimer available ? */
741 if (ref1 == ref2)
742 continue;
743
744 /* Check, whether the sampling was disturbed by an SMI */
745 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
746 continue;
747
748 tsc2 = (tsc2 - tsc1) * 1000000LL;
749 if (hpet)
750 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
751 else
752 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
753
754 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
755
756 /* Check the reference deviation */
757 delta = ((u64) tsc_pit_min) * 100;
758 do_div(delta, tsc_ref_min);
759
760 /*
761 * If both calibration results are inside a 10% window
762 * then we can be sure, that the calibration
763 * succeeded. We break out of the loop right away. We
764 * use the reference value, as it is more precise.
765 */
766 if (delta >= 90 && delta <= 110) {
767 pr_info("PIT calibration matches %s. %d loops\n",
768 hpet ? "HPET" : "PMTIMER", i + 1);
769 return tsc_ref_min;
770 }
771
772 /*
773 * Check whether PIT failed more than once. This
774 * happens in virtualized environments. We need to
775 * give the virtual PC a slightly longer timeframe for
776 * the HPET/PMTIMER to make the result precise.
777 */
778 if (i == 1 && tsc_pit_min == ULONG_MAX) {
779 latch = CAL2_LATCH;
780 ms = CAL2_MS;
781 loopmin = CAL2_PIT_LOOPS;
782 }
783 }
784
785 /*
786 * Now check the results.
787 */
788 if (tsc_pit_min == ULONG_MAX) {
789 /* PIT gave no useful value */
790 pr_warn("Unable to calibrate against PIT\n");
791
792 /* We don't have an alternative source, disable TSC */
793 if (!hpet && !ref1 && !ref2) {
794 pr_notice("No reference (HPET/PMTIMER) available\n");
795 return 0;
796 }
797
798 /* The alternative source failed as well, disable TSC */
799 if (tsc_ref_min == ULONG_MAX) {
800 pr_warn("HPET/PMTIMER calibration failed\n");
801 return 0;
802 }
803
804 /* Use the alternative source */
805 pr_info("using %s reference calibration\n",
806 hpet ? "HPET" : "PMTIMER");
807
808 return tsc_ref_min;
809 }
810
811 /* We don't have an alternative source, use the PIT calibration value */
812 if (!hpet && !ref1 && !ref2) {
813 pr_info("Using PIT calibration value\n");
814 return tsc_pit_min;
815 }
816
817 /* The alternative source failed, use the PIT calibration value */
818 if (tsc_ref_min == ULONG_MAX) {
819 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
820 return tsc_pit_min;
821 }
822
823 /*
824 * The calibration values differ too much. In doubt, we use
825 * the PIT value as we know that there are PMTIMERs around
826 * running at double speed. At least we let the user know:
827 */
828 pr_warn("PIT calibration deviates from %s: %lu %lu\n",
829 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
830 pr_info("Using PIT calibration value\n");
831 return tsc_pit_min;
832}
833
834void recalibrate_cpu_khz(void)
835{
836#ifndef CONFIG_SMP
837 unsigned long cpu_khz_old = cpu_khz;
838
839 if (!boot_cpu_has(X86_FEATURE_TSC))
840 return;
841
842 cpu_khz = x86_platform.calibrate_cpu();
843 tsc_khz = x86_platform.calibrate_tsc();
844 if (tsc_khz == 0)
845 tsc_khz = cpu_khz;
846 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
847 cpu_khz = tsc_khz;
848 cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy,
849 cpu_khz_old, cpu_khz);
850#endif
851}
852
853EXPORT_SYMBOL(recalibrate_cpu_khz);
854
855
856static unsigned long long cyc2ns_suspend;
857
858void tsc_save_sched_clock_state(void)
859{
860 if (!sched_clock_stable())
861 return;
862
863 cyc2ns_suspend = sched_clock();
864}
865
866/*
867 * Even on processors with invariant TSC, TSC gets reset in some the
868 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
869 * arbitrary value (still sync'd across cpu's) during resume from such sleep
870 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
871 * that sched_clock() continues from the point where it was left off during
872 * suspend.
873 */
874void tsc_restore_sched_clock_state(void)
875{
876 unsigned long long offset;
877 unsigned long flags;
878 int cpu;
879
880 if (!sched_clock_stable())
881 return;
882
883 local_irq_save(flags);
884
885 /*
886 * We're coming out of suspend, there's no concurrency yet; don't
887 * bother being nice about the RCU stuff, just write to both
888 * data fields.
889 */
890
891 this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0);
892 this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0);
893
894 offset = cyc2ns_suspend - sched_clock();
895
896 for_each_possible_cpu(cpu) {
897 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset;
898 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset;
899 }
900
901 local_irq_restore(flags);
902}
903
904#ifdef CONFIG_CPU_FREQ
905/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
906 * changes.
907 *
908 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
909 * not that important because current Opteron setups do not support
910 * scaling on SMP anyroads.
911 *
912 * Should fix up last_tsc too. Currently gettimeofday in the
913 * first tick after the change will be slightly wrong.
914 */
915
916static unsigned int ref_freq;
917static unsigned long loops_per_jiffy_ref;
918static unsigned long tsc_khz_ref;
919
920static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
921 void *data)
922{
923 struct cpufreq_freqs *freq = data;
924 unsigned long *lpj;
925
926 lpj = &boot_cpu_data.loops_per_jiffy;
927#ifdef CONFIG_SMP
928 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
929 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
930#endif
931
932 if (!ref_freq) {
933 ref_freq = freq->old;
934 loops_per_jiffy_ref = *lpj;
935 tsc_khz_ref = tsc_khz;
936 }
937 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
938 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
939 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
940
941 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
942 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
943 mark_tsc_unstable("cpufreq changes");
944
945 set_cyc2ns_scale(tsc_khz, freq->cpu, rdtsc());
946 }
947
948 return 0;
949}
950
951static struct notifier_block time_cpufreq_notifier_block = {
952 .notifier_call = time_cpufreq_notifier
953};
954
955static int __init cpufreq_register_tsc_scaling(void)
956{
957 if (!boot_cpu_has(X86_FEATURE_TSC))
958 return 0;
959 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
960 return 0;
961 cpufreq_register_notifier(&time_cpufreq_notifier_block,
962 CPUFREQ_TRANSITION_NOTIFIER);
963 return 0;
964}
965
966core_initcall(cpufreq_register_tsc_scaling);
967
968#endif /* CONFIG_CPU_FREQ */
969
970#define ART_CPUID_LEAF (0x15)
971#define ART_MIN_DENOMINATOR (1)
972
973
974/*
975 * If ART is present detect the numerator:denominator to convert to TSC
976 */
977static void __init detect_art(void)
978{
979 unsigned int unused[2];
980
981 if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF)
982 return;
983
984 /*
985 * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required,
986 * and the TSC counter resets must not occur asynchronously.
987 */
988 if (boot_cpu_has(X86_FEATURE_HYPERVISOR) ||
989 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) ||
990 !boot_cpu_has(X86_FEATURE_TSC_ADJUST) ||
991 tsc_async_resets)
992 return;
993
994 cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator,
995 &art_to_tsc_numerator, unused, unused+1);
996
997 if (art_to_tsc_denominator < ART_MIN_DENOMINATOR)
998 return;
999
1000 rdmsrl(MSR_IA32_TSC_ADJUST, art_to_tsc_offset);
1001
1002 /* Make this sticky over multiple CPU init calls */
1003 setup_force_cpu_cap(X86_FEATURE_ART);
1004}
1005
1006
1007/* clocksource code */
1008
1009static void tsc_resume(struct clocksource *cs)
1010{
1011 tsc_verify_tsc_adjust(true);
1012}
1013
1014/*
1015 * We used to compare the TSC to the cycle_last value in the clocksource
1016 * structure to avoid a nasty time-warp. This can be observed in a
1017 * very small window right after one CPU updated cycle_last under
1018 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
1019 * is smaller than the cycle_last reference value due to a TSC which
1020 * is slighty behind. This delta is nowhere else observable, but in
1021 * that case it results in a forward time jump in the range of hours
1022 * due to the unsigned delta calculation of the time keeping core
1023 * code, which is necessary to support wrapping clocksources like pm
1024 * timer.
1025 *
1026 * This sanity check is now done in the core timekeeping code.
1027 * checking the result of read_tsc() - cycle_last for being negative.
1028 * That works because CLOCKSOURCE_MASK(64) does not mask out any bit.
1029 */
1030static u64 read_tsc(struct clocksource *cs)
1031{
1032 return (u64)rdtsc_ordered();
1033}
1034
1035static void tsc_cs_mark_unstable(struct clocksource *cs)
1036{
1037 if (tsc_unstable)
1038 return;
1039
1040 tsc_unstable = 1;
1041 if (using_native_sched_clock())
1042 clear_sched_clock_stable();
1043 disable_sched_clock_irqtime();
1044 pr_info("Marking TSC unstable due to clocksource watchdog\n");
1045}
1046
1047static void tsc_cs_tick_stable(struct clocksource *cs)
1048{
1049 if (tsc_unstable)
1050 return;
1051
1052 if (using_native_sched_clock())
1053 sched_clock_tick_stable();
1054}
1055
1056/*
1057 * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc()
1058 */
1059static struct clocksource clocksource_tsc_early = {
1060 .name = "tsc-early",
1061 .rating = 299,
1062 .read = read_tsc,
1063 .mask = CLOCKSOURCE_MASK(64),
1064 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
1065 CLOCK_SOURCE_MUST_VERIFY,
1066 .archdata = { .vclock_mode = VCLOCK_TSC },
1067 .resume = tsc_resume,
1068 .mark_unstable = tsc_cs_mark_unstable,
1069 .tick_stable = tsc_cs_tick_stable,
1070 .list = LIST_HEAD_INIT(clocksource_tsc_early.list),
1071};
1072
1073/*
1074 * Must mark VALID_FOR_HRES early such that when we unregister tsc_early
1075 * this one will immediately take over. We will only register if TSC has
1076 * been found good.
1077 */
1078static struct clocksource clocksource_tsc = {
1079 .name = "tsc",
1080 .rating = 300,
1081 .read = read_tsc,
1082 .mask = CLOCKSOURCE_MASK(64),
1083 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
1084 CLOCK_SOURCE_VALID_FOR_HRES |
1085 CLOCK_SOURCE_MUST_VERIFY,
1086 .archdata = { .vclock_mode = VCLOCK_TSC },
1087 .resume = tsc_resume,
1088 .mark_unstable = tsc_cs_mark_unstable,
1089 .tick_stable = tsc_cs_tick_stable,
1090 .list = LIST_HEAD_INIT(clocksource_tsc.list),
1091};
1092
1093void mark_tsc_unstable(char *reason)
1094{
1095 if (tsc_unstable)
1096 return;
1097
1098 tsc_unstable = 1;
1099 if (using_native_sched_clock())
1100 clear_sched_clock_stable();
1101 disable_sched_clock_irqtime();
1102 pr_info("Marking TSC unstable due to %s\n", reason);
1103
1104 clocksource_mark_unstable(&clocksource_tsc_early);
1105 clocksource_mark_unstable(&clocksource_tsc);
1106}
1107
1108EXPORT_SYMBOL_GPL(mark_tsc_unstable);
1109
1110static void __init check_system_tsc_reliable(void)
1111{
1112#if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
1113 if (is_geode_lx()) {
1114 /* RTSC counts during suspend */
1115#define RTSC_SUSP 0x100
1116 unsigned long res_low, res_high;
1117
1118 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
1119 /* Geode_LX - the OLPC CPU has a very reliable TSC */
1120 if (res_low & RTSC_SUSP)
1121 tsc_clocksource_reliable = 1;
1122 }
1123#endif
1124 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
1125 tsc_clocksource_reliable = 1;
1126}
1127
1128/*
1129 * Make an educated guess if the TSC is trustworthy and synchronized
1130 * over all CPUs.
1131 */
1132int unsynchronized_tsc(void)
1133{
1134 if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable)
1135 return 1;
1136
1137#ifdef CONFIG_SMP
1138 if (apic_is_clustered_box())
1139 return 1;
1140#endif
1141
1142 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1143 return 0;
1144
1145 if (tsc_clocksource_reliable)
1146 return 0;
1147 /*
1148 * Intel systems are normally all synchronized.
1149 * Exceptions must mark TSC as unstable:
1150 */
1151 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1152 /* assume multi socket systems are not synchronized: */
1153 if (num_possible_cpus() > 1)
1154 return 1;
1155 }
1156
1157 return 0;
1158}
1159
1160/*
1161 * Convert ART to TSC given numerator/denominator found in detect_art()
1162 */
1163struct system_counterval_t convert_art_to_tsc(u64 art)
1164{
1165 u64 tmp, res, rem;
1166
1167 rem = do_div(art, art_to_tsc_denominator);
1168
1169 res = art * art_to_tsc_numerator;
1170 tmp = rem * art_to_tsc_numerator;
1171
1172 do_div(tmp, art_to_tsc_denominator);
1173 res += tmp + art_to_tsc_offset;
1174
1175 return (struct system_counterval_t) {.cs = art_related_clocksource,
1176 .cycles = res};
1177}
1178EXPORT_SYMBOL(convert_art_to_tsc);
1179
1180/**
1181 * convert_art_ns_to_tsc() - Convert ART in nanoseconds to TSC.
1182 * @art_ns: ART (Always Running Timer) in unit of nanoseconds
1183 *
1184 * PTM requires all timestamps to be in units of nanoseconds. When user
1185 * software requests a cross-timestamp, this function converts system timestamp
1186 * to TSC.
1187 *
1188 * This is valid when CPU feature flag X86_FEATURE_TSC_KNOWN_FREQ is set
1189 * indicating the tsc_khz is derived from CPUID[15H]. Drivers should check
1190 * that this flag is set before conversion to TSC is attempted.
1191 *
1192 * Return:
1193 * struct system_counterval_t - system counter value with the pointer to the
1194 * corresponding clocksource
1195 * @cycles: System counter value
1196 * @cs: Clocksource corresponding to system counter value. Used
1197 * by timekeeping code to verify comparibility of two cycle
1198 * values.
1199 */
1200
1201struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns)
1202{
1203 u64 tmp, res, rem;
1204
1205 rem = do_div(art_ns, USEC_PER_SEC);
1206
1207 res = art_ns * tsc_khz;
1208 tmp = rem * tsc_khz;
1209
1210 do_div(tmp, USEC_PER_SEC);
1211 res += tmp;
1212
1213 return (struct system_counterval_t) { .cs = art_related_clocksource,
1214 .cycles = res};
1215}
1216EXPORT_SYMBOL(convert_art_ns_to_tsc);
1217
1218
1219static void tsc_refine_calibration_work(struct work_struct *work);
1220static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
1221/**
1222 * tsc_refine_calibration_work - Further refine tsc freq calibration
1223 * @work - ignored.
1224 *
1225 * This functions uses delayed work over a period of a
1226 * second to further refine the TSC freq value. Since this is
1227 * timer based, instead of loop based, we don't block the boot
1228 * process while this longer calibration is done.
1229 *
1230 * If there are any calibration anomalies (too many SMIs, etc),
1231 * or the refined calibration is off by 1% of the fast early
1232 * calibration, we throw out the new calibration and use the
1233 * early calibration.
1234 */
1235static void tsc_refine_calibration_work(struct work_struct *work)
1236{
1237 static u64 tsc_start = -1, ref_start;
1238 static int hpet;
1239 u64 tsc_stop, ref_stop, delta;
1240 unsigned long freq;
1241 int cpu;
1242
1243 /* Don't bother refining TSC on unstable systems */
1244 if (tsc_unstable)
1245 goto unreg;
1246
1247 /*
1248 * Since the work is started early in boot, we may be
1249 * delayed the first time we expire. So set the workqueue
1250 * again once we know timers are working.
1251 */
1252 if (tsc_start == -1) {
1253 /*
1254 * Only set hpet once, to avoid mixing hardware
1255 * if the hpet becomes enabled later.
1256 */
1257 hpet = is_hpet_enabled();
1258 schedule_delayed_work(&tsc_irqwork, HZ);
1259 tsc_start = tsc_read_refs(&ref_start, hpet);
1260 return;
1261 }
1262
1263 tsc_stop = tsc_read_refs(&ref_stop, hpet);
1264
1265 /* hpet or pmtimer available ? */
1266 if (ref_start == ref_stop)
1267 goto out;
1268
1269 /* Check, whether the sampling was disturbed by an SMI */
1270 if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
1271 goto out;
1272
1273 delta = tsc_stop - tsc_start;
1274 delta *= 1000000LL;
1275 if (hpet)
1276 freq = calc_hpet_ref(delta, ref_start, ref_stop);
1277 else
1278 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
1279
1280 /* Make sure we're within 1% */
1281 if (abs(tsc_khz - freq) > tsc_khz/100)
1282 goto out;
1283
1284 tsc_khz = freq;
1285 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
1286 (unsigned long)tsc_khz / 1000,
1287 (unsigned long)tsc_khz % 1000);
1288
1289 /* Inform the TSC deadline clockevent devices about the recalibration */
1290 lapic_update_tsc_freq();
1291
1292 /* Update the sched_clock() rate to match the clocksource one */
1293 for_each_possible_cpu(cpu)
1294 set_cyc2ns_scale(tsc_khz, cpu, tsc_stop);
1295
1296out:
1297 if (tsc_unstable)
1298 goto unreg;
1299
1300 if (boot_cpu_has(X86_FEATURE_ART))
1301 art_related_clocksource = &clocksource_tsc;
1302 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1303unreg:
1304 clocksource_unregister(&clocksource_tsc_early);
1305}
1306
1307
1308static int __init init_tsc_clocksource(void)
1309{
1310 if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_disabled > 0 || !tsc_khz)
1311 return 0;
1312
1313 if (tsc_unstable)
1314 goto unreg;
1315
1316 if (tsc_clocksource_reliable)
1317 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
1318
1319 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
1320 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1321
1322 /*
1323 * When TSC frequency is known (retrieved via MSR or CPUID), we skip
1324 * the refined calibration and directly register it as a clocksource.
1325 */
1326 if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) {
1327 if (boot_cpu_has(X86_FEATURE_ART))
1328 art_related_clocksource = &clocksource_tsc;
1329 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1330unreg:
1331 clocksource_unregister(&clocksource_tsc_early);
1332 return 0;
1333 }
1334
1335 schedule_delayed_work(&tsc_irqwork, 0);
1336 return 0;
1337}
1338/*
1339 * We use device_initcall here, to ensure we run after the hpet
1340 * is fully initialized, which may occur at fs_initcall time.
1341 */
1342device_initcall(init_tsc_clocksource);
1343
1344void __init tsc_early_delay_calibrate(void)
1345{
1346 unsigned long lpj;
1347
1348 if (!boot_cpu_has(X86_FEATURE_TSC))
1349 return;
1350
1351 cpu_khz = x86_platform.calibrate_cpu();
1352 tsc_khz = x86_platform.calibrate_tsc();
1353
1354 tsc_khz = tsc_khz ? : cpu_khz;
1355 if (!tsc_khz)
1356 return;
1357
1358 lpj = tsc_khz * 1000;
1359 do_div(lpj, HZ);
1360 loops_per_jiffy = lpj;
1361}
1362
1363void __init tsc_init(void)
1364{
1365 u64 lpj, cyc;
1366 int cpu;
1367
1368 if (!boot_cpu_has(X86_FEATURE_TSC)) {
1369 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1370 return;
1371 }
1372
1373 cpu_khz = x86_platform.calibrate_cpu();
1374 tsc_khz = x86_platform.calibrate_tsc();
1375
1376 /*
1377 * Trust non-zero tsc_khz as authorative,
1378 * and use it to sanity check cpu_khz,
1379 * which will be off if system timer is off.
1380 */
1381 if (tsc_khz == 0)
1382 tsc_khz = cpu_khz;
1383 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
1384 cpu_khz = tsc_khz;
1385
1386 if (!tsc_khz) {
1387 mark_tsc_unstable("could not calculate TSC khz");
1388 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1389 return;
1390 }
1391
1392 pr_info("Detected %lu.%03lu MHz processor\n",
1393 (unsigned long)cpu_khz / 1000,
1394 (unsigned long)cpu_khz % 1000);
1395
1396 if (cpu_khz != tsc_khz) {
1397 pr_info("Detected %lu.%03lu MHz TSC",
1398 (unsigned long)tsc_khz / 1000,
1399 (unsigned long)tsc_khz % 1000);
1400 }
1401
1402 /* Sanitize TSC ADJUST before cyc2ns gets initialized */
1403 tsc_store_and_check_tsc_adjust(true);
1404
1405 /*
1406 * Secondary CPUs do not run through tsc_init(), so set up
1407 * all the scale factors for all CPUs, assuming the same
1408 * speed as the bootup CPU. (cpufreq notifiers will fix this
1409 * up if their speed diverges)
1410 */
1411 cyc = rdtsc();
1412 for_each_possible_cpu(cpu) {
1413 cyc2ns_init(cpu);
1414 set_cyc2ns_scale(tsc_khz, cpu, cyc);
1415 }
1416
1417 if (tsc_disabled > 0)
1418 return;
1419
1420 /* now allow native_sched_clock() to use rdtsc */
1421
1422 tsc_disabled = 0;
1423 static_branch_enable(&__use_tsc);
1424
1425 if (!no_sched_irq_time)
1426 enable_sched_clock_irqtime();
1427
1428 lpj = ((u64)tsc_khz * 1000);
1429 do_div(lpj, HZ);
1430 lpj_fine = lpj;
1431
1432 use_tsc_delay();
1433
1434 check_system_tsc_reliable();
1435
1436 if (unsynchronized_tsc()) {
1437 mark_tsc_unstable("TSCs unsynchronized");
1438 return;
1439 }
1440
1441 clocksource_register_khz(&clocksource_tsc_early, tsc_khz);
1442 detect_art();
1443}
1444
1445#ifdef CONFIG_SMP
1446/*
1447 * If we have a constant TSC and are using the TSC for the delay loop,
1448 * we can skip clock calibration if another cpu in the same socket has already
1449 * been calibrated. This assumes that CONSTANT_TSC applies to all
1450 * cpus in the socket - this should be a safe assumption.
1451 */
1452unsigned long calibrate_delay_is_known(void)
1453{
1454 int sibling, cpu = smp_processor_id();
1455 int constant_tsc = cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC);
1456 const struct cpumask *mask = topology_core_cpumask(cpu);
1457
1458 if (tsc_disabled || !constant_tsc || !mask)
1459 return 0;
1460
1461 sibling = cpumask_any_but(mask, cpu);
1462 if (sibling < nr_cpu_ids)
1463 return cpu_data(sibling).loops_per_jiffy;
1464 return 0;
1465}
1466#endif
1#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
2
3#include <linux/kernel.h>
4#include <linux/sched.h>
5#include <linux/init.h>
6#include <linux/export.h>
7#include <linux/timer.h>
8#include <linux/acpi_pmtmr.h>
9#include <linux/cpufreq.h>
10#include <linux/delay.h>
11#include <linux/clocksource.h>
12#include <linux/percpu.h>
13#include <linux/timex.h>
14#include <linux/static_key.h>
15
16#include <asm/hpet.h>
17#include <asm/timer.h>
18#include <asm/vgtod.h>
19#include <asm/time.h>
20#include <asm/delay.h>
21#include <asm/hypervisor.h>
22#include <asm/nmi.h>
23#include <asm/x86_init.h>
24#include <asm/geode.h>
25#include <asm/apic.h>
26#include <asm/intel-family.h>
27
28unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
29EXPORT_SYMBOL(cpu_khz);
30
31unsigned int __read_mostly tsc_khz;
32EXPORT_SYMBOL(tsc_khz);
33
34/*
35 * TSC can be unstable due to cpufreq or due to unsynced TSCs
36 */
37static int __read_mostly tsc_unstable;
38
39/* native_sched_clock() is called before tsc_init(), so
40 we must start with the TSC soft disabled to prevent
41 erroneous rdtsc usage on !boot_cpu_has(X86_FEATURE_TSC) processors */
42static int __read_mostly tsc_disabled = -1;
43
44static DEFINE_STATIC_KEY_FALSE(__use_tsc);
45
46int tsc_clocksource_reliable;
47
48static u32 art_to_tsc_numerator;
49static u32 art_to_tsc_denominator;
50static u64 art_to_tsc_offset;
51struct clocksource *art_related_clocksource;
52
53/*
54 * Use a ring-buffer like data structure, where a writer advances the head by
55 * writing a new data entry and a reader advances the tail when it observes a
56 * new entry.
57 *
58 * Writers are made to wait on readers until there's space to write a new
59 * entry.
60 *
61 * This means that we can always use an {offset, mul} pair to compute a ns
62 * value that is 'roughly' in the right direction, even if we're writing a new
63 * {offset, mul} pair during the clock read.
64 *
65 * The down-side is that we can no longer guarantee strict monotonicity anymore
66 * (assuming the TSC was that to begin with), because while we compute the
67 * intersection point of the two clock slopes and make sure the time is
68 * continuous at the point of switching; we can no longer guarantee a reader is
69 * strictly before or after the switch point.
70 *
71 * It does mean a reader no longer needs to disable IRQs in order to avoid
72 * CPU-Freq updates messing with his times, and similarly an NMI reader will
73 * no longer run the risk of hitting half-written state.
74 */
75
76struct cyc2ns {
77 struct cyc2ns_data data[2]; /* 0 + 2*24 = 48 */
78 struct cyc2ns_data *head; /* 48 + 8 = 56 */
79 struct cyc2ns_data *tail; /* 56 + 8 = 64 */
80}; /* exactly fits one cacheline */
81
82static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
83
84struct cyc2ns_data *cyc2ns_read_begin(void)
85{
86 struct cyc2ns_data *head;
87
88 preempt_disable();
89
90 head = this_cpu_read(cyc2ns.head);
91 /*
92 * Ensure we observe the entry when we observe the pointer to it.
93 * matches the wmb from cyc2ns_write_end().
94 */
95 smp_read_barrier_depends();
96 head->__count++;
97 barrier();
98
99 return head;
100}
101
102void cyc2ns_read_end(struct cyc2ns_data *head)
103{
104 barrier();
105 /*
106 * If we're the outer most nested read; update the tail pointer
107 * when we're done. This notifies possible pending writers
108 * that we've observed the head pointer and that the other
109 * entry is now free.
110 */
111 if (!--head->__count) {
112 /*
113 * x86-TSO does not reorder writes with older reads;
114 * therefore once this write becomes visible to another
115 * cpu, we must be finished reading the cyc2ns_data.
116 *
117 * matches with cyc2ns_write_begin().
118 */
119 this_cpu_write(cyc2ns.tail, head);
120 }
121 preempt_enable();
122}
123
124/*
125 * Begin writing a new @data entry for @cpu.
126 *
127 * Assumes some sort of write side lock; currently 'provided' by the assumption
128 * that cpufreq will call its notifiers sequentially.
129 */
130static struct cyc2ns_data *cyc2ns_write_begin(int cpu)
131{
132 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
133 struct cyc2ns_data *data = c2n->data;
134
135 if (data == c2n->head)
136 data++;
137
138 /* XXX send an IPI to @cpu in order to guarantee a read? */
139
140 /*
141 * When we observe the tail write from cyc2ns_read_end(),
142 * the cpu must be done with that entry and its safe
143 * to start writing to it.
144 */
145 while (c2n->tail == data)
146 cpu_relax();
147
148 return data;
149}
150
151static void cyc2ns_write_end(int cpu, struct cyc2ns_data *data)
152{
153 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
154
155 /*
156 * Ensure the @data writes are visible before we publish the
157 * entry. Matches the data-depencency in cyc2ns_read_begin().
158 */
159 smp_wmb();
160
161 ACCESS_ONCE(c2n->head) = data;
162}
163
164/*
165 * Accelerators for sched_clock()
166 * convert from cycles(64bits) => nanoseconds (64bits)
167 * basic equation:
168 * ns = cycles / (freq / ns_per_sec)
169 * ns = cycles * (ns_per_sec / freq)
170 * ns = cycles * (10^9 / (cpu_khz * 10^3))
171 * ns = cycles * (10^6 / cpu_khz)
172 *
173 * Then we use scaling math (suggested by george@mvista.com) to get:
174 * ns = cycles * (10^6 * SC / cpu_khz) / SC
175 * ns = cycles * cyc2ns_scale / SC
176 *
177 * And since SC is a constant power of two, we can convert the div
178 * into a shift. The larger SC is, the more accurate the conversion, but
179 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication
180 * (64-bit result) can be used.
181 *
182 * We can use khz divisor instead of mhz to keep a better precision.
183 * (mathieu.desnoyers@polymtl.ca)
184 *
185 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
186 */
187
188static void cyc2ns_data_init(struct cyc2ns_data *data)
189{
190 data->cyc2ns_mul = 0;
191 data->cyc2ns_shift = 0;
192 data->cyc2ns_offset = 0;
193 data->__count = 0;
194}
195
196static void cyc2ns_init(int cpu)
197{
198 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
199
200 cyc2ns_data_init(&c2n->data[0]);
201 cyc2ns_data_init(&c2n->data[1]);
202
203 c2n->head = c2n->data;
204 c2n->tail = c2n->data;
205}
206
207static inline unsigned long long cycles_2_ns(unsigned long long cyc)
208{
209 struct cyc2ns_data *data, *tail;
210 unsigned long long ns;
211
212 /*
213 * See cyc2ns_read_*() for details; replicated in order to avoid
214 * an extra few instructions that came with the abstraction.
215 * Notable, it allows us to only do the __count and tail update
216 * dance when its actually needed.
217 */
218
219 preempt_disable_notrace();
220 data = this_cpu_read(cyc2ns.head);
221 tail = this_cpu_read(cyc2ns.tail);
222
223 if (likely(data == tail)) {
224 ns = data->cyc2ns_offset;
225 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
226 } else {
227 data->__count++;
228
229 barrier();
230
231 ns = data->cyc2ns_offset;
232 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
233
234 barrier();
235
236 if (!--data->__count)
237 this_cpu_write(cyc2ns.tail, data);
238 }
239 preempt_enable_notrace();
240
241 return ns;
242}
243
244static void set_cyc2ns_scale(unsigned long khz, int cpu)
245{
246 unsigned long long tsc_now, ns_now;
247 struct cyc2ns_data *data;
248 unsigned long flags;
249
250 local_irq_save(flags);
251 sched_clock_idle_sleep_event();
252
253 if (!khz)
254 goto done;
255
256 data = cyc2ns_write_begin(cpu);
257
258 tsc_now = rdtsc();
259 ns_now = cycles_2_ns(tsc_now);
260
261 /*
262 * Compute a new multiplier as per the above comment and ensure our
263 * time function is continuous; see the comment near struct
264 * cyc2ns_data.
265 */
266 clocks_calc_mult_shift(&data->cyc2ns_mul, &data->cyc2ns_shift, khz,
267 NSEC_PER_MSEC, 0);
268
269 /*
270 * cyc2ns_shift is exported via arch_perf_update_userpage() where it is
271 * not expected to be greater than 31 due to the original published
272 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit
273 * value) - refer perf_event_mmap_page documentation in perf_event.h.
274 */
275 if (data->cyc2ns_shift == 32) {
276 data->cyc2ns_shift = 31;
277 data->cyc2ns_mul >>= 1;
278 }
279
280 data->cyc2ns_offset = ns_now -
281 mul_u64_u32_shr(tsc_now, data->cyc2ns_mul, data->cyc2ns_shift);
282
283 cyc2ns_write_end(cpu, data);
284
285done:
286 sched_clock_idle_wakeup_event(0);
287 local_irq_restore(flags);
288}
289/*
290 * Scheduler clock - returns current time in nanosec units.
291 */
292u64 native_sched_clock(void)
293{
294 if (static_branch_likely(&__use_tsc)) {
295 u64 tsc_now = rdtsc();
296
297 /* return the value in ns */
298 return cycles_2_ns(tsc_now);
299 }
300
301 /*
302 * Fall back to jiffies if there's no TSC available:
303 * ( But note that we still use it if the TSC is marked
304 * unstable. We do this because unlike Time Of Day,
305 * the scheduler clock tolerates small errors and it's
306 * very important for it to be as fast as the platform
307 * can achieve it. )
308 */
309
310 /* No locking but a rare wrong value is not a big deal: */
311 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
312}
313
314/*
315 * Generate a sched_clock if you already have a TSC value.
316 */
317u64 native_sched_clock_from_tsc(u64 tsc)
318{
319 return cycles_2_ns(tsc);
320}
321
322/* We need to define a real function for sched_clock, to override the
323 weak default version */
324#ifdef CONFIG_PARAVIRT
325unsigned long long sched_clock(void)
326{
327 return paravirt_sched_clock();
328}
329#else
330unsigned long long
331sched_clock(void) __attribute__((alias("native_sched_clock")));
332#endif
333
334int check_tsc_unstable(void)
335{
336 return tsc_unstable;
337}
338EXPORT_SYMBOL_GPL(check_tsc_unstable);
339
340#ifdef CONFIG_X86_TSC
341int __init notsc_setup(char *str)
342{
343 pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
344 tsc_disabled = 1;
345 return 1;
346}
347#else
348/*
349 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
350 * in cpu/common.c
351 */
352int __init notsc_setup(char *str)
353{
354 setup_clear_cpu_cap(X86_FEATURE_TSC);
355 return 1;
356}
357#endif
358
359__setup("notsc", notsc_setup);
360
361static int no_sched_irq_time;
362
363static int __init tsc_setup(char *str)
364{
365 if (!strcmp(str, "reliable"))
366 tsc_clocksource_reliable = 1;
367 if (!strncmp(str, "noirqtime", 9))
368 no_sched_irq_time = 1;
369 return 1;
370}
371
372__setup("tsc=", tsc_setup);
373
374#define MAX_RETRIES 5
375#define SMI_TRESHOLD 50000
376
377/*
378 * Read TSC and the reference counters. Take care of SMI disturbance
379 */
380static u64 tsc_read_refs(u64 *p, int hpet)
381{
382 u64 t1, t2;
383 int i;
384
385 for (i = 0; i < MAX_RETRIES; i++) {
386 t1 = get_cycles();
387 if (hpet)
388 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
389 else
390 *p = acpi_pm_read_early();
391 t2 = get_cycles();
392 if ((t2 - t1) < SMI_TRESHOLD)
393 return t2;
394 }
395 return ULLONG_MAX;
396}
397
398/*
399 * Calculate the TSC frequency from HPET reference
400 */
401static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
402{
403 u64 tmp;
404
405 if (hpet2 < hpet1)
406 hpet2 += 0x100000000ULL;
407 hpet2 -= hpet1;
408 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
409 do_div(tmp, 1000000);
410 do_div(deltatsc, tmp);
411
412 return (unsigned long) deltatsc;
413}
414
415/*
416 * Calculate the TSC frequency from PMTimer reference
417 */
418static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
419{
420 u64 tmp;
421
422 if (!pm1 && !pm2)
423 return ULONG_MAX;
424
425 if (pm2 < pm1)
426 pm2 += (u64)ACPI_PM_OVRRUN;
427 pm2 -= pm1;
428 tmp = pm2 * 1000000000LL;
429 do_div(tmp, PMTMR_TICKS_PER_SEC);
430 do_div(deltatsc, tmp);
431
432 return (unsigned long) deltatsc;
433}
434
435#define CAL_MS 10
436#define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
437#define CAL_PIT_LOOPS 1000
438
439#define CAL2_MS 50
440#define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
441#define CAL2_PIT_LOOPS 5000
442
443
444/*
445 * Try to calibrate the TSC against the Programmable
446 * Interrupt Timer and return the frequency of the TSC
447 * in kHz.
448 *
449 * Return ULONG_MAX on failure to calibrate.
450 */
451static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
452{
453 u64 tsc, t1, t2, delta;
454 unsigned long tscmin, tscmax;
455 int pitcnt;
456
457 /* Set the Gate high, disable speaker */
458 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
459
460 /*
461 * Setup CTC channel 2* for mode 0, (interrupt on terminal
462 * count mode), binary count. Set the latch register to 50ms
463 * (LSB then MSB) to begin countdown.
464 */
465 outb(0xb0, 0x43);
466 outb(latch & 0xff, 0x42);
467 outb(latch >> 8, 0x42);
468
469 tsc = t1 = t2 = get_cycles();
470
471 pitcnt = 0;
472 tscmax = 0;
473 tscmin = ULONG_MAX;
474 while ((inb(0x61) & 0x20) == 0) {
475 t2 = get_cycles();
476 delta = t2 - tsc;
477 tsc = t2;
478 if ((unsigned long) delta < tscmin)
479 tscmin = (unsigned int) delta;
480 if ((unsigned long) delta > tscmax)
481 tscmax = (unsigned int) delta;
482 pitcnt++;
483 }
484
485 /*
486 * Sanity checks:
487 *
488 * If we were not able to read the PIT more than loopmin
489 * times, then we have been hit by a massive SMI
490 *
491 * If the maximum is 10 times larger than the minimum,
492 * then we got hit by an SMI as well.
493 */
494 if (pitcnt < loopmin || tscmax > 10 * tscmin)
495 return ULONG_MAX;
496
497 /* Calculate the PIT value */
498 delta = t2 - t1;
499 do_div(delta, ms);
500 return delta;
501}
502
503/*
504 * This reads the current MSB of the PIT counter, and
505 * checks if we are running on sufficiently fast and
506 * non-virtualized hardware.
507 *
508 * Our expectations are:
509 *
510 * - the PIT is running at roughly 1.19MHz
511 *
512 * - each IO is going to take about 1us on real hardware,
513 * but we allow it to be much faster (by a factor of 10) or
514 * _slightly_ slower (ie we allow up to a 2us read+counter
515 * update - anything else implies a unacceptably slow CPU
516 * or PIT for the fast calibration to work.
517 *
518 * - with 256 PIT ticks to read the value, we have 214us to
519 * see the same MSB (and overhead like doing a single TSC
520 * read per MSB value etc).
521 *
522 * - We're doing 2 reads per loop (LSB, MSB), and we expect
523 * them each to take about a microsecond on real hardware.
524 * So we expect a count value of around 100. But we'll be
525 * generous, and accept anything over 50.
526 *
527 * - if the PIT is stuck, and we see *many* more reads, we
528 * return early (and the next caller of pit_expect_msb()
529 * then consider it a failure when they don't see the
530 * next expected value).
531 *
532 * These expectations mean that we know that we have seen the
533 * transition from one expected value to another with a fairly
534 * high accuracy, and we didn't miss any events. We can thus
535 * use the TSC value at the transitions to calculate a pretty
536 * good value for the TSC frequencty.
537 */
538static inline int pit_verify_msb(unsigned char val)
539{
540 /* Ignore LSB */
541 inb(0x42);
542 return inb(0x42) == val;
543}
544
545static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
546{
547 int count;
548 u64 tsc = 0, prev_tsc = 0;
549
550 for (count = 0; count < 50000; count++) {
551 if (!pit_verify_msb(val))
552 break;
553 prev_tsc = tsc;
554 tsc = get_cycles();
555 }
556 *deltap = get_cycles() - prev_tsc;
557 *tscp = tsc;
558
559 /*
560 * We require _some_ success, but the quality control
561 * will be based on the error terms on the TSC values.
562 */
563 return count > 5;
564}
565
566/*
567 * How many MSB values do we want to see? We aim for
568 * a maximum error rate of 500ppm (in practice the
569 * real error is much smaller), but refuse to spend
570 * more than 50ms on it.
571 */
572#define MAX_QUICK_PIT_MS 50
573#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
574
575static unsigned long quick_pit_calibrate(void)
576{
577 int i;
578 u64 tsc, delta;
579 unsigned long d1, d2;
580
581 /* Set the Gate high, disable speaker */
582 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
583
584 /*
585 * Counter 2, mode 0 (one-shot), binary count
586 *
587 * NOTE! Mode 2 decrements by two (and then the
588 * output is flipped each time, giving the same
589 * final output frequency as a decrement-by-one),
590 * so mode 0 is much better when looking at the
591 * individual counts.
592 */
593 outb(0xb0, 0x43);
594
595 /* Start at 0xffff */
596 outb(0xff, 0x42);
597 outb(0xff, 0x42);
598
599 /*
600 * The PIT starts counting at the next edge, so we
601 * need to delay for a microsecond. The easiest way
602 * to do that is to just read back the 16-bit counter
603 * once from the PIT.
604 */
605 pit_verify_msb(0);
606
607 if (pit_expect_msb(0xff, &tsc, &d1)) {
608 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
609 if (!pit_expect_msb(0xff-i, &delta, &d2))
610 break;
611
612 delta -= tsc;
613
614 /*
615 * Extrapolate the error and fail fast if the error will
616 * never be below 500 ppm.
617 */
618 if (i == 1 &&
619 d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11)
620 return 0;
621
622 /*
623 * Iterate until the error is less than 500 ppm
624 */
625 if (d1+d2 >= delta >> 11)
626 continue;
627
628 /*
629 * Check the PIT one more time to verify that
630 * all TSC reads were stable wrt the PIT.
631 *
632 * This also guarantees serialization of the
633 * last cycle read ('d2') in pit_expect_msb.
634 */
635 if (!pit_verify_msb(0xfe - i))
636 break;
637 goto success;
638 }
639 }
640 pr_info("Fast TSC calibration failed\n");
641 return 0;
642
643success:
644 /*
645 * Ok, if we get here, then we've seen the
646 * MSB of the PIT decrement 'i' times, and the
647 * error has shrunk to less than 500 ppm.
648 *
649 * As a result, we can depend on there not being
650 * any odd delays anywhere, and the TSC reads are
651 * reliable (within the error).
652 *
653 * kHz = ticks / time-in-seconds / 1000;
654 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
655 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
656 */
657 delta *= PIT_TICK_RATE;
658 do_div(delta, i*256*1000);
659 pr_info("Fast TSC calibration using PIT\n");
660 return delta;
661}
662
663/**
664 * native_calibrate_tsc
665 * Determine TSC frequency via CPUID, else return 0.
666 */
667unsigned long native_calibrate_tsc(void)
668{
669 unsigned int eax_denominator, ebx_numerator, ecx_hz, edx;
670 unsigned int crystal_khz;
671
672 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
673 return 0;
674
675 if (boot_cpu_data.cpuid_level < 0x15)
676 return 0;
677
678 eax_denominator = ebx_numerator = ecx_hz = edx = 0;
679
680 /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
681 cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx);
682
683 if (ebx_numerator == 0 || eax_denominator == 0)
684 return 0;
685
686 crystal_khz = ecx_hz / 1000;
687
688 if (crystal_khz == 0) {
689 switch (boot_cpu_data.x86_model) {
690 case INTEL_FAM6_SKYLAKE_MOBILE:
691 case INTEL_FAM6_SKYLAKE_DESKTOP:
692 case INTEL_FAM6_KABYLAKE_MOBILE:
693 case INTEL_FAM6_KABYLAKE_DESKTOP:
694 crystal_khz = 24000; /* 24.0 MHz */
695 break;
696 case INTEL_FAM6_SKYLAKE_X:
697 case INTEL_FAM6_ATOM_DENVERTON:
698 crystal_khz = 25000; /* 25.0 MHz */
699 break;
700 case INTEL_FAM6_ATOM_GOLDMONT:
701 crystal_khz = 19200; /* 19.2 MHz */
702 break;
703 }
704 }
705
706 /*
707 * TSC frequency determined by CPUID is a "hardware reported"
708 * frequency and is the most accurate one so far we have. This
709 * is considered a known frequency.
710 */
711 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
712
713 /*
714 * For Atom SoCs TSC is the only reliable clocksource.
715 * Mark TSC reliable so no watchdog on it.
716 */
717 if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
718 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
719
720 return crystal_khz * ebx_numerator / eax_denominator;
721}
722
723static unsigned long cpu_khz_from_cpuid(void)
724{
725 unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx;
726
727 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
728 return 0;
729
730 if (boot_cpu_data.cpuid_level < 0x16)
731 return 0;
732
733 eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0;
734
735 cpuid(0x16, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx);
736
737 return eax_base_mhz * 1000;
738}
739
740/**
741 * native_calibrate_cpu - calibrate the cpu on boot
742 */
743unsigned long native_calibrate_cpu(void)
744{
745 u64 tsc1, tsc2, delta, ref1, ref2;
746 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
747 unsigned long flags, latch, ms, fast_calibrate;
748 int hpet = is_hpet_enabled(), i, loopmin;
749
750 fast_calibrate = cpu_khz_from_cpuid();
751 if (fast_calibrate)
752 return fast_calibrate;
753
754 fast_calibrate = cpu_khz_from_msr();
755 if (fast_calibrate)
756 return fast_calibrate;
757
758 local_irq_save(flags);
759 fast_calibrate = quick_pit_calibrate();
760 local_irq_restore(flags);
761 if (fast_calibrate)
762 return fast_calibrate;
763
764 /*
765 * Run 5 calibration loops to get the lowest frequency value
766 * (the best estimate). We use two different calibration modes
767 * here:
768 *
769 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
770 * load a timeout of 50ms. We read the time right after we
771 * started the timer and wait until the PIT count down reaches
772 * zero. In each wait loop iteration we read the TSC and check
773 * the delta to the previous read. We keep track of the min
774 * and max values of that delta. The delta is mostly defined
775 * by the IO time of the PIT access, so we can detect when a
776 * SMI/SMM disturbance happened between the two reads. If the
777 * maximum time is significantly larger than the minimum time,
778 * then we discard the result and have another try.
779 *
780 * 2) Reference counter. If available we use the HPET or the
781 * PMTIMER as a reference to check the sanity of that value.
782 * We use separate TSC readouts and check inside of the
783 * reference read for a SMI/SMM disturbance. We dicard
784 * disturbed values here as well. We do that around the PIT
785 * calibration delay loop as we have to wait for a certain
786 * amount of time anyway.
787 */
788
789 /* Preset PIT loop values */
790 latch = CAL_LATCH;
791 ms = CAL_MS;
792 loopmin = CAL_PIT_LOOPS;
793
794 for (i = 0; i < 3; i++) {
795 unsigned long tsc_pit_khz;
796
797 /*
798 * Read the start value and the reference count of
799 * hpet/pmtimer when available. Then do the PIT
800 * calibration, which will take at least 50ms, and
801 * read the end value.
802 */
803 local_irq_save(flags);
804 tsc1 = tsc_read_refs(&ref1, hpet);
805 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
806 tsc2 = tsc_read_refs(&ref2, hpet);
807 local_irq_restore(flags);
808
809 /* Pick the lowest PIT TSC calibration so far */
810 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
811
812 /* hpet or pmtimer available ? */
813 if (ref1 == ref2)
814 continue;
815
816 /* Check, whether the sampling was disturbed by an SMI */
817 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
818 continue;
819
820 tsc2 = (tsc2 - tsc1) * 1000000LL;
821 if (hpet)
822 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
823 else
824 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
825
826 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
827
828 /* Check the reference deviation */
829 delta = ((u64) tsc_pit_min) * 100;
830 do_div(delta, tsc_ref_min);
831
832 /*
833 * If both calibration results are inside a 10% window
834 * then we can be sure, that the calibration
835 * succeeded. We break out of the loop right away. We
836 * use the reference value, as it is more precise.
837 */
838 if (delta >= 90 && delta <= 110) {
839 pr_info("PIT calibration matches %s. %d loops\n",
840 hpet ? "HPET" : "PMTIMER", i + 1);
841 return tsc_ref_min;
842 }
843
844 /*
845 * Check whether PIT failed more than once. This
846 * happens in virtualized environments. We need to
847 * give the virtual PC a slightly longer timeframe for
848 * the HPET/PMTIMER to make the result precise.
849 */
850 if (i == 1 && tsc_pit_min == ULONG_MAX) {
851 latch = CAL2_LATCH;
852 ms = CAL2_MS;
853 loopmin = CAL2_PIT_LOOPS;
854 }
855 }
856
857 /*
858 * Now check the results.
859 */
860 if (tsc_pit_min == ULONG_MAX) {
861 /* PIT gave no useful value */
862 pr_warn("Unable to calibrate against PIT\n");
863
864 /* We don't have an alternative source, disable TSC */
865 if (!hpet && !ref1 && !ref2) {
866 pr_notice("No reference (HPET/PMTIMER) available\n");
867 return 0;
868 }
869
870 /* The alternative source failed as well, disable TSC */
871 if (tsc_ref_min == ULONG_MAX) {
872 pr_warn("HPET/PMTIMER calibration failed\n");
873 return 0;
874 }
875
876 /* Use the alternative source */
877 pr_info("using %s reference calibration\n",
878 hpet ? "HPET" : "PMTIMER");
879
880 return tsc_ref_min;
881 }
882
883 /* We don't have an alternative source, use the PIT calibration value */
884 if (!hpet && !ref1 && !ref2) {
885 pr_info("Using PIT calibration value\n");
886 return tsc_pit_min;
887 }
888
889 /* The alternative source failed, use the PIT calibration value */
890 if (tsc_ref_min == ULONG_MAX) {
891 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
892 return tsc_pit_min;
893 }
894
895 /*
896 * The calibration values differ too much. In doubt, we use
897 * the PIT value as we know that there are PMTIMERs around
898 * running at double speed. At least we let the user know:
899 */
900 pr_warn("PIT calibration deviates from %s: %lu %lu\n",
901 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
902 pr_info("Using PIT calibration value\n");
903 return tsc_pit_min;
904}
905
906int recalibrate_cpu_khz(void)
907{
908#ifndef CONFIG_SMP
909 unsigned long cpu_khz_old = cpu_khz;
910
911 if (!boot_cpu_has(X86_FEATURE_TSC))
912 return -ENODEV;
913
914 cpu_khz = x86_platform.calibrate_cpu();
915 tsc_khz = x86_platform.calibrate_tsc();
916 if (tsc_khz == 0)
917 tsc_khz = cpu_khz;
918 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
919 cpu_khz = tsc_khz;
920 cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy,
921 cpu_khz_old, cpu_khz);
922
923 return 0;
924#else
925 return -ENODEV;
926#endif
927}
928
929EXPORT_SYMBOL(recalibrate_cpu_khz);
930
931
932static unsigned long long cyc2ns_suspend;
933
934void tsc_save_sched_clock_state(void)
935{
936 if (!sched_clock_stable())
937 return;
938
939 cyc2ns_suspend = sched_clock();
940}
941
942/*
943 * Even on processors with invariant TSC, TSC gets reset in some the
944 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
945 * arbitrary value (still sync'd across cpu's) during resume from such sleep
946 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
947 * that sched_clock() continues from the point where it was left off during
948 * suspend.
949 */
950void tsc_restore_sched_clock_state(void)
951{
952 unsigned long long offset;
953 unsigned long flags;
954 int cpu;
955
956 if (!sched_clock_stable())
957 return;
958
959 local_irq_save(flags);
960
961 /*
962 * We're coming out of suspend, there's no concurrency yet; don't
963 * bother being nice about the RCU stuff, just write to both
964 * data fields.
965 */
966
967 this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0);
968 this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0);
969
970 offset = cyc2ns_suspend - sched_clock();
971
972 for_each_possible_cpu(cpu) {
973 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset;
974 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset;
975 }
976
977 local_irq_restore(flags);
978}
979
980#ifdef CONFIG_CPU_FREQ
981
982/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
983 * changes.
984 *
985 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
986 * not that important because current Opteron setups do not support
987 * scaling on SMP anyroads.
988 *
989 * Should fix up last_tsc too. Currently gettimeofday in the
990 * first tick after the change will be slightly wrong.
991 */
992
993static unsigned int ref_freq;
994static unsigned long loops_per_jiffy_ref;
995static unsigned long tsc_khz_ref;
996
997static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
998 void *data)
999{
1000 struct cpufreq_freqs *freq = data;
1001 unsigned long *lpj;
1002
1003 lpj = &boot_cpu_data.loops_per_jiffy;
1004#ifdef CONFIG_SMP
1005 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
1006 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
1007#endif
1008
1009 if (!ref_freq) {
1010 ref_freq = freq->old;
1011 loops_per_jiffy_ref = *lpj;
1012 tsc_khz_ref = tsc_khz;
1013 }
1014 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
1015 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
1016 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
1017
1018 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
1019 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
1020 mark_tsc_unstable("cpufreq changes");
1021
1022 set_cyc2ns_scale(tsc_khz, freq->cpu);
1023 }
1024
1025 return 0;
1026}
1027
1028static struct notifier_block time_cpufreq_notifier_block = {
1029 .notifier_call = time_cpufreq_notifier
1030};
1031
1032static int __init cpufreq_register_tsc_scaling(void)
1033{
1034 if (!boot_cpu_has(X86_FEATURE_TSC))
1035 return 0;
1036 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1037 return 0;
1038 cpufreq_register_notifier(&time_cpufreq_notifier_block,
1039 CPUFREQ_TRANSITION_NOTIFIER);
1040 return 0;
1041}
1042
1043core_initcall(cpufreq_register_tsc_scaling);
1044
1045#endif /* CONFIG_CPU_FREQ */
1046
1047#define ART_CPUID_LEAF (0x15)
1048#define ART_MIN_DENOMINATOR (1)
1049
1050
1051/*
1052 * If ART is present detect the numerator:denominator to convert to TSC
1053 */
1054static void detect_art(void)
1055{
1056 unsigned int unused[2];
1057
1058 if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF)
1059 return;
1060
1061 /* Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required */
1062 if (boot_cpu_has(X86_FEATURE_HYPERVISOR) ||
1063 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) ||
1064 !boot_cpu_has(X86_FEATURE_TSC_ADJUST))
1065 return;
1066
1067 cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator,
1068 &art_to_tsc_numerator, unused, unused+1);
1069
1070 if (art_to_tsc_denominator < ART_MIN_DENOMINATOR)
1071 return;
1072
1073 rdmsrl(MSR_IA32_TSC_ADJUST, art_to_tsc_offset);
1074
1075 /* Make this sticky over multiple CPU init calls */
1076 setup_force_cpu_cap(X86_FEATURE_ART);
1077}
1078
1079
1080/* clocksource code */
1081
1082static struct clocksource clocksource_tsc;
1083
1084static void tsc_resume(struct clocksource *cs)
1085{
1086 tsc_verify_tsc_adjust(true);
1087}
1088
1089/*
1090 * We used to compare the TSC to the cycle_last value in the clocksource
1091 * structure to avoid a nasty time-warp. This can be observed in a
1092 * very small window right after one CPU updated cycle_last under
1093 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
1094 * is smaller than the cycle_last reference value due to a TSC which
1095 * is slighty behind. This delta is nowhere else observable, but in
1096 * that case it results in a forward time jump in the range of hours
1097 * due to the unsigned delta calculation of the time keeping core
1098 * code, which is necessary to support wrapping clocksources like pm
1099 * timer.
1100 *
1101 * This sanity check is now done in the core timekeeping code.
1102 * checking the result of read_tsc() - cycle_last for being negative.
1103 * That works because CLOCKSOURCE_MASK(64) does not mask out any bit.
1104 */
1105static u64 read_tsc(struct clocksource *cs)
1106{
1107 return (u64)rdtsc_ordered();
1108}
1109
1110/*
1111 * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc()
1112 */
1113static struct clocksource clocksource_tsc = {
1114 .name = "tsc",
1115 .rating = 300,
1116 .read = read_tsc,
1117 .mask = CLOCKSOURCE_MASK(64),
1118 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
1119 CLOCK_SOURCE_MUST_VERIFY,
1120 .archdata = { .vclock_mode = VCLOCK_TSC },
1121 .resume = tsc_resume,
1122};
1123
1124void mark_tsc_unstable(char *reason)
1125{
1126 if (!tsc_unstable) {
1127 tsc_unstable = 1;
1128 clear_sched_clock_stable();
1129 disable_sched_clock_irqtime();
1130 pr_info("Marking TSC unstable due to %s\n", reason);
1131 /* Change only the rating, when not registered */
1132 if (clocksource_tsc.mult)
1133 clocksource_mark_unstable(&clocksource_tsc);
1134 else {
1135 clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
1136 clocksource_tsc.rating = 0;
1137 }
1138 }
1139}
1140
1141EXPORT_SYMBOL_GPL(mark_tsc_unstable);
1142
1143static void __init check_system_tsc_reliable(void)
1144{
1145#if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
1146 if (is_geode_lx()) {
1147 /* RTSC counts during suspend */
1148#define RTSC_SUSP 0x100
1149 unsigned long res_low, res_high;
1150
1151 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
1152 /* Geode_LX - the OLPC CPU has a very reliable TSC */
1153 if (res_low & RTSC_SUSP)
1154 tsc_clocksource_reliable = 1;
1155 }
1156#endif
1157 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
1158 tsc_clocksource_reliable = 1;
1159}
1160
1161/*
1162 * Make an educated guess if the TSC is trustworthy and synchronized
1163 * over all CPUs.
1164 */
1165int unsynchronized_tsc(void)
1166{
1167 if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable)
1168 return 1;
1169
1170#ifdef CONFIG_SMP
1171 if (apic_is_clustered_box())
1172 return 1;
1173#endif
1174
1175 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1176 return 0;
1177
1178 if (tsc_clocksource_reliable)
1179 return 0;
1180 /*
1181 * Intel systems are normally all synchronized.
1182 * Exceptions must mark TSC as unstable:
1183 */
1184 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1185 /* assume multi socket systems are not synchronized: */
1186 if (num_possible_cpus() > 1)
1187 return 1;
1188 }
1189
1190 return 0;
1191}
1192
1193/*
1194 * Convert ART to TSC given numerator/denominator found in detect_art()
1195 */
1196struct system_counterval_t convert_art_to_tsc(u64 art)
1197{
1198 u64 tmp, res, rem;
1199
1200 rem = do_div(art, art_to_tsc_denominator);
1201
1202 res = art * art_to_tsc_numerator;
1203 tmp = rem * art_to_tsc_numerator;
1204
1205 do_div(tmp, art_to_tsc_denominator);
1206 res += tmp + art_to_tsc_offset;
1207
1208 return (struct system_counterval_t) {.cs = art_related_clocksource,
1209 .cycles = res};
1210}
1211EXPORT_SYMBOL(convert_art_to_tsc);
1212
1213static void tsc_refine_calibration_work(struct work_struct *work);
1214static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
1215/**
1216 * tsc_refine_calibration_work - Further refine tsc freq calibration
1217 * @work - ignored.
1218 *
1219 * This functions uses delayed work over a period of a
1220 * second to further refine the TSC freq value. Since this is
1221 * timer based, instead of loop based, we don't block the boot
1222 * process while this longer calibration is done.
1223 *
1224 * If there are any calibration anomalies (too many SMIs, etc),
1225 * or the refined calibration is off by 1% of the fast early
1226 * calibration, we throw out the new calibration and use the
1227 * early calibration.
1228 */
1229static void tsc_refine_calibration_work(struct work_struct *work)
1230{
1231 static u64 tsc_start = -1, ref_start;
1232 static int hpet;
1233 u64 tsc_stop, ref_stop, delta;
1234 unsigned long freq;
1235
1236 /* Don't bother refining TSC on unstable systems */
1237 if (check_tsc_unstable())
1238 goto out;
1239
1240 /*
1241 * Since the work is started early in boot, we may be
1242 * delayed the first time we expire. So set the workqueue
1243 * again once we know timers are working.
1244 */
1245 if (tsc_start == -1) {
1246 /*
1247 * Only set hpet once, to avoid mixing hardware
1248 * if the hpet becomes enabled later.
1249 */
1250 hpet = is_hpet_enabled();
1251 schedule_delayed_work(&tsc_irqwork, HZ);
1252 tsc_start = tsc_read_refs(&ref_start, hpet);
1253 return;
1254 }
1255
1256 tsc_stop = tsc_read_refs(&ref_stop, hpet);
1257
1258 /* hpet or pmtimer available ? */
1259 if (ref_start == ref_stop)
1260 goto out;
1261
1262 /* Check, whether the sampling was disturbed by an SMI */
1263 if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
1264 goto out;
1265
1266 delta = tsc_stop - tsc_start;
1267 delta *= 1000000LL;
1268 if (hpet)
1269 freq = calc_hpet_ref(delta, ref_start, ref_stop);
1270 else
1271 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
1272
1273 /* Make sure we're within 1% */
1274 if (abs(tsc_khz - freq) > tsc_khz/100)
1275 goto out;
1276
1277 tsc_khz = freq;
1278 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
1279 (unsigned long)tsc_khz / 1000,
1280 (unsigned long)tsc_khz % 1000);
1281
1282 /* Inform the TSC deadline clockevent devices about the recalibration */
1283 lapic_update_tsc_freq();
1284
1285out:
1286 if (boot_cpu_has(X86_FEATURE_ART))
1287 art_related_clocksource = &clocksource_tsc;
1288 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1289}
1290
1291
1292static int __init init_tsc_clocksource(void)
1293{
1294 if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_disabled > 0 || !tsc_khz)
1295 return 0;
1296
1297 if (tsc_clocksource_reliable)
1298 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
1299 /* lower the rating if we already know its unstable: */
1300 if (check_tsc_unstable()) {
1301 clocksource_tsc.rating = 0;
1302 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
1303 }
1304
1305 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
1306 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1307
1308 /*
1309 * When TSC frequency is known (retrieved via MSR or CPUID), we skip
1310 * the refined calibration and directly register it as a clocksource.
1311 */
1312 if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) {
1313 if (boot_cpu_has(X86_FEATURE_ART))
1314 art_related_clocksource = &clocksource_tsc;
1315 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1316 return 0;
1317 }
1318
1319 schedule_delayed_work(&tsc_irqwork, 0);
1320 return 0;
1321}
1322/*
1323 * We use device_initcall here, to ensure we run after the hpet
1324 * is fully initialized, which may occur at fs_initcall time.
1325 */
1326device_initcall(init_tsc_clocksource);
1327
1328void __init tsc_init(void)
1329{
1330 u64 lpj;
1331 int cpu;
1332
1333 if (!boot_cpu_has(X86_FEATURE_TSC)) {
1334 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1335 return;
1336 }
1337
1338 cpu_khz = x86_platform.calibrate_cpu();
1339 tsc_khz = x86_platform.calibrate_tsc();
1340
1341 /*
1342 * Trust non-zero tsc_khz as authorative,
1343 * and use it to sanity check cpu_khz,
1344 * which will be off if system timer is off.
1345 */
1346 if (tsc_khz == 0)
1347 tsc_khz = cpu_khz;
1348 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
1349 cpu_khz = tsc_khz;
1350
1351 if (!tsc_khz) {
1352 mark_tsc_unstable("could not calculate TSC khz");
1353 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1354 return;
1355 }
1356
1357 pr_info("Detected %lu.%03lu MHz processor\n",
1358 (unsigned long)cpu_khz / 1000,
1359 (unsigned long)cpu_khz % 1000);
1360
1361 /* Sanitize TSC ADJUST before cyc2ns gets initialized */
1362 tsc_store_and_check_tsc_adjust(true);
1363
1364 /*
1365 * Secondary CPUs do not run through tsc_init(), so set up
1366 * all the scale factors for all CPUs, assuming the same
1367 * speed as the bootup CPU. (cpufreq notifiers will fix this
1368 * up if their speed diverges)
1369 */
1370 for_each_possible_cpu(cpu) {
1371 cyc2ns_init(cpu);
1372 set_cyc2ns_scale(tsc_khz, cpu);
1373 }
1374
1375 if (tsc_disabled > 0)
1376 return;
1377
1378 /* now allow native_sched_clock() to use rdtsc */
1379
1380 tsc_disabled = 0;
1381 static_branch_enable(&__use_tsc);
1382
1383 if (!no_sched_irq_time)
1384 enable_sched_clock_irqtime();
1385
1386 lpj = ((u64)tsc_khz * 1000);
1387 do_div(lpj, HZ);
1388 lpj_fine = lpj;
1389
1390 use_tsc_delay();
1391
1392 if (unsynchronized_tsc())
1393 mark_tsc_unstable("TSCs unsynchronized");
1394
1395 check_system_tsc_reliable();
1396
1397 detect_art();
1398}
1399
1400#ifdef CONFIG_SMP
1401/*
1402 * If we have a constant TSC and are using the TSC for the delay loop,
1403 * we can skip clock calibration if another cpu in the same socket has already
1404 * been calibrated. This assumes that CONSTANT_TSC applies to all
1405 * cpus in the socket - this should be a safe assumption.
1406 */
1407unsigned long calibrate_delay_is_known(void)
1408{
1409 int sibling, cpu = smp_processor_id();
1410 struct cpumask *mask = topology_core_cpumask(cpu);
1411
1412 if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
1413 return 0;
1414
1415 if (!mask)
1416 return 0;
1417
1418 sibling = cpumask_any_but(mask, cpu);
1419 if (sibling < nr_cpu_ids)
1420 return cpu_data(sibling).loops_per_jiffy;
1421 return 0;
1422}
1423#endif