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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Architecture specific OF callbacks.
4 */
5#include <linux/export.h>
6#include <linux/io.h>
7#include <linux/interrupt.h>
8#include <linux/list.h>
9#include <linux/of.h>
10#include <linux/of_fdt.h>
11#include <linux/of_address.h>
12#include <linux/of_platform.h>
13#include <linux/of_irq.h>
14#include <linux/libfdt.h>
15#include <linux/slab.h>
16#include <linux/pci.h>
17#include <linux/of_pci.h>
18#include <linux/initrd.h>
19
20#include <asm/irqdomain.h>
21#include <asm/hpet.h>
22#include <asm/apic.h>
23#include <asm/pci_x86.h>
24#include <asm/setup.h>
25#include <asm/i8259.h>
26
27__initdata u64 initial_dtb;
28char __initdata cmd_line[COMMAND_LINE_SIZE];
29
30int __initdata of_ioapic;
31
32void __init early_init_dt_scan_chosen_arch(unsigned long node)
33{
34 BUG();
35}
36
37void __init early_init_dt_add_memory_arch(u64 base, u64 size)
38{
39 BUG();
40}
41
42void __init add_dtb(u64 data)
43{
44 initial_dtb = data + offsetof(struct setup_data, data);
45}
46
47/*
48 * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
49 */
50static struct of_device_id __initdata ce4100_ids[] = {
51 { .compatible = "intel,ce4100-cp", },
52 { .compatible = "isa", },
53 { .compatible = "pci", },
54 {},
55};
56
57static int __init add_bus_probe(void)
58{
59 if (!of_have_populated_dt())
60 return 0;
61
62 return of_platform_bus_probe(NULL, ce4100_ids, NULL);
63}
64device_initcall(add_bus_probe);
65
66#ifdef CONFIG_PCI
67struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
68{
69 struct device_node *np;
70
71 for_each_node_by_type(np, "pci") {
72 const void *prop;
73 unsigned int bus_min;
74
75 prop = of_get_property(np, "bus-range", NULL);
76 if (!prop)
77 continue;
78 bus_min = be32_to_cpup(prop);
79 if (bus->number == bus_min)
80 return np;
81 }
82 return NULL;
83}
84
85static int x86_of_pci_irq_enable(struct pci_dev *dev)
86{
87 u32 virq;
88 int ret;
89 u8 pin;
90
91 ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
92 if (ret)
93 return ret;
94 if (!pin)
95 return 0;
96
97 virq = of_irq_parse_and_map_pci(dev, 0, 0);
98 if (virq == 0)
99 return -EINVAL;
100 dev->irq = virq;
101 return 0;
102}
103
104static void x86_of_pci_irq_disable(struct pci_dev *dev)
105{
106}
107
108void x86_of_pci_init(void)
109{
110 pcibios_enable_irq = x86_of_pci_irq_enable;
111 pcibios_disable_irq = x86_of_pci_irq_disable;
112}
113#endif
114
115static void __init dtb_setup_hpet(void)
116{
117#ifdef CONFIG_HPET_TIMER
118 struct device_node *dn;
119 struct resource r;
120 int ret;
121
122 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
123 if (!dn)
124 return;
125 ret = of_address_to_resource(dn, 0, &r);
126 if (ret) {
127 WARN_ON(1);
128 return;
129 }
130 hpet_address = r.start;
131#endif
132}
133
134#ifdef CONFIG_X86_LOCAL_APIC
135
136static void __init dtb_cpu_setup(void)
137{
138 struct device_node *dn;
139 u32 apic_id, version;
140 int ret;
141
142 version = GET_APIC_VERSION(apic_read(APIC_LVR));
143 for_each_node_by_type(dn, "cpu") {
144 ret = of_property_read_u32(dn, "reg", &apic_id);
145 if (ret < 0) {
146 pr_warn("%pOF: missing local APIC ID\n", dn);
147 continue;
148 }
149 generic_processor_info(apic_id, version);
150 }
151}
152
153static void __init dtb_lapic_setup(void)
154{
155 struct device_node *dn;
156 struct resource r;
157 unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
158 int ret;
159
160 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
161 if (dn) {
162 ret = of_address_to_resource(dn, 0, &r);
163 if (WARN_ON(ret))
164 return;
165 lapic_addr = r.start;
166 }
167
168 /* Did the boot loader setup the local APIC ? */
169 if (!boot_cpu_has(X86_FEATURE_APIC)) {
170 if (apic_force_enable(lapic_addr))
171 return;
172 }
173 smp_found_config = 1;
174 pic_mode = 1;
175 register_lapic_address(lapic_addr);
176}
177
178#endif /* CONFIG_X86_LOCAL_APIC */
179
180#ifdef CONFIG_X86_IO_APIC
181static unsigned int ioapic_id;
182
183struct of_ioapic_type {
184 u32 out_type;
185 u32 trigger;
186 u32 polarity;
187};
188
189static struct of_ioapic_type of_ioapic_type[] =
190{
191 {
192 .out_type = IRQ_TYPE_EDGE_RISING,
193 .trigger = IOAPIC_EDGE,
194 .polarity = 1,
195 },
196 {
197 .out_type = IRQ_TYPE_LEVEL_LOW,
198 .trigger = IOAPIC_LEVEL,
199 .polarity = 0,
200 },
201 {
202 .out_type = IRQ_TYPE_LEVEL_HIGH,
203 .trigger = IOAPIC_LEVEL,
204 .polarity = 1,
205 },
206 {
207 .out_type = IRQ_TYPE_EDGE_FALLING,
208 .trigger = IOAPIC_EDGE,
209 .polarity = 0,
210 },
211};
212
213static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
214 unsigned int nr_irqs, void *arg)
215{
216 struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
217 struct of_ioapic_type *it;
218 struct irq_alloc_info tmp;
219 int type_index;
220
221 if (WARN_ON(fwspec->param_count < 2))
222 return -EINVAL;
223
224 type_index = fwspec->param[1];
225 if (type_index >= ARRAY_SIZE(of_ioapic_type))
226 return -EINVAL;
227
228 it = &of_ioapic_type[type_index];
229 ioapic_set_alloc_attr(&tmp, NUMA_NO_NODE, it->trigger, it->polarity);
230 tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
231 tmp.ioapic_pin = fwspec->param[0];
232
233 return mp_irqdomain_alloc(domain, virq, nr_irqs, &tmp);
234}
235
236static const struct irq_domain_ops ioapic_irq_domain_ops = {
237 .alloc = dt_irqdomain_alloc,
238 .free = mp_irqdomain_free,
239 .activate = mp_irqdomain_activate,
240 .deactivate = mp_irqdomain_deactivate,
241};
242
243static void __init dtb_add_ioapic(struct device_node *dn)
244{
245 struct resource r;
246 int ret;
247 struct ioapic_domain_cfg cfg = {
248 .type = IOAPIC_DOMAIN_DYNAMIC,
249 .ops = &ioapic_irq_domain_ops,
250 .dev = dn,
251 };
252
253 ret = of_address_to_resource(dn, 0, &r);
254 if (ret) {
255 printk(KERN_ERR "Can't obtain address from device node %pOF.\n", dn);
256 return;
257 }
258 mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg);
259}
260
261static void __init dtb_ioapic_setup(void)
262{
263 struct device_node *dn;
264
265 for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
266 dtb_add_ioapic(dn);
267
268 if (nr_ioapics) {
269 of_ioapic = 1;
270 return;
271 }
272 printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
273}
274#else
275static void __init dtb_ioapic_setup(void) {}
276#endif
277
278static void __init dtb_apic_setup(void)
279{
280#ifdef CONFIG_X86_LOCAL_APIC
281 dtb_lapic_setup();
282 dtb_cpu_setup();
283#endif
284 dtb_ioapic_setup();
285}
286
287#ifdef CONFIG_OF_EARLY_FLATTREE
288static void __init x86_flattree_get_config(void)
289{
290 u32 size, map_len;
291 void *dt;
292
293 if (!initial_dtb)
294 return;
295
296 map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
297
298 dt = early_memremap(initial_dtb, map_len);
299 size = fdt_totalsize(dt);
300 if (map_len < size) {
301 early_memunmap(dt, map_len);
302 dt = early_memremap(initial_dtb, size);
303 map_len = size;
304 }
305
306 early_init_dt_verify(dt);
307 unflatten_and_copy_device_tree();
308 early_memunmap(dt, map_len);
309}
310#else
311static inline void x86_flattree_get_config(void) { }
312#endif
313
314void __init x86_dtb_init(void)
315{
316 x86_flattree_get_config();
317
318 if (!of_have_populated_dt())
319 return;
320
321 dtb_setup_hpet();
322 dtb_apic_setup();
323}
1/*
2 * Architecture specific OF callbacks.
3 */
4#include <linux/bootmem.h>
5#include <linux/io.h>
6#include <linux/interrupt.h>
7#include <linux/list.h>
8#include <linux/of.h>
9#include <linux/of_fdt.h>
10#include <linux/of_address.h>
11#include <linux/of_platform.h>
12#include <linux/of_irq.h>
13#include <linux/slab.h>
14#include <linux/pci.h>
15#include <linux/of_pci.h>
16#include <linux/initrd.h>
17
18#include <asm/hpet.h>
19#include <asm/irq_controller.h>
20#include <asm/apic.h>
21#include <asm/pci_x86.h>
22
23__initdata u64 initial_dtb;
24char __initdata cmd_line[COMMAND_LINE_SIZE];
25static LIST_HEAD(irq_domains);
26static DEFINE_RAW_SPINLOCK(big_irq_lock);
27
28int __initdata of_ioapic;
29
30#ifdef CONFIG_X86_IO_APIC
31static void add_interrupt_host(struct irq_domain *ih)
32{
33 unsigned long flags;
34
35 raw_spin_lock_irqsave(&big_irq_lock, flags);
36 list_add(&ih->l, &irq_domains);
37 raw_spin_unlock_irqrestore(&big_irq_lock, flags);
38}
39#endif
40
41static struct irq_domain *get_ih_from_node(struct device_node *controller)
42{
43 struct irq_domain *ih, *found = NULL;
44 unsigned long flags;
45
46 raw_spin_lock_irqsave(&big_irq_lock, flags);
47 list_for_each_entry(ih, &irq_domains, l) {
48 if (ih->controller == controller) {
49 found = ih;
50 break;
51 }
52 }
53 raw_spin_unlock_irqrestore(&big_irq_lock, flags);
54 return found;
55}
56
57unsigned int irq_create_of_mapping(struct device_node *controller,
58 const u32 *intspec, unsigned int intsize)
59{
60 struct irq_domain *ih;
61 u32 virq, type;
62 int ret;
63
64 ih = get_ih_from_node(controller);
65 if (!ih)
66 return 0;
67 ret = ih->xlate(ih, intspec, intsize, &virq, &type);
68 if (ret)
69 return 0;
70 if (type == IRQ_TYPE_NONE)
71 return virq;
72 irq_set_irq_type(virq, type);
73 return virq;
74}
75EXPORT_SYMBOL_GPL(irq_create_of_mapping);
76
77unsigned long pci_address_to_pio(phys_addr_t address)
78{
79 /*
80 * The ioport address can be directly used by inX / outX
81 */
82 BUG_ON(address >= (1 << 16));
83 return (unsigned long)address;
84}
85EXPORT_SYMBOL_GPL(pci_address_to_pio);
86
87void __init early_init_dt_scan_chosen_arch(unsigned long node)
88{
89 BUG();
90}
91
92void __init early_init_dt_add_memory_arch(u64 base, u64 size)
93{
94 BUG();
95}
96
97void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
98{
99 return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
100}
101
102#ifdef CONFIG_BLK_DEV_INITRD
103void __init early_init_dt_setup_initrd_arch(unsigned long start,
104 unsigned long end)
105{
106 initrd_start = (unsigned long)__va(start);
107 initrd_end = (unsigned long)__va(end);
108 initrd_below_start_ok = 1;
109}
110#endif
111
112void __init add_dtb(u64 data)
113{
114 initial_dtb = data + offsetof(struct setup_data, data);
115}
116
117/*
118 * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
119 */
120static struct of_device_id __initdata ce4100_ids[] = {
121 { .compatible = "intel,ce4100-cp", },
122 { .compatible = "isa", },
123 { .compatible = "pci", },
124 {},
125};
126
127static int __init add_bus_probe(void)
128{
129 if (!of_have_populated_dt())
130 return 0;
131
132 return of_platform_bus_probe(NULL, ce4100_ids, NULL);
133}
134module_init(add_bus_probe);
135
136#ifdef CONFIG_PCI
137struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
138{
139 struct device_node *np;
140
141 for_each_node_by_type(np, "pci") {
142 const void *prop;
143 unsigned int bus_min;
144
145 prop = of_get_property(np, "bus-range", NULL);
146 if (!prop)
147 continue;
148 bus_min = be32_to_cpup(prop);
149 if (bus->number == bus_min)
150 return np;
151 }
152 return NULL;
153}
154
155static int x86_of_pci_irq_enable(struct pci_dev *dev)
156{
157 struct of_irq oirq;
158 u32 virq;
159 int ret;
160 u8 pin;
161
162 ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
163 if (ret)
164 return ret;
165 if (!pin)
166 return 0;
167
168 ret = of_irq_map_pci(dev, &oirq);
169 if (ret)
170 return ret;
171
172 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
173 oirq.size);
174 if (virq == 0)
175 return -EINVAL;
176 dev->irq = virq;
177 return 0;
178}
179
180static void x86_of_pci_irq_disable(struct pci_dev *dev)
181{
182}
183
184void __cpuinit x86_of_pci_init(void)
185{
186 pcibios_enable_irq = x86_of_pci_irq_enable;
187 pcibios_disable_irq = x86_of_pci_irq_disable;
188}
189#endif
190
191static void __init dtb_setup_hpet(void)
192{
193#ifdef CONFIG_HPET_TIMER
194 struct device_node *dn;
195 struct resource r;
196 int ret;
197
198 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
199 if (!dn)
200 return;
201 ret = of_address_to_resource(dn, 0, &r);
202 if (ret) {
203 WARN_ON(1);
204 return;
205 }
206 hpet_address = r.start;
207#endif
208}
209
210static void __init dtb_lapic_setup(void)
211{
212#ifdef CONFIG_X86_LOCAL_APIC
213 struct device_node *dn;
214 struct resource r;
215 int ret;
216
217 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
218 if (!dn)
219 return;
220
221 ret = of_address_to_resource(dn, 0, &r);
222 if (WARN_ON(ret))
223 return;
224
225 /* Did the boot loader setup the local APIC ? */
226 if (!cpu_has_apic) {
227 if (apic_force_enable(r.start))
228 return;
229 }
230 smp_found_config = 1;
231 pic_mode = 1;
232 register_lapic_address(r.start);
233 generic_processor_info(boot_cpu_physical_apicid,
234 GET_APIC_VERSION(apic_read(APIC_LVR)));
235#endif
236}
237
238#ifdef CONFIG_X86_IO_APIC
239static unsigned int ioapic_id;
240
241static void __init dtb_add_ioapic(struct device_node *dn)
242{
243 struct resource r;
244 int ret;
245
246 ret = of_address_to_resource(dn, 0, &r);
247 if (ret) {
248 printk(KERN_ERR "Can't obtain address from node %s.\n",
249 dn->full_name);
250 return;
251 }
252 mp_register_ioapic(++ioapic_id, r.start, gsi_top);
253}
254
255static void __init dtb_ioapic_setup(void)
256{
257 struct device_node *dn;
258
259 for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
260 dtb_add_ioapic(dn);
261
262 if (nr_ioapics) {
263 of_ioapic = 1;
264 return;
265 }
266 printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
267}
268#else
269static void __init dtb_ioapic_setup(void) {}
270#endif
271
272static void __init dtb_apic_setup(void)
273{
274 dtb_lapic_setup();
275 dtb_ioapic_setup();
276}
277
278#ifdef CONFIG_OF_FLATTREE
279static void __init x86_flattree_get_config(void)
280{
281 u32 size, map_len;
282 void *new_dtb;
283
284 if (!initial_dtb)
285 return;
286
287 map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK),
288 (u64)sizeof(struct boot_param_header));
289
290 initial_boot_params = early_memremap(initial_dtb, map_len);
291 size = be32_to_cpu(initial_boot_params->totalsize);
292 if (map_len < size) {
293 early_iounmap(initial_boot_params, map_len);
294 initial_boot_params = early_memremap(initial_dtb, size);
295 map_len = size;
296 }
297
298 new_dtb = alloc_bootmem(size);
299 memcpy(new_dtb, initial_boot_params, size);
300 early_iounmap(initial_boot_params, map_len);
301
302 initial_boot_params = new_dtb;
303
304 /* root level address cells */
305 of_scan_flat_dt(early_init_dt_scan_root, NULL);
306
307 unflatten_device_tree();
308}
309#else
310static inline void x86_flattree_get_config(void) { }
311#endif
312
313void __init x86_dtb_init(void)
314{
315 x86_flattree_get_config();
316
317 if (!of_have_populated_dt())
318 return;
319
320 dtb_setup_hpet();
321 dtb_apic_setup();
322}
323
324#ifdef CONFIG_X86_IO_APIC
325
326struct of_ioapic_type {
327 u32 out_type;
328 u32 trigger;
329 u32 polarity;
330};
331
332static struct of_ioapic_type of_ioapic_type[] =
333{
334 {
335 .out_type = IRQ_TYPE_EDGE_RISING,
336 .trigger = IOAPIC_EDGE,
337 .polarity = 1,
338 },
339 {
340 .out_type = IRQ_TYPE_LEVEL_LOW,
341 .trigger = IOAPIC_LEVEL,
342 .polarity = 0,
343 },
344 {
345 .out_type = IRQ_TYPE_LEVEL_HIGH,
346 .trigger = IOAPIC_LEVEL,
347 .polarity = 1,
348 },
349 {
350 .out_type = IRQ_TYPE_EDGE_FALLING,
351 .trigger = IOAPIC_EDGE,
352 .polarity = 0,
353 },
354};
355
356static int ioapic_xlate(struct irq_domain *id, const u32 *intspec, u32 intsize,
357 u32 *out_hwirq, u32 *out_type)
358{
359 struct mp_ioapic_gsi *gsi_cfg;
360 struct io_apic_irq_attr attr;
361 struct of_ioapic_type *it;
362 u32 line, idx, type;
363
364 if (intsize < 2)
365 return -EINVAL;
366
367 line = *intspec;
368 idx = (u32) id->priv;
369 gsi_cfg = mp_ioapic_gsi_routing(idx);
370 *out_hwirq = line + gsi_cfg->gsi_base;
371
372 intspec++;
373 type = *intspec;
374
375 if (type >= ARRAY_SIZE(of_ioapic_type))
376 return -EINVAL;
377
378 it = of_ioapic_type + type;
379 *out_type = it->out_type;
380
381 set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity);
382
383 return io_apic_setup_irq_pin_once(*out_hwirq, cpu_to_node(0), &attr);
384}
385
386static void __init ioapic_add_ofnode(struct device_node *np)
387{
388 struct resource r;
389 int i, ret;
390
391 ret = of_address_to_resource(np, 0, &r);
392 if (ret) {
393 printk(KERN_ERR "Failed to obtain address for %s\n",
394 np->full_name);
395 return;
396 }
397
398 for (i = 0; i < nr_ioapics; i++) {
399 if (r.start == mpc_ioapic_addr(i)) {
400 struct irq_domain *id;
401
402 id = kzalloc(sizeof(*id), GFP_KERNEL);
403 BUG_ON(!id);
404 id->controller = np;
405 id->xlate = ioapic_xlate;
406 id->priv = (void *)i;
407 add_interrupt_host(id);
408 return;
409 }
410 }
411 printk(KERN_ERR "IOxAPIC at %s is not registered.\n", np->full_name);
412}
413
414void __init x86_add_irq_domains(void)
415{
416 struct device_node *dp;
417
418 if (!of_have_populated_dt())
419 return;
420
421 for_each_node_with_property(dp, "interrupt-controller") {
422 if (of_device_is_compatible(dp, "intel,ce4100-ioapic"))
423 ioapic_add_ofnode(dp);
424 }
425}
426#else
427void __init x86_add_irq_domains(void) { }
428#endif