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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Architecture specific OF callbacks.
4 */
5#include <linux/export.h>
6#include <linux/io.h>
7#include <linux/interrupt.h>
8#include <linux/list.h>
9#include <linux/of.h>
10#include <linux/of_fdt.h>
11#include <linux/of_address.h>
12#include <linux/of_platform.h>
13#include <linux/of_irq.h>
14#include <linux/libfdt.h>
15#include <linux/slab.h>
16#include <linux/pci.h>
17#include <linux/of_pci.h>
18#include <linux/initrd.h>
19
20#include <asm/irqdomain.h>
21#include <asm/hpet.h>
22#include <asm/apic.h>
23#include <asm/pci_x86.h>
24#include <asm/setup.h>
25#include <asm/i8259.h>
26
27__initdata u64 initial_dtb;
28char __initdata cmd_line[COMMAND_LINE_SIZE];
29
30int __initdata of_ioapic;
31
32void __init early_init_dt_scan_chosen_arch(unsigned long node)
33{
34 BUG();
35}
36
37void __init early_init_dt_add_memory_arch(u64 base, u64 size)
38{
39 BUG();
40}
41
42void __init add_dtb(u64 data)
43{
44 initial_dtb = data + offsetof(struct setup_data, data);
45}
46
47/*
48 * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
49 */
50static struct of_device_id __initdata ce4100_ids[] = {
51 { .compatible = "intel,ce4100-cp", },
52 { .compatible = "isa", },
53 { .compatible = "pci", },
54 {},
55};
56
57static int __init add_bus_probe(void)
58{
59 if (!of_have_populated_dt())
60 return 0;
61
62 return of_platform_bus_probe(NULL, ce4100_ids, NULL);
63}
64device_initcall(add_bus_probe);
65
66#ifdef CONFIG_PCI
67struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
68{
69 struct device_node *np;
70
71 for_each_node_by_type(np, "pci") {
72 const void *prop;
73 unsigned int bus_min;
74
75 prop = of_get_property(np, "bus-range", NULL);
76 if (!prop)
77 continue;
78 bus_min = be32_to_cpup(prop);
79 if (bus->number == bus_min)
80 return np;
81 }
82 return NULL;
83}
84
85static int x86_of_pci_irq_enable(struct pci_dev *dev)
86{
87 u32 virq;
88 int ret;
89 u8 pin;
90
91 ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
92 if (ret)
93 return ret;
94 if (!pin)
95 return 0;
96
97 virq = of_irq_parse_and_map_pci(dev, 0, 0);
98 if (virq == 0)
99 return -EINVAL;
100 dev->irq = virq;
101 return 0;
102}
103
104static void x86_of_pci_irq_disable(struct pci_dev *dev)
105{
106}
107
108void x86_of_pci_init(void)
109{
110 pcibios_enable_irq = x86_of_pci_irq_enable;
111 pcibios_disable_irq = x86_of_pci_irq_disable;
112}
113#endif
114
115static void __init dtb_setup_hpet(void)
116{
117#ifdef CONFIG_HPET_TIMER
118 struct device_node *dn;
119 struct resource r;
120 int ret;
121
122 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
123 if (!dn)
124 return;
125 ret = of_address_to_resource(dn, 0, &r);
126 if (ret) {
127 WARN_ON(1);
128 return;
129 }
130 hpet_address = r.start;
131#endif
132}
133
134#ifdef CONFIG_X86_LOCAL_APIC
135
136static void __init dtb_cpu_setup(void)
137{
138 struct device_node *dn;
139 u32 apic_id, version;
140 int ret;
141
142 version = GET_APIC_VERSION(apic_read(APIC_LVR));
143 for_each_node_by_type(dn, "cpu") {
144 ret = of_property_read_u32(dn, "reg", &apic_id);
145 if (ret < 0) {
146 pr_warn("%pOF: missing local APIC ID\n", dn);
147 continue;
148 }
149 generic_processor_info(apic_id, version);
150 }
151}
152
153static void __init dtb_lapic_setup(void)
154{
155 struct device_node *dn;
156 struct resource r;
157 unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
158 int ret;
159
160 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
161 if (dn) {
162 ret = of_address_to_resource(dn, 0, &r);
163 if (WARN_ON(ret))
164 return;
165 lapic_addr = r.start;
166 }
167
168 /* Did the boot loader setup the local APIC ? */
169 if (!boot_cpu_has(X86_FEATURE_APIC)) {
170 if (apic_force_enable(lapic_addr))
171 return;
172 }
173 smp_found_config = 1;
174 pic_mode = 1;
175 register_lapic_address(lapic_addr);
176}
177
178#endif /* CONFIG_X86_LOCAL_APIC */
179
180#ifdef CONFIG_X86_IO_APIC
181static unsigned int ioapic_id;
182
183struct of_ioapic_type {
184 u32 out_type;
185 u32 trigger;
186 u32 polarity;
187};
188
189static struct of_ioapic_type of_ioapic_type[] =
190{
191 {
192 .out_type = IRQ_TYPE_EDGE_RISING,
193 .trigger = IOAPIC_EDGE,
194 .polarity = 1,
195 },
196 {
197 .out_type = IRQ_TYPE_LEVEL_LOW,
198 .trigger = IOAPIC_LEVEL,
199 .polarity = 0,
200 },
201 {
202 .out_type = IRQ_TYPE_LEVEL_HIGH,
203 .trigger = IOAPIC_LEVEL,
204 .polarity = 1,
205 },
206 {
207 .out_type = IRQ_TYPE_EDGE_FALLING,
208 .trigger = IOAPIC_EDGE,
209 .polarity = 0,
210 },
211};
212
213static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
214 unsigned int nr_irqs, void *arg)
215{
216 struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
217 struct of_ioapic_type *it;
218 struct irq_alloc_info tmp;
219 int type_index;
220
221 if (WARN_ON(fwspec->param_count < 2))
222 return -EINVAL;
223
224 type_index = fwspec->param[1];
225 if (type_index >= ARRAY_SIZE(of_ioapic_type))
226 return -EINVAL;
227
228 it = &of_ioapic_type[type_index];
229 ioapic_set_alloc_attr(&tmp, NUMA_NO_NODE, it->trigger, it->polarity);
230 tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
231 tmp.ioapic_pin = fwspec->param[0];
232
233 return mp_irqdomain_alloc(domain, virq, nr_irqs, &tmp);
234}
235
236static const struct irq_domain_ops ioapic_irq_domain_ops = {
237 .alloc = dt_irqdomain_alloc,
238 .free = mp_irqdomain_free,
239 .activate = mp_irqdomain_activate,
240 .deactivate = mp_irqdomain_deactivate,
241};
242
243static void __init dtb_add_ioapic(struct device_node *dn)
244{
245 struct resource r;
246 int ret;
247 struct ioapic_domain_cfg cfg = {
248 .type = IOAPIC_DOMAIN_DYNAMIC,
249 .ops = &ioapic_irq_domain_ops,
250 .dev = dn,
251 };
252
253 ret = of_address_to_resource(dn, 0, &r);
254 if (ret) {
255 printk(KERN_ERR "Can't obtain address from device node %pOF.\n", dn);
256 return;
257 }
258 mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg);
259}
260
261static void __init dtb_ioapic_setup(void)
262{
263 struct device_node *dn;
264
265 for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
266 dtb_add_ioapic(dn);
267
268 if (nr_ioapics) {
269 of_ioapic = 1;
270 return;
271 }
272 printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
273}
274#else
275static void __init dtb_ioapic_setup(void) {}
276#endif
277
278static void __init dtb_apic_setup(void)
279{
280#ifdef CONFIG_X86_LOCAL_APIC
281 dtb_lapic_setup();
282 dtb_cpu_setup();
283#endif
284 dtb_ioapic_setup();
285}
286
287#ifdef CONFIG_OF_EARLY_FLATTREE
288static void __init x86_flattree_get_config(void)
289{
290 u32 size, map_len;
291 void *dt;
292
293 if (!initial_dtb)
294 return;
295
296 map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
297
298 dt = early_memremap(initial_dtb, map_len);
299 size = fdt_totalsize(dt);
300 if (map_len < size) {
301 early_memunmap(dt, map_len);
302 dt = early_memremap(initial_dtb, size);
303 map_len = size;
304 }
305
306 early_init_dt_verify(dt);
307 unflatten_and_copy_device_tree();
308 early_memunmap(dt, map_len);
309}
310#else
311static inline void x86_flattree_get_config(void) { }
312#endif
313
314void __init x86_dtb_init(void)
315{
316 x86_flattree_get_config();
317
318 if (!of_have_populated_dt())
319 return;
320
321 dtb_setup_hpet();
322 dtb_apic_setup();
323}
1/*
2 * Architecture specific OF callbacks.
3 */
4#include <linux/bootmem.h>
5#include <linux/export.h>
6#include <linux/io.h>
7#include <linux/interrupt.h>
8#include <linux/list.h>
9#include <linux/of.h>
10#include <linux/of_fdt.h>
11#include <linux/of_address.h>
12#include <linux/of_platform.h>
13#include <linux/of_irq.h>
14#include <linux/slab.h>
15#include <linux/pci.h>
16#include <linux/of_pci.h>
17#include <linux/initrd.h>
18
19#include <asm/irqdomain.h>
20#include <asm/hpet.h>
21#include <asm/apic.h>
22#include <asm/pci_x86.h>
23#include <asm/setup.h>
24#include <asm/i8259.h>
25
26__initdata u64 initial_dtb;
27char __initdata cmd_line[COMMAND_LINE_SIZE];
28
29int __initdata of_ioapic;
30
31void __init early_init_dt_scan_chosen_arch(unsigned long node)
32{
33 BUG();
34}
35
36void __init early_init_dt_add_memory_arch(u64 base, u64 size)
37{
38 BUG();
39}
40
41void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
42{
43 return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
44}
45
46void __init add_dtb(u64 data)
47{
48 initial_dtb = data + offsetof(struct setup_data, data);
49}
50
51/*
52 * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
53 */
54static struct of_device_id __initdata ce4100_ids[] = {
55 { .compatible = "intel,ce4100-cp", },
56 { .compatible = "isa", },
57 { .compatible = "pci", },
58 {},
59};
60
61static int __init add_bus_probe(void)
62{
63 if (!of_have_populated_dt())
64 return 0;
65
66 return of_platform_bus_probe(NULL, ce4100_ids, NULL);
67}
68device_initcall(add_bus_probe);
69
70#ifdef CONFIG_PCI
71struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
72{
73 struct device_node *np;
74
75 for_each_node_by_type(np, "pci") {
76 const void *prop;
77 unsigned int bus_min;
78
79 prop = of_get_property(np, "bus-range", NULL);
80 if (!prop)
81 continue;
82 bus_min = be32_to_cpup(prop);
83 if (bus->number == bus_min)
84 return np;
85 }
86 return NULL;
87}
88
89static int x86_of_pci_irq_enable(struct pci_dev *dev)
90{
91 u32 virq;
92 int ret;
93 u8 pin;
94
95 ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
96 if (ret)
97 return ret;
98 if (!pin)
99 return 0;
100
101 virq = of_irq_parse_and_map_pci(dev, 0, 0);
102 if (virq == 0)
103 return -EINVAL;
104 dev->irq = virq;
105 return 0;
106}
107
108static void x86_of_pci_irq_disable(struct pci_dev *dev)
109{
110}
111
112void x86_of_pci_init(void)
113{
114 pcibios_enable_irq = x86_of_pci_irq_enable;
115 pcibios_disable_irq = x86_of_pci_irq_disable;
116}
117#endif
118
119static void __init dtb_setup_hpet(void)
120{
121#ifdef CONFIG_HPET_TIMER
122 struct device_node *dn;
123 struct resource r;
124 int ret;
125
126 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
127 if (!dn)
128 return;
129 ret = of_address_to_resource(dn, 0, &r);
130 if (ret) {
131 WARN_ON(1);
132 return;
133 }
134 hpet_address = r.start;
135#endif
136}
137
138static void __init dtb_lapic_setup(void)
139{
140#ifdef CONFIG_X86_LOCAL_APIC
141 struct device_node *dn;
142 struct resource r;
143 int ret;
144
145 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
146 if (!dn)
147 return;
148
149 ret = of_address_to_resource(dn, 0, &r);
150 if (WARN_ON(ret))
151 return;
152
153 /* Did the boot loader setup the local APIC ? */
154 if (!cpu_has_apic) {
155 if (apic_force_enable(r.start))
156 return;
157 }
158 smp_found_config = 1;
159 pic_mode = 1;
160 register_lapic_address(r.start);
161 generic_processor_info(boot_cpu_physical_apicid,
162 GET_APIC_VERSION(apic_read(APIC_LVR)));
163#endif
164}
165
166#ifdef CONFIG_X86_IO_APIC
167static unsigned int ioapic_id;
168
169struct of_ioapic_type {
170 u32 out_type;
171 u32 trigger;
172 u32 polarity;
173};
174
175static struct of_ioapic_type of_ioapic_type[] =
176{
177 {
178 .out_type = IRQ_TYPE_EDGE_RISING,
179 .trigger = IOAPIC_EDGE,
180 .polarity = 1,
181 },
182 {
183 .out_type = IRQ_TYPE_LEVEL_LOW,
184 .trigger = IOAPIC_LEVEL,
185 .polarity = 0,
186 },
187 {
188 .out_type = IRQ_TYPE_LEVEL_HIGH,
189 .trigger = IOAPIC_LEVEL,
190 .polarity = 1,
191 },
192 {
193 .out_type = IRQ_TYPE_EDGE_FALLING,
194 .trigger = IOAPIC_EDGE,
195 .polarity = 0,
196 },
197};
198
199static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
200 unsigned int nr_irqs, void *arg)
201{
202 struct of_phandle_args *irq_data = (void *)arg;
203 struct of_ioapic_type *it;
204 struct irq_alloc_info tmp;
205
206 if (WARN_ON(irq_data->args_count < 2))
207 return -EINVAL;
208 if (irq_data->args[1] >= ARRAY_SIZE(of_ioapic_type))
209 return -EINVAL;
210
211 it = &of_ioapic_type[irq_data->args[1]];
212 ioapic_set_alloc_attr(&tmp, NUMA_NO_NODE, it->trigger, it->polarity);
213 tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
214 tmp.ioapic_pin = irq_data->args[0];
215
216 return mp_irqdomain_alloc(domain, virq, nr_irqs, &tmp);
217}
218
219static const struct irq_domain_ops ioapic_irq_domain_ops = {
220 .alloc = dt_irqdomain_alloc,
221 .free = mp_irqdomain_free,
222 .activate = mp_irqdomain_activate,
223 .deactivate = mp_irqdomain_deactivate,
224};
225
226static void __init dtb_add_ioapic(struct device_node *dn)
227{
228 struct resource r;
229 int ret;
230 struct ioapic_domain_cfg cfg = {
231 .type = IOAPIC_DOMAIN_DYNAMIC,
232 .ops = &ioapic_irq_domain_ops,
233 .dev = dn,
234 };
235
236 ret = of_address_to_resource(dn, 0, &r);
237 if (ret) {
238 printk(KERN_ERR "Can't obtain address from node %s.\n",
239 dn->full_name);
240 return;
241 }
242 mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg);
243}
244
245static void __init dtb_ioapic_setup(void)
246{
247 struct device_node *dn;
248
249 for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
250 dtb_add_ioapic(dn);
251
252 if (nr_ioapics) {
253 of_ioapic = 1;
254 return;
255 }
256 printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
257}
258#else
259static void __init dtb_ioapic_setup(void) {}
260#endif
261
262static void __init dtb_apic_setup(void)
263{
264 dtb_lapic_setup();
265 dtb_ioapic_setup();
266}
267
268#ifdef CONFIG_OF_FLATTREE
269static void __init x86_flattree_get_config(void)
270{
271 u32 size, map_len;
272 void *dt;
273
274 if (!initial_dtb)
275 return;
276
277 map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
278
279 initial_boot_params = dt = early_memremap(initial_dtb, map_len);
280 size = of_get_flat_dt_size();
281 if (map_len < size) {
282 early_memunmap(dt, map_len);
283 initial_boot_params = dt = early_memremap(initial_dtb, size);
284 map_len = size;
285 }
286
287 unflatten_and_copy_device_tree();
288 early_memunmap(dt, map_len);
289}
290#else
291static inline void x86_flattree_get_config(void) { }
292#endif
293
294void __init x86_dtb_init(void)
295{
296 x86_flattree_get_config();
297
298 if (!of_have_populated_dt())
299 return;
300
301 dtb_setup_hpet();
302 dtb_apic_setup();
303}