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1/*
2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41#include <linux/slab.h>
42#include "pm8001_sas.h"
43#include "pm8001_chips.h"
44
45static struct scsi_transport_template *pm8001_stt;
46
47/**
48 * chip info structure to identify chip key functionality as
49 * encryption available/not, no of ports, hw specific function ref
50 */
51static const struct pm8001_chip_info pm8001_chips[] = {
52 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
53 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
54 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
55 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
56 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
57 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
58 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
59 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
60 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,},
61 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,},
62 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,},
63};
64static int pm8001_id;
65
66LIST_HEAD(hba_list);
67
68struct workqueue_struct *pm8001_wq;
69
70/**
71 * The main structure which LLDD must register for scsi core.
72 */
73static struct scsi_host_template pm8001_sht = {
74 .module = THIS_MODULE,
75 .name = DRV_NAME,
76 .queuecommand = sas_queuecommand,
77 .target_alloc = sas_target_alloc,
78 .slave_configure = sas_slave_configure,
79 .scan_finished = pm8001_scan_finished,
80 .scan_start = pm8001_scan_start,
81 .change_queue_depth = sas_change_queue_depth,
82 .bios_param = sas_bios_param,
83 .can_queue = 1,
84 .this_id = -1,
85 .sg_tablesize = SG_ALL,
86 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
87 .use_clustering = ENABLE_CLUSTERING,
88 .eh_device_reset_handler = sas_eh_device_reset_handler,
89 .eh_bus_reset_handler = sas_eh_bus_reset_handler,
90 .target_destroy = sas_target_destroy,
91 .ioctl = sas_ioctl,
92 .shost_attrs = pm8001_host_attrs,
93 .track_queue_depth = 1,
94};
95
96/**
97 * Sas layer call this function to execute specific task.
98 */
99static struct sas_domain_function_template pm8001_transport_ops = {
100 .lldd_dev_found = pm8001_dev_found,
101 .lldd_dev_gone = pm8001_dev_gone,
102
103 .lldd_execute_task = pm8001_queue_command,
104 .lldd_control_phy = pm8001_phy_control,
105
106 .lldd_abort_task = pm8001_abort_task,
107 .lldd_abort_task_set = pm8001_abort_task_set,
108 .lldd_clear_aca = pm8001_clear_aca,
109 .lldd_clear_task_set = pm8001_clear_task_set,
110 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
111 .lldd_lu_reset = pm8001_lu_reset,
112 .lldd_query_task = pm8001_query_task,
113};
114
115/**
116 *pm8001_phy_init - initiate our adapter phys
117 *@pm8001_ha: our hba structure.
118 *@phy_id: phy id.
119 */
120static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
121{
122 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
123 struct asd_sas_phy *sas_phy = &phy->sas_phy;
124 phy->phy_state = 0;
125 phy->pm8001_ha = pm8001_ha;
126 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
127 sas_phy->class = SAS;
128 sas_phy->iproto = SAS_PROTOCOL_ALL;
129 sas_phy->tproto = 0;
130 sas_phy->type = PHY_TYPE_PHYSICAL;
131 sas_phy->role = PHY_ROLE_INITIATOR;
132 sas_phy->oob_mode = OOB_NOT_CONNECTED;
133 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
134 sas_phy->id = phy_id;
135 sas_phy->sas_addr = &pm8001_ha->sas_addr[0];
136 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
137 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
138 sas_phy->lldd_phy = phy;
139}
140
141/**
142 *pm8001_free - free hba
143 *@pm8001_ha: our hba structure.
144 *
145 */
146static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
147{
148 int i;
149
150 if (!pm8001_ha)
151 return;
152
153 for (i = 0; i < USI_MAX_MEMCNT; i++) {
154 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
155 pci_free_consistent(pm8001_ha->pdev,
156 (pm8001_ha->memoryMap.region[i].total_len +
157 pm8001_ha->memoryMap.region[i].alignment),
158 pm8001_ha->memoryMap.region[i].virt_ptr,
159 pm8001_ha->memoryMap.region[i].phys_addr);
160 }
161 }
162 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
163 if (pm8001_ha->shost)
164 scsi_host_put(pm8001_ha->shost);
165 flush_workqueue(pm8001_wq);
166 kfree(pm8001_ha->tags);
167 kfree(pm8001_ha);
168}
169
170#ifdef PM8001_USE_TASKLET
171
172/**
173 * tasklet for 64 msi-x interrupt handler
174 * @opaque: the passed general host adapter struct
175 * Note: pm8001_tasklet is common for pm8001 & pm80xx
176 */
177static void pm8001_tasklet(unsigned long opaque)
178{
179 struct pm8001_hba_info *pm8001_ha;
180 struct isr_param *irq_vector;
181
182 irq_vector = (struct isr_param *)opaque;
183 pm8001_ha = irq_vector->drv_inst;
184 if (unlikely(!pm8001_ha))
185 BUG_ON(1);
186 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
187}
188#endif
189
190/**
191 * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
192 * It obtains the vector number and calls the equivalent bottom
193 * half or services directly.
194 * @opaque: the passed outbound queue/vector. Host structure is
195 * retrieved from the same.
196 */
197static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
198{
199 struct isr_param *irq_vector;
200 struct pm8001_hba_info *pm8001_ha;
201 irqreturn_t ret = IRQ_HANDLED;
202 irq_vector = (struct isr_param *)opaque;
203 pm8001_ha = irq_vector->drv_inst;
204
205 if (unlikely(!pm8001_ha))
206 return IRQ_NONE;
207 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
208 return IRQ_NONE;
209#ifdef PM8001_USE_TASKLET
210 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
211#else
212 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
213#endif
214 return ret;
215}
216
217/**
218 * pm8001_interrupt_handler_intx - main INTx interrupt handler.
219 * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
220 */
221
222static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
223{
224 struct pm8001_hba_info *pm8001_ha;
225 irqreturn_t ret = IRQ_HANDLED;
226 struct sas_ha_struct *sha = dev_id;
227 pm8001_ha = sha->lldd_ha;
228 if (unlikely(!pm8001_ha))
229 return IRQ_NONE;
230 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
231 return IRQ_NONE;
232
233#ifdef PM8001_USE_TASKLET
234 tasklet_schedule(&pm8001_ha->tasklet[0]);
235#else
236 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
237#endif
238 return ret;
239}
240
241/**
242 * pm8001_alloc - initiate our hba structure and 6 DMAs area.
243 * @pm8001_ha:our hba structure.
244 *
245 */
246static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
247 const struct pci_device_id *ent)
248{
249 int i;
250 spin_lock_init(&pm8001_ha->lock);
251 spin_lock_init(&pm8001_ha->bitmap_lock);
252 PM8001_INIT_DBG(pm8001_ha,
253 pm8001_printk("pm8001_alloc: PHY:%x\n",
254 pm8001_ha->chip->n_phy));
255 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
256 pm8001_phy_init(pm8001_ha, i);
257 pm8001_ha->port[i].wide_port_phymap = 0;
258 pm8001_ha->port[i].port_attached = 0;
259 pm8001_ha->port[i].port_state = 0;
260 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
261 }
262
263 pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
264 if (!pm8001_ha->tags)
265 goto err_out;
266 /* MPI Memory region 1 for AAP Event Log for fw */
267 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
268 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
269 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
270 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
271
272 /* MPI Memory region 2 for IOP Event Log for fw */
273 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
274 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
275 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
276 pm8001_ha->memoryMap.region[IOP].alignment = 32;
277
278 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
279 /* MPI Memory region 3 for consumer Index of inbound queues */
280 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
281 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
282 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
283 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
284
285 if ((ent->driver_data) != chip_8001) {
286 /* MPI Memory region 5 inbound queues */
287 pm8001_ha->memoryMap.region[IB+i].num_elements =
288 PM8001_MPI_QUEUE;
289 pm8001_ha->memoryMap.region[IB+i].element_size = 128;
290 pm8001_ha->memoryMap.region[IB+i].total_len =
291 PM8001_MPI_QUEUE * 128;
292 pm8001_ha->memoryMap.region[IB+i].alignment = 128;
293 } else {
294 pm8001_ha->memoryMap.region[IB+i].num_elements =
295 PM8001_MPI_QUEUE;
296 pm8001_ha->memoryMap.region[IB+i].element_size = 64;
297 pm8001_ha->memoryMap.region[IB+i].total_len =
298 PM8001_MPI_QUEUE * 64;
299 pm8001_ha->memoryMap.region[IB+i].alignment = 64;
300 }
301 }
302
303 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
304 /* MPI Memory region 4 for producer Index of outbound queues */
305 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
306 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
307 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
308 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
309
310 if (ent->driver_data != chip_8001) {
311 /* MPI Memory region 6 Outbound queues */
312 pm8001_ha->memoryMap.region[OB+i].num_elements =
313 PM8001_MPI_QUEUE;
314 pm8001_ha->memoryMap.region[OB+i].element_size = 128;
315 pm8001_ha->memoryMap.region[OB+i].total_len =
316 PM8001_MPI_QUEUE * 128;
317 pm8001_ha->memoryMap.region[OB+i].alignment = 128;
318 } else {
319 /* MPI Memory region 6 Outbound queues */
320 pm8001_ha->memoryMap.region[OB+i].num_elements =
321 PM8001_MPI_QUEUE;
322 pm8001_ha->memoryMap.region[OB+i].element_size = 64;
323 pm8001_ha->memoryMap.region[OB+i].total_len =
324 PM8001_MPI_QUEUE * 64;
325 pm8001_ha->memoryMap.region[OB+i].alignment = 64;
326 }
327
328 }
329 /* Memory region write DMA*/
330 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
331 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
332 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
333 /* Memory region for devices*/
334 pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
335 pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
336 sizeof(struct pm8001_device);
337 pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
338 sizeof(struct pm8001_device);
339
340 /* Memory region for ccb_info*/
341 pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
342 pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
343 sizeof(struct pm8001_ccb_info);
344 pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
345 sizeof(struct pm8001_ccb_info);
346
347 /* Memory region for fw flash */
348 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
349
350 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
351 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
352 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
353 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
354 for (i = 0; i < USI_MAX_MEMCNT; i++) {
355 if (pm8001_mem_alloc(pm8001_ha->pdev,
356 &pm8001_ha->memoryMap.region[i].virt_ptr,
357 &pm8001_ha->memoryMap.region[i].phys_addr,
358 &pm8001_ha->memoryMap.region[i].phys_addr_hi,
359 &pm8001_ha->memoryMap.region[i].phys_addr_lo,
360 pm8001_ha->memoryMap.region[i].total_len,
361 pm8001_ha->memoryMap.region[i].alignment) != 0) {
362 PM8001_FAIL_DBG(pm8001_ha,
363 pm8001_printk("Mem%d alloc failed\n",
364 i));
365 goto err_out;
366 }
367 }
368
369 pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
370 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
371 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
372 pm8001_ha->devices[i].id = i;
373 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
374 pm8001_ha->devices[i].running_req = 0;
375 }
376 pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
377 for (i = 0; i < PM8001_MAX_CCB; i++) {
378 pm8001_ha->ccb_info[i].ccb_dma_handle =
379 pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
380 i * sizeof(struct pm8001_ccb_info);
381 pm8001_ha->ccb_info[i].task = NULL;
382 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
383 pm8001_ha->ccb_info[i].device = NULL;
384 ++pm8001_ha->tags_num;
385 }
386 pm8001_ha->flags = PM8001F_INIT_TIME;
387 /* Initialize tags */
388 pm8001_tag_init(pm8001_ha);
389 return 0;
390err_out:
391 return 1;
392}
393
394/**
395 * pm8001_ioremap - remap the pci high physical address to kernal virtual
396 * address so that we can access them.
397 * @pm8001_ha:our hba structure.
398 */
399static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
400{
401 u32 bar;
402 u32 logicalBar = 0;
403 struct pci_dev *pdev;
404
405 pdev = pm8001_ha->pdev;
406 /* map pci mem (PMC pci base 0-3)*/
407 for (bar = 0; bar < 6; bar++) {
408 /*
409 ** logical BARs for SPC:
410 ** bar 0 and 1 - logical BAR0
411 ** bar 2 and 3 - logical BAR1
412 ** bar4 - logical BAR2
413 ** bar5 - logical BAR3
414 ** Skip the appropriate assignments:
415 */
416 if ((bar == 1) || (bar == 3))
417 continue;
418 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
419 pm8001_ha->io_mem[logicalBar].membase =
420 pci_resource_start(pdev, bar);
421 pm8001_ha->io_mem[logicalBar].memsize =
422 pci_resource_len(pdev, bar);
423 pm8001_ha->io_mem[logicalBar].memvirtaddr =
424 ioremap(pm8001_ha->io_mem[logicalBar].membase,
425 pm8001_ha->io_mem[logicalBar].memsize);
426 PM8001_INIT_DBG(pm8001_ha,
427 pm8001_printk("PCI: bar %d, logicalBar %d ",
428 bar, logicalBar));
429 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
430 "base addr %llx virt_addr=%llx len=%d\n",
431 (u64)pm8001_ha->io_mem[logicalBar].membase,
432 (u64)(unsigned long)
433 pm8001_ha->io_mem[logicalBar].memvirtaddr,
434 pm8001_ha->io_mem[logicalBar].memsize));
435 } else {
436 pm8001_ha->io_mem[logicalBar].membase = 0;
437 pm8001_ha->io_mem[logicalBar].memsize = 0;
438 pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
439 }
440 logicalBar++;
441 }
442 return 0;
443}
444
445/**
446 * pm8001_pci_alloc - initialize our ha card structure
447 * @pdev: pci device.
448 * @ent: ent
449 * @shost: scsi host struct which has been initialized before.
450 */
451static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
452 const struct pci_device_id *ent,
453 struct Scsi_Host *shost)
454
455{
456 struct pm8001_hba_info *pm8001_ha;
457 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
458 int j;
459
460 pm8001_ha = sha->lldd_ha;
461 if (!pm8001_ha)
462 return NULL;
463
464 pm8001_ha->pdev = pdev;
465 pm8001_ha->dev = &pdev->dev;
466 pm8001_ha->chip_id = ent->driver_data;
467 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
468 pm8001_ha->irq = pdev->irq;
469 pm8001_ha->sas = sha;
470 pm8001_ha->shost = shost;
471 pm8001_ha->id = pm8001_id++;
472 pm8001_ha->logging_level = 0x01;
473 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
474 /* IOMB size is 128 for 8088/89 controllers */
475 if (pm8001_ha->chip_id != chip_8001)
476 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
477 else
478 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
479
480#ifdef PM8001_USE_TASKLET
481 /* Tasklet for non msi-x interrupt handler */
482 if ((!pdev->msix_cap || !pci_msi_enabled())
483 || (pm8001_ha->chip_id == chip_8001))
484 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
485 (unsigned long)&(pm8001_ha->irq_vector[0]));
486 else
487 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
488 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
489 (unsigned long)&(pm8001_ha->irq_vector[j]));
490#endif
491 pm8001_ioremap(pm8001_ha);
492 if (!pm8001_alloc(pm8001_ha, ent))
493 return pm8001_ha;
494 pm8001_free(pm8001_ha);
495 return NULL;
496}
497
498/**
499 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
500 * @pdev: pci device.
501 */
502static int pci_go_44(struct pci_dev *pdev)
503{
504 int rc;
505
506 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) {
507 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44));
508 if (rc) {
509 rc = pci_set_consistent_dma_mask(pdev,
510 DMA_BIT_MASK(32));
511 if (rc) {
512 dev_printk(KERN_ERR, &pdev->dev,
513 "44-bit DMA enable failed\n");
514 return rc;
515 }
516 }
517 } else {
518 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
519 if (rc) {
520 dev_printk(KERN_ERR, &pdev->dev,
521 "32-bit DMA enable failed\n");
522 return rc;
523 }
524 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
525 if (rc) {
526 dev_printk(KERN_ERR, &pdev->dev,
527 "32-bit consistent DMA enable failed\n");
528 return rc;
529 }
530 }
531 return rc;
532}
533
534/**
535 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
536 * @shost: scsi host which has been allocated outside.
537 * @chip_info: our ha struct.
538 */
539static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
540 const struct pm8001_chip_info *chip_info)
541{
542 int phy_nr, port_nr;
543 struct asd_sas_phy **arr_phy;
544 struct asd_sas_port **arr_port;
545 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
546
547 phy_nr = chip_info->n_phy;
548 port_nr = phy_nr;
549 memset(sha, 0x00, sizeof(*sha));
550 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
551 if (!arr_phy)
552 goto exit;
553 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
554 if (!arr_port)
555 goto exit_free2;
556
557 sha->sas_phy = arr_phy;
558 sha->sas_port = arr_port;
559 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
560 if (!sha->lldd_ha)
561 goto exit_free1;
562
563 shost->transportt = pm8001_stt;
564 shost->max_id = PM8001_MAX_DEVICES;
565 shost->max_lun = 8;
566 shost->max_channel = 0;
567 shost->unique_id = pm8001_id;
568 shost->max_cmd_len = 16;
569 shost->can_queue = PM8001_CAN_QUEUE;
570 shost->cmd_per_lun = 32;
571 return 0;
572exit_free1:
573 kfree(arr_port);
574exit_free2:
575 kfree(arr_phy);
576exit:
577 return -1;
578}
579
580/**
581 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
582 * @shost: scsi host which has been allocated outside
583 * @chip_info: our ha struct.
584 */
585static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
586 const struct pm8001_chip_info *chip_info)
587{
588 int i = 0;
589 struct pm8001_hba_info *pm8001_ha;
590 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
591
592 pm8001_ha = sha->lldd_ha;
593 for (i = 0; i < chip_info->n_phy; i++) {
594 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
595 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
596 }
597 sha->sas_ha_name = DRV_NAME;
598 sha->dev = pm8001_ha->dev;
599
600 sha->lldd_module = THIS_MODULE;
601 sha->sas_addr = &pm8001_ha->sas_addr[0];
602 sha->num_phys = chip_info->n_phy;
603 sha->core.shost = shost;
604}
605
606/**
607 * pm8001_init_sas_add - initialize sas address
608 * @chip_info: our ha struct.
609 *
610 * Currently we just set the fixed SAS address to our HBA,for manufacture,
611 * it should read from the EEPROM
612 */
613static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
614{
615 u8 i, j;
616#ifdef PM8001_READ_VPD
617 /* For new SPC controllers WWN is stored in flash vpd
618 * For SPC/SPCve controllers WWN is stored in EEPROM
619 * For Older SPC WWN is stored in NVMD
620 */
621 DECLARE_COMPLETION_ONSTACK(completion);
622 struct pm8001_ioctl_payload payload;
623 u16 deviceid;
624 int rc;
625
626 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
627 pm8001_ha->nvmd_completion = &completion;
628
629 if (pm8001_ha->chip_id == chip_8001) {
630 if (deviceid == 0x8081 || deviceid == 0x0042) {
631 payload.minor_function = 4;
632 payload.length = 4096;
633 } else {
634 payload.minor_function = 0;
635 payload.length = 128;
636 }
637 } else if ((pm8001_ha->chip_id == chip_8070 ||
638 pm8001_ha->chip_id == chip_8072) &&
639 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
640 payload.minor_function = 4;
641 payload.length = 4096;
642 } else {
643 payload.minor_function = 1;
644 payload.length = 4096;
645 }
646 payload.offset = 0;
647 payload.func_specific = kzalloc(payload.length, GFP_KERNEL);
648 if (!payload.func_specific) {
649 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n"));
650 return;
651 }
652 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
653 if (rc) {
654 kfree(payload.func_specific);
655 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
656 return;
657 }
658 wait_for_completion(&completion);
659
660 for (i = 0, j = 0; i <= 7; i++, j++) {
661 if (pm8001_ha->chip_id == chip_8001) {
662 if (deviceid == 0x8081)
663 pm8001_ha->sas_addr[j] =
664 payload.func_specific[0x704 + i];
665 else if (deviceid == 0x0042)
666 pm8001_ha->sas_addr[j] =
667 payload.func_specific[0x010 + i];
668 } else if ((pm8001_ha->chip_id == chip_8070 ||
669 pm8001_ha->chip_id == chip_8072) &&
670 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
671 pm8001_ha->sas_addr[j] =
672 payload.func_specific[0x010 + i];
673 } else
674 pm8001_ha->sas_addr[j] =
675 payload.func_specific[0x804 + i];
676 }
677
678 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
679 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
680 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
681 PM8001_INIT_DBG(pm8001_ha,
682 pm8001_printk("phy %d sas_addr = %016llx\n", i,
683 pm8001_ha->phy[i].dev_sas_addr));
684 }
685 kfree(payload.func_specific);
686#else
687 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
688 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
689 pm8001_ha->phy[i].dev_sas_addr =
690 cpu_to_be64((u64)
691 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
692 }
693 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
694 SAS_ADDR_SIZE);
695#endif
696}
697
698/*
699 * pm8001_get_phy_settings_info : Read phy setting values.
700 * @pm8001_ha : our hba.
701 */
702static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
703{
704
705#ifdef PM8001_READ_VPD
706 /*OPTION ROM FLASH read for the SPC cards */
707 DECLARE_COMPLETION_ONSTACK(completion);
708 struct pm8001_ioctl_payload payload;
709 int rc;
710
711 pm8001_ha->nvmd_completion = &completion;
712 /* SAS ADDRESS read from flash / EEPROM */
713 payload.minor_function = 6;
714 payload.offset = 0;
715 payload.length = 4096;
716 payload.func_specific = kzalloc(4096, GFP_KERNEL);
717 if (!payload.func_specific)
718 return -ENOMEM;
719 /* Read phy setting values from flash */
720 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
721 if (rc) {
722 kfree(payload.func_specific);
723 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
724 return -ENOMEM;
725 }
726 wait_for_completion(&completion);
727 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
728 kfree(payload.func_specific);
729#endif
730 return 0;
731}
732
733struct pm8001_mpi3_phy_pg_trx_config {
734 u32 LaneLosCfg;
735 u32 LanePgaCfg1;
736 u32 LanePisoCfg1;
737 u32 LanePisoCfg2;
738 u32 LanePisoCfg3;
739 u32 LanePisoCfg4;
740 u32 LanePisoCfg5;
741 u32 LanePisoCfg6;
742 u32 LaneBctCtrl;
743};
744
745/**
746 * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings
747 * @pm8001_ha : our adapter
748 * @phycfg : PHY config page to populate
749 */
750static
751void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
752 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
753{
754 phycfg->LaneLosCfg = 0x00000132;
755 phycfg->LanePgaCfg1 = 0x00203949;
756 phycfg->LanePisoCfg1 = 0x000000FF;
757 phycfg->LanePisoCfg2 = 0xFF000001;
758 phycfg->LanePisoCfg3 = 0xE7011300;
759 phycfg->LanePisoCfg4 = 0x631C40C0;
760 phycfg->LanePisoCfg5 = 0xF8102036;
761 phycfg->LanePisoCfg6 = 0xF74A1000;
762 phycfg->LaneBctCtrl = 0x00FB33F8;
763}
764
765/**
766 * pm8001_get_external_phy_settings : Retrieves the external PHY settings
767 * @pm8001_ha : our adapter
768 * @phycfg : PHY config page to populate
769 */
770static
771void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
772 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
773{
774 phycfg->LaneLosCfg = 0x00000132;
775 phycfg->LanePgaCfg1 = 0x00203949;
776 phycfg->LanePisoCfg1 = 0x000000FF;
777 phycfg->LanePisoCfg2 = 0xFF000001;
778 phycfg->LanePisoCfg3 = 0xE7011300;
779 phycfg->LanePisoCfg4 = 0x63349140;
780 phycfg->LanePisoCfg5 = 0xF8102036;
781 phycfg->LanePisoCfg6 = 0xF80D9300;
782 phycfg->LaneBctCtrl = 0x00FB33F8;
783}
784
785/**
786 * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext
787 * @pm8001_ha : our adapter
788 * @phymask : The PHY mask
789 */
790static
791void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
792{
793 switch (pm8001_ha->pdev->subsystem_device) {
794 case 0x0070: /* H1280 - 8 external 0 internal */
795 case 0x0072: /* H12F0 - 16 external 0 internal */
796 *phymask = 0x0000;
797 break;
798
799 case 0x0071: /* H1208 - 0 external 8 internal */
800 case 0x0073: /* H120F - 0 external 16 internal */
801 *phymask = 0xFFFF;
802 break;
803
804 case 0x0080: /* H1244 - 4 external 4 internal */
805 *phymask = 0x00F0;
806 break;
807
808 case 0x0081: /* H1248 - 4 external 8 internal */
809 *phymask = 0x0FF0;
810 break;
811
812 case 0x0082: /* H1288 - 8 external 8 internal */
813 *phymask = 0xFF00;
814 break;
815
816 default:
817 PM8001_INIT_DBG(pm8001_ha,
818 pm8001_printk("Unknown subsystem device=0x%.04x",
819 pm8001_ha->pdev->subsystem_device));
820 }
821}
822
823/**
824 * pm8001_set_phy_settings_ven_117c_12Gb : Configure ATTO 12Gb PHY settings
825 * @pm8001_ha : our adapter
826 */
827static
828int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
829{
830 struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
831 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
832 int phymask = 0;
833 int i = 0;
834
835 memset(&phycfg_int, 0, sizeof(phycfg_int));
836 memset(&phycfg_ext, 0, sizeof(phycfg_ext));
837
838 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
839 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
840 pm8001_get_phy_mask(pm8001_ha, &phymask);
841
842 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
843 if (phymask & (1 << i)) {/* Internal PHY */
844 pm8001_set_phy_profile_single(pm8001_ha, i,
845 sizeof(phycfg_int) / sizeof(u32),
846 (u32 *)&phycfg_int);
847
848 } else { /* External PHY */
849 pm8001_set_phy_profile_single(pm8001_ha, i,
850 sizeof(phycfg_ext) / sizeof(u32),
851 (u32 *)&phycfg_ext);
852 }
853 }
854
855 return 0;
856}
857
858/**
859 * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID.
860 * @pm8001_ha : our hba.
861 */
862static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
863{
864 switch (pm8001_ha->pdev->subsystem_vendor) {
865 case PCI_VENDOR_ID_ATTO:
866 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
867 return 0;
868 else
869 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
870
871 case PCI_VENDOR_ID_ADAPTEC2:
872 case 0:
873 return 0;
874
875 default:
876 return pm8001_get_phy_settings_info(pm8001_ha);
877 }
878}
879
880#ifdef PM8001_USE_MSIX
881/**
882 * pm8001_setup_msix - enable MSI-X interrupt
883 * @chip_info: our ha struct.
884 * @irq_handler: irq_handler
885 */
886static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
887{
888 u32 i = 0, j = 0;
889 u32 number_of_intr;
890 int flag = 0;
891 u32 max_entry;
892 int rc;
893 static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3];
894
895 /* SPCv controllers supports 64 msi-x */
896 if (pm8001_ha->chip_id == chip_8001) {
897 number_of_intr = 1;
898 } else {
899 number_of_intr = PM8001_MAX_MSIX_VEC;
900 flag &= ~IRQF_SHARED;
901 }
902
903 max_entry = sizeof(pm8001_ha->msix_entries) /
904 sizeof(pm8001_ha->msix_entries[0]);
905 for (i = 0; i < max_entry ; i++)
906 pm8001_ha->msix_entries[i].entry = i;
907 rc = pci_enable_msix_exact(pm8001_ha->pdev, pm8001_ha->msix_entries,
908 number_of_intr);
909 pm8001_ha->number_of_intr = number_of_intr;
910 if (rc)
911 return rc;
912
913 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
914 "pci_enable_msix_exact request ret:%d no of intr %d\n",
915 rc, pm8001_ha->number_of_intr));
916
917 for (i = 0; i < number_of_intr; i++) {
918 snprintf(intr_drvname[i], sizeof(intr_drvname[0]),
919 DRV_NAME"%d", i);
920 pm8001_ha->irq_vector[i].irq_id = i;
921 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
922
923 rc = request_irq(pm8001_ha->msix_entries[i].vector,
924 pm8001_interrupt_handler_msix, flag,
925 intr_drvname[i], &(pm8001_ha->irq_vector[i]));
926 if (rc) {
927 for (j = 0; j < i; j++) {
928 free_irq(pm8001_ha->msix_entries[j].vector,
929 &(pm8001_ha->irq_vector[i]));
930 }
931 pci_disable_msix(pm8001_ha->pdev);
932 break;
933 }
934 }
935
936 return rc;
937}
938#endif
939
940/**
941 * pm8001_request_irq - register interrupt
942 * @chip_info: our ha struct.
943 */
944static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
945{
946 struct pci_dev *pdev;
947 int rc;
948
949 pdev = pm8001_ha->pdev;
950
951#ifdef PM8001_USE_MSIX
952 if (pdev->msix_cap && pci_msi_enabled())
953 return pm8001_setup_msix(pm8001_ha);
954 else {
955 PM8001_INIT_DBG(pm8001_ha,
956 pm8001_printk("MSIX not supported!!!\n"));
957 goto intx;
958 }
959#endif
960
961intx:
962 /* initialize the INT-X interrupt */
963 pm8001_ha->irq_vector[0].irq_id = 0;
964 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
965 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
966 DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost));
967 return rc;
968}
969
970/**
971 * pm8001_pci_probe - probe supported device
972 * @pdev: pci device which kernel has been prepared for.
973 * @ent: pci device id
974 *
975 * This function is the main initialization function, when register a new
976 * pci driver it is invoked, all struct an hardware initilization should be done
977 * here, also, register interrupt
978 */
979static int pm8001_pci_probe(struct pci_dev *pdev,
980 const struct pci_device_id *ent)
981{
982 unsigned int rc;
983 u32 pci_reg;
984 u8 i = 0;
985 struct pm8001_hba_info *pm8001_ha;
986 struct Scsi_Host *shost = NULL;
987 const struct pm8001_chip_info *chip;
988
989 dev_printk(KERN_INFO, &pdev->dev,
990 "pm80xx: driver version %s\n", DRV_VERSION);
991 rc = pci_enable_device(pdev);
992 if (rc)
993 goto err_out_enable;
994 pci_set_master(pdev);
995 /*
996 * Enable pci slot busmaster by setting pci command register.
997 * This is required by FW for Cyclone card.
998 */
999
1000 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1001 pci_reg |= 0x157;
1002 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1003 rc = pci_request_regions(pdev, DRV_NAME);
1004 if (rc)
1005 goto err_out_disable;
1006 rc = pci_go_44(pdev);
1007 if (rc)
1008 goto err_out_regions;
1009
1010 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1011 if (!shost) {
1012 rc = -ENOMEM;
1013 goto err_out_regions;
1014 }
1015 chip = &pm8001_chips[ent->driver_data];
1016 SHOST_TO_SAS_HA(shost) =
1017 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1018 if (!SHOST_TO_SAS_HA(shost)) {
1019 rc = -ENOMEM;
1020 goto err_out_free_host;
1021 }
1022
1023 rc = pm8001_prep_sas_ha_init(shost, chip);
1024 if (rc) {
1025 rc = -ENOMEM;
1026 goto err_out_free;
1027 }
1028 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1029 /* ent->driver variable is used to differentiate between controllers */
1030 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1031 if (!pm8001_ha) {
1032 rc = -ENOMEM;
1033 goto err_out_free;
1034 }
1035 list_add_tail(&pm8001_ha->list, &hba_list);
1036 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1037 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1038 if (rc) {
1039 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1040 "chip_init failed [ret: %d]\n", rc));
1041 goto err_out_ha_free;
1042 }
1043
1044 rc = scsi_add_host(shost, &pdev->dev);
1045 if (rc)
1046 goto err_out_ha_free;
1047 rc = pm8001_request_irq(pm8001_ha);
1048 if (rc) {
1049 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1050 "pm8001_request_irq failed [ret: %d]\n", rc));
1051 goto err_out_shost;
1052 }
1053
1054 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1055 if (pm8001_ha->chip_id != chip_8001) {
1056 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1057 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1058 /* setup thermal configuration. */
1059 pm80xx_set_thermal_config(pm8001_ha);
1060 }
1061
1062 pm8001_init_sas_add(pm8001_ha);
1063 /* phy setting support for motherboard controller */
1064 if (pm8001_configure_phy_settings(pm8001_ha))
1065 goto err_out_shost;
1066
1067 pm8001_post_sas_ha_init(shost, chip);
1068 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1069 if (rc)
1070 goto err_out_shost;
1071 scsi_scan_host(pm8001_ha->shost);
1072 return 0;
1073
1074err_out_shost:
1075 scsi_remove_host(pm8001_ha->shost);
1076err_out_ha_free:
1077 pm8001_free(pm8001_ha);
1078err_out_free:
1079 kfree(SHOST_TO_SAS_HA(shost));
1080err_out_free_host:
1081 kfree(shost);
1082err_out_regions:
1083 pci_release_regions(pdev);
1084err_out_disable:
1085 pci_disable_device(pdev);
1086err_out_enable:
1087 return rc;
1088}
1089
1090static void pm8001_pci_remove(struct pci_dev *pdev)
1091{
1092 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1093 struct pm8001_hba_info *pm8001_ha;
1094 int i, j;
1095 pm8001_ha = sha->lldd_ha;
1096 scsi_remove_host(pm8001_ha->shost);
1097 sas_unregister_ha(sha);
1098 sas_remove_host(pm8001_ha->shost);
1099 list_del(&pm8001_ha->list);
1100 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1101 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1102
1103#ifdef PM8001_USE_MSIX
1104 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1105 synchronize_irq(pm8001_ha->msix_entries[i].vector);
1106 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1107 free_irq(pm8001_ha->msix_entries[i].vector,
1108 &(pm8001_ha->irq_vector[i]));
1109 pci_disable_msix(pdev);
1110#else
1111 free_irq(pm8001_ha->irq, sha);
1112#endif
1113#ifdef PM8001_USE_TASKLET
1114 /* For non-msix and msix interrupts */
1115 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1116 (pm8001_ha->chip_id == chip_8001))
1117 tasklet_kill(&pm8001_ha->tasklet[0]);
1118 else
1119 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1120 tasklet_kill(&pm8001_ha->tasklet[j]);
1121#endif
1122 pm8001_free(pm8001_ha);
1123 kfree(sha->sas_phy);
1124 kfree(sha->sas_port);
1125 kfree(sha);
1126 pci_release_regions(pdev);
1127 pci_disable_device(pdev);
1128}
1129
1130/**
1131 * pm8001_pci_suspend - power management suspend main entry point
1132 * @pdev: PCI device struct
1133 * @state: PM state change to (usually PCI_D3)
1134 *
1135 * Returns 0 success, anything else error.
1136 */
1137static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1138{
1139 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1140 struct pm8001_hba_info *pm8001_ha;
1141 int i, j;
1142 u32 device_state;
1143 pm8001_ha = sha->lldd_ha;
1144 sas_suspend_ha(sha);
1145 flush_workqueue(pm8001_wq);
1146 scsi_block_requests(pm8001_ha->shost);
1147 if (!pdev->pm_cap) {
1148 dev_err(&pdev->dev, " PCI PM not supported\n");
1149 return -ENODEV;
1150 }
1151 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1152 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1153#ifdef PM8001_USE_MSIX
1154 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1155 synchronize_irq(pm8001_ha->msix_entries[i].vector);
1156 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1157 free_irq(pm8001_ha->msix_entries[i].vector,
1158 &(pm8001_ha->irq_vector[i]));
1159 pci_disable_msix(pdev);
1160#else
1161 free_irq(pm8001_ha->irq, sha);
1162#endif
1163#ifdef PM8001_USE_TASKLET
1164 /* For non-msix and msix interrupts */
1165 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1166 (pm8001_ha->chip_id == chip_8001))
1167 tasklet_kill(&pm8001_ha->tasklet[0]);
1168 else
1169 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1170 tasklet_kill(&pm8001_ha->tasklet[j]);
1171#endif
1172 device_state = pci_choose_state(pdev, state);
1173 pm8001_printk("pdev=0x%p, slot=%s, entering "
1174 "operating state [D%d]\n", pdev,
1175 pm8001_ha->name, device_state);
1176 pci_save_state(pdev);
1177 pci_disable_device(pdev);
1178 pci_set_power_state(pdev, device_state);
1179 return 0;
1180}
1181
1182/**
1183 * pm8001_pci_resume - power management resume main entry point
1184 * @pdev: PCI device struct
1185 *
1186 * Returns 0 success, anything else error.
1187 */
1188static int pm8001_pci_resume(struct pci_dev *pdev)
1189{
1190 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1191 struct pm8001_hba_info *pm8001_ha;
1192 int rc;
1193 u8 i = 0, j;
1194 u32 device_state;
1195 DECLARE_COMPLETION_ONSTACK(completion);
1196 pm8001_ha = sha->lldd_ha;
1197 device_state = pdev->current_state;
1198
1199 pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1200 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1201
1202 pci_set_power_state(pdev, PCI_D0);
1203 pci_enable_wake(pdev, PCI_D0, 0);
1204 pci_restore_state(pdev);
1205 rc = pci_enable_device(pdev);
1206 if (rc) {
1207 pm8001_printk("slot=%s Enable device failed during resume\n",
1208 pm8001_ha->name);
1209 goto err_out_enable;
1210 }
1211
1212 pci_set_master(pdev);
1213 rc = pci_go_44(pdev);
1214 if (rc)
1215 goto err_out_disable;
1216 sas_prep_resume_ha(sha);
1217 /* chip soft rst only for spc */
1218 if (pm8001_ha->chip_id == chip_8001) {
1219 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1220 PM8001_INIT_DBG(pm8001_ha,
1221 pm8001_printk("chip soft reset successful\n"));
1222 }
1223 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1224 if (rc)
1225 goto err_out_disable;
1226
1227 /* disable all the interrupt bits */
1228 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1229
1230 rc = pm8001_request_irq(pm8001_ha);
1231 if (rc)
1232 goto err_out_disable;
1233#ifdef PM8001_USE_TASKLET
1234 /* Tasklet for non msi-x interrupt handler */
1235 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1236 (pm8001_ha->chip_id == chip_8001))
1237 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1238 (unsigned long)&(pm8001_ha->irq_vector[0]));
1239 else
1240 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1241 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1242 (unsigned long)&(pm8001_ha->irq_vector[j]));
1243#endif
1244 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1245 if (pm8001_ha->chip_id != chip_8001) {
1246 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1247 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1248 }
1249
1250 /* Chip documentation for the 8070 and 8072 SPCv */
1251 /* states that a 500ms minimum delay is required */
1252 /* before issuing commands. Otherwise, the firmware */
1253 /* will enter an unrecoverable state. */
1254
1255 if (pm8001_ha->chip_id == chip_8070 ||
1256 pm8001_ha->chip_id == chip_8072) {
1257 mdelay(500);
1258 }
1259
1260 /* Spin up the PHYs */
1261
1262 pm8001_ha->flags = PM8001F_RUN_TIME;
1263 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1264 pm8001_ha->phy[i].enable_completion = &completion;
1265 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1266 wait_for_completion(&completion);
1267 }
1268 sas_resume_ha(sha);
1269 return 0;
1270
1271err_out_disable:
1272 scsi_remove_host(pm8001_ha->shost);
1273 pci_disable_device(pdev);
1274err_out_enable:
1275 return rc;
1276}
1277
1278/* update of pci device, vendor id and driver data with
1279 * unique value for each of the controller
1280 */
1281static struct pci_device_id pm8001_pci_table[] = {
1282 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1283 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1284 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1285 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1286 /* Support for SPC/SPCv/SPCve controllers */
1287 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1288 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1289 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1290 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1291 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1292 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1293 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1294 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1295 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1296 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1297 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1298 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1299 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1300 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1301 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1302 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1303 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1304 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1305 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1306 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1307 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1308 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1309 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1310 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1311 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1312 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1313 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1314 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1315 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1316 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1317 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1318 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1319 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1320 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1321 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1322 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1323 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1324 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1325 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1326 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1327 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1328 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1329 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1330 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1331 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1332 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1333 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1334 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1335 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1336 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1337 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1338 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1339 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1340 { PCI_VENDOR_ID_ATTO, 0x8070,
1341 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1342 { PCI_VENDOR_ID_ATTO, 0x8070,
1343 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1344 { PCI_VENDOR_ID_ATTO, 0x8072,
1345 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1346 { PCI_VENDOR_ID_ATTO, 0x8072,
1347 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1348 { PCI_VENDOR_ID_ATTO, 0x8070,
1349 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1350 { PCI_VENDOR_ID_ATTO, 0x8072,
1351 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1352 { PCI_VENDOR_ID_ATTO, 0x8072,
1353 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1354 {} /* terminate list */
1355};
1356
1357static struct pci_driver pm8001_pci_driver = {
1358 .name = DRV_NAME,
1359 .id_table = pm8001_pci_table,
1360 .probe = pm8001_pci_probe,
1361 .remove = pm8001_pci_remove,
1362 .suspend = pm8001_pci_suspend,
1363 .resume = pm8001_pci_resume,
1364};
1365
1366/**
1367 * pm8001_init - initialize scsi transport template
1368 */
1369static int __init pm8001_init(void)
1370{
1371 int rc = -ENOMEM;
1372
1373 pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1374 if (!pm8001_wq)
1375 goto err;
1376
1377 pm8001_id = 0;
1378 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1379 if (!pm8001_stt)
1380 goto err_wq;
1381 rc = pci_register_driver(&pm8001_pci_driver);
1382 if (rc)
1383 goto err_tp;
1384 return 0;
1385
1386err_tp:
1387 sas_release_transport(pm8001_stt);
1388err_wq:
1389 destroy_workqueue(pm8001_wq);
1390err:
1391 return rc;
1392}
1393
1394static void __exit pm8001_exit(void)
1395{
1396 pci_unregister_driver(&pm8001_pci_driver);
1397 sas_release_transport(pm8001_stt);
1398 destroy_workqueue(pm8001_wq);
1399}
1400
1401module_init(pm8001_init);
1402module_exit(pm8001_exit);
1403
1404MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1405MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1406MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1407MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1408MODULE_DESCRIPTION(
1409 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1410 "SAS/SATA controller driver");
1411MODULE_VERSION(DRV_VERSION);
1412MODULE_LICENSE("GPL");
1413MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1414
1/*
2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41#include <linux/slab.h>
42#include "pm8001_sas.h"
43#include "pm8001_chips.h"
44#include "pm80xx_hwi.h"
45
46static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING |
47 PM8001_EVENT_LOGGING | PM8001_INIT_LOGGING;
48module_param(logging_level, ulong, 0644);
49MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
50
51static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
52module_param(link_rate, ulong, 0644);
53MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
54 " 1: Link rate 1.5G\n"
55 " 2: Link rate 3.0G\n"
56 " 4: Link rate 6.0G\n"
57 " 8: Link rate 12.0G\n");
58
59bool pm8001_use_msix = true;
60module_param_named(use_msix, pm8001_use_msix, bool, 0444);
61MODULE_PARM_DESC(zoned, "Use MSIX interrupts. Default: true");
62
63static bool pm8001_use_tasklet = true;
64module_param_named(use_tasklet, pm8001_use_tasklet, bool, 0444);
65MODULE_PARM_DESC(zoned, "Use MSIX interrupts. Default: true");
66
67static bool pm8001_read_wwn = true;
68module_param_named(read_wwn, pm8001_read_wwn, bool, 0444);
69MODULE_PARM_DESC(zoned, "Get WWN from the controller. Default: true");
70
71static struct scsi_transport_template *pm8001_stt;
72static int pm8001_init_ccb_tag(struct pm8001_hba_info *);
73
74/*
75 * chip info structure to identify chip key functionality as
76 * encryption available/not, no of ports, hw specific function ref
77 */
78static const struct pm8001_chip_info pm8001_chips[] = {
79 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
80 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
81 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
82 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
83 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
84 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
85 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
86 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
87 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,},
88 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,},
89 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,},
90};
91static int pm8001_id;
92
93LIST_HEAD(hba_list);
94
95struct workqueue_struct *pm8001_wq;
96
97static void pm8001_map_queues(struct Scsi_Host *shost)
98{
99 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
100 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
101 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
102
103 if (pm8001_ha->number_of_intr > 1)
104 blk_mq_pci_map_queues(qmap, pm8001_ha->pdev, 1);
105
106 return blk_mq_map_queues(qmap);
107}
108
109/*
110 * The main structure which LLDD must register for scsi core.
111 */
112static const struct scsi_host_template pm8001_sht = {
113 .module = THIS_MODULE,
114 .name = DRV_NAME,
115 .proc_name = DRV_NAME,
116 .queuecommand = sas_queuecommand,
117 .dma_need_drain = ata_scsi_dma_need_drain,
118 .target_alloc = sas_target_alloc,
119 .slave_configure = sas_slave_configure,
120 .scan_finished = pm8001_scan_finished,
121 .scan_start = pm8001_scan_start,
122 .change_queue_depth = sas_change_queue_depth,
123 .bios_param = sas_bios_param,
124 .can_queue = 1,
125 .this_id = -1,
126 .sg_tablesize = PM8001_MAX_DMA_SG,
127 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
128 .eh_device_reset_handler = sas_eh_device_reset_handler,
129 .eh_target_reset_handler = sas_eh_target_reset_handler,
130 .slave_alloc = sas_slave_alloc,
131 .target_destroy = sas_target_destroy,
132 .ioctl = sas_ioctl,
133#ifdef CONFIG_COMPAT
134 .compat_ioctl = sas_ioctl,
135#endif
136 .shost_groups = pm8001_host_groups,
137 .track_queue_depth = 1,
138 .cmd_per_lun = 32,
139 .map_queues = pm8001_map_queues,
140};
141
142/*
143 * Sas layer call this function to execute specific task.
144 */
145static struct sas_domain_function_template pm8001_transport_ops = {
146 .lldd_dev_found = pm8001_dev_found,
147 .lldd_dev_gone = pm8001_dev_gone,
148
149 .lldd_execute_task = pm8001_queue_command,
150 .lldd_control_phy = pm8001_phy_control,
151
152 .lldd_abort_task = pm8001_abort_task,
153 .lldd_abort_task_set = sas_abort_task_set,
154 .lldd_clear_task_set = pm8001_clear_task_set,
155 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
156 .lldd_lu_reset = pm8001_lu_reset,
157 .lldd_query_task = pm8001_query_task,
158 .lldd_port_formed = pm8001_port_formed,
159 .lldd_tmf_exec_complete = pm8001_setds_completion,
160 .lldd_tmf_aborted = pm8001_tmf_aborted,
161};
162
163/**
164 * pm8001_phy_init - initiate our adapter phys
165 * @pm8001_ha: our hba structure.
166 * @phy_id: phy id.
167 */
168static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
169{
170 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
171 struct asd_sas_phy *sas_phy = &phy->sas_phy;
172 phy->phy_state = PHY_LINK_DISABLE;
173 phy->pm8001_ha = pm8001_ha;
174 phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
175 phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
176 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
177 sas_phy->iproto = SAS_PROTOCOL_ALL;
178 sas_phy->tproto = 0;
179 sas_phy->role = PHY_ROLE_INITIATOR;
180 sas_phy->oob_mode = OOB_NOT_CONNECTED;
181 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
182 sas_phy->id = phy_id;
183 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
184 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
185 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
186 sas_phy->lldd_phy = phy;
187}
188
189/**
190 * pm8001_free - free hba
191 * @pm8001_ha: our hba structure.
192 */
193static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
194{
195 int i;
196
197 if (!pm8001_ha)
198 return;
199
200 for (i = 0; i < USI_MAX_MEMCNT; i++) {
201 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
202 dma_free_coherent(&pm8001_ha->pdev->dev,
203 (pm8001_ha->memoryMap.region[i].total_len +
204 pm8001_ha->memoryMap.region[i].alignment),
205 pm8001_ha->memoryMap.region[i].virt_ptr,
206 pm8001_ha->memoryMap.region[i].phys_addr);
207 }
208 }
209 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
210 flush_workqueue(pm8001_wq);
211 bitmap_free(pm8001_ha->rsvd_tags);
212 kfree(pm8001_ha);
213}
214
215/**
216 * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler
217 * @opaque: the passed general host adapter struct
218 * Note: pm8001_tasklet is common for pm8001 & pm80xx
219 */
220static void pm8001_tasklet(unsigned long opaque)
221{
222 struct isr_param *irq_vector = (struct isr_param *)opaque;
223 struct pm8001_hba_info *pm8001_ha = irq_vector->drv_inst;
224
225 if (WARN_ON_ONCE(!pm8001_ha))
226 return;
227
228 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
229}
230
231static void pm8001_init_tasklet(struct pm8001_hba_info *pm8001_ha)
232{
233 int i;
234
235 if (!pm8001_use_tasklet)
236 return;
237
238 /* Tasklet for non msi-x interrupt handler */
239 if ((!pm8001_ha->pdev->msix_cap || !pci_msi_enabled()) ||
240 (pm8001_ha->chip_id == chip_8001)) {
241 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
242 (unsigned long)&(pm8001_ha->irq_vector[0]));
243 return;
244 }
245 for (i = 0; i < PM8001_MAX_MSIX_VEC; i++)
246 tasklet_init(&pm8001_ha->tasklet[i], pm8001_tasklet,
247 (unsigned long)&(pm8001_ha->irq_vector[i]));
248}
249
250static void pm8001_kill_tasklet(struct pm8001_hba_info *pm8001_ha)
251{
252 int i;
253
254 if (!pm8001_use_tasklet)
255 return;
256
257 /* For non-msix and msix interrupts */
258 if ((!pm8001_ha->pdev->msix_cap || !pci_msi_enabled()) ||
259 (pm8001_ha->chip_id == chip_8001)) {
260 tasklet_kill(&pm8001_ha->tasklet[0]);
261 return;
262 }
263
264 for (i = 0; i < PM8001_MAX_MSIX_VEC; i++)
265 tasklet_kill(&pm8001_ha->tasklet[i]);
266}
267
268static irqreturn_t pm8001_handle_irq(struct pm8001_hba_info *pm8001_ha,
269 int irq)
270{
271 if (unlikely(!pm8001_ha))
272 return IRQ_NONE;
273
274 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
275 return IRQ_NONE;
276
277 if (!pm8001_use_tasklet)
278 return PM8001_CHIP_DISP->isr(pm8001_ha, irq);
279
280 tasklet_schedule(&pm8001_ha->tasklet[irq]);
281 return IRQ_HANDLED;
282}
283
284/**
285 * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
286 * It obtains the vector number and calls the equivalent bottom
287 * half or services directly.
288 * @irq: interrupt number
289 * @opaque: the passed outbound queue/vector. Host structure is
290 * retrieved from the same.
291 */
292static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
293{
294 struct isr_param *irq_vector = (struct isr_param *)opaque;
295 struct pm8001_hba_info *pm8001_ha = irq_vector->drv_inst;
296
297 return pm8001_handle_irq(pm8001_ha, irq_vector->irq_id);
298}
299
300/**
301 * pm8001_interrupt_handler_intx - main INTx interrupt handler.
302 * @irq: interrupt number
303 * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure.
304 */
305
306static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
307{
308 struct sas_ha_struct *sha = dev_id;
309 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
310
311 return pm8001_handle_irq(pm8001_ha, 0);
312}
313
314static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
315static void pm8001_free_irq(struct pm8001_hba_info *pm8001_ha);
316
317/**
318 * pm8001_alloc - initiate our hba structure and 6 DMAs area.
319 * @pm8001_ha: our hba structure.
320 * @ent: PCI device ID structure to match on
321 */
322static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
323 const struct pci_device_id *ent)
324{
325 int i, count = 0, rc = 0;
326 u32 ci_offset, ib_offset, ob_offset, pi_offset;
327 struct inbound_queue_table *ibq;
328 struct outbound_queue_table *obq;
329
330 spin_lock_init(&pm8001_ha->lock);
331 spin_lock_init(&pm8001_ha->bitmap_lock);
332 pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
333 pm8001_ha->chip->n_phy);
334
335 /* Request Interrupt */
336 rc = pm8001_request_irq(pm8001_ha);
337 if (rc)
338 goto err_out;
339
340 count = pm8001_ha->max_q_num;
341 /* Queues are chosen based on the number of cores/msix availability */
342 ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE;
343 ci_offset = pm8001_ha->ci_offset = ib_offset + count;
344 ob_offset = pm8001_ha->ob_offset = ci_offset + count;
345 pi_offset = pm8001_ha->pi_offset = ob_offset + count;
346 pm8001_ha->max_memcnt = pi_offset + count;
347
348 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
349 pm8001_phy_init(pm8001_ha, i);
350 pm8001_ha->port[i].wide_port_phymap = 0;
351 pm8001_ha->port[i].port_attached = 0;
352 pm8001_ha->port[i].port_state = 0;
353 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
354 }
355
356 /* MPI Memory region 1 for AAP Event Log for fw */
357 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
358 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
359 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
360 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
361
362 /* MPI Memory region 2 for IOP Event Log for fw */
363 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
364 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
365 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
366 pm8001_ha->memoryMap.region[IOP].alignment = 32;
367
368 for (i = 0; i < count; i++) {
369 ibq = &pm8001_ha->inbnd_q_tbl[i];
370 spin_lock_init(&ibq->iq_lock);
371 /* MPI Memory region 3 for consumer Index of inbound queues */
372 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
373 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
374 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
375 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
376
377 if ((ent->driver_data) != chip_8001) {
378 /* MPI Memory region 5 inbound queues */
379 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
380 PM8001_MPI_QUEUE;
381 pm8001_ha->memoryMap.region[ib_offset+i].element_size
382 = 128;
383 pm8001_ha->memoryMap.region[ib_offset+i].total_len =
384 PM8001_MPI_QUEUE * 128;
385 pm8001_ha->memoryMap.region[ib_offset+i].alignment
386 = 128;
387 } else {
388 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
389 PM8001_MPI_QUEUE;
390 pm8001_ha->memoryMap.region[ib_offset+i].element_size
391 = 64;
392 pm8001_ha->memoryMap.region[ib_offset+i].total_len =
393 PM8001_MPI_QUEUE * 64;
394 pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
395 }
396 }
397
398 for (i = 0; i < count; i++) {
399 obq = &pm8001_ha->outbnd_q_tbl[i];
400 spin_lock_init(&obq->oq_lock);
401 /* MPI Memory region 4 for producer Index of outbound queues */
402 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
403 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
404 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
405 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
406
407 if (ent->driver_data != chip_8001) {
408 /* MPI Memory region 6 Outbound queues */
409 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
410 PM8001_MPI_QUEUE;
411 pm8001_ha->memoryMap.region[ob_offset+i].element_size
412 = 128;
413 pm8001_ha->memoryMap.region[ob_offset+i].total_len =
414 PM8001_MPI_QUEUE * 128;
415 pm8001_ha->memoryMap.region[ob_offset+i].alignment
416 = 128;
417 } else {
418 /* MPI Memory region 6 Outbound queues */
419 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
420 PM8001_MPI_QUEUE;
421 pm8001_ha->memoryMap.region[ob_offset+i].element_size
422 = 64;
423 pm8001_ha->memoryMap.region[ob_offset+i].total_len =
424 PM8001_MPI_QUEUE * 64;
425 pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
426 }
427
428 }
429 /* Memory region write DMA*/
430 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
431 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
432 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
433
434 /* Memory region for fw flash */
435 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
436
437 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
438 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
439 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
440 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
441 for (i = 0; i < pm8001_ha->max_memcnt; i++) {
442 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i];
443
444 if (pm8001_mem_alloc(pm8001_ha->pdev,
445 ®ion->virt_ptr,
446 ®ion->phys_addr,
447 ®ion->phys_addr_hi,
448 ®ion->phys_addr_lo,
449 region->total_len,
450 region->alignment) != 0) {
451 pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i);
452 goto err_out;
453 }
454 }
455
456 /* Memory region for devices*/
457 pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
458 * sizeof(struct pm8001_device), GFP_KERNEL);
459 if (!pm8001_ha->devices) {
460 rc = -ENOMEM;
461 goto err_out_nodev;
462 }
463 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
464 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
465 pm8001_ha->devices[i].id = i;
466 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
467 atomic_set(&pm8001_ha->devices[i].running_req, 0);
468 }
469 pm8001_ha->flags = PM8001F_INIT_TIME;
470 return 0;
471
472err_out_nodev:
473 for (i = 0; i < pm8001_ha->max_memcnt; i++) {
474 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
475 dma_free_coherent(&pm8001_ha->pdev->dev,
476 (pm8001_ha->memoryMap.region[i].total_len +
477 pm8001_ha->memoryMap.region[i].alignment),
478 pm8001_ha->memoryMap.region[i].virt_ptr,
479 pm8001_ha->memoryMap.region[i].phys_addr);
480 }
481 }
482err_out:
483 return 1;
484}
485
486/**
487 * pm8001_ioremap - remap the pci high physical address to kernel virtual
488 * address so that we can access them.
489 * @pm8001_ha: our hba structure.
490 */
491static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
492{
493 u32 bar;
494 u32 logicalBar = 0;
495 struct pci_dev *pdev;
496
497 pdev = pm8001_ha->pdev;
498 /* map pci mem (PMC pci base 0-3)*/
499 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
500 /*
501 ** logical BARs for SPC:
502 ** bar 0 and 1 - logical BAR0
503 ** bar 2 and 3 - logical BAR1
504 ** bar4 - logical BAR2
505 ** bar5 - logical BAR3
506 ** Skip the appropriate assignments:
507 */
508 if ((bar == 1) || (bar == 3))
509 continue;
510 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
511 pm8001_ha->io_mem[logicalBar].membase =
512 pci_resource_start(pdev, bar);
513 pm8001_ha->io_mem[logicalBar].memsize =
514 pci_resource_len(pdev, bar);
515 pm8001_ha->io_mem[logicalBar].memvirtaddr =
516 ioremap(pm8001_ha->io_mem[logicalBar].membase,
517 pm8001_ha->io_mem[logicalBar].memsize);
518 if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) {
519 pm8001_dbg(pm8001_ha, INIT,
520 "Failed to ioremap bar %d, logicalBar %d",
521 bar, logicalBar);
522 return -ENOMEM;
523 }
524 pm8001_dbg(pm8001_ha, INIT,
525 "base addr %llx virt_addr=%llx len=%d\n",
526 (u64)pm8001_ha->io_mem[logicalBar].membase,
527 (u64)(unsigned long)
528 pm8001_ha->io_mem[logicalBar].memvirtaddr,
529 pm8001_ha->io_mem[logicalBar].memsize);
530 } else {
531 pm8001_ha->io_mem[logicalBar].membase = 0;
532 pm8001_ha->io_mem[logicalBar].memsize = 0;
533 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
534 }
535 logicalBar++;
536 }
537 return 0;
538}
539
540/**
541 * pm8001_pci_alloc - initialize our ha card structure
542 * @pdev: pci device.
543 * @ent: ent
544 * @shost: scsi host struct which has been initialized before.
545 */
546static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
547 const struct pci_device_id *ent,
548 struct Scsi_Host *shost)
549
550{
551 struct pm8001_hba_info *pm8001_ha;
552 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
553
554 pm8001_ha = sha->lldd_ha;
555 if (!pm8001_ha)
556 return NULL;
557
558 pm8001_ha->pdev = pdev;
559 pm8001_ha->dev = &pdev->dev;
560 pm8001_ha->chip_id = ent->driver_data;
561 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
562 pm8001_ha->irq = pdev->irq;
563 pm8001_ha->sas = sha;
564 pm8001_ha->shost = shost;
565 pm8001_ha->id = pm8001_id++;
566 pm8001_ha->logging_level = logging_level;
567 pm8001_ha->non_fatal_count = 0;
568 if (link_rate >= 1 && link_rate <= 15)
569 pm8001_ha->link_rate = (link_rate << 8);
570 else {
571 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
572 LINKRATE_60 | LINKRATE_120;
573 pm8001_dbg(pm8001_ha, FAIL,
574 "Setting link rate to default value\n");
575 }
576 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
577 /* IOMB size is 128 for 8088/89 controllers */
578 if (pm8001_ha->chip_id != chip_8001)
579 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
580 else
581 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
582
583 pm8001_init_tasklet(pm8001_ha);
584
585 if (pm8001_ioremap(pm8001_ha))
586 goto failed_pci_alloc;
587 if (!pm8001_alloc(pm8001_ha, ent))
588 return pm8001_ha;
589failed_pci_alloc:
590 pm8001_free(pm8001_ha);
591 return NULL;
592}
593
594/**
595 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
596 * @pdev: pci device.
597 */
598static int pci_go_44(struct pci_dev *pdev)
599{
600 int rc;
601
602 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
603 if (rc) {
604 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
605 if (rc)
606 dev_printk(KERN_ERR, &pdev->dev,
607 "32-bit DMA enable failed\n");
608 }
609 return rc;
610}
611
612/**
613 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
614 * @shost: scsi host which has been allocated outside.
615 * @chip_info: our ha struct.
616 */
617static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
618 const struct pm8001_chip_info *chip_info)
619{
620 int phy_nr, port_nr;
621 struct asd_sas_phy **arr_phy;
622 struct asd_sas_port **arr_port;
623 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
624
625 phy_nr = chip_info->n_phy;
626 port_nr = phy_nr;
627 memset(sha, 0x00, sizeof(*sha));
628 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
629 if (!arr_phy)
630 goto exit;
631 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
632 if (!arr_port)
633 goto exit_free2;
634
635 sha->sas_phy = arr_phy;
636 sha->sas_port = arr_port;
637 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
638 if (!sha->lldd_ha)
639 goto exit_free1;
640
641 shost->transportt = pm8001_stt;
642 shost->max_id = PM8001_MAX_DEVICES;
643 shost->unique_id = pm8001_id;
644 shost->max_cmd_len = 16;
645 return 0;
646exit_free1:
647 kfree(arr_port);
648exit_free2:
649 kfree(arr_phy);
650exit:
651 return -1;
652}
653
654/**
655 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
656 * @shost: scsi host which has been allocated outside
657 * @chip_info: our ha struct.
658 */
659static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
660 const struct pm8001_chip_info *chip_info)
661{
662 int i = 0;
663 struct pm8001_hba_info *pm8001_ha;
664 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
665
666 pm8001_ha = sha->lldd_ha;
667 for (i = 0; i < chip_info->n_phy; i++) {
668 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
669 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
670 sha->sas_phy[i]->sas_addr =
671 (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
672 }
673 sha->sas_ha_name = DRV_NAME;
674 sha->dev = pm8001_ha->dev;
675 sha->strict_wide_ports = 1;
676 sha->sas_addr = &pm8001_ha->sas_addr[0];
677 sha->num_phys = chip_info->n_phy;
678 sha->shost = shost;
679}
680
681/**
682 * pm8001_init_sas_add - initialize sas address
683 * @pm8001_ha: our ha struct.
684 *
685 * Currently we just set the fixed SAS address to our HBA, for manufacture,
686 * it should read from the EEPROM
687 */
688static int pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
689{
690 DECLARE_COMPLETION_ONSTACK(completion);
691 struct pm8001_ioctl_payload payload;
692 unsigned long time_remaining;
693 u8 sas_add[8];
694 u16 deviceid;
695 int rc;
696 u8 i, j;
697
698 if (!pm8001_read_wwn) {
699 __be64 dev_sas_addr = cpu_to_be64(0x50010c600047f9d0ULL);
700
701 for (i = 0; i < pm8001_ha->chip->n_phy; i++)
702 memcpy(&pm8001_ha->phy[i].dev_sas_addr, &dev_sas_addr,
703 SAS_ADDR_SIZE);
704 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
705 SAS_ADDR_SIZE);
706 return 0;
707 }
708
709 /*
710 * For new SPC controllers WWN is stored in flash vpd. For SPC/SPCve
711 * controllers WWN is stored in EEPROM. And for Older SPC WWN is stored
712 * in NVMD.
713 */
714 if (PM8001_CHIP_DISP->fatal_errors(pm8001_ha)) {
715 pm8001_dbg(pm8001_ha, FAIL, "controller is in fatal error state\n");
716 return -EIO;
717 }
718
719 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
720 pm8001_ha->nvmd_completion = &completion;
721
722 if (pm8001_ha->chip_id == chip_8001) {
723 if (deviceid == 0x8081 || deviceid == 0x0042) {
724 payload.minor_function = 4;
725 payload.rd_length = 4096;
726 } else {
727 payload.minor_function = 0;
728 payload.rd_length = 128;
729 }
730 } else if ((pm8001_ha->chip_id == chip_8070 ||
731 pm8001_ha->chip_id == chip_8072) &&
732 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
733 payload.minor_function = 4;
734 payload.rd_length = 4096;
735 } else {
736 payload.minor_function = 1;
737 payload.rd_length = 4096;
738 }
739 payload.offset = 0;
740 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
741 if (!payload.func_specific) {
742 pm8001_dbg(pm8001_ha, FAIL, "mem alloc fail\n");
743 return -ENOMEM;
744 }
745 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
746 if (rc) {
747 kfree(payload.func_specific);
748 pm8001_dbg(pm8001_ha, FAIL, "nvmd failed\n");
749 return -EIO;
750 }
751 time_remaining = wait_for_completion_timeout(&completion,
752 msecs_to_jiffies(60*1000)); // 1 min
753 if (!time_remaining) {
754 kfree(payload.func_specific);
755 pm8001_dbg(pm8001_ha, FAIL, "get_nvmd_req timeout\n");
756 return -EIO;
757 }
758
759
760 for (i = 0, j = 0; i <= 7; i++, j++) {
761 if (pm8001_ha->chip_id == chip_8001) {
762 if (deviceid == 0x8081)
763 pm8001_ha->sas_addr[j] =
764 payload.func_specific[0x704 + i];
765 else if (deviceid == 0x0042)
766 pm8001_ha->sas_addr[j] =
767 payload.func_specific[0x010 + i];
768 } else if ((pm8001_ha->chip_id == chip_8070 ||
769 pm8001_ha->chip_id == chip_8072) &&
770 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
771 pm8001_ha->sas_addr[j] =
772 payload.func_specific[0x010 + i];
773 } else
774 pm8001_ha->sas_addr[j] =
775 payload.func_specific[0x804 + i];
776 }
777 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
778 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
779 if (i && ((i % 4) == 0))
780 sas_add[7] = sas_add[7] + 4;
781 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
782 sas_add, SAS_ADDR_SIZE);
783 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
784 pm8001_ha->phy[i].dev_sas_addr);
785 }
786 kfree(payload.func_specific);
787
788 return 0;
789}
790
791/*
792 * pm8001_get_phy_settings_info : Read phy setting values.
793 * @pm8001_ha : our hba.
794 */
795static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
796{
797 DECLARE_COMPLETION_ONSTACK(completion);
798 struct pm8001_ioctl_payload payload;
799 int rc;
800
801 if (!pm8001_read_wwn)
802 return 0;
803
804 pm8001_ha->nvmd_completion = &completion;
805 /* SAS ADDRESS read from flash / EEPROM */
806 payload.minor_function = 6;
807 payload.offset = 0;
808 payload.rd_length = 4096;
809 payload.func_specific = kzalloc(4096, GFP_KERNEL);
810 if (!payload.func_specific)
811 return -ENOMEM;
812 /* Read phy setting values from flash */
813 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
814 if (rc) {
815 kfree(payload.func_specific);
816 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
817 return -ENOMEM;
818 }
819 wait_for_completion(&completion);
820 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
821 kfree(payload.func_specific);
822
823 return 0;
824}
825
826struct pm8001_mpi3_phy_pg_trx_config {
827 u32 LaneLosCfg;
828 u32 LanePgaCfg1;
829 u32 LanePisoCfg1;
830 u32 LanePisoCfg2;
831 u32 LanePisoCfg3;
832 u32 LanePisoCfg4;
833 u32 LanePisoCfg5;
834 u32 LanePisoCfg6;
835 u32 LaneBctCtrl;
836};
837
838/**
839 * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings
840 * @pm8001_ha : our adapter
841 * @phycfg : PHY config page to populate
842 */
843static
844void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
845 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
846{
847 phycfg->LaneLosCfg = 0x00000132;
848 phycfg->LanePgaCfg1 = 0x00203949;
849 phycfg->LanePisoCfg1 = 0x000000FF;
850 phycfg->LanePisoCfg2 = 0xFF000001;
851 phycfg->LanePisoCfg3 = 0xE7011300;
852 phycfg->LanePisoCfg4 = 0x631C40C0;
853 phycfg->LanePisoCfg5 = 0xF8102036;
854 phycfg->LanePisoCfg6 = 0xF74A1000;
855 phycfg->LaneBctCtrl = 0x00FB33F8;
856}
857
858/**
859 * pm8001_get_external_phy_settings - Retrieves the external PHY settings
860 * @pm8001_ha : our adapter
861 * @phycfg : PHY config page to populate
862 */
863static
864void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
865 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
866{
867 phycfg->LaneLosCfg = 0x00000132;
868 phycfg->LanePgaCfg1 = 0x00203949;
869 phycfg->LanePisoCfg1 = 0x000000FF;
870 phycfg->LanePisoCfg2 = 0xFF000001;
871 phycfg->LanePisoCfg3 = 0xE7011300;
872 phycfg->LanePisoCfg4 = 0x63349140;
873 phycfg->LanePisoCfg5 = 0xF8102036;
874 phycfg->LanePisoCfg6 = 0xF80D9300;
875 phycfg->LaneBctCtrl = 0x00FB33F8;
876}
877
878/**
879 * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext
880 * @pm8001_ha : our adapter
881 * @phymask : The PHY mask
882 */
883static
884void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
885{
886 switch (pm8001_ha->pdev->subsystem_device) {
887 case 0x0070: /* H1280 - 8 external 0 internal */
888 case 0x0072: /* H12F0 - 16 external 0 internal */
889 *phymask = 0x0000;
890 break;
891
892 case 0x0071: /* H1208 - 0 external 8 internal */
893 case 0x0073: /* H120F - 0 external 16 internal */
894 *phymask = 0xFFFF;
895 break;
896
897 case 0x0080: /* H1244 - 4 external 4 internal */
898 *phymask = 0x00F0;
899 break;
900
901 case 0x0081: /* H1248 - 4 external 8 internal */
902 *phymask = 0x0FF0;
903 break;
904
905 case 0x0082: /* H1288 - 8 external 8 internal */
906 *phymask = 0xFF00;
907 break;
908
909 default:
910 pm8001_dbg(pm8001_ha, INIT,
911 "Unknown subsystem device=0x%.04x\n",
912 pm8001_ha->pdev->subsystem_device);
913 }
914}
915
916/**
917 * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings
918 * @pm8001_ha : our adapter
919 */
920static
921int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
922{
923 struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
924 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
925 int phymask = 0;
926 int i = 0;
927
928 memset(&phycfg_int, 0, sizeof(phycfg_int));
929 memset(&phycfg_ext, 0, sizeof(phycfg_ext));
930
931 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
932 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
933 pm8001_get_phy_mask(pm8001_ha, &phymask);
934
935 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
936 if (phymask & (1 << i)) {/* Internal PHY */
937 pm8001_set_phy_profile_single(pm8001_ha, i,
938 sizeof(phycfg_int) / sizeof(u32),
939 (u32 *)&phycfg_int);
940
941 } else { /* External PHY */
942 pm8001_set_phy_profile_single(pm8001_ha, i,
943 sizeof(phycfg_ext) / sizeof(u32),
944 (u32 *)&phycfg_ext);
945 }
946 }
947
948 return 0;
949}
950
951/**
952 * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID.
953 * @pm8001_ha : our hba.
954 */
955static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
956{
957 switch (pm8001_ha->pdev->subsystem_vendor) {
958 case PCI_VENDOR_ID_ATTO:
959 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
960 return 0;
961 else
962 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
963
964 case PCI_VENDOR_ID_ADAPTEC2:
965 case 0:
966 return 0;
967
968 default:
969 return pm8001_get_phy_settings_info(pm8001_ha);
970 }
971}
972
973/**
974 * pm8001_setup_msix - enable MSI-X interrupt
975 * @pm8001_ha: our ha struct.
976 */
977static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
978{
979 unsigned int allocated_irq_vectors;
980 int rc;
981
982 /* SPCv controllers supports 64 msi-x */
983 if (pm8001_ha->chip_id == chip_8001) {
984 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, 1, 1,
985 PCI_IRQ_MSIX);
986 } else {
987 /*
988 * Queue index #0 is used always for housekeeping, so don't
989 * include in the affinity spreading.
990 */
991 struct irq_affinity desc = {
992 .pre_vectors = 1,
993 };
994 rc = pci_alloc_irq_vectors_affinity(
995 pm8001_ha->pdev, 2, PM8001_MAX_MSIX_VEC,
996 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, &desc);
997 }
998
999 allocated_irq_vectors = rc;
1000 if (rc < 0)
1001 return rc;
1002
1003 /* Assigns the number of interrupts */
1004 pm8001_ha->number_of_intr = allocated_irq_vectors;
1005
1006 /* Maximum queue number updating in HBA structure */
1007 pm8001_ha->max_q_num = allocated_irq_vectors;
1008
1009 pm8001_dbg(pm8001_ha, INIT,
1010 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
1011 rc, pm8001_ha->number_of_intr);
1012 return 0;
1013}
1014
1015static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
1016{
1017 u32 i = 0, j = 0;
1018 int flag = 0, rc = 0;
1019 int nr_irqs = pm8001_ha->number_of_intr;
1020
1021 if (pm8001_ha->chip_id != chip_8001)
1022 flag &= ~IRQF_SHARED;
1023
1024 pm8001_dbg(pm8001_ha, INIT,
1025 "pci_enable_msix request number of intr %d\n",
1026 pm8001_ha->number_of_intr);
1027
1028 if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname))
1029 nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname);
1030
1031 for (i = 0; i < nr_irqs; i++) {
1032 snprintf(pm8001_ha->intr_drvname[i],
1033 sizeof(pm8001_ha->intr_drvname[0]),
1034 "%s-%d", pm8001_ha->name, i);
1035 pm8001_ha->irq_vector[i].irq_id = i;
1036 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
1037
1038 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
1039 pm8001_interrupt_handler_msix, flag,
1040 pm8001_ha->intr_drvname[i],
1041 &(pm8001_ha->irq_vector[i]));
1042 if (rc) {
1043 for (j = 0; j < i; j++) {
1044 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
1045 &(pm8001_ha->irq_vector[i]));
1046 }
1047 pci_free_irq_vectors(pm8001_ha->pdev);
1048 break;
1049 }
1050 }
1051
1052 return rc;
1053}
1054
1055/**
1056 * pm8001_request_irq - register interrupt
1057 * @pm8001_ha: our ha struct.
1058 */
1059static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1060{
1061 struct pci_dev *pdev = pm8001_ha->pdev;
1062 int rc;
1063
1064 if (pm8001_use_msix && pci_find_capability(pdev, PCI_CAP_ID_MSIX)) {
1065 rc = pm8001_setup_msix(pm8001_ha);
1066 if (rc) {
1067 pm8001_dbg(pm8001_ha, FAIL,
1068 "pm8001_setup_irq failed [ret: %d]\n", rc);
1069 return rc;
1070 }
1071
1072 if (!pdev->msix_cap || !pci_msi_enabled())
1073 goto use_intx;
1074
1075 rc = pm8001_request_msix(pm8001_ha);
1076 if (rc)
1077 return rc;
1078
1079 pm8001_ha->use_msix = true;
1080
1081 return 0;
1082 }
1083
1084use_intx:
1085 /* Initialize the INT-X interrupt */
1086 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1087 pm8001_ha->use_msix = false;
1088 pm8001_ha->irq_vector[0].irq_id = 0;
1089 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1090
1091 return request_irq(pdev->irq, pm8001_interrupt_handler_intx,
1092 IRQF_SHARED, pm8001_ha->name,
1093 SHOST_TO_SAS_HA(pm8001_ha->shost));
1094}
1095
1096static void pm8001_free_irq(struct pm8001_hba_info *pm8001_ha)
1097{
1098 struct pci_dev *pdev = pm8001_ha->pdev;
1099 int i;
1100
1101 if (pm8001_ha->use_msix) {
1102 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1103 synchronize_irq(pci_irq_vector(pdev, i));
1104
1105 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1106 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1107
1108 pci_free_irq_vectors(pdev);
1109 return;
1110 }
1111
1112 /* INT-X */
1113 free_irq(pm8001_ha->irq, pm8001_ha->sas);
1114}
1115
1116/**
1117 * pm8001_pci_probe - probe supported device
1118 * @pdev: pci device which kernel has been prepared for.
1119 * @ent: pci device id
1120 *
1121 * This function is the main initialization function, when register a new
1122 * pci driver it is invoked, all struct and hardware initialization should be
1123 * done here, also, register interrupt.
1124 */
1125static int pm8001_pci_probe(struct pci_dev *pdev,
1126 const struct pci_device_id *ent)
1127{
1128 unsigned int rc;
1129 u32 pci_reg;
1130 u8 i = 0;
1131 struct pm8001_hba_info *pm8001_ha;
1132 struct Scsi_Host *shost = NULL;
1133 const struct pm8001_chip_info *chip;
1134 struct sas_ha_struct *sha;
1135
1136 dev_printk(KERN_INFO, &pdev->dev,
1137 "pm80xx: driver version %s\n", DRV_VERSION);
1138 rc = pci_enable_device(pdev);
1139 if (rc)
1140 goto err_out_enable;
1141 pci_set_master(pdev);
1142 /*
1143 * Enable pci slot busmaster by setting pci command register.
1144 * This is required by FW for Cyclone card.
1145 */
1146
1147 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1148 pci_reg |= 0x157;
1149 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1150 rc = pci_request_regions(pdev, DRV_NAME);
1151 if (rc)
1152 goto err_out_disable;
1153 rc = pci_go_44(pdev);
1154 if (rc)
1155 goto err_out_regions;
1156
1157 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1158 if (!shost) {
1159 rc = -ENOMEM;
1160 goto err_out_regions;
1161 }
1162 chip = &pm8001_chips[ent->driver_data];
1163 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1164 if (!sha) {
1165 rc = -ENOMEM;
1166 goto err_out_free_host;
1167 }
1168 SHOST_TO_SAS_HA(shost) = sha;
1169
1170 rc = pm8001_prep_sas_ha_init(shost, chip);
1171 if (rc) {
1172 rc = -ENOMEM;
1173 goto err_out_free;
1174 }
1175 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1176 /* ent->driver variable is used to differentiate between controllers */
1177 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1178 if (!pm8001_ha) {
1179 rc = -ENOMEM;
1180 goto err_out_free;
1181 }
1182
1183 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1184 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1185 if (rc) {
1186 pm8001_dbg(pm8001_ha, FAIL,
1187 "chip_init failed [ret: %d]\n", rc);
1188 goto err_out_ha_free;
1189 }
1190
1191 rc = pm8001_init_ccb_tag(pm8001_ha);
1192 if (rc)
1193 goto err_out_enable;
1194
1195
1196 PM8001_CHIP_DISP->chip_post_init(pm8001_ha);
1197
1198 if (pm8001_ha->number_of_intr > 1) {
1199 shost->nr_hw_queues = pm8001_ha->number_of_intr - 1;
1200 /*
1201 * For now, ensure we're not sent too many commands by setting
1202 * host_tagset. This is also required if we start using request
1203 * tag.
1204 */
1205 shost->host_tagset = 1;
1206 }
1207
1208 rc = scsi_add_host(shost, &pdev->dev);
1209 if (rc)
1210 goto err_out_ha_free;
1211
1212 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1213 if (pm8001_ha->chip_id != chip_8001) {
1214 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1215 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1216 /* setup thermal configuration. */
1217 pm80xx_set_thermal_config(pm8001_ha);
1218 }
1219
1220 rc = pm8001_init_sas_add(pm8001_ha);
1221 if (rc)
1222 goto err_out_shost;
1223 /* phy setting support for motherboard controller */
1224 rc = pm8001_configure_phy_settings(pm8001_ha);
1225 if (rc)
1226 goto err_out_shost;
1227
1228 pm8001_post_sas_ha_init(shost, chip);
1229 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1230 if (rc) {
1231 pm8001_dbg(pm8001_ha, FAIL,
1232 "sas_register_ha failed [ret: %d]\n", rc);
1233 goto err_out_shost;
1234 }
1235 list_add_tail(&pm8001_ha->list, &hba_list);
1236 pm8001_ha->flags = PM8001F_RUN_TIME;
1237 scsi_scan_host(pm8001_ha->shost);
1238 return 0;
1239
1240err_out_shost:
1241 scsi_remove_host(pm8001_ha->shost);
1242err_out_ha_free:
1243 pm8001_free(pm8001_ha);
1244err_out_free:
1245 kfree(sha);
1246err_out_free_host:
1247 scsi_host_put(shost);
1248err_out_regions:
1249 pci_release_regions(pdev);
1250err_out_disable:
1251 pci_disable_device(pdev);
1252err_out_enable:
1253 return rc;
1254}
1255
1256/**
1257 * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1258 * @pm8001_ha: our hba card information.
1259 */
1260static int pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha)
1261{
1262 struct Scsi_Host *shost = pm8001_ha->shost;
1263 struct device *dev = pm8001_ha->dev;
1264 u32 max_out_io, ccb_count;
1265 int i;
1266
1267 max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1268 ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1269
1270 shost->can_queue = ccb_count - PM8001_RESERVE_SLOT;
1271
1272 pm8001_ha->rsvd_tags = bitmap_zalloc(PM8001_RESERVE_SLOT, GFP_KERNEL);
1273 if (!pm8001_ha->rsvd_tags)
1274 goto err_out;
1275
1276 /* Memory region for ccb_info*/
1277 pm8001_ha->ccb_count = ccb_count;
1278 pm8001_ha->ccb_info =
1279 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1280 if (!pm8001_ha->ccb_info) {
1281 pm8001_dbg(pm8001_ha, FAIL,
1282 "Unable to allocate memory for ccb\n");
1283 goto err_out_noccb;
1284 }
1285 for (i = 0; i < ccb_count; i++) {
1286 pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(dev,
1287 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1288 &pm8001_ha->ccb_info[i].ccb_dma_handle,
1289 GFP_KERNEL);
1290 if (!pm8001_ha->ccb_info[i].buf_prd) {
1291 pm8001_dbg(pm8001_ha, FAIL,
1292 "ccb prd memory allocation error\n");
1293 goto err_out;
1294 }
1295 pm8001_ha->ccb_info[i].task = NULL;
1296 pm8001_ha->ccb_info[i].ccb_tag = PM8001_INVALID_TAG;
1297 pm8001_ha->ccb_info[i].device = NULL;
1298 }
1299
1300 return 0;
1301
1302err_out_noccb:
1303 kfree(pm8001_ha->devices);
1304err_out:
1305 return -ENOMEM;
1306}
1307
1308static void pm8001_pci_remove(struct pci_dev *pdev)
1309{
1310 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1311 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1312 int i;
1313
1314 sas_unregister_ha(sha);
1315 sas_remove_host(pm8001_ha->shost);
1316 list_del(&pm8001_ha->list);
1317 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1318 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1319
1320 pm8001_free_irq(pm8001_ha);
1321 pm8001_kill_tasklet(pm8001_ha);
1322 scsi_host_put(pm8001_ha->shost);
1323
1324 for (i = 0; i < pm8001_ha->ccb_count; i++) {
1325 dma_free_coherent(&pm8001_ha->pdev->dev,
1326 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1327 pm8001_ha->ccb_info[i].buf_prd,
1328 pm8001_ha->ccb_info[i].ccb_dma_handle);
1329 }
1330 kfree(pm8001_ha->ccb_info);
1331 kfree(pm8001_ha->devices);
1332
1333 pm8001_free(pm8001_ha);
1334 kfree(sha->sas_phy);
1335 kfree(sha->sas_port);
1336 kfree(sha);
1337 pci_release_regions(pdev);
1338 pci_disable_device(pdev);
1339}
1340
1341/**
1342 * pm8001_pci_suspend - power management suspend main entry point
1343 * @dev: Device struct
1344 *
1345 * Return: 0 on success, anything else on error.
1346 */
1347static int __maybe_unused pm8001_pci_suspend(struct device *dev)
1348{
1349 struct pci_dev *pdev = to_pci_dev(dev);
1350 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1351 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1352
1353 sas_suspend_ha(sha);
1354 flush_workqueue(pm8001_wq);
1355 scsi_block_requests(pm8001_ha->shost);
1356 if (!pdev->pm_cap) {
1357 dev_err(dev, " PCI PM not supported\n");
1358 return -ENODEV;
1359 }
1360 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1361 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1362
1363 pm8001_free_irq(pm8001_ha);
1364 pm8001_kill_tasklet(pm8001_ha);
1365
1366 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering "
1367 "suspended state\n", pdev,
1368 pm8001_ha->name);
1369 return 0;
1370}
1371
1372/**
1373 * pm8001_pci_resume - power management resume main entry point
1374 * @dev: Device struct
1375 *
1376 * Return: 0 on success, anything else on error.
1377 */
1378static int __maybe_unused pm8001_pci_resume(struct device *dev)
1379{
1380 struct pci_dev *pdev = to_pci_dev(dev);
1381 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1382 struct pm8001_hba_info *pm8001_ha;
1383 int rc;
1384 u8 i = 0;
1385 DECLARE_COMPLETION_ONSTACK(completion);
1386
1387 pm8001_ha = sha->lldd_ha;
1388
1389 pm8001_info(pm8001_ha,
1390 "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n",
1391 pdev, pm8001_ha->name, pdev->current_state);
1392
1393 rc = pci_go_44(pdev);
1394 if (rc)
1395 goto err_out_disable;
1396 sas_prep_resume_ha(sha);
1397 /* chip soft rst only for spc */
1398 if (pm8001_ha->chip_id == chip_8001) {
1399 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1400 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
1401 }
1402 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1403 if (rc)
1404 goto err_out_disable;
1405
1406 /* disable all the interrupt bits */
1407 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1408
1409 rc = pm8001_request_irq(pm8001_ha);
1410 if (rc)
1411 goto err_out_disable;
1412
1413 pm8001_init_tasklet(pm8001_ha);
1414
1415 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1416 if (pm8001_ha->chip_id != chip_8001) {
1417 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1418 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1419 }
1420
1421 /* Chip documentation for the 8070 and 8072 SPCv */
1422 /* states that a 500ms minimum delay is required */
1423 /* before issuing commands. Otherwise, the firmware */
1424 /* will enter an unrecoverable state. */
1425
1426 if (pm8001_ha->chip_id == chip_8070 ||
1427 pm8001_ha->chip_id == chip_8072) {
1428 mdelay(500);
1429 }
1430
1431 /* Spin up the PHYs */
1432
1433 pm8001_ha->flags = PM8001F_RUN_TIME;
1434 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1435 pm8001_ha->phy[i].enable_completion = &completion;
1436 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1437 wait_for_completion(&completion);
1438 }
1439 sas_resume_ha(sha);
1440 return 0;
1441
1442err_out_disable:
1443 scsi_remove_host(pm8001_ha->shost);
1444
1445 return rc;
1446}
1447
1448/* update of pci device, vendor id and driver data with
1449 * unique value for each of the controller
1450 */
1451static struct pci_device_id pm8001_pci_table[] = {
1452 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1453 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1454 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1455 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1456 /* Support for SPC/SPCv/SPCve controllers */
1457 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1458 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1459 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1460 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1461 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1462 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1463 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1464 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1465 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1466 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1467 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1468 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1469 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1470 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1471 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1472 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1473 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1474 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1475 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1476 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1477 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1478 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1479 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1480 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1481 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1482 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1483 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1484 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1485 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1486 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1487 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1488 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1489 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1490 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1491 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1492 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1493 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1494 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1495 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1496 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1497 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1498 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1499 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1500 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1501 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1502 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1503 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1504 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1505 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1506 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1507 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1508 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1509 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1510 { PCI_VENDOR_ID_ATTO, 0x8070,
1511 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1512 { PCI_VENDOR_ID_ATTO, 0x8070,
1513 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1514 { PCI_VENDOR_ID_ATTO, 0x8072,
1515 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1516 { PCI_VENDOR_ID_ATTO, 0x8072,
1517 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1518 { PCI_VENDOR_ID_ATTO, 0x8070,
1519 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1520 { PCI_VENDOR_ID_ATTO, 0x8072,
1521 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1522 { PCI_VENDOR_ID_ATTO, 0x8072,
1523 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1524 {} /* terminate list */
1525};
1526
1527static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops,
1528 pm8001_pci_suspend,
1529 pm8001_pci_resume);
1530
1531static struct pci_driver pm8001_pci_driver = {
1532 .name = DRV_NAME,
1533 .id_table = pm8001_pci_table,
1534 .probe = pm8001_pci_probe,
1535 .remove = pm8001_pci_remove,
1536 .driver.pm = &pm8001_pci_pm_ops,
1537};
1538
1539/**
1540 * pm8001_init - initialize scsi transport template
1541 */
1542static int __init pm8001_init(void)
1543{
1544 int rc = -ENOMEM;
1545
1546 if (pm8001_use_tasklet && !pm8001_use_msix)
1547 pm8001_use_tasklet = false;
1548
1549 pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1550 if (!pm8001_wq)
1551 goto err;
1552
1553 pm8001_id = 0;
1554 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1555 if (!pm8001_stt)
1556 goto err_wq;
1557 rc = pci_register_driver(&pm8001_pci_driver);
1558 if (rc)
1559 goto err_tp;
1560 return 0;
1561
1562err_tp:
1563 sas_release_transport(pm8001_stt);
1564err_wq:
1565 destroy_workqueue(pm8001_wq);
1566err:
1567 return rc;
1568}
1569
1570static void __exit pm8001_exit(void)
1571{
1572 pci_unregister_driver(&pm8001_pci_driver);
1573 sas_release_transport(pm8001_stt);
1574 destroy_workqueue(pm8001_wq);
1575}
1576
1577module_init(pm8001_init);
1578module_exit(pm8001_exit);
1579
1580MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1581MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1582MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1583MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1584MODULE_DESCRIPTION(
1585 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1586 "SAS/SATA controller driver");
1587MODULE_VERSION(DRV_VERSION);
1588MODULE_LICENSE("GPL");
1589MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1590