1/*
   2 *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3 *           monitoring.
   4 *
   5 *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6 *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7 *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8 *  Fan Controller)
   9 *
  10 *  This driver supports only the Environment Controller in the IT8705F and
  11 *  similar parts.  The other devices are supported by different drivers.
  12 *
  13 *  Supports: IT8603E  Super I/O chip w/LPC interface
  14 *            IT8620E  Super I/O chip w/LPC interface
 
  15 *            IT8623E  Super I/O chip w/LPC interface
  16 *            IT8628E  Super I/O chip w/LPC interface
  17 *            IT8705F  Super I/O chip w/LPC interface
  18 *            IT8712F  Super I/O chip w/LPC interface
  19 *            IT8716F  Super I/O chip w/LPC interface
  20 *            IT8718F  Super I/O chip w/LPC interface
  21 *            IT8720F  Super I/O chip w/LPC interface
  22 *            IT8721F  Super I/O chip w/LPC interface
  23 *            IT8726F  Super I/O chip w/LPC interface
  24 *            IT8728F  Super I/O chip w/LPC interface
  25 *            IT8732F  Super I/O chip w/LPC interface
  26 *            IT8758E  Super I/O chip w/LPC interface
  27 *            IT8771E  Super I/O chip w/LPC interface
  28 *            IT8772E  Super I/O chip w/LPC interface
  29 *            IT8781F  Super I/O chip w/LPC interface
  30 *            IT8782F  Super I/O chip w/LPC interface
  31 *            IT8783E/F Super I/O chip w/LPC interface
  32 *            IT8786E  Super I/O chip w/LPC interface
  33 *            IT8790E  Super I/O chip w/LPC interface
 
  34 *            Sis950   A clone of the IT8705F
  35 *
  36 *  Copyright (C) 2001 Chris Gauthron
  37 *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  38 *
  39 *  This program is free software; you can redistribute it and/or modify
  40 *  it under the terms of the GNU General Public License as published by
  41 *  the Free Software Foundation; either version 2 of the License, or
  42 *  (at your option) any later version.
  43 *
  44 *  This program is distributed in the hope that it will be useful,
  45 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  46 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  47 *  GNU General Public License for more details.
  48 */
  49
  50#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  51
  52#include <linux/bitops.h>
  53#include <linux/module.h>
  54#include <linux/init.h>
  55#include <linux/slab.h>
  56#include <linux/jiffies.h>
  57#include <linux/platform_device.h>
  58#include <linux/hwmon.h>
  59#include <linux/hwmon-sysfs.h>
  60#include <linux/hwmon-vid.h>
  61#include <linux/err.h>
  62#include <linux/mutex.h>
  63#include <linux/sysfs.h>
  64#include <linux/string.h>
  65#include <linux/dmi.h>
  66#include <linux/acpi.h>
  67#include <linux/io.h>
  68
  69#define DRVNAME "it87"
  70
  71enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  72	     it8771, it8772, it8781, it8782, it8783, it8786, it8790, it8603,
  73	     it8620, it8628 };
  74
  75static unsigned short force_id;
  76module_param(force_id, ushort, 0);
  77MODULE_PARM_DESC(force_id, "Override the detected device ID");
  78
 
 
 
 
  79static struct platform_device *it87_pdev[2];
  80
  81#define	REG_2E	0x2e	/* The register to read/write */
  82#define	REG_4E	0x4e	/* Secondary register to read/write */
  83
  84#define	DEV	0x07	/* Register: Logical device select */
  85#define PME	0x04	/* The device with the fan registers in it */
  86
  87/* The device with the IT8718F/IT8720F VID value in it */
  88#define GPIO	0x07
  89
  90#define	DEVID	0x20	/* Register: Device ID */
  91#define	DEVREV	0x22	/* Register: Device Revision */
  92
  93static inline int superio_inb(int ioreg, int reg)
  94{
  95	outb(reg, ioreg);
  96	return inb(ioreg + 1);
  97}
  98
  99static inline void superio_outb(int ioreg, int reg, int val)
 100{
 101	outb(reg, ioreg);
 102	outb(val, ioreg + 1);
 103}
 104
 105static int superio_inw(int ioreg, int reg)
 106{
 107	int val;
 108
 109	outb(reg++, ioreg);
 110	val = inb(ioreg + 1) << 8;
 111	outb(reg, ioreg);
 112	val |= inb(ioreg + 1);
 113	return val;
 114}
 115
 116static inline void superio_select(int ioreg, int ldn)
 117{
 118	outb(DEV, ioreg);
 119	outb(ldn, ioreg + 1);
 120}
 121
 122static inline int superio_enter(int ioreg)
 123{
 124	/*
 125	 * Try to reserve ioreg and ioreg + 1 for exclusive access.
 126	 */
 127	if (!request_muxed_region(ioreg, 2, DRVNAME))
 128		return -EBUSY;
 129
 130	outb(0x87, ioreg);
 131	outb(0x01, ioreg);
 132	outb(0x55, ioreg);
 133	outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 134	return 0;
 135}
 136
 137static inline void superio_exit(int ioreg)
 138{
 139	outb(0x02, ioreg);
 140	outb(0x02, ioreg + 1);
 141	release_region(ioreg, 2);
 142}
 143
 144/* Logical device 4 registers */
 145#define IT8712F_DEVID 0x8712
 146#define IT8705F_DEVID 0x8705
 147#define IT8716F_DEVID 0x8716
 148#define IT8718F_DEVID 0x8718
 149#define IT8720F_DEVID 0x8720
 150#define IT8721F_DEVID 0x8721
 151#define IT8726F_DEVID 0x8726
 152#define IT8728F_DEVID 0x8728
 153#define IT8732F_DEVID 0x8732
 
 154#define IT8771E_DEVID 0x8771
 155#define IT8772E_DEVID 0x8772
 156#define IT8781F_DEVID 0x8781
 157#define IT8782F_DEVID 0x8782
 158#define IT8783E_DEVID 0x8783
 159#define IT8786E_DEVID 0x8786
 160#define IT8790E_DEVID 0x8790
 161#define IT8603E_DEVID 0x8603
 162#define IT8620E_DEVID 0x8620
 
 163#define IT8623E_DEVID 0x8623
 164#define IT8628E_DEVID 0x8628
 165#define IT87_ACT_REG  0x30
 166#define IT87_BASE_REG 0x60
 167
 168/* Logical device 7 registers (IT8712F and later) */
 169#define IT87_SIO_GPIO1_REG	0x25
 170#define IT87_SIO_GPIO2_REG	0x26
 171#define IT87_SIO_GPIO3_REG	0x27
 172#define IT87_SIO_GPIO4_REG	0x28
 173#define IT87_SIO_GPIO5_REG	0x29
 174#define IT87_SIO_PINX1_REG	0x2a	/* Pin selection */
 175#define IT87_SIO_PINX2_REG	0x2c	/* Pin selection */
 176#define IT87_SIO_SPI_REG	0xef	/* SPI function pin select */
 177#define IT87_SIO_VID_REG	0xfc	/* VID value */
 178#define IT87_SIO_BEEP_PIN_REG	0xf6	/* Beep pin mapping */
 179
 180/* Update battery voltage after every reading if true */
 181static bool update_vbat;
 182
 183/* Not all BIOSes properly configure the PWM registers */
 184static bool fix_pwm_polarity;
 185
 186/* Many IT87 constants specified below */
 187
 188/* Length of ISA address segment */
 189#define IT87_EXTENT 8
 190
 191/* Length of ISA address segment for Environmental Controller */
 192#define IT87_EC_EXTENT 2
 193
 194/* Offset of EC registers from ISA base address */
 195#define IT87_EC_OFFSET 5
 196
 197/* Where are the ISA address/data registers relative to the EC base address */
 198#define IT87_ADDR_REG_OFFSET 0
 199#define IT87_DATA_REG_OFFSET 1
 200
 201/*----- The IT87 registers -----*/
 202
 203#define IT87_REG_CONFIG        0x00
 204
 205#define IT87_REG_ALARM1        0x01
 206#define IT87_REG_ALARM2        0x02
 207#define IT87_REG_ALARM3        0x03
 208
 209/*
 210 * The IT8718F and IT8720F have the VID value in a different register, in
 211 * Super-I/O configuration space.
 212 */
 213#define IT87_REG_VID           0x0a
 214/*
 215 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 216 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 217 * mode.
 218 */
 219#define IT87_REG_FAN_DIV       0x0b
 220#define IT87_REG_FAN_16BIT     0x0c
 221
 222/*
 223 * Monitors:
 224 * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 225 * - up to 6 temp (1 to 6)
 226 * - up to 6 fan (1 to 6)
 227 */
 228
 229static const u8 IT87_REG_FAN[]         = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 230static const u8 IT87_REG_FAN_MIN[]     = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 231static const u8 IT87_REG_FANX[]        = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 232static const u8 IT87_REG_FANX_MIN[]    = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 233static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
 234
 235#define IT87_REG_FAN_MAIN_CTRL 0x13
 236#define IT87_REG_FAN_CTL       0x14
 237static const u8 IT87_REG_PWM[]         = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 238static const u8 IT87_REG_PWM_DUTY[]    = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 239
 240static const u8 IT87_REG_VIN[]	= { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 241				    0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 242
 243#define IT87_REG_TEMP(nr)      (0x29 + (nr))
 244
 245#define IT87_REG_VIN_MAX(nr)   (0x30 + (nr) * 2)
 246#define IT87_REG_VIN_MIN(nr)   (0x31 + (nr) * 2)
 247#define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
 248#define IT87_REG_TEMP_LOW(nr)  (0x41 + (nr) * 2)
 249
 250#define IT87_REG_VIN_ENABLE    0x50
 251#define IT87_REG_TEMP_ENABLE   0x51
 252#define IT87_REG_TEMP_EXTRA    0x55
 253#define IT87_REG_BEEP_ENABLE   0x5c
 254
 255#define IT87_REG_CHIPID        0x58
 256
 257static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 258
 259#define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 260#define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 261
 262#define IT87_REG_TEMP456_ENABLE	0x77
 263
 264#define NUM_VIN			ARRAY_SIZE(IT87_REG_VIN)
 265#define NUM_VIN_LIMIT		8
 266#define NUM_TEMP		6
 267#define NUM_TEMP_OFFSET		ARRAY_SIZE(IT87_REG_TEMP_OFFSET)
 268#define NUM_TEMP_LIMIT		3
 269#define NUM_FAN			ARRAY_SIZE(IT87_REG_FAN)
 270#define NUM_FAN_DIV		3
 271#define NUM_PWM			ARRAY_SIZE(IT87_REG_PWM)
 272#define NUM_AUTO_PWM		ARRAY_SIZE(IT87_REG_PWM)
 273
 274struct it87_devices {
 275	const char *name;
 276	const char * const suffix;
 277	u32 features;
 278	u8 peci_mask;
 279	u8 old_peci_mask;
 280};
 281
 282#define FEAT_12MV_ADC		BIT(0)
 283#define FEAT_NEWER_AUTOPWM	BIT(1)
 284#define FEAT_OLD_AUTOPWM	BIT(2)
 285#define FEAT_16BIT_FANS		BIT(3)
 286#define FEAT_TEMP_OFFSET	BIT(4)
 287#define FEAT_TEMP_PECI		BIT(5)
 288#define FEAT_TEMP_OLD_PECI	BIT(6)
 289#define FEAT_FAN16_CONFIG	BIT(7)	/* Need to enable 16-bit fans */
 290#define FEAT_FIVE_FANS		BIT(8)	/* Supports five fans */
 291#define FEAT_VID		BIT(9)	/* Set if chip supports VID */
 292#define FEAT_IN7_INTERNAL	BIT(10)	/* Set if in7 is internal */
 293#define FEAT_SIX_FANS		BIT(11)	/* Supports six fans */
 294#define FEAT_10_9MV_ADC		BIT(12)
 295#define FEAT_AVCC3		BIT(13)	/* Chip supports in9/AVCC3 */
 296#define FEAT_SIX_PWM		BIT(14)	/* Chip supports 6 pwm chn */
 297#define FEAT_PWM_FREQ2		BIT(15)	/* Separate pwm freq 2 */
 298#define FEAT_SIX_TEMP		BIT(16)	/* Up to 6 temp sensors */
 
 
 299
 300static const struct it87_devices it87_devices[] = {
 301	[it87] = {
 302		.name = "it87",
 303		.suffix = "F",
 304		.features = FEAT_OLD_AUTOPWM,	/* may need to overwrite */
 305	},
 306	[it8712] = {
 307		.name = "it8712",
 308		.suffix = "F",
 309		.features = FEAT_OLD_AUTOPWM | FEAT_VID,
 310						/* may need to overwrite */
 311	},
 312	[it8716] = {
 313		.name = "it8716",
 314		.suffix = "F",
 315		.features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
 316		  | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2,
 317	},
 318	[it8718] = {
 319		.name = "it8718",
 320		.suffix = "F",
 321		.features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
 322		  | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 323		  | FEAT_PWM_FREQ2,
 324		.old_peci_mask = 0x4,
 325	},
 326	[it8720] = {
 327		.name = "it8720",
 328		.suffix = "F",
 329		.features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
 330		  | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 331		  | FEAT_PWM_FREQ2,
 332		.old_peci_mask = 0x4,
 333	},
 334	[it8721] = {
 335		.name = "it8721",
 336		.suffix = "F",
 337		.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 338		  | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 339		  | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 340		  | FEAT_PWM_FREQ2,
 341		.peci_mask = 0x05,
 342		.old_peci_mask = 0x02,	/* Actually reports PCH */
 343	},
 344	[it8728] = {
 345		.name = "it8728",
 346		.suffix = "F",
 347		.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 348		  | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 349		  | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2,
 350		.peci_mask = 0x07,
 351	},
 352	[it8732] = {
 353		.name = "it8732",
 354		.suffix = "F",
 355		.features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 356		  | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 357		  | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL,
 358		.peci_mask = 0x07,
 359		.old_peci_mask = 0x02,	/* Actually reports PCH */
 360	},
 361	[it8771] = {
 362		.name = "it8771",
 363		.suffix = "E",
 364		.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 365		  | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 366		  | FEAT_PWM_FREQ2,
 367				/* PECI: guesswork */
 368				/* 12mV ADC (OHM) */
 369				/* 16 bit fans (OHM) */
 370				/* three fans, always 16 bit (guesswork) */
 371		.peci_mask = 0x07,
 372	},
 373	[it8772] = {
 374		.name = "it8772",
 375		.suffix = "E",
 376		.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 377		  | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 378		  | FEAT_PWM_FREQ2,
 379				/* PECI (coreboot) */
 380				/* 12mV ADC (HWSensors4, OHM) */
 381				/* 16 bit fans (HWSensors4, OHM) */
 382				/* three fans, always 16 bit (datasheet) */
 383		.peci_mask = 0x07,
 384	},
 385	[it8781] = {
 386		.name = "it8781",
 387		.suffix = "F",
 388		.features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
 389		  | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
 390		.old_peci_mask = 0x4,
 391	},
 392	[it8782] = {
 393		.name = "it8782",
 394		.suffix = "F",
 395		.features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
 396		  | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
 397		.old_peci_mask = 0x4,
 398	},
 399	[it8783] = {
 400		.name = "it8783",
 401		.suffix = "E/F",
 402		.features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
 403		  | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
 404		.old_peci_mask = 0x4,
 405	},
 406	[it8786] = {
 407		.name = "it8786",
 408		.suffix = "E",
 409		.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 410		  | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 411		  | FEAT_PWM_FREQ2,
 412		.peci_mask = 0x07,
 413	},
 414	[it8790] = {
 415		.name = "it8790",
 416		.suffix = "E",
 417		.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 418		  | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 419		  | FEAT_PWM_FREQ2,
 420		.peci_mask = 0x07,
 421	},
 
 
 
 
 
 
 
 
 
 422	[it8603] = {
 423		.name = "it8603",
 424		.suffix = "E",
 425		.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 426		  | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 427		  | FEAT_AVCC3 | FEAT_PWM_FREQ2,
 428		.peci_mask = 0x07,
 429	},
 430	[it8620] = {
 431		.name = "it8620",
 432		.suffix = "E",
 433		.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 434		  | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
 435		  | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 436		  | FEAT_SIX_TEMP,
 
 
 
 
 
 
 
 
 
 437		.peci_mask = 0x07,
 438	},
 439	[it8628] = {
 440		.name = "it8628",
 441		.suffix = "E",
 442		.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 443		  | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
 444		  | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 445		  | FEAT_SIX_TEMP,
 446		.peci_mask = 0x07,
 447	},
 448};
 449
 450#define has_16bit_fans(data)	((data)->features & FEAT_16BIT_FANS)
 451#define has_12mv_adc(data)	((data)->features & FEAT_12MV_ADC)
 452#define has_10_9mv_adc(data)	((data)->features & FEAT_10_9MV_ADC)
 453#define has_newer_autopwm(data)	((data)->features & FEAT_NEWER_AUTOPWM)
 454#define has_old_autopwm(data)	((data)->features & FEAT_OLD_AUTOPWM)
 455#define has_temp_offset(data)	((data)->features & FEAT_TEMP_OFFSET)
 456#define has_temp_peci(data, nr)	(((data)->features & FEAT_TEMP_PECI) && \
 457				 ((data)->peci_mask & BIT(nr)))
 458#define has_temp_old_peci(data, nr) \
 459				(((data)->features & FEAT_TEMP_OLD_PECI) && \
 460				 ((data)->old_peci_mask & BIT(nr)))
 461#define has_fan16_config(data)	((data)->features & FEAT_FAN16_CONFIG)
 462#define has_five_fans(data)	((data)->features & (FEAT_FIVE_FANS | \
 463						     FEAT_SIX_FANS))
 464#define has_vid(data)		((data)->features & FEAT_VID)
 465#define has_in7_internal(data)	((data)->features & FEAT_IN7_INTERNAL)
 466#define has_six_fans(data)	((data)->features & FEAT_SIX_FANS)
 467#define has_avcc3(data)		((data)->features & FEAT_AVCC3)
 
 
 468#define has_six_pwm(data)	((data)->features & FEAT_SIX_PWM)
 469#define has_pwm_freq2(data)	((data)->features & FEAT_PWM_FREQ2)
 470#define has_six_temp(data)	((data)->features & FEAT_SIX_TEMP)
 
 471
 472struct it87_sio_data {
 
 473	enum chips type;
 474	/* Values read from Super-I/O config space */
 475	u8 revision;
 476	u8 vid_value;
 477	u8 beep_pin;
 478	u8 internal;	/* Internal sensors can be labeled */
 
 479	/* Features skipped based on config or DMI */
 480	u16 skip_in;
 481	u8 skip_vid;
 482	u8 skip_fan;
 483	u8 skip_pwm;
 484	u8 skip_temp;
 485};
 486
 487/*
 488 * For each registered chip, we need to keep some data in memory.
 489 * The structure is dynamically allocated.
 490 */
 491struct it87_data {
 492	const struct attribute_group *groups[7];
 
 493	enum chips type;
 494	u32 features;
 495	u8 peci_mask;
 496	u8 old_peci_mask;
 497
 498	unsigned short addr;
 499	const char *name;
 500	struct mutex update_lock;
 501	char valid;		/* !=0 if following fields are valid */
 502	unsigned long last_updated;	/* In jiffies */
 503
 504	u16 in_scaled;		/* Internal voltage sensors are scaled */
 505	u16 in_internal;	/* Bitfield, internal sensors (for labels) */
 506	u16 has_in;		/* Bitfield, voltage sensors enabled */
 507	u8 in[NUM_VIN][3];		/* [nr][0]=in, [1]=min, [2]=max */
 
 508	u8 has_fan;		/* Bitfield, fans enabled */
 509	u16 fan[NUM_FAN][2];	/* Register values, [nr][0]=fan, [1]=min */
 510	u8 has_temp;		/* Bitfield, temp sensors enabled */
 511	s8 temp[NUM_TEMP][4];	/* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 512	u8 sensor;		/* Register value (IT87_REG_TEMP_ENABLE) */
 513	u8 extra;		/* Register value (IT87_REG_TEMP_EXTRA) */
 514	u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 515	bool has_vid;		/* True if VID supported */
 516	u8 vid;			/* Register encoding, combined */
 517	u8 vrm;
 518	u32 alarms;		/* Register encoding, combined */
 519	bool has_beep;		/* true if beep supported */
 520	u8 beeps;		/* Register encoding */
 521	u8 fan_main_ctrl;	/* Register value */
 522	u8 fan_ctl;		/* Register value */
 523
 524	/*
 525	 * The following 3 arrays correspond to the same registers up to
 526	 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 527	 * 7, and we want to preserve settings on mode changes, so we have
 528	 * to track all values separately.
 529	 * Starting with the IT8721F, the manual PWM duty cycles are stored
 530	 * in separate registers (8-bit values), so the separate tracking
 531	 * is no longer needed, but it is still done to keep the driver
 532	 * simple.
 533	 */
 534	u8 has_pwm;		/* Bitfield, pwm control enabled */
 535	u8 pwm_ctrl[NUM_PWM];	/* Register value */
 536	u8 pwm_duty[NUM_PWM];	/* Manual PWM value set by user */
 537	u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 538
 539	/* Automatic fan speed control registers */
 540	u8 auto_pwm[NUM_AUTO_PWM][4];	/* [nr][3] is hard-coded */
 541	s8 auto_temp[NUM_AUTO_PWM][5];	/* [nr][0] is point1_temp_hyst */
 542};
 543
 
 
 
 
 
 
 
 
 544static int adc_lsb(const struct it87_data *data, int nr)
 545{
 546	int lsb;
 547
 548	if (has_12mv_adc(data))
 549		lsb = 120;
 550	else if (has_10_9mv_adc(data))
 551		lsb = 109;
 552	else
 553		lsb = 160;
 554	if (data->in_scaled & BIT(nr))
 555		lsb <<= 1;
 556	return lsb;
 557}
 558
 559static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 560{
 561	val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 562	return clamp_val(val, 0, 255);
 563}
 564
 565static int in_from_reg(const struct it87_data *data, int nr, int val)
 566{
 567	return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 568}
 569
 570static inline u8 FAN_TO_REG(long rpm, int div)
 571{
 572	if (rpm == 0)
 573		return 255;
 574	rpm = clamp_val(rpm, 1, 1000000);
 575	return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 576}
 577
 578static inline u16 FAN16_TO_REG(long rpm)
 579{
 580	if (rpm == 0)
 581		return 0xffff;
 582	return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 583}
 584
 585#define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 586				1350000 / ((val) * (div)))
 587/* The divider is fixed to 2 in 16-bit mode */
 588#define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 589			     1350000 / ((val) * 2))
 590
 591#define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 592				    ((val) + 500) / 1000), -128, 127))
 593#define TEMP_FROM_REG(val) ((val) * 1000)
 594
 595static u8 pwm_to_reg(const struct it87_data *data, long val)
 596{
 597	if (has_newer_autopwm(data))
 598		return val;
 599	else
 600		return val >> 1;
 601}
 602
 603static int pwm_from_reg(const struct it87_data *data, u8 reg)
 604{
 605	if (has_newer_autopwm(data))
 606		return reg;
 607	else
 608		return (reg & 0x7f) << 1;
 609}
 610
 611static int DIV_TO_REG(int val)
 612{
 613	int answer = 0;
 614
 615	while (answer < 7 && (val >>= 1))
 616		answer++;
 617	return answer;
 618}
 619
 620#define DIV_FROM_REG(val) BIT(val)
 621
 622/*
 623 * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 624 * depending on the chip type, to calculate the actual PWM frequency.
 625 *
 626 * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 627 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 628 * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 629 * sometimes just one. It is unknown if this is a datasheet error or real,
 630 * so this is ignored for now.
 631 */
 632static const unsigned int pwm_freq[8] = {
 633	48000000,
 634	24000000,
 635	12000000,
 636	8000000,
 637	6000000,
 638	3000000,
 639	1500000,
 640	750000,
 641};
 642
 643/*
 644 * Must be called with data->update_lock held, except during initialization.
 645 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 646 * would slow down the IT87 access and should not be necessary.
 647 */
 648static int it87_read_value(struct it87_data *data, u8 reg)
 649{
 650	outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 651	return inb_p(data->addr + IT87_DATA_REG_OFFSET);
 652}
 653
 654/*
 655 * Must be called with data->update_lock held, except during initialization.
 656 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
 657 * would slow down the IT87 access and should not be necessary.
 658 */
 659static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
 660{
 661	outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
 662	outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
 663}
 664
 665static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
 666{
 667	data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]);
 668	if (has_newer_autopwm(data)) {
 669		data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
 670		data->pwm_duty[nr] = it87_read_value(data,
 671						     IT87_REG_PWM_DUTY[nr]);
 672	} else {
 673		if (data->pwm_ctrl[nr] & 0x80)	/* Automatic mode */
 674			data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
 675		else				/* Manual mode */
 676			data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
 677	}
 678
 679	if (has_old_autopwm(data)) {
 680		int i;
 681
 682		for (i = 0; i < 5 ; i++)
 683			data->auto_temp[nr][i] = it87_read_value(data,
 684						IT87_REG_AUTO_TEMP(nr, i));
 685		for (i = 0; i < 3 ; i++)
 686			data->auto_pwm[nr][i] = it87_read_value(data,
 687						IT87_REG_AUTO_PWM(nr, i));
 688	} else if (has_newer_autopwm(data)) {
 689		int i;
 690
 691		/*
 692		 * 0: temperature hysteresis (base + 5)
 693		 * 1: fan off temperature (base + 0)
 694		 * 2: fan start temperature (base + 1)
 695		 * 3: fan max temperature (base + 2)
 696		 */
 697		data->auto_temp[nr][0] =
 698			it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
 699
 700		for (i = 0; i < 3 ; i++)
 701			data->auto_temp[nr][i + 1] =
 702				it87_read_value(data,
 703						IT87_REG_AUTO_TEMP(nr, i));
 704		/*
 705		 * 0: start pwm value (base + 3)
 706		 * 1: pwm slope (base + 4, 1/8th pwm)
 707		 */
 708		data->auto_pwm[nr][0] =
 709			it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
 710		data->auto_pwm[nr][1] =
 711			it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
 712	}
 713}
 714
 715static struct it87_data *it87_update_device(struct device *dev)
 716{
 717	struct it87_data *data = dev_get_drvdata(dev);
 718	int i;
 719
 720	mutex_lock(&data->update_lock);
 721
 722	if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
 723	    !data->valid) {
 724		if (update_vbat) {
 725			/*
 726			 * Cleared after each update, so reenable.  Value
 727			 * returned by this read will be previous value
 728			 */
 729			it87_write_value(data, IT87_REG_CONFIG,
 730				it87_read_value(data, IT87_REG_CONFIG) | 0x40);
 731		}
 732		for (i = 0; i < NUM_VIN; i++) {
 733			if (!(data->has_in & BIT(i)))
 734				continue;
 735
 736			data->in[i][0] =
 737				it87_read_value(data, IT87_REG_VIN[i]);
 738
 739			/* VBAT and AVCC don't have limit registers */
 740			if (i >= NUM_VIN_LIMIT)
 741				continue;
 742
 743			data->in[i][1] =
 744				it87_read_value(data, IT87_REG_VIN_MIN(i));
 745			data->in[i][2] =
 746				it87_read_value(data, IT87_REG_VIN_MAX(i));
 747		}
 748
 749		for (i = 0; i < NUM_FAN; i++) {
 750			/* Skip disabled fans */
 751			if (!(data->has_fan & BIT(i)))
 752				continue;
 753
 754			data->fan[i][1] =
 755				it87_read_value(data, IT87_REG_FAN_MIN[i]);
 756			data->fan[i][0] = it87_read_value(data,
 757				       IT87_REG_FAN[i]);
 758			/* Add high byte if in 16-bit mode */
 759			if (has_16bit_fans(data)) {
 760				data->fan[i][0] |= it87_read_value(data,
 761						IT87_REG_FANX[i]) << 8;
 762				data->fan[i][1] |= it87_read_value(data,
 763						IT87_REG_FANX_MIN[i]) << 8;
 764			}
 765		}
 766		for (i = 0; i < NUM_TEMP; i++) {
 767			if (!(data->has_temp & BIT(i)))
 768				continue;
 769			data->temp[i][0] =
 770				it87_read_value(data, IT87_REG_TEMP(i));
 771
 772			if (has_temp_offset(data) && i < NUM_TEMP_OFFSET)
 773				data->temp[i][3] =
 774				  it87_read_value(data,
 775						  IT87_REG_TEMP_OFFSET[i]);
 776
 777			if (i >= NUM_TEMP_LIMIT)
 778				continue;
 779
 780			data->temp[i][1] =
 781				it87_read_value(data, IT87_REG_TEMP_LOW(i));
 782			data->temp[i][2] =
 783				it87_read_value(data, IT87_REG_TEMP_HIGH(i));
 784		}
 785
 786		/* Newer chips don't have clock dividers */
 787		if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
 788			i = it87_read_value(data, IT87_REG_FAN_DIV);
 789			data->fan_div[0] = i & 0x07;
 790			data->fan_div[1] = (i >> 3) & 0x07;
 791			data->fan_div[2] = (i & 0x40) ? 3 : 1;
 792		}
 793
 794		data->alarms =
 795			it87_read_value(data, IT87_REG_ALARM1) |
 796			(it87_read_value(data, IT87_REG_ALARM2) << 8) |
 797			(it87_read_value(data, IT87_REG_ALARM3) << 16);
 798		data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
 799
 800		data->fan_main_ctrl = it87_read_value(data,
 801				IT87_REG_FAN_MAIN_CTRL);
 802		data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
 803		for (i = 0; i < NUM_PWM; i++) {
 804			if (!(data->has_pwm & BIT(i)))
 805				continue;
 806			it87_update_pwm_ctrl(data, i);
 807		}
 808
 809		data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
 810		data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
 811		/*
 812		 * The IT8705F does not have VID capability.
 813		 * The IT8718F and later don't use IT87_REG_VID for the
 814		 * same purpose.
 815		 */
 816		if (data->type == it8712 || data->type == it8716) {
 817			data->vid = it87_read_value(data, IT87_REG_VID);
 818			/*
 819			 * The older IT8712F revisions had only 5 VID pins,
 820			 * but we assume it is always safe to read 6 bits.
 821			 */
 822			data->vid &= 0x3f;
 823		}
 824		data->last_updated = jiffies;
 825		data->valid = 1;
 826	}
 827
 828	mutex_unlock(&data->update_lock);
 829
 830	return data;
 831}
 832
 833static ssize_t show_in(struct device *dev, struct device_attribute *attr,
 834		       char *buf)
 835{
 836	struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
 837	struct it87_data *data = it87_update_device(dev);
 838	int index = sattr->index;
 839	int nr = sattr->nr;
 840
 841	return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
 842}
 843
 844static ssize_t set_in(struct device *dev, struct device_attribute *attr,
 845		      const char *buf, size_t count)
 846{
 847	struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
 848	struct it87_data *data = dev_get_drvdata(dev);
 849	int index = sattr->index;
 850	int nr = sattr->nr;
 851	unsigned long val;
 852
 853	if (kstrtoul(buf, 10, &val) < 0)
 854		return -EINVAL;
 855
 856	mutex_lock(&data->update_lock);
 857	data->in[nr][index] = in_to_reg(data, nr, val);
 858	it87_write_value(data,
 859			 index == 1 ? IT87_REG_VIN_MIN(nr)
 860				    : IT87_REG_VIN_MAX(nr),
 861			 data->in[nr][index]);
 862	mutex_unlock(&data->update_lock);
 863	return count;
 864}
 865
 866static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
 867static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
 868			    0, 1);
 869static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
 870			    0, 2);
 871
 872static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
 873static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
 874			    1, 1);
 875static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
 876			    1, 2);
 877
 878static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
 879static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
 880			    2, 1);
 881static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
 882			    2, 2);
 883
 884static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
 885static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
 886			    3, 1);
 887static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
 888			    3, 2);
 889
 890static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
 891static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
 892			    4, 1);
 893static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
 894			    4, 2);
 895
 896static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
 897static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
 898			    5, 1);
 899static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
 900			    5, 2);
 901
 902static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
 903static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
 904			    6, 1);
 905static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
 906			    6, 2);
 907
 908static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
 909static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
 910			    7, 1);
 911static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
 912			    7, 2);
 913
 914static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
 915static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
 916static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
 917static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
 918static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
 919
 920/* Up to 6 temperatures */
 921static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
 922			 char *buf)
 923{
 924	struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
 925	int nr = sattr->nr;
 926	int index = sattr->index;
 927	struct it87_data *data = it87_update_device(dev);
 928
 929	return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
 930}
 931
 932static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
 933			const char *buf, size_t count)
 934{
 935	struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
 936	int nr = sattr->nr;
 937	int index = sattr->index;
 938	struct it87_data *data = dev_get_drvdata(dev);
 939	long val;
 940	u8 reg, regval;
 941
 942	if (kstrtol(buf, 10, &val) < 0)
 943		return -EINVAL;
 944
 945	mutex_lock(&data->update_lock);
 946
 947	switch (index) {
 948	default:
 949	case 1:
 950		reg = IT87_REG_TEMP_LOW(nr);
 951		break;
 952	case 2:
 953		reg = IT87_REG_TEMP_HIGH(nr);
 954		break;
 955	case 3:
 956		regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
 957		if (!(regval & 0x80)) {
 958			regval |= 0x80;
 959			it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
 960		}
 961		data->valid = 0;
 962		reg = IT87_REG_TEMP_OFFSET[nr];
 963		break;
 964	}
 965
 966	data->temp[nr][index] = TEMP_TO_REG(val);
 967	it87_write_value(data, reg, data->temp[nr][index]);
 968	mutex_unlock(&data->update_lock);
 969	return count;
 970}
 971
 972static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
 973static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
 974			    0, 1);
 975static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
 976			    0, 2);
 977static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
 978			    set_temp, 0, 3);
 979static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
 980static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
 981			    1, 1);
 982static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
 983			    1, 2);
 984static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
 985			    set_temp, 1, 3);
 986static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
 987static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
 988			    2, 1);
 989static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
 990			    2, 2);
 991static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
 992			    set_temp, 2, 3);
 993static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
 994static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
 995static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
 996
 997static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
 998			      char *buf)
 999{
1000	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1001	int nr = sensor_attr->index;
1002	struct it87_data *data = it87_update_device(dev);
1003	u8 reg = data->sensor;	    /* In case value is updated while used */
1004	u8 extra = data->extra;
1005
1006	if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1)) ||
1007	    (has_temp_old_peci(data, nr) && (extra & 0x80)))
1008		return sprintf(buf, "6\n");  /* Intel PECI */
1009	if (reg & (1 << nr))
1010		return sprintf(buf, "3\n");  /* thermal diode */
1011	if (reg & (8 << nr))
1012		return sprintf(buf, "4\n");  /* thermistor */
1013	return sprintf(buf, "0\n");      /* disabled */
1014}
1015
1016static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1017			     const char *buf, size_t count)
1018{
1019	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1020	int nr = sensor_attr->index;
1021
1022	struct it87_data *data = dev_get_drvdata(dev);
1023	long val;
1024	u8 reg, extra;
1025
1026	if (kstrtol(buf, 10, &val) < 0)
1027		return -EINVAL;
1028
1029	reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1030	reg &= ~(1 << nr);
1031	reg &= ~(8 << nr);
1032	if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1033		reg &= 0x3f;
1034	extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1035	if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1036		extra &= 0x7f;
1037	if (val == 2) {	/* backwards compatibility */
1038		dev_warn(dev,
1039			 "Sensor type 2 is deprecated, please use 4 instead\n");
1040		val = 4;
1041	}
1042	/* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1043	if (val == 3)
1044		reg |= 1 << nr;
1045	else if (val == 4)
1046		reg |= 8 << nr;
1047	else if (has_temp_peci(data, nr) && val == 6)
1048		reg |= (nr + 1) << 6;
1049	else if (has_temp_old_peci(data, nr) && val == 6)
1050		extra |= 0x80;
1051	else if (val != 0)
1052		return -EINVAL;
1053
1054	mutex_lock(&data->update_lock);
1055	data->sensor = reg;
1056	data->extra = extra;
1057	it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1058	if (has_temp_old_peci(data, nr))
1059		it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1060	data->valid = 0;	/* Force cache refresh */
1061	mutex_unlock(&data->update_lock);
1062	return count;
1063}
1064
1065static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1066			  set_temp_type, 0);
1067static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1068			  set_temp_type, 1);
1069static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1070			  set_temp_type, 2);
1071
1072/* 6 Fans */
1073
1074static int pwm_mode(const struct it87_data *data, int nr)
1075{
1076	if (data->type != it8603 && nr < 3 && !(data->fan_main_ctrl & BIT(nr)))
1077		return 0;				/* Full speed */
1078	if (data->pwm_ctrl[nr] & 0x80)
1079		return 2;				/* Automatic mode */
1080	if ((data->type == it8603 || nr >= 3) &&
1081	    data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1082		return 0;			/* Full speed */
1083
1084	return 1;				/* Manual mode */
1085}
1086
1087static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1088			char *buf)
1089{
1090	struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1091	int nr = sattr->nr;
1092	int index = sattr->index;
1093	int speed;
1094	struct it87_data *data = it87_update_device(dev);
1095
1096	speed = has_16bit_fans(data) ?
1097		FAN16_FROM_REG(data->fan[nr][index]) :
1098		FAN_FROM_REG(data->fan[nr][index],
1099			     DIV_FROM_REG(data->fan_div[nr]));
1100	return sprintf(buf, "%d\n", speed);
1101}
1102
1103static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1104			    char *buf)
1105{
1106	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1107	struct it87_data *data = it87_update_device(dev);
1108	int nr = sensor_attr->index;
1109
1110	return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1111}
1112
1113static ssize_t show_pwm_enable(struct device *dev,
1114			       struct device_attribute *attr, char *buf)
1115{
1116	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1117	struct it87_data *data = it87_update_device(dev);
1118	int nr = sensor_attr->index;
1119
1120	return sprintf(buf, "%d\n", pwm_mode(data, nr));
1121}
1122
1123static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1124			char *buf)
1125{
1126	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1127	struct it87_data *data = it87_update_device(dev);
1128	int nr = sensor_attr->index;
1129
1130	return sprintf(buf, "%d\n",
1131		       pwm_from_reg(data, data->pwm_duty[nr]));
1132}
1133
1134static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1135			     char *buf)
1136{
1137	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1138	struct it87_data *data = it87_update_device(dev);
1139	int nr = sensor_attr->index;
1140	unsigned int freq;
1141	int index;
1142
1143	if (has_pwm_freq2(data) && nr == 1)
1144		index = (data->extra >> 4) & 0x07;
1145	else
1146		index = (data->fan_ctl >> 4) & 0x07;
1147
1148	freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1149
1150	return sprintf(buf, "%u\n", freq);
1151}
1152
1153static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1154		       const char *buf, size_t count)
1155{
1156	struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1157	int nr = sattr->nr;
1158	int index = sattr->index;
1159
1160	struct it87_data *data = dev_get_drvdata(dev);
1161	long val;
1162	u8 reg;
1163
1164	if (kstrtol(buf, 10, &val) < 0)
1165		return -EINVAL;
1166
1167	mutex_lock(&data->update_lock);
1168
1169	if (has_16bit_fans(data)) {
1170		data->fan[nr][index] = FAN16_TO_REG(val);
1171		it87_write_value(data, IT87_REG_FAN_MIN[nr],
1172				 data->fan[nr][index] & 0xff);
1173		it87_write_value(data, IT87_REG_FANX_MIN[nr],
1174				 data->fan[nr][index] >> 8);
1175	} else {
1176		reg = it87_read_value(data, IT87_REG_FAN_DIV);
1177		switch (nr) {
1178		case 0:
1179			data->fan_div[nr] = reg & 0x07;
1180			break;
1181		case 1:
1182			data->fan_div[nr] = (reg >> 3) & 0x07;
1183			break;
1184		case 2:
1185			data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1186			break;
1187		}
1188		data->fan[nr][index] =
1189		  FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1190		it87_write_value(data, IT87_REG_FAN_MIN[nr],
1191				 data->fan[nr][index]);
1192	}
1193
1194	mutex_unlock(&data->update_lock);
1195	return count;
1196}
1197
1198static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1199			   const char *buf, size_t count)
1200{
1201	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1202	struct it87_data *data = dev_get_drvdata(dev);
1203	int nr = sensor_attr->index;
1204	unsigned long val;
1205	int min;
1206	u8 old;
1207
1208	if (kstrtoul(buf, 10, &val) < 0)
1209		return -EINVAL;
1210
1211	mutex_lock(&data->update_lock);
1212	old = it87_read_value(data, IT87_REG_FAN_DIV);
1213
1214	/* Save fan min limit */
1215	min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1216
1217	switch (nr) {
1218	case 0:
1219	case 1:
1220		data->fan_div[nr] = DIV_TO_REG(val);
1221		break;
1222	case 2:
1223		if (val < 8)
1224			data->fan_div[nr] = 1;
1225		else
1226			data->fan_div[nr] = 3;
1227	}
1228	val = old & 0x80;
1229	val |= (data->fan_div[0] & 0x07);
1230	val |= (data->fan_div[1] & 0x07) << 3;
1231	if (data->fan_div[2] == 3)
1232		val |= 0x1 << 6;
1233	it87_write_value(data, IT87_REG_FAN_DIV, val);
1234
1235	/* Restore fan min limit */
1236	data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1237	it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
1238
1239	mutex_unlock(&data->update_lock);
1240	return count;
1241}
1242
1243/* Returns 0 if OK, -EINVAL otherwise */
1244static int check_trip_points(struct device *dev, int nr)
1245{
1246	const struct it87_data *data = dev_get_drvdata(dev);
1247	int i, err = 0;
1248
1249	if (has_old_autopwm(data)) {
1250		for (i = 0; i < 3; i++) {
1251			if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1252				err = -EINVAL;
1253		}
1254		for (i = 0; i < 2; i++) {
1255			if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1256				err = -EINVAL;
1257		}
1258	} else if (has_newer_autopwm(data)) {
1259		for (i = 1; i < 3; i++) {
1260			if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1261				err = -EINVAL;
1262		}
1263	}
1264
1265	if (err) {
1266		dev_err(dev,
1267			"Inconsistent trip points, not switching to automatic mode\n");
1268		dev_err(dev, "Adjust the trip points and try again\n");
1269	}
1270	return err;
1271}
1272
1273static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1274			      const char *buf, size_t count)
1275{
1276	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1277	struct it87_data *data = dev_get_drvdata(dev);
1278	int nr = sensor_attr->index;
1279	long val;
1280
1281	if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1282		return -EINVAL;
1283
1284	/* Check trip points before switching to automatic mode */
1285	if (val == 2) {
1286		if (check_trip_points(dev, nr) < 0)
1287			return -EINVAL;
1288	}
1289
1290	mutex_lock(&data->update_lock);
1291
1292	if (val == 0) {
1293		if (nr < 3 && data->type != it8603) {
1294			int tmp;
1295			/* make sure the fan is on when in on/off mode */
1296			tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1297			it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1298			/* set on/off mode */
1299			data->fan_main_ctrl &= ~BIT(nr);
1300			it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1301					 data->fan_main_ctrl);
1302		} else {
1303			u8 ctrl;
1304
1305			/* No on/off mode, set maximum pwm value */
1306			data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1307			it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1308					 data->pwm_duty[nr]);
1309			/* and set manual mode */
1310			if (has_newer_autopwm(data)) {
1311				ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1312					data->pwm_temp_map[nr];
1313			} else {
1314				ctrl = data->pwm_duty[nr];
1315			}
1316			data->pwm_ctrl[nr] = ctrl;
1317			it87_write_value(data, IT87_REG_PWM[nr], ctrl);
1318		}
1319	} else {
1320		u8 ctrl;
1321
1322		if (has_newer_autopwm(data)) {
1323			ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1324				data->pwm_temp_map[nr];
1325			if (val != 1)
1326				ctrl |= 0x80;
1327		} else {
1328			ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1329		}
1330		data->pwm_ctrl[nr] = ctrl;
1331		it87_write_value(data, IT87_REG_PWM[nr], ctrl);
1332
1333		if (data->type != it8603 && nr < 3) {
1334			/* set SmartGuardian mode */
1335			data->fan_main_ctrl |= BIT(nr);
1336			it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1337					 data->fan_main_ctrl);
1338		}
1339	}
1340
1341	mutex_unlock(&data->update_lock);
1342	return count;
1343}
1344
1345static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1346		       const char *buf, size_t count)
1347{
1348	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1349	struct it87_data *data = dev_get_drvdata(dev);
1350	int nr = sensor_attr->index;
1351	long val;
1352
1353	if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1354		return -EINVAL;
1355
1356	mutex_lock(&data->update_lock);
1357	it87_update_pwm_ctrl(data, nr);
1358	if (has_newer_autopwm(data)) {
1359		/*
1360		 * If we are in automatic mode, the PWM duty cycle register
1361		 * is read-only so we can't write the value.
1362		 */
1363		if (data->pwm_ctrl[nr] & 0x80) {
1364			mutex_unlock(&data->update_lock);
1365			return -EBUSY;
1366		}
1367		data->pwm_duty[nr] = pwm_to_reg(data, val);
1368		it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1369				 data->pwm_duty[nr]);
1370	} else {
1371		data->pwm_duty[nr] = pwm_to_reg(data, val);
1372		/*
1373		 * If we are in manual mode, write the duty cycle immediately;
1374		 * otherwise, just store it for later use.
1375		 */
1376		if (!(data->pwm_ctrl[nr] & 0x80)) {
1377			data->pwm_ctrl[nr] = data->pwm_duty[nr];
1378			it87_write_value(data, IT87_REG_PWM[nr],
1379					 data->pwm_ctrl[nr]);
1380		}
1381	}
1382	mutex_unlock(&data->update_lock);
1383	return count;
1384}
1385
1386static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1387			    const char *buf, size_t count)
1388{
1389	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1390	struct it87_data *data = dev_get_drvdata(dev);
1391	int nr = sensor_attr->index;
1392	unsigned long val;
1393	int i;
1394
1395	if (kstrtoul(buf, 10, &val) < 0)
1396		return -EINVAL;
1397
1398	val = clamp_val(val, 0, 1000000);
1399	val *= has_newer_autopwm(data) ? 256 : 128;
1400
1401	/* Search for the nearest available frequency */
1402	for (i = 0; i < 7; i++) {
1403		if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1404			break;
1405	}
1406
1407	mutex_lock(&data->update_lock);
1408	if (nr == 0) {
1409		data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1410		data->fan_ctl |= i << 4;
1411		it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1412	} else {
1413		data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1414		data->extra |= i << 4;
1415		it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1416	}
1417	mutex_unlock(&data->update_lock);
1418
1419	return count;
1420}
1421
1422static ssize_t show_pwm_temp_map(struct device *dev,
1423				 struct device_attribute *attr, char *buf)
1424{
1425	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1426	struct it87_data *data = it87_update_device(dev);
1427	int nr = sensor_attr->index;
1428	int map;
1429
1430	map = data->pwm_temp_map[nr];
1431	if (map >= 3)
1432		map = 0;	/* Should never happen */
1433	if (nr >= 3)		/* pwm channels 3..6 map to temp4..6 */
1434		map += 3;
1435
1436	return sprintf(buf, "%d\n", (int)BIT(map));
1437}
1438
1439static ssize_t set_pwm_temp_map(struct device *dev,
1440				struct device_attribute *attr, const char *buf,
1441				size_t count)
1442{
1443	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1444	struct it87_data *data = dev_get_drvdata(dev);
1445	int nr = sensor_attr->index;
1446	long val;
1447	u8 reg;
1448
1449	if (kstrtol(buf, 10, &val) < 0)
1450		return -EINVAL;
1451
1452	if (nr >= 3)
1453		val -= 3;
1454
1455	switch (val) {
1456	case BIT(0):
1457		reg = 0x00;
1458		break;
1459	case BIT(1):
1460		reg = 0x01;
1461		break;
1462	case BIT(2):
1463		reg = 0x02;
1464		break;
1465	default:
1466		return -EINVAL;
1467	}
1468
1469	mutex_lock(&data->update_lock);
1470	it87_update_pwm_ctrl(data, nr);
1471	data->pwm_temp_map[nr] = reg;
1472	/*
1473	 * If we are in automatic mode, write the temp mapping immediately;
1474	 * otherwise, just store it for later use.
1475	 */
1476	if (data->pwm_ctrl[nr] & 0x80) {
1477		data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & 0xfc) |
1478						data->pwm_temp_map[nr];
1479		it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]);
1480	}
1481	mutex_unlock(&data->update_lock);
1482	return count;
1483}
1484
1485static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1486			     char *buf)
1487{
1488	struct it87_data *data = it87_update_device(dev);
1489	struct sensor_device_attribute_2 *sensor_attr =
1490			to_sensor_dev_attr_2(attr);
1491	int nr = sensor_attr->nr;
1492	int point = sensor_attr->index;
1493
1494	return sprintf(buf, "%d\n",
1495		       pwm_from_reg(data, data->auto_pwm[nr][point]));
1496}
1497
1498static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1499			    const char *buf, size_t count)
1500{
1501	struct it87_data *data = dev_get_drvdata(dev);
1502	struct sensor_device_attribute_2 *sensor_attr =
1503			to_sensor_dev_attr_2(attr);
1504	int nr = sensor_attr->nr;
1505	int point = sensor_attr->index;
1506	int regaddr;
1507	long val;
1508
1509	if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1510		return -EINVAL;
1511
1512	mutex_lock(&data->update_lock);
1513	data->auto_pwm[nr][point] = pwm_to_reg(data, val);
1514	if (has_newer_autopwm(data))
1515		regaddr = IT87_REG_AUTO_TEMP(nr, 3);
1516	else
1517		regaddr = IT87_REG_AUTO_PWM(nr, point);
1518	it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
1519	mutex_unlock(&data->update_lock);
1520	return count;
1521}
1522
1523static ssize_t show_auto_pwm_slope(struct device *dev,
1524				   struct device_attribute *attr, char *buf)
1525{
1526	struct it87_data *data = it87_update_device(dev);
1527	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1528	int nr = sensor_attr->index;
1529
1530	return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
1531}
1532
1533static ssize_t set_auto_pwm_slope(struct device *dev,
1534				  struct device_attribute *attr,
1535				  const char *buf, size_t count)
1536{
1537	struct it87_data *data = dev_get_drvdata(dev);
1538	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1539	int nr = sensor_attr->index;
1540	unsigned long val;
1541
1542	if (kstrtoul(buf, 10, &val) < 0 || val > 127)
1543		return -EINVAL;
1544
1545	mutex_lock(&data->update_lock);
1546	data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
1547	it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
1548			 data->auto_pwm[nr][1]);
1549	mutex_unlock(&data->update_lock);
1550	return count;
1551}
1552
1553static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1554			      char *buf)
1555{
1556	struct it87_data *data = it87_update_device(dev);
1557	struct sensor_device_attribute_2 *sensor_attr =
1558			to_sensor_dev_attr_2(attr);
1559	int nr = sensor_attr->nr;
1560	int point = sensor_attr->index;
1561	int reg;
1562
1563	if (has_old_autopwm(data) || point)
1564		reg = data->auto_temp[nr][point];
1565	else
1566		reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
1567
1568	return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
1569}
1570
1571static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1572			     const char *buf, size_t count)
1573{
1574	struct it87_data *data = dev_get_drvdata(dev);
1575	struct sensor_device_attribute_2 *sensor_attr =
1576			to_sensor_dev_attr_2(attr);
1577	int nr = sensor_attr->nr;
1578	int point = sensor_attr->index;
1579	long val;
1580	int reg;
1581
1582	if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
1583		return -EINVAL;
1584
1585	mutex_lock(&data->update_lock);
1586	if (has_newer_autopwm(data) && !point) {
1587		reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
1588		reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
1589		data->auto_temp[nr][0] = reg;
1590		it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
1591	} else {
1592		reg = TEMP_TO_REG(val);
1593		data->auto_temp[nr][point] = reg;
1594		if (has_newer_autopwm(data))
1595			point--;
1596		it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
1597	}
1598	mutex_unlock(&data->update_lock);
1599	return count;
1600}
1601
1602static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1603static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1604			    0, 1);
1605static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1606			  set_fan_div, 0);
1607
1608static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1609static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1610			    1, 1);
1611static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1612			  set_fan_div, 1);
1613
1614static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1615static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1616			    2, 1);
1617static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1618			  set_fan_div, 2);
1619
1620static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1621static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1622			    3, 1);
1623
1624static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1625static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1626			    4, 1);
1627
1628static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
1629static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1630			    5, 1);
1631
1632static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1633			  show_pwm_enable, set_pwm_enable, 0);
1634static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
1635static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
1636			  set_pwm_freq, 0);
1637static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
1638			  show_pwm_temp_map, set_pwm_temp_map, 0);
1639static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1640			    show_auto_pwm, set_auto_pwm, 0, 0);
1641static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1642			    show_auto_pwm, set_auto_pwm, 0, 1);
1643static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1644			    show_auto_pwm, set_auto_pwm, 0, 2);
1645static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1646			    show_auto_pwm, NULL, 0, 3);
1647static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1648			    show_auto_temp, set_auto_temp, 0, 1);
1649static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1650			    show_auto_temp, set_auto_temp, 0, 0);
1651static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1652			    show_auto_temp, set_auto_temp, 0, 2);
1653static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1654			    show_auto_temp, set_auto_temp, 0, 3);
1655static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1656			    show_auto_temp, set_auto_temp, 0, 4);
1657static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
1658			    show_auto_pwm, set_auto_pwm, 0, 0);
1659static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
1660			  show_auto_pwm_slope, set_auto_pwm_slope, 0);
1661
1662static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1663			  show_pwm_enable, set_pwm_enable, 1);
1664static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
1665static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
1666static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
1667			  show_pwm_temp_map, set_pwm_temp_map, 1);
1668static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1669			    show_auto_pwm, set_auto_pwm, 1, 0);
1670static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1671			    show_auto_pwm, set_auto_pwm, 1, 1);
1672static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1673			    show_auto_pwm, set_auto_pwm, 1, 2);
1674static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1675			    show_auto_pwm, NULL, 1, 3);
1676static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1677			    show_auto_temp, set_auto_temp, 1, 1);
1678static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1679			    show_auto_temp, set_auto_temp, 1, 0);
1680static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1681			    show_auto_temp, set_auto_temp, 1, 2);
1682static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1683			    show_auto_temp, set_auto_temp, 1, 3);
1684static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1685			    show_auto_temp, set_auto_temp, 1, 4);
1686static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
1687			    show_auto_pwm, set_auto_pwm, 1, 0);
1688static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
1689			  show_auto_pwm_slope, set_auto_pwm_slope, 1);
1690
1691static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
1692			  show_pwm_enable, set_pwm_enable, 2);
1693static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
1694static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
1695static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
1696			  show_pwm_temp_map, set_pwm_temp_map, 2);
1697static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
1698			    show_auto_pwm, set_auto_pwm, 2, 0);
1699static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
1700			    show_auto_pwm, set_auto_pwm, 2, 1);
1701static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
1702			    show_auto_pwm, set_auto_pwm, 2, 2);
1703static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
1704			    show_auto_pwm, NULL, 2, 3);
1705static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
1706			    show_auto_temp, set_auto_temp, 2, 1);
1707static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1708			    show_auto_temp, set_auto_temp, 2, 0);
1709static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
1710			    show_auto_temp, set_auto_temp, 2, 2);
1711static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
1712			    show_auto_temp, set_auto_temp, 2, 3);
1713static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
1714			    show_auto_temp, set_auto_temp, 2, 4);
1715static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
1716			    show_auto_pwm, set_auto_pwm, 2, 0);
1717static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
1718			  show_auto_pwm_slope, set_auto_pwm_slope, 2);
1719
1720static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
1721			  show_pwm_enable, set_pwm_enable, 3);
1722static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
1723static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
1724static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
1725			  show_pwm_temp_map, set_pwm_temp_map, 3);
1726static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
1727			    show_auto_temp, set_auto_temp, 2, 1);
1728static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1729			    show_auto_temp, set_auto_temp, 2, 0);
1730static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
1731			    show_auto_temp, set_auto_temp, 2, 2);
1732static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
1733			    show_auto_temp, set_auto_temp, 2, 3);
1734static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
1735			    show_auto_pwm, set_auto_pwm, 3, 0);
1736static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
1737			  show_auto_pwm_slope, set_auto_pwm_slope, 3);
1738
1739static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
1740			  show_pwm_enable, set_pwm_enable, 4);
1741static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
1742static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
1743static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
1744			  show_pwm_temp_map, set_pwm_temp_map, 4);
1745static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
1746			    show_auto_temp, set_auto_temp, 2, 1);
1747static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1748			    show_auto_temp, set_auto_temp, 2, 0);
1749static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
1750			    show_auto_temp, set_auto_temp, 2, 2);
1751static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
1752			    show_auto_temp, set_auto_temp, 2, 3);
1753static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
1754			    show_auto_pwm, set_auto_pwm, 4, 0);
1755static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
1756			  show_auto_pwm_slope, set_auto_pwm_slope, 4);
1757
1758static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
1759			  show_pwm_enable, set_pwm_enable, 5);
1760static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
1761static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
1762static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
1763			  show_pwm_temp_map, set_pwm_temp_map, 5);
1764static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
1765			    show_auto_temp, set_auto_temp, 2, 1);
1766static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1767			    show_auto_temp, set_auto_temp, 2, 0);
1768static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
1769			    show_auto_temp, set_auto_temp, 2, 2);
1770static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
1771			    show_auto_temp, set_auto_temp, 2, 3);
1772static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
1773			    show_auto_pwm, set_auto_pwm, 5, 0);
1774static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
1775			  show_auto_pwm_slope, set_auto_pwm_slope, 5);
1776
1777/* Alarms */
1778static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
1779			   char *buf)
1780{
1781	struct it87_data *data = it87_update_device(dev);
1782
1783	return sprintf(buf, "%u\n", data->alarms);
1784}
1785static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
1786
1787static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
1788			  char *buf)
1789{
1790	struct it87_data *data = it87_update_device(dev);
1791	int bitnr = to_sensor_dev_attr(attr)->index;
1792
1793	return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
1794}
1795
1796static ssize_t clear_intrusion(struct device *dev,
1797			       struct device_attribute *attr, const char *buf,
1798			       size_t count)
1799{
1800	struct it87_data *data = dev_get_drvdata(dev);
1801	int config;
1802	long val;
1803
1804	if (kstrtol(buf, 10, &val) < 0 || val != 0)
1805		return -EINVAL;
1806
1807	mutex_lock(&data->update_lock);
1808	config = it87_read_value(data, IT87_REG_CONFIG);
1809	if (config < 0) {
1810		count = config;
1811	} else {
1812		config |= BIT(5);
1813		it87_write_value(data, IT87_REG_CONFIG, config);
1814		/* Invalidate cache to force re-read */
1815		data->valid = 0;
1816	}
1817	mutex_unlock(&data->update_lock);
1818
1819	return count;
1820}
1821
1822static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
1823static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
1824static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
1825static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
1826static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
1827static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
1828static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
1829static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
1830static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
1831static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
1832static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
1833static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
1834static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
1835static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
1836static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
1837static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
1838static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
1839static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
1840			  show_alarm, clear_intrusion, 4);
1841
1842static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
1843			 char *buf)
1844{
1845	struct it87_data *data = it87_update_device(dev);
1846	int bitnr = to_sensor_dev_attr(attr)->index;
1847
1848	return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
1849}
1850
1851static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
1852			const char *buf, size_t count)
1853{
1854	int bitnr = to_sensor_dev_attr(attr)->index;
1855	struct it87_data *data = dev_get_drvdata(dev);
1856	long val;
1857
1858	if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
1859		return -EINVAL;
1860
1861	mutex_lock(&data->update_lock);
1862	data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1863	if (val)
1864		data->beeps |= BIT(bitnr);
1865	else
1866		data->beeps &= ~BIT(bitnr);
1867	it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
1868	mutex_unlock(&data->update_lock);
1869	return count;
1870}
1871
1872static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
1873			  show_beep, set_beep, 1);
1874static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
1875static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
1876static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
1877static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
1878static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
1879static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
1880static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
1881/* fanX_beep writability is set later */
1882static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
1883static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
1884static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
1885static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
1886static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
1887static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
1888static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
1889			  show_beep, set_beep, 2);
1890static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
1891static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
1892
1893static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
1894			    char *buf)
1895{
1896	struct it87_data *data = dev_get_drvdata(dev);
1897
1898	return sprintf(buf, "%u\n", data->vrm);
1899}
1900
1901static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
1902			     const char *buf, size_t count)
1903{
1904	struct it87_data *data = dev_get_drvdata(dev);
1905	unsigned long val;
1906
1907	if (kstrtoul(buf, 10, &val) < 0)
1908		return -EINVAL;
1909
1910	data->vrm = val;
1911
1912	return count;
1913}
1914static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
1915
1916static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
1917			    char *buf)
1918{
1919	struct it87_data *data = it87_update_device(dev);
1920
1921	return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
1922}
1923static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
1924
1925static ssize_t show_label(struct device *dev, struct device_attribute *attr,
1926			  char *buf)
1927{
1928	static const char * const labels[] = {
1929		"+5V",
1930		"5VSB",
1931		"Vbat",
 
1932	};
1933	static const char * const labels_it8721[] = {
1934		"+3.3V",
1935		"3VSB",
1936		"Vbat",
 
1937	};
1938	struct it87_data *data = dev_get_drvdata(dev);
1939	int nr = to_sensor_dev_attr(attr)->index;
1940	const char *label;
1941
1942	if (has_12mv_adc(data) || has_10_9mv_adc(data))
 
 
1943		label = labels_it8721[nr];
1944	else
1945		label = labels[nr];
1946
1947	return sprintf(buf, "%s\n", label);
1948}
1949static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
1950static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
1951static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
1952/* AVCC3 */
1953static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 0);
1954
1955static umode_t it87_in_is_visible(struct kobject *kobj,
1956				  struct attribute *attr, int index)
1957{
1958	struct device *dev = container_of(kobj, struct device, kobj);
1959	struct it87_data *data = dev_get_drvdata(dev);
1960	int i = index / 5;	/* voltage index */
1961	int a = index % 5;	/* attribute index */
1962
1963	if (index >= 40) {	/* in8 and higher only have input attributes */
1964		i = index - 40 + 8;
1965		a = 0;
1966	}
1967
1968	if (!(data->has_in & BIT(i)))
1969		return 0;
1970
1971	if (a == 4 && !data->has_beep)
1972		return 0;
1973
1974	return attr->mode;
1975}
1976
1977static struct attribute *it87_attributes_in[] = {
1978	&sensor_dev_attr_in0_input.dev_attr.attr,
1979	&sensor_dev_attr_in0_min.dev_attr.attr,
1980	&sensor_dev_attr_in0_max.dev_attr.attr,
1981	&sensor_dev_attr_in0_alarm.dev_attr.attr,
1982	&sensor_dev_attr_in0_beep.dev_attr.attr,	/* 4 */
1983
1984	&sensor_dev_attr_in1_input.dev_attr.attr,
1985	&sensor_dev_attr_in1_min.dev_attr.attr,
1986	&sensor_dev_attr_in1_max.dev_attr.attr,
1987	&sensor_dev_attr_in1_alarm.dev_attr.attr,
1988	&sensor_dev_attr_in1_beep.dev_attr.attr,	/* 9 */
1989
1990	&sensor_dev_attr_in2_input.dev_attr.attr,
1991	&sensor_dev_attr_in2_min.dev_attr.attr,
1992	&sensor_dev_attr_in2_max.dev_attr.attr,
1993	&sensor_dev_attr_in2_alarm.dev_attr.attr,
1994	&sensor_dev_attr_in2_beep.dev_attr.attr,	/* 14 */
1995
1996	&sensor_dev_attr_in3_input.dev_attr.attr,
1997	&sensor_dev_attr_in3_min.dev_attr.attr,
1998	&sensor_dev_attr_in3_max.dev_attr.attr,
1999	&sensor_dev_attr_in3_alarm.dev_attr.attr,
2000	&sensor_dev_attr_in3_beep.dev_attr.attr,	/* 19 */
2001
2002	&sensor_dev_attr_in4_input.dev_attr.attr,
2003	&sensor_dev_attr_in4_min.dev_attr.attr,
2004	&sensor_dev_attr_in4_max.dev_attr.attr,
2005	&sensor_dev_attr_in4_alarm.dev_attr.attr,
2006	&sensor_dev_attr_in4_beep.dev_attr.attr,	/* 24 */
2007
2008	&sensor_dev_attr_in5_input.dev_attr.attr,
2009	&sensor_dev_attr_in5_min.dev_attr.attr,
2010	&sensor_dev_attr_in5_max.dev_attr.attr,
2011	&sensor_dev_attr_in5_alarm.dev_attr.attr,
2012	&sensor_dev_attr_in5_beep.dev_attr.attr,	/* 29 */
2013
2014	&sensor_dev_attr_in6_input.dev_attr.attr,
2015	&sensor_dev_attr_in6_min.dev_attr.attr,
2016	&sensor_dev_attr_in6_max.dev_attr.attr,
2017	&sensor_dev_attr_in6_alarm.dev_attr.attr,
2018	&sensor_dev_attr_in6_beep.dev_attr.attr,	/* 34 */
2019
2020	&sensor_dev_attr_in7_input.dev_attr.attr,
2021	&sensor_dev_attr_in7_min.dev_attr.attr,
2022	&sensor_dev_attr_in7_max.dev_attr.attr,
2023	&sensor_dev_attr_in7_alarm.dev_attr.attr,
2024	&sensor_dev_attr_in7_beep.dev_attr.attr,	/* 39 */
2025
2026	&sensor_dev_attr_in8_input.dev_attr.attr,	/* 40 */
2027	&sensor_dev_attr_in9_input.dev_attr.attr,
2028	&sensor_dev_attr_in10_input.dev_attr.attr,
2029	&sensor_dev_attr_in11_input.dev_attr.attr,
2030	&sensor_dev_attr_in12_input.dev_attr.attr,
2031	NULL
2032};
2033
2034static const struct attribute_group it87_group_in = {
2035	.attrs = it87_attributes_in,
2036	.is_visible = it87_in_is_visible,
2037};
2038
2039static umode_t it87_temp_is_visible(struct kobject *kobj,
2040				    struct attribute *attr, int index)
2041{
2042	struct device *dev = container_of(kobj, struct device, kobj);
2043	struct it87_data *data = dev_get_drvdata(dev);
2044	int i = index / 7;	/* temperature index */
2045	int a = index % 7;	/* attribute index */
2046
2047	if (index >= 21) {
2048		i = index - 21 + 3;
2049		a = 0;
2050	}
2051
2052	if (!(data->has_temp & BIT(i)))
2053		return 0;
2054
2055	if (a == 5 && !has_temp_offset(data))
2056		return 0;
2057
2058	if (a == 6 && !data->has_beep)
2059		return 0;
2060
2061	return attr->mode;
2062}
2063
2064static struct attribute *it87_attributes_temp[] = {
2065	&sensor_dev_attr_temp1_input.dev_attr.attr,
2066	&sensor_dev_attr_temp1_max.dev_attr.attr,
2067	&sensor_dev_attr_temp1_min.dev_attr.attr,
2068	&sensor_dev_attr_temp1_type.dev_attr.attr,
2069	&sensor_dev_attr_temp1_alarm.dev_attr.attr,
2070	&sensor_dev_attr_temp1_offset.dev_attr.attr,	/* 5 */
2071	&sensor_dev_attr_temp1_beep.dev_attr.attr,	/* 6 */
2072
2073	&sensor_dev_attr_temp2_input.dev_attr.attr,	/* 7 */
2074	&sensor_dev_attr_temp2_max.dev_attr.attr,
2075	&sensor_dev_attr_temp2_min.dev_attr.attr,
2076	&sensor_dev_attr_temp2_type.dev_attr.attr,
2077	&sensor_dev_attr_temp2_alarm.dev_attr.attr,
2078	&sensor_dev_attr_temp2_offset.dev_attr.attr,
2079	&sensor_dev_attr_temp2_beep.dev_attr.attr,
2080
2081	&sensor_dev_attr_temp3_input.dev_attr.attr,	/* 14 */
2082	&sensor_dev_attr_temp3_max.dev_attr.attr,
2083	&sensor_dev_attr_temp3_min.dev_attr.attr,
2084	&sensor_dev_attr_temp3_type.dev_attr.attr,
2085	&sensor_dev_attr_temp3_alarm.dev_attr.attr,
2086	&sensor_dev_attr_temp3_offset.dev_attr.attr,
2087	&sensor_dev_attr_temp3_beep.dev_attr.attr,
2088
2089	&sensor_dev_attr_temp4_input.dev_attr.attr,	/* 21 */
2090	&sensor_dev_attr_temp5_input.dev_attr.attr,
2091	&sensor_dev_attr_temp6_input.dev_attr.attr,
2092	NULL
2093};
2094
2095static const struct attribute_group it87_group_temp = {
2096	.attrs = it87_attributes_temp,
2097	.is_visible = it87_temp_is_visible,
2098};
2099
2100static umode_t it87_is_visible(struct kobject *kobj,
2101			       struct attribute *attr, int index)
2102{
2103	struct device *dev = container_of(kobj, struct device, kobj);
2104	struct it87_data *data = dev_get_drvdata(dev);
2105
2106	if ((index == 2 || index == 3) && !data->has_vid)
2107		return 0;
2108
2109	if (index > 3 && !(data->in_internal & BIT(index - 4)))
2110		return 0;
2111
2112	return attr->mode;
2113}
2114
2115static struct attribute *it87_attributes[] = {
2116	&dev_attr_alarms.attr,
2117	&sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2118	&dev_attr_vrm.attr,				/* 2 */
2119	&dev_attr_cpu0_vid.attr,			/* 3 */
2120	&sensor_dev_attr_in3_label.dev_attr.attr,	/* 4 .. 7 */
2121	&sensor_dev_attr_in7_label.dev_attr.attr,
2122	&sensor_dev_attr_in8_label.dev_attr.attr,
2123	&sensor_dev_attr_in9_label.dev_attr.attr,
2124	NULL
2125};
2126
2127static const struct attribute_group it87_group = {
2128	.attrs = it87_attributes,
2129	.is_visible = it87_is_visible,
2130};
2131
2132static umode_t it87_fan_is_visible(struct kobject *kobj,
2133				   struct attribute *attr, int index)
2134{
2135	struct device *dev = container_of(kobj, struct device, kobj);
2136	struct it87_data *data = dev_get_drvdata(dev);
2137	int i = index / 5;	/* fan index */
2138	int a = index % 5;	/* attribute index */
2139
2140	if (index >= 15) {	/* fan 4..6 don't have divisor attributes */
2141		i = (index - 15) / 4 + 3;
2142		a = (index - 15) % 4;
2143	}
2144
2145	if (!(data->has_fan & BIT(i)))
2146		return 0;
2147
2148	if (a == 3) {				/* beep */
2149		if (!data->has_beep)
2150			return 0;
2151		/* first fan beep attribute is writable */
2152		if (i == __ffs(data->has_fan))
2153			return attr->mode | S_IWUSR;
2154	}
2155
2156	if (a == 4 && has_16bit_fans(data))	/* divisor */
2157		return 0;
2158
2159	return attr->mode;
2160}
2161
2162static struct attribute *it87_attributes_fan[] = {
2163	&sensor_dev_attr_fan1_input.dev_attr.attr,
2164	&sensor_dev_attr_fan1_min.dev_attr.attr,
2165	&sensor_dev_attr_fan1_alarm.dev_attr.attr,
2166	&sensor_dev_attr_fan1_beep.dev_attr.attr,	/* 3 */
2167	&sensor_dev_attr_fan1_div.dev_attr.attr,	/* 4 */
2168
2169	&sensor_dev_attr_fan2_input.dev_attr.attr,
2170	&sensor_dev_attr_fan2_min.dev_attr.attr,
2171	&sensor_dev_attr_fan2_alarm.dev_attr.attr,
2172	&sensor_dev_attr_fan2_beep.dev_attr.attr,
2173	&sensor_dev_attr_fan2_div.dev_attr.attr,	/* 9 */
2174
2175	&sensor_dev_attr_fan3_input.dev_attr.attr,
2176	&sensor_dev_attr_fan3_min.dev_attr.attr,
2177	&sensor_dev_attr_fan3_alarm.dev_attr.attr,
2178	&sensor_dev_attr_fan3_beep.dev_attr.attr,
2179	&sensor_dev_attr_fan3_div.dev_attr.attr,	/* 14 */
2180
2181	&sensor_dev_attr_fan4_input.dev_attr.attr,	/* 15 */
2182	&sensor_dev_attr_fan4_min.dev_attr.attr,
2183	&sensor_dev_attr_fan4_alarm.dev_attr.attr,
2184	&sensor_dev_attr_fan4_beep.dev_attr.attr,
2185
2186	&sensor_dev_attr_fan5_input.dev_attr.attr,	/* 19 */
2187	&sensor_dev_attr_fan5_min.dev_attr.attr,
2188	&sensor_dev_attr_fan5_alarm.dev_attr.attr,
2189	&sensor_dev_attr_fan5_beep.dev_attr.attr,
2190
2191	&sensor_dev_attr_fan6_input.dev_attr.attr,	/* 23 */
2192	&sensor_dev_attr_fan6_min.dev_attr.attr,
2193	&sensor_dev_attr_fan6_alarm.dev_attr.attr,
2194	&sensor_dev_attr_fan6_beep.dev_attr.attr,
2195	NULL
2196};
2197
2198static const struct attribute_group it87_group_fan = {
2199	.attrs = it87_attributes_fan,
2200	.is_visible = it87_fan_is_visible,
2201};
2202
2203static umode_t it87_pwm_is_visible(struct kobject *kobj,
2204				   struct attribute *attr, int index)
2205{
2206	struct device *dev = container_of(kobj, struct device, kobj);
2207	struct it87_data *data = dev_get_drvdata(dev);
2208	int i = index / 4;	/* pwm index */
2209	int a = index % 4;	/* attribute index */
2210
2211	if (!(data->has_pwm & BIT(i)))
2212		return 0;
2213
2214	/* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2215	if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2216		return attr->mode | S_IWUSR;
2217
2218	/* pwm2_freq is writable if there are two pwm frequency selects */
2219	if (has_pwm_freq2(data) && i == 1 && a == 2)
2220		return attr->mode | S_IWUSR;
2221
2222	return attr->mode;
2223}
2224
2225static struct attribute *it87_attributes_pwm[] = {
2226	&sensor_dev_attr_pwm1_enable.dev_attr.attr,
2227	&sensor_dev_attr_pwm1.dev_attr.attr,
2228	&sensor_dev_attr_pwm1_freq.dev_attr.attr,
2229	&sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2230
2231	&sensor_dev_attr_pwm2_enable.dev_attr.attr,
2232	&sensor_dev_attr_pwm2.dev_attr.attr,
2233	&sensor_dev_attr_pwm2_freq.dev_attr.attr,
2234	&sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2235
2236	&sensor_dev_attr_pwm3_enable.dev_attr.attr,
2237	&sensor_dev_attr_pwm3.dev_attr.attr,
2238	&sensor_dev_attr_pwm3_freq.dev_attr.attr,
2239	&sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2240
2241	&sensor_dev_attr_pwm4_enable.dev_attr.attr,
2242	&sensor_dev_attr_pwm4.dev_attr.attr,
2243	&sensor_dev_attr_pwm4_freq.dev_attr.attr,
2244	&sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2245
2246	&sensor_dev_attr_pwm5_enable.dev_attr.attr,
2247	&sensor_dev_attr_pwm5.dev_attr.attr,
2248	&sensor_dev_attr_pwm5_freq.dev_attr.attr,
2249	&sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2250
2251	&sensor_dev_attr_pwm6_enable.dev_attr.attr,
2252	&sensor_dev_attr_pwm6.dev_attr.attr,
2253	&sensor_dev_attr_pwm6_freq.dev_attr.attr,
2254	&sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2255
2256	NULL
2257};
2258
2259static const struct attribute_group it87_group_pwm = {
2260	.attrs = it87_attributes_pwm,
2261	.is_visible = it87_pwm_is_visible,
2262};
2263
2264static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2265					struct attribute *attr, int index)
2266{
2267	struct device *dev = container_of(kobj, struct device, kobj);
2268	struct it87_data *data = dev_get_drvdata(dev);
2269	int i = index / 11;	/* pwm index */
2270	int a = index % 11;	/* attribute index */
2271
2272	if (index >= 33) {	/* pwm 4..6 */
2273		i = (index - 33) / 6 + 3;
2274		a = (index - 33) % 6 + 4;
2275	}
2276
2277	if (!(data->has_pwm & BIT(i)))
2278		return 0;
2279
2280	if (has_newer_autopwm(data)) {
2281		if (a < 4)	/* no auto point pwm */
2282			return 0;
2283		if (a == 8)	/* no auto_point4 */
2284			return 0;
2285	}
2286	if (has_old_autopwm(data)) {
2287		if (a >= 9)	/* no pwm_auto_start, pwm_auto_slope */
2288			return 0;
2289	}
2290
2291	return attr->mode;
2292}
2293
2294static struct attribute *it87_attributes_auto_pwm[] = {
2295	&sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2296	&sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2297	&sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2298	&sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2299	&sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2300	&sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2301	&sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2302	&sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2303	&sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2304	&sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2305	&sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2306
2307	&sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,	/* 11 */
2308	&sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2309	&sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2310	&sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2311	&sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2312	&sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2313	&sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2314	&sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2315	&sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2316	&sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2317	&sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2318
2319	&sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,	/* 22 */
2320	&sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2321	&sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2322	&sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2323	&sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2324	&sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2325	&sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2326	&sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2327	&sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2328	&sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2329	&sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2330
2331	&sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,	/* 33 */
2332	&sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2333	&sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2334	&sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2335	&sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2336	&sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2337
2338	&sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2339	&sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2340	&sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2341	&sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2342	&sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2343	&sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2344
2345	&sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2346	&sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2347	&sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2348	&sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2349	&sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2350	&sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2351
2352	NULL,
2353};
2354
2355static const struct attribute_group it87_group_auto_pwm = {
2356	.attrs = it87_attributes_auto_pwm,
2357	.is_visible = it87_auto_pwm_is_visible,
2358};
2359
2360/* SuperIO detection - will change isa_address if a chip is found */
2361static int __init it87_find(int sioaddr, unsigned short *address,
2362			    struct it87_sio_data *sio_data)
2363{
2364	int err;
2365	u16 chip_type;
2366	const char *board_vendor, *board_name;
2367	const struct it87_devices *config;
2368
2369	err = superio_enter(sioaddr);
2370	if (err)
2371		return err;
2372
2373	err = -ENODEV;
2374	chip_type = force_id ? force_id : superio_inw(sioaddr, DEVID);
 
 
 
 
 
 
2375
2376	switch (chip_type) {
2377	case IT8705F_DEVID:
2378		sio_data->type = it87;
2379		break;
2380	case IT8712F_DEVID:
2381		sio_data->type = it8712;
2382		break;
2383	case IT8716F_DEVID:
2384	case IT8726F_DEVID:
2385		sio_data->type = it8716;
2386		break;
2387	case IT8718F_DEVID:
2388		sio_data->type = it8718;
2389		break;
2390	case IT8720F_DEVID:
2391		sio_data->type = it8720;
2392		break;
2393	case IT8721F_DEVID:
2394		sio_data->type = it8721;
2395		break;
2396	case IT8728F_DEVID:
2397		sio_data->type = it8728;
2398		break;
2399	case IT8732F_DEVID:
2400		sio_data->type = it8732;
2401		break;
 
 
 
2402	case IT8771E_DEVID:
2403		sio_data->type = it8771;
2404		break;
2405	case IT8772E_DEVID:
2406		sio_data->type = it8772;
2407		break;
2408	case IT8781F_DEVID:
2409		sio_data->type = it8781;
2410		break;
2411	case IT8782F_DEVID:
2412		sio_data->type = it8782;
2413		break;
2414	case IT8783E_DEVID:
2415		sio_data->type = it8783;
2416		break;
2417	case IT8786E_DEVID:
2418		sio_data->type = it8786;
2419		break;
2420	case IT8790E_DEVID:
2421		sio_data->type = it8790;
2422		break;
2423	case IT8603E_DEVID:
2424	case IT8623E_DEVID:
2425		sio_data->type = it8603;
2426		break;
2427	case IT8620E_DEVID:
2428		sio_data->type = it8620;
2429		break;
 
 
 
2430	case IT8628E_DEVID:
2431		sio_data->type = it8628;
2432		break;
2433	case 0xffff:	/* No device at all */
2434		goto exit;
2435	default:
2436		pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
2437		goto exit;
2438	}
2439
2440	superio_select(sioaddr, PME);
2441	if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
2442		pr_info("Device not activated, skipping\n");
2443		goto exit;
2444	}
2445
2446	*address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
2447	if (*address == 0) {
2448		pr_info("Base address not set, skipping\n");
2449		goto exit;
2450	}
2451
2452	err = 0;
 
2453	sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
2454	pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2455		it87_devices[sio_data->type].suffix,
2456		*address, sio_data->revision);
2457
2458	config = &it87_devices[sio_data->type];
2459
2460	/* in7 (VSB or VCCH5V) is always internal on some chips */
2461	if (has_in7_internal(config))
2462		sio_data->internal |= BIT(1);
2463
2464	/* in8 (Vbat) is always internal */
2465	sio_data->internal |= BIT(2);
2466
2467	/* in9 (AVCC3), always internal if supported */
2468	if (has_avcc3(config))
2469		sio_data->internal |= BIT(3); /* in9 is AVCC */
2470	else
2471		sio_data->skip_in |= BIT(9);
2472
2473	if (!has_six_pwm(config))
2474		sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
 
 
2475
2476	if (!has_vid(config))
2477		sio_data->skip_vid = 1;
2478
2479	/* Read GPIO config and VID value from LDN 7 (GPIO) */
2480	if (sio_data->type == it87) {
2481		/* The IT8705F has a different LD number for GPIO */
2482		superio_select(sioaddr, 5);
2483		sio_data->beep_pin = superio_inb(sioaddr,
2484						 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2485	} else if (sio_data->type == it8783) {
2486		int reg25, reg27, reg2a, reg2c, regef;
2487
2488		superio_select(sioaddr, GPIO);
2489
2490		reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2491		reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2492		reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2493		reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2494		regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
2495
2496		/* Check if fan3 is there or not */
2497		if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2498			sio_data->skip_fan |= BIT(2);
2499		if ((reg25 & BIT(4)) ||
2500		    (!(reg2a & BIT(1)) && (regef & BIT(0))))
2501			sio_data->skip_pwm |= BIT(2);
2502
2503		/* Check if fan2 is there or not */
2504		if (reg27 & BIT(7))
2505			sio_data->skip_fan |= BIT(1);
2506		if (reg27 & BIT(3))
2507			sio_data->skip_pwm |= BIT(1);
2508
2509		/* VIN5 */
2510		if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2511			sio_data->skip_in |= BIT(5); /* No VIN5 */
2512
2513		/* VIN6 */
2514		if (reg27 & BIT(1))
2515			sio_data->skip_in |= BIT(6); /* No VIN6 */
2516
2517		/*
2518		 * VIN7
2519		 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2520		 */
2521		if (reg27 & BIT(2)) {
2522			/*
2523			 * The data sheet is a bit unclear regarding the
2524			 * internal voltage divider for VCCH5V. It says
2525			 * "This bit enables and switches VIN7 (pin 91) to the
2526			 * internal voltage divider for VCCH5V".
2527			 * This is different to other chips, where the internal
2528			 * voltage divider would connect VIN7 to an internal
2529			 * voltage source. Maybe that is the case here as well.
2530			 *
2531			 * Since we don't know for sure, re-route it if that is
2532			 * not the case, and ask the user to report if the
2533			 * resulting voltage is sane.
2534			 */
2535			if (!(reg2c & BIT(1))) {
2536				reg2c |= BIT(1);
2537				superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2538					     reg2c);
 
2539				pr_notice("Routing internal VCCH5V to in7.\n");
2540			}
2541			pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
2542			pr_notice("Please report if it displays a reasonable voltage.\n");
2543		}
2544
2545		if (reg2c & BIT(0))
2546			sio_data->internal |= BIT(0);
2547		if (reg2c & BIT(1))
2548			sio_data->internal |= BIT(1);
2549
2550		sio_data->beep_pin = superio_inb(sioaddr,
2551						 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2552	} else if (sio_data->type == it8603) {
2553		int reg27, reg29;
2554
2555		superio_select(sioaddr, GPIO);
2556
2557		reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2558
2559		/* Check if fan3 is there or not */
2560		if (reg27 & BIT(6))
2561			sio_data->skip_pwm |= BIT(2);
2562		if (reg27 & BIT(7))
2563			sio_data->skip_fan |= BIT(2);
2564
2565		/* Check if fan2 is there or not */
2566		reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2567		if (reg29 & BIT(1))
2568			sio_data->skip_pwm |= BIT(1);
2569		if (reg29 & BIT(2))
2570			sio_data->skip_fan |= BIT(1);
2571
2572		sio_data->skip_in |= BIT(5); /* No VIN5 */
2573		sio_data->skip_in |= BIT(6); /* No VIN6 */
2574
2575		sio_data->beep_pin = superio_inb(sioaddr,
2576						 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2577	} else if (sio_data->type == it8620 || sio_data->type == it8628) {
2578		int reg;
2579
2580		superio_select(sioaddr, GPIO);
2581
2582		/* Check for pwm5 */
2583		reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2584		if (reg & BIT(6))
2585			sio_data->skip_pwm |= BIT(4);
2586
2587		/* Check for fan4, fan5 */
2588		reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
2589		if (!(reg & BIT(5)))
2590			sio_data->skip_fan |= BIT(3);
2591		if (!(reg & BIT(4)))
2592			sio_data->skip_fan |= BIT(4);
2593
2594		/* Check for pwm3, fan3 */
2595		reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2596		if (reg & BIT(6))
2597			sio_data->skip_pwm |= BIT(2);
2598		if (reg & BIT(7))
2599			sio_data->skip_fan |= BIT(2);
2600
2601		/* Check for pwm4 */
2602		reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
2603		if (!(reg & BIT(2)))
2604			sio_data->skip_pwm |= BIT(3);
2605
2606		/* Check for pwm2, fan2 */
2607		reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2608		if (reg & BIT(1))
2609			sio_data->skip_pwm |= BIT(1);
2610		if (reg & BIT(2))
2611			sio_data->skip_fan |= BIT(1);
2612		/* Check for pwm6, fan6 */
2613		if (!(reg & BIT(7))) {
2614			sio_data->skip_pwm |= BIT(5);
2615			sio_data->skip_fan |= BIT(5);
2616		}
2617
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2618		sio_data->beep_pin = superio_inb(sioaddr,
2619						 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2620	} else {
2621		int reg;
2622		bool uart6;
2623
2624		superio_select(sioaddr, GPIO);
2625
2626		/* Check for fan4, fan5 */
2627		if (has_five_fans(config)) {
2628			reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
2629			switch (sio_data->type) {
2630			case it8718:
2631				if (reg & BIT(5))
2632					sio_data->skip_fan |= BIT(3);
2633				if (reg & BIT(4))
2634					sio_data->skip_fan |= BIT(4);
2635				break;
2636			case it8720:
2637			case it8721:
2638			case it8728:
2639				if (!(reg & BIT(5)))
2640					sio_data->skip_fan |= BIT(3);
2641				if (!(reg & BIT(4)))
2642					sio_data->skip_fan |= BIT(4);
2643				break;
2644			default:
2645				break;
2646			}
2647		}
2648
2649		reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2650		if (!sio_data->skip_vid) {
2651			/* We need at least 4 VID pins */
2652			if (reg & 0x0f) {
2653				pr_info("VID is disabled (pins used for GPIO)\n");
2654				sio_data->skip_vid = 1;
2655			}
2656		}
2657
2658		/* Check if fan3 is there or not */
2659		if (reg & BIT(6))
2660			sio_data->skip_pwm |= BIT(2);
2661		if (reg & BIT(7))
2662			sio_data->skip_fan |= BIT(2);
2663
2664		/* Check if fan2 is there or not */
2665		reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2666		if (reg & BIT(1))
2667			sio_data->skip_pwm |= BIT(1);
2668		if (reg & BIT(2))
2669			sio_data->skip_fan |= BIT(1);
2670
2671		if ((sio_data->type == it8718 || sio_data->type == it8720) &&
2672		    !(sio_data->skip_vid))
2673			sio_data->vid_value = superio_inb(sioaddr,
2674							  IT87_SIO_VID_REG);
2675
2676		reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2677
2678		uart6 = sio_data->type == it8782 && (reg & BIT(2));
2679
2680		/*
2681		 * The IT8720F has no VIN7 pin, so VCCH should always be
2682		 * routed internally to VIN7 with an internal divider.
2683		 * Curiously, there still is a configuration bit to control
2684		 * this, which means it can be set incorrectly. And even
2685		 * more curiously, many boards out there are improperly
2686		 * configured, even though the IT8720F datasheet claims
2687		 * that the internal routing of VCCH to VIN7 is the default
2688		 * setting. So we force the internal routing in this case.
2689		 *
2690		 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
2691		 * If UART6 is enabled, re-route VIN7 to the internal divider
2692		 * if that is not already the case.
2693		 */
2694		if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
2695			reg |= BIT(1);
2696			superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
2697			pr_notice("Routing internal VCCH to in7\n");
 
2698		}
2699		if (reg & BIT(0))
2700			sio_data->internal |= BIT(0);
2701		if (reg & BIT(1))
2702			sio_data->internal |= BIT(1);
2703
2704		/*
2705		 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
2706		 * While VIN7 can be routed to the internal voltage divider,
2707		 * VIN5 and VIN6 are not available if UART6 is enabled.
2708		 *
2709		 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
2710		 * is the temperature source. Since we can not read the
2711		 * temperature source here, skip_temp is preliminary.
2712		 */
2713		if (uart6) {
2714			sio_data->skip_in |= BIT(5) | BIT(6);
2715			sio_data->skip_temp |= BIT(2);
2716		}
2717
2718		sio_data->beep_pin = superio_inb(sioaddr,
2719						 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2720	}
2721	if (sio_data->beep_pin)
2722		pr_info("Beeping is supported\n");
2723
2724	/* Disable specific features based on DMI strings */
2725	board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
2726	board_name = dmi_get_system_info(DMI_BOARD_NAME);
2727	if (board_vendor && board_name) {
2728		if (strcmp(board_vendor, "nVIDIA") == 0 &&
2729		    strcmp(board_name, "FN68PT") == 0) {
2730			/*
2731			 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
2732			 * connected to a fan, but to something else. One user
2733			 * has reported instant system power-off when changing
2734			 * the PWM2 duty cycle, so we disable it.
2735			 * I use the board name string as the trigger in case
2736			 * the same board is ever used in other systems.
2737			 */
2738			pr_info("Disabling pwm2 due to hardware constraints\n");
2739			sio_data->skip_pwm = BIT(1);
2740		}
2741	}
2742
2743exit:
2744	superio_exit(sioaddr);
2745	return err;
2746}
2747
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2748/* Called when we have found a new IT87. */
2749static void it87_init_device(struct platform_device *pdev)
2750{
2751	struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
2752	struct it87_data *data = platform_get_drvdata(pdev);
2753	int tmp, i;
2754	u8 mask;
2755
2756	/*
2757	 * For each PWM channel:
2758	 * - If it is in automatic mode, setting to manual mode should set
2759	 *   the fan to full speed by default.
2760	 * - If it is in manual mode, we need a mapping to temperature
2761	 *   channels to use when later setting to automatic mode later.
2762	 *   Use a 1:1 mapping by default (we are clueless.)
2763	 * In both cases, the value can (and should) be changed by the user
2764	 * prior to switching to a different mode.
2765	 * Note that this is no longer needed for the IT8721F and later, as
2766	 * these have separate registers for the temperature mapping and the
2767	 * manual duty cycle.
2768	 */
2769	for (i = 0; i < NUM_AUTO_PWM; i++) {
2770		data->pwm_temp_map[i] = i;
2771		data->pwm_duty[i] = 0x7f;	/* Full speed */
2772		data->auto_pwm[i][3] = 0x7f;	/* Full speed, hard-coded */
2773	}
2774
2775	/*
2776	 * Some chips seem to have default value 0xff for all limit
2777	 * registers. For low voltage limits it makes no sense and triggers
2778	 * alarms, so change to 0 instead. For high temperature limits, it
2779	 * means -1 degree C, which surprisingly doesn't trigger an alarm,
2780	 * but is still confusing, so change to 127 degrees C.
2781	 */
2782	for (i = 0; i < NUM_VIN_LIMIT; i++) {
2783		tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
2784		if (tmp == 0xff)
2785			it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
2786	}
2787	for (i = 0; i < NUM_TEMP_LIMIT; i++) {
2788		tmp = it87_read_value(data, IT87_REG_TEMP_HIGH(i));
2789		if (tmp == 0xff)
2790			it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
2791	}
2792
2793	/*
2794	 * Temperature channels are not forcibly enabled, as they can be
2795	 * set to two different sensor types and we can't guess which one
2796	 * is correct for a given system. These channels can be enabled at
2797	 * run-time through the temp{1-3}_type sysfs accessors if needed.
2798	 */
2799
2800	/* Check if voltage monitors are reset manually or by some reason */
2801	tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
2802	if ((tmp & 0xff) == 0) {
2803		/* Enable all voltage monitors */
2804		it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
2805	}
2806
2807	/* Check if tachometers are reset manually or by some reason */
2808	mask = 0x70 & ~(sio_data->skip_fan << 4);
2809	data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
2810	if ((data->fan_main_ctrl & mask) == 0) {
2811		/* Enable all fan tachometers */
2812		data->fan_main_ctrl |= mask;
2813		it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
2814				 data->fan_main_ctrl);
2815	}
2816	data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
2817
2818	tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
2819
2820	/* Set tachometers to 16-bit mode if needed */
2821	if (has_fan16_config(data)) {
2822		if (~tmp & 0x07 & data->has_fan) {
2823			dev_dbg(&pdev->dev,
2824				"Setting fan1-3 to 16-bit mode\n");
2825			it87_write_value(data, IT87_REG_FAN_16BIT,
2826					 tmp | 0x07);
2827		}
2828	}
2829
2830	/* Check for additional fans */
2831	if (has_five_fans(data)) {
 
 
2832		if (tmp & BIT(4))
2833			data->has_fan |= BIT(3); /* fan4 enabled */
2834		if (tmp & BIT(5))
2835			data->has_fan |= BIT(4); /* fan5 enabled */
2836		if (has_six_fans(data) && (tmp & BIT(2)))
2837			data->has_fan |= BIT(5); /* fan6 enabled */
2838	}
2839
2840	/* Fan input pins may be used for alternative functions */
2841	data->has_fan &= ~sio_data->skip_fan;
2842
2843	/* Check if pwm5, pwm6 are enabled */
2844	if (has_six_pwm(data)) {
2845		/* The following code may be IT8620E specific */
2846		tmp = it87_read_value(data, IT87_REG_FAN_DIV);
2847		if ((tmp & 0xc0) == 0xc0)
2848			sio_data->skip_pwm |= BIT(4);
2849		if (!(tmp & BIT(3)))
2850			sio_data->skip_pwm |= BIT(5);
2851	}
2852
2853	/* Start monitoring */
2854	it87_write_value(data, IT87_REG_CONFIG,
2855			 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
2856			 | (update_vbat ? 0x41 : 0x01));
2857}
2858
2859/* Return 1 if and only if the PWM interface is safe to use */
2860static int it87_check_pwm(struct device *dev)
2861{
2862	struct it87_data *data = dev_get_drvdata(dev);
2863	/*
2864	 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
2865	 * and polarity set to active low is sign that this is the case so we
2866	 * disable pwm control to protect the user.
2867	 */
2868	int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
2869
2870	if ((tmp & 0x87) == 0) {
2871		if (fix_pwm_polarity) {
2872			/*
2873			 * The user asks us to attempt a chip reconfiguration.
2874			 * This means switching to active high polarity and
2875			 * inverting all fan speed values.
2876			 */
2877			int i;
2878			u8 pwm[3];
2879
2880			for (i = 0; i < ARRAY_SIZE(pwm); i++)
2881				pwm[i] = it87_read_value(data,
2882							 IT87_REG_PWM[i]);
2883
2884			/*
2885			 * If any fan is in automatic pwm mode, the polarity
2886			 * might be correct, as suspicious as it seems, so we
2887			 * better don't change anything (but still disable the
2888			 * PWM interface).
2889			 */
2890			if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
2891				dev_info(dev,
2892					 "Reconfiguring PWM to active high polarity\n");
2893				it87_write_value(data, IT87_REG_FAN_CTL,
2894						 tmp | 0x87);
2895				for (i = 0; i < 3; i++)
2896					it87_write_value(data,
2897							 IT87_REG_PWM[i],
2898							 0x7f & ~pwm[i]);
2899				return 1;
2900			}
2901
2902			dev_info(dev,
2903				 "PWM configuration is too broken to be fixed\n");
2904		}
2905
2906		dev_info(dev,
2907			 "Detected broken BIOS defaults, disabling PWM interface\n");
2908		return 0;
2909	} else if (fix_pwm_polarity) {
2910		dev_info(dev,
2911			 "PWM configuration looks sane, won't touch\n");
2912	}
2913
2914	return 1;
2915}
2916
2917static int it87_probe(struct platform_device *pdev)
2918{
2919	struct it87_data *data;
2920	struct resource *res;
2921	struct device *dev = &pdev->dev;
2922	struct it87_sio_data *sio_data = dev_get_platdata(dev);
2923	int enable_pwm_interface;
2924	struct device *hwmon_dev;
2925
2926	res = platform_get_resource(pdev, IORESOURCE_IO, 0);
2927	if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
2928				 DRVNAME)) {
2929		dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
2930			(unsigned long)res->start,
2931			(unsigned long)(res->start + IT87_EC_EXTENT - 1));
2932		return -EBUSY;
2933	}
2934
2935	data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
2936	if (!data)
2937		return -ENOMEM;
2938
2939	data->addr = res->start;
 
2940	data->type = sio_data->type;
2941	data->features = it87_devices[sio_data->type].features;
2942	data->peci_mask = it87_devices[sio_data->type].peci_mask;
2943	data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
2944	/*
2945	 * IT8705F Datasheet 0.4.1, 3h == Version G.
2946	 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
2947	 * These are the first revisions with 16-bit tachometer support.
2948	 */
2949	switch (data->type) {
2950	case it87:
2951		if (sio_data->revision >= 0x03) {
2952			data->features &= ~FEAT_OLD_AUTOPWM;
2953			data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
2954		}
2955		break;
2956	case it8712:
2957		if (sio_data->revision >= 0x08) {
2958			data->features &= ~FEAT_OLD_AUTOPWM;
2959			data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
2960					  FEAT_FIVE_FANS;
2961		}
2962		break;
2963	default:
2964		break;
2965	}
2966
2967	/* Now, we do the remaining detection. */
2968	if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
2969	    it87_read_value(data, IT87_REG_CHIPID) != 0x90)
2970		return -ENODEV;
2971
2972	platform_set_drvdata(pdev, data);
2973
2974	mutex_init(&data->update_lock);
2975
2976	/* Check PWM configuration */
2977	enable_pwm_interface = it87_check_pwm(dev);
 
 
 
2978
2979	/* Starting with IT8721F, we handle scaling of internal voltages */
2980	if (has_12mv_adc(data)) {
2981		if (sio_data->internal & BIT(0))
2982			data->in_scaled |= BIT(3);	/* in3 is AVCC */
2983		if (sio_data->internal & BIT(1))
2984			data->in_scaled |= BIT(7);	/* in7 is VSB */
2985		if (sio_data->internal & BIT(2))
2986			data->in_scaled |= BIT(8);	/* in8 is Vbat */
2987		if (sio_data->internal & BIT(3))
2988			data->in_scaled |= BIT(9);	/* in9 is AVCC */
2989	} else if (sio_data->type == it8781 || sio_data->type == it8782 ||
2990		   sio_data->type == it8783) {
2991		if (sio_data->internal & BIT(0))
2992			data->in_scaled |= BIT(3);	/* in3 is VCC5V */
2993		if (sio_data->internal & BIT(1))
2994			data->in_scaled |= BIT(7);	/* in7 is VCCH5V */
2995	}
2996
2997	data->has_temp = 0x07;
2998	if (sio_data->skip_temp & BIT(2)) {
2999		if (sio_data->type == it8782 &&
3000		    !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3001			data->has_temp &= ~BIT(2);
3002	}
3003
3004	data->in_internal = sio_data->internal;
 
3005	data->has_in = 0x3ff & ~sio_data->skip_in;
3006
3007	if (has_six_temp(data)) {
3008		u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3009
3010		/* Check for additional temperature sensors */
3011		if ((reg & 0x03) >= 0x02)
3012			data->has_temp |= BIT(3);
3013		if (((reg >> 2) & 0x03) >= 0x02)
3014			data->has_temp |= BIT(4);
3015		if (((reg >> 4) & 0x03) >= 0x02)
3016			data->has_temp |= BIT(5);
3017
3018		/* Check for additional voltage sensors */
3019		if ((reg & 0x03) == 0x01)
3020			data->has_in |= BIT(10);
3021		if (((reg >> 2) & 0x03) == 0x01)
3022			data->has_in |= BIT(11);
3023		if (((reg >> 4) & 0x03) == 0x01)
3024			data->has_in |= BIT(12);
3025	}
3026
3027	data->has_beep = !!sio_data->beep_pin;
3028
3029	/* Initialize the IT87 chip */
3030	it87_init_device(pdev);
3031
3032	if (!sio_data->skip_vid) {
3033		data->has_vid = true;
3034		data->vrm = vid_which_vrm();
3035		/* VID reading from Super-I/O config space if available */
3036		data->vid = sio_data->vid_value;
3037	}
3038
3039	/* Prepare for sysfs hooks */
3040	data->groups[0] = &it87_group;
3041	data->groups[1] = &it87_group_in;
3042	data->groups[2] = &it87_group_temp;
3043	data->groups[3] = &it87_group_fan;
3044
3045	if (enable_pwm_interface) {
3046		data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
3047		data->has_pwm &= ~sio_data->skip_pwm;
3048
3049		data->groups[4] = &it87_group_pwm;
3050		if (has_old_autopwm(data) || has_newer_autopwm(data))
3051			data->groups[5] = &it87_group_auto_pwm;
3052	}
3053
3054	hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3055					it87_devices[sio_data->type].name,
3056					data, data->groups);
3057	return PTR_ERR_OR_ZERO(hwmon_dev);
3058}
3059
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
3060static struct platform_driver it87_driver = {
3061	.driver = {
3062		.name	= DRVNAME,
 
3063	},
3064	.probe	= it87_probe,
3065};
3066
3067static int __init it87_device_add(int index, unsigned short address,
3068				  const struct it87_sio_data *sio_data)
3069{
3070	struct platform_device *pdev;
3071	struct resource res = {
3072		.start	= address + IT87_EC_OFFSET,
3073		.end	= address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
3074		.name	= DRVNAME,
3075		.flags	= IORESOURCE_IO,
3076	};
3077	int err;
3078
3079	err = acpi_check_resource_conflict(&res);
3080	if (err)
3081		return err;
 
 
3082
3083	pdev = platform_device_alloc(DRVNAME, address);
3084	if (!pdev)
3085		return -ENOMEM;
3086
3087	err = platform_device_add_resources(pdev, &res, 1);
3088	if (err) {
3089		pr_err("Device resource addition failed (%d)\n", err);
3090		goto exit_device_put;
3091	}
3092
3093	err = platform_device_add_data(pdev, sio_data,
3094				       sizeof(struct it87_sio_data));
3095	if (err) {
3096		pr_err("Platform data allocation failed\n");
3097		goto exit_device_put;
3098	}
3099
3100	err = platform_device_add(pdev);
3101	if (err) {
3102		pr_err("Device addition failed (%d)\n", err);
3103		goto exit_device_put;
3104	}
3105
3106	it87_pdev[index] = pdev;
3107	return 0;
3108
3109exit_device_put:
3110	platform_device_put(pdev);
3111	return err;
3112}
3113
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
3114static int __init sm_it87_init(void)
3115{
3116	int sioaddr[2] = { REG_2E, REG_4E };
3117	struct it87_sio_data sio_data;
3118	unsigned short isa_address;
3119	bool found = false;
3120	int i, err;
3121
3122	err = platform_driver_register(&it87_driver);
3123	if (err)
3124		return err;
3125
 
 
3126	for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3127		memset(&sio_data, 0, sizeof(struct it87_sio_data));
3128		isa_address = 0;
3129		err = it87_find(sioaddr[i], &isa_address, &sio_data);
3130		if (err || isa_address == 0)
3131			continue;
 
 
 
 
 
 
3132
3133		err = it87_device_add(i, isa_address, &sio_data);
3134		if (err)
3135			goto exit_dev_unregister;
 
3136		found = true;
 
 
 
 
 
 
 
3137	}
3138
3139	if (!found) {
3140		err = -ENODEV;
3141		goto exit_unregister;
3142	}
3143	return 0;
3144
3145exit_dev_unregister:
3146	/* NULL check handled by platform_device_unregister */
3147	platform_device_unregister(it87_pdev[0]);
3148exit_unregister:
3149	platform_driver_unregister(&it87_driver);
3150	return err;
3151}
3152
3153static void __exit sm_it87_exit(void)
3154{
3155	/* NULL check handled by platform_device_unregister */
3156	platform_device_unregister(it87_pdev[1]);
3157	platform_device_unregister(it87_pdev[0]);
3158	platform_driver_unregister(&it87_driver);
3159}
3160
3161MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
3162MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
3163module_param(update_vbat, bool, 0);
3164MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
3165module_param(fix_pwm_polarity, bool, 0);
3166MODULE_PARM_DESC(fix_pwm_polarity,
3167		 "Force PWM polarity to active high (DANGEROUS)");
3168MODULE_LICENSE("GPL");
3169
3170module_init(sm_it87_init);
3171module_exit(sm_it87_exit);